From c1ec62f1fb21fd7dd4f83fb6724d9b210b2e59f2 Mon Sep 17 00:00:00 2001 From: Bernd Edlinger Date: Fri, 5 Oct 2018 19:19:42 +0000 Subject: string_merge1.adb: Fix test expectations. 2018-10-05 Bernd Edlinger * gnat.dg/string_merge1.adb: Fix test expectations. * gnat.dg/string_merge2.adb: Likewise. From-SVN: r264888 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gnat.dg/string_merge1.adb | 2 -- gcc/testsuite/gnat.dg/string_merge2.adb | 2 -- 3 files changed, 5 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 37a035a..818f6ea 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-10-05 Bernd Edlinger + + * gnat.dg/string_merge1.adb: Fix test expectations. + * gnat.dg/string_merge2.adb: Likewise. + 2018-10-05 David Malcolm PR c++/56856 diff --git a/gcc/testsuite/gnat.dg/string_merge1.adb b/gcc/testsuite/gnat.dg/string_merge1.adb index f67c7c1..52b9f3c 100644 --- a/gcc/testsuite/gnat.dg/string_merge1.adb +++ b/gcc/testsuite/gnat.dg/string_merge1.adb @@ -15,5 +15,3 @@ end; -- .string "ABCD" -- { dg-final { scan-assembler-times "\\.rodata\\.str" 1 } } --- { dg-final { scan-assembler-times "\\.string" 1 } } --- { dg-final { scan-assembler-times "\"ABCD\"" 1 } } diff --git a/gcc/testsuite/gnat.dg/string_merge2.adb b/gcc/testsuite/gnat.dg/string_merge2.adb index bbec005..a2d37bd 100644 --- a/gcc/testsuite/gnat.dg/string_merge2.adb +++ b/gcc/testsuite/gnat.dg/string_merge2.adb @@ -15,5 +15,3 @@ end; -- .string "ABCD" -- { dg-final { scan-assembler-times "\\.rodata\\.str" 1 } } --- { dg-final { scan-assembler-times "\\.string" 1 } } --- { dg-final { scan-assembler-times "\"ABCD\"" 1 } } -- cgit v1.1 From a3a81f292256069546bc2b0b9ebddb229af117b1 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Fri, 5 Oct 2018 21:40:36 +0200 Subject: rs6000: Some mfcr pattern simplification * config/rs6000/rs6000.md (unnamed mfcr scc_comparison_operator patterns): Merge SI and DI patterns to a GPR pattern. (unnamed define_insn and define_split for record form of that): Merge to a single define_insn_and_split pattern. From-SVN: r264889 --- gcc/ChangeLog | 7 +++++++ gcc/config/rs6000/rs6000.md | 43 ++++++++++--------------------------------- 2 files changed, 17 insertions(+), 33 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 53c9c89..8d754af 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-10-05 Segher Boessenkool + + * config/rs6000/rs6000.md (unnamed mfcr scc_comparison_operator + patterns): Merge SI and DI patterns to a GPR pattern. + (unnamed define_insn and define_split for record form of that): Merge + to a single define_insn_and_split pattern. + 2018-10-05 David Malcolm PR c++/56856 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5db3e57..0e7cf35 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -11765,10 +11765,10 @@ ;; cases the insns below which don't use an intermediate CR field will ;; be used instead. (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (match_operator:SI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand" "y") - (const_int 0)]))] + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (match_operator:GPR 1 "scc_comparison_operator" + [(match_operand 2 "cc_reg_operand" "y") + (const_int 0)]))] "" "mfcr %0%Q2\;rlwinm %0,%0,%J1,1" [(set (attr "type") @@ -11778,21 +11778,7 @@ (const_string "mfcr"))) (set_attr "length" "8")]) -(define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (match_operator:DI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand" "y") - (const_int 0)]))] - "TARGET_POWERPC64" - "mfcr %0%Q2\;rlwinm %0,%0,%J1,1" - [(set (attr "type") - (cond [(match_test "TARGET_MFCRF") - (const_string "mfcrf") - ] - (const_string "mfcr"))) - (set_attr "length" "8")]) - -(define_insn "" +(define_insn_and_split "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (match_operator:SI 1 "scc_comparison_operator" [(match_operand 2 "cc_reg_operand" "y,y") @@ -11804,25 +11790,16 @@ "@ mfcr %3%Q2\;rlwinm. %3,%3,%J1,1 #" - [(set_attr "type" "shift") - (set_attr "dot" "yes") - (set_attr "length" "8,16")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand") - (compare:CC (match_operator:SI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand") - (const_int 0)]) - (const_int 0))) - (set (match_operand:SI 3 "gpc_reg_operand") - (match_op_dup 1 [(match_dup 2) (const_int 0)]))] - "TARGET_32BIT && reload_completed" + "&& reload_completed" [(set (match_dup 3) (match_op_dup 1 [(match_dup 2) (const_int 0)])) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] - "") + "" + [(set_attr "type" "shift") + (set_attr "dot" "yes") + (set_attr "length" "8,16")]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") -- cgit v1.1 From 1fcbfb00fc675ee33b90ae486f3acb5916c93400 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 5 Oct 2018 20:18:21 +0000 Subject: RISC-V: Fix -fsignaling-nans for glibc testsuite. gcc/ * config/riscv/riscv.md (f_quiet4): Add define_expand. Add ! HONOR_SNANS check to current pattern. Add new pattern using HONOR_SNANS that emits one extra instruction. Co-Authored-By: Jim Wilson From-SVN: r264892 --- gcc/ChangeLog | 7 +++++++ gcc/config/riscv/riscv.md | 34 ++++++++++++++++++++++++++++------ 2 files changed, 35 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8d754af..6d81f73 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-10-05 Andrew Waterman + Jim Wilson + + * config/riscv/riscv.md (f_quiet4): + Add define_expand. Add ! HONOR_SNANS check to current pattern. Add + new pattern using HONOR_SNANS that emits one extra instruction. + 2018-10-05 Segher Boessenkool * config/rs6000/rs6000.md (unnamed mfcr scc_comparison_operator diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 4162dc5..b6c2023 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1957,19 +1957,41 @@ [(set_attr "type" "fcmp") (set_attr "mode" "")]) -(define_insn "f_quiet4" - [(set (match_operand:X 0 "register_operand" "=r") +(define_expand "f_quiet4" + [(parallel [(set (match_operand:X 0 "register_operand") + (unspec:X + [(match_operand:ANYF 1 "register_operand") + (match_operand:ANYF 2 "register_operand")] + QUIET_COMPARISON)) + (clobber (match_scratch:X 3))])] + "TARGET_HARD_FLOAT") + +(define_insn "*f_quiet4_default" + [(set (match_operand:X 0 "register_operand" "=r") (unspec:X - [(match_operand:ANYF 1 "register_operand" " f") - (match_operand:ANYF 2 "register_operand" " f")] - QUIET_COMPARISON)) + [(match_operand:ANYF 1 "register_operand" " f") + (match_operand:ANYF 2 "register_operand" " f")] + QUIET_COMPARISON)) (clobber (match_scratch:X 3 "=&r"))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && ! HONOR_SNANS (mode)" "frflags\t%3\n\tf.\t%0,%1,%2\n\tfsflags %3" [(set_attr "type" "fcmp") (set_attr "mode" "") (set (attr "length") (const_int 12))]) +(define_insn "*f_quiet4_snan" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X + [(match_operand:ANYF 1 "register_operand" " f") + (match_operand:ANYF 2 "register_operand" " f")] + QUIET_COMPARISON)) + (clobber (match_scratch:X 3 "=&r"))] + "TARGET_HARD_FLOAT && HONOR_SNANS (mode)" + "frflags\t%3\n\tf.\t%0,%1,%2\n\tfsflags %3\n\tfeq.\tzero,%1,%2" + [(set_attr "type" "fcmp") + (set_attr "mode" "") + (set (attr "length") (const_int 16))]) + (define_insn "*seq_zero_" [(set (match_operand:GPR 0 "register_operand" "=r") (eq:GPR (match_operand:X 1 "register_operand" " r") -- cgit v1.1 From fb6f9bbc754df7f410d0ae00e0cd8dc839203dc4 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sat, 6 Oct 2018 00:17:07 +0000 Subject: Daily bump. From-SVN: r264896 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 3faa601..3a02e74 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20181005 +20181006 -- cgit v1.1 From a141f2d86293dc202e35bd4d7f832756e1792cdf Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Sat, 6 Oct 2018 02:12:30 +0000 Subject: re PR rtl-optimization/86939 (IRA incorrectly creates an interference between a pseudo register and a hard register) gcc/ PR rtl-optimization/86939 PR rtl-optimization/87479 * ira.h (non_conflicting_reg_copy_p): New prototype. * ira-lives.c (ignore_reg_for_conflicts): New static variable. (make_hard_regno_dead): Don't add conflicts for register ignore_reg_for_conflicts. (make_object_dead): Likewise. (non_conflicting_reg_copy_p): New function. (process_bb_node_lives): Set ignore_reg_for_conflicts for copies. Remove special conflict handling of REAL_PIC_OFFSET_TABLE_REGNUM. * lra-lives.c (ignore_reg_for_conflicts): New static variable. (make_hard_regno_dead): Don't add conflicts for register ignore_reg_for_conflicts. Remove special conflict handling of REAL_PIC_OFFSET_TABLE_REGNUM. Remove now unused argument check_pic_pseudo_p and update callers. (mark_pseudo_dead): Don't add conflicts for register ignore_reg_for_conflicts. (process_bb_lives): Set ignore_reg_for_conflicts for copies. gcc/testsuite/ PR rtl-optimization/86939 PR rtl-optimization/87479 * gcc.target/powerpc/pr86939.c: New test. * gcc/testsuite/gcc.target/i386/pr49095.c: Fix expected results. From-SVN: r264897 --- gcc/ChangeLog | 21 +++++++ gcc/ira-lives.c | 97 +++++++++++++++++++++--------- gcc/ira.h | 3 + gcc/lra-lives.c | 64 ++++++++++++++------ gcc/testsuite/ChangeLog | 7 +++ gcc/testsuite/gcc.target/i386/pr49095.c | 3 +- gcc/testsuite/gcc.target/powerpc/pr86939.c | 12 ++++ 7 files changed, 160 insertions(+), 47 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr86939.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6d81f73..73f26a9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,24 @@ +2018-10-05 Peter Bergner + + PR rtl-optimization/86939 + PR rtl-optimization/87479 + * ira.h (non_conflicting_reg_copy_p): New prototype. + * ira-lives.c (ignore_reg_for_conflicts): New static variable. + (make_hard_regno_dead): Don't add conflicts for register + ignore_reg_for_conflicts. + (make_object_dead): Likewise. + (non_conflicting_reg_copy_p): New function. + (process_bb_node_lives): Set ignore_reg_for_conflicts for copies. + Remove special conflict handling of REAL_PIC_OFFSET_TABLE_REGNUM. + * lra-lives.c (ignore_reg_for_conflicts): New static variable. + (make_hard_regno_dead): Don't add conflicts for register + ignore_reg_for_conflicts. Remove special conflict handling of + REAL_PIC_OFFSET_TABLE_REGNUM. Remove now unused argument + check_pic_pseudo_p and update callers. + (mark_pseudo_dead): Don't add conflicts for register + ignore_reg_for_conflicts. + (process_bb_lives): Set ignore_reg_for_conflicts for copies. + 2018-10-05 Andrew Waterman Jim Wilson diff --git a/gcc/ira-lives.c b/gcc/ira-lives.c index f1a7d27..dd8b334 100644 --- a/gcc/ira-lives.c +++ b/gcc/ira-lives.c @@ -84,6 +84,10 @@ static int *allocno_saved_at_call; supplemental to recog_data. */ static alternative_mask preferred_alternatives; +/* If non-NULL, the source operand of a register to register copy for which + we should not add a conflict with the copy's destination operand. */ +static rtx ignore_reg_for_conflicts; + /* Record hard register REGNO as now being live. */ static void make_hard_regno_live (int regno) @@ -101,6 +105,11 @@ make_hard_regno_dead (int regno) { ira_object_t obj = ira_object_id_map[i]; + if (ignore_reg_for_conflicts != NULL_RTX + && REGNO (ignore_reg_for_conflicts) + == (unsigned int) ALLOCNO_REGNO (OBJECT_ALLOCNO (obj))) + continue; + SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); } @@ -154,12 +163,38 @@ static void make_object_dead (ira_object_t obj) { live_range_t lr; + int ignore_regno = -1; + int end_regno = -1; sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj)); + /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts + with OBJ. */ + if (ignore_reg_for_conflicts != NULL_RTX + && REGNO (ignore_reg_for_conflicts) < FIRST_PSEUDO_REGISTER) + { + end_regno = END_REGNO (ignore_reg_for_conflicts); + int src_regno = ignore_regno = REGNO (ignore_reg_for_conflicts); + + while (src_regno < end_regno) + { + if (TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), src_regno)) + { + ignore_regno = end_regno = -1; + break; + } + src_regno++; + } + } + IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), hard_regs_live); IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), hard_regs_live); + /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with OBJ, make + sure it still doesn't. */ + for (; ignore_regno < end_regno; ignore_regno++) + CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), ignore_regno); + lr = OBJECT_LIVE_RANGES (obj); ira_assert (lr != NULL); lr->finish = curr_point; @@ -1022,6 +1057,38 @@ find_call_crossed_cheap_reg (rtx_insn *insn) return cheap_reg; } +/* Determine whether INSN is a register to register copy of the type where + we do not need to make the source and destiniation registers conflict. + If this is a copy instruction, then return the source reg. Otherwise, + return NULL_RTX. */ +rtx +non_conflicting_reg_copy_p (rtx_insn *insn) +{ + rtx set = single_set (insn); + + /* Disallow anything other than a simple register to register copy + that has no side effects. */ + if (set == NULL_RTX + || !REG_P (SET_DEST (set)) + || !REG_P (SET_SRC (set)) + || side_effects_p (set)) + return NULL_RTX; + + int dst_regno = REGNO (SET_DEST (set)); + int src_regno = REGNO (SET_SRC (set)); + machine_mode mode = GET_MODE (SET_DEST (set)); + + /* Computing conflicts for register pairs is difficult to get right, so + for now, disallow it. */ + if ((dst_regno < FIRST_PSEUDO_REGISTER + && hard_regno_nregs (dst_regno, mode) != 1) + || (src_regno < FIRST_PSEUDO_REGISTER + && hard_regno_nregs (src_regno, mode) != 1)) + return NULL_RTX; + + return SET_SRC (set); +} + /* Process insns of the basic block given by its LOOP_TREE_NODE to update allocno live ranges, allocno hard register conflicts, intersected calls, and register pressure info for allocnos for the @@ -1107,22 +1174,7 @@ process_bb_node_lives (ira_loop_tree_node_t loop_tree_node) curr_point); call_p = CALL_P (insn); -#ifdef REAL_PIC_OFFSET_TABLE_REGNUM - int regno; - bool clear_pic_use_conflict_p = false; - /* Processing insn usage in call insn can create conflict - with pic pseudo and pic hard reg and that is wrong. - Check this situation and fix it at the end of the insn - processing. */ - if (call_p && pic_offset_table_rtx != NULL_RTX - && (regno = REGNO (pic_offset_table_rtx)) >= FIRST_PSEUDO_REGISTER - && (a = ira_curr_regno_allocno_map[regno]) != NULL) - clear_pic_use_conflict_p - = (find_regno_fusage (insn, USE, REAL_PIC_OFFSET_TABLE_REGNUM) - && ! TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS - (ALLOCNO_OBJECT (a, 0)), - REAL_PIC_OFFSET_TABLE_REGNUM)); -#endif + ignore_reg_for_conflicts = non_conflicting_reg_copy_p (insn); /* Mark each defined value as live. We need to do this for unused values because they still conflict with quantities @@ -1276,20 +1328,9 @@ process_bb_node_lives (ira_loop_tree_node_t loop_tree_node) } } -#ifdef REAL_PIC_OFFSET_TABLE_REGNUM - if (clear_pic_use_conflict_p) - { - regno = REGNO (pic_offset_table_rtx); - a = ira_curr_regno_allocno_map[regno]; - CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (ALLOCNO_OBJECT (a, 0)), - REAL_PIC_OFFSET_TABLE_REGNUM); - CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS - (ALLOCNO_OBJECT (a, 0)), - REAL_PIC_OFFSET_TABLE_REGNUM); - } -#endif curr_point++; } + ignore_reg_for_conflicts = NULL_RTX; if (bb_has_eh_pred (bb)) for (j = 0; ; ++j) diff --git a/gcc/ira.h b/gcc/ira.h index 9df983c..8a8e460 100644 --- a/gcc/ira.h +++ b/gcc/ira.h @@ -210,6 +210,9 @@ extern void ira_adjust_equiv_reg_cost (unsigned, int); /* ira-costs.c */ extern void ira_costs_c_finalize (void); +/* ira-lives.c */ +extern rtx non_conflicting_reg_copy_p (rtx_insn *); + /* Spilling static chain pseudo may result in generation of wrong non-local goto code using frame-pointer to address saved stack pointer value after restoring old frame pointer value. The diff --git a/gcc/lra-lives.c b/gcc/lra-lives.c index a3bc29c..0bf8cd0 100644 --- a/gcc/lra-lives.c +++ b/gcc/lra-lives.c @@ -96,6 +96,10 @@ static bitmap_head temp_bitmap; /* Pool for pseudo live ranges. */ static object_allocator lra_live_range_pool ("live ranges"); +/* If non-NULL, the source operand of a register to register copy for which + we should not add a conflict with the copy's destination operand. */ +static rtx ignore_reg_for_conflicts; + /* Free live range list LR. */ static void free_live_range_list (lra_live_range_t lr) @@ -239,11 +243,9 @@ make_hard_regno_live (int regno) /* Process the definition of hard register REGNO. This updates hard_regs_live, START_DYING and conflict hard regs for living - pseudos. Conflict hard regs for the pic pseudo is not updated if - REGNO is REAL_PIC_OFFSET_TABLE_REGNUM and CHECK_PIC_PSEUDO_P is - true. */ + pseudos. */ static void -make_hard_regno_dead (int regno, bool check_pic_pseudo_p ATTRIBUTE_UNUSED) +make_hard_regno_dead (int regno) { lra_assert (regno < FIRST_PSEUDO_REGISTER); if (! TEST_HARD_REG_BIT (hard_regs_live, regno)) @@ -251,13 +253,12 @@ make_hard_regno_dead (int regno, bool check_pic_pseudo_p ATTRIBUTE_UNUSED) sparseset_set_bit (start_dying, regno); unsigned int i; EXECUTE_IF_SET_IN_SPARSESET (pseudos_live, i) -#ifdef REAL_PIC_OFFSET_TABLE_REGNUM - if (! check_pic_pseudo_p - || regno != REAL_PIC_OFFSET_TABLE_REGNUM - || pic_offset_table_rtx == NULL - || i != REGNO (pic_offset_table_rtx)) -#endif + { + if (ignore_reg_for_conflicts != NULL_RTX + && REGNO (ignore_reg_for_conflicts) == i) + continue; SET_HARD_REG_BIT (lra_reg_info[i].conflict_hard_regs, regno); + } CLEAR_HARD_REG_BIT (hard_regs_live, regno); if (fixed_regs[regno] || TEST_HARD_REG_BIT (hard_regs_spilled_into, regno)) { @@ -294,14 +295,41 @@ static void mark_pseudo_dead (int regno, int point) { lra_live_range_t p; + int ignore_regno = -1; + int end_regno = -1; lra_assert (regno >= FIRST_PSEUDO_REGISTER); lra_assert (sparseset_bit_p (pseudos_live, regno)); sparseset_clear_bit (pseudos_live, regno); sparseset_set_bit (start_dying, regno); + /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts + with REGNO. */ + if (ignore_reg_for_conflicts != NULL_RTX + && REGNO (ignore_reg_for_conflicts) < FIRST_PSEUDO_REGISTER) + { + end_regno = END_REGNO (ignore_reg_for_conflicts); + int src_regno = ignore_regno = REGNO (ignore_reg_for_conflicts); + + while (src_regno < end_regno) + { + if (TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, + src_regno)) + { + ignore_regno = end_regno = -1; + break; + } + src_regno++; + } + } + IOR_HARD_REG_SET (lra_reg_info[regno].conflict_hard_regs, hard_regs_live); + /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with REGNO, make + sure it still doesn't. */ + for (; ignore_regno < end_regno; ignore_regno++) + CLEAR_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, ignore_regno); + if (complete_info_p || lra_get_regno_hard_regno (regno) < 0) { p = lra_reg_info[regno].live_ranges; @@ -350,7 +378,7 @@ mark_regno_dead (int regno, machine_mode mode, int point) if (regno < FIRST_PSEUDO_REGISTER) { for (last = end_hard_regno (mode, regno); regno < last; regno++) - make_hard_regno_dead (regno, false); + make_hard_regno_dead (regno); } else { @@ -747,6 +775,7 @@ process_bb_lives (basic_block bb, int &curr_point, bool dead_insn_p) } call_p = CALL_P (curr_insn); + ignore_reg_for_conflicts = non_conflicting_reg_copy_p (curr_insn); src_regno = (set != NULL_RTX && REG_P (SET_SRC (set)) ? REGNO (SET_SRC (set)) : -1); dst_regno = (set != NULL_RTX && REG_P (SET_DEST (set)) @@ -858,14 +887,13 @@ process_bb_lives (basic_block bb, int &curr_point, bool dead_insn_p) for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) if (reg->type == OP_OUT && ! reg_early_clobber_p (reg, n_alt) && ! reg->subreg_p) - make_hard_regno_dead (reg->regno, false); + make_hard_regno_dead (reg->regno); if (curr_id->arg_hard_regs != NULL) for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) if (regno >= FIRST_PSEUDO_REGISTER) - /* It is a clobber. Don't create conflict of used - REAL_PIC_OFFSET_TABLE_REGNUM and the pic pseudo. */ - make_hard_regno_dead (regno - FIRST_PSEUDO_REGISTER, true); + /* It is a clobber. */ + make_hard_regno_dead (regno - FIRST_PSEUDO_REGISTER); if (call_p) { @@ -926,8 +954,7 @@ process_bb_lives (basic_block bb, int &curr_point, bool dead_insn_p) make_hard_regno_live (reg->regno); if (curr_id->arg_hard_regs != NULL) - /* Make argument hard registers live. Don't create conflict - of used REAL_PIC_OFFSET_TABLE_REGNUM and the pic pseudo. */ + /* Make argument hard registers live. */ for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) if (regno < FIRST_PSEUDO_REGISTER) make_hard_regno_live (regno); @@ -955,7 +982,7 @@ process_bb_lives (basic_block bb, int &curr_point, bool dead_insn_p) if (reg2->type != OP_OUT && reg2->regno == reg->regno) break; if (reg2 == NULL) - make_hard_regno_dead (reg->regno, false); + make_hard_regno_dead (reg->regno); } if (need_curr_point_incr) @@ -990,6 +1017,7 @@ process_bb_lives (basic_block bb, int &curr_point, bool dead_insn_p) EXECUTE_IF_SET_IN_SPARSESET (unused_set, j) add_reg_note (curr_insn, REG_UNUSED, regno_reg_rtx[j]); } + ignore_reg_for_conflicts = NULL_RTX; if (bb_has_eh_pred (bb)) for (j = 0; ; ++j) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 818f6ea..f34b167 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2018-10-05 Peter Bergner + + PR rtl-optimization/86939 + PR rtl-optimization/87479 + * gcc.target/powerpc/pr86939.c: New test. + * gcc/testsuite/gcc.target/i386/pr49095.c: Fix expected results. + 2018-10-05 Bernd Edlinger * gnat.dg/string_merge1.adb: Fix test expectations. diff --git a/gcc/testsuite/gcc.target/i386/pr49095.c b/gcc/testsuite/gcc.target/i386/pr49095.c index 0780719..20175e7 100644 --- a/gcc/testsuite/gcc.target/i386/pr49095.c +++ b/gcc/testsuite/gcc.target/i386/pr49095.c @@ -73,4 +73,5 @@ G (long) /* { dg-final { scan-assembler-not "test\[lq\]" } } */ /* The {f,h}{char,short,int,long}xor functions aren't optimized into a RMW instruction, so need load, modify and store. FIXME eventually. */ -/* { dg-final { scan-assembler-times "\\), %" 8 } } */ +/* { dg-final { scan-assembler-times "\\), %" 57 { target { ia32 } } } } */ +/* { dg-final { scan-assembler-times "\\), %" 45 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr86939.c b/gcc/testsuite/gcc.target/powerpc/pr86939.c new file mode 100644 index 0000000..4bc9793 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr86939.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2" } */ + +typedef long (*fptr_t) (void); +long +func (fptr_t *p) +{ + if (p) + return (*p) (); + return 0; +} +/* { dg-final { scan-assembler-not {mr %?r?12,} } } */ -- cgit v1.1 From f64b9ed94ccf6ee21b769a7213def41918d793a1 Mon Sep 17 00:00:00 2001 From: Thomas Koenig Date: Sat, 6 Oct 2018 11:45:05 +0000 Subject: re PR fortran/84640 (gcc/fortran/simplify.c:2587:9: runtime error: pointer index expression with base 0x0000090de160 overflowed to 0xffffffffc0632960) 2018-10-06 Thomas Koenig PR fortran/84640 * simplify.c (gfc_simplify_cshift): Extend size of hs_ex and ss_ex by one. Set extents one past the array boundaries to zero to avoid warning with instrumented compiler. (gfc_simplify_eoshift): Likewise, only for ss_ex. From-SVN: r264898 --- gcc/fortran/ChangeLog | 8 ++++++++ gcc/fortran/simplify.c | 9 ++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 7eece23..309a714 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,11 @@ + 2018-10-06 Thomas Koenig + + PR fortran/84640 + * simplify.c (gfc_simplify_cshift): Extend size of hs_ex and ss_ex + by one. Set extents one past the array boundaries to zero to avoid + warning with instrumented compiler. + (gfc_simplify_eoshift): Likewise, only for ss_ex. + 2018-10-05 Paul Thomas PR fortran/87487 diff --git a/gcc/fortran/simplify.c b/gcc/fortran/simplify.c index d35bbba..7bdd23d 100644 --- a/gcc/fortran/simplify.c +++ b/gcc/fortran/simplify.c @@ -2011,11 +2011,11 @@ gfc_simplify_cshift (gfc_expr *array, gfc_expr *shift, gfc_expr *dim) ssize_t *shiftvec, *hptr; ssize_t shift_val, len; ssize_t count[GFC_MAX_DIMENSIONS], extent[GFC_MAX_DIMENSIONS], - hs_ex[GFC_MAX_DIMENSIONS], + hs_ex[GFC_MAX_DIMENSIONS + 1], hstride[GFC_MAX_DIMENSIONS], sstride[GFC_MAX_DIMENSIONS], a_extent[GFC_MAX_DIMENSIONS], a_stride[GFC_MAX_DIMENSIONS], h_extent[GFC_MAX_DIMENSIONS], - ss_ex[GFC_MAX_DIMENSIONS]; + ss_ex[GFC_MAX_DIMENSIONS + 1]; ssize_t rsoffset; int d, n; bool continue_loop; @@ -2110,6 +2110,8 @@ gfc_simplify_cshift (gfc_expr *array, gfc_expr *shift, gfc_expr *dim) n++; } } + ss_ex[n] = 0; + hs_ex[n] = 0; if (shiftvec) { @@ -2403,7 +2405,7 @@ gfc_simplify_eoshift (gfc_expr *array, gfc_expr *shift, gfc_expr *boundary, ssize_t shift_val, len; ssize_t count[GFC_MAX_DIMENSIONS], extent[GFC_MAX_DIMENSIONS], sstride[GFC_MAX_DIMENSIONS], a_extent[GFC_MAX_DIMENSIONS], - a_stride[GFC_MAX_DIMENSIONS], ss_ex[GFC_MAX_DIMENSIONS]; + a_stride[GFC_MAX_DIMENSIONS], ss_ex[GFC_MAX_DIMENSIONS + 1]; ssize_t rsoffset; int d, n; bool continue_loop; @@ -2546,6 +2548,7 @@ gfc_simplify_eoshift (gfc_expr *array, gfc_expr *shift, gfc_expr *boundary, n++; } } + ss_ex[n] = 0; continue_loop = true; d = array->rank; -- cgit v1.1 From 2b03b800d866d345b078eaec77ef47fb05daeec2 Mon Sep 17 00:00:00 2001 From: Paul Thomas Date: Sat, 6 Oct 2018 15:14:29 +0000 Subject: re PR fortran/83999 (ICE in gfc_trans_assignment_1, at fortran/trans-expr.c:10233) 2018-10-06 Paul Thomas PR fortran/83999 * resolve.c (resolve_fl_procedure): Include class functions in the test that elemental function results be scalar. 2018-10-06 Paul Thomas PR fortran/83999 * gfortran.dg/elemental_function_4.f90 : New test. From-SVN: r264899 --- gcc/fortran/ChangeLog | 8 +++++++- gcc/fortran/resolve.c | 3 ++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gfortran.dg/elemental_function_4.f90 | 18 ++++++++++++++++++ 4 files changed, 32 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/elemental_function_4.f90 (limited to 'gcc') diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 309a714..542d04c 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,4 +1,10 @@ - 2018-10-06 Thomas Koenig +2018-10-06 Paul Thomas + + Backport from trunk + * resolve.c (resolve_fl_procedure): Include class functions in + the test that elemental function results be scalar. + +2018-10-06 Thomas Koenig PR fortran/84640 * simplify.c (gfc_simplify_cshift): Extend size of hs_ex and ss_ex diff --git a/gcc/fortran/resolve.c b/gcc/fortran/resolve.c index a2beb7f..87e65df 100644 --- a/gcc/fortran/resolve.c +++ b/gcc/fortran/resolve.c @@ -12503,7 +12503,8 @@ resolve_fl_procedure (gfc_symbol *sym, int mp_flag) } /* An elemental function is required to return a scalar 12.7.1 */ - if (sym->attr.elemental && sym->attr.function && sym->as) + if (sym->attr.elemental && sym->attr.function + && (sym->as || (sym->ts.type == BT_CLASS && CLASS_DATA (sym)->as))) { gfc_error ("ELEMENTAL function %qs at %L must have a scalar " "result", sym->name, &sym->declared_at); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f34b167..407e90a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-10-06 Paul Thomas + + PR fortran/83999 + * gfortran.dg/elemental_function_4.f90 : New test. + 2018-10-05 Peter Bergner PR rtl-optimization/86939 diff --git a/gcc/testsuite/gfortran.dg/elemental_function_4.f90 b/gcc/testsuite/gfortran.dg/elemental_function_4.f90 new file mode 100644 index 0000000..fbd55ac --- /dev/null +++ b/gcc/testsuite/gfortran.dg/elemental_function_4.f90 @@ -0,0 +1,18 @@ +! { dg-do compile } +! +! Tests the fix for PR83999, where the invalid function 'f' caused an ICE. +! +! Contributed by Gerhard Steinmetz +! +program p + type t + integer :: a + end type + type(t) :: x(3) + x = f() + print *, x +contains + elemental function f() result(z) ! { dg-error "must have a scalar result" } + type(t), pointer :: z(:) + end +end -- cgit v1.1 From 7318fdcaaabd65b2fc4a38ef2867a94d1550b11a Mon Sep 17 00:00:00 2001 From: Thomas Koenig Date: Sat, 6 Oct 2018 18:20:14 +0000 Subject: re PR fortran/86111 (ICE in gfc_arith_concat, at fortran/arith.c:985) 2018-10-06 Thomas Koenig PR fortran/86111 * gfortran.h (enum arith): Add ARITH_WRONGCONCAT. * arith.h (gfc_arith_error): Issue error for ARITH_WRONGCONCAT. (gfc_arith_concat): If the types of op1 and op2 are not character of if their kinds do not match, issue ARITH_WRONGCONCAT. 2018-10-06 Thomas Koenig PR fortran/86111 * gfortran.dg/array_constructor_type_23.f90: New test. From-SVN: r264900 --- gcc/fortran/ChangeLog | 10 +++++++++- gcc/fortran/arith.c | 12 +++++++++++- gcc/fortran/gfortran.h | 3 ++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gfortran.dg/array_constructor_type_23.f90 | 7 +++++++ 5 files changed, 34 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/array_constructor_type_23.f90 (limited to 'gcc') diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 542d04c..da3200d 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,6 +1,14 @@ +2018-10-06 Thomas Koenig + + PR fortran/86111 + * gfortran.h (enum arith): Add ARITH_WRONGCONCAT. + * arith.h (gfc_arith_error): Issue error for ARITH_WRONGCONCAT. + (gfc_arith_concat): If the types of op1 and op2 are not + character of if their kinds do not match, issue ARITH_WRONGCONCAT. + 2018-10-06 Paul Thomas - Backport from trunk + PR fortran/83999 * resolve.c (resolve_fl_procedure): Include class functions in the test that elemental function results be scalar. diff --git a/gcc/fortran/arith.c b/gcc/fortran/arith.c index 6f97d0f..98af27e 100644 --- a/gcc/fortran/arith.c +++ b/gcc/fortran/arith.c @@ -113,6 +113,11 @@ gfc_arith_error (arith code) p = _("Integer outside symmetric range implied by Standard Fortran at %L"); break; + case ARITH_WRONGCONCAT: + p = + _("Illegal type in character concatenation at %L"); + break; + default: gfc_internal_error ("gfc_arith_error(): Bad error code"); } @@ -982,7 +987,12 @@ gfc_arith_concat (gfc_expr *op1, gfc_expr *op2, gfc_expr **resultp) gfc_expr *result; size_t len; - gcc_assert (op1->ts.kind == op2->ts.kind); + /* By cleverly playing around with constructors, is is possible + to get mismaching types here. */ + if (op1->ts.type != BT_CHARACTER || op2->ts.type != BT_CHARACTER + || op1->ts.kind != op2->ts.kind) + return ARITH_WRONGCONCAT; + result = gfc_get_constant_expr (BT_CHARACTER, op1->ts.kind, &op1->where); diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h index b0518e2..8e50e4d 100644 --- a/gcc/fortran/gfortran.h +++ b/gcc/fortran/gfortran.h @@ -191,7 +191,8 @@ enum gfc_intrinsic_op /* Arithmetic results. */ enum arith { ARITH_OK = 1, ARITH_OVERFLOW, ARITH_UNDERFLOW, ARITH_NAN, - ARITH_DIV0, ARITH_INCOMMENSURATE, ARITH_ASYMMETRIC, ARITH_PROHIBIT + ARITH_DIV0, ARITH_INCOMMENSURATE, ARITH_ASYMMETRIC, ARITH_PROHIBIT, + ARITH_WRONGCONCAT }; /* Statements. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 407e90a..a0b6ead 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-10-06 Thomas Koenig + + PR fortran/86111 + * gfortran.dg/array_constructor_type_23.f90: New test. + 2018-10-06 Paul Thomas PR fortran/83999 diff --git a/gcc/testsuite/gfortran.dg/array_constructor_type_23.f90 b/gcc/testsuite/gfortran.dg/array_constructor_type_23.f90 new file mode 100644 index 0000000..cb88ad2 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/array_constructor_type_23.f90 @@ -0,0 +1,7 @@ +! { dg-do compile } +! PR 83999 - this used to ICE +! Origial test case by Gerhard Steinmetz + +program p + character(2) :: c = 'a' // [character :: [1]] ! { dg-error "Illegal type in character concatenation" } +end -- cgit v1.1 From 7a7bd6960da3712b65bbbcae385abd5ead35332c Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sun, 7 Oct 2018 00:16:21 +0000 Subject: Daily bump. From-SVN: r264906 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 3a02e74..d37cebc 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20181006 +20181007 -- cgit v1.1 From c0485831b79ec7f8e0e4e1975c395f97f26020d7 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Mon, 8 Oct 2018 00:16:56 +0000 Subject: Daily bump. From-SVN: r264910 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index d37cebc..2327ffc 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20181007 +20181008 -- cgit v1.1 From 090680870b633853e40a750036dab2b3df63dd18 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 8 Oct 2018 07:16:28 +0000 Subject: re PR middle-end/63155 (memory hog) 2018-10-08 Richard Biener PR tree-optimization/63155 * tree-ssa-propagate.c (add_ssa_edge): Do cheap check first. (ssa_propagation_engine::ssa_propagate): Remove redundant bitmap bit clearing. From-SVN: r264912 --- gcc/ChangeLog | 7 +++++++ gcc/tree-ssa-propagate.c | 8 +++----- 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 73f26a9..e53b795 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-10-08 Richard Biener + + PR tree-optimization/63155 + * tree-ssa-propagate.c (add_ssa_edge): Do cheap check first. + (ssa_propagation_engine::ssa_propagate): Remove redundant + bitmap bit clearing. + 2018-10-05 Peter Bergner PR rtl-optimization/86939 diff --git a/gcc/tree-ssa-propagate.c b/gcc/tree-ssa-propagate.c index 4cb0fba..b1bfdd5 100644 --- a/gcc/tree-ssa-propagate.c +++ b/gcc/tree-ssa-propagate.c @@ -143,10 +143,12 @@ add_ssa_edge (tree var) FOR_EACH_IMM_USE_FAST (use_p, iter, var) { gimple *use_stmt = USE_STMT (use_p); - basic_block use_bb = gimple_bb (use_stmt); + if (!prop_simulate_again_p (use_stmt)) + continue; /* If we did not yet simulate the block wait for this to happen and do not add the stmt to the SSA edge worklist. */ + basic_block use_bb = gimple_bb (use_stmt); if (! (use_bb->flags & BB_VISITED)) continue; @@ -157,9 +159,6 @@ add_ssa_edge (tree var) & EDGE_EXECUTABLE)) continue; - if (!prop_simulate_again_p (use_stmt)) - continue; - bitmap worklist; if (bb_to_cfg_order[gimple_bb (use_stmt)->index] < curr_order) worklist = ssa_edge_worklist_back; @@ -804,7 +803,6 @@ ssa_propagation_engine::ssa_propagate (void) else { curr_order = next_stmt_bb_order; - bitmap_clear_bit (ssa_edge_worklist, next_stmt_uid); if (dump_file && (dump_flags & TDF_DETAILS)) { fprintf (dump_file, "\nSimulating statement: "); -- cgit v1.1 From 8656dafa39de8e537940433220e8f5db3bf7a614 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 8 Oct 2018 08:16:13 +0000 Subject: Don't ICE on vectors of enums (PR 87286) We've traditionally allowed vectors of enums (not sure if that's deliberate) but vector_types_compatible_elements_p checked for INTEGER_TYPE rather than INTEGRAL_TYPE_P. 2018-10-08 Richard Sandiford gcc/c-family/ PR c/87286 * c-common.c (vector_types_compatible_elements_p): Use INTEGRAL_TYPE_P instead of checking only for INTEGER_TYPE. gcc/testsuite/ PR c/87286 * gcc.dg/pr87286.c: New test. From-SVN: r264913 --- gcc/c-family/ChangeLog | 6 ++++++ gcc/c-family/c-common.c | 9 ++++++--- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/pr87286.c | 3 +++ 4 files changed, 20 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr87286.c (limited to 'gcc') diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index b6ff1f7..6307337 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,9 @@ +2018-10-08 Richard Sandiford + + PR c/87286 + * c-common.c (vector_types_compatible_elements_p): Use + INTEGRAL_TYPE_P instead of checking only for INTEGER_TYPE. + 2018-10-04 Vinay Kumar * c-attribs.c (get_priority): Add a warning flag warn_prio_ctor_dtor diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c index 10a8bc2..c0198e1 100644 --- a/gcc/c-family/c-common.c +++ b/gcc/c-family/c-common.c @@ -7465,8 +7465,11 @@ vector_types_compatible_elements_p (tree t1, tree t2) enum tree_code c1 = TREE_CODE (t1), c2 = TREE_CODE (t2); - gcc_assert ((c1 == INTEGER_TYPE || c1 == REAL_TYPE || c1 == FIXED_POINT_TYPE) - && (c2 == INTEGER_TYPE || c2 == REAL_TYPE + gcc_assert ((INTEGRAL_TYPE_P (t1) + || c1 == REAL_TYPE + || c1 == FIXED_POINT_TYPE) + && (INTEGRAL_TYPE_P (t2) + || c2 == REAL_TYPE || c2 == FIXED_POINT_TYPE)); t1 = c_common_signed_type (t1); @@ -7476,7 +7479,7 @@ vector_types_compatible_elements_p (tree t1, tree t2) if (t1 == t2) return true; if (opaque && c1 == c2 - && (c1 == INTEGER_TYPE || c1 == REAL_TYPE) + && (INTEGRAL_TYPE_P (t1) || c1 == REAL_TYPE) && TYPE_PRECISION (t1) == TYPE_PRECISION (t2)) return true; return false; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a0b6ead..7b8bdc7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-10-08 Richard Sandiford + + PR c/87286 + * gcc.dg/pr87286.c: New test. + 2018-10-06 Thomas Koenig PR fortran/86111 diff --git a/gcc/testsuite/gcc.dg/pr87286.c b/gcc/testsuite/gcc.dg/pr87286.c new file mode 100644 index 0000000..d92d29c --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr87286.c @@ -0,0 +1,3 @@ +enum foo { F }; +typedef enum foo vec_foo __attribute__((vector_size (16))); +vec_foo add (vec_foo x, vec_foo y) { return x + y; } -- cgit v1.1 From a52cdecf114f4f1e5acbdeeb28b9381875a4b9a8 Mon Sep 17 00:00:00 2001 From: Paolo Carlini Date: Mon, 8 Oct 2018 09:02:55 +0000 Subject: re PR c++/71128 ([concepts] ICE on ill-formed explicit instantiation of a function concept) /cp 2018-10-08 Paolo Carlini PR c++/71128 * pt.c (do_decl_instantiation): Per 12.6.8/5, a concept cannot be explicitly instantiated. /testsuite 2018-10-08 Paolo Carlini PR c++/71128 * g++.dg/concepts/pr71128.C: New. From-SVN: r264914 --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/pt.c | 8 ++++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/concepts/pr71128.C | 10 ++++++++++ 4 files changed, 29 insertions(+) create mode 100644 gcc/testsuite/g++.dg/concepts/pr71128.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 97d7e8d..9a0a5ea 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2018-10-08 Paolo Carlini + + PR c++/71128 + * pt.c (do_decl_instantiation): Per 12.6.8/5, a concept cannot be + explicitly instantiated. + 2018-10-05 David Malcolm PR c++/56856 diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index b8b6545..aced6f2 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -23127,6 +23127,14 @@ do_decl_instantiation (tree decl, tree storage) error ("explicit instantiation of non-template %q#D", decl); return; } + else if (DECL_DECLARED_CONCEPT_P (decl)) + { + if (VAR_P (decl)) + error ("explicit instantiation of variable concept %q#D", decl); + else + error ("explicit instantiation of function concept %q#D", decl); + return; + } bool var_templ = (DECL_TEMPLATE_INFO (decl) && variable_template_p (DECL_TI_TEMPLATE (decl))); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7b8bdc7..5a9141d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-10-08 Paolo Carlini + + PR c++/71128 + * g++.dg/concepts/pr71128.C: New. + 2018-10-08 Richard Sandiford PR c/87286 diff --git a/gcc/testsuite/g++.dg/concepts/pr71128.C b/gcc/testsuite/g++.dg/concepts/pr71128.C new file mode 100644 index 0000000..8b4eb41 --- /dev/null +++ b/gcc/testsuite/g++.dg/concepts/pr71128.C @@ -0,0 +1,10 @@ +// { dg-do compile { target c++14 } } +// { dg-additional-options "-fconcepts" } + +template +concept bool C() { return true; } +template bool C(); // { dg-error "explicit instantiation of function concept" } + +template +concept bool D = true; +template bool D; // { dg-error "explicit instantiation of variable concept" } -- cgit v1.1 From c16ac98ea9cddb4725dd5c6d010bdeaac14d1a25 Mon Sep 17 00:00:00 2001 From: Paul Thomas Date: Mon, 8 Oct 2018 09:11:03 +0000 Subject: re PR fortran/86372 (Segfault on ASSOCIATE statement with CHARACTER variable) 2018-10-08 Paul Thomas PR fortran/86372 * trans-stmt.c (trans_associate_var): Character associate names with variable string length do not have to be deferred length for the string length to be set, if variable. 2018-10-08 Paul Thomas PR fortran/86372 * gfortran.dg/associate_41.f90: New test. From-SVN: r264915 --- gcc/fortran/trans-stmt.c | 1 - gcc/testsuite/gfortran.dg/associate_41.f90 | 25 +++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gfortran.dg/associate_41.f90 (limited to 'gcc') diff --git a/gcc/fortran/trans-stmt.c b/gcc/fortran/trans-stmt.c index ef9e519..6256e3f 100644 --- a/gcc/fortran/trans-stmt.c +++ b/gcc/fortran/trans-stmt.c @@ -1885,7 +1885,6 @@ trans_associate_var (gfc_symbol *sym, gfc_wrapped_block *block) } if (sym->ts.type == BT_CHARACTER - && sym->ts.deferred && !sym->attr.select_type_temporary && VAR_P (sym->ts.u.cl->backend_decl) && se.string_length != sym->ts.u.cl->backend_decl) diff --git a/gcc/testsuite/gfortran.dg/associate_41.f90 b/gcc/testsuite/gfortran.dg/associate_41.f90 new file mode 100644 index 0000000..9177582a --- /dev/null +++ b/gcc/testsuite/gfortran.dg/associate_41.f90 @@ -0,0 +1,25 @@ +! { dg-do run } +! +! Test the fix for PR86372 in which the associate name string length was +! not being set, thereby causing a segfault. +! +! Contributed by Janus Weil +! +program xxx + + character(len=50) :: s + + s = repeat ('*', len(s)) + call sub(s) + if (s .ne. '**'//'123'//repeat ('*', len(s) - 5)) stop 1 + +contains + + subroutine sub(str) + character(len=*), intent(inout) :: str + associate (substr => str(3:5)) + substr = '123' + end associate + end subroutine + +end -- cgit v1.1 From 1a097fd827d2a73220e21a7582017fba67ba1677 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Mon, 8 Oct 2018 11:53:44 +0200 Subject: Limit a MV test just for x86 target. 2018-10-08 Martin Liska * g++.dg/ext/pr82625.C: Add dg-compile filter. From-SVN: r264916 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/g++.dg/ext/pr82625.C | 1 + 2 files changed, 5 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5a9141d..021235e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2018-10-08 Martin Liska + + * g++.dg/ext/pr82625.C: Add dg-compile filter. + 2018-10-08 Paolo Carlini PR c++/71128 diff --git a/gcc/testsuite/g++.dg/ext/pr82625.C b/gcc/testsuite/g++.dg/ext/pr82625.C index 47bd2df..59b174f 100644 --- a/gcc/testsuite/g++.dg/ext/pr82625.C +++ b/gcc/testsuite/g++.dg/ext/pr82625.C @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-ifunc "" } */ /* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ __attribute__ ((target ("default"))) static unsigned foo(const char *buf, unsigned size) { -- cgit v1.1 From 1a2a0b604457d4920151a4f8d0712430438fe8dc Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Mon, 8 Oct 2018 10:59:36 +0000 Subject: Require constructor priority support in c-c++-common/Wprio-ctor-dtor.c * c-c++-common/Wprio-ctor-dtor.c: Require init_priority support. From-SVN: r264917 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/c-c++-common/Wprio-ctor-dtor.c | 1 + 2 files changed, 5 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 021235e..dd4852f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2018-10-08 Rainer Orth + + * c-c++-common/Wprio-ctor-dtor.c: Require init_priority support. + 2018-10-08 Martin Liska * g++.dg/ext/pr82625.C: Add dg-compile filter. diff --git a/gcc/testsuite/c-c++-common/Wprio-ctor-dtor.c b/gcc/testsuite/c-c++-common/Wprio-ctor-dtor.c index 5b08059..9da7254 100644 --- a/gcc/testsuite/c-c++-common/Wprio-ctor-dtor.c +++ b/gcc/testsuite/c-c++-common/Wprio-ctor-dtor.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-effective-target init_priority } */ /* { dg-options "-Wno-prio-ctor-dtor" } */ void construct1 () __attribute__ ((constructor (10))); -- cgit v1.1 From 87454aad9964de6234e661e29f96d73dff65a0e4 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Mon, 8 Oct 2018 11:03:22 +0000 Subject: Require string merging support in gnat.dg/string_merge?.adb etc. * gcc.dg/merge-all-constants-2.c: Require string_merging support. * gnat.dg/string_merge1.adb: Likewise. * gnat.dg/string_merge2.adb: Likewise. From-SVN: r264918 --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.dg/merge-all-constants-2.c | 1 + gcc/testsuite/gnat.dg/string_merge1.adb | 1 + gcc/testsuite/gnat.dg/string_merge2.adb | 1 + 4 files changed, 9 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dd4852f..e3f48d7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2018-10-08 Rainer Orth + * gcc.dg/merge-all-constants-2.c: Require string_merging support. + * gnat.dg/string_merge1.adb: Likewise. + * gnat.dg/string_merge2.adb: Likewise. + +2018-10-08 Rainer Orth + * c-c++-common/Wprio-ctor-dtor.c: Require init_priority support. 2018-10-08 Martin Liska diff --git a/gcc/testsuite/gcc.dg/merge-all-constants-2.c b/gcc/testsuite/gcc.dg/merge-all-constants-2.c index fbdb2bb..852d35e 100644 --- a/gcc/testsuite/gcc.dg/merge-all-constants-2.c +++ b/gcc/testsuite/gcc.dg/merge-all-constants-2.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-effective-target string_merging } */ /* { dg-options "-w -O2 -fmerge-all-constants" } */ const char str1[36] = "0123456789abcdefghijklmnopqrstuvwxyz"; diff --git a/gcc/testsuite/gnat.dg/string_merge1.adb b/gcc/testsuite/gnat.dg/string_merge1.adb index 52b9f3c..f3fcac9 100644 --- a/gcc/testsuite/gnat.dg/string_merge1.adb +++ b/gcc/testsuite/gnat.dg/string_merge1.adb @@ -1,4 +1,5 @@ -- { dg-do compile } +-- { dg-require-effective-target string_merging } -- { dg-options "-O1 -fmerge-all-constants" } procedure String_Merge1 is diff --git a/gcc/testsuite/gnat.dg/string_merge2.adb b/gcc/testsuite/gnat.dg/string_merge2.adb index a2d37bd..3615b0d 100644 --- a/gcc/testsuite/gnat.dg/string_merge2.adb +++ b/gcc/testsuite/gnat.dg/string_merge2.adb @@ -1,4 +1,5 @@ -- { dg-do compile } +-- { dg-require-effective-target string_merging } -- { dg-options "-O1 -fmerge-all-constants" } procedure String_Merge2 is -- cgit v1.1 From 0054ef84b0435bb46844a56eb9587454c4f53c87 Mon Sep 17 00:00:00 2001 From: Paul Thomas Date: Mon, 8 Oct 2018 11:17:10 +0000 Subject: re PR fortran/86372 (Segfault on ASSOCIATE statement with CHARACTER variable) 2018-10-08 Paul Thomas PR fortran/86372 * trans-stmt.c (trans_associate_var): Character associate names with variable string length do not have to be deferred length for the string length to be set, if variable. 2018-10-08 Paul Thomas PR fortran/86372 * gfortran.dg/associate_41.f90: New test. From-SVN: r264919 --- gcc/fortran/ChangeLog | 7 +++++++ gcc/testsuite/ChangeLog | 5 +++++ 2 files changed, 12 insertions(+) (limited to 'gcc') diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index da3200d..c4c14f8 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,10 @@ +2018-10-08 Paul Thomas + + PR fortran/86372 + * trans-stmt.c (trans_associate_var): Character associate names + with variable string length do not have to be deferred length + for the string length to be set, if variable. + 2018-10-06 Thomas Koenig PR fortran/86111 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e3f48d7..28e84d2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-10-08 Paul Thomas + + PR fortran/86372 + * gfortran.dg/associate_41.f90: New test. + 2018-10-08 Rainer Orth * gcc.dg/merge-all-constants-2.c: Require string_merging support. -- cgit v1.1 From 269ba95042e9fa35f6fa4c8270339bb932e8f7e9 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 8 Oct 2018 12:29:51 +0000 Subject: tree-vect-loop.c (vect_compute_single_scalar_iteration_cost): Open a dump scope. 2018-10-08 Richard Biener * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost): Open a dump scope. * tree-vectorizer.c (dump_stmt_cost): Add cost param and dump it. * tree-vectorizer.h (dump_stmt_cost): Adjust. (add_stmt_cost): Dump return value of the hook. From-SVN: r264923 --- gcc/ChangeLog | 8 ++++++++ gcc/tree-vect-loop.c | 2 ++ gcc/tree-vectorizer.c | 3 ++- gcc/tree-vectorizer.h | 11 +++++++---- 4 files changed, 19 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e53b795..b7265c0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2018-10-08 Richard Biener + * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost): + Open a dump scope. + * tree-vectorizer.c (dump_stmt_cost): Add cost param and dump it. + * tree-vectorizer.h (dump_stmt_cost): Adjust. + (add_stmt_cost): Dump return value of the hook. + +2018-10-08 Richard Biener + PR tree-optimization/63155 * tree-ssa-propagate.c (add_ssa_edge): Do cheap check first. (ssa_propagation_engine::ssa_propagate): Remove redundant diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c index 6ea1e77..177b284 100644 --- a/gcc/tree-vect-loop.c +++ b/gcc/tree-vect-loop.c @@ -1072,6 +1072,8 @@ vect_compute_single_scalar_iteration_cost (loop_vec_info loop_vinfo) int nbbs = loop->num_nodes, factor; int innerloop_iters, i; + DUMP_VECT_SCOPE ("vect_compute_single_scalar_iteration_cost"); + /* Gather costs for statements in the scalar loop. */ /* FORNOW. */ diff --git a/gcc/tree-vectorizer.c b/gcc/tree-vectorizer.c index 747fb67..0ab366b 100644 --- a/gcc/tree-vectorizer.c +++ b/gcc/tree-vectorizer.c @@ -89,7 +89,7 @@ dump_user_location_t vect_location; void dump_stmt_cost (FILE *f, void *data, int count, enum vect_cost_for_stmt kind, - stmt_vec_info stmt_info, int misalign, + stmt_vec_info stmt_info, int misalign, unsigned cost, enum vect_cost_model_location where) { fprintf (f, "%p ", data); @@ -159,6 +159,7 @@ dump_stmt_cost (FILE *f, void *data, int count, enum vect_cost_for_stmt kind, fprintf (f, "%s ", ks); if (kind == unaligned_load || kind == unaligned_store) fprintf (f, "(misalign %d) ", misalign); + fprintf (f, "costs %u ", cost); const char *ws = "unknown"; switch (where) { diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h index 63cff79..9884568 100644 --- a/gcc/tree-vectorizer.h +++ b/gcc/tree-vectorizer.h @@ -1199,7 +1199,8 @@ init_cost (struct loop *loop_info) } extern void dump_stmt_cost (FILE *, void *, int, enum vect_cost_for_stmt, - stmt_vec_info, int, enum vect_cost_model_location); + stmt_vec_info, int, unsigned, + enum vect_cost_model_location); /* Alias targetm.vectorize.add_stmt_cost. */ @@ -1208,10 +1209,12 @@ add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind, stmt_vec_info stmt_info, int misalign, enum vect_cost_model_location where) { + unsigned cost = targetm.vectorize.add_stmt_cost (data, count, kind, + stmt_info, misalign, where); if (dump_file && (dump_flags & TDF_DETAILS)) - dump_stmt_cost (dump_file, data, count, kind, stmt_info, misalign, where); - return targetm.vectorize.add_stmt_cost (data, count, kind, - stmt_info, misalign, where); + dump_stmt_cost (dump_file, data, count, kind, stmt_info, misalign, + cost, where); + return cost; } /* Alias targetm.vectorize.finish_cost. */ -- cgit v1.1 From 49108562af2b2c0b96090ed0c6b4abbabb3f9080 Mon Sep 17 00:00:00 2001 From: Robin Dapp Date: Mon, 8 Oct 2018 13:16:32 +0000 Subject: S/390: Increase latencies for some FP instructions This patch increases the latency of some floating point instructions to better match the real machine's behavior. 2018-10-08 Robin Dapp * config/s390/2827.md: Increase latencies for some FP instructions. From-SVN: r264927 --- gcc/ChangeLog | 4 ++++ gcc/config/s390/2827.md | 14 +++++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b7265c0..1ee5edd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2018-10-08 Robin Dapp + + * config/s390/2827.md: Increase latencies for some FP instructions. + 2018-10-08 Richard Biener * tree-vect-loop.c (vect_compute_single_scalar_iteration_cost): diff --git a/gcc/config/s390/2827.md b/gcc/config/s390/2827.md index a709a2e..1fef0bb 100644 --- a/gcc/config/s390/2827.md +++ b/gcc/config/s390/2827.md @@ -38,9 +38,13 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ltg,ogrk,lr,lghrl,x,asi,lhr,ar,lhrl,llgfr,clghrl,cgr,cli,agrk,ic,lrv,clg,cy,cghi,sy,clgfr,al,tm,lang,lghr,laa,ark,lh,or,icy,xi,n,llihl,afi,cs,nrk,sth,lgr,l,lcr,stey,xg,crt,slgfr,ny,ld,j,llihh,slgr,clfhsi,slg,lb,lgrl,lrl,llihf,llcr,laxg,mvghi,rllg,xrk,laag,alhsik,algfi,algr,aly,agfi,lrvr,d,crl,llgc,tmhl,algsi,lgh,icmh,clhrl,xgrk,icm,iilf,ork,cg,ldgr,lgf,iihf,llghr,sg,stam,tmhh,slgf,basr,lgb,cgfi,lax,clfit,lrvgr,nihl,ni,srdl,srk,xihf,stgrl,sthrl,algf,cgit,ng,lat,llghrl,ltgr,nihh,clgfrl,srlk,agr,ler,bcr_flush,stcy,cds,clfi,nihf,ly,clt,lgat,alg,lhy,lgfrl,clghsi,clrt,tmll,srlg,ay,sty,clr,lgfi,lan,clgt,ahik,sra,algrk,clgr,tmy,tmlh,alghsik,lcgr,mvi,ltgf,xr,larl,ldr,llgcr,clgrt,clrl,cghsi,cliy,oy,ogr,llgt,slr,chi,s,icmy,llc,ngr,clhhsi,ltgfr,llill,lhi,o,sll,clgrl,clgf,mviy,algfr,rll,sldl,lg,niy,st,sgr,ag,le,xgr,cr,stg,llilh,sr,cdsg,sllk,stoc,csg,clgit,chhsi,strl,llilf,lndfr,ngrk,clgfi,llgh,oill,la,llhrl,stc,lghi,oihl,xiy,sllg,llgf,cgrt,cl,sl,oi,oilh,nr,srak,oihh,ear,slgrk,og,c,slgfi,sthy,oilf,oiy,oihf,a,cfi,srag,brasl,alr,cgrl,llgfrl,cit,ley,exrl,lcdfr,lay,xilf,alsi,mvhhi,srl,chsi,lgfr,lrvg,cly,sgrk,ahi,nill,jg,slrk,lxr,sar,slfi,cpsdr,lcgfr,aghik,nilh,mvhi,lpdfr,xy,alrk,lao,agsi,ldy,nilf,llhr,alfi,laog,sly,aghi,bras,srda,lt,lbr,lzxr,lzdr,lzer")) "nothing") -(define_insn_reservation "zEC12_simple_fp" 1 +(define_insn_reservation "zEC12_simple_fp" 0 (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "lnebr,sdbr,sebr,clfxtr,adbr,aebr,celfbr,clfebr,lpebr,msebr,lndbr,clfdbr,llgtr,cebr,lgbr,maebr,ltebr,clfdtr,ltr,cdlgbr,cxlftr,lpdbr,cdfbr,lcebr,clfxbr,msdbr,cdbr,madbr,meebr,clgxbr,clgdtr,ledbr,cegbr,cdlftr,cdlgtr,mdbr,clgebr,ltdbr,cdlfbr,cdgbr,clgxtr,lcdbr,celgbr,clgdbr,ldebr,cefbr,fidtr,fixtr,madb,msdb,mseb,fiebra,fidbra,fixbra,aeb,mdb,seb,cdb,tcdb,sdb,adb,tceb,maeb,ceb,meeb,ldeb")) "nothing") + (eq_attr "mnemonic" "llgtr,lgbr,ltr")) "nothing") + +(define_insn_reservation "zEC12_normal_fp" 8 + (and (eq_attr "cpu" "zEC12") + (eq_attr "mnemonic" "lnebr,sdbr,sebr,clfxtr,adbr,aebr,celfbr,clfebr,lpebr,msebr,lndbr,clfdbr,cebr,maebr,ltebr,clfdtr,cdlgbr,cxlftr,lpdbr,cdfbr,lcebr,clfxbr,msdbr,cdbr,madbr,meebr,clgxbr,clgdtr,ledbr,cegbr,cdlftr,cdlgtr,mdbr,clgebr,ltdbr,cdlfbr,cdgbr,clgxtr,lcdbr,celgbr,clgdbr,ldebr,cefbr,fidtr,fixtr,madb,msdb,mseb,fiebra,fidbra,aeb,mdb,seb,cdb,tcdb,sdb,adb,tceb,maeb,ceb,meeb,ldeb")) "nothing") (define_insn_reservation "zEC12_cgdbr" 2 (and (eq_attr "cpu" "zEC12") @@ -294,7 +298,7 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "locgr")) "nothing") -(define_insn_reservation "zEC12_debr" 23 +(define_insn_reservation "zEC12_debr" 29 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "debr")) "nothing") @@ -422,7 +426,7 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "cxbr")) "nothing") -(define_insn_reservation "zEC12_ddbr" 30 +(define_insn_reservation "zEC12_ddbr" 36 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ddbr")) "nothing") @@ -430,7 +434,7 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "stmy")) "nothing") -(define_insn_reservation "zEC12_ste" 3 +(define_insn_reservation "zEC12_ste" 4 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ste")) "nothing") -- cgit v1.1 From ed9984a03070a1be7c5b3815e410e6269ab721e4 Mon Sep 17 00:00:00 2001 From: Cesar Philippidis Date: Mon, 8 Oct 2018 07:04:45 -0700 Subject: [Fortran] Disable "Assignment to contiguous pointer from non-contiguous target" error gcc/fortran/ * expr.c (gfc_check_pointer_assign): Demote "Assignment to contiguous pointer from non-contiguous target" to a warning. gcc/testsuite/ * gfortran.dg/contiguous_4.f90: Adjust. * gfortran.dg/contiguous_4.f90: New test. From-SVN: r264928 --- gcc/fortran/ChangeLog | 5 +++++ gcc/fortran/expr.c | 6 +++--- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gfortran.dg/contiguous_4.f90 | 6 +++--- gcc/testsuite/gfortran.dg/contiguous_7.f90 | 24 ++++++++++++++++++++++++ 5 files changed, 40 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/contiguous_7.f90 (limited to 'gcc') diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index c4c14f8..6fc3857 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,8 @@ +2018-10-08 Cesar Philippidis + + * expr.c (gfc_check_pointer_assign): Demote "Assignment to + contiguous pointer from non-contiguous target" to a warning. + 2018-10-08 Paul Thomas PR fortran/86372 diff --git a/gcc/fortran/expr.c b/gcc/fortran/expr.c index 3315bb8..1cfda5f 100644 --- a/gcc/fortran/expr.c +++ b/gcc/fortran/expr.c @@ -3957,13 +3957,13 @@ gfc_check_pointer_assign (gfc_expr *lvalue, gfc_expr *rvalue) } } - /* Error for assignments of contiguous pointers to targets which is not + /* Warn for assignments of contiguous pointers to targets which is not contiguous. Be lenient in the definition of what counts as contiguous. */ if (lhs_attr.contiguous && !gfc_is_simply_contiguous (rvalue, false, true)) - gfc_error ("Assignment to contiguous pointer from non-contiguous " - "target at %L", &rvalue->where); + gfc_warning (OPT_Wextra, "Assignment to contiguous pointer from " + "non-contiguous target at %L", &rvalue->where); /* Warn if it is the LHS pointer may lives longer than the RHS target. */ if (warn_target_lifetime diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 28e84d2..9d495d4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-10-08 Cesar Philippidis + + * gfortran.dg/contiguous_4.f90: Adjust. + * gfortran.dg/contiguous_4.f90: New test. + 2018-10-08 Paul Thomas PR fortran/86372 diff --git a/gcc/testsuite/gfortran.dg/contiguous_4.f90 b/gcc/testsuite/gfortran.dg/contiguous_4.f90 index b05dcfb..874ef8b 100644 --- a/gcc/testsuite/gfortran.dg/contiguous_4.f90 +++ b/gcc/testsuite/gfortran.dg/contiguous_4.f90 @@ -10,10 +10,10 @@ program cont_01_neg x = (/ (real(i),i=1,45) /) x2 = reshape(x,shape(x2)) - r => x(::3) ! { dg-error "Assignment to contiguous pointer" } - r2 => x2(2:,:) ! { dg-error "Assignment to contiguous pointer" } + r => x(::3) + r2 => x2(2:,:) r2 => x2(:,2:3) r => x2(2:3,1) r => x(::1) - r => x(::n) ! { dg-error "Assignment to contiguous pointer" } + r => x(::n) end program diff --git a/gcc/testsuite/gfortran.dg/contiguous_7.f90 b/gcc/testsuite/gfortran.dg/contiguous_7.f90 new file mode 100644 index 0000000..cccc89f --- /dev/null +++ b/gcc/testsuite/gfortran.dg/contiguous_7.f90 @@ -0,0 +1,24 @@ +! { dg-do compile } +! { dg-additional-options "-Wextra" } +! +! Ensure that contiguous pointers pointing to noncontiguous pointers +! to array results in a warning with -Wextra. + +program cont_01_neg + implicit none + real, pointer, contiguous :: r(:) + real, pointer, contiguous :: r2(:,:) + real, target :: x(45) + real, target :: x2(5,9) + integer :: i + integer :: n=1 + + x = (/ (real(i),i=1,45) /) + x2 = reshape(x,shape(x2)) + r => x(::3) ! { dg-warning "ssignment to contiguous pointer from non-contiguous target" } + r2 => x2(2:,:) ! { dg-warning "ssignment to contiguous pointer from non-contiguous target" } + r2 => x2(:,2:3) + r => x2(2:3,1) + r => x(::1) + r => x(::n) ! { dg-warning "ssignment to contiguous pointer from non-contiguous target" } +end program -- cgit v1.1 From a3927ffb90429d9ac6bd73190063f8b922cfec45 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Mon, 8 Oct 2018 16:12:53 +0200 Subject: Come up with gcc/testsuite/g++.target/i386/i386.dg and move there some tests. 2018-10-08 Martin Liska * gcc.target/i386/i386.exp: Move procedures to target-supports.exp. * g++.target/i386/i386.exp: New file. * gcc.target/i386/mv*.C: Move here tests and remove target filter in these tests. From-SVN: r264929 --- gcc/testsuite/ChangeLog | 8 + gcc/testsuite/g++.dg/ext/mv1.C | 132 --------- gcc/testsuite/g++.dg/ext/mv10.C | 12 - gcc/testsuite/g++.dg/ext/mv11.C | 23 -- gcc/testsuite/g++.dg/ext/mv12-aux.cc | 10 - gcc/testsuite/g++.dg/ext/mv12.C | 22 -- gcc/testsuite/g++.dg/ext/mv12.h | 4 - gcc/testsuite/g++.dg/ext/mv13.C | 18 -- gcc/testsuite/g++.dg/ext/mv14.C | 40 --- gcc/testsuite/g++.dg/ext/mv15.C | 40 --- gcc/testsuite/g++.dg/ext/mv16.C | 101 ------- gcc/testsuite/g++.dg/ext/mv17.C | 93 ------ gcc/testsuite/g++.dg/ext/mv18.C | 7 - gcc/testsuite/g++.dg/ext/mv19.C | 7 - gcc/testsuite/g++.dg/ext/mv2.C | 127 -------- gcc/testsuite/g++.dg/ext/mv20.C | 7 - gcc/testsuite/g++.dg/ext/mv21.C | 7 - gcc/testsuite/g++.dg/ext/mv22.C | 7 - gcc/testsuite/g++.dg/ext/mv23.C | 7 - gcc/testsuite/g++.dg/ext/mv24.C | 35 --- gcc/testsuite/g++.dg/ext/mv25.C | 35 --- gcc/testsuite/g++.dg/ext/mv26.C | 15 - gcc/testsuite/g++.dg/ext/mv27.C | 18 -- gcc/testsuite/g++.dg/ext/mv3.C | 36 --- gcc/testsuite/g++.dg/ext/mv4.C | 24 -- gcc/testsuite/g++.dg/ext/mv5.C | 25 -- gcc/testsuite/g++.dg/ext/mv6.C | 28 -- gcc/testsuite/g++.dg/ext/mv7.C | 12 - gcc/testsuite/g++.dg/ext/mv8.C | 7 - gcc/testsuite/g++.dg/ext/mv9.C | 9 - gcc/testsuite/g++.dg/ext/mvc1.C | 35 --- gcc/testsuite/g++.dg/ext/mvc2.C | 9 - gcc/testsuite/g++.dg/ext/mvc3.C | 9 - gcc/testsuite/g++.dg/ext/mvc4.C | 35 --- gcc/testsuite/g++.target/i386/i386.exp | 43 +++ gcc/testsuite/g++.target/i386/mv1.C | 132 +++++++++ gcc/testsuite/g++.target/i386/mv10.C | 12 + gcc/testsuite/g++.target/i386/mv11.C | 23 ++ gcc/testsuite/g++.target/i386/mv12-aux.cc | 10 + gcc/testsuite/g++.target/i386/mv12.C | 22 ++ gcc/testsuite/g++.target/i386/mv12.h | 4 + gcc/testsuite/g++.target/i386/mv13.C | 18 ++ gcc/testsuite/g++.target/i386/mv14.C | 40 +++ gcc/testsuite/g++.target/i386/mv15.C | 40 +++ gcc/testsuite/g++.target/i386/mv16.C | 101 +++++++ gcc/testsuite/g++.target/i386/mv17.C | 93 ++++++ gcc/testsuite/g++.target/i386/mv18.C | 7 + gcc/testsuite/g++.target/i386/mv19.C | 7 + gcc/testsuite/g++.target/i386/mv2.C | 127 ++++++++ gcc/testsuite/g++.target/i386/mv20.C | 7 + gcc/testsuite/g++.target/i386/mv21.C | 7 + gcc/testsuite/g++.target/i386/mv22.C | 7 + gcc/testsuite/g++.target/i386/mv23.C | 7 + gcc/testsuite/g++.target/i386/mv24.C | 35 +++ gcc/testsuite/g++.target/i386/mv25.C | 35 +++ gcc/testsuite/g++.target/i386/mv26.C | 15 + gcc/testsuite/g++.target/i386/mv27.C | 18 ++ gcc/testsuite/g++.target/i386/mv3.C | 36 +++ gcc/testsuite/g++.target/i386/mv4.C | 24 ++ gcc/testsuite/g++.target/i386/mv5.C | 25 ++ gcc/testsuite/g++.target/i386/mv6.C | 28 ++ gcc/testsuite/g++.target/i386/mv7.C | 12 + gcc/testsuite/g++.target/i386/mv8.C | 7 + gcc/testsuite/g++.target/i386/mv9.C | 9 + gcc/testsuite/g++.target/i386/mvc1.C | 35 +++ gcc/testsuite/g++.target/i386/mvc2.C | 9 + gcc/testsuite/g++.target/i386/mvc3.C | 9 + gcc/testsuite/g++.target/i386/mvc4.C | 35 +++ gcc/testsuite/gcc.target/i386/i386.exp | 471 ------------------------------ gcc/testsuite/lib/target-supports.exp | 470 +++++++++++++++++++++++++++++ 70 files changed, 1517 insertions(+), 1467 deletions(-) delete mode 100644 gcc/testsuite/g++.dg/ext/mv1.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv10.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv11.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv12-aux.cc delete mode 100644 gcc/testsuite/g++.dg/ext/mv12.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv12.h delete mode 100644 gcc/testsuite/g++.dg/ext/mv13.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv14.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv15.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv16.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv17.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv18.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv19.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv2.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv20.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv21.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv22.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv23.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv24.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv25.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv26.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv27.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv3.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv4.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv5.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv6.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv7.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv8.C delete mode 100644 gcc/testsuite/g++.dg/ext/mv9.C delete mode 100644 gcc/testsuite/g++.dg/ext/mvc1.C delete mode 100644 gcc/testsuite/g++.dg/ext/mvc2.C delete mode 100644 gcc/testsuite/g++.dg/ext/mvc3.C delete mode 100644 gcc/testsuite/g++.dg/ext/mvc4.C create mode 100644 gcc/testsuite/g++.target/i386/i386.exp create mode 100644 gcc/testsuite/g++.target/i386/mv1.C create mode 100644 gcc/testsuite/g++.target/i386/mv10.C create mode 100644 gcc/testsuite/g++.target/i386/mv11.C create mode 100644 gcc/testsuite/g++.target/i386/mv12-aux.cc create mode 100644 gcc/testsuite/g++.target/i386/mv12.C create mode 100644 gcc/testsuite/g++.target/i386/mv12.h create mode 100644 gcc/testsuite/g++.target/i386/mv13.C create mode 100644 gcc/testsuite/g++.target/i386/mv14.C create mode 100644 gcc/testsuite/g++.target/i386/mv15.C create mode 100644 gcc/testsuite/g++.target/i386/mv16.C create mode 100644 gcc/testsuite/g++.target/i386/mv17.C create mode 100644 gcc/testsuite/g++.target/i386/mv18.C create mode 100644 gcc/testsuite/g++.target/i386/mv19.C create mode 100644 gcc/testsuite/g++.target/i386/mv2.C create mode 100644 gcc/testsuite/g++.target/i386/mv20.C create mode 100644 gcc/testsuite/g++.target/i386/mv21.C create mode 100644 gcc/testsuite/g++.target/i386/mv22.C create mode 100644 gcc/testsuite/g++.target/i386/mv23.C create mode 100644 gcc/testsuite/g++.target/i386/mv24.C create mode 100644 gcc/testsuite/g++.target/i386/mv25.C create mode 100644 gcc/testsuite/g++.target/i386/mv26.C create mode 100644 gcc/testsuite/g++.target/i386/mv27.C create mode 100644 gcc/testsuite/g++.target/i386/mv3.C create mode 100644 gcc/testsuite/g++.target/i386/mv4.C create mode 100644 gcc/testsuite/g++.target/i386/mv5.C create mode 100644 gcc/testsuite/g++.target/i386/mv6.C create mode 100644 gcc/testsuite/g++.target/i386/mv7.C create mode 100644 gcc/testsuite/g++.target/i386/mv8.C create mode 100644 gcc/testsuite/g++.target/i386/mv9.C create mode 100644 gcc/testsuite/g++.target/i386/mvc1.C create mode 100644 gcc/testsuite/g++.target/i386/mvc2.C create mode 100644 gcc/testsuite/g++.target/i386/mvc3.C create mode 100644 gcc/testsuite/g++.target/i386/mvc4.C (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9d495d4..a4ee18f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2018-10-08 Martin Liska + + * gcc.target/i386/i386.exp: Move procedures to + target-supports.exp. + * g++.target/i386/i386.exp: New file. + * gcc.target/i386/mv*.C: Move here tests and remove + target filter in these tests. + 2018-10-08 Cesar Philippidis * gfortran.dg/contiguous_4.f90: Adjust. diff --git a/gcc/testsuite/g++.dg/ext/mv1.C b/gcc/testsuite/g++.dg/ext/mv1.C deleted file mode 100644 index 4eedbff..0000000 --- a/gcc/testsuite/g++.dg/ext/mv1.C +++ /dev/null @@ -1,132 +0,0 @@ -/* Test case to check if Multiversioning works. */ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-options "-O2 -fPIC" } */ - -#include - -/* Default version. */ -int foo (); // Extra declaration that is merged with the second one. -int foo () __attribute__ ((target("default"))); -/* The other versions of foo. Mix up the ordering and - check if the dispatching does it in the order of priority. */ -/* Check combination of target attributes. */ -int foo () __attribute__ ((target("arch=corei7,popcnt"))); -/* The target operands in this declaration and the definition are re-ordered. - This should still work. */ -int foo () __attribute__ ((target("ssse3,avx2"))); - -/* Check for all target attributes for which dispatchers are available. */ -/* Check arch= */ -int foo () __attribute__((target("arch=core2"))); -int foo () __attribute__((target("arch=corei7"))); -int foo () __attribute__((target("arch=atom"))); -/* Check ISAs */ -int foo () __attribute__((target("avx"))); -int foo () __attribute__ ((target("arch=core2,sse4.2"))); -/* Check more arch=. */ -int foo () __attribute__((target("arch=amdfam10"))); -int foo () __attribute__((target("arch=bdver1"))); -int foo () __attribute__((target("arch=bdver2"))); - -int (*p)() = &foo; -int main () -{ - int val = foo (); - assert (val == (*p)()); - - /* Check in the exact same order in which the dispatching - is expected to happen. */ - if (__builtin_cpu_is ("bdver1")) - assert (val == 1); - else if (__builtin_cpu_is ("bdver2")) - assert (val == 2); - else if (__builtin_cpu_supports ("avx2") - && __builtin_cpu_supports ("ssse3")) - assert (val == 3); - else if (__builtin_cpu_supports ("avx")) - assert (val == 4); - else if (__builtin_cpu_is ("corei7") - && __builtin_cpu_supports ("popcnt")) - assert (val == 5); - else if (__builtin_cpu_is ("corei7")) - assert (val == 6); - else if (__builtin_cpu_is ("amdfam10h")) - assert (val == 7); - else if (__builtin_cpu_is ("core2") - && __builtin_cpu_supports ("sse4.2")) - assert (val == 8); - else if (__builtin_cpu_is ("core2")) - assert (val == 9); - else if (__builtin_cpu_is ("atom")) - assert (val == 10); - else - assert (val == 0); - - return 0; -} - -int __attribute__ ((target("default"))) -foo () -{ - return 0; -} - -int __attribute__ ((target("arch=corei7,popcnt"))) -foo () -{ - return 5; -} -int __attribute__ ((target("avx2,ssse3"))) -foo () -{ - return 3; -} - -int __attribute__ ((target("arch=core2"))) -foo () -{ - return 9; -} - -int __attribute__ ((target("arch=corei7"))) -foo () -{ - return 6; -} - -int __attribute__ ((target("arch=atom"))) -foo () -{ - return 10; -} - -int __attribute__ ((target("avx"))) -foo () -{ - return 4; -} - -int __attribute__ ((target("arch=core2,sse4.2"))) -foo () -{ - return 8; -} - -int __attribute__ ((target("arch=amdfam10"))) -foo () -{ - return 7; -} - -int __attribute__ ((target("arch=bdver1"))) -foo () -{ - return 1; -} - -int __attribute__ ((target("arch=bdver2"))) -foo () -{ - return 2; -} diff --git a/gcc/testsuite/g++.dg/ext/mv10.C b/gcc/testsuite/g++.dg/ext/mv10.C deleted file mode 100644 index 5dfe363..0000000 --- a/gcc/testsuite/g++.dg/ext/mv10.C +++ /dev/null @@ -1,12 +0,0 @@ -// { dg-do assemble { target i?86-*-* x86_64-*-* } } -// { dg-options "" } - -__attribute__((target ("popcnt"), used)) -void foo (void) -{ -} - -__attribute__((target ("popcnt","avx"), used)) -void foo (void) -{ -} diff --git a/gcc/testsuite/g++.dg/ext/mv11.C b/gcc/testsuite/g++.dg/ext/mv11.C deleted file mode 100644 index 1f5c576..0000000 --- a/gcc/testsuite/g++.dg/ext/mv11.C +++ /dev/null @@ -1,23 +0,0 @@ -// { dg-do compile { target i?86-*-* x86_64-*-* } } -// { dg-options "-msse2" } - -int foo () __attribute__ ((target("default"))); -int foo () __attribute__ ((target("sse2"))); - -int -main () -{ - return foo (); -} - -int __attribute__ ((target("default"))) -foo () -{ - return 0; -} - -int __attribute__ ((target("sse2"))) -foo () -{ - return 0; -} diff --git a/gcc/testsuite/g++.dg/ext/mv12-aux.cc b/gcc/testsuite/g++.dg/ext/mv12-aux.cc deleted file mode 100644 index 611c679..0000000 --- a/gcc/testsuite/g++.dg/ext/mv12-aux.cc +++ /dev/null @@ -1,10 +0,0 @@ -// Test case to check if multiversioning works as expected when the versions -// are defined in different files. Auxiliary file for mv12.C. - -#include "mv12.h" - -__attribute__ ((target ("sse4.2"))) -int foo () -{ - return 1; -} diff --git a/gcc/testsuite/g++.dg/ext/mv12.C b/gcc/testsuite/g++.dg/ext/mv12.C deleted file mode 100644 index 8b2e423..0000000 --- a/gcc/testsuite/g++.dg/ext/mv12.C +++ /dev/null @@ -1,22 +0,0 @@ -// Test case to check if multiversioning works as expected when the versions -// are defined in different files. - -// { dg-do run { target i?86-*-* x86_64-*-* } } -// { dg-require-ifunc "" } -// { dg-options "-O2" } -// { dg-additional-sources "mv12-aux.cc" } - -#include "mv12.h" - -int main () -{ - if (__builtin_cpu_supports ("sse4.2")) - return foo () - 1; - return foo (); -} - -__attribute__ ((target ("default"))) -int foo () -{ - return 0; -} diff --git a/gcc/testsuite/g++.dg/ext/mv12.h b/gcc/testsuite/g++.dg/ext/mv12.h deleted file mode 100644 index 650358d..0000000 --- a/gcc/testsuite/g++.dg/ext/mv12.h +++ /dev/null @@ -1,4 +0,0 @@ -// Header file used by mv12.C and mv12-aux.cc. - -int foo () __attribute__ ((target ("default"))); -int foo () __attribute__ ((target ("sse4.2"))); diff --git a/gcc/testsuite/g++.dg/ext/mv13.C b/gcc/testsuite/g++.dg/ext/mv13.C deleted file mode 100644 index 5674d19..0000000 --- a/gcc/testsuite/g++.dg/ext/mv13.C +++ /dev/null @@ -1,18 +0,0 @@ -// Test case to check if multiversioning functions that are extern "C" -// generates errors. - -// { dg-do compile { target i?86-*-* x86_64-*-* } } - -extern "C" -__attribute__ ((target ("default"))) -int foo () // { dg-message "previously defined here" } -{ - return 0; -} - -extern "C" -__attribute__ ((target ("sse4.2"))) -int foo () // { dg-error "redefinition" } -{ - return 1; -} diff --git a/gcc/testsuite/g++.dg/ext/mv14.C b/gcc/testsuite/g++.dg/ext/mv14.C deleted file mode 100644 index 1e7a161..0000000 --- a/gcc/testsuite/g++.dg/ext/mv14.C +++ /dev/null @@ -1,40 +0,0 @@ -/* Test case to check if Multiversioning works. */ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-options "-O2 -fPIC -march=x86-64" } */ - -#include - -/* Default version. */ -int foo (); // Extra declaration that is merged with the second one. -int foo () __attribute__ ((target("default"))); - -int foo () __attribute__ ((target("arch=corei7"))); - -int (*p)() = &foo; -int main () -{ - int val = foo (); - assert (val == (*p)()); - - /* Check in the exact same order in which the dispatching - is expected to happen. */ - if (__builtin_cpu_is ("corei7")) - assert (val == 5); - else - assert (val == 0); - - return 0; -} - -int __attribute__ ((target("default"))) -foo () -{ - return 0; -} - -int __attribute__ ((target("arch=corei7"))) -foo () -{ - return 5; -} diff --git a/gcc/testsuite/g++.dg/ext/mv15.C b/gcc/testsuite/g++.dg/ext/mv15.C deleted file mode 100644 index c0beadf..0000000 --- a/gcc/testsuite/g++.dg/ext/mv15.C +++ /dev/null @@ -1,40 +0,0 @@ -/* Test case to check if Multiversioning works. */ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-options "-O2 -fPIC -march=x86-64" } */ - -#include - -/* Default version. */ -int foo (); // Extra declaration that is merged with the second one. -int foo () __attribute__ ((target("default"))); - -int foo () __attribute__ ((target("arch=nehalem"))); - -int (*p)() = &foo; -int main () -{ - int val = foo (); - assert (val == (*p)()); - - /* Check in the exact same order in which the dispatching - is expected to happen. */ - if (__builtin_cpu_is ("corei7")) - assert (val == 5); - else - assert (val == 0); - - return 0; -} - -int __attribute__ ((target("default"))) -foo () -{ - return 0; -} - -int __attribute__ ((target("arch=nehalem"))) -foo () -{ - return 5; -} diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C deleted file mode 100644 index 3e7c228..0000000 --- a/gcc/testsuite/g++.dg/ext/mv16.C +++ /dev/null @@ -1,101 +0,0 @@ -// Test that dispatching can choose the right multiversion -// for Intel CPUs with the same internal GCC processor id -// but slighly different sets of x86 extensions. - -// { dg-do run { target i?86-*-* x86_64-*-* } } -// { dg-require-ifunc "" } -// { dg-options "-O2" } - -#include - -int __attribute__ ((target("default"))) -foo () -{ - return 0; -} - -int __attribute__ ((target("arch=nehalem"))) -foo () -{ - return 4; -} - -int __attribute__ ((target("arch=westmere"))) -foo () -{ - return 5; -} - -int __attribute__ ((target("arch=sandybridge"))) -foo () -{ - return 8; -} - -int __attribute__ ((target("arch=ivybridge"))) -foo () -{ - return 9; -} - -int __attribute__ ((target("arch=haswell"))) -foo () -{ - return 12; -} - -int __attribute__ ((target("arch=broadwell"))) foo () { - return 13; -} - -int __attribute__ ((target("arch=skylake"))) foo () { - return 14; -} - -int __attribute__ ((target("arch=skylake-avx512"))) foo () { - return 15; -} - -int __attribute__ ((target("arch=cannonlake"))) foo () { - return 16; -} - -int __attribute__ ((target("arch=icelake-client"))) foo () { - return 17; -} - -int __attribute__ ((target("arch=icelake-server"))) foo () { - return 18; -} - -int main () -{ - int val = foo (); - - if (__builtin_cpu_is ("nehalem")) - assert (val == 4); - else if (__builtin_cpu_is ("westmere")) - assert (val == 5); - else if (__builtin_cpu_is ("sandybridge")) - assert (val == 8); - else if (__builtin_cpu_is ("ivybridge")) - assert (val == 9); - else if (__builtin_cpu_is ("haswell")) - assert (val == 12); - else if (__builtin_cpu_is ("broadwell")) - assert (val == 13); - else if (__builtin_cpu_is ("skylake")) - assert (val == 14); - else if (__builtin_cpu_is ("skylake-avx512")) - assert (val == 15); - else if (__builtin_cpu_is ("cannonlake")) - assert (val == 16); - else if (__builtin_cpu_is ("icelake-client")) - assert (val == 17); - else if (__builtin_cpu_is ("icelake-server")) - assert (val == 18); - else - assert (val == 0); - - return 0; -} diff --git a/gcc/testsuite/g++.dg/ext/mv17.C b/gcc/testsuite/g++.dg/ext/mv17.C deleted file mode 100644 index 87c1324..0000000 --- a/gcc/testsuite/g++.dg/ext/mv17.C +++ /dev/null @@ -1,93 +0,0 @@ -// Test case to check if Multiversioning works for BMI and BMI2. - -// { dg-do run { target i?86-*-* x86_64-*-* } } -// { dg-require-ifunc "" } -// { dg-options "-O2" } - -#include - -// Check BMI feature selection works -int foo () __attribute__((target("default"))); -int foo () __attribute__((target("bmi"))); -int foo () __attribute__((target("bmi2"))); - -// Check specialized versions for archs with BMI is chosen over generic BMI versions. -int bar () __attribute__((target("default"))); -int bar () __attribute__((target("bmi"))); -int bar () __attribute__((target("bmi2"))); -int bar () __attribute__((target("arch=btver2"))); -int bar () __attribute__((target("arch=haswell"))); - -int main () -{ - int val = foo (); - - if (__builtin_cpu_supports ("bmi2")) - assert (val == 2); - else if (__builtin_cpu_supports ("bmi")) - assert (val == 1); - else - assert (val == 0); - - val = bar (); - - if (__builtin_cpu_is ("btver2")) - assert (val == 5); - else if (__builtin_cpu_is ("haswell")) - assert (val == 6); - else if (__builtin_cpu_supports ("bmi2")) - assert (val == 2); - else if (__builtin_cpu_supports ("bmi")) - assert (val == 1); - else - assert (val == 0); - - return 0; -} - -int __attribute__ ((target("default"))) -foo () -{ - return 0; -} - -int __attribute__ ((target("bmi"))) -foo () -{ - return 1; -} -int __attribute__ ((target("bmi2"))) -foo () -{ - return 2; -} - -int __attribute__ ((target("default"))) -bar () -{ - return 0; -} - -int __attribute__ ((target("bmi"))) -bar () -{ - return 1; -} -int __attribute__ ((target("bmi2"))) -bar () -{ - return 2; -} - -int __attribute__ ((target("arch=btver2"))) -bar () -{ - return 5; -} - -int __attribute__ ((target("arch=haswell"))) -bar () -{ - return 6; -} - diff --git a/gcc/testsuite/g++.dg/ext/mv18.C b/gcc/testsuite/g++.dg/ext/mv18.C deleted file mode 100644 index 1f024de..0000000 --- a/gcc/testsuite/g++.dg/ext/mv18.C +++ /dev/null @@ -1,7 +0,0 @@ -/* Test case to check if Multiversioning works. */ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-require-effective-target pie } */ -/* { dg-options "-O2 -fPIE -pie" } */ - -#include "mv1.C" diff --git a/gcc/testsuite/g++.dg/ext/mv19.C b/gcc/testsuite/g++.dg/ext/mv19.C deleted file mode 100644 index d1ea788..0000000 --- a/gcc/testsuite/g++.dg/ext/mv19.C +++ /dev/null @@ -1,7 +0,0 @@ -/* Test case to check if Multiversioning works. */ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-require-effective-target pie } */ -/* { dg-options "-O2 -fPIE -pie -march=x86-64" } */ - -#include "mv14.C" diff --git a/gcc/testsuite/g++.dg/ext/mv2.C b/gcc/testsuite/g++.dg/ext/mv2.C deleted file mode 100644 index d4f1f92..0000000 --- a/gcc/testsuite/g++.dg/ext/mv2.C +++ /dev/null @@ -1,127 +0,0 @@ -/* Test case to check if Multiversioning chooses the correct - dispatching order when versions are for various ISAs. */ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-options "-O2" } */ - -#include - -/* Default version. */ -int foo () __attribute__ ((target ("default"))); -/* The dispatch checks should be in the exact reverse order of the - declarations below. */ -int foo () __attribute__ ((target ("mmx"))); -int foo () __attribute__ ((target ("sse"))); -int foo () __attribute__ ((target ("sse2"))); -int foo () __attribute__ ((target ("sse3"))); -int foo () __attribute__ ((target ("ssse3"))); -int foo () __attribute__ ((target ("sse4.1"))); -int foo () __attribute__ ((target ("sse4.2"))); -int foo () __attribute__ ((target ("popcnt"))); -int foo () __attribute__ ((target ("avx"))); -int foo () __attribute__ ((target ("avx2"))); -int foo () __attribute__ ((target ("avx512f"))); - -int main () -{ - int val = foo (); - - if (__builtin_cpu_supports ("avx512f")) - assert (val == 11); - else if (__builtin_cpu_supports ("avx2")) - assert (val == 10); - else if (__builtin_cpu_supports ("avx")) - assert (val == 9); - else if (__builtin_cpu_supports ("popcnt")) - assert (val == 8); - else if (__builtin_cpu_supports ("sse4.2")) - assert (val == 7); - else if (__builtin_cpu_supports ("sse4.1")) - assert (val == 6); - else if (__builtin_cpu_supports ("ssse3")) - assert (val == 5); - else if (__builtin_cpu_supports ("sse3")) - assert (val == 4); - else if (__builtin_cpu_supports ("sse2")) - assert (val == 3); - else if (__builtin_cpu_supports ("sse")) - assert (val == 2); - else if (__builtin_cpu_supports ("mmx")) - assert (val == 1); - else - assert (val == 0); - - return 0; -} - -int __attribute__ ((target("default"))) -foo () -{ - return 0; -} - -int __attribute__ ((target("mmx"))) -foo () -{ - return 1; -} - -int __attribute__ ((target("sse"))) -foo () -{ - return 2; -} - -int __attribute__ ((target("sse2"))) -foo () -{ - return 3; -} - -int __attribute__ ((target("sse3"))) -foo () -{ - return 4; -} - -int __attribute__ ((target("ssse3"))) -foo () -{ - return 5; -} - -int __attribute__ ((target("sse4.1"))) -foo () -{ - return 6; -} - -int __attribute__ ((target("sse4.2"))) -foo () -{ - return 7; -} - -int __attribute__ ((target("popcnt"))) -foo () -{ - return 8; -} - -int __attribute__ ((target("avx"))) -foo () -{ - return 9; -} - -int __attribute__ ((target("avx2"))) -foo () -{ - return 10; -} - -int __attribute__ ((target("avx512f"))) -foo () -{ - return 11; -} diff --git a/gcc/testsuite/g++.dg/ext/mv20.C b/gcc/testsuite/g++.dg/ext/mv20.C deleted file mode 100644 index 98f7408..0000000 --- a/gcc/testsuite/g++.dg/ext/mv20.C +++ /dev/null @@ -1,7 +0,0 @@ -/* Test case to check if Multiversioning works. */ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-require-effective-target pie } */ -/* { dg-options "-O2 -fPIE -pie -march=x86-64" } */ - -#include "mv15.C" diff --git a/gcc/testsuite/g++.dg/ext/mv21.C b/gcc/testsuite/g++.dg/ext/mv21.C deleted file mode 100644 index 9708ad9..0000000 --- a/gcc/testsuite/g++.dg/ext/mv21.C +++ /dev/null @@ -1,7 +0,0 @@ -/* Test case to check if Multiversioning works. */ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-require-effective-target static } */ -/* { dg-options "-O2 -static" } */ - -#include "mv1.C" diff --git a/gcc/testsuite/g++.dg/ext/mv22.C b/gcc/testsuite/g++.dg/ext/mv22.C deleted file mode 100644 index 2550136..0000000 --- a/gcc/testsuite/g++.dg/ext/mv22.C +++ /dev/null @@ -1,7 +0,0 @@ -/* Test case to check if Multiversioning works. */ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-require-effective-target static } */ -/* { dg-options "-O2 -static -march=x86-64" } */ - -#include "mv14.C" diff --git a/gcc/testsuite/g++.dg/ext/mv23.C b/gcc/testsuite/g++.dg/ext/mv23.C deleted file mode 100644 index f00afb0..0000000 --- a/gcc/testsuite/g++.dg/ext/mv23.C +++ /dev/null @@ -1,7 +0,0 @@ -/* Test case to check if Multiversioning works. */ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-require-effective-target static } */ -/* { dg-options "-O2 -static -march=x86-64" } */ - -#include "mv15.C" diff --git a/gcc/testsuite/g++.dg/ext/mv24.C b/gcc/testsuite/g++.dg/ext/mv24.C deleted file mode 100644 index 58292a8..0000000 --- a/gcc/testsuite/g++.dg/ext/mv24.C +++ /dev/null @@ -1,35 +0,0 @@ -// Test case to check if Multiversioning works for AES - -// { dg-do run { target i?86-*-* x86_64-*-* } } -// { dg-require-ifunc "" } -// { dg-options "-O2" } - -#include - -// Check if AES feature selection works -int foo () __attribute__((target("default"))); -int foo () __attribute__((target("aes"))); - -int main () -{ - int val = foo (); - - if (__builtin_cpu_supports ("aes")) - assert (val == 1); - else - assert (val == 0); - - return 0; -} - -int __attribute__ ((target("default"))) -foo () -{ - return 0; -} - -int __attribute__ ((target("aes"))) -foo () -{ - return 1; -} diff --git a/gcc/testsuite/g++.dg/ext/mv25.C b/gcc/testsuite/g++.dg/ext/mv25.C deleted file mode 100644 index fd40eca..0000000 --- a/gcc/testsuite/g++.dg/ext/mv25.C +++ /dev/null @@ -1,35 +0,0 @@ -// Test case to check if Multiversioning works for PCLMUL - -// { dg-do run { target i?86-*-* x86_64-*-* } } -// { dg-require-ifunc "" } -// { dg-options "-O2" } - -#include - -// Check if PCLMUL feature selection works -int foo () __attribute__((target("default"))); -int foo () __attribute__((target("pclmul"))); - -int main () -{ - int val = foo (); - - if (__builtin_cpu_supports ("pclmul")) - assert (val == 1); - else - assert (val == 0); - - return 0; -} - -int __attribute__ ((target("default"))) -foo () -{ - return 0; -} - -int __attribute__ ((target("pclmul"))) -foo () -{ - return 1; -} diff --git a/gcc/testsuite/g++.dg/ext/mv26.C b/gcc/testsuite/g++.dg/ext/mv26.C deleted file mode 100644 index 1b45513..0000000 --- a/gcc/testsuite/g++.dg/ext/mv26.C +++ /dev/null @@ -1,15 +0,0 @@ -// PR c++/84059 -// { dg-do compile { target i?86-*-* x86_64-*-* } } -// { dg-require-ifunc "" } - -template struct a -{ - int __attribute__ ((target ("arch=ivybridge"))) c (int) {return 1;} - int __attribute__ ((target ("default"))) c (int) { return 2; } -}; -void -d () -{ - a b; - b.c (2); -} diff --git a/gcc/testsuite/g++.dg/ext/mv27.C b/gcc/testsuite/g++.dg/ext/mv27.C deleted file mode 100644 index 443a54b..0000000 --- a/gcc/testsuite/g++.dg/ext/mv27.C +++ /dev/null @@ -1,18 +0,0 @@ -// PR c++/83911 -// { dg-do compile { target i?86-*-* x86_64-*-* } } -// { dg-require-ifunc "" } - -class SimdFloat -{ -public: - __attribute__ ((target ("default"))) - SimdFloat(float x) {} - - __attribute__ ((target ("avx2"))) - SimdFloat(float x) {} -}; - -SimdFloat foo() -{ - return 1; -} diff --git a/gcc/testsuite/g++.dg/ext/mv3.C b/gcc/testsuite/g++.dg/ext/mv3.C deleted file mode 100644 index ec2aa1f..0000000 --- a/gcc/testsuite/g++.dg/ext/mv3.C +++ /dev/null @@ -1,36 +0,0 @@ -/* Test case to check if a call to a multiversioned function - is replaced with a direct call to the particular version when - the most specialized version's target attributes match the - caller. - - In this program, foo is multiversioned but there is no default - function. This is an error if the call has to go through a - dispatcher. However, the call to foo in bar can be replaced - with a direct call to the popcnt version of foo. Hence, this - test should pass. */ - -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O2" } */ - - -int __attribute__ ((target ("sse"))) -foo () -{ - return 1; -} -int __attribute__ ((target ("popcnt"))) -foo () -{ - return 0; -} - -int __attribute__ ((target ("popcnt"))) -bar () -{ - return foo (); -} - -int main () -{ - return bar (); -} diff --git a/gcc/testsuite/g++.dg/ext/mv4.C b/gcc/testsuite/g++.dg/ext/mv4.C deleted file mode 100644 index ff1cc2f..0000000 --- a/gcc/testsuite/g++.dg/ext/mv4.C +++ /dev/null @@ -1,24 +0,0 @@ -/* Test case to check if the compiler generates an error message - when the default version of a multiversioned function is absent - and its pointer is taken. */ - -/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-options "-O2" } */ - -int __attribute__ ((target ("sse"))) -foo () -{ - return 1; -} -int __attribute__ ((target ("popcnt"))) -foo () -{ - return 0; -} - -int main () -{ - int (*p)() = &foo; /* { dg-error "use of multiversioned function without a default" {} } */ - return (*p)(); -} diff --git a/gcc/testsuite/g++.dg/ext/mv5.C b/gcc/testsuite/g++.dg/ext/mv5.C deleted file mode 100644 index fd62eee..0000000 --- a/gcc/testsuite/g++.dg/ext/mv5.C +++ /dev/null @@ -1,25 +0,0 @@ -/* Test case to check if multiversioned functions are still generated if they are - marked comdat with inline keyword. */ - -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-options "-O2" } */ - - -/* Default version. */ -inline int __attribute__ ((target ("default"))) -foo () -{ - return 0; -} - -inline int __attribute__ ((target ("popcnt"))) -foo () -{ - return 0; -} - -int main () -{ - return foo (); -} diff --git a/gcc/testsuite/g++.dg/ext/mv6.C b/gcc/testsuite/g++.dg/ext/mv6.C deleted file mode 100644 index 2273065..0000000 --- a/gcc/testsuite/g++.dg/ext/mv6.C +++ /dev/null @@ -1,28 +0,0 @@ -/* Test to check if member version multiversioning works correctly. */ - -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-options "-march=x86-64" } */ - -class Foo -{ - public: - /* Default version of foo. */ - __attribute__ ((target("default"))) - int foo () - { - return 0; - } - /* corei7 version of foo. */ - __attribute__ ((target("arch=corei7"))) - int foo () - { - return 0; - } -}; - -int main () -{ - Foo f; - return f.foo (); -} diff --git a/gcc/testsuite/g++.dg/ext/mv7.C b/gcc/testsuite/g++.dg/ext/mv7.C deleted file mode 100644 index 64c04fa..0000000 --- a/gcc/testsuite/g++.dg/ext/mv7.C +++ /dev/null @@ -1,12 +0,0 @@ -// { dg-do compile { target i?86-*-* x86_64-*-* } } -// { dg-options "" } - -__attribute__((target ("default"))) -void foo (void) // { dg-message "previously defined here" } -{ -} - -__attribute__((target (128))) -void foo (void) // { dg-error "(not a string|redefinition)" } -{ -} diff --git a/gcc/testsuite/g++.dg/ext/mv8.C b/gcc/testsuite/g++.dg/ext/mv8.C deleted file mode 100644 index b49ef84..0000000 --- a/gcc/testsuite/g++.dg/ext/mv8.C +++ /dev/null @@ -1,7 +0,0 @@ -// { dg-do compile { target i?86-*-* x86_64-*-* powerpc*-*-* aarch64*-*-* } } -// { dg-options "" } - -__attribute__((target (11,12))) -void foo (void) // { dg-error "not a string" } -{ -} diff --git a/gcc/testsuite/g++.dg/ext/mv9.C b/gcc/testsuite/g++.dg/ext/mv9.C deleted file mode 100644 index c59651e..0000000 --- a/gcc/testsuite/g++.dg/ext/mv9.C +++ /dev/null @@ -1,9 +0,0 @@ -// { dg-do compile { target i?86-*-* x86_64-*-* } } -// { dg-options "" } - -void foo (); -void foo () __attribute__((target ("sse4"))); -void foo () __attribute__((target ("default"))); // { dg-message "previous declaration" } -void foo () // { dg-error "attribute for multi-versioned" } -{ -} diff --git a/gcc/testsuite/g++.dg/ext/mvc1.C b/gcc/testsuite/g++.dg/ext/mvc1.C deleted file mode 100644 index ff37238..0000000 --- a/gcc/testsuite/g++.dg/ext/mvc1.C +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do run { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ - -__attribute__((target_clones("avx","arch=slm","arch=core-avx2","default"))) -int -foo () -{ - return -2; -} - -__attribute__((target("avx","arch=core-avx2"))) -int -bar () -{ - return 2; -} - -__attribute__((target("default"))) -int -bar () -{ - return 2; -} - -int -main () -{ - int r = 0; - r += bar (); - r += foo (); - r += bar (); - r += foo (); - r += bar (); - return r - 2; -} diff --git a/gcc/testsuite/g++.dg/ext/mvc2.C b/gcc/testsuite/g++.dg/ext/mvc2.C deleted file mode 100644 index 1b8c6f4d..0000000 --- a/gcc/testsuite/g++.dg/ext/mvc2.C +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ - -__attribute__((target_clones("avx","arch=slm","default"))) -__attribute__((target("avx"))) -int foo (); /* { dg-warning "'target' attribute ignored due to conflict with 'target_clones' attribute" } */ - -__attribute__((target_clones("avx","arch=slm","default"),always_inline)) -int bar (); /* { dg-warning "'always_inline' attribute ignored due to conflict with 'target_clones' attribute" } */ diff --git a/gcc/testsuite/g++.dg/ext/mvc3.C b/gcc/testsuite/g++.dg/ext/mvc3.C deleted file mode 100644 index d32b2c9..0000000 --- a/gcc/testsuite/g++.dg/ext/mvc3.C +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ - -__attribute__((target("avx"))) -__attribute__((target_clones("avx","arch=slm","default"))) -int foo (); /* { dg-warning "'target_clones' attribute ignored due to conflict with 'target' attribute" } */ - -__attribute__((always_inline,target_clones("avx","arch=slm","default"))) -int bar (); /* { dg-warning "'target_clones' attribute ignored due to conflict with 'always_inline' attribute" } */ diff --git a/gcc/testsuite/g++.dg/ext/mvc4.C b/gcc/testsuite/g++.dg/ext/mvc4.C deleted file mode 100644 index 6e18e56..0000000 --- a/gcc/testsuite/g++.dg/ext/mvc4.C +++ /dev/null @@ -1,35 +0,0 @@ -/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-require-ifunc "" } */ -/* { dg-options "-mavx" } */ - -#include - -__m256 x, y, z; - -__attribute__((target("avx"))) -int bar() -{ - x = _mm256_add_ps (y, z); - return 1; -} - -__attribute__((target("default"))) -int bar() -{ - return 2; -} - -int -foobar() -{ - if (__builtin_cpu_supports ("avx")) - return bar(); - else - return 0; -} - -__attribute__((target_clones("default","sse3"))) -int foo() -{ - return foobar(); -} diff --git a/gcc/testsuite/g++.target/i386/i386.exp b/gcc/testsuite/g++.target/i386/i386.exp new file mode 100644 index 0000000..76a7e53 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/i386.exp @@ -0,0 +1,43 @@ +# Copyright (C) 2018 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `g++.exp' driver. + +# Exit immediately if this isn't a x86 target. +if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then { + return +} + +# Load support procs. +load_lib g++-dg.exp +load_lib clearcap.exp + +global DEFAULT_CXXFLAGS +if ![info exists DEFAULT_CXXFLAGS] then { + set DEFAULT_CXXFLAGS " -pedantic-errors" +} + +# Initialize `dg'. +dg-init +clearcap-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.C]] \ + "" $DEFAULT_CXXFLAGS + +# All done. +clearcap-finish +dg-finish diff --git a/gcc/testsuite/g++.target/i386/mv1.C b/gcc/testsuite/g++.target/i386/mv1.C new file mode 100644 index 0000000..fc71347 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv1.C @@ -0,0 +1,132 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-O2 -fPIC" } */ + +#include + +/* Default version. */ +int foo (); // Extra declaration that is merged with the second one. +int foo () __attribute__ ((target("default"))); +/* The other versions of foo. Mix up the ordering and + check if the dispatching does it in the order of priority. */ +/* Check combination of target attributes. */ +int foo () __attribute__ ((target("arch=corei7,popcnt"))); +/* The target operands in this declaration and the definition are re-ordered. + This should still work. */ +int foo () __attribute__ ((target("ssse3,avx2"))); + +/* Check for all target attributes for which dispatchers are available. */ +/* Check arch= */ +int foo () __attribute__((target("arch=core2"))); +int foo () __attribute__((target("arch=corei7"))); +int foo () __attribute__((target("arch=atom"))); +/* Check ISAs */ +int foo () __attribute__((target("avx"))); +int foo () __attribute__ ((target("arch=core2,sse4.2"))); +/* Check more arch=. */ +int foo () __attribute__((target("arch=amdfam10"))); +int foo () __attribute__((target("arch=bdver1"))); +int foo () __attribute__((target("arch=bdver2"))); + +int (*p)() = &foo; +int main () +{ + int val = foo (); + assert (val == (*p)()); + + /* Check in the exact same order in which the dispatching + is expected to happen. */ + if (__builtin_cpu_is ("bdver1")) + assert (val == 1); + else if (__builtin_cpu_is ("bdver2")) + assert (val == 2); + else if (__builtin_cpu_supports ("avx2") + && __builtin_cpu_supports ("ssse3")) + assert (val == 3); + else if (__builtin_cpu_supports ("avx")) + assert (val == 4); + else if (__builtin_cpu_is ("corei7") + && __builtin_cpu_supports ("popcnt")) + assert (val == 5); + else if (__builtin_cpu_is ("corei7")) + assert (val == 6); + else if (__builtin_cpu_is ("amdfam10h")) + assert (val == 7); + else if (__builtin_cpu_is ("core2") + && __builtin_cpu_supports ("sse4.2")) + assert (val == 8); + else if (__builtin_cpu_is ("core2")) + assert (val == 9); + else if (__builtin_cpu_is ("atom")) + assert (val == 10); + else + assert (val == 0); + + return 0; +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("arch=corei7,popcnt"))) +foo () +{ + return 5; +} +int __attribute__ ((target("avx2,ssse3"))) +foo () +{ + return 3; +} + +int __attribute__ ((target("arch=core2"))) +foo () +{ + return 9; +} + +int __attribute__ ((target("arch=corei7"))) +foo () +{ + return 6; +} + +int __attribute__ ((target("arch=atom"))) +foo () +{ + return 10; +} + +int __attribute__ ((target("avx"))) +foo () +{ + return 4; +} + +int __attribute__ ((target("arch=core2,sse4.2"))) +foo () +{ + return 8; +} + +int __attribute__ ((target("arch=amdfam10"))) +foo () +{ + return 7; +} + +int __attribute__ ((target("arch=bdver1"))) +foo () +{ + return 1; +} + +int __attribute__ ((target("arch=bdver2"))) +foo () +{ + return 2; +} diff --git a/gcc/testsuite/g++.target/i386/mv10.C b/gcc/testsuite/g++.target/i386/mv10.C new file mode 100644 index 0000000..07fbd0e --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv10.C @@ -0,0 +1,12 @@ +// { dg-do assemble } +// { dg-options "" } + +__attribute__((target ("popcnt"), used)) +void foo (void) +{ +} + +__attribute__((target ("popcnt","avx"), used)) +void foo (void) +{ +} diff --git a/gcc/testsuite/g++.target/i386/mv11.C b/gcc/testsuite/g++.target/i386/mv11.C new file mode 100644 index 0000000..58aaf50 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv11.C @@ -0,0 +1,23 @@ +// { dg-do compile } +// { dg-options "-msse2" } + +int foo () __attribute__ ((target("default"))); +int foo () __attribute__ ((target("sse2"))); + +int +main () +{ + return foo (); +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("sse2"))) +foo () +{ + return 0; +} diff --git a/gcc/testsuite/g++.target/i386/mv12-aux.cc b/gcc/testsuite/g++.target/i386/mv12-aux.cc new file mode 100644 index 0000000..611c679 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv12-aux.cc @@ -0,0 +1,10 @@ +// Test case to check if multiversioning works as expected when the versions +// are defined in different files. Auxiliary file for mv12.C. + +#include "mv12.h" + +__attribute__ ((target ("sse4.2"))) +int foo () +{ + return 1; +} diff --git a/gcc/testsuite/g++.target/i386/mv12.C b/gcc/testsuite/g++.target/i386/mv12.C new file mode 100644 index 0000000..2156962 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv12.C @@ -0,0 +1,22 @@ +// Test case to check if multiversioning works as expected when the versions +// are defined in different files. + +// { dg-do run } +// { dg-require-ifunc "" } +// { dg-options "-O2" } +// { dg-additional-sources "mv12-aux.cc" } + +#include "mv12.h" + +int main () +{ + if (__builtin_cpu_supports ("sse4.2")) + return foo () - 1; + return foo (); +} + +__attribute__ ((target ("default"))) +int foo () +{ + return 0; +} diff --git a/gcc/testsuite/g++.target/i386/mv12.h b/gcc/testsuite/g++.target/i386/mv12.h new file mode 100644 index 0000000..650358d --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv12.h @@ -0,0 +1,4 @@ +// Header file used by mv12.C and mv12-aux.cc. + +int foo () __attribute__ ((target ("default"))); +int foo () __attribute__ ((target ("sse4.2"))); diff --git a/gcc/testsuite/g++.target/i386/mv13.C b/gcc/testsuite/g++.target/i386/mv13.C new file mode 100644 index 0000000..39d05c7 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv13.C @@ -0,0 +1,18 @@ +// Test case to check if multiversioning functions that are extern "C" +// generates errors. + +// { dg-do compile } + +extern "C" +__attribute__ ((target ("default"))) +int foo () // { dg-message "previously defined here" } +{ + return 0; +} + +extern "C" +__attribute__ ((target ("sse4.2"))) +int foo () // { dg-error "redefinition" } +{ + return 1; +} diff --git a/gcc/testsuite/g++.target/i386/mv14.C b/gcc/testsuite/g++.target/i386/mv14.C new file mode 100644 index 0000000..ccebb33 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv14.C @@ -0,0 +1,40 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-O2 -fPIC -march=x86-64" } */ + +#include + +/* Default version. */ +int foo (); // Extra declaration that is merged with the second one. +int foo () __attribute__ ((target("default"))); + +int foo () __attribute__ ((target("arch=corei7"))); + +int (*p)() = &foo; +int main () +{ + int val = foo (); + assert (val == (*p)()); + + /* Check in the exact same order in which the dispatching + is expected to happen. */ + if (__builtin_cpu_is ("corei7")) + assert (val == 5); + else + assert (val == 0); + + return 0; +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("arch=corei7"))) +foo () +{ + return 5; +} diff --git a/gcc/testsuite/g++.target/i386/mv15.C b/gcc/testsuite/g++.target/i386/mv15.C new file mode 100644 index 0000000..4e867f2 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv15.C @@ -0,0 +1,40 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-O2 -fPIC -march=x86-64" } */ + +#include + +/* Default version. */ +int foo (); // Extra declaration that is merged with the second one. +int foo () __attribute__ ((target("default"))); + +int foo () __attribute__ ((target("arch=nehalem"))); + +int (*p)() = &foo; +int main () +{ + int val = foo (); + assert (val == (*p)()); + + /* Check in the exact same order in which the dispatching + is expected to happen. */ + if (__builtin_cpu_is ("corei7")) + assert (val == 5); + else + assert (val == 0); + + return 0; +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("arch=nehalem"))) +foo () +{ + return 5; +} diff --git a/gcc/testsuite/g++.target/i386/mv16.C b/gcc/testsuite/g++.target/i386/mv16.C new file mode 100644 index 0000000..1091868 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv16.C @@ -0,0 +1,101 @@ +// Test that dispatching can choose the right multiversion +// for Intel CPUs with the same internal GCC processor id +// but slighly different sets of x86 extensions. + +// { dg-do run } +// { dg-require-ifunc "" } +// { dg-options "-O2" } + +#include + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("arch=nehalem"))) +foo () +{ + return 4; +} + +int __attribute__ ((target("arch=westmere"))) +foo () +{ + return 5; +} + +int __attribute__ ((target("arch=sandybridge"))) +foo () +{ + return 8; +} + +int __attribute__ ((target("arch=ivybridge"))) +foo () +{ + return 9; +} + +int __attribute__ ((target("arch=haswell"))) +foo () +{ + return 12; +} + +int __attribute__ ((target("arch=broadwell"))) foo () { + return 13; +} + +int __attribute__ ((target("arch=skylake"))) foo () { + return 14; +} + +int __attribute__ ((target("arch=skylake-avx512"))) foo () { + return 15; +} + +int __attribute__ ((target("arch=cannonlake"))) foo () { + return 16; +} + +int __attribute__ ((target("arch=icelake-client"))) foo () { + return 17; +} + +int __attribute__ ((target("arch=icelake-server"))) foo () { + return 18; +} + +int main () +{ + int val = foo (); + + if (__builtin_cpu_is ("nehalem")) + assert (val == 4); + else if (__builtin_cpu_is ("westmere")) + assert (val == 5); + else if (__builtin_cpu_is ("sandybridge")) + assert (val == 8); + else if (__builtin_cpu_is ("ivybridge")) + assert (val == 9); + else if (__builtin_cpu_is ("haswell")) + assert (val == 12); + else if (__builtin_cpu_is ("broadwell")) + assert (val == 13); + else if (__builtin_cpu_is ("skylake")) + assert (val == 14); + else if (__builtin_cpu_is ("skylake-avx512")) + assert (val == 15); + else if (__builtin_cpu_is ("cannonlake")) + assert (val == 16); + else if (__builtin_cpu_is ("icelake-client")) + assert (val == 17); + else if (__builtin_cpu_is ("icelake-server")) + assert (val == 18); + else + assert (val == 0); + + return 0; +} diff --git a/gcc/testsuite/g++.target/i386/mv17.C b/gcc/testsuite/g++.target/i386/mv17.C new file mode 100644 index 0000000..fefbfaa --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv17.C @@ -0,0 +1,93 @@ +// Test case to check if Multiversioning works for BMI and BMI2. + +// { dg-do run } +// { dg-require-ifunc "" } +// { dg-options "-O2" } + +#include + +// Check BMI feature selection works +int foo () __attribute__((target("default"))); +int foo () __attribute__((target("bmi"))); +int foo () __attribute__((target("bmi2"))); + +// Check specialized versions for archs with BMI is chosen over generic BMI versions. +int bar () __attribute__((target("default"))); +int bar () __attribute__((target("bmi"))); +int bar () __attribute__((target("bmi2"))); +int bar () __attribute__((target("arch=btver2"))); +int bar () __attribute__((target("arch=haswell"))); + +int main () +{ + int val = foo (); + + if (__builtin_cpu_supports ("bmi2")) + assert (val == 2); + else if (__builtin_cpu_supports ("bmi")) + assert (val == 1); + else + assert (val == 0); + + val = bar (); + + if (__builtin_cpu_is ("btver2")) + assert (val == 5); + else if (__builtin_cpu_is ("haswell")) + assert (val == 6); + else if (__builtin_cpu_supports ("bmi2")) + assert (val == 2); + else if (__builtin_cpu_supports ("bmi")) + assert (val == 1); + else + assert (val == 0); + + return 0; +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("bmi"))) +foo () +{ + return 1; +} +int __attribute__ ((target("bmi2"))) +foo () +{ + return 2; +} + +int __attribute__ ((target("default"))) +bar () +{ + return 0; +} + +int __attribute__ ((target("bmi"))) +bar () +{ + return 1; +} +int __attribute__ ((target("bmi2"))) +bar () +{ + return 2; +} + +int __attribute__ ((target("arch=btver2"))) +bar () +{ + return 5; +} + +int __attribute__ ((target("arch=haswell"))) +bar () +{ + return 6; +} + diff --git a/gcc/testsuite/g++.target/i386/mv18.C b/gcc/testsuite/g++.target/i386/mv18.C new file mode 100644 index 0000000..b62bc36 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv18.C @@ -0,0 +1,7 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target pie } */ +/* { dg-options "-O2 -fPIE -pie" } */ + +#include "mv1.C" diff --git a/gcc/testsuite/g++.target/i386/mv19.C b/gcc/testsuite/g++.target/i386/mv19.C new file mode 100644 index 0000000..b014c2e --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv19.C @@ -0,0 +1,7 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target pie } */ +/* { dg-options "-O2 -fPIE -pie -march=x86-64" } */ + +#include "mv14.C" diff --git a/gcc/testsuite/g++.target/i386/mv2.C b/gcc/testsuite/g++.target/i386/mv2.C new file mode 100644 index 0000000..3013a2f --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv2.C @@ -0,0 +1,127 @@ +/* Test case to check if Multiversioning chooses the correct + dispatching order when versions are for various ISAs. */ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-O2" } */ + +#include + +/* Default version. */ +int foo () __attribute__ ((target ("default"))); +/* The dispatch checks should be in the exact reverse order of the + declarations below. */ +int foo () __attribute__ ((target ("mmx"))); +int foo () __attribute__ ((target ("sse"))); +int foo () __attribute__ ((target ("sse2"))); +int foo () __attribute__ ((target ("sse3"))); +int foo () __attribute__ ((target ("ssse3"))); +int foo () __attribute__ ((target ("sse4.1"))); +int foo () __attribute__ ((target ("sse4.2"))); +int foo () __attribute__ ((target ("popcnt"))); +int foo () __attribute__ ((target ("avx"))); +int foo () __attribute__ ((target ("avx2"))); +int foo () __attribute__ ((target ("avx512f"))); + +int main () +{ + int val = foo (); + + if (__builtin_cpu_supports ("avx512f")) + assert (val == 11); + else if (__builtin_cpu_supports ("avx2")) + assert (val == 10); + else if (__builtin_cpu_supports ("avx")) + assert (val == 9); + else if (__builtin_cpu_supports ("popcnt")) + assert (val == 8); + else if (__builtin_cpu_supports ("sse4.2")) + assert (val == 7); + else if (__builtin_cpu_supports ("sse4.1")) + assert (val == 6); + else if (__builtin_cpu_supports ("ssse3")) + assert (val == 5); + else if (__builtin_cpu_supports ("sse3")) + assert (val == 4); + else if (__builtin_cpu_supports ("sse2")) + assert (val == 3); + else if (__builtin_cpu_supports ("sse")) + assert (val == 2); + else if (__builtin_cpu_supports ("mmx")) + assert (val == 1); + else + assert (val == 0); + + return 0; +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("mmx"))) +foo () +{ + return 1; +} + +int __attribute__ ((target("sse"))) +foo () +{ + return 2; +} + +int __attribute__ ((target("sse2"))) +foo () +{ + return 3; +} + +int __attribute__ ((target("sse3"))) +foo () +{ + return 4; +} + +int __attribute__ ((target("ssse3"))) +foo () +{ + return 5; +} + +int __attribute__ ((target("sse4.1"))) +foo () +{ + return 6; +} + +int __attribute__ ((target("sse4.2"))) +foo () +{ + return 7; +} + +int __attribute__ ((target("popcnt"))) +foo () +{ + return 8; +} + +int __attribute__ ((target("avx"))) +foo () +{ + return 9; +} + +int __attribute__ ((target("avx2"))) +foo () +{ + return 10; +} + +int __attribute__ ((target("avx512f"))) +foo () +{ + return 11; +} diff --git a/gcc/testsuite/g++.target/i386/mv20.C b/gcc/testsuite/g++.target/i386/mv20.C new file mode 100644 index 0000000..ed8607e --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv20.C @@ -0,0 +1,7 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target pie } */ +/* { dg-options "-O2 -fPIE -pie -march=x86-64" } */ + +#include "mv15.C" diff --git a/gcc/testsuite/g++.target/i386/mv21.C b/gcc/testsuite/g++.target/i386/mv21.C new file mode 100644 index 0000000..a99805f --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv21.C @@ -0,0 +1,7 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target static } */ +/* { dg-options "-O2 -static" } */ + +#include "mv1.C" diff --git a/gcc/testsuite/g++.target/i386/mv22.C b/gcc/testsuite/g++.target/i386/mv22.C new file mode 100644 index 0000000..5e43de7 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv22.C @@ -0,0 +1,7 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target static } */ +/* { dg-options "-O2 -static -march=x86-64" } */ + +#include "mv14.C" diff --git a/gcc/testsuite/g++.target/i386/mv23.C b/gcc/testsuite/g++.target/i386/mv23.C new file mode 100644 index 0000000..674a0ff --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv23.C @@ -0,0 +1,7 @@ +/* Test case to check if Multiversioning works. */ +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target static } */ +/* { dg-options "-O2 -static -march=x86-64" } */ + +#include "mv15.C" diff --git a/gcc/testsuite/g++.target/i386/mv24.C b/gcc/testsuite/g++.target/i386/mv24.C new file mode 100644 index 0000000..f8736cc --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv24.C @@ -0,0 +1,35 @@ +// Test case to check if Multiversioning works for AES + +// { dg-do run } +// { dg-require-ifunc "" } +// { dg-options "-O2" } + +#include + +// Check if AES feature selection works +int foo () __attribute__((target("default"))); +int foo () __attribute__((target("aes"))); + +int main () +{ + int val = foo (); + + if (__builtin_cpu_supports ("aes")) + assert (val == 1); + else + assert (val == 0); + + return 0; +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("aes"))) +foo () +{ + return 1; +} diff --git a/gcc/testsuite/g++.target/i386/mv25.C b/gcc/testsuite/g++.target/i386/mv25.C new file mode 100644 index 0000000..2e2fcc3 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv25.C @@ -0,0 +1,35 @@ +// Test case to check if Multiversioning works for PCLMUL + +// { dg-do run } +// { dg-require-ifunc "" } +// { dg-options "-O2" } + +#include + +// Check if PCLMUL feature selection works +int foo () __attribute__((target("default"))); +int foo () __attribute__((target("pclmul"))); + +int main () +{ + int val = foo (); + + if (__builtin_cpu_supports ("pclmul")) + assert (val == 1); + else + assert (val == 0); + + return 0; +} + +int __attribute__ ((target("default"))) +foo () +{ + return 0; +} + +int __attribute__ ((target("pclmul"))) +foo () +{ + return 1; +} diff --git a/gcc/testsuite/g++.target/i386/mv26.C b/gcc/testsuite/g++.target/i386/mv26.C new file mode 100644 index 0000000..6693ca1 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv26.C @@ -0,0 +1,15 @@ +// PR c++/84059 +// { dg-do compile } +// { dg-require-ifunc "" } + +template struct a +{ + int __attribute__ ((target ("arch=ivybridge"))) c (int) {return 1;} + int __attribute__ ((target ("default"))) c (int) { return 2; } +}; +void +d () +{ + a b; + b.c (2); +} diff --git a/gcc/testsuite/g++.target/i386/mv27.C b/gcc/testsuite/g++.target/i386/mv27.C new file mode 100644 index 0000000..60fa8ca --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv27.C @@ -0,0 +1,18 @@ +// PR c++/83911 +// { dg-do compile } +// { dg-require-ifunc "" } + +class SimdFloat +{ +public: + __attribute__ ((target ("default"))) + SimdFloat(float x) {} + + __attribute__ ((target ("avx2"))) + SimdFloat(float x) {} +}; + +SimdFloat foo() +{ + return 1; +} diff --git a/gcc/testsuite/g++.target/i386/mv3.C b/gcc/testsuite/g++.target/i386/mv3.C new file mode 100644 index 0000000..4a57a52 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv3.C @@ -0,0 +1,36 @@ +/* Test case to check if a call to a multiversioned function + is replaced with a direct call to the particular version when + the most specialized version's target attributes match the + caller. + + In this program, foo is multiversioned but there is no default + function. This is an error if the call has to go through a + dispatcher. However, the call to foo in bar can be replaced + with a direct call to the popcnt version of foo. Hence, this + test should pass. */ + +/* { dg-do run } */ +/* { dg-options "-O2" } */ + + +int __attribute__ ((target ("sse"))) +foo () +{ + return 1; +} +int __attribute__ ((target ("popcnt"))) +foo () +{ + return 0; +} + +int __attribute__ ((target ("popcnt"))) +bar () +{ + return foo (); +} + +int main () +{ + return bar (); +} diff --git a/gcc/testsuite/g++.target/i386/mv4.C b/gcc/testsuite/g++.target/i386/mv4.C new file mode 100644 index 0000000..c4c4d68 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv4.C @@ -0,0 +1,24 @@ +/* Test case to check if the compiler generates an error message + when the default version of a multiversioned function is absent + and its pointer is taken. */ + +/* { dg-do compile } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-O2" } */ + +int __attribute__ ((target ("sse"))) +foo () +{ + return 1; +} +int __attribute__ ((target ("popcnt"))) +foo () +{ + return 0; +} + +int main () +{ + int (*p)() = &foo; /* { dg-error "use of multiversioned function without a default" {} } */ + return (*p)(); +} diff --git a/gcc/testsuite/g++.target/i386/mv5.C b/gcc/testsuite/g++.target/i386/mv5.C new file mode 100644 index 0000000..6690a02 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv5.C @@ -0,0 +1,25 @@ +/* Test case to check if multiversioned functions are still generated if they are + marked comdat with inline keyword. */ + +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-O2" } */ + + +/* Default version. */ +inline int __attribute__ ((target ("default"))) +foo () +{ + return 0; +} + +inline int __attribute__ ((target ("popcnt"))) +foo () +{ + return 0; +} + +int main () +{ + return foo (); +} diff --git a/gcc/testsuite/g++.target/i386/mv6.C b/gcc/testsuite/g++.target/i386/mv6.C new file mode 100644 index 0000000..766b6de --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv6.C @@ -0,0 +1,28 @@ +/* Test to check if member version multiversioning works correctly. */ + +/* { dg-do run } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-march=x86-64" } */ + +class Foo +{ + public: + /* Default version of foo. */ + __attribute__ ((target("default"))) + int foo () + { + return 0; + } + /* corei7 version of foo. */ + __attribute__ ((target("arch=corei7"))) + int foo () + { + return 0; + } +}; + +int main () +{ + Foo f; + return f.foo (); +} diff --git a/gcc/testsuite/g++.target/i386/mv7.C b/gcc/testsuite/g++.target/i386/mv7.C new file mode 100644 index 0000000..2a7ce65 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv7.C @@ -0,0 +1,12 @@ +// { dg-do compile } +// { dg-options "" } + +__attribute__((target ("default"))) +void foo (void) // { dg-message "previously defined here" } +{ +} + +__attribute__((target (128))) +void foo (void) // { dg-error "(not a string|redefinition)" } +{ +} diff --git a/gcc/testsuite/g++.target/i386/mv8.C b/gcc/testsuite/g++.target/i386/mv8.C new file mode 100644 index 0000000..f25399d --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv8.C @@ -0,0 +1,7 @@ +// { dg-do compile } +// { dg-options "" } + +__attribute__((target (11,12))) +void foo (void) // { dg-error "not a string" } +{ +} diff --git a/gcc/testsuite/g++.target/i386/mv9.C b/gcc/testsuite/g++.target/i386/mv9.C new file mode 100644 index 0000000..876a736 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mv9.C @@ -0,0 +1,9 @@ +// { dg-do compile } +// { dg-options "" } + +void foo (); +void foo () __attribute__((target ("sse4"))); +void foo () __attribute__((target ("default"))); // { dg-message "previous declaration" } +void foo () // { dg-error "attribute for multi-versioned" } +{ +} diff --git a/gcc/testsuite/g++.target/i386/mvc1.C b/gcc/testsuite/g++.target/i386/mvc1.C new file mode 100644 index 0000000..b307d01 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mvc1.C @@ -0,0 +1,35 @@ +/* { dg-do run} */ +/* { dg-require-ifunc "" } */ + +__attribute__((target_clones("avx","arch=slm","arch=core-avx2","default"))) +int +foo () +{ + return -2; +} + +__attribute__((target("avx","arch=core-avx2"))) +int +bar () +{ + return 2; +} + +__attribute__((target("default"))) +int +bar () +{ + return 2; +} + +int +main () +{ + int r = 0; + r += bar (); + r += foo (); + r += bar (); + r += foo (); + r += bar (); + return r - 2; +} diff --git a/gcc/testsuite/g++.target/i386/mvc2.C b/gcc/testsuite/g++.target/i386/mvc2.C new file mode 100644 index 0000000..7c1fb65 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mvc2.C @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-require-ifunc "" } */ + +__attribute__((target_clones("avx","arch=slm","default"))) +__attribute__((target("avx"))) +int foo (); /* { dg-warning "'target' attribute ignored due to conflict with 'target_clones' attribute" } */ + +__attribute__((target_clones("avx","arch=slm","default"),always_inline)) +int bar (); /* { dg-warning "'always_inline' attribute ignored due to conflict with 'target_clones' attribute" } */ diff --git a/gcc/testsuite/g++.target/i386/mvc3.C b/gcc/testsuite/g++.target/i386/mvc3.C new file mode 100644 index 0000000..5d634fd --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mvc3.C @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-require-ifunc "" } */ + +__attribute__((target("avx"))) +__attribute__((target_clones("avx","arch=slm","default"))) +int foo (); /* { dg-warning "'target_clones' attribute ignored due to conflict with 'target' attribute" } */ + +__attribute__((always_inline,target_clones("avx","arch=slm","default"))) +int bar (); /* { dg-warning "'target_clones' attribute ignored due to conflict with 'always_inline' attribute" } */ diff --git a/gcc/testsuite/g++.target/i386/mvc4.C b/gcc/testsuite/g++.target/i386/mvc4.C new file mode 100644 index 0000000..68df5e3 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/mvc4.C @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-require-ifunc "" } */ +/* { dg-options "-mavx" } */ + +#include + +__m256 x, y, z; + +__attribute__((target("avx"))) +int bar() +{ + x = _mm256_add_ps (y, z); + return 1; +} + +__attribute__((target("default"))) +int bar() +{ + return 2; +} + +int +foobar() +{ + if (__builtin_cpu_supports ("avx")) + return bar(); + else + return 0; +} + +__attribute__((target_clones("default","sse3"))) +int foo() +{ + return foobar(); +} diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp index 91fa2a6..42bb7e6 100644 --- a/gcc/testsuite/gcc.target/i386/i386.exp +++ b/gcc/testsuite/gcc.target/i386/i386.exp @@ -25,477 +25,6 @@ if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then { load_lib gcc-dg.exp load_lib clearcap.exp -# Return 1 if attribute ms_hook_prologue is supported. -proc check_effective_target_ms_hook_prologue { } { - if { [check_no_compiler_messages ms_hook_prologue object { - void __attribute__ ((__ms_hook_prologue__)) foo (); - } ""] } { - return 1 - } else { - return 0 - } -} - -# Return 1 if 3dnow instructions can be compiled. -proc check_effective_target_3dnow { } { - return [check_no_compiler_messages 3dnow object { - typedef int __m64 __attribute__ ((__vector_size__ (8))); - typedef float __v2sf __attribute__ ((__vector_size__ (8))); - - __m64 _m_pfadd (__m64 __A, __m64 __B) - { - return (__m64) __builtin_ia32_pfadd ((__v2sf)__A, (__v2sf)__B); - } - } "-O2 -m3dnow" ] -} - -# Return 1 if sse3 instructions can be compiled. -proc check_effective_target_sse3 { } { - return [check_no_compiler_messages sse3 object { - typedef double __m128d __attribute__ ((__vector_size__ (16))); - typedef double __v2df __attribute__ ((__vector_size__ (16))); - - __m128d _mm_addsub_pd (__m128d __X, __m128d __Y) - { - return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y); - } - } "-O2 -msse3" ] -} - -# Return 1 if ssse3 instructions can be compiled. -proc check_effective_target_ssse3 { } { - return [check_no_compiler_messages ssse3 object { - typedef long long __m128i __attribute__ ((__vector_size__ (16))); - typedef int __v4si __attribute__ ((__vector_size__ (16))); - - __m128i _mm_abs_epi32 (__m128i __X) - { - return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X); - } - } "-O2 -mssse3" ] -} - -# Return 1 if aes instructions can be compiled. -proc check_effective_target_aes { } { - return [check_no_compiler_messages aes object { - typedef long long __m128i __attribute__ ((__vector_size__ (16))); - typedef long long __v2di __attribute__ ((__vector_size__ (16))); - - __m128i _mm_aesimc_si128 (__m128i __X) - { - return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X); - } - } "-O2 -maes" ] -} - -# Return 1 if vaes instructions can be compiled. -proc check_effective_target_vaes { } { - return [check_no_compiler_messages vaes object { - typedef long long __m128i __attribute__ ((__vector_size__ (16))); - typedef long long __v2di __attribute__ ((__vector_size__ (16))); - - __m128i _mm_aesimc_si128 (__m128i __X) - { - return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X); - } - } "-O2 -maes -mavx" ] -} - -# Return 1 if pclmul instructions can be compiled. -proc check_effective_target_pclmul { } { - return [check_no_compiler_messages pclmul object { - typedef long long __m128i __attribute__ ((__vector_size__ (16))); - typedef long long __v2di __attribute__ ((__vector_size__ (16))); - - __m128i pclmulqdq_test (__m128i __X, __m128i __Y) - { - return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X, - (__v2di)__Y, - 1); - } - } "-O2 -mpclmul" ] -} - -# Return 1 if vpclmul instructions can be compiled. -proc check_effective_target_vpclmul { } { - return [check_no_compiler_messages vpclmul object { - typedef long long __m128i __attribute__ ((__vector_size__ (16))); - typedef long long __v2di __attribute__ ((__vector_size__ (16))); - - __m128i pclmulqdq_test (__m128i __X, __m128i __Y) - { - return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X, - (__v2di)__Y, - 1); - } - } "-O2 -mpclmul -mavx" ] -} - -# Return 1 if sse4a instructions can be compiled. -proc check_effective_target_sse4a { } { - return [check_no_compiler_messages sse4a object { - typedef long long __m128i __attribute__ ((__vector_size__ (16))); - typedef long long __v2di __attribute__ ((__vector_size__ (16))); - - __m128i _mm_insert_si64 (__m128i __X,__m128i __Y) - { - return (__m128i) __builtin_ia32_insertq ((__v2di)__X, (__v2di)__Y); - } - } "-O2 -msse4a" ] -} - -# Return 1 if fma4 instructions can be compiled. -proc check_effective_target_fma4 { } { - return [check_no_compiler_messages fma4 object { - typedef float __m128 __attribute__ ((__vector_size__ (16))); - typedef float __v4sf __attribute__ ((__vector_size__ (16))); - __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C) - { - return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A, - (__v4sf)__B, - (__v4sf)__C); - } - } "-O2 -mfma4" ] -} - -# Return 1 if fma instructions can be compiled. -proc check_effective_target_fma { } { - return [check_no_compiler_messages fma object { - typedef float __m128 __attribute__ ((__vector_size__ (16))); - typedef float __v4sf __attribute__ ((__vector_size__ (16))); - __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C) - { - return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A, - (__v4sf)__B, - (__v4sf)__C); - } - } "-O2 -mfma" ] -} - -# Return 1 if xop instructions can be compiled. -proc check_effective_target_xop { } { - return [check_no_compiler_messages xop object { - typedef long long __m128i __attribute__ ((__vector_size__ (16))); - typedef short __v8hi __attribute__ ((__vector_size__ (16))); - __m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C) - { - return (__m128i) __builtin_ia32_vpmacssww ((__v8hi)__A, - (__v8hi)__B, - (__v8hi)__C); - } - } "-O2 -mxop" ] -} - -# Return 1 if lzcnt instruction can be compiled. -proc check_effective_target_lzcnt { } { - return [check_no_compiler_messages lzcnt object { - unsigned short _lzcnt (unsigned short __X) - { - return __builtin_clzs (__X); - } - } "-mlzcnt" ] -} - -# Return 1 if bmi instructions can be compiled. -proc check_effective_target_bmi { } { - return [check_no_compiler_messages bmi object { - unsigned int __bextr_u32 (unsigned int __X, unsigned int __Y) - { - return __builtin_ia32_bextr_u32 (__X, __Y); - } - } "-mbmi" ] -} - -# Return 1 if ADX instructions can be compiled. -proc check_effective_target_adx { } { - return [check_no_compiler_messages adx object { - unsigned char - _adxcarry_u32 (unsigned char __CF, unsigned int __X, - unsigned int __Y, unsigned int *__P) - { - return __builtin_ia32_addcarryx_u32 (__CF, __X, __Y, __P); - } - } "-madx" ] -} - -# Return 1 if rtm instructions can be compiled. -proc check_effective_target_rtm { } { - return [check_no_compiler_messages rtm object { - void - _rtm_xend (void) - { - return __builtin_ia32_xend (); - } - } "-mrtm" ] -} - -# Return 1 if avx512vl instructions can be compiled. -proc check_effective_target_avx512vl { } { - return [check_no_compiler_messages avx512vl object { - typedef long long __v4di __attribute__ ((__vector_size__ (32))); - __v4di - mm256_and_epi64 (__v4di __X, __v4di __Y) - { - __v4di __W; - return __builtin_ia32_pandq256_mask (__X, __Y, __W, -1); - } - } "-mavx512vl" ] -} - -# Return 1 if avx512cd instructions can be compiled. -proc check_effective_target_avx512cd { } { - return [check_no_compiler_messages avx512cd_trans object { - typedef long long __v8di __attribute__ ((__vector_size__ (64))); - __v8di - _mm512_conflict_epi64 (__v8di __W, __v8di __A) - { - return (__v8di) __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A, - (__v8di) __W, - -1); - } - } "-Wno-psabi -mavx512cd" ] -} - -# Return 1 if avx512er instructions can be compiled. -proc check_effective_target_avx512er { } { - return [check_no_compiler_messages avx512er_trans object { - typedef float __v16sf __attribute__ ((__vector_size__ (64))); - __v16sf - mm512_exp2a23_ps (__v16sf __X) - { - return __builtin_ia32_exp2ps_mask (__X, __X, -1, 4); - } - } "-Wno-psabi -mavx512er" ] -} - -# Return 1 if sha instructions can be compiled. -proc check_effective_target_sha { } { - return [check_no_compiler_messages sha object { - typedef long long __m128i __attribute__ ((__vector_size__ (16))); - typedef int __v4si __attribute__ ((__vector_size__ (16))); - - __m128i _mm_sha1msg1_epu32 (__m128i __X, __m128i __Y) - { - return (__m128i) __builtin_ia32_sha1msg1 ((__v4si)__X, - (__v4si)__Y); - } - } "-O2 -msha" ] -} - -# Return 1 if avx512dq instructions can be compiled. -proc check_effective_target_avx512dq { } { - return [check_no_compiler_messages avx512dq object { - typedef long long __v8di __attribute__ ((__vector_size__ (64))); - __v8di - _mm512_mask_mullo_epi64 (__v8di __W, __v8di __A, __v8di __B) - { - return (__v8di) __builtin_ia32_pmullq512_mask ((__v8di) __A, - (__v8di) __B, - (__v8di) __W, - -1); - } - } "-mavx512dq" ] -} - -# Return 1 if avx512bw instructions can be compiled. -proc check_effective_target_avx512bw { } { - return [check_no_compiler_messages avx512bw object { - typedef short __v32hi __attribute__ ((__vector_size__ (64))); - __v32hi - _mm512_mask_mulhrs_epi16 (__v32hi __W, __v32hi __A, __v32hi __B) - { - return (__v32hi) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A, - (__v32hi) __B, - (__v32hi) __W, - -1); - } - } "-mavx512bw" ] -} - -# Return 1 if avx512ifma instructions can be compiled. -proc check_effective_target_avx512ifma { } { - return [check_no_compiler_messages avx512ifma object { - typedef long long __v8di __attribute__ ((__vector_size__ (64))); - __v8di - _mm512_madd52lo_epu64 (__v8di __X, __v8di __Y, __v8di __Z) - { - return (__v8di) __builtin_ia32_vpmadd52luq512_mask ((__v8di) __X, - (__v8di) __Y, - (__v8di) __Z, - -1); - } - } "-mavx512ifma" ] -} - -# Return 1 if avx512vbmi instructions can be compiled. -proc check_effective_target_avx512vbmi { } { - return [check_no_compiler_messages avx512vbmi object { - typedef char __v64qi __attribute__ ((__vector_size__ (64))); - __v64qi - _mm512_multishift_epi64_epi8 (__v64qi __X, __v64qi __Y) - { - return (__v64qi) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X, - (__v64qi) __Y, - (__v64qi) __Y, - -1); - } - } "-mavx512vbmi" ] -} - -# Return 1 if avx512_4fmaps instructions can be compiled. -proc check_effective_target_avx5124fmaps { } { - return [check_no_compiler_messages avx5124fmaps object { - typedef float __v16sf __attribute__ ((__vector_size__ (64))); - typedef float __v4sf __attribute__ ((__vector_size__ (16))); - - __v16sf - _mm512_mask_4fmadd_ps (__v16sf __DEST, __v16sf __A, __v16sf __B, __v16sf __C, - __v16sf __D, __v16sf __E, __v4sf *__F) - { - return (__v16sf) __builtin_ia32_4fmaddps_mask ((__v16sf) __A, - (__v16sf) __B, - (__v16sf) __C, - (__v16sf) __D, - (__v16sf) __E, - (const __v4sf *) __F, - (__v16sf) __DEST, - 0xffff); - } - } "-mavx5124fmaps" ] -} - -# Return 1 if avx512_4vnniw instructions can be compiled. -proc check_effective_target_avx5124vnniw { } { - return [check_no_compiler_messages avx5124vnniw object { - typedef int __v16si __attribute__ ((__vector_size__ (64))); - typedef int __v4si __attribute__ ((__vector_size__ (16))); - - __v16si - _mm512_4dpwssd_epi32 (__v16si __A, __v16si __B, __v16si __C, - __v16si __D, __v16si __E, __v4si *__F) - { - return (__v16si) __builtin_ia32_vp4dpwssd ((__v16si) __B, - (__v16si) __C, - (__v16si) __D, - (__v16si) __E, - (__v16si) __A, - (const __v4si *) __F); - } - } "-mavx5124vnniw" ] -} - -# Return 1 if avx512_vpopcntdq instructions can be compiled. -proc check_effective_target_avx512vpopcntdq { } { - return [check_no_compiler_messages avx512vpopcntdq object { - typedef int __v16si __attribute__ ((__vector_size__ (64))); - - __v16si - _mm512_popcnt_epi32 (__v16si __A) - { - return (__v16si) __builtin_ia32_vpopcountd_v16si ((__v16si) __A); - } - } "-mavx512vpopcntdq" ] -} - -# Return 1 if 128 or 256-bit avx512_vpopcntdq instructions can be compiled. -proc check_effective_target_avx512vpopcntdqvl { } { - return [check_no_compiler_messages avx512vpopcntdqvl object { - typedef int __v8si __attribute__ ((__vector_size__ (32))); - - __v8si - _mm256_popcnt_epi32 (__v8si __A) - { - return (__v8si) __builtin_ia32_vpopcountd_v8si ((__v8si) __A); - } - } "-mavx512vpopcntdq -mavx512vl" ] -} - -# Return 1 if gfni instructions can be compiled. -proc check_effective_target_gfni { } { - return [check_no_compiler_messages gfni object { - typedef char __v16qi __attribute__ ((__vector_size__ (16))); - - __v16qi - _mm_gf2p8affineinv_epi64_epi8 (__v16qi __A, __v16qi __B, const int __C) - { - return (__v16qi) __builtin_ia32_vgf2p8affineinvqb_v16qi ((__v16qi) __A, - (__v16qi) __B, - 0); - } - } "-mgfni" ] -} - -# Return 1 if avx512vbmi2 instructions can be compiled. -proc check_effective_target_avx512vbmi2 { } { - return [check_no_compiler_messages avx512vbmi2 object { - typedef char __v16qi __attribute__ ((__vector_size__ (16))); - typedef unsigned long long __mmask16; - - __v16qi - _mm_mask_compress_epi8 (__v16qi __A, __mmask16 __B, __v16qi __C) - { - return (__v16qi) __builtin_ia32_compressqi128_mask((__v16qi)__C, - (__v16qi)__A, - (__mmask16)__B); - } - } "-mavx512vbmi2 -mavx512vl" ] -} - -# Return 1 if avx512vbmi2 instructions can be compiled. -proc check_effective_target_avx512vnni { } { - return [check_no_compiler_messages avx512vnni object { - typedef int __v16si __attribute__ ((__vector_size__ (64))); - - __v16si - _mm_mask_compress_epi8 (__v16si __A, __v16si __B, __v16si __C) - { - return (__v16si) __builtin_ia32_vpdpbusd_v16si ((__v16si)__A, - (__v16si)__B, - (__v16si)__C); - } - } "-mavx512vnni -mavx512f" ] -} - -# Return 1 if vaes instructions can be compiled. -proc check_effective_target_avx512vaes { } { - return [check_no_compiler_messages avx512vaes object { - - typedef int __v16si __attribute__ ((__vector_size__ (64))); - - __v32qi - _mm256_aesdec_epi128 (__v32qi __A, __v32qi __B) - { - return (__v32qi)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B); - } - } "-mvaes" ] -} - -# Return 1 if vpclmulqdq instructions can be compiled. -proc check_effective_target_vpclmulqdq { } { - return [check_no_compiler_messages vpclmulqdq object { - typedef long long __v4di __attribute__ ((__vector_size__ (32))); - - __v4di - _mm256_clmulepi64_epi128 (__v4di __A, __v4di __B) - { - return (__v4di) __builtin_ia32_vpclmulqdq_v4di (__A, __B, 0); - } - } "-mvpclmulqdq -mavx512vl" ] -} - -# Return 1 if avx512_bitalg instructions can be compiled. -proc check_effective_target_avx512bitalg { } { - return [check_no_compiler_messages avx512bitalg object { - typedef short int __v32hi __attribute__ ((__vector_size__ (64))); - - __v32hi - _mm512_popcnt_epi16 (__v32hi __A) - { - return (__v32hi) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A); - } - } "-mavx512bitalg" ] -} - # If a testcase doesn't have special options, use these. global DEFAULT_CFLAGS if ![info exists DEFAULT_CFLAGS] then { diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index b82c332..fd74c04 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -7296,6 +7296,476 @@ proc check_effective_target_f16c { } { } "-O2 -mf16c" ] } +proc check_effective_target_ms_hook_prologue { } { + if { [check_no_compiler_messages ms_hook_prologue object { + void __attribute__ ((__ms_hook_prologue__)) foo (); + } ""] } { + return 1 + } else { + return 0 + } +} + +# Return 1 if 3dnow instructions can be compiled. +proc check_effective_target_3dnow { } { + return [check_no_compiler_messages 3dnow object { + typedef int __m64 __attribute__ ((__vector_size__ (8))); + typedef float __v2sf __attribute__ ((__vector_size__ (8))); + + __m64 _m_pfadd (__m64 __A, __m64 __B) + { + return (__m64) __builtin_ia32_pfadd ((__v2sf)__A, (__v2sf)__B); + } + } "-O2 -m3dnow" ] +} + +# Return 1 if sse3 instructions can be compiled. +proc check_effective_target_sse3 { } { + return [check_no_compiler_messages sse3 object { + typedef double __m128d __attribute__ ((__vector_size__ (16))); + typedef double __v2df __attribute__ ((__vector_size__ (16))); + + __m128d _mm_addsub_pd (__m128d __X, __m128d __Y) + { + return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y); + } + } "-O2 -msse3" ] +} + +# Return 1 if ssse3 instructions can be compiled. +proc check_effective_target_ssse3 { } { + return [check_no_compiler_messages ssse3 object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef int __v4si __attribute__ ((__vector_size__ (16))); + + __m128i _mm_abs_epi32 (__m128i __X) + { + return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X); + } + } "-O2 -mssse3" ] +} + +# Return 1 if aes instructions can be compiled. +proc check_effective_target_aes { } { + return [check_no_compiler_messages aes object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + + __m128i _mm_aesimc_si128 (__m128i __X) + { + return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X); + } + } "-O2 -maes" ] +} + +# Return 1 if vaes instructions can be compiled. +proc check_effective_target_vaes { } { + return [check_no_compiler_messages vaes object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + + __m128i _mm_aesimc_si128 (__m128i __X) + { + return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X); + } + } "-O2 -maes -mavx" ] +} + +# Return 1 if pclmul instructions can be compiled. +proc check_effective_target_pclmul { } { + return [check_no_compiler_messages pclmul object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + + __m128i pclmulqdq_test (__m128i __X, __m128i __Y) + { + return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X, + (__v2di)__Y, + 1); + } + } "-O2 -mpclmul" ] +} + +# Return 1 if vpclmul instructions can be compiled. +proc check_effective_target_vpclmul { } { + return [check_no_compiler_messages vpclmul object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + + __m128i pclmulqdq_test (__m128i __X, __m128i __Y) + { + return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X, + (__v2di)__Y, + 1); + } + } "-O2 -mpclmul -mavx" ] +} + +# Return 1 if sse4a instructions can be compiled. +proc check_effective_target_sse4a { } { + return [check_no_compiler_messages sse4a object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + + __m128i _mm_insert_si64 (__m128i __X,__m128i __Y) + { + return (__m128i) __builtin_ia32_insertq ((__v2di)__X, (__v2di)__Y); + } + } "-O2 -msse4a" ] +} + +# Return 1 if fma4 instructions can be compiled. +proc check_effective_target_fma4 { } { + return [check_no_compiler_messages fma4 object { + typedef float __m128 __attribute__ ((__vector_size__ (16))); + typedef float __v4sf __attribute__ ((__vector_size__ (16))); + __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C) + { + return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A, + (__v4sf)__B, + (__v4sf)__C); + } + } "-O2 -mfma4" ] +} + +# Return 1 if fma instructions can be compiled. +proc check_effective_target_fma { } { + return [check_no_compiler_messages fma object { + typedef float __m128 __attribute__ ((__vector_size__ (16))); + typedef float __v4sf __attribute__ ((__vector_size__ (16))); + __m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C) + { + return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A, + (__v4sf)__B, + (__v4sf)__C); + } + } "-O2 -mfma" ] +} + +# Return 1 if xop instructions can be compiled. +proc check_effective_target_xop { } { + return [check_no_compiler_messages xop object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef short __v8hi __attribute__ ((__vector_size__ (16))); + __m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C) + { + return (__m128i) __builtin_ia32_vpmacssww ((__v8hi)__A, + (__v8hi)__B, + (__v8hi)__C); + } + } "-O2 -mxop" ] +} + +# Return 1 if lzcnt instruction can be compiled. +proc check_effective_target_lzcnt { } { + return [check_no_compiler_messages lzcnt object { + unsigned short _lzcnt (unsigned short __X) + { + return __builtin_clzs (__X); + } + } "-mlzcnt" ] +} + +# Return 1 if bmi instructions can be compiled. +proc check_effective_target_bmi { } { + return [check_no_compiler_messages bmi object { + unsigned int __bextr_u32 (unsigned int __X, unsigned int __Y) + { + return __builtin_ia32_bextr_u32 (__X, __Y); + } + } "-mbmi" ] +} + +# Return 1 if ADX instructions can be compiled. +proc check_effective_target_adx { } { + return [check_no_compiler_messages adx object { + unsigned char + _adxcarry_u32 (unsigned char __CF, unsigned int __X, + unsigned int __Y, unsigned int *__P) + { + return __builtin_ia32_addcarryx_u32 (__CF, __X, __Y, __P); + } + } "-madx" ] +} + +# Return 1 if rtm instructions can be compiled. +proc check_effective_target_rtm { } { + return [check_no_compiler_messages rtm object { + void + _rtm_xend (void) + { + return __builtin_ia32_xend (); + } + } "-mrtm" ] +} + +# Return 1 if avx512vl instructions can be compiled. +proc check_effective_target_avx512vl { } { + return [check_no_compiler_messages avx512vl object { + typedef long long __v4di __attribute__ ((__vector_size__ (32))); + __v4di + mm256_and_epi64 (__v4di __X, __v4di __Y) + { + __v4di __W; + return __builtin_ia32_pandq256_mask (__X, __Y, __W, -1); + } + } "-mavx512vl" ] +} + +# Return 1 if avx512cd instructions can be compiled. +proc check_effective_target_avx512cd { } { + return [check_no_compiler_messages avx512cd_trans object { + typedef long long __v8di __attribute__ ((__vector_size__ (64))); + __v8di + _mm512_conflict_epi64 (__v8di __W, __v8di __A) + { + return (__v8di) __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A, + (__v8di) __W, + -1); + } + } "-Wno-psabi -mavx512cd" ] +} + +# Return 1 if avx512er instructions can be compiled. +proc check_effective_target_avx512er { } { + return [check_no_compiler_messages avx512er_trans object { + typedef float __v16sf __attribute__ ((__vector_size__ (64))); + __v16sf + mm512_exp2a23_ps (__v16sf __X) + { + return __builtin_ia32_exp2ps_mask (__X, __X, -1, 4); + } + } "-Wno-psabi -mavx512er" ] +} + +# Return 1 if sha instructions can be compiled. +proc check_effective_target_sha { } { + return [check_no_compiler_messages sha object { + typedef long long __m128i __attribute__ ((__vector_size__ (16))); + typedef int __v4si __attribute__ ((__vector_size__ (16))); + + __m128i _mm_sha1msg1_epu32 (__m128i __X, __m128i __Y) + { + return (__m128i) __builtin_ia32_sha1msg1 ((__v4si)__X, + (__v4si)__Y); + } + } "-O2 -msha" ] +} + +# Return 1 if avx512dq instructions can be compiled. +proc check_effective_target_avx512dq { } { + return [check_no_compiler_messages avx512dq object { + typedef long long __v8di __attribute__ ((__vector_size__ (64))); + __v8di + _mm512_mask_mullo_epi64 (__v8di __W, __v8di __A, __v8di __B) + { + return (__v8di) __builtin_ia32_pmullq512_mask ((__v8di) __A, + (__v8di) __B, + (__v8di) __W, + -1); + } + } "-mavx512dq" ] +} + +# Return 1 if avx512bw instructions can be compiled. +proc check_effective_target_avx512bw { } { + return [check_no_compiler_messages avx512bw object { + typedef short __v32hi __attribute__ ((__vector_size__ (64))); + __v32hi + _mm512_mask_mulhrs_epi16 (__v32hi __W, __v32hi __A, __v32hi __B) + { + return (__v32hi) __builtin_ia32_pmulhrsw512_mask ((__v32hi) __A, + (__v32hi) __B, + (__v32hi) __W, + -1); + } + } "-mavx512bw" ] +} + +# Return 1 if avx512ifma instructions can be compiled. +proc check_effective_target_avx512ifma { } { + return [check_no_compiler_messages avx512ifma object { + typedef long long __v8di __attribute__ ((__vector_size__ (64))); + __v8di + _mm512_madd52lo_epu64 (__v8di __X, __v8di __Y, __v8di __Z) + { + return (__v8di) __builtin_ia32_vpmadd52luq512_mask ((__v8di) __X, + (__v8di) __Y, + (__v8di) __Z, + -1); + } + } "-mavx512ifma" ] +} + +# Return 1 if avx512vbmi instructions can be compiled. +proc check_effective_target_avx512vbmi { } { + return [check_no_compiler_messages avx512vbmi object { + typedef char __v64qi __attribute__ ((__vector_size__ (64))); + __v64qi + _mm512_multishift_epi64_epi8 (__v64qi __X, __v64qi __Y) + { + return (__v64qi) __builtin_ia32_vpmultishiftqb512_mask ((__v64qi) __X, + (__v64qi) __Y, + (__v64qi) __Y, + -1); + } + } "-mavx512vbmi" ] +} + +# Return 1 if avx512_4fmaps instructions can be compiled. +proc check_effective_target_avx5124fmaps { } { + return [check_no_compiler_messages avx5124fmaps object { + typedef float __v16sf __attribute__ ((__vector_size__ (64))); + typedef float __v4sf __attribute__ ((__vector_size__ (16))); + + __v16sf + _mm512_mask_4fmadd_ps (__v16sf __DEST, __v16sf __A, __v16sf __B, __v16sf __C, + __v16sf __D, __v16sf __E, __v4sf *__F) + { + return (__v16sf) __builtin_ia32_4fmaddps_mask ((__v16sf) __A, + (__v16sf) __B, + (__v16sf) __C, + (__v16sf) __D, + (__v16sf) __E, + (const __v4sf *) __F, + (__v16sf) __DEST, + 0xffff); + } + } "-mavx5124fmaps" ] +} + +# Return 1 if avx512_4vnniw instructions can be compiled. +proc check_effective_target_avx5124vnniw { } { + return [check_no_compiler_messages avx5124vnniw object { + typedef int __v16si __attribute__ ((__vector_size__ (64))); + typedef int __v4si __attribute__ ((__vector_size__ (16))); + + __v16si + _mm512_4dpwssd_epi32 (__v16si __A, __v16si __B, __v16si __C, + __v16si __D, __v16si __E, __v4si *__F) + { + return (__v16si) __builtin_ia32_vp4dpwssd ((__v16si) __B, + (__v16si) __C, + (__v16si) __D, + (__v16si) __E, + (__v16si) __A, + (const __v4si *) __F); + } + } "-mavx5124vnniw" ] +} + +# Return 1 if avx512_vpopcntdq instructions can be compiled. +proc check_effective_target_avx512vpopcntdq { } { + return [check_no_compiler_messages avx512vpopcntdq object { + typedef int __v16si __attribute__ ((__vector_size__ (64))); + + __v16si + _mm512_popcnt_epi32 (__v16si __A) + { + return (__v16si) __builtin_ia32_vpopcountd_v16si ((__v16si) __A); + } + } "-mavx512vpopcntdq" ] +} + +# Return 1 if 128 or 256-bit avx512_vpopcntdq instructions can be compiled. +proc check_effective_target_avx512vpopcntdqvl { } { + return [check_no_compiler_messages avx512vpopcntdqvl object { + typedef int __v8si __attribute__ ((__vector_size__ (32))); + + __v8si + _mm256_popcnt_epi32 (__v8si __A) + { + return (__v8si) __builtin_ia32_vpopcountd_v8si ((__v8si) __A); + } + } "-mavx512vpopcntdq -mavx512vl" ] +} + +# Return 1 if gfni instructions can be compiled. +proc check_effective_target_gfni { } { + return [check_no_compiler_messages gfni object { + typedef char __v16qi __attribute__ ((__vector_size__ (16))); + + __v16qi + _mm_gf2p8affineinv_epi64_epi8 (__v16qi __A, __v16qi __B, const int __C) + { + return (__v16qi) __builtin_ia32_vgf2p8affineinvqb_v16qi ((__v16qi) __A, + (__v16qi) __B, + 0); + } + } "-mgfni" ] +} + +# Return 1 if avx512vbmi2 instructions can be compiled. +proc check_effective_target_avx512vbmi2 { } { + return [check_no_compiler_messages avx512vbmi2 object { + typedef char __v16qi __attribute__ ((__vector_size__ (16))); + typedef unsigned long long __mmask16; + + __v16qi + _mm_mask_compress_epi8 (__v16qi __A, __mmask16 __B, __v16qi __C) + { + return (__v16qi) __builtin_ia32_compressqi128_mask((__v16qi)__C, + (__v16qi)__A, + (__mmask16)__B); + } + } "-mavx512vbmi2 -mavx512vl" ] +} + +# Return 1 if avx512vbmi2 instructions can be compiled. +proc check_effective_target_avx512vnni { } { + return [check_no_compiler_messages avx512vnni object { + typedef int __v16si __attribute__ ((__vector_size__ (64))); + + __v16si + _mm_mask_compress_epi8 (__v16si __A, __v16si __B, __v16si __C) + { + return (__v16si) __builtin_ia32_vpdpbusd_v16si ((__v16si)__A, + (__v16si)__B, + (__v16si)__C); + } + } "-mavx512vnni -mavx512f" ] +} + +# Return 1 if vaes instructions can be compiled. +proc check_effective_target_avx512vaes { } { + return [check_no_compiler_messages avx512vaes object { + + typedef int __v16si __attribute__ ((__vector_size__ (64))); + + __v32qi + _mm256_aesdec_epi128 (__v32qi __A, __v32qi __B) + { + return (__v32qi)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B); + } + } "-mvaes" ] +} + +# Return 1 if vpclmulqdq instructions can be compiled. +proc check_effective_target_vpclmulqdq { } { + return [check_no_compiler_messages vpclmulqdq object { + typedef long long __v4di __attribute__ ((__vector_size__ (32))); + + __v4di + _mm256_clmulepi64_epi128 (__v4di __A, __v4di __B) + { + return (__v4di) __builtin_ia32_vpclmulqdq_v4di (__A, __B, 0); + } + } "-mvpclmulqdq -mavx512vl" ] +} + +# Return 1 if avx512_bitalg instructions can be compiled. +proc check_effective_target_avx512bitalg { } { + return [check_no_compiler_messages avx512bitalg object { + typedef short int __v32hi __attribute__ ((__vector_size__ (64))); + + __v32hi + _mm512_popcnt_epi16 (__v32hi __A) + { + return (__v32hi) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A); + } + } "-mavx512bitalg" ] +} + # Return 1 if C wchar_t type is compatible with char16_t. proc check_effective_target_wchar_t_char16_t_compatible { } { -- cgit v1.1 From a3368b8ea1bda5edd41900096b10514bcf7c6de7 Mon Sep 17 00:00:00 2001 From: Paul Koning Date: Mon, 8 Oct 2018 10:16:13 -0400 Subject: Fix ICE on block move when using LRA. * config/pdp11/pdp11-protos.h (output_block_move): Remove. (expand_block_move): New function. * config/pdp11/pdp11.c (output_block_move): Remove. (expand_block_move): New function. * config/pdp11/pdp11.h (MOVE_RATIO): New definition. * config/pdp11/pdp11.md (movmemhi): Use expand_block_move. (*movmemhi1): Remove. From-SVN: r264930 --- gcc/ChangeLog | 10 +++ gcc/config/pdp11/pdp11-protos.h | 2 +- gcc/config/pdp11/pdp11.c | 180 +++++++--------------------------------- gcc/config/pdp11/pdp11.h | 5 +- gcc/config/pdp11/pdp11.md | 44 ++-------- 5 files changed, 51 insertions(+), 190 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1ee5edd..0e10c55 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2018-10-08 Paul Koning + + * config/pdp11/pdp11-protos.h (output_block_move): Remove. + (expand_block_move): New function. + * config/pdp11/pdp11.c (output_block_move): Remove. + (expand_block_move): New function. + * config/pdp11/pdp11.h (MOVE_RATIO): New definition. + * config/pdp11/pdp11.md (movmemhi): Use expand_block_move. + (*movmemhi1): Remove. + 2018-10-08 Robin Dapp * config/s390/2827.md: Increase latencies for some FP instructions. diff --git a/gcc/config/pdp11/pdp11-protos.h b/gcc/config/pdp11/pdp11-protos.h index 0ce72fd..0ed61ea 100644 --- a/gcc/config/pdp11/pdp11-protos.h +++ b/gcc/config/pdp11/pdp11-protos.h @@ -26,7 +26,7 @@ extern int legitimate_const_double_p (rtx); extern void notice_update_cc_on_set (rtx, rtx); extern void output_addr_const_pdp11 (FILE *, rtx); extern const char *output_move_multiple (rtx *); -extern const char *output_block_move (rtx *); +extern void expand_block_move (rtx *); extern const char *output_jump (rtx *, int, int); extern void print_operand_address (FILE *, rtx); typedef enum { no_action, dec_before, inc_after } pdp11_action; diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index b3b7ced..06129f1 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -45,6 +45,7 @@ along with GCC; see the file COPYING3. If not see #include "expr.h" #include "builtins.h" #include "dbxout.h" +#include "explow.h" #include "expmed.h" /* This file should be included last. */ @@ -1513,173 +1514,48 @@ no_side_effect_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED) /* - * output a block move: + * expand a block move: * * operands[0] ... to * operands[1] ... from * operands[2] ... length * operands[3] ... alignment - * operands[4] ... scratch register */ - -const char * -output_block_move(rtx *operands) +void +expand_block_move(rtx *operands) { - static int count = 0; - char buf[200]; - int unroll; - int lastbyte = 0; - - /* Move of zero bytes is a NOP. */ - if (operands[2] == const0_rtx) - return ""; - - /* Look for moves by small constant byte counts, those we'll - expand to straight line code. */ - if (CONSTANT_P (operands[2])) - { - if (INTVAL (operands[2]) < 16 - && (!optimize_size || INTVAL (operands[2]) < 5) - && INTVAL (operands[3]) == 1) - { - register int i; - - for (i = 1; i <= INTVAL (operands[2]); i++) - output_asm_insn("movb\t(%1)+,(%0)+", operands); - - return ""; - } - else if (INTVAL(operands[2]) < 32 - && (!optimize_size || INTVAL (operands[2]) < 9) - && INTVAL (operands[3]) >= 2) - { - register int i; - - for (i = 1; i <= INTVAL (operands[2]) / 2; i++) - output_asm_insn ("mov\t(%1)+,(%0)+", operands); - if (INTVAL (operands[2]) & 1) - output_asm_insn ("movb\t(%1),(%0)", operands); - - return ""; - } - } - - /* Ideally we'd look for moves that are multiples of 4 or 8 - bytes and handle those by unrolling the move loop. That - makes for a lot of code if done at run time, but it's ok - for constant counts. Also, for variable counts we have - to worry about odd byte count with even aligned pointers. - On 11/40 and up we handle that case; on older machines - we don't and just use byte-wise moves all the time. */ - - if (CONSTANT_P (operands[2]) ) - { - if (INTVAL (operands[3]) < 2) - unroll = 0; - else - { - lastbyte = INTVAL (operands[2]) & 1; - - if (optimize_size || INTVAL (operands[2]) & 2) - unroll = 1; - else if (INTVAL (operands[2]) & 4) - unroll = 2; - else - unroll = 3; - } - - /* Loop count is byte count scaled by unroll. */ - operands[2] = GEN_INT (INTVAL (operands[2]) >> unroll); - output_asm_insn ("mov\t%2,%4", operands); - } - else - { - /* Variable byte count; use the input register - as the scratch. */ - operands[4] = operands[2]; - - /* Decide whether to move by words, and check - the byte count for zero. */ - if (TARGET_40_PLUS && INTVAL (operands[3]) > 1) - { - unroll = 1; - output_asm_insn ("asr\t%4", operands); - } - else - { - unroll = 0; - output_asm_insn ("tst\t%4", operands); - } - sprintf (buf, "beq movestrhi%d", count + 1); - output_asm_insn (buf, NULL); - } + rtx lb, test; + rtx fromop, toop, counter; + int count; - /* Output the loop label. */ - sprintf (buf, "\nmovestrhi%d:", count); - output_asm_insn (buf, NULL); + /* Transform BLKmode MEM reference into a (reg)+ operand. */ + toop = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); + toop = gen_rtx_POST_INC (Pmode, toop); + fromop = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); + fromop = gen_rtx_POST_INC (Pmode, fromop); - /* Output the appropriate move instructions. */ - switch (unroll) - { - case 0: - output_asm_insn ("movb\t(%1)+,(%0)+", operands); - break; - - case 1: - output_asm_insn ("mov\t(%1)+,(%0)+", operands); - break; - - case 2: - output_asm_insn ("mov\t(%1)+,(%0)+", operands); - output_asm_insn ("mov\t(%1)+,(%0)+", operands); - break; - - default: - output_asm_insn ("mov\t(%1)+,(%0)+", operands); - output_asm_insn ("mov\t(%1)+,(%0)+", operands); - output_asm_insn ("mov\t(%1)+,(%0)+", operands); - output_asm_insn ("mov\t(%1)+,(%0)+", operands); - break; - } - - /* Output the decrement and test. */ - if (TARGET_40_PLUS) + count = INTVAL (operands[2]); + if (INTVAL (operands [3]) >= 2 && (count & 1) == 0) { - sprintf (buf, "sob\t%%4, movestrhi%d", count); - output_asm_insn (buf, operands); + count >>= 1; + toop = gen_rtx_MEM (HImode, toop); + fromop = gen_rtx_MEM (HImode, fromop); } else { - output_asm_insn ("dec\t%4", operands); - sprintf (buf, "bgt movestrhi%d", count); - output_asm_insn (buf, NULL); - } - count ++; - - /* If constant odd byte count, move the last byte. */ - if (lastbyte) - output_asm_insn ("movb\t(%1),(%0)", operands); - else if (!CONSTANT_P (operands[2])) - { - /* Output the destination label for the zero byte count check. */ - sprintf (buf, "\nmovestrhi%d:", count); - output_asm_insn (buf, NULL); - count++; - - /* If we did word moves, check for trailing last byte. */ - if (unroll) - { - sprintf (buf, "bcc movestrhi%d", count); - output_asm_insn (buf, NULL); - output_asm_insn ("movb\t(%1),(%0)", operands); - sprintf (buf, "\nmovestrhi%d:", count); - output_asm_insn (buf, NULL); - count++; - } + toop = gen_rtx_MEM (QImode, toop); + fromop = gen_rtx_MEM (QImode, fromop); } - - return ""; + counter = copy_to_mode_reg (HImode, gen_rtx_CONST_INT (HImode, count)); + + /* Label at top of loop */ + lb = gen_label_rtx (); + emit_label (lb); + emit_move_insn (toop, fromop); + emit_insn (gen_subhi3 (counter, counter, const1_rtx)); + test = gen_rtx_NE (HImode, counter, const0_rtx); + emit_jump_insn (gen_cbranchhi4 (test, counter, const0_rtx, lb)); } /* This function checks whether a real value can be encoded as diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h index c68a74d..d65d8f5 100644 --- a/gcc/config/pdp11/pdp11.h +++ b/gcc/config/pdp11/pdp11.h @@ -439,9 +439,12 @@ extern int may_call_alloca; /* Max number of bytes we can move from memory to memory in one reasonably fast instruction. */ - #define MOVE_MAX 2 +/* Max number of insns to use for inline move rather than library + call. */ +#define MOVE_RATIO(speed) 6 + /* Nonzero if access to memory by byte is no faster than by word. */ #define SLOW_BYTE_ACCESS 1 diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md index e51f538..a41e1590 100644 --- a/gcc/config/pdp11/pdp11.md +++ b/gcc/config/pdp11/pdp11.md @@ -570,48 +570,20 @@ clrf\t%0" [(set_attr "length" "2,2,4,4,2")]) -;; maybe fiddle a bit with move_ratio, then -;; let constraints only accept a register ... - +;; Expand a block move. We turn this into a move loop. (define_expand "movmemhi" - [(parallel [(set (match_operand:BLK 0 "general_operand" "=g,g") - (match_operand:BLK 1 "general_operand" "g,g")) - (use (match_operand:HI 2 "general_operand" "n,mr")) - (use (match_operand:HI 3 "immediate_operand" "i,i")) - (clobber (match_scratch:HI 6 "=&r,X")) - (clobber (match_dup 4)) - (clobber (match_dup 5)) - (clobber (match_dup 2))])] + [(match_operand:BLK 0 "general_operand" "=g") + (match_operand:BLK 1 "general_operand" "g") + (match_operand:HI 2 "immediate_operand" "i") + (match_operand:HI 3 "immediate_operand" "i")] "" " { - operands[0] - = replace_equiv_address (operands[0], - copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); - operands[1] - = replace_equiv_address (operands[1], - copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); - - operands[4] = XEXP (operands[0], 0); - operands[5] = XEXP (operands[1], 0); + if (INTVAL (operands[2]) != 0) + expand_block_move (operands); + DONE; }") - -(define_insn "*movmemhi1" - [(set (mem:BLK (match_operand:HI 0 "register_operand" "r,r")) - (mem:BLK (match_operand:HI 1 "register_operand" "r,r"))) - (use (match_operand:HI 2 "general_operand" "n,r")) - (use (match_operand:HI 3 "immediate_operand" "i,i")) - (clobber (match_scratch:HI 4 "=&r,X")) - (clobber (match_dup 0)) - (clobber (match_dup 1)) - (clobber (match_dup 2))] - "" - "* return output_block_move (operands);" -;;; just a guess - [(set_attr "length" "80")]) - - ;;- truncation instructions -- cgit v1.1 From 3cbb7cbb096134746588d08a469778b11ae6ac73 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Mon, 8 Oct 2018 14:21:30 +0000 Subject: libgo: update to Go 1.11.1 release Reviewed-on: https://go-review.googlesource.com/c/140277 From-SVN: r264932 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 2c7a860..6e783c9 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -d0739c13ca3686df1f8d0fae7c6c5caaed058503 +a9da4d34a2f878a5058f7e7d2beef52aa62471a1 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1