From e26b63b29fc9567f9eab418b05657bcc00a9eb0a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 23 Dec 2004 02:32:42 -0800 Subject: alpha.md (one_cmpl2, [...]): New macroized vector operate patterns. * config/alpha/alpha.md (one_cmpl2, and3, andnot3, ior3, iornot3, xor3, xornot3): New macroized vector operate patterns. From-SVN: r92545 --- gcc/ChangeLog | 6 ++++++ gcc/config/alpha/alpha.md | 55 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1fa3c95..3ddbf23 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2004-12-23 Richard Henderson + * config/alpha/alpha.md (one_cmpl2, and3, andnot3, + ior3, iornot3, xor3, xornot3): New macroized + vector operate patterns. + +2004-12-23 Richard Henderson + * config/i386/i386.c (ix86_expand_vector_move): Tidy. (ix86_expand_vector_move_misalign): New. (ix86_misaligned_mem_ok): Remove. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 145e23c..2679324 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -6207,6 +6207,61 @@ "TARGET_MAX" "maxsw4 %r1,%r2,%0" [(set_attr "type" "mvi")]) + +(define_insn "one_cmpl2" + [(set (match_operand:VEC 0 "register_operand" "=r") + (not:VEC (match_operand:VEC 1 "register_operand" "r")))] + "" + "ornot $31,%1,%0" + [(set_attr "type" "ilog")]) + +(define_insn "and3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (and:VEC (match_operand:VEC 1 "register_operand" "r") + (match_operand:VEC 2 "register_operand" "r")))] + "" + "and %1,%2,%0" + [(set_attr "type" "ilog")]) + +(define_insn "*andnot3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r")) + (match_operand:VEC 2 "register_operand" "r")))] + "" + "bic %2,%1,%0" + [(set_attr "type" "ilog")]) + +(define_insn "ior3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (ior:VEC (match_operand:VEC 1 "register_operand" "r") + (match_operand:VEC 2 "register_operand" "r")))] + "" + "bis %1,%2,%0" + [(set_attr "type" "ilog")]) + +(define_insn "*iornot3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r")) + (match_operand:VEC 2 "register_operand" "r")))] + "" + "ornot %2,%1,%0" + [(set_attr "type" "ilog")]) + +(define_insn "xor3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (xor:VEC (match_operand:VEC 1 "register_operand" "r") + (match_operand:VEC 2 "register_operand" "r")))] + "" + "xor %1,%2,%0" + [(set_attr "type" "ilog")]) + +(define_insn "*xornot3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r") + (match_operand:VEC 2 "register_operand" "r"))))] + "" + "eqv %1,%2,%0" + [(set_attr "type" "ilog")]) ;; Bit field extract patterns which use ext[wlq][lh] -- cgit v1.1