From d6f31c8d579f44bf8383ce1fcc1f2bb05c8d8df2 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Tue, 2 Sep 2025 13:31:40 +0800 Subject: RISC-V: Add test for vec_duplicate + vmadd.vv unsigned combine with GR2VR cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vmadd.vvm combine to vmadd.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vmadd.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: Add test data for run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u8.c: New test. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 + .../gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 + .../riscv/rvv/autovec/vx_vf/vx_ternary.h | 1 + .../riscv/rvv/autovec/vx_vf/vx_ternary_data.h | 184 +++++++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u16.c | 16 ++ .../riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u32.c | 16 ++ .../riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u64.c | 16 ++ .../riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u8.c | 16 ++ 18 files changed, 261 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u8.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index 27204de..b9065ad 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index 4c655c5..a4d422e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index 27f5253..7d7ec75 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -27,3 +27,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) } } } } } */ /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c index 8622b30..0cdda99 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vaaddu.vx} 2 } } */ /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index 330d541..f460ccb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ +/* { dg-final { scan-assembler-not {vmadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index 7095cc7..4ed60f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ +/* { dg-final { scan-assembler-not {vmadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index 29824ed..2a7e332 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ +/* { dg-final { scan-assembler-not {vmadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c index 525dd38..923b9c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ +/* { dg-final { scan-assembler-not {vmadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index 7c98625..3ddd6b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ +/* { dg-final { scan-assembler-not {vmadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index 9de7c9f..609bdec 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ +/* { dg-final { scan-assembler-not {vmadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index b35a9b7..a498e53 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ +/* { dg-final { scan-assembler-not {vmadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c index 9eeb272..b9b624e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c @@ -24,3 +24,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vaaddu.vx} } } */ /* { dg-final { scan-assembler-not {vmacc.vx} } } */ /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ +/* { dg-final { scan-assembler-not {vmadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h index 30f3325..06fde11 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h @@ -52,6 +52,7 @@ test_vx_ternary_##NAME##_##T##_case_1 (T * restrict vd, T * restrict vs2, \ #define TEST_TERNARY_VX_UNSIGNED_0(T) \ DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc) \ + DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, madd) \ DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac) \ #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h index 3155d6a..447a58c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h @@ -926,4 +926,188 @@ int64_t TEST_TERNARY_DATA(int64_t, madd)[][4][N] = }, }; +uint8_t TEST_TERNARY_DATA(uint8_t, madd)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 255 }, /* rs1 */ + { /* vs2 */ + 127, 127, 127, 127, + 255, 255, 255, 255, + 0, 0, 0, 0, + 128, 128, 128, 128, + }, + { /* vd */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 250, 250, 250, 250, + 253, 253, 253, 253, + 127, 127, 127, 127, + }, + }, +}; + +uint16_t TEST_TERNARY_DATA(uint16_t, madd)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 65535 }, /* rs1 */ + { /* vs2 */ + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 0, 0, 0, 0, + 32768, 32768, 32768, 32768, + }, + { /* vd */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 65530, 65530, 65530, 65530, + 65533, 65533, 65533, 65533, + 32767, 32767, 32767, 32767, + }, + }, +}; + +uint32_t TEST_TERNARY_DATA(uint32_t, madd)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 4294967295 }, /* rs1 */ + { /* vs2 */ + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 0, 0, 0, 0, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + { /* vd */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967290, 4294967290, 4294967290, 4294967290, + 4294967293, 4294967293, 4294967293, 4294967293, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, +}; + +uint64_t TEST_TERNARY_DATA(uint64_t, madd)[][4][N] = +{ + { + { 1 }, /* rs1 */ + { /* vs2 */ + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { /* vd */ + 0, 0, 0, 0, + 1, 1, 1, 1, + 6, 6, 6, 6, + 3, 3, 3, 3, + }, + { + 1, 1, 1, 1, + 3, 3, 3, 3, + 6, 6, 6, 6, + 7, 7, 7, 7, + }, + }, + { + { 18446744073709551615ull }, /* rs1 */ + { /* vs2 */ + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 0, 0, 0, 0, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + { /* vd */ + 0, 0, 0, 0, + 5, 5, 5, 5, + 3, 3, 3, 3, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551610ull, 18446744073709551610ull, 18446744073709551610ull, 18446744073709551610ull, + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u16.c new file mode 100644 index 0000000..a1312c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint16_t +#define NAME madd +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u32.c new file mode 100644 index 0000000..0cb79a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint32_t +#define NAME madd +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u64.c new file mode 100644 index 0000000..e6397b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint64_t +#define NAME madd +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u8.c new file mode 100644 index 0000000..22e6424 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-u8.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_ternary.h" +#include "vx_ternary_data.h" + +#define T uint8_t +#define NAME madd +#define TEST_DATA TEST_TERNARY_DATA_WRAP(T, NAME) + +DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, NAME) + +#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \ + RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) + +#include "vx_ternary_run.h" -- cgit v1.1