From ef0e3441246ee1dc01b3bf39622bc53644b181f8 Mon Sep 17 00:00:00 2001 From: Renlin Li Date: Tue, 13 Jun 2017 13:57:45 +0000 Subject: [ARM][Testsuite]make dump_stack function call conditional in cold-lc.c After r249013, die () and dump_stack () are both in cold section. This makes the compiler generate bl instruction for the function call, instead of honoring the -mlong-calls option. This patch changes the dump_stack function call conditional, which fixes the regression. gcc/testsuite/ * gcc.target/arm/cold-lc.c: Update coding style, call dump_stack conditionally. From-SVN: r249157 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/arm/cold-lc.c | 7 ++++--- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d9a9fb2..6b33a67 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-13 Renlin Li + + * gcc.target/arm/cold-lc.c: Update coding style, call dump_stack + conditionally. + 2017-06-13 Martin Jambor PR tree-optimization/80803 diff --git a/gcc/testsuite/gcc.target/arm/cold-lc.c b/gcc/testsuite/gcc.target/arm/cold-lc.c index 467a696..f0cd6df 100644 --- a/gcc/testsuite/gcc.target/arm/cold-lc.c +++ b/gcc/testsuite/gcc.target/arm/cold-lc.c @@ -11,13 +11,14 @@ extern int show_stack (struct task_struct *, unsigned long *); void dump_stack (void) { - unsigned long stack; - show_stack ((current_thread_info ()->task), &stack); + unsigned long stack; + show_stack ((current_thread_info ()->task), &stack); } void die (char *str, void *fp, int nr) { + if (nr) dump_stack (); - while (1); + while (1); } -- cgit v1.1 From 45b2222a13eae86582966de6b8203ca75660c1fe Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Tue, 13 Jun 2017 15:59:05 +0200 Subject: Implement no_sanitize function attribute 2017-06-13 Martin Liska PR sanitize/78204 * c-c++-common/ubsan/attrib-2.c (float_cast2): Enhance the test by adding no_sanitize attribute. * gcc.dg/asan/use-after-scope-4.c: Likewise. 2017-06-13 Martin Liska PR sanitize/78204 * c-attribs.c (add_no_sanitize_value): New function. (handle_no_sanitize_attribute): Likewise. (handle_no_sanitize_address_attribute): Use the function. (handle_no_sanitize_thread_attribute): New function. (handle_no_address_safety_analysis_attribute): Use add_no_sanitize_value. (handle_no_sanitize_undefined_attribute): Likewise. * c-common.h: Declare new functions. * c-ubsan.c (ubsan_instrument_division): Use sanitize_flags_p. (ubsan_instrument_shift): Likewise. (ubsan_instrument_bounds): Likewise. (ubsan_maybe_instrument_array_ref): Likewise. (ubsan_maybe_instrument_reference_or_call): Likewise. 2017-06-13 Martin Liska PR sanitize/78204 * asan.c (asan_sanitize_stack_p): Use sanitize_flags_p. (gate_asan): Likewise. * asan.h (asan_no_sanitize_address_p): Remove the function. (sanitize_flags_p): New function. * builtins.def: Fix coding style. * common.opt: Use renamed enum value. * convert.c (convert_to_integer_1): Use sanitize_flags_p. * doc/extend.texi: Document no_sanitize attribute. * flag-types.h (enum sanitize_code): Rename SANITIZE_NONDEFAULT to SANITIZE_UNDEFINED_NONDEFAULT. * gcc.c (sanitize_spec_function): Use the renamed enum value. * gimple-fold.c (optimize_atomic_compare_exchange_p): Use sanitize_flags_p. * gimplify.c (gimplify_function_tree): Likewise. * ipa-inline.c (sanitize_attrs_match_for_inline_p): Likewise. * opts.c (parse_no_sanitize_attribute): New function. (common_handle_option): Use renamed enum value. * opts.h (parse_no_sanitize_attribute): Declare. * tree.c (sanitize_flags_p): New function. * tree.h: Declared here. * tsan.c: Use sanitize_flags_p. * ubsan.c (ubsan_expand_null_ifn): Likewise. (instrument_mem_ref): Likewise. (instrument_bool_enum_load): Likewise. (do_ubsan_in_current_function): Remove the function. (pass_ubsan::execute): Use sanitize_flags_p. * ubsan.h: Remove do_ubsan_in_current_function * tree-cfg.c (print_no_sanitize_attr_value): New function. (dump_function_to_file): Use it here. 2017-06-13 Martin Liska PR sanitize/78204 * class.c (build_base_path): Use sanitize_flags_p. * cp-gimplify.c (cp_genericize_r): Likewise. (cp_genericize_tree): Likewise. (cp_genericize): Likewise. * cp-ubsan.c (cp_ubsan_instrument_vptr_p): Likewise. * decl.c (compute_array_index_type): Likewise. (start_preparsed_function): Likewise. * decl2.c (one_static_initialization_or_destruction): Likewise. * init.c (finish_length_check): Likewise. * lambda.c (maybe_add_lambda_conv_op): Likewise. * typeck.c (cp_build_binary_op): Likewise. (build_static_cast_1): Likewise. 2017-06-13 Martin Liska PR sanitize/78204 * c-convert.c (convert): Use sanitize_flags_p. * c-decl.c (grokdeclarator): Likewise. * c-typeck.c (convert_for_assignment): Likewise. (c_finish_return): Likewise. (build_binary_op): Likewise. From-SVN: r249158 --- gcc/ChangeLog | 33 ++++++++ gcc/asan.c | 8 +- gcc/asan.h | 27 +++++-- gcc/builtins.def | 3 +- gcc/c-family/ChangeLog | 17 ++++ gcc/c-family/c-attribs.c | 110 ++++++++++++++++++++++---- gcc/c-family/c-common.h | 1 + gcc/c-family/c-ubsan.c | 22 +++--- gcc/c-family/c-ubsan.h | 3 - gcc/c/ChangeLog | 9 +++ gcc/c/c-convert.c | 6 +- gcc/c/c-decl.c | 6 +- gcc/c/c-typeck.c | 16 ++-- gcc/common.opt | 2 +- gcc/convert.c | 4 +- gcc/cp/ChangeLog | 16 ++++ gcc/cp/class.c | 4 +- gcc/cp/cp-gimplify.c | 19 +++-- gcc/cp/cp-ubsan.c | 3 +- gcc/cp/decl.c | 6 +- gcc/cp/decl2.c | 2 +- gcc/cp/init.c | 4 +- gcc/cp/lambda.c | 4 +- gcc/cp/typeck.c | 16 ++-- gcc/doc/extend.texi | 12 +++ gcc/flag-types.h | 4 +- gcc/gcc.c | 3 +- gcc/gimple-fold.c | 3 +- gcc/gimplify.c | 5 +- gcc/ipa-inline.c | 11 +-- gcc/opts.c | 35 +++++++- gcc/opts.h | 2 + gcc/sanopt.c | 4 +- gcc/testsuite/ChangeLog | 7 ++ gcc/testsuite/c-c++-common/ubsan/attrib-2.c | 10 +++ gcc/testsuite/gcc.dg/asan/use-after-scope-4.c | 42 +++++++--- gcc/tree-cfg.c | 29 ++++++- gcc/tsan.c | 8 +- gcc/ubsan.c | 46 +++++------ gcc/ubsan.h | 1 - 40 files changed, 409 insertions(+), 154 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e0a894f..32f2d34 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,36 @@ +2017-06-13 Martin Liska + + PR sanitize/78204 + * asan.c (asan_sanitize_stack_p): Use sanitize_flags_p. + (gate_asan): Likewise. + * asan.h (asan_no_sanitize_address_p): Remove the function. + (sanitize_flags_p): New function. + * builtins.def: Fix coding style. + * common.opt: Use renamed enum value. + * convert.c (convert_to_integer_1): Use sanitize_flags_p. + * doc/extend.texi: Document no_sanitize attribute. + * flag-types.h (enum sanitize_code): Rename SANITIZE_NONDEFAULT + to SANITIZE_UNDEFINED_NONDEFAULT. + * gcc.c (sanitize_spec_function): Use the renamed enum value. + * gimple-fold.c (optimize_atomic_compare_exchange_p): + Use sanitize_flags_p. + * gimplify.c (gimplify_function_tree): Likewise. + * ipa-inline.c (sanitize_attrs_match_for_inline_p): Likewise. + * opts.c (parse_no_sanitize_attribute): New function. + (common_handle_option): Use renamed enum value. + * opts.h (parse_no_sanitize_attribute): Declare. + * tree.c (sanitize_flags_p): New function. + * tree.h: Declared here. + * tsan.c: Use sanitize_flags_p. + * ubsan.c (ubsan_expand_null_ifn): Likewise. + (instrument_mem_ref): Likewise. + (instrument_bool_enum_load): Likewise. + (do_ubsan_in_current_function): Remove the function. + (pass_ubsan::execute): Use sanitize_flags_p. + * ubsan.h: Remove do_ubsan_in_current_function + * tree-cfg.c (print_no_sanitize_attr_value): New function. + (dump_function_to_file): Use it here. + 2017-06-13 Martin Jambor PR tree-optimization/80803 diff --git a/gcc/asan.c b/gcc/asan.c index bf564a4..e730530 100644 --- a/gcc/asan.c +++ b/gcc/asan.c @@ -305,9 +305,7 @@ asan_mark_p (gimple *stmt, enum asan_mark_flags flag) bool asan_sanitize_stack_p (void) { - return ((flag_sanitize & SANITIZE_ADDRESS) - && ASAN_STACK - && !asan_no_sanitize_address_p ()); + return (sanitize_flags_p (SANITIZE_ADDRESS) && ASAN_STACK); } /* Checks whether section SEC should be sanitized. */ @@ -3194,9 +3192,7 @@ asan_instrument (void) static bool gate_asan (void) { - return (flag_sanitize & SANITIZE_ADDRESS) != 0 - && !lookup_attribute ("no_sanitize_address", - DECL_ATTRIBUTES (current_function_decl)); + return sanitize_flags_p (SANITIZE_ADDRESS); } namespace { diff --git a/gcc/asan.h b/gcc/asan.h index 5766397..95bb89e 100644 --- a/gcc/asan.h +++ b/gcc/asan.h @@ -144,13 +144,6 @@ asan_sanitize_use_after_scope (void) return (flag_sanitize_address_use_after_scope && asan_sanitize_stack_p ()); } -static inline bool -asan_no_sanitize_address_p (void) -{ - return lookup_attribute ("no_sanitize_address", - DECL_ATTRIBUTES (current_function_decl)); -} - /* Return true if DECL should be guarded on the stack. */ static inline bool @@ -161,4 +154,24 @@ asan_protect_stack_decl (tree decl) || (asan_sanitize_use_after_scope () && TREE_ADDRESSABLE (decl))); } +/* Return true when flag_sanitize & FLAG is non-zero. If FN is non-null, + remove all flags mentioned in "no_sanitize" of DECL_ATTRIBUTES. */ + +static inline bool +sanitize_flags_p (unsigned int flag, const_tree fn = current_function_decl) +{ + unsigned int result_flags = flag_sanitize & flag; + if (result_flags == 0) + return false; + + if (fn != NULL_TREE) + { + tree value = lookup_attribute ("no_sanitize", DECL_ATTRIBUTES (fn)); + if (value) + result_flags &= ~tree_to_uhwi (TREE_VALUE (value)); + } + + return result_flags; +} + #endif /* TREE_ASAN */ diff --git a/gcc/builtins.def b/gcc/builtins.def index 1c887db..f242137 100644 --- a/gcc/builtins.def +++ b/gcc/builtins.def @@ -236,7 +236,8 @@ along with GCC; see the file COPYING3. If not see DEF_BUILTIN (ENUM, "__builtin_" NAME, BUILT_IN_NORMAL, TYPE, TYPE, \ true, true, true, ATTRS, true, \ (flag_sanitize & (SANITIZE_ADDRESS | SANITIZE_THREAD \ - | SANITIZE_UNDEFINED | SANITIZE_NONDEFAULT) \ + | SANITIZE_UNDEFINED \ + | SANITIZE_UNDEFINED_NONDEFAULT) \ || flag_sanitize_coverage)) #undef DEF_CILKPLUS_BUILTIN diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 7ea7781..8488768 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,20 @@ +2017-06-13 Martin Liska + + PR sanitize/78204 + * c-attribs.c (add_no_sanitize_value): New function. + (handle_no_sanitize_attribute): Likewise. + (handle_no_sanitize_address_attribute): Use the function. + (handle_no_sanitize_thread_attribute): New function. + (handle_no_address_safety_analysis_attribute): Use + add_no_sanitize_value. + (handle_no_sanitize_undefined_attribute): Likewise. + * c-common.h: Declare new functions. + * c-ubsan.c (ubsan_instrument_division): Use sanitize_flags_p. + (ubsan_instrument_shift): Likewise. + (ubsan_instrument_bounds): Likewise. + (ubsan_maybe_instrument_array_ref): Likewise. + (ubsan_maybe_instrument_reference_or_call): Likewise. + 2017-06-11 Jason Merrill * c-ada-spec.c, c-pragma.c: Use id_equal. diff --git a/gcc/c-family/c-attribs.c b/gcc/c-family/c-attribs.c index 695c58c..2b6845f 100644 --- a/gcc/c-family/c-attribs.c +++ b/gcc/c-family/c-attribs.c @@ -51,8 +51,11 @@ static tree handle_common_attribute (tree *, tree, tree, int, bool *); static tree handle_noreturn_attribute (tree *, tree, tree, int, bool *); static tree handle_hot_attribute (tree *, tree, tree, int, bool *); static tree handle_cold_attribute (tree *, tree, tree, int, bool *); +static tree handle_no_sanitize_attribute (tree *, tree, tree, int, bool *); static tree handle_no_sanitize_address_attribute (tree *, tree, tree, int, bool *); +static tree handle_no_sanitize_thread_attribute (tree *, tree, tree, + int, bool *); static tree handle_no_address_safety_analysis_attribute (tree *, tree, tree, int, bool *); static tree handle_no_sanitize_undefined_attribute (tree *, tree, tree, int, @@ -285,11 +288,14 @@ const struct attribute_spec c_common_attribute_table[] = 0, 0, true, false, false, handle_no_address_safety_analysis_attribute, false }, + { "no_sanitize", 1, 1, true, false, false, + handle_no_sanitize_attribute, + false }, { "no_sanitize_address", 0, 0, true, false, false, handle_no_sanitize_address_attribute, false }, { "no_sanitize_thread", 0, 0, true, false, false, - handle_no_sanitize_address_attribute, + handle_no_sanitize_thread_attribute, false }, { "no_sanitize_undefined", 0, 0, true, false, false, handle_no_sanitize_undefined_attribute, @@ -547,22 +553,98 @@ handle_cold_attribute (tree *node, tree name, tree ARG_UNUSED (args), return NULL_TREE; } -/* Handle a "no_sanitize_address" attribute; arguments as in +/* Add FLAGS for a function NODE to no_sanitize_flags in DECL_ATTRIBUTES. */ + +void +add_no_sanitize_value (tree node, unsigned int flags) +{ + tree attr = lookup_attribute ("no_sanitize", DECL_ATTRIBUTES (node)); + if (attr) + { + unsigned int old_value = tree_to_uhwi (TREE_VALUE (attr)); + flags |= old_value; + + if (flags == old_value) + return; + + TREE_VALUE (attr) = build_int_cst (unsigned_type_node, flags); + } + else + DECL_ATTRIBUTES (node) + = tree_cons (get_identifier ("no_sanitize"), + build_int_cst (unsigned_type_node, flags), + DECL_ATTRIBUTES (node)); +} + +/* Handle a "no_sanitize" attribute; arguments as in struct attribute_spec.handler. */ static tree -handle_no_sanitize_address_attribute (tree *node, tree name, tree, int, - bool *no_add_attrs) +handle_no_sanitize_attribute (tree *node, tree name, tree args, int, + bool *no_add_attrs) { + *no_add_attrs = true; + tree id = TREE_VALUE (args); if (TREE_CODE (*node) != FUNCTION_DECL) { warning (OPT_Wattributes, "%qE attribute ignored", name); - *no_add_attrs = true; + return NULL_TREE; + } + + if (TREE_CODE (id) != STRING_CST) + { + error ("no_sanitize argument not a string"); + return NULL_TREE; + } + + char *error_value = NULL; + char *string = ASTRDUP (TREE_STRING_POINTER (id)); + unsigned int flags = parse_no_sanitize_attribute (string, &error_value); + + if (error_value) + { + error ("wrong argument: \"%s\"", error_value); + return NULL_TREE; } + add_no_sanitize_value (*node, flags); + + return NULL_TREE; +} + +/* Handle a "no_sanitize_address" attribute; arguments as in + struct attribute_spec.handler. */ + +static tree +handle_no_sanitize_address_attribute (tree *node, tree name, tree, int, + bool *no_add_attrs) +{ + *no_add_attrs = true; + if (TREE_CODE (*node) != FUNCTION_DECL) + warning (OPT_Wattributes, "%qE attribute ignored", name); + else + add_no_sanitize_value (*node, SANITIZE_ADDRESS); + + return NULL_TREE; +} + +/* Handle a "no_sanitize_thread" attribute; arguments as in + struct attribute_spec.handler. */ + +static tree +handle_no_sanitize_thread_attribute (tree *node, tree name, tree, int, + bool *no_add_attrs) +{ + *no_add_attrs = true; + if (TREE_CODE (*node) != FUNCTION_DECL) + warning (OPT_Wattributes, "%qE attribute ignored", name); + else + add_no_sanitize_value (*node, SANITIZE_THREAD); + return NULL_TREE; } + /* Handle a "no_address_safety_analysis" attribute; arguments as in struct attribute_spec.handler. */ @@ -570,13 +652,12 @@ static tree handle_no_address_safety_analysis_attribute (tree *node, tree name, tree, int, bool *no_add_attrs) { + *no_add_attrs = true; if (TREE_CODE (*node) != FUNCTION_DECL) warning (OPT_Wattributes, "%qE attribute ignored", name); - else if (!lookup_attribute ("no_sanitize_address", DECL_ATTRIBUTES (*node))) - DECL_ATTRIBUTES (*node) - = tree_cons (get_identifier ("no_sanitize_address"), - NULL_TREE, DECL_ATTRIBUTES (*node)); - *no_add_attrs = true; + else + add_no_sanitize_value (*node, SANITIZE_ADDRESS); + return NULL_TREE; } @@ -587,11 +668,12 @@ static tree handle_no_sanitize_undefined_attribute (tree *node, tree name, tree, int, bool *no_add_attrs) { + *no_add_attrs = true; if (TREE_CODE (*node) != FUNCTION_DECL) - { - warning (OPT_Wattributes, "%qE attribute ignored", name); - *no_add_attrs = true; - } + warning (OPT_Wattributes, "%qE attribute ignored", name); + else + add_no_sanitize_value (*node, + SANITIZE_UNDEFINED | SANITIZE_UNDEFINED_NONDEFAULT); return NULL_TREE; } diff --git a/gcc/c-family/c-common.h b/gcc/c-family/c-common.h index 79072e6..1748c19 100644 --- a/gcc/c-family/c-common.h +++ b/gcc/c-family/c-common.h @@ -1552,6 +1552,7 @@ extern enum flt_eval_method excess_precision_mode_join (enum flt_eval_method, enum flt_eval_method); extern int c_flt_eval_method (bool ts18661_p); +extern void add_no_sanitize_value (tree node, unsigned int flags); #if CHECKING_P namespace selftest { diff --git a/gcc/c-family/c-ubsan.c b/gcc/c-family/c-ubsan.c index e48841a..a072d19 100644 --- a/gcc/c-family/c-ubsan.c +++ b/gcc/c-family/c-ubsan.c @@ -49,11 +49,11 @@ ubsan_instrument_division (location_t loc, tree op0, tree op1) op1 = unshare_expr (op1); if (TREE_CODE (type) == INTEGER_TYPE - && (flag_sanitize & SANITIZE_DIVIDE)) + && sanitize_flags_p (SANITIZE_DIVIDE)) t = fold_build2 (EQ_EXPR, boolean_type_node, op1, build_int_cst (type, 0)); else if (TREE_CODE (type) == REAL_TYPE - && (flag_sanitize & SANITIZE_FLOAT_DIVIDE)) + && sanitize_flags_p (SANITIZE_FLOAT_DIVIDE)) t = fold_build2 (EQ_EXPR, boolean_type_node, op1, build_real (type, dconst0)); else @@ -61,7 +61,7 @@ ubsan_instrument_division (location_t loc, tree op0, tree op1) /* We check INT_MIN / -1 only for signed types. */ if (TREE_CODE (type) == INTEGER_TYPE - && (flag_sanitize & SANITIZE_DIVIDE) + && sanitize_flags_p (SANITIZE_DIVIDE) && !TYPE_UNSIGNED (type)) { tree x; @@ -131,7 +131,7 @@ ubsan_instrument_shift (location_t loc, enum tree_code code, Also punt on bit-fields. */ if (TYPE_OVERFLOW_WRAPS (type0) || GET_MODE_BITSIZE (TYPE_MODE (type0)) != TYPE_PRECISION (type0) - || (flag_sanitize & SANITIZE_SHIFT_BASE) == 0) + || !sanitize_flags_p (SANITIZE_SHIFT_BASE)) ; /* For signed x << y, in C99/C11, the following: @@ -178,7 +178,7 @@ ubsan_instrument_shift (location_t loc, enum tree_code code, tree else_t = void_node; if (tt) { - if ((flag_sanitize & SANITIZE_SHIFT_EXPONENT) == 0) + if (!sanitize_flags_p (SANITIZE_SHIFT_EXPONENT)) { t = fold_build1 (TRUTH_NOT_EXPR, boolean_type_node, t); t = fold_build2 (TRUTH_AND_EXPR, boolean_type_node, t, tt); @@ -301,7 +301,7 @@ ubsan_instrument_bounds (location_t loc, tree array, tree *index, /* Detect flexible array members and suchlike, unless -fsanitize=bounds-strict. */ tree base = get_base_address (array); - if ((flag_sanitize & SANITIZE_BOUNDS_STRICT) == 0 + if (!sanitize_flags_p (SANITIZE_BOUNDS_STRICT) && TREE_CODE (array) == COMPONENT_REF && base && (INDIRECT_REF_P (base) || TREE_CODE (base) == MEM_REF)) { @@ -373,7 +373,7 @@ void ubsan_maybe_instrument_array_ref (tree *expr_p, bool ignore_off_by_one) { if (!ubsan_array_ref_instrumented_p (*expr_p) - && do_ubsan_in_current_function ()) + && sanitize_flags_p (SANITIZE_BOUNDS | SANITIZE_BOUNDS_STRICT)) { tree op0 = TREE_OPERAND (*expr_p, 0); tree op1 = TREE_OPERAND (*expr_p, 1); @@ -393,7 +393,7 @@ static tree ubsan_maybe_instrument_reference_or_call (location_t loc, tree op, tree ptype, enum ubsan_null_ckind ckind) { - if (!do_ubsan_in_current_function ()) + if (!sanitize_flags_p (SANITIZE_ALIGNMENT | SANITIZE_NULL)) return NULL_TREE; tree type = TREE_TYPE (ptype); @@ -401,7 +401,7 @@ ubsan_maybe_instrument_reference_or_call (location_t loc, tree op, tree ptype, bool instrument = false; unsigned int mina = 0; - if (flag_sanitize & SANITIZE_ALIGNMENT) + if (sanitize_flags_p (SANITIZE_ALIGNMENT)) { mina = min_align_of_type (type); if (mina <= 1) @@ -419,7 +419,7 @@ ubsan_maybe_instrument_reference_or_call (location_t loc, tree op, tree ptype, } else { - if ((flag_sanitize & SANITIZE_NULL) && TREE_CODE (op) == ADDR_EXPR) + if (sanitize_flags_p (SANITIZE_NULL) && TREE_CODE (op) == ADDR_EXPR) { bool strict_overflow_p = false; /* tree_single_nonzero_warnv_p will not return true for non-weak @@ -435,7 +435,7 @@ ubsan_maybe_instrument_reference_or_call (location_t loc, tree op, tree ptype, flag_delete_null_pointer_checks = save_flag_delete_null_pointer_checks; } - else if (flag_sanitize & SANITIZE_NULL) + else if (sanitize_flags_p (SANITIZE_NULL)) instrument = true; if (mina && mina > 1) { diff --git a/gcc/c-family/c-ubsan.h b/gcc/c-family/c-ubsan.h index 3c3ffc7..1e2d192 100644 --- a/gcc/c-family/c-ubsan.h +++ b/gcc/c-family/c-ubsan.h @@ -31,7 +31,4 @@ extern void ubsan_maybe_instrument_array_ref (tree *, bool); extern void ubsan_maybe_instrument_reference (tree *); extern void ubsan_maybe_instrument_member_call (tree, bool); -/* Declare this here as well as in ubsan.h. */ -extern bool do_ubsan_in_current_function (void); - #endif /* GCC_C_UBSAN_H */ diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index e94bcea..173fa92 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,12 @@ +2017-06-13 Martin Liska + + PR sanitize/78204 + * c-convert.c (convert): Use sanitize_flags_p. + * c-decl.c (grokdeclarator): Likewise. + * c-typeck.c (convert_for_assignment): Likewise. + (c_finish_return): Likewise. + (build_binary_op): Likewise. + 2017-06-08 Jakub Jelinek PR c/81006 diff --git a/gcc/c/c-convert.c b/gcc/c/c-convert.c index b8117b4..33c9143 100644 --- a/gcc/c/c-convert.c +++ b/gcc/c/c-convert.c @@ -31,6 +31,7 @@ along with GCC; see the file COPYING3. If not see #include "convert.h" #include "langhooks.h" #include "ubsan.h" +#include "asan.h" /* Change of width--truncation and extension of integers or reals-- is represented with NOP_EXPR. Proper functioning of many things @@ -106,10 +107,9 @@ convert (tree type, tree expr) case INTEGER_TYPE: case ENUMERAL_TYPE: - if (flag_sanitize & SANITIZE_FLOAT_CAST + if (sanitize_flags_p (SANITIZE_FLOAT_CAST) && TREE_CODE (TREE_TYPE (expr)) == REAL_TYPE - && COMPLETE_TYPE_P (type) - && do_ubsan_in_current_function ()) + && COMPLETE_TYPE_P (type)) { expr = save_expr (expr); tree check = ubsan_instrument_float_cast (loc, type, expr); diff --git a/gcc/c/c-decl.c b/gcc/c/c-decl.c index 3a0a4f5..317d5cd 100644 --- a/gcc/c/c-decl.c +++ b/gcc/c/c-decl.c @@ -53,6 +53,7 @@ along with GCC; see the file COPYING3. If not see #include "builtins.h" #include "spellcheck-tree.h" #include "gcc-rich-location.h" +#include "asan.h" /* In grokdeclarator, distinguish syntactic contexts of declarators. */ enum decl_context @@ -6044,9 +6045,8 @@ grokdeclarator (const struct c_declarator *declarator, with known value. */ this_size_varies = size_varies = true; warn_variable_length_array (name, size); - if (flag_sanitize & SANITIZE_VLA - && decl_context == NORMAL - && do_ubsan_in_current_function ()) + if (sanitize_flags_p (SANITIZE_VLA) + && decl_context == NORMAL) { /* Evaluate the array size only once. */ size = save_expr (size); diff --git a/gcc/c/c-typeck.c b/gcc/c/c-typeck.c index ba44406..4d067e9 100644 --- a/gcc/c/c-typeck.c +++ b/gcc/c/c-typeck.c @@ -50,6 +50,7 @@ along with GCC; see the file COPYING3. If not see #include "gomp-constants.h" #include "spellcheck-tree.h" #include "gcc-rich-location.h" +#include "asan.h" /* Possible cases of implicit bad conversions. Used to select diagnostic messages in convert_for_assignment. */ @@ -6378,7 +6379,7 @@ convert_for_assignment (location_t location, location_t expr_loc, tree type, if (codel == BOOLEAN_TYPE || codel == COMPLEX_TYPE || (coder == REAL_TYPE && (codel == INTEGER_TYPE || codel == ENUMERAL_TYPE) - && (flag_sanitize & SANITIZE_FLOAT_CAST))) + && sanitize_flags_p (SANITIZE_FLOAT_CAST))) in_late_binary_op = true; ret = convert_and_check (expr_loc != UNKNOWN_LOCATION ? expr_loc : location, type, orig_rhs); @@ -9955,7 +9956,7 @@ c_finish_return (location_t loc, tree retval, tree origtype) || (TREE_CODE (TREE_TYPE (t)) == REAL_TYPE && (TREE_CODE (TREE_TYPE (res)) == INTEGER_TYPE || TREE_CODE (TREE_TYPE (res)) == ENUMERAL_TYPE) - && (flag_sanitize & SANITIZE_FLOAT_CAST))) + && sanitize_flags_p (SANITIZE_FLOAT_CAST))) in_late_binary_op = true; inner = t = convert (TREE_TYPE (res), t); in_late_binary_op = save; @@ -11835,9 +11836,8 @@ build_binary_op (location_t location, enum tree_code code, return error_mark_node; } - if ((flag_sanitize & (SANITIZE_SHIFT | SANITIZE_DIVIDE - | SANITIZE_FLOAT_DIVIDE)) - && do_ubsan_in_current_function () + if (sanitize_flags_p ((SANITIZE_SHIFT + | SANITIZE_DIVIDE | SANITIZE_FLOAT_DIVIDE)) && (doing_div_or_mod || doing_shift) && !require_constant_value) { @@ -11846,10 +11846,10 @@ build_binary_op (location_t location, enum tree_code code, op1 = save_expr (op1); op0 = c_fully_fold (op0, false, NULL); op1 = c_fully_fold (op1, false, NULL); - if (doing_div_or_mod && (flag_sanitize & (SANITIZE_DIVIDE - | SANITIZE_FLOAT_DIVIDE))) + if (doing_div_or_mod && (sanitize_flags_p ((SANITIZE_DIVIDE + | SANITIZE_FLOAT_DIVIDE)))) instrument_expr = ubsan_instrument_division (location, op0, op1); - else if (doing_shift && (flag_sanitize & SANITIZE_SHIFT)) + else if (doing_shift && sanitize_flags_p (SANITIZE_SHIFT)) instrument_expr = ubsan_instrument_shift (location, code, op0, op1); } diff --git a/gcc/common.opt b/gcc/common.opt index 0a10511..4f9c3dc 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -224,7 +224,7 @@ unsigned int flag_sanitize ; What sanitizers should recover from errors Variable -unsigned int flag_sanitize_recover = (SANITIZE_UNDEFINED | SANITIZE_NONDEFAULT | SANITIZE_KERNEL_ADDRESS) & ~(SANITIZE_UNREACHABLE | SANITIZE_RETURN) +unsigned int flag_sanitize_recover = (SANITIZE_UNDEFINED | SANITIZE_UNDEFINED_NONDEFAULT | SANITIZE_KERNEL_ADDRESS) & ~(SANITIZE_UNREACHABLE | SANITIZE_RETURN) fsanitize-coverage=trace-pc Common Report Var(flag_sanitize_coverage) diff --git a/gcc/convert.c b/gcc/convert.c index af8dfda..429f988 100644 --- a/gcc/convert.c +++ b/gcc/convert.c @@ -33,6 +33,7 @@ along with GCC; see the file COPYING3. If not see #include "langhooks.h" #include "builtins.h" #include "ubsan.h" +#include "asan.h" #define maybe_fold_build1_loc(FOLD_P, LOC, CODE, TYPE, EXPR) \ ((FOLD_P) ? fold_build1_loc (LOC, CODE, TYPE, EXPR) \ @@ -937,8 +938,7 @@ convert_to_integer_1 (tree type, tree expr, bool dofold) return build1 (CONVERT_EXPR, type, expr); case REAL_TYPE: - if (flag_sanitize & SANITIZE_FLOAT_CAST - && do_ubsan_in_current_function ()) + if (sanitize_flags_p (SANITIZE_FLOAT_CAST)) { expr = save_expr (expr); tree check = ubsan_instrument_float_cast (loc, type, expr); diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 6d2f28b..4388830 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,19 @@ +2017-06-13 Martin Liska + + PR sanitize/78204 + * class.c (build_base_path): Use sanitize_flags_p. + * cp-gimplify.c (cp_genericize_r): Likewise. + (cp_genericize_tree): Likewise. + (cp_genericize): Likewise. + * cp-ubsan.c (cp_ubsan_instrument_vptr_p): Likewise. + * decl.c (compute_array_index_type): Likewise. + (start_preparsed_function): Likewise. + * decl2.c (one_static_initialization_or_destruction): Likewise. + * init.c (finish_length_check): Likewise. + * lambda.c (maybe_add_lambda_conv_op): Likewise. + * typeck.c (cp_build_binary_op): Likewise. + (build_static_cast_1): Likewise. + 2017-06-11 Jason Merrill * error.c (dump_expr): Use is_this_parameter. diff --git a/gcc/cp/class.c b/gcc/cp/class.c index 66f4262..dd1051e 100644 --- a/gcc/cp/class.c +++ b/gcc/cp/class.c @@ -36,6 +36,7 @@ along with GCC; see the file COPYING3. If not see #include "dumpfile.h" #include "gimplify.h" #include "intl.h" +#include "asan.h" /* Id for dumping the class hierarchy. */ int class_dump_id; @@ -462,7 +463,8 @@ build_base_path (enum tree_code code, else { tree t = expr; - if ((flag_sanitize & SANITIZE_VPTR) && fixed_type_p == 0) + if (sanitize_flags_p (SANITIZE_VPTR) + && fixed_type_p == 0) { t = cp_ubsan_maybe_instrument_cast_to_vbase (input_location, probe, expr); diff --git a/gcc/cp/cp-gimplify.c b/gcc/cp/cp-gimplify.c index e3802f1..3c8f4b0 100644 --- a/gcc/cp/cp-gimplify.c +++ b/gcc/cp/cp-gimplify.c @@ -33,6 +33,7 @@ along with GCC; see the file COPYING3. If not see #include "c-family/c-ubsan.h" #include "cilk.h" #include "cp-cilkplus.h" +#include "asan.h" /* Forward declarations. */ @@ -1262,8 +1263,7 @@ cp_genericize_r (tree *stmt_p, int *walk_subtrees, void *data) : OMP_CLAUSE_DEFAULT_PRIVATE); } } - if (flag_sanitize - & (SANITIZE_NULL | SANITIZE_ALIGNMENT | SANITIZE_VPTR)) + if (sanitize_flags_p (SANITIZE_NULL | SANITIZE_ALIGNMENT | SANITIZE_VPTR)) { /* The point here is to not sanitize static initializers. */ bool no_sanitize_p = wtd->no_sanitize_p; @@ -1450,11 +1450,11 @@ cp_genericize_r (tree *stmt_p, int *walk_subtrees, void *data) *stmt_p = cplus_expand_constant (stmt); *walk_subtrees = 0; } - else if ((flag_sanitize - & (SANITIZE_NULL | SANITIZE_ALIGNMENT | SANITIZE_VPTR)) + else if (sanitize_flags_p ((SANITIZE_NULL + | SANITIZE_ALIGNMENT | SANITIZE_VPTR)) && !wtd->no_sanitize_p) { - if ((flag_sanitize & (SANITIZE_NULL | SANITIZE_ALIGNMENT)) + if (sanitize_flags_p (SANITIZE_NULL | SANITIZE_ALIGNMENT) && TREE_CODE (stmt) == NOP_EXPR && TREE_CODE (TREE_TYPE (stmt)) == REFERENCE_TYPE) ubsan_maybe_instrument_reference (stmt_p); @@ -1470,9 +1470,9 @@ cp_genericize_r (tree *stmt_p, int *walk_subtrees, void *data) = TREE_CODE (fn) == ADDR_EXPR && TREE_CODE (TREE_OPERAND (fn, 0)) == FUNCTION_DECL && DECL_CONSTRUCTOR_P (TREE_OPERAND (fn, 0)); - if (flag_sanitize & (SANITIZE_NULL | SANITIZE_ALIGNMENT)) + if (sanitize_flags_p (SANITIZE_NULL | SANITIZE_ALIGNMENT)) ubsan_maybe_instrument_member_call (stmt, is_ctor); - if ((flag_sanitize & SANITIZE_VPTR) && !is_ctor) + if (sanitize_flags_p (SANITIZE_VPTR) && !is_ctor) cp_ubsan_maybe_instrument_member_call (stmt); } } @@ -1499,7 +1499,7 @@ cp_genericize_tree (tree* t_p, bool handle_invisiref_parm_p) cp_walk_tree (t_p, cp_genericize_r, &wtd, NULL); delete wtd.p_set; wtd.bind_expr_stack.release (); - if (flag_sanitize & SANITIZE_VPTR) + if (sanitize_flags_p (SANITIZE_VPTR)) cp_ubsan_instrument_member_accesses (t_p); } @@ -1622,8 +1622,7 @@ cp_genericize (tree fndecl) walk_tree's hash functionality. */ cp_genericize_tree (&DECL_SAVED_TREE (fndecl), true); - if (flag_sanitize & SANITIZE_RETURN - && do_ubsan_in_current_function ()) + if (sanitize_flags_p (SANITIZE_RETURN)) cp_ubsan_maybe_instrument_return (fndecl); /* Do everything else. */ diff --git a/gcc/cp/cp-ubsan.c b/gcc/cp/cp-ubsan.c index 71d315e..f00f870 100644 --- a/gcc/cp/cp-ubsan.c +++ b/gcc/cp/cp-ubsan.c @@ -23,6 +23,7 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "cp-tree.h" #include "ubsan.h" +#include "asan.h" /* Test if we should instrument vptr access. */ @@ -32,7 +33,7 @@ cp_ubsan_instrument_vptr_p (tree type) if (!flag_rtti || flag_sanitize_undefined_trap_on_error) return false; - if (!do_ubsan_in_current_function ()) + if (!sanitize_flags_p (SANITIZE_VPTR)) return false; if (type) diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index b0df3c9..3711476 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -51,6 +51,7 @@ along with GCC; see the file COPYING3. If not see #include "cilk.h" #include "builtins.h" #include "gimplify.h" +#include "asan.h" /* Possible cases of bad specifiers type used by bad_specifiers. */ enum bad_spec_place { @@ -9524,8 +9525,7 @@ compute_array_index_type (tree name, tree size, tsubst_flags_t complain) stabilize_vla_size (itype); - if (flag_sanitize & SANITIZE_VLA - && do_ubsan_in_current_function ()) + if (sanitize_flags_p (SANITIZE_VLA)) { /* We have to add 1 -- in the ubsan routine we generate LE_EXPR rather than LT_EXPR. */ @@ -15108,7 +15108,7 @@ start_preparsed_function (tree decl1, tree attrs, int flags) if (!processing_template_decl && DECL_CONSTRUCTOR_P (decl1) - && (flag_sanitize & SANITIZE_VPTR) + && sanitize_flags_p (SANITIZE_VPTR) && !DECL_CLONED_FUNCTION_P (decl1) && !implicit_default_ctor_p (decl1)) cp_ubsan_maybe_initialize_vtbl_ptrs (current_class_ptr); diff --git a/gcc/cp/decl2.c b/gcc/cp/decl2.c index d3d9002..ab32b71 100644 --- a/gcc/cp/decl2.c +++ b/gcc/cp/decl2.c @@ -3737,7 +3737,7 @@ one_static_initialization_or_destruction (tree decl, tree init, bool initp) if (init) { finish_expr_stmt (init); - if (flag_sanitize & SANITIZE_ADDRESS) + if (sanitize_flags_p (SANITIZE_ADDRESS, decl)) { varpool_node *vnode = varpool_node::get (decl); if (vnode) diff --git a/gcc/cp/init.c b/gcc/cp/init.c index 4ad2cae..90abd23 100644 --- a/gcc/cp/init.c +++ b/gcc/cp/init.c @@ -30,6 +30,7 @@ along with GCC; see the file COPYING3. If not see #include "gimplify.h" #include "c-family/c-ubsan.h" #include "intl.h" +#include "asan.h" static bool begin_init_stmts (tree *, tree *); static tree finish_init_stmts (bool, tree, tree); @@ -3911,8 +3912,7 @@ finish_length_check (tree atype, tree iterator, tree obase, unsigned n) } /* Don't check an array new when -fno-exceptions. */ } - else if (flag_sanitize & SANITIZE_BOUNDS - && do_ubsan_in_current_function ()) + else if (sanitize_flags_p (SANITIZE_BOUNDS)) { /* Make sure the last element of the initializer is in bounds. */ finish_expr_stmt diff --git a/gcc/cp/lambda.c b/gcc/cp/lambda.c index 5587f60..52e1fb7 100644 --- a/gcc/cp/lambda.c +++ b/gcc/cp/lambda.c @@ -1150,9 +1150,7 @@ maybe_add_lambda_conv_op (tree type) { /* Don't UBsan this function; we're deliberately calling op() with a null object argument. */ - tree attrs = build_tree_list (get_identifier ("no_sanitize_undefined"), - NULL_TREE); - cplus_decl_attributes (&fn, attrs, 0); + add_no_sanitize_value (fn, SANITIZE_UNDEFINED); } add_method (type, fn, false); diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c index 34d475b..05b4fbb 100644 --- a/gcc/cp/typeck.c +++ b/gcc/cp/typeck.c @@ -37,6 +37,7 @@ along with GCC; see the file COPYING3. If not see #include "c-family/c-ubsan.h" #include "params.h" #include "gcc-rich-location.h" +#include "asan.h" static tree cp_build_addr_expr_strict (tree, tsubst_flags_t); static tree cp_build_function_call (tree, tree, tsubst_flags_t); @@ -5253,10 +5254,9 @@ cp_build_binary_op (location_t location, if (build_type == NULL_TREE) build_type = result_type; - if ((flag_sanitize & (SANITIZE_SHIFT | SANITIZE_DIVIDE - | SANITIZE_FLOAT_DIVIDE)) + if (sanitize_flags_p ((SANITIZE_SHIFT + | SANITIZE_DIVIDE | SANITIZE_FLOAT_DIVIDE)) && !processing_template_decl - && do_ubsan_in_current_function () && (doing_div_or_mod || doing_shift)) { /* OP0 and/or OP1 might have side-effects. */ @@ -5264,8 +5264,8 @@ cp_build_binary_op (location_t location, op1 = cp_save_expr (op1); op0 = fold_non_dependent_expr (op0); op1 = fold_non_dependent_expr (op1); - if (doing_div_or_mod && (flag_sanitize & (SANITIZE_DIVIDE - | SANITIZE_FLOAT_DIVIDE))) + if (doing_div_or_mod + && sanitize_flags_p (SANITIZE_DIVIDE | SANITIZE_FLOAT_DIVIDE)) { /* For diagnostics we want to use the promoted types without shorten_binary_op. So convert the arguments to the @@ -5278,7 +5278,7 @@ cp_build_binary_op (location_t location, cop1 = cp_convert (orig_type, op1, complain); instrument_expr = ubsan_instrument_division (location, cop0, cop1); } - else if (doing_shift && (flag_sanitize & SANITIZE_SHIFT)) + else if (doing_shift && sanitize_flags_p (SANITIZE_SHIFT)) instrument_expr = ubsan_instrument_shift (location, code, op0, op1); } @@ -6823,7 +6823,7 @@ build_static_cast_1 (tree type, tree expr, bool c_cast_p, NULL, complain); expr = build_address (expr); - if (flag_sanitize & SANITIZE_VPTR) + if (sanitize_flags_p (SANITIZE_VPTR)) { tree ubsan_check = cp_ubsan_maybe_instrument_downcast (input_location, type, @@ -6967,7 +6967,7 @@ build_static_cast_1 (tree type, tree expr, bool c_cast_p, expr = build_base_path (MINUS_EXPR, expr, base, /*nonnull=*/false, complain); - if (flag_sanitize & SANITIZE_VPTR) + if (sanitize_flags_p (SANITIZE_VPTR)) { tree ubsan_check = cp_ubsan_maybe_instrument_downcast (input_location, type, diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index ef1ae73..1de17b4 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -2911,6 +2911,18 @@ This has a similar effect as the @option{-fno-toplevel-reorder} option, but only applies to the marked symbols. +@item no_sanitize ("@var{sanitize_option}") +@cindex @code{no_sanitize} function attribute +The @code{no_sanitize} attribute on functions is used +to inform the compiler that it should not do sanitization of all options +mentioned in @var{sanitize_option}. A list of values acceptable by +@option{-fsanitize} option can be provided. + +@smallexample +void __attribute__ ((no_sanitize ("alignment", "object-size"))) +f () @{ /* @r{Do something.} */; @} +@end smallexample + @item no_sanitize_address @itemx no_address_safety_analysis @cindex @code{no_sanitize_address} function attribute diff --git a/gcc/flag-types.h b/gcc/flag-types.h index 27a38ef..5faade5 100644 --- a/gcc/flag-types.h +++ b/gcc/flag-types.h @@ -246,8 +246,8 @@ enum sanitize_code { | SANITIZE_NONNULL_ATTRIBUTE | SANITIZE_RETURNS_NONNULL_ATTRIBUTE | SANITIZE_OBJECT_SIZE | SANITIZE_VPTR, - SANITIZE_NONDEFAULT = SANITIZE_FLOAT_DIVIDE | SANITIZE_FLOAT_CAST - | SANITIZE_BOUNDS_STRICT + SANITIZE_UNDEFINED_NONDEFAULT = SANITIZE_FLOAT_DIVIDE | SANITIZE_FLOAT_CAST + | SANITIZE_BOUNDS_STRICT }; /* flag_vtable_verify initialization levels. */ diff --git a/gcc/gcc.c b/gcc/gcc.c index 4724276..3292532 100644 --- a/gcc/gcc.c +++ b/gcc/gcc.c @@ -9398,7 +9398,8 @@ sanitize_spec_function (int argc, const char **argv) if (strcmp (argv[0], "thread") == 0) return (flag_sanitize & SANITIZE_THREAD) ? "" : NULL; if (strcmp (argv[0], "undefined") == 0) - return ((flag_sanitize & (SANITIZE_UNDEFINED | SANITIZE_NONDEFAULT)) + return ((flag_sanitize + & (SANITIZE_UNDEFINED | SANITIZE_UNDEFINED_NONDEFAULT)) && !flag_sanitize_undefined_trap_on_error) ? "" : NULL; if (strcmp (argv[0], "leak") == 0) return ((flag_sanitize diff --git a/gcc/gimple-fold.c b/gcc/gimple-fold.c index d12f9d0..0f8e326 100644 --- a/gcc/gimple-fold.c +++ b/gcc/gimple-fold.c @@ -56,6 +56,7 @@ along with GCC; see the file COPYING3. If not see #include "ipa-chkp.h" #include "tree-cfg.h" #include "fold-const-call.h" +#include "asan.h" /* Return true when DECL can be referenced from current unit. FROM_DECL (if non-null) specify constructor of variable DECL was taken from. @@ -3479,7 +3480,7 @@ optimize_atomic_compare_exchange_p (gimple *stmt) if (gimple_call_num_args (stmt) != 6 || !flag_inline_atomics || !optimize - || (flag_sanitize & (SANITIZE_THREAD | SANITIZE_ADDRESS)) != 0 + || sanitize_flags_p (SANITIZE_THREAD | SANITIZE_ADDRESS) || !gimple_call_builtin_p (stmt, BUILT_IN_NORMAL) || !gimple_vdef (stmt) || !gimple_vuse (stmt)) diff --git a/gcc/gimplify.c b/gcc/gimplify.c index 653057f..9af95a2 100644 --- a/gcc/gimplify.c +++ b/gcc/gimplify.c @@ -12647,7 +12647,7 @@ gimplify_function_tree (tree fndecl) && !needs_to_live_in_memory (ret)) DECL_GIMPLE_REG_P (ret) = 1; - if (asan_sanitize_use_after_scope () && !asan_no_sanitize_address_p ()) + if (asan_sanitize_use_after_scope () && sanitize_flags_p (SANITIZE_ADDRESS)) asan_poisoned_variables = new hash_set (); bind = gimplify_body (fndecl, true); if (asan_poisoned_variables) @@ -12714,8 +12714,7 @@ gimplify_function_tree (tree fndecl) bind = new_bind; } - if ((flag_sanitize & SANITIZE_THREAD) != 0 - && !lookup_attribute ("no_sanitize_thread", DECL_ATTRIBUTES (fndecl))) + if (sanitize_flags_p (SANITIZE_THREAD)) { gcall *call = gimple_build_call_internal (IFN_TSAN_FUNC_EXIT, 0); gimple *tf = gimple_build_try (seq, call, GIMPLE_TRY_FINALLY); diff --git a/gcc/ipa-inline.c b/gcc/ipa-inline.c index 8924f7e..fb20d37 100644 --- a/gcc/ipa-inline.c +++ b/gcc/ipa-inline.c @@ -117,6 +117,7 @@ along with GCC; see the file COPYING3. If not see #include "auto-profile.h" #include "builtins.h" #include "fibonacci_heap.h" +#include "asan.h" typedef fibonacci_heap edge_heap_t; typedef fibonacci_node edge_heap_node_t; @@ -257,17 +258,11 @@ report_inline_failed_reason (struct cgraph_edge *e) static bool sanitize_attrs_match_for_inline_p (const_tree caller, const_tree callee) { - /* Don't care if sanitizer is disabled */ - if (!(flag_sanitize & SANITIZE_ADDRESS)) - return true; - if (!caller || !callee) return true; - return !!lookup_attribute ("no_sanitize_address", - DECL_ATTRIBUTES (caller)) == - !!lookup_attribute ("no_sanitize_address", - DECL_ATTRIBUTES (callee)); + return sanitize_flags_p (SANITIZE_ADDRESS, caller) + == sanitize_flags_p (SANITIZE_ADDRESS, callee); } /* Used for flags where it is safe to inline when caller's value is diff --git a/gcc/opts.c b/gcc/opts.c index 60ebe56..4013ea5 100644 --- a/gcc/opts.c +++ b/gcc/opts.c @@ -1656,6 +1656,37 @@ parse_sanitizer_options (const char *p, location_t loc, int scode, return flags; } +/* Parse string values of no_sanitize attribute passed in VALUE. + Values are separated with comma. Wrong argument is stored to + WRONG_ARGUMENT variable. */ + +unsigned int +parse_no_sanitize_attribute (char *value, char **wrong_argument) +{ + unsigned int flags = 0; + unsigned int i; + char *q = strtok (value, ","); + + while (q != NULL) + { + for (i = 0; sanitizer_opts[i].name != NULL; ++i) + if (strcmp (sanitizer_opts[i].name, q) == 0) + { + flags |= sanitizer_opts[i].flag; + if (sanitizer_opts[i].flag == SANITIZE_UNDEFINED) + flags |= SANITIZE_UNDEFINED_NONDEFAULT; + break; + } + + if (sanitizer_opts[i].name == NULL) + *wrong_argument = q; + + q = strtok (NULL, ","); + } + + return flags; +} + /* Handle target- and language-independent options. Return zero to generate an "unknown option" message. Only options that need extra handling need to be listed here; if you simply want @@ -1892,11 +1923,11 @@ common_handle_option (struct gcc_options *opts, case OPT_fsanitize_recover: if (value) opts->x_flag_sanitize_recover - |= (SANITIZE_UNDEFINED | SANITIZE_NONDEFAULT) + |= (SANITIZE_UNDEFINED | SANITIZE_UNDEFINED_NONDEFAULT) & ~(SANITIZE_UNREACHABLE | SANITIZE_RETURN); else opts->x_flag_sanitize_recover - &= ~(SANITIZE_UNDEFINED | SANITIZE_NONDEFAULT); + &= ~(SANITIZE_UNDEFINED | SANITIZE_UNDEFINED_NONDEFAULT); break; case OPT_O: diff --git a/gcc/opts.h b/gcc/opts.h index eb626aa..16371e8 100644 --- a/gcc/opts.h +++ b/gcc/opts.h @@ -378,6 +378,8 @@ extern void print_ignored_options (void); extern void handle_common_deferred_options (void); unsigned int parse_sanitizer_options (const char *, location_t, int, unsigned int, int, bool); + +unsigned int parse_no_sanitize_attribute (char *value, char **wrong_argument); extern bool common_handle_option (struct gcc_options *opts, struct gcc_options *opts_set, const struct cl_decoded_option *decoded, diff --git a/gcc/sanopt.c b/gcc/sanopt.c index 70b7aeb..16bdba7 100644 --- a/gcc/sanopt.c +++ b/gcc/sanopt.c @@ -948,9 +948,7 @@ pass_sanopt::execute (function *fun) switch (DECL_FUNCTION_CODE (callee)) { case BUILT_IN_UNREACHABLE: - if (flag_sanitize & SANITIZE_UNREACHABLE - && !lookup_attribute ("no_sanitize_undefined", - DECL_ATTRIBUTES (fun->decl))) + if (sanitize_flags_p (SANITIZE_UNREACHABLE)) no_next = ubsan_instrument_unreachable (&gsi); break; default: diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 6b33a67..1eddf49 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2017-06-13 Martin Liska + + PR sanitize/78204 + * c-c++-common/ubsan/attrib-2.c (float_cast2): Enhance the + test by adding no_sanitize attribute. + * gcc.dg/asan/use-after-scope-4.c: Likewise. + 2017-06-13 Renlin Li * gcc.target/arm/cold-lc.c: Update coding style, call dump_stack diff --git a/gcc/testsuite/c-c++-common/ubsan/attrib-2.c b/gcc/testsuite/c-c++-common/ubsan/attrib-2.c index 71f2e58..3f0a9c3 100644 --- a/gcc/testsuite/c-c++-common/ubsan/attrib-2.c +++ b/gcc/testsuite/c-c++-common/ubsan/attrib-2.c @@ -68,4 +68,14 @@ float_cast (void) c = d; } +__attribute__((no_sanitize(("undefined")))) +static void +float_cast2 (void) +{ + volatile double d = 300; + volatile signed char c; + c = d; +} + + /* { dg-final { scan-assembler-not "__ubsan_handle" } } */ diff --git a/gcc/testsuite/gcc.dg/asan/use-after-scope-4.c b/gcc/testsuite/gcc.dg/asan/use-after-scope-4.c index 77d7052..44dc795 100644 --- a/gcc/testsuite/gcc.dg/asan/use-after-scope-4.c +++ b/gcc/testsuite/gcc.dg/asan/use-after-scope-4.c @@ -1,16 +1,40 @@ // { dg-do run } -int +#define FN(NAME) \ +NAME (void) \ +{ \ + char *ptr; \ + char *ptr2; \ + { \ + char my_char[9]; \ + ptr = &my_char[0]; \ + __builtin_memcpy (&ptr2, &ptr, sizeof (ptr2)); \ + } \ + \ + *(ptr2+9) = 'c'; \ +} + +void +__attribute__((no_sanitize(("address")))) +__attribute__((no_sanitize(("undefined")))) +__attribute__((no_sanitize(("address")))) +__attribute__((no_sanitize(("null")))) +FN (fn1) + +void +__attribute__((no_sanitize(("all")))) +FN (fn2) + +void __attribute__((no_sanitize_address)) +FN (fn3) + +int main (void) { - char *ptr; - char *ptr2; - { - char my_char[9]; - ptr = &my_char[0]; - __builtin_memcpy (&ptr2, &ptr, sizeof (ptr2)); - } + fn1 (); + fn2 (); + fn3 (); - *(ptr2+9) = 'c'; + return 0; } diff --git a/gcc/tree-cfg.c b/gcc/tree-cfg.c index c84e99d..7df80f8 100644 --- a/gcc/tree-cfg.c +++ b/gcc/tree-cfg.c @@ -60,6 +60,7 @@ along with GCC; see the file COPYING3. If not see #include "gimplify.h" #include "attribs.h" #include "selftest.h" +#include "opts.h" /* This file contains functions for building the Control Flow Graph (CFG) for a function tree. */ @@ -7555,6 +7556,25 @@ dump_default_def (FILE *file, tree def, int spc, dump_flags_t flags) fprintf (file, ";\n"); } +/* Print no_sanitize attribute to FILE for a given attribute VALUE. */ + +static void +print_no_sanitize_attr_value (FILE *file, tree value) +{ + unsigned int flags = tree_to_uhwi (value); + bool first = true; + for (int i = 0; sanitizer_opts[i].name != NULL; ++i) + { + if ((sanitizer_opts[i].flag & flags) == sanitizer_opts[i].flag) + { + if (!first) + fprintf (file, " | "); + fprintf (file, "%s", sanitizer_opts[i].name); + first = false; + } + } +} + /* Dump FUNCTION_DECL FN to file FILE using FLAGS (see TDF_* in dumpfile.h) */ @@ -7582,11 +7602,16 @@ dump_function_to_file (tree fndecl, FILE *file, dump_flags_t flags) if (!first) fprintf (file, ", "); - print_generic_expr (file, get_attribute_name (chain), dump_flags); + tree name = get_attribute_name (chain); + print_generic_expr (file, name, dump_flags); if (TREE_VALUE (chain) != NULL_TREE) { fprintf (file, " ("); - print_generic_expr (file, TREE_VALUE (chain), dump_flags); + + if (strstr (IDENTIFIER_POINTER (name), "no_sanitize")) + print_no_sanitize_attr_value (file, TREE_VALUE (chain)); + else + print_generic_expr (file, TREE_VALUE (chain), dump_flags); fprintf (file, ")"); } } diff --git a/gcc/tsan.c b/gcc/tsan.c index dd8cd85..2f98b93 100644 --- a/gcc/tsan.c +++ b/gcc/tsan.c @@ -896,9 +896,7 @@ public: opt_pass * clone () { return new pass_tsan (m_ctxt); } virtual bool gate (function *) { - return ((flag_sanitize & SANITIZE_THREAD) != 0 - && !lookup_attribute ("no_sanitize_thread", - DECL_ATTRIBUTES (current_function_decl))); + return sanitize_flags_p (SANITIZE_THREAD); } virtual unsigned int execute (function *) { return tsan_pass (); } @@ -938,9 +936,7 @@ public: /* opt_pass methods: */ virtual bool gate (function *) { - return ((flag_sanitize & SANITIZE_THREAD) != 0 && !optimize - && !lookup_attribute ("no_sanitize_thread", - DECL_ATTRIBUTES (current_function_decl))); + return (sanitize_flags_p (SANITIZE_THREAD) && !optimize); } virtual unsigned int execute (function *) { return tsan_pass (); } diff --git a/gcc/ubsan.c b/gcc/ubsan.c index 133409a..cee525c 100644 --- a/gcc/ubsan.c +++ b/gcc/ubsan.c @@ -757,7 +757,7 @@ ubsan_expand_null_ifn (gimple_stmt_iterator *gsip) gsi_insert_before (&gsi, g, GSI_SAME_STMT); } } - check_null = (flag_sanitize & SANITIZE_NULL) != 0; + check_null = sanitize_flags_p (SANITIZE_NULL); if (check_align == NULL_TREE && !check_null) { @@ -1181,13 +1181,13 @@ instrument_mem_ref (tree mem, tree base, gimple_stmt_iterator *iter, { enum ubsan_null_ckind ikind = is_lhs ? UBSAN_STORE_OF : UBSAN_LOAD_OF; unsigned int align = 0; - if (flag_sanitize & SANITIZE_ALIGNMENT) + if (sanitize_flags_p (SANITIZE_ALIGNMENT)) { align = min_align_of_type (TREE_TYPE (base)); if (align <= 1) align = 0; } - if (align == 0 && (flag_sanitize & SANITIZE_NULL) == 0) + if (align == 0 && !sanitize_flags_p (SANITIZE_NULL)) return; tree t = TREE_OPERAND (base, 0); if (!POINTER_TYPE_P (TREE_TYPE (t))) @@ -1355,13 +1355,14 @@ instrument_bool_enum_load (gimple_stmt_iterator *gsi) tree type = TREE_TYPE (rhs); tree minv = NULL_TREE, maxv = NULL_TREE; - if (TREE_CODE (type) == BOOLEAN_TYPE && (flag_sanitize & SANITIZE_BOOL)) + if (TREE_CODE (type) == BOOLEAN_TYPE + && sanitize_flags_p (SANITIZE_BOOL)) { minv = boolean_false_node; maxv = boolean_true_node; } else if (TREE_CODE (type) == ENUMERAL_TYPE - && (flag_sanitize & SANITIZE_ENUM) + && sanitize_flags_p (SANITIZE_ENUM) && TREE_TYPE (type) != NULL_TREE && TREE_CODE (TREE_TYPE (type)) == INTEGER_TYPE && (TYPE_PRECISION (TREE_TYPE (type)) @@ -1924,16 +1925,6 @@ instrument_object_size (gimple_stmt_iterator *gsi, bool is_lhs) gsi_insert_before (gsi, g, GSI_SAME_STMT); } -/* True if we want to play UBSan games in the current function. */ - -bool -do_ubsan_in_current_function () -{ - return (current_function_decl != NULL_TREE - && !lookup_attribute ("no_sanitize_undefined", - DECL_ATTRIBUTES (current_function_decl))); -} - namespace { const pass_data pass_data_ubsan = @@ -1959,13 +1950,12 @@ public: /* opt_pass methods: */ virtual bool gate (function *) { - return flag_sanitize & (SANITIZE_NULL | SANITIZE_SI_OVERFLOW - | SANITIZE_BOOL | SANITIZE_ENUM - | SANITIZE_ALIGNMENT - | SANITIZE_NONNULL_ATTRIBUTE - | SANITIZE_RETURNS_NONNULL_ATTRIBUTE - | SANITIZE_OBJECT_SIZE) - && do_ubsan_in_current_function (); + return sanitize_flags_p ((SANITIZE_NULL | SANITIZE_SI_OVERFLOW + | SANITIZE_BOOL | SANITIZE_ENUM + | SANITIZE_ALIGNMENT + | SANITIZE_NONNULL_ATTRIBUTE + | SANITIZE_RETURNS_NONNULL_ATTRIBUTE + | SANITIZE_OBJECT_SIZE)); } virtual unsigned int execute (function *); @@ -1992,11 +1982,11 @@ pass_ubsan::execute (function *fun) continue; } - if ((flag_sanitize & SANITIZE_SI_OVERFLOW) + if ((sanitize_flags_p (SANITIZE_SI_OVERFLOW, fun->decl)) && is_gimple_assign (stmt)) instrument_si_overflow (gsi); - if (flag_sanitize & (SANITIZE_NULL | SANITIZE_ALIGNMENT)) + if (sanitize_flags_p (SANITIZE_NULL | SANITIZE_ALIGNMENT, fun->decl)) { if (gimple_store_p (stmt)) instrument_null (gsi, true); @@ -2018,14 +2008,14 @@ pass_ubsan::execute (function *fun) } } - if (flag_sanitize & (SANITIZE_BOOL | SANITIZE_ENUM) + if (sanitize_flags_p (SANITIZE_BOOL | SANITIZE_ENUM, fun->decl) && gimple_assign_load_p (stmt)) { instrument_bool_enum_load (&gsi); bb = gimple_bb (stmt); } - if ((flag_sanitize & SANITIZE_NONNULL_ATTRIBUTE) + if (sanitize_flags_p (SANITIZE_NONNULL_ATTRIBUTE, fun->decl) && is_gimple_call (stmt) && !gimple_call_internal_p (stmt)) { @@ -2033,14 +2023,14 @@ pass_ubsan::execute (function *fun) bb = gimple_bb (stmt); } - if ((flag_sanitize & SANITIZE_RETURNS_NONNULL_ATTRIBUTE) + if (sanitize_flags_p (SANITIZE_RETURNS_NONNULL_ATTRIBUTE, fun->decl) && gimple_code (stmt) == GIMPLE_RETURN) { instrument_nonnull_return (&gsi); bb = gimple_bb (stmt); } - if (flag_sanitize & SANITIZE_OBJECT_SIZE) + if (sanitize_flags_p (SANITIZE_OBJECT_SIZE, fun->decl)) { if (gimple_store_p (stmt)) instrument_object_size (&gsi, true); diff --git a/gcc/ubsan.h b/gcc/ubsan.h index f04929d..fddd359 100644 --- a/gcc/ubsan.h +++ b/gcc/ubsan.h @@ -42,7 +42,6 @@ enum ubsan_print_style { UBSAN_PRINT_ARRAY }; -extern bool do_ubsan_in_current_function (void); extern bool ubsan_expand_bounds_ifn (gimple_stmt_iterator *); extern bool ubsan_expand_null_ifn (gimple_stmt_iterator *); extern bool ubsan_expand_objsize_ifn (gimple_stmt_iterator *); -- cgit v1.1 From 78a88fb63f23fd9f3d9bf84e31b2f7acc67f25d7 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Tue, 13 Jun 2017 14:26:07 +0000 Subject: compiler: containing small bfunction mixup in Gogo::write_globals Fix buglet in Gogo::write_globals-- in a couple of places the wrong Bfunction was being used for the containing (not target) function when creating calls for init functions. Reviewed-on: https://go-review.googlesource.com/45510 From-SVN: r249159 --- gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/gogo.cc | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 78bd057..2d9adaf 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -c4ecdd3edb9febe72b5527481ae3d7310105ca67 +be5fa26b2b1b5d0755bc1c7ce25f3aa26bea9d9c The first line of this file holds the git revision number of the last merge done from the gofrontend repository. diff --git a/gcc/go/gofrontend/gogo.cc b/gcc/go/gofrontend/gogo.cc index 9071bc8..a9d72ff 100644 --- a/gcc/go/gofrontend/gogo.cc +++ b/gcc/go/gofrontend/gogo.cc @@ -1504,10 +1504,10 @@ Gogo::write_globals() Bfunction* initfn = func->get_or_make_decl(this, *p); Bexpression* func_code = this->backend()->function_code_expression(initfn, func_loc); - Bexpression* call = this->backend()->call_expression(initfn, func_code, + Bexpression* call = this->backend()->call_expression(init_bfn, func_code, empty_args, NULL, func_loc); - Bstatement* ist = this->backend()->expression_statement(initfn, call); + Bstatement* ist = this->backend()->expression_statement(init_bfn, call); init_stmts.push_back(ist); } -- cgit v1.1 From 5b1ebbca8dbba62d58f460bf119c63884238452a Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 13 Jun 2017 19:05:26 +0200 Subject: rs6000: Sanitize vector modes This removes the vector modes that were only used by SPE. It also rearranges things so it is easier to see what is there, and for what. * config/rs6000/rs6000-modes.def: Remove all 8-byte vector modes except V2SF and V2SI. Rearrange the vector modes, and add comments. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Remove V8QImode and V4HImode. (reg_offset_addressing_ok_p): Remove V4HImode and V1DImode. (rs6000_legitimate_offset_address_p): Ditto. (rs6000_emit_move): Ditto. (rs6000_init_builtins): Remove V4HI_type_node. From-SVN: r249162 --- gcc/ChangeLog | 11 +++++++++++ gcc/config/rs6000/rs6000-modes.def | 15 ++++++++++----- gcc/config/rs6000/rs6000.c | 10 ---------- 3 files changed, 21 insertions(+), 15 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 32f2d34..9e2bfa4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2017-06-13 Segher Boessenkool + + * config/rs6000/rs6000-modes.def: Remove all 8-byte vector modes + except V2SF and V2SI. Rearrange the vector modes, and add comments. + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Remove V8QImode + and V4HImode. + (reg_offset_addressing_ok_p): Remove V4HImode and V1DImode. + (rs6000_legitimate_offset_address_p): Ditto. + (rs6000_emit_move): Ditto. + (rs6000_init_builtins): Remove V4HI_type_node. + 2017-06-13 Martin Liska PR sanitize/78204 diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index fc66fca..65f890e 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -41,15 +41,20 @@ CC_MODE (CCFP); CC_MODE (CCEQ); /* Vector modes. */ -VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ + +/* VMX/VSX. */ VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ -VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ -VECTOR_MODE (INT, DI, 1); -VECTOR_MODE (INT, TI, 1); -VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ +VECTOR_MODE (INT, TI, 1); /* V1TI */ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ + +/* Two VMX/VSX vectors (for permute, select, concat, etc.) */ +VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ +/* Paired single. */ +VECTOR_MODE (FLOAT, SF, 2); /* The only valid paired-single mode. */ +VECTOR_MODE (INT, SI, 2); /* For paired-single permutes. */ + /* Replacement for TImode that only is allowed in GPRs. We also use PTImode for quad memory atomic operations to force getting an even/odd register combination. */ diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 8e82570..b51ffcc 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2450,8 +2450,6 @@ rs6000_debug_reg_global (void) SDmode, DDmode, TDmode, - V8QImode, - V4HImode, V2SImode, V16QImode, V8HImode, @@ -8490,9 +8488,7 @@ reg_offset_addressing_ok_p (machine_mode mode) return mode_supports_vsx_dform_quad (mode); break; - case V4HImode: case V2SImode: - case V1DImode: case V2SFmode: /* Paired vector modes. Only reg+reg addressing is valid. */ if (TARGET_PAIRED_FLOAT) @@ -8730,9 +8726,7 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x, extra = 0; switch (mode) { - case V4HImode: case V2SImode: - case V1DImode: case V2SFmode: /* SPE vector modes. */ return SPE_CONST_OFFSET_OK (offset); @@ -10981,10 +10975,8 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode) case V8HImode: case V4SFmode: case V4SImode: - case V4HImode: case V2SFmode: case V2SImode: - case V1DImode: case V2DFmode: case V2DImode: case V1TImode: @@ -16843,7 +16835,6 @@ rs6000_init_builtins (void) : "__vector long long", intDI_type_node, 2); V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2); - V4HI_type_node = build_vector_type (intHI_type_node, 4); V4SI_type_node = rs6000_vector_type ("__vector signed int", intSI_type_node, 4); V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4); @@ -16991,7 +16982,6 @@ rs6000_init_builtins (void) builtin_mode_to_type[V2DImode][0] = V2DI_type_node; builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node; builtin_mode_to_type[V2DFmode][0] = V2DF_type_node; - builtin_mode_to_type[V4HImode][0] = V4HI_type_node; builtin_mode_to_type[V4SImode][0] = V4SI_type_node; builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node; builtin_mode_to_type[V4SFmode][0] = V4SF_type_node; -- cgit v1.1 From afb0e4255a0a67aab004b2ce1bf781362e4055d7 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 13 Jun 2017 19:06:37 +0200 Subject: rs6000: Remove SPE_CONST_OFFSET_OK * config/rs6000/rs6000.c (SPE_CONST_OFFSET_OK): Delete. (rs6000_legitimate_offset_address_p): Return false for anything in V2SImode or V2SFmode. From-SVN: r249163 --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/rs6000.c | 7 ++----- 2 files changed, 8 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9e2bfa4..ba35929 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2017-06-13 Segher Boessenkool + * config/rs6000/rs6000.c (SPE_CONST_OFFSET_OK): Delete. + (rs6000_legitimate_offset_address_p): Return false for anything in + V2SImode or V2SFmode. + +2017-06-13 Segher Boessenkool + * config/rs6000/rs6000-modes.def: Remove all 8-byte vector modes except V2SF and V2SI. Rearrange the vector modes, and add comments. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Remove V8QImode diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index b51ffcc..a1005c0 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -8697,9 +8697,6 @@ legitimate_small_data_p (machine_mode mode, rtx x) && small_data_operand (x, mode)); } -/* SPE offset addressing is limited to 5-bits worth of double words. */ -#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) - bool rs6000_legitimate_offset_address_p (machine_mode mode, rtx x, bool strict, bool worst_case) @@ -8728,8 +8725,8 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x, { case V2SImode: case V2SFmode: - /* SPE vector modes. */ - return SPE_CONST_OFFSET_OK (offset); + /* Paired single modes: offset addressing isn't valid. */ + return false; case DFmode: case DDmode: -- cgit v1.1 From bcfa5d6f8816d1ec7aca6456228063b2b2f0a3ce Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 13 Jun 2017 19:10:57 +0200 Subject: rs6000: Remove t-spe * config/rs6000/t-spe: Delete file. From-SVN: r249164 --- gcc/ChangeLog | 4 +++ gcc/config/rs6000/t-spe | 72 ------------------------------------------------- 2 files changed, 4 insertions(+), 72 deletions(-) delete mode 100644 gcc/config/rs6000/t-spe (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ba35929..a1198c9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-06-13 Segher Boessenkool + * config/rs6000/t-spe: Delete file. + +2017-06-13 Segher Boessenkool + * config/rs6000/rs6000.c (SPE_CONST_OFFSET_OK): Delete. (rs6000_legitimate_offset_address_p): Return false for anything in V2SImode or V2SFmode. diff --git a/gcc/config/rs6000/t-spe b/gcc/config/rs6000/t-spe deleted file mode 100644 index fe5de53..0000000 --- a/gcc/config/rs6000/t-spe +++ /dev/null @@ -1,72 +0,0 @@ -# Multilibs for e500 -# -# Copyright (C) 2003-2017 Free Software Foundation, Inc. -# -# This file is part of GCC. -# -# GCC is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GCC is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# . - -# What we really want are these variants: -# -mcpu=7400 -# -mcpu=7400 -maltivec -mabi=altivec -# -mcpu=7400 -msoft-float -# -msoft-float -# -mno-spe -mabi=no-spe -# -mno-spe -mabi=no-spe -mno-isel -# so we'll need to create exceptions later below. - -MULTILIB_OPTIONS = mcpu=7400 \ - maltivec \ - mabi=altivec \ - msoft-float \ - mno-spe \ - mabi=no-spe \ - mno-isel \ - mlittle - -MULTILIB_DIRNAMES = mpc7400 altivec abi-altivec \ - nof no-spe no-abi-spe no-isel le - -MULTILIB_EXCEPTIONS = maltivec mabi=altivec mno-spe mabi=no-spe mno-isel \ - maltivec/mabi=altivec \ - mcpu=7400/maltivec \ - mcpu=7400/mabi=altivec \ - *mcpu=7400/*mno-spe* \ - *mcpu=7400/*mabi=no-spe* \ - *mcpu=7400/*mno-isel* \ - *maltivec/*msoft-float* \ - *maltivec/*mno-spe* \ - *maltivec/*mabi=no-spe* \ - *maltivec/*mno-isel* \ - *mabi=altivec/*msoft-float* \ - *mabi=altivec/*mno-spe* \ - *mabi=altivec/*mabi=no-spe* \ - *mabi=altivec/*mno-isel* \ - *msoft-float/*mno-spe* \ - *msoft-float/*mabi=no-spe* \ - *msoft-float/*mno-isel* \ - mno-spe/mno-isel \ - mabi=no-spe/mno-isel \ - mno-isel/mlittle \ - mabi=no-spe/mno-isel/mlittle \ - mno-spe/mlittle \ - mabi=spe/mlittle \ - mcpu=7400/mabi=altivec/mlittle \ - mcpu=7400/maltivec/mlittle \ - mabi=no-spe/mlittle \ - mno-spe/mno-isel/mlittle \ - mabi=altivec/mlittle \ - maltivec/mlittle \ - maltivec/mabi=altivec/mlittle -- cgit v1.1 From 37e3456afe7925f4c5574dd0a46648ed26bd8c19 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 13 Jun 2017 19:13:24 +0200 Subject: rs6000: Remove eabispe.h * config/rs6000/eabispe.h: Delete file. From-SVN: r249165 --- gcc/ChangeLog | 4 ++++ gcc/config/rs6000/eabispe.h | 26 -------------------------- 2 files changed, 4 insertions(+), 26 deletions(-) delete mode 100644 gcc/config/rs6000/eabispe.h (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a1198c9..e49e9fd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-06-13 Segher Boessenkool + * config/rs6000/eabispe.h: Delete file. + +2017-06-13 Segher Boessenkool + * config/rs6000/t-spe: Delete file. 2017-06-13 Segher Boessenkool diff --git a/gcc/config/rs6000/eabispe.h b/gcc/config/rs6000/eabispe.h deleted file mode 100644 index db8030a..0000000 --- a/gcc/config/rs6000/eabispe.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Core target definitions for GNU compiler - for PowerPC embedded targeted systems with SPE support. - Copyright (C) 2002-2017 Free Software Foundation, Inc. - Contributed by Aldy Hernandez (aldyh@redhat.com). - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - . */ - -#undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_EABI) - -#undef ASM_DEFAULT_SPEC -#define ASM_DEFAULT_SPEC "-mppc -mspe -me500" -- cgit v1.1 From 22f8f4a94330430f54b756e27c304db47eb4fa0b Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 13 Jun 2017 19:14:25 +0200 Subject: rs6000: Updates to t-linux * config/rs6000/t-linux: Don't handle SPE. From-SVN: r249166 --- gcc/ChangeLog | 4 ++++ gcc/config/rs6000/t-linux | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e49e9fd..153473a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-06-13 Segher Boessenkool + * config/rs6000/t-linux: Don't handle SPE. + +2017-06-13 Segher Boessenkool + * config/rs6000/eabispe.h: Delete file. 2017-06-13 Segher Boessenkool diff --git a/gcc/config/rs6000/t-linux b/gcc/config/rs6000/t-linux index 4cb63bd..acfde1f 100644 --- a/gcc/config/rs6000/t-linux +++ b/gcc/config/rs6000/t-linux @@ -4,12 +4,8 @@ ifeq (,$(filter $(with_cpu),$(SOFT_FLOAT_CPUS))$(findstring soft,$(with_float))) ifneq (,$(findstring powerpc64,$(target))) MULTILIB_OSDIRNAMES := .=../lib64$(call if_multiarch,:powerpc64-linux-gnu) else -ifneq (,$(findstring spe,$(target))) -MULTIARCH_DIRNAME := powerpc-linux-gnuspe$(if $(findstring 8548,$(with_cpu)),,v1) -else MULTIARCH_DIRNAME := powerpc-linux-gnu endif -endif ifneq (,$(findstring powerpcle,$(target))) MULTIARCH_DIRNAME := $(subst -linux,le-linux,$(MULTIARCH_DIRNAME)) endif -- cgit v1.1 From 2f5f2b57e98ec7c3eff13915e8f553c399e21ee7 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 13 Jun 2017 19:15:42 +0200 Subject: rs6000: Updates to t-rtems * config/rs6000/t-rtems: Don't handle SPE. From-SVN: r249167 --- gcc/ChangeLog | 4 ++++ gcc/config/rs6000/t-rtems | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 153473a..89f225e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-06-13 Segher Boessenkool + * config/rs6000/t-rtems: Don't handle SPE. + +2017-06-13 Segher Boessenkool + * config/rs6000/t-linux: Don't handle SPE. 2017-06-13 Segher Boessenkool diff --git a/gcc/config/rs6000/t-rtems b/gcc/config/rs6000/t-rtems index 723c6a3..8290f5c 100644 --- a/gcc/config/rs6000/t-rtems +++ b/gcc/config/rs6000/t-rtems @@ -33,8 +33,8 @@ MULTILIB_DIRNAMES += m32 MULTILIB_OPTIONS += msoft-float MULTILIB_DIRNAMES += nof -MULTILIB_OPTIONS += mno-spe/mno-altivec -MULTILIB_DIRNAMES += nospe noaltivec +MULTILIB_OPTIONS += mno-altivec +MULTILIB_DIRNAMES += noaltivec MULTILIB_MATCHES += ${MULTILIB_MATCHES_ENDIAN} MULTILIB_MATCHES += ${MULTILIB_MATCHES_SYSV} @@ -68,7 +68,7 @@ MULTILIB_REQUIRED += mcpu=604/msoft-float MULTILIB_REQUIRED += mcpu=7400 MULTILIB_REQUIRED += mcpu=7400/msoft-float MULTILIB_REQUIRED += mcpu=8540 -MULTILIB_REQUIRED += mcpu=8540/msoft-float/mno-spe +MULTILIB_REQUIRED += mcpu=8540/msoft-float MULTILIB_REQUIRED += mcpu=860 MULTILIB_REQUIRED += mcpu=e6500/m32 MULTILIB_REQUIRED += mcpu=e6500/m32/msoft-float/mno-altivec -- cgit v1.1 From a1450d5ff285e76d9f04301ccbd44113a2117314 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 13 Jun 2017 19:16:57 +0200 Subject: rs6000: Remove FIXED_SCRATCH * config/rs6000/rs6000.h (FIXED_SCRATCH): Delete. From-SVN: r249168 --- gcc/ChangeLog | 4 ++++ gcc/config/rs6000/rs6000.h | 7 ------- 2 files changed, 4 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 89f225e..53e3acd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-06-13 Segher Boessenkool + * config/rs6000/rs6000.h (FIXED_SCRATCH): Delete. + +2017-06-13 Segher Boessenkool + * config/rs6000/t-rtems: Don't handle SPE. 2017-06-13 Segher Boessenkool diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index edfa546..e8305aa 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1330,13 +1330,6 @@ enum data_align { align_abi, align_opt, align_both }; #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 -/* A fixed register used at epilogue generation to address SPE registers - with negative offsets. The 64-bit load/store instructions on the SPE - only take positive offsets (and small ones at that), so we need to - reserve a register for consing up negative offsets. */ - -#define FIXED_SCRATCH 0 - /* Specify the registers used for certain standard purposes. The values of these macros are register numbers. */ -- cgit v1.1 From d20ae4d7dab9768e5698f948e18ef2bb3042451d Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 13 Jun 2017 19:17:54 +0200 Subject: rs6000: Remove VECTOR_SPE * config/rs6000/rs6000-opts.h (enum rs6000_vector): Delete VECTOR_SPE. * config/rs6000/rs6000.c (rs6000_debug_vector_unit): Delete VECTOR_SPE. From-SVN: r249169 --- gcc/ChangeLog | 5 +++++ gcc/config/rs6000/rs6000-opts.h | 1 - gcc/config/rs6000/rs6000.c | 1 - 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 53e3acd..dfd40da 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-13 Segher Boessenkool + * config/rs6000/rs6000-opts.h (enum rs6000_vector): Delete VECTOR_SPE. + * config/rs6000/rs6000.c (rs6000_debug_vector_unit): Delete VECTOR_SPE. + +2017-06-13 Segher Boessenkool + * config/rs6000/rs6000.h (FIXED_SCRATCH): Delete. 2017-06-13 Segher Boessenkool diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 086217a..6dffe8d 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -150,7 +150,6 @@ enum rs6000_vector { VECTOR_VSX, /* Use VSX for vector processing */ VECTOR_P8_VECTOR, /* Use ISA 2.07 VSX for vector processing */ VECTOR_PAIRED, /* Use paired floating point for vectors */ - VECTOR_SPE, /* Use SPE for vector processing */ VECTOR_OTHER /* Some other vector unit */ }; diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a1005c0..58ef789 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2236,7 +2236,6 @@ rs6000_debug_vector_unit (enum rs6000_vector v) case VECTOR_VSX: ret = "vsx"; break; case VECTOR_P8_VECTOR: ret = "p8_vector"; break; case VECTOR_PAIRED: ret = "paired"; break; - case VECTOR_SPE: ret = "spe"; break; case VECTOR_OTHER: ret = "other"; break; default: ret = "unknown"; break; } -- cgit v1.1 From 6ae036b33000414f273b9ad2a7ca7c1a668d0b31 Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Tue, 13 Jun 2017 19:18:51 +0200 Subject: rs6000: Comment fixes + some leftovers * config/rs6000/rs6000.c: Update all comments that mentioned SPE. (rs6000_expand_builtin): Remove RS6000_BTC_EVSEL. * config/rs6000/rs6000.h (RS6000_BTC_EVSEL): Delete. * config/rs6000/vxworks.h (VXCPU_FOR_8548): Delete. Adjust former use. * config/rs6000/vxworksae.h (VXCPU_FOR_8548): Delete. * config/rs6000/vxworksmils.h (VXCPU_FOR_8548): Delete. From-SVN: r249170 --- gcc/ChangeLog | 9 +++++ gcc/config/rs6000/rs6000.c | 79 ++++++++++++++++------------------------- gcc/config/rs6000/rs6000.h | 5 ++- gcc/config/rs6000/vxworks.h | 8 +---- gcc/config/rs6000/vxworksae.h | 4 --- gcc/config/rs6000/vxworksmils.h | 4 --- 6 files changed, 42 insertions(+), 67 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dfd40da..ab872e1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,14 @@ 2017-06-13 Segher Boessenkool + * config/rs6000/rs6000.c: Update all comments that mentioned SPE. + (rs6000_expand_builtin): Remove RS6000_BTC_EVSEL. + * config/rs6000/rs6000.h (RS6000_BTC_EVSEL): Delete. + * config/rs6000/vxworks.h (VXCPU_FOR_8548): Delete. Adjust former use. + * config/rs6000/vxworksae.h (VXCPU_FOR_8548): Delete. + * config/rs6000/vxworksmils.h (VXCPU_FOR_8548): Delete. + +2017-06-13 Segher Boessenkool + * config/rs6000/rs6000-opts.h (enum rs6000_vector): Delete VECTOR_SPE. * config/rs6000/rs6000.c (rs6000_debug_vector_unit): Delete VECTOR_SPE. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 58ef789..6b28658 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2014,10 +2014,6 @@ rs6000_cpu_name_lookup (const char *name) This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. - For the SPE, GPRs are 64 bits but only 32 bits are visible in - scalar instructions. The upper 32 bits are only available to the - SIMD instructions. - POWER and PowerPC GPRs hold 32 bits worth; PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ @@ -2901,9 +2897,7 @@ rs6000_setup_reg_addr_masks (void) addr_mask |= RELOAD_REG_INDEXED; /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY - addressing. Restrict addressing on SPE for 64-bit types - because of the SUBREG hackery used to address 64-bit floats in - '32-bit' GPRs. If we allow scalars into Altivec registers, + addressing. If we allow scalars into Altivec registers, don't allow PRE_INC, PRE_DEC, or PRE_MODIFY. */ if (TARGET_UPDATE @@ -3171,7 +3165,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_vector_align[TImode] = align64; } - /* TODO add SPE and paired floating point vector support. */ + /* TODO add paired floating point vector support. */ /* Register class constraints for the constraints that depend on compile switches. When the VSX code was added, different constraints were added @@ -3827,8 +3821,7 @@ darwin_rs6000_override_options (void) /* Return the builtin mask of the various options used that could affect which builtins were used. In the past we used target_flags, but we've run out of - bits, and some options like SPE and PAIRED are no longer in - target_flags. */ + bits, and some options like PAIRED are no longer in target_flags. */ HOST_WIDE_INT rs6000_builtin_mask_calculate (void) @@ -5479,8 +5472,7 @@ rs6000_option_override_internal (bool global_init_p) /* Set the builtin mask of the various options used that could affect which builtins were used. In the past we used target_flags, but we've run out - of bits, and some options like SPE and PAIRED are no longer in - target_flags. */ + of bits, and some options like PAIRED are no longer in target_flags. */ rs6000_builtin_mask = rs6000_builtin_mask_calculate (); if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) rs6000_print_builtin_options (stderr, 0, "builtin mask", @@ -11767,7 +11759,6 @@ function_arg_padding (machine_mode mode, const_tree type) However, we're stuck with this because changing the ABI might break existing library interfaces. - Doubleword align SPE vectors. Quadword align Altivec/VSX vectors. Quadword align large synthetic vector types. */ @@ -12188,18 +12179,17 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode, int n_words = rs6000_arg_size (mode, type); int gregno = cum->sysv_gregno; - /* Long long and SPE vectors are put in (r3,r4), (r5,r6), - (r7,r8) or (r9,r10). As does any other 2 word item such - as complex int due to a historical mistake. */ + /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10). + As does any other 2 word item such as complex int due to a + historical mistake. */ if (n_words == 2) gregno += (1 - gregno) & 1; /* Multi-reg args are not split between registers and stack. */ if (gregno + n_words - 1 > GP_ARG_MAX_REG) { - /* Long long and SPE vectors are aligned on the stack. - So are other 2 word items such as complex int due to - a historical mistake. */ + /* Long long is aligned on the stack. So are other 2 word + items such as complex int due to a historical mistake. */ if (n_words == 2) cum->words += cum->words & 1; cum->words += n_words; @@ -12736,9 +12726,9 @@ rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode, int n_words = rs6000_arg_size (mode, type); int gregno = cum->sysv_gregno; - /* Long long and SPE vectors are put in (r3,r4), (r5,r6), - (r7,r8) or (r9,r10). As does any other 2 word item such - as complex int due to a historical mistake. */ + /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10). + As does any other 2 word item such as complex int due to a + historical mistake. */ if (n_words == 2) gregno += (1 - gregno) & 1; @@ -13675,9 +13665,8 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, lab_false = create_artificial_label (input_location); lab_over = create_artificial_label (input_location); - /* Long long and SPE vectors are aligned in the registers. - As are any other 2 gpr item such as complex int due to a - historical mistake. */ + /* Long long is aligned in the registers. As are any other 2 gpr + item such as complex int due to a historical mistake. */ u = reg; if (n_reg == 2 && reg == gpr) { @@ -16623,7 +16612,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case RS6000_BTC_TERNARY: name3 = "ternary"; break; case RS6000_BTC_PREDICATE: name3 = "predicate"; break; case RS6000_BTC_ABS: name3 = "abs"; break; - case RS6000_BTC_EVSEL: name3 = "evsel"; break; case RS6000_BTC_DST: name3 = "dst"; break; } @@ -17011,11 +16999,11 @@ rs6000_init_builtins (void) pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel", pixel_type_node, 8); - /* Paired and SPE builtins are only available if you build a compiler with - the appropriate options, so only create those builtins with the - appropriate compiler option. Create Altivec and VSX builtins on machines - with at least the general purpose extensions (970 and newer) to allow the - use of the target attribute. */ + /* Paired builtins are only available if you build a compiler with the + appropriate options, so only create those builtins with the appropriate + compiler option. Create Altivec and VSX builtins on machines with at + least the general purpose extensions (970 and newer) to allow the use of + the target attribute. */ if (TARGET_PAIRED_FLOAT) paired_init_builtins (); if (TARGET_EXTRA_BUILTINS) @@ -18147,11 +18135,11 @@ rs6000_common_init_builtins (void) builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node; } - /* Paired and SPE builtins are only available if you build a compiler with - the appropriate options, so only create those builtins with the - appropriate compiler option. Create Altivec and VSX builtins on machines - with at least the general purpose extensions (970 and newer) to allow the - use of the target attribute.. */ + /* Paired builtins are only available if you build a compiler with the + appropriate options, so only create those builtins with the appropriate + compiler option. Create Altivec and VSX builtins on machines with at + least the general purpose extensions (970 and newer) to allow the use of + the target attribute.. */ if (TARGET_EXTRA_BUILTINS) builtin_mask |= RS6000_BTM_COMMON; @@ -18395,7 +18383,7 @@ rs6000_common_init_builtins (void) mode0 = insn_data[icode].operand[0].mode; if (mode0 == V2SImode) { - /* code for SPE */ + /* code for paired single */ if (! (type = v2si_ftype)) { v2si_ftype @@ -23109,7 +23097,7 @@ print_operand (FILE *file, rtx x, int code) } return; - /* Print AltiVec or SPE memory operand. */ + /* Print AltiVec memory operand. */ case 'y': { rtx tmp; @@ -26155,10 +26143,6 @@ rs6000_savres_strategy (rs6000_stack_t *info, +---------------------------------------+ | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y +---------------------------------------+ - | SPE: area for 64-bit GP registers | - +---------------------------------------+ - | SPE alignment padding | - +---------------------------------------+ | saved CR (C) | 8+P+A+V+L+X+W+Y+Z +---------------------------------------+ | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C @@ -29956,7 +29940,6 @@ rs6000_emit_epilogue (int sibcall) if (regno == INVALID_REGNUM) break; - /* Note: possible use of r0 here to address SPE regs. */ mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, info->ehrd_offset + frame_off + reg_size * (int) i); @@ -36986,7 +36969,7 @@ altivec_expand_vec_perm_const (rtx operands[4]) return false; } -/* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation. +/* Expand a Paired Single or VSX Permute Doubleword constant permutation. Return true if we match an efficient implementation. */ static bool @@ -37213,10 +37196,8 @@ rs6000_parallel_return (machine_mode mode, /* Target hook for TARGET_FUNCTION_VALUE. - On the SPE, both FPs and vectors are returned in r3. - - On RS/6000 an integer value is in r3 and a floating-point value is in - fp1, unless -msoft-float. */ + An integer value is in r3 and a floating-point value is in fp1, + unless -msoft-float. */ static rtx rs6000_function_value (const_tree valtype, @@ -37428,7 +37409,7 @@ rs6000_initial_elimination_offset (int from, int to) return offset; } -/* Fill in sizes for SPE register high parts in table used by unwinder. */ +/* Fill in sizes of registers used by unwinder. */ static void rs6000_init_dwarf_reg_sizes_extra (tree address) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index e8305aa..9b73be1 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -698,8 +698,8 @@ extern int rs6000_vector_align[]; /* For power systems, we want to enable Altivec and VSX builtins even if the user did not use -maltivec or -mvsx to allow the builtins to be used inside of #pragma GCC target or the target attribute to change the code level for a - given system. The SPE and Paired builtins are only enabled if you configure - the compiler for those builtins, and those machines don't support altivec or + given system. The Paired builtins are only enabled if you configure the + compiler for those builtins, and those machines don't support altivec or VSX. */ #define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \ @@ -2553,7 +2553,6 @@ extern int frame_pointer_needed; #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ -#define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */ #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index ccf6a66..97cc349 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -60,12 +60,6 @@ along with GCC; see the file COPYING3. If not see #define SUBTARGET_EXTRA_SPECS /* none needed */ -/* VxWorks and VxWorksAE (aka 653) expect different CPU values to designate - SPE on 8548. We define a dedicated macro for the base VxWorks here, which - the AE configuration will override. */ - -#define VXCPU_FOR_8548 "PPC85XX" - /* FIXME: The only reason we allow no -mcpu switch at all is because config-ml.in insists on a "." multilib. */ #define CPP_SPEC \ @@ -79,7 +73,7 @@ along with GCC; see the file COPYING3. If not see mcpu=604 : -DCPU=PPC604 ; \ mcpu=860 : -DCPU=PPC860 ; \ mcpu=8540: -DCPU=PPC85XX ; \ - mcpu=8548: -DCPU=" VXCPU_FOR_8548 "; \ + mcpu=8548: -DCPU=PPC85XX ; \ : -DCPU=PPC604 }}" \ VXWORKS_ADDITIONAL_CPP_SPEC diff --git a/gcc/config/rs6000/vxworksae.h b/gcc/config/rs6000/vxworksae.h index 27bf470..9f21e91 100644 --- a/gcc/config/rs6000/vxworksae.h +++ b/gcc/config/rs6000/vxworksae.h @@ -18,10 +18,6 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see . */ -/* VxWorksAE for E500V2 expects a specific CPU value to designate 8548. */ -#undef VXCPU_FOR_8548 -#define VXCPU_FOR_8548 "PPCE500V2" - /* This platform supports the probing method of stack checking and requires 4K of space for executing a possible last chance handler. */ #undef STACK_CHECK_PROTECT diff --git a/gcc/config/rs6000/vxworksmils.h b/gcc/config/rs6000/vxworksmils.h index 7b1e2cc..a14deb4 100644 --- a/gcc/config/rs6000/vxworksmils.h +++ b/gcc/config/rs6000/vxworksmils.h @@ -23,7 +23,3 @@ along with GCC; see the file COPYING3. If not see requires 4K of space for executing a possible last chance handler. */ #undef STACK_CHECK_PROTECT #define STACK_CHECK_PROTECT 4096 - -/* VxWorksMILS for E500V2 expects a specific CPU value to designate 8548. */ -#undef VXCPU_FOR_8548 -#define VXCPU_FOR_8548 "PPC85XX" -- cgit v1.1 From 8a516588143f1b61b66b7ef6181e3b4a9a3077b4 Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Tue, 13 Jun 2017 17:30:58 +0000 Subject: re PR objc/80949 (ICE in do_warn_duplicated_branches_r) PR objc/80949 * c-warn.c (do_warn_duplicated_branches): Return if any of the branches is null. From-SVN: r249171 --- gcc/c-family/ChangeLog | 6 ++++++ gcc/c-family/c-warn.c | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 8488768..9387bb0 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,9 @@ +2017-06-13 Marek Polacek + + PR objc/80949 + * c-warn.c (do_warn_duplicated_branches): Return if any of the + branches is null. + 2017-06-13 Martin Liska PR sanitize/78204 diff --git a/gcc/c-family/c-warn.c b/gcc/c-family/c-warn.c index 35321a6..056a058 100644 --- a/gcc/c-family/c-warn.c +++ b/gcc/c-family/c-warn.c @@ -2354,8 +2354,8 @@ do_warn_duplicated_branches (tree expr) tree thenb = COND_EXPR_THEN (expr); tree elseb = COND_EXPR_ELSE (expr); - /* Don't bother if there's no else branch. */ - if (elseb == NULL_TREE) + /* Don't bother if any of the branches is missing. */ + if (thenb == NULL_TREE || elseb == NULL_TREE) return; /* And don't warn for empty statements. */ -- cgit v1.1 From c60dc05326dbf6960dbaa898db854fd062afeecd Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 13 Jun 2017 22:02:38 +0200 Subject: re PR c++/80984 (ICE with label/variable ambiguity) PR c++/80984 * cp-gimplify.c (cp_genericize): Only look for VAR_DECLs in BLOCK_VARS (outer) chain. (cxx_omp_const_qual_no_mutable): Likewise. * g++.dg/opt/nrv18.C: New test. From-SVN: r249173 --- gcc/cp/ChangeLog | 7 +++++++ gcc/cp/cp-gimplify.c | 6 ++++-- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/opt/nrv18.C | 12 ++++++++++++ 4 files changed, 28 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.dg/opt/nrv18.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 4388830..ae91a9d 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,10 @@ +2017-06-13 Jakub Jelinek + + PR c++/80984 + * cp-gimplify.c (cp_genericize): Only look for VAR_DECLs in + BLOCK_VARS (outer) chain. + (cxx_omp_const_qual_no_mutable): Likewise. + 2017-06-13 Martin Liska PR sanitize/78204 diff --git a/gcc/cp/cp-gimplify.c b/gcc/cp/cp-gimplify.c index 3c8f4b0..d546208 100644 --- a/gcc/cp/cp-gimplify.c +++ b/gcc/cp/cp-gimplify.c @@ -1590,7 +1590,8 @@ cp_genericize (tree fndecl) if (outer) for (var = BLOCK_VARS (outer); var; var = DECL_CHAIN (var)) - if (DECL_NAME (t) == DECL_NAME (var) + if (VAR_P (var) + && DECL_NAME (t) == DECL_NAME (var) && DECL_HAS_VALUE_EXPR_P (var) && DECL_VALUE_EXPR (var) == t) { @@ -1836,7 +1837,8 @@ cxx_omp_const_qual_no_mutable (tree decl) if (outer) for (var = BLOCK_VARS (outer); var; var = DECL_CHAIN (var)) - if (DECL_NAME (decl) == DECL_NAME (var) + if (VAR_P (var) + && DECL_NAME (decl) == DECL_NAME (var) && (TYPE_MAIN_VARIANT (type) == TYPE_MAIN_VARIANT (TREE_TYPE (var)))) { diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1eddf49..5164fa9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-13 Jakub Jelinek + + PR c++/80984 + * g++.dg/opt/nrv18.C: New test. + 2017-06-13 Martin Liska PR sanitize/78204 diff --git a/gcc/testsuite/g++.dg/opt/nrv18.C b/gcc/testsuite/g++.dg/opt/nrv18.C new file mode 100644 index 0000000..92e9bdf --- /dev/null +++ b/gcc/testsuite/g++.dg/opt/nrv18.C @@ -0,0 +1,12 @@ +// PR c++/80984 +// { dg-do compile } + +struct A { ~A (); }; + +A +foo () +{ + A a; +a: + return a; +} -- cgit v1.1 From f31a8339835b2dda14b622cf35555ea666966a9a Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 13 Jun 2017 22:05:20 +0200 Subject: re PR sanitizer/80973 (ICE with lambda and -fsanitize=undefined) PR c++/80973 * cp-gimplify.c (cp_genericize_r): Don't instrument MEM_REF second argument even if it has REFERENCE_TYPE. * g++.dg/ubsan/pr80973.C: New test. From-SVN: r249174 --- gcc/cp/ChangeLog | 4 ++++ gcc/cp/cp-gimplify.c | 10 ++++++++++ gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/g++.dg/ubsan/pr80973.C | 16 ++++++++++++++++ 4 files changed, 33 insertions(+) create mode 100644 gcc/testsuite/g++.dg/ubsan/pr80973.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index ae91a9d..ca0f9b2 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,9 @@ 2017-06-13 Jakub Jelinek + PR c++/80973 + * cp-gimplify.c (cp_genericize_r): Don't instrument MEM_REF second + argument even if it has REFERENCE_TYPE. + PR c++/80984 * cp-gimplify.c (cp_genericize): Only look for VAR_DECLs in BLOCK_VARS (outer) chain. diff --git a/gcc/cp/cp-gimplify.c b/gcc/cp/cp-gimplify.c index d546208..a0abd51 100644 --- a/gcc/cp/cp-gimplify.c +++ b/gcc/cp/cp-gimplify.c @@ -1450,6 +1450,16 @@ cp_genericize_r (tree *stmt_p, int *walk_subtrees, void *data) *stmt_p = cplus_expand_constant (stmt); *walk_subtrees = 0; } + else if (TREE_CODE (stmt) == MEM_REF) + { + /* For MEM_REF, make sure not to sanitize the second operand even + if it has reference type. It is just an offset with a type + holding other information. There is no other processing we + need to do for INTEGER_CSTs, so just ignore the second argument + unconditionally. */ + cp_walk_tree (&TREE_OPERAND (stmt, 0), cp_genericize_r, data, NULL); + *walk_subtrees = 0; + } else if (sanitize_flags_p ((SANITIZE_NULL | SANITIZE_ALIGNMENT | SANITIZE_VPTR)) && !wtd->no_sanitize_p) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5164fa9..f32b8c8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2017-06-13 Jakub Jelinek + PR c++/80973 + * g++.dg/ubsan/pr80973.C: New test. + PR c++/80984 * g++.dg/opt/nrv18.C: New test. diff --git a/gcc/testsuite/g++.dg/ubsan/pr80973.C b/gcc/testsuite/g++.dg/ubsan/pr80973.C new file mode 100644 index 0000000..b534fdb --- /dev/null +++ b/gcc/testsuite/g++.dg/ubsan/pr80973.C @@ -0,0 +1,16 @@ +// PR c++/80973 +// { dg-do compile } +// { dg-options "-fsanitize=undefined -std=c++14" } + +struct A { + A(); + A(const A &); +}; +struct B { + B(); + template auto g(Args &&... p1) { + return [=] { f(p1...); }; + } + void f(A, const char *); +}; +B::B() { g(A(), ""); } -- cgit v1.1 From f3bc6d3ad3e38b4af776f99758341d3406cd811a Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Wed, 14 Jun 2017 00:16:20 +0000 Subject: Daily bump. From-SVN: r249179 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 0cdf576..8df707d 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170613 +20170614 -- cgit v1.1 From 11c16c2a22667d1738e90ac5b754439f03b4dff2 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 14 Jun 2017 08:25:06 +0200 Subject: vrp101.c: Fix scan-tree-dump regex. * gcc.dg/tree-ssa/vrp101.c: Fix scan-tree-dump regex. * gcc.dg/tree-ssa/builtin-sprintf-2.c: Likewise. Adjust comment. From-SVN: r249180 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c | 10 +++++----- gcc/testsuite/gcc.dg/tree-ssa/vrp101.c | 2 +- 3 files changed, 11 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f32b8c8..1378dc8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-14 Jakub Jelinek + + * gcc.dg/tree-ssa/vrp101.c: Fix scan-tree-dump regex. + * gcc.dg/tree-ssa/builtin-sprintf-2.c: Likewise. Adjust comment. + 2017-06-13 Jakub Jelinek PR c++/80973 diff --git a/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c b/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c index e15d88b..17908ac 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c @@ -279,18 +279,18 @@ RNG (0, 6, 8, "%s%ls", "1", L"2"); : result_3 = __builtin_sprintf (&MEM[(void *)&buf8k + 8192B], "%c", 32); if (result_3 != 0) - goto ; [50.0%] + goto ; [50.0%] [count: INV] else - goto ; [50.0%] + goto ; [50.0%] [count: INV] - [50.0%]: + [50.0%] [count: INV]: must_not_eliminate (); */ /* Only conditional calls to must_not_eliminate must be made (with any probability): - { dg-final { scan-tree-dump-times "> \\\[\[0-9.\]+%\\\]\\ \\\[count:\\[^:\\]*\\\]:\n *must_not_eliminate" 127 "optimized" { target { ilp32 || lp64 } } } } - { dg-final { scan-tree-dump-times "> \\\[\[0-9.\]+%\\\]\\ \\\[count:\\[^:\\]*\\\]:\n *must_not_eliminate" 96 "optimized" { target { { ! ilp32 } && { ! lp64 } } } } } + { dg-final { scan-tree-dump-times "> \\\[\[0-9.\]+%\\\] \\\[count: \[^0-9INV\]*\\\]:\n *must_not_eliminate" 127 "optimized" { target { ilp32 || lp64 } } } } + { dg-final { scan-tree-dump-times "> \\\[\[0-9.\]+%\\\] \\\[count: \[^0-9INV\]*\\\]:\n *must_not_eliminate" 96 "optimized" { target { { ! ilp32 } && { ! lp64 } } } } } No unconditional calls to abort should be made: { dg-final { scan-tree-dump-not ";\n *must_not_eliminate" "optimized" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp101.c b/gcc/testsuite/gcc.dg/tree-ssa/vrp101.c index e7cad28..c9feb25 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/vrp101.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp101.c @@ -10,4 +10,4 @@ int main () return 0; } -/* { dg-final { scan-tree-dump " \\\[\[0-9.\]+%\\\] \\\[count: \\[^:\\]*\\\]:\[\n\r \]*return 0;" "optimized" } } */ +/* { dg-final { scan-tree-dump " \\\[\[0-9.\]+%\\\] \\\[count: \[0-9INV\]*\\\]:\[\n\r \]*return 0;" "optimized" } } */ -- cgit v1.1 From 6aa397703c5802b14cbd00c1fd8cfd0b7c15934e Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 14 Jun 2017 08:29:09 +0200 Subject: vrp101.c: Fix scan-tree-dump regex. * gcc.dg/tree-ssa/vrp101.c: Fix scan-tree-dump regex. * gcc.dg/tree-ssa/builtin-sprintf-2.c: Likewise. Adjust comment. From-SVN: r249181 --- gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c b/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c index 17908ac..2323b7f 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-2.c @@ -290,7 +290,7 @@ RNG (0, 6, 8, "%s%ls", "1", L"2"); /* Only conditional calls to must_not_eliminate must be made (with any probability): - { dg-final { scan-tree-dump-times "> \\\[\[0-9.\]+%\\\] \\\[count: \[^0-9INV\]*\\\]:\n *must_not_eliminate" 127 "optimized" { target { ilp32 || lp64 } } } } - { dg-final { scan-tree-dump-times "> \\\[\[0-9.\]+%\\\] \\\[count: \[^0-9INV\]*\\\]:\n *must_not_eliminate" 96 "optimized" { target { { ! ilp32 } && { ! lp64 } } } } } + { dg-final { scan-tree-dump-times "> \\\[\[0-9.\]+%\\\] \\\[count: \[0-9INV\]*\\\]:\n *must_not_eliminate" 127 "optimized" { target { ilp32 || lp64 } } } } + { dg-final { scan-tree-dump-times "> \\\[\[0-9.\]+%\\\] \\\[count: \[0-9INV\]*\\\]:\n *must_not_eliminate" 96 "optimized" { target { { ! ilp32 } && { ! lp64 } } } } } No unconditional calls to abort should be made: { dg-final { scan-tree-dump-not ";\n *must_not_eliminate" "optimized" } } */ -- cgit v1.1 From 24d020bd46fc94b262af4f729aff24fb4ee8aca3 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 14 Jun 2017 07:22:32 +0000 Subject: re PR tree-optimization/81083 (ICE: Unable to coalesce ssa_names 4 and 13 which are marked as MUST COALESCE) 2017-06-14 Richard Biener PR tree-optimization/81083 * tree-ssa-sccvn.c (vn_reference_lookup_3): Do not use abnormals as values. * gcc.dg/torture/pr81083.c: New testcase. From-SVN: r249182 --- gcc/ChangeLog | 6 ++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/torture/pr81083.c | 13 +++++++++++++ gcc/tree-ssa-sccvn.c | 4 +++- 4 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/torture/pr81083.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ab872e1..8960eab 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-14 Richard Biener + + PR tree-optimization/81083 + * tree-ssa-sccvn.c (vn_reference_lookup_3): Do not use abnormals + as values. + 2017-06-13 Segher Boessenkool * config/rs6000/rs6000.c: Update all comments that mentioned SPE. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1378dc8..0bc4384 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-14 Richard Biener + + PR tree-optimization/81083 + * gcc.dg/torture/pr81083.c: New testcase. + 2017-06-14 Jakub Jelinek * gcc.dg/tree-ssa/vrp101.c: Fix scan-tree-dump regex. diff --git a/gcc/testsuite/gcc.dg/torture/pr81083.c b/gcc/testsuite/gcc.dg/torture/pr81083.c new file mode 100644 index 0000000..39c3f63 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr81083.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ + +void a(int arg) +{ + extern struct { int x; } obj; + setjmp(); + obj.x = arg; + arg = arg; + if (obj.x) + func(); + if (obj.x) + func(); +} diff --git a/gcc/tree-ssa-sccvn.c b/gcc/tree-ssa-sccvn.c index ff5c800..419da47 100644 --- a/gcc/tree-ssa-sccvn.c +++ b/gcc/tree-ssa-sccvn.c @@ -2035,7 +2035,9 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void *vr_, ops[1] = bitsize_int (ref->size); ops[2] = bitsize_int (offset - offset2); tree val = vn_nary_build_or_lookup (rcode, vr->type, ops); - if (val) + if (val + && (TREE_CODE (val) != SSA_NAME + || ! SSA_NAME_OCCURS_IN_ABNORMAL_PHI (val))) { vn_reference_t res = vn_reference_lookup_or_insert_for_pieces (vuse, vr->set, vr->type, vr->operands, val); -- cgit v1.1 From 280cace4589e2a44bd42dd52a9ff4273d6083d66 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Wed, 14 Jun 2017 07:44:59 +0000 Subject: * config/sparc/driver-sparc.c (cpu_names): Add SPARC-T5 entry. From-SVN: r249183 --- gcc/ChangeLog | 4 ++++ gcc/config/sparc/driver-sparc.c | 2 ++ 2 files changed, 6 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8960eab..5eb7464 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2017-06-14 Eric Botcazou + + * config/sparc/driver-sparc.c (cpu_names): Add SPARC-T5 entry. + 2017-06-14 Richard Biener PR tree-optimization/81083 diff --git a/gcc/config/sparc/driver-sparc.c b/gcc/config/sparc/driver-sparc.c index 9eca20d..b96ef47 100644 --- a/gcc/config/sparc/driver-sparc.c +++ b/gcc/config/sparc/driver-sparc.c @@ -57,6 +57,7 @@ static const struct cpu_names { { "UltraSPARC-T2+", "niagara2" }, { "SPARC-T3", "niagara3" }, { "SPARC-T4", "niagara4" }, + { "SPARC-T5", "niagara4" }, #else { "SuperSparc", "supersparc" }, { "HyperSparc", "hypersparc" }, @@ -73,6 +74,7 @@ static const struct cpu_names { { "UltraSparc T2", "niagara2" }, { "UltraSparc T3", "niagara3" }, { "UltraSparc T4", "niagara4" }, + { "UltraSparc T5", "niagara4" }, { "LEON", "leon3" }, #endif { "SPARC-M7", "niagara7" }, -- cgit v1.1 From bee9e49f6ccbb2abcfc5fb9f2d16d82132eb6e81 Mon Sep 17 00:00:00 2001 From: Paolo Carlini Date: Wed, 14 Jun 2017 09:18:57 +0000 Subject: =?UTF-8?q?re=20PR=20c++/58541=20([c++11]=20Bogus=20"error:=20rede?= =?UTF-8?q?claration=20...=20differs=20in=20=E2=80=98constexpr=E2=80=99")?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 2017-06-14 Paolo Carlini PR c++/58541 * g++.dg/cpp0x/constexpr-58541.C: New. From-SVN: r249186 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/cpp0x/constexpr-58541.C | 6 ++++++ 2 files changed, 11 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-58541.C (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0bc4384..0f5a293 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-14 Paolo Carlini + + PR c++/58541 + * g++.dg/cpp0x/constexpr-58541.C: New. + 2017-06-14 Richard Biener PR tree-optimization/81083 diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-58541.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-58541.C new file mode 100644 index 0000000..ab951d2 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-58541.C @@ -0,0 +1,6 @@ +// { dg-do compile { target c++11 } } + +struct X { + static constexpr const char x[] = "x"; +}; +const char X::x[]; -- cgit v1.1 From 85c1b6d7c855fd1b76a385af2b7f2c56bf3b7f11 Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Wed, 14 Jun 2017 10:20:07 +0000 Subject: re PR target/71663 (aarch64 Vector initialization can be improved slightly) PR target/71663 gcc * config/aarch64/aarch64.c (aarch64_expand_vector_init): Improve vector initialization code gen for only variable case. gcc/testsuite * gcc.target/aarch64/vect-init-1.c: Newtestcase. * gcc.target/aarch64/vect-init-2.c: Likewise. * gcc.target/aarch64/vect-init-3.c: Likewise. * gcc.target/aarch64/vect-init-4.c: Likewise. * gcc.target/aarch64/vect-init-5.c: Likewise. Co-Authored-By: Naveen H.S From-SVN: r249187 --- gcc/ChangeLog | 7 ++++ gcc/config/aarch64/aarch64.c | 55 ++++++++++++++++++++++++-- gcc/testsuite/ChangeLog | 10 +++++ gcc/testsuite/gcc.target/aarch64/vect-init-1.c | 12 ++++++ gcc/testsuite/gcc.target/aarch64/vect-init-2.c | 12 ++++++ gcc/testsuite/gcc.target/aarch64/vect-init-3.c | 12 ++++++ gcc/testsuite/gcc.target/aarch64/vect-init-4.c | 12 ++++++ gcc/testsuite/gcc.target/aarch64/vect-init-5.c | 12 ++++++ 8 files changed, 128 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/vect-init-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vect-init-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vect-init-3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vect-init-4.c create mode 100644 gcc/testsuite/gcc.target/aarch64/vect-init-5.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5eb7464..8205b0e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-06-14 Andrew Pinski + Naveen H.S + + PR target/71663 + * config/aarch64/aarch64.c (aarch64_expand_vector_init): + Improve vector initialization code gen for only variable case. + 2017-06-14 Eric Botcazou * config/sparc/driver-sparc.c (cpu_names): Add SPARC-T5 entry. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index bce490f..239ba72 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -11707,6 +11707,57 @@ aarch64_expand_vector_init (rtx target, rtx vals) return; } + enum insn_code icode = optab_handler (vec_set_optab, mode); + gcc_assert (icode != CODE_FOR_nothing); + + /* If there are only variable elements, try to optimize + the insertion using dup for the most common element + followed by insertions. */ + + /* The algorithm will fill matches[*][0] with the earliest matching element, + and matches[X][1] with the count of duplicate elements (if X is the + earliest element which has duplicates). */ + + if (n_var == n_elts && n_elts <= 16) + { + int matches[16][2] = {0}; + for (int i = 0; i < n_elts; i++) + { + for (int j = 0; j <= i; j++) + { + if (rtx_equal_p (XVECEXP (vals, 0, i), XVECEXP (vals, 0, j))) + { + matches[i][0] = j; + matches[j][1]++; + break; + } + } + } + int maxelement = 0; + int maxv = 0; + for (int i = 0; i < n_elts; i++) + if (matches[i][1] > maxv) + { + maxelement = i; + maxv = matches[i][1]; + } + + /* Create a duplicate of the most common element. */ + rtx x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, maxelement)); + aarch64_emit_move (target, gen_rtx_VEC_DUPLICATE (mode, x)); + + /* Insert the rest. */ + for (int i = 0; i < n_elts; i++) + { + rtx x = XVECEXP (vals, 0, i); + if (matches[i][0] == maxelement) + continue; + x = copy_to_mode_reg (inner_mode, x); + emit_insn (GEN_FCN (icode) (target, x, GEN_INT (i))); + } + return; + } + /* Initialise a vector which is part-variable. We want to first try to build those lanes which are constant in the most efficient way we can. */ @@ -11740,10 +11791,6 @@ aarch64_expand_vector_init (rtx target, rtx vals) } /* Insert the variable lanes directly. */ - - enum insn_code icode = optab_handler (vec_set_optab, mode); - gcc_assert (icode != CODE_FOR_nothing); - for (int i = 0; i < n_elts; i++) { rtx x = XVECEXP (vals, 0, i); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0f5a293..a41cecf 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2017-06-14 Andrew Pinski + Naveen H.S + + PR target/71663 + * gcc.target/aarch64/vect-init-1.c: Newtestcase. + * gcc.target/aarch64/vect-init-2.c: Likewise. + * gcc.target/aarch64/vect-init-3.c: Likewise. + * gcc.target/aarch64/vect-init-4.c: Likewise. + * gcc.target/aarch64/vect-init-5.c: Likewise. + 2017-06-14 Paolo Carlini PR c++/58541 diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-1.c b/gcc/testsuite/gcc.target/aarch64/vect-init-1.c new file mode 100644 index 0000000..90ba3ae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b, float c, float d) +{ + return (vector float) { a, b, c, d }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-2.c b/gcc/testsuite/gcc.target/aarch64/vect-init-2.c new file mode 100644 index 0000000..0444675 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b, float d) +{ + return (vector float) { a, b, a, d }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-3.c b/gcc/testsuite/gcc.target/aarch64/vect-init-3.c new file mode 100644 index 0000000..b5822b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b) +{ + return (vector float) { a, b, a, b }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-4.c b/gcc/testsuite/gcc.target/aarch64/vect-init-4.c new file mode 100644 index 0000000..09a0095 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b) +{ + return (vector float) { a, b, b, a }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vect-init-5.c b/gcc/testsuite/gcc.target/aarch64/vect-init-5.c new file mode 100644 index 0000000..76d5502 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect-init-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b) +{ + return (vector float) { a, b, a, a }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ -- cgit v1.1 From 934861488090cd5fa80845d9b07c6497e5d7621a Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Wed, 14 Jun 2017 10:40:34 +0000 Subject: simplify-rtx.c (simplify_binary_operation_1): Do not simplify a division of 0 if non-call exceptions are enabled. * simplify-rtx.c (simplify_binary_operation_1) : Do not simplify a division of 0 if non-call exceptions are enabled. From-SVN: r249188 --- gcc/ChangeLog | 5 +++++ gcc/simplify-rtx.c | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8205b0e..c6e6572 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-14 Eric Botcazou + + * simplify-rtx.c (simplify_binary_operation_1) : Do not simplify + a division of 0 if non-call exceptions are enabled. + 2017-06-14 Andrew Pinski Naveen H.S diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index 7cab26a..e8af7f3 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -3194,7 +3194,8 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode, case UDIV: /* 0/x is 0 (or x&0 if x has side-effects). */ - if (trueop0 == CONST0_RTX (mode)) + if (trueop0 == CONST0_RTX (mode) + && !cfun->can_throw_non_call_exceptions) { if (side_effects_p (op1)) return simplify_gen_binary (AND, mode, op1, trueop0); -- cgit v1.1 From 938a807a68f4ee61343b4f0b03b2cc8110d3c0b9 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Wed, 14 Jun 2017 11:22:19 +0000 Subject: sparc.h (MASK_ISA): Add MASK_LEON and MASK_LEON3. * config/sparc/sparc.h (MASK_ISA): Add MASK_LEON and MASK_LEON3. (MASK_FEATURES): New macro. * config/sparc/sparc.c (sparc_option_override): Remove the special handling of -mfpu and generalize it to all MASK_FEATURES switches. From-SVN: r249189 --- gcc/ChangeLog | 7 +++++++ gcc/config/sparc/sparc.c | 20 ++++++-------------- gcc/config/sparc/sparc.h | 9 +++++++-- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/sparc/overflow-4.c | 2 +- 5 files changed, 25 insertions(+), 17 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c6e6572..11e3533 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2017-06-14 Eric Botcazou + * config/sparc/sparc.h (MASK_ISA): Add MASK_LEON and MASK_LEON3. + (MASK_FEATURES): New macro. + * config/sparc/sparc.c (sparc_option_override): Remove the special + handling of -mfpu and generalize it to all MASK_FEATURES switches. + +2017-06-14 Eric Botcazou + * simplify-rtx.c (simplify_binary_operation_1) : Do not simplify a division of 0 if non-call exceptions are enabled. diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 95a64a4..790a036 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1341,7 +1341,6 @@ sparc_option_override (void) }; const struct cpu_table *cpu; unsigned int i; - int fpu; if (sparc_debug_string != NULL) { @@ -1433,8 +1432,6 @@ sparc_option_override (void) call_used_regs [i] = 1; } - fpu = target_flags & MASK_FPU; /* save current -mfpu status */ - /* Set the default CPU. */ if (!global_options_set.x_sparc_cpu_and_features) { @@ -1473,22 +1470,18 @@ sparc_option_override (void) #ifndef HAVE_AS_LEON & ~(MASK_LEON | MASK_LEON3) #endif + & ~(target_flags_explicit & MASK_FEATURES) ); - /* If -mfpu or -mno-fpu was explicitly used, don't override with - the processor default. */ - if (target_flags_explicit & MASK_FPU) - target_flags = (target_flags & ~MASK_FPU) | fpu; - - /* -mvis2 implies -mvis */ + /* -mvis2 implies -mvis. */ if (TARGET_VIS2) target_flags |= MASK_VIS; - /* -mvis3 implies -mvis2 and -mvis */ + /* -mvis3 implies -mvis2 and -mvis. */ if (TARGET_VIS3) target_flags |= MASK_VIS2 | MASK_VIS; - /* -mvis4 implies -mvis3, -mvis2 and -mvis */ + /* -mvis4 implies -mvis3, -mvis2 and -mvis. */ if (TARGET_VIS4) target_flags |= MASK_VIS3 | MASK_VIS2 | MASK_VIS; @@ -1499,15 +1492,14 @@ sparc_option_override (void) | MASK_FMAF); /* -mvis assumes UltraSPARC+, so we are sure v9 instructions - are available. - -m64 also implies v9. */ + are available; -m64 also implies v9. */ if (TARGET_VIS || TARGET_ARCH64) { target_flags |= MASK_V9; target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); } - /* -mvis also implies -mv8plus on 32-bit */ + /* -mvis also implies -mv8plus on 32-bit. */ if (TARGET_VIS && ! TARGET_ARCH64) target_flags |= MASK_V8PLUS; diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 686a3d5..581774e 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -423,10 +423,15 @@ extern enum cmodel sparc_cmodel; #define WCHAR_TYPE_SIZE 16 /* Mask of all CPU selection flags. */ -#define MASK_ISA \ - (MASK_SPARCLITE + MASK_SPARCLET \ +#define MASK_ISA \ + (MASK_SPARCLITE + MASK_SPARCLET + MASK_LEON + MASK_LEON3 \ + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS) +/* Mask of all CPU feature flags. */ +#define MASK_FEATURES \ + (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \ + + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_POPC + MASK_SUBXC) + /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ #define TARGET_HARD_MUL \ (TARGET_SPARCLITE || TARGET_SPARCLET \ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a41cecf..d6fdd84 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-14 Eric Botcazou + + * gcc.target/sparc/overflow-4.c: Add -mno-vis3. + 2017-06-14 Andrew Pinski Naveen H.S diff --git a/gcc/testsuite/gcc.target/sparc/overflow-4.c b/gcc/testsuite/gcc.target/sparc/overflow-4.c index 31b3264..868edea 100644 --- a/gcc/testsuite/gcc.target/sparc/overflow-4.c +++ b/gcc/testsuite/gcc.target/sparc/overflow-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O" } */ +/* { dg-options "-O -mno-vis3" } */ /* { dg-require-effective-target lp64 } */ #include -- cgit v1.1 From c74985e3ee7f30091582908b1bdf3cdec5218897 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 14 Jun 2017 13:24:48 +0200 Subject: cp-gimplify.c (cp_genericize_r): Turn most of the function into a switch (TREE_CODE (stmt)) statement from long... * cp-gimplify.c (cp_genericize_r): Turn most of the function into a switch (TREE_CODE (stmt)) statement from long else if sequence. From-SVN: r249191 --- gcc/cp/ChangeLog | 6 + gcc/cp/cp-gimplify.c | 585 +++++++++++++++++++++++++++------------------------ 2 files changed, 316 insertions(+), 275 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index ca0f9b2..b933392 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2017-06-14 Jakub Jelinek + + * cp-gimplify.c (cp_genericize_r): Turn most of the function + into a switch (TREE_CODE (stmt)) statement from long else if + sequence. + 2017-06-13 Jakub Jelinek PR c++/80973 diff --git a/gcc/cp/cp-gimplify.c b/gcc/cp/cp-gimplify.c index a0abd51..f010f6c 100644 --- a/gcc/cp/cp-gimplify.c +++ b/gcc/cp/cp-gimplify.c @@ -1118,132 +1118,135 @@ cp_genericize_r (tree *stmt_p, int *walk_subtrees, void *data) return NULL_TREE; } - if (TREE_CODE (stmt) == ADDR_EXPR - && is_invisiref_parm (TREE_OPERAND (stmt, 0))) + switch (TREE_CODE (stmt)) { - /* If in an OpenMP context, note var uses. */ - if (__builtin_expect (wtd->omp_ctx != NULL, 0) - && omp_var_to_track (TREE_OPERAND (stmt, 0))) - omp_cxx_notice_variable (wtd->omp_ctx, TREE_OPERAND (stmt, 0)); - *stmt_p = fold_convert (TREE_TYPE (stmt), TREE_OPERAND (stmt, 0)); - *walk_subtrees = 0; - } - else if (TREE_CODE (stmt) == RETURN_EXPR - && TREE_OPERAND (stmt, 0) - && is_invisiref_parm (TREE_OPERAND (stmt, 0))) - /* Don't dereference an invisiref RESULT_DECL inside a RETURN_EXPR. */ - *walk_subtrees = 0; - else if (TREE_CODE (stmt) == OMP_CLAUSE) - switch (OMP_CLAUSE_CODE (stmt)) - { - case OMP_CLAUSE_LASTPRIVATE: - /* Don't dereference an invisiref in OpenMP clauses. */ - if (is_invisiref_parm (OMP_CLAUSE_DECL (stmt))) - { - *walk_subtrees = 0; - if (OMP_CLAUSE_LASTPRIVATE_STMT (stmt)) - cp_walk_tree (&OMP_CLAUSE_LASTPRIVATE_STMT (stmt), - cp_genericize_r, data, NULL); - } - break; - case OMP_CLAUSE_PRIVATE: - /* Don't dereference an invisiref in OpenMP clauses. */ - if (is_invisiref_parm (OMP_CLAUSE_DECL (stmt))) + case ADDR_EXPR: + if (is_invisiref_parm (TREE_OPERAND (stmt, 0))) + { + /* If in an OpenMP context, note var uses. */ + if (__builtin_expect (wtd->omp_ctx != NULL, 0) + && omp_var_to_track (TREE_OPERAND (stmt, 0))) + omp_cxx_notice_variable (wtd->omp_ctx, TREE_OPERAND (stmt, 0)); + *stmt_p = fold_convert (TREE_TYPE (stmt), TREE_OPERAND (stmt, 0)); *walk_subtrees = 0; - else if (wtd->omp_ctx != NULL) - { - /* Private clause doesn't cause any references to the - var in outer contexts, avoid calling - omp_cxx_notice_variable for it. */ - struct cp_genericize_omp_taskreg *old = wtd->omp_ctx; - wtd->omp_ctx = NULL; - cp_walk_tree (&OMP_CLAUSE_DECL (stmt), cp_genericize_r, - data, NULL); - wtd->omp_ctx = old; + } + break; + + case RETURN_EXPR: + if (TREE_OPERAND (stmt, 0) && is_invisiref_parm (TREE_OPERAND (stmt, 0))) + /* Don't dereference an invisiref RESULT_DECL inside a RETURN_EXPR. */ + *walk_subtrees = 0; + break; + + case OMP_CLAUSE: + switch (OMP_CLAUSE_CODE (stmt)) + { + case OMP_CLAUSE_LASTPRIVATE: + /* Don't dereference an invisiref in OpenMP clauses. */ + if (is_invisiref_parm (OMP_CLAUSE_DECL (stmt))) + { + *walk_subtrees = 0; + if (OMP_CLAUSE_LASTPRIVATE_STMT (stmt)) + cp_walk_tree (&OMP_CLAUSE_LASTPRIVATE_STMT (stmt), + cp_genericize_r, data, NULL); + } + break; + case OMP_CLAUSE_PRIVATE: + /* Don't dereference an invisiref in OpenMP clauses. */ + if (is_invisiref_parm (OMP_CLAUSE_DECL (stmt))) *walk_subtrees = 0; - } - break; - case OMP_CLAUSE_SHARED: - case OMP_CLAUSE_FIRSTPRIVATE: - case OMP_CLAUSE_COPYIN: - case OMP_CLAUSE_COPYPRIVATE: - /* Don't dereference an invisiref in OpenMP clauses. */ - if (is_invisiref_parm (OMP_CLAUSE_DECL (stmt))) - *walk_subtrees = 0; - break; - case OMP_CLAUSE_REDUCTION: - /* Don't dereference an invisiref in reduction clause's - OMP_CLAUSE_DECL either. OMP_CLAUSE_REDUCTION_{INIT,MERGE} - still needs to be genericized. */ - if (is_invisiref_parm (OMP_CLAUSE_DECL (stmt))) - { + else if (wtd->omp_ctx != NULL) + { + /* Private clause doesn't cause any references to the + var in outer contexts, avoid calling + omp_cxx_notice_variable for it. */ + struct cp_genericize_omp_taskreg *old = wtd->omp_ctx; + wtd->omp_ctx = NULL; + cp_walk_tree (&OMP_CLAUSE_DECL (stmt), cp_genericize_r, + data, NULL); + wtd->omp_ctx = old; + *walk_subtrees = 0; + } + break; + case OMP_CLAUSE_SHARED: + case OMP_CLAUSE_FIRSTPRIVATE: + case OMP_CLAUSE_COPYIN: + case OMP_CLAUSE_COPYPRIVATE: + /* Don't dereference an invisiref in OpenMP clauses. */ + if (is_invisiref_parm (OMP_CLAUSE_DECL (stmt))) *walk_subtrees = 0; - if (OMP_CLAUSE_REDUCTION_INIT (stmt)) - cp_walk_tree (&OMP_CLAUSE_REDUCTION_INIT (stmt), - cp_genericize_r, data, NULL); - if (OMP_CLAUSE_REDUCTION_MERGE (stmt)) - cp_walk_tree (&OMP_CLAUSE_REDUCTION_MERGE (stmt), - cp_genericize_r, data, NULL); - } - break; - default: - break; - } - else if (IS_TYPE_OR_DECL_P (stmt)) - *walk_subtrees = 0; - - /* Due to the way voidify_wrapper_expr is written, we don't get a chance - to lower this construct before scanning it, so we need to lower these - before doing anything else. */ - else if (TREE_CODE (stmt) == CLEANUP_STMT) - *stmt_p = build2_loc (EXPR_LOCATION (stmt), - CLEANUP_EH_ONLY (stmt) ? TRY_CATCH_EXPR - : TRY_FINALLY_EXPR, - void_type_node, - CLEANUP_BODY (stmt), - CLEANUP_EXPR (stmt)); - - else if (TREE_CODE (stmt) == IF_STMT) - { + break; + case OMP_CLAUSE_REDUCTION: + /* Don't dereference an invisiref in reduction clause's + OMP_CLAUSE_DECL either. OMP_CLAUSE_REDUCTION_{INIT,MERGE} + still needs to be genericized. */ + if (is_invisiref_parm (OMP_CLAUSE_DECL (stmt))) + { + *walk_subtrees = 0; + if (OMP_CLAUSE_REDUCTION_INIT (stmt)) + cp_walk_tree (&OMP_CLAUSE_REDUCTION_INIT (stmt), + cp_genericize_r, data, NULL); + if (OMP_CLAUSE_REDUCTION_MERGE (stmt)) + cp_walk_tree (&OMP_CLAUSE_REDUCTION_MERGE (stmt), + cp_genericize_r, data, NULL); + } + break; + default: + break; + } + break; + + /* Due to the way voidify_wrapper_expr is written, we don't get a chance + to lower this construct before scanning it, so we need to lower these + before doing anything else. */ + case CLEANUP_STMT: + *stmt_p = build2_loc (EXPR_LOCATION (stmt), + CLEANUP_EH_ONLY (stmt) ? TRY_CATCH_EXPR + : TRY_FINALLY_EXPR, + void_type_node, + CLEANUP_BODY (stmt), + CLEANUP_EXPR (stmt)); + break; + + case IF_STMT: genericize_if_stmt (stmt_p); /* *stmt_p has changed, tail recurse to handle it again. */ return cp_genericize_r (stmt_p, walk_subtrees, data); - } - /* COND_EXPR might have incompatible types in branches if one or both - arms are bitfields. Fix it up now. */ - else if (TREE_CODE (stmt) == COND_EXPR) - { - tree type_left - = (TREE_OPERAND (stmt, 1) - ? is_bitfield_expr_with_lowered_type (TREE_OPERAND (stmt, 1)) - : NULL_TREE); - tree type_right - = (TREE_OPERAND (stmt, 2) - ? is_bitfield_expr_with_lowered_type (TREE_OPERAND (stmt, 2)) - : NULL_TREE); - if (type_left - && !useless_type_conversion_p (TREE_TYPE (stmt), - TREE_TYPE (TREE_OPERAND (stmt, 1)))) - { - TREE_OPERAND (stmt, 1) - = fold_convert (type_left, TREE_OPERAND (stmt, 1)); - gcc_assert (useless_type_conversion_p (TREE_TYPE (stmt), - type_left)); - } - if (type_right - && !useless_type_conversion_p (TREE_TYPE (stmt), - TREE_TYPE (TREE_OPERAND (stmt, 2)))) - { - TREE_OPERAND (stmt, 2) - = fold_convert (type_right, TREE_OPERAND (stmt, 2)); - gcc_assert (useless_type_conversion_p (TREE_TYPE (stmt), - type_right)); - } - } + /* COND_EXPR might have incompatible types in branches if one or both + arms are bitfields. Fix it up now. */ + case COND_EXPR: + { + tree type_left + = (TREE_OPERAND (stmt, 1) + ? is_bitfield_expr_with_lowered_type (TREE_OPERAND (stmt, 1)) + : NULL_TREE); + tree type_right + = (TREE_OPERAND (stmt, 2) + ? is_bitfield_expr_with_lowered_type (TREE_OPERAND (stmt, 2)) + : NULL_TREE); + if (type_left + && !useless_type_conversion_p (TREE_TYPE (stmt), + TREE_TYPE (TREE_OPERAND (stmt, 1)))) + { + TREE_OPERAND (stmt, 1) + = fold_convert (type_left, TREE_OPERAND (stmt, 1)); + gcc_assert (useless_type_conversion_p (TREE_TYPE (stmt), + type_left)); + } + if (type_right + && !useless_type_conversion_p (TREE_TYPE (stmt), + TREE_TYPE (TREE_OPERAND (stmt, 2)))) + { + TREE_OPERAND (stmt, 2) + = fold_convert (type_right, TREE_OPERAND (stmt, 2)); + gcc_assert (useless_type_conversion_p (TREE_TYPE (stmt), + type_right)); + } + } + break; - else if (TREE_CODE (stmt) == BIND_EXPR) - { + case BIND_EXPR: if (__builtin_expect (wtd->omp_ctx != NULL, 0)) { tree decl; @@ -1281,113 +1284,118 @@ cp_genericize_r (tree *stmt_p, int *walk_subtrees, void *data) cp_walk_tree (&BIND_EXPR_BODY (stmt), cp_genericize_r, data, NULL); wtd->bind_expr_stack.pop (); - } + break; - else if (TREE_CODE (stmt) == USING_STMT) - { - tree block = NULL_TREE; + case USING_STMT: + { + tree block = NULL_TREE; + + /* Get the innermost inclosing GIMPLE_BIND that has a non NULL + BLOCK, and append an IMPORTED_DECL to its + BLOCK_VARS chained list. */ + if (wtd->bind_expr_stack.exists ()) + { + int i; + for (i = wtd->bind_expr_stack.length () - 1; i >= 0; i--) + if ((block = BIND_EXPR_BLOCK (wtd->bind_expr_stack[i]))) + break; + } + if (block) + { + tree using_directive; + gcc_assert (TREE_OPERAND (stmt, 0)); - /* Get the innermost inclosing GIMPLE_BIND that has a non NULL - BLOCK, and append an IMPORTED_DECL to its - BLOCK_VARS chained list. */ - if (wtd->bind_expr_stack.exists ()) + using_directive = make_node (IMPORTED_DECL); + TREE_TYPE (using_directive) = void_type_node; + + IMPORTED_DECL_ASSOCIATED_DECL (using_directive) + = TREE_OPERAND (stmt, 0); + DECL_CHAIN (using_directive) = BLOCK_VARS (block); + BLOCK_VARS (block) = using_directive; + } + /* The USING_STMT won't appear in GENERIC. */ + *stmt_p = build1 (NOP_EXPR, void_type_node, integer_zero_node); + *walk_subtrees = 0; + } + break; + + case DECL_EXPR: + if (TREE_CODE (DECL_EXPR_DECL (stmt)) == USING_DECL) { - int i; - for (i = wtd->bind_expr_stack.length () - 1; i >= 0; i--) - if ((block = BIND_EXPR_BLOCK (wtd->bind_expr_stack[i]))) - break; + /* Using decls inside DECL_EXPRs are just dropped on the floor. */ + *stmt_p = build1 (NOP_EXPR, void_type_node, integer_zero_node); + *walk_subtrees = 0; } - if (block) + else { - tree using_directive; - gcc_assert (TREE_OPERAND (stmt, 0)); - - using_directive = make_node (IMPORTED_DECL); - TREE_TYPE (using_directive) = void_type_node; - - IMPORTED_DECL_ASSOCIATED_DECL (using_directive) - = TREE_OPERAND (stmt, 0); - DECL_CHAIN (using_directive) = BLOCK_VARS (block); - BLOCK_VARS (block) = using_directive; + tree d = DECL_EXPR_DECL (stmt); + if (VAR_P (d)) + gcc_assert (CP_DECL_THREAD_LOCAL_P (d) == DECL_THREAD_LOCAL_P (d)); } - /* The USING_STMT won't appear in GENERIC. */ - *stmt_p = build1 (NOP_EXPR, void_type_node, integer_zero_node); - *walk_subtrees = 0; - } - - else if (TREE_CODE (stmt) == DECL_EXPR - && TREE_CODE (DECL_EXPR_DECL (stmt)) == USING_DECL) - { - /* Using decls inside DECL_EXPRs are just dropped on the floor. */ - *stmt_p = build1 (NOP_EXPR, void_type_node, integer_zero_node); - *walk_subtrees = 0; - } - else if (TREE_CODE (stmt) == DECL_EXPR) - { - tree d = DECL_EXPR_DECL (stmt); - if (VAR_P (d)) - gcc_assert (CP_DECL_THREAD_LOCAL_P (d) == DECL_THREAD_LOCAL_P (d)); - } - else if (TREE_CODE (stmt) == OMP_PARALLEL - || TREE_CODE (stmt) == OMP_TASK - || TREE_CODE (stmt) == OMP_TASKLOOP) - { - struct cp_genericize_omp_taskreg omp_ctx; - tree c, decl; - splay_tree_node n; + break; - *walk_subtrees = 0; - cp_walk_tree (&OMP_CLAUSES (stmt), cp_genericize_r, data, NULL); - omp_ctx.is_parallel = TREE_CODE (stmt) == OMP_PARALLEL; - omp_ctx.default_shared = omp_ctx.is_parallel; - omp_ctx.outer = wtd->omp_ctx; - omp_ctx.variables = splay_tree_new (splay_tree_compare_decl_uid, 0, 0); - wtd->omp_ctx = &omp_ctx; - for (c = OMP_CLAUSES (stmt); c; c = OMP_CLAUSE_CHAIN (c)) - switch (OMP_CLAUSE_CODE (c)) - { - case OMP_CLAUSE_SHARED: - case OMP_CLAUSE_PRIVATE: - case OMP_CLAUSE_FIRSTPRIVATE: - case OMP_CLAUSE_LASTPRIVATE: - decl = OMP_CLAUSE_DECL (c); - if (decl == error_mark_node || !omp_var_to_track (decl)) + case OMP_PARALLEL: + case OMP_TASK: + case OMP_TASKLOOP: + { + struct cp_genericize_omp_taskreg omp_ctx; + tree c, decl; + splay_tree_node n; + + *walk_subtrees = 0; + cp_walk_tree (&OMP_CLAUSES (stmt), cp_genericize_r, data, NULL); + omp_ctx.is_parallel = TREE_CODE (stmt) == OMP_PARALLEL; + omp_ctx.default_shared = omp_ctx.is_parallel; + omp_ctx.outer = wtd->omp_ctx; + omp_ctx.variables = splay_tree_new (splay_tree_compare_decl_uid, 0, 0); + wtd->omp_ctx = &omp_ctx; + for (c = OMP_CLAUSES (stmt); c; c = OMP_CLAUSE_CHAIN (c)) + switch (OMP_CLAUSE_CODE (c)) + { + case OMP_CLAUSE_SHARED: + case OMP_CLAUSE_PRIVATE: + case OMP_CLAUSE_FIRSTPRIVATE: + case OMP_CLAUSE_LASTPRIVATE: + decl = OMP_CLAUSE_DECL (c); + if (decl == error_mark_node || !omp_var_to_track (decl)) + break; + n = splay_tree_lookup (omp_ctx.variables, (splay_tree_key) decl); + if (n != NULL) + break; + splay_tree_insert (omp_ctx.variables, (splay_tree_key) decl, + OMP_CLAUSE_CODE (c) == OMP_CLAUSE_SHARED + ? OMP_CLAUSE_DEFAULT_SHARED + : OMP_CLAUSE_DEFAULT_PRIVATE); + if (OMP_CLAUSE_CODE (c) != OMP_CLAUSE_PRIVATE && omp_ctx.outer) + omp_cxx_notice_variable (omp_ctx.outer, decl); break; - n = splay_tree_lookup (omp_ctx.variables, (splay_tree_key) decl); - if (n != NULL) + case OMP_CLAUSE_DEFAULT: + if (OMP_CLAUSE_DEFAULT_KIND (c) == OMP_CLAUSE_DEFAULT_SHARED) + omp_ctx.default_shared = true; + default: break; - splay_tree_insert (omp_ctx.variables, (splay_tree_key) decl, - OMP_CLAUSE_CODE (c) == OMP_CLAUSE_SHARED - ? OMP_CLAUSE_DEFAULT_SHARED - : OMP_CLAUSE_DEFAULT_PRIVATE); - if (OMP_CLAUSE_CODE (c) != OMP_CLAUSE_PRIVATE - && omp_ctx.outer) - omp_cxx_notice_variable (omp_ctx.outer, decl); - break; - case OMP_CLAUSE_DEFAULT: - if (OMP_CLAUSE_DEFAULT_KIND (c) == OMP_CLAUSE_DEFAULT_SHARED) - omp_ctx.default_shared = true; - default: - break; - } - if (TREE_CODE (stmt) == OMP_TASKLOOP) - genericize_omp_for_stmt (stmt_p, walk_subtrees, data); - else - cp_walk_tree (&OMP_BODY (stmt), cp_genericize_r, data, NULL); - wtd->omp_ctx = omp_ctx.outer; - splay_tree_delete (omp_ctx.variables); - } - else if (TREE_CODE (stmt) == TRY_BLOCK) - { - *walk_subtrees = 0; - tree try_block = wtd->try_block; - wtd->try_block = stmt; - cp_walk_tree (&TRY_STMTS (stmt), cp_genericize_r, data, NULL); - wtd->try_block = try_block; - cp_walk_tree (&TRY_HANDLERS (stmt), cp_genericize_r, data, NULL); - } - else if (TREE_CODE (stmt) == MUST_NOT_THROW_EXPR) - { + } + if (TREE_CODE (stmt) == OMP_TASKLOOP) + genericize_omp_for_stmt (stmt_p, walk_subtrees, data); + else + cp_walk_tree (&OMP_BODY (stmt), cp_genericize_r, data, NULL); + wtd->omp_ctx = omp_ctx.outer; + splay_tree_delete (omp_ctx.variables); + } + break; + + case TRY_BLOCK: + { + *walk_subtrees = 0; + tree try_block = wtd->try_block; + wtd->try_block = stmt; + cp_walk_tree (&TRY_STMTS (stmt), cp_genericize_r, data, NULL); + wtd->try_block = try_block; + cp_walk_tree (&TRY_HANDLERS (stmt), cp_genericize_r, data, NULL); + } + break; + + case MUST_NOT_THROW_EXPR: /* MUST_NOT_THROW_COND might be something else with TM. */ if (MUST_NOT_THROW_COND (stmt) == NULL_TREE) { @@ -1397,78 +1405,99 @@ cp_genericize_r (tree *stmt_p, int *walk_subtrees, void *data) cp_walk_tree (&TREE_OPERAND (stmt, 0), cp_genericize_r, data, NULL); wtd->try_block = try_block; } - } - else if (TREE_CODE (stmt) == THROW_EXPR) - { - location_t loc = location_of (stmt); - if (TREE_NO_WARNING (stmt)) - /* Never mind. */; - else if (wtd->try_block) - { - if (TREE_CODE (wtd->try_block) == MUST_NOT_THROW_EXPR - && warning_at (loc, OPT_Wterminate, - "throw will always call terminate()") - && cxx_dialect >= cxx11 - && DECL_DESTRUCTOR_P (current_function_decl)) - inform (loc, "in C++11 destructors default to noexcept"); - } - else - { - if (warn_cxx11_compat && cxx_dialect < cxx11 - && DECL_DESTRUCTOR_P (current_function_decl) - && (TYPE_RAISES_EXCEPTIONS (TREE_TYPE (current_function_decl)) - == NULL_TREE) - && (get_defaulted_eh_spec (current_function_decl) - == empty_except_spec)) - warning_at (loc, OPT_Wc__11_compat, - "in C++11 this throw will terminate because " - "destructors default to noexcept"); - } - } - else if (TREE_CODE (stmt) == CONVERT_EXPR) - gcc_assert (!CONVERT_EXPR_VBASE_PATH (stmt)); - else if (TREE_CODE (stmt) == FOR_STMT) - genericize_for_stmt (stmt_p, walk_subtrees, data); - else if (TREE_CODE (stmt) == WHILE_STMT) - genericize_while_stmt (stmt_p, walk_subtrees, data); - else if (TREE_CODE (stmt) == DO_STMT) - genericize_do_stmt (stmt_p, walk_subtrees, data); - else if (TREE_CODE (stmt) == SWITCH_STMT) - genericize_switch_stmt (stmt_p, walk_subtrees, data); - else if (TREE_CODE (stmt) == CONTINUE_STMT) - genericize_continue_stmt (stmt_p); - else if (TREE_CODE (stmt) == BREAK_STMT) - genericize_break_stmt (stmt_p); - else if (TREE_CODE (stmt) == OMP_FOR - || TREE_CODE (stmt) == OMP_SIMD - || TREE_CODE (stmt) == OMP_DISTRIBUTE) - genericize_omp_for_stmt (stmt_p, walk_subtrees, data); - else if (TREE_CODE (stmt) == PTRMEM_CST) - { + break; + + case THROW_EXPR: + { + location_t loc = location_of (stmt); + if (TREE_NO_WARNING (stmt)) + /* Never mind. */; + else if (wtd->try_block) + { + if (TREE_CODE (wtd->try_block) == MUST_NOT_THROW_EXPR + && warning_at (loc, OPT_Wterminate, + "throw will always call terminate()") + && cxx_dialect >= cxx11 + && DECL_DESTRUCTOR_P (current_function_decl)) + inform (loc, "in C++11 destructors default to noexcept"); + } + else + { + if (warn_cxx11_compat && cxx_dialect < cxx11 + && DECL_DESTRUCTOR_P (current_function_decl) + && (TYPE_RAISES_EXCEPTIONS (TREE_TYPE (current_function_decl)) + == NULL_TREE) + && (get_defaulted_eh_spec (current_function_decl) + == empty_except_spec)) + warning_at (loc, OPT_Wc__11_compat, + "in C++11 this throw will terminate because " + "destructors default to noexcept"); + } + } + break; + + case CONVERT_EXPR: + gcc_assert (!CONVERT_EXPR_VBASE_PATH (stmt)); + break; + + case FOR_STMT: + genericize_for_stmt (stmt_p, walk_subtrees, data); + break; + + case WHILE_STMT: + genericize_while_stmt (stmt_p, walk_subtrees, data); + break; + + case DO_STMT: + genericize_do_stmt (stmt_p, walk_subtrees, data); + break; + + case SWITCH_STMT: + genericize_switch_stmt (stmt_p, walk_subtrees, data); + break; + + case CONTINUE_STMT: + genericize_continue_stmt (stmt_p); + break; + + case BREAK_STMT: + genericize_break_stmt (stmt_p); + break; + + case OMP_FOR: + case OMP_SIMD: + case OMP_DISTRIBUTE: + genericize_omp_for_stmt (stmt_p, walk_subtrees, data); + break; + + case PTRMEM_CST: /* By the time we get here we're handing off to the back end, so we don't need or want to preserve PTRMEM_CST anymore. */ *stmt_p = cplus_expand_constant (stmt); *walk_subtrees = 0; - } - else if (TREE_CODE (stmt) == MEM_REF) - { + break; + + case MEM_REF: /* For MEM_REF, make sure not to sanitize the second operand even - if it has reference type. It is just an offset with a type + if it has reference type. It is just an offset with a type holding other information. There is no other processing we need to do for INTEGER_CSTs, so just ignore the second argument unconditionally. */ cp_walk_tree (&TREE_OPERAND (stmt, 0), cp_genericize_r, data, NULL); *walk_subtrees = 0; - } - else if (sanitize_flags_p ((SANITIZE_NULL - | SANITIZE_ALIGNMENT | SANITIZE_VPTR)) - && !wtd->no_sanitize_p) - { - if (sanitize_flags_p (SANITIZE_NULL | SANITIZE_ALIGNMENT) - && TREE_CODE (stmt) == NOP_EXPR + break; + + case NOP_EXPR: + if (!wtd->no_sanitize_p + && sanitize_flags_p (SANITIZE_NULL | SANITIZE_ALIGNMENT) && TREE_CODE (TREE_TYPE (stmt)) == REFERENCE_TYPE) ubsan_maybe_instrument_reference (stmt_p); - else if (TREE_CODE (stmt) == CALL_EXPR) + break; + + case CALL_EXPR: + if (!wtd->no_sanitize_p + && sanitize_flags_p ((SANITIZE_NULL + | SANITIZE_ALIGNMENT | SANITIZE_VPTR))) { tree fn = CALL_EXPR_FN (stmt); if (fn != NULL_TREE @@ -1486,6 +1515,12 @@ cp_genericize_r (tree *stmt_p, int *walk_subtrees, void *data) cp_ubsan_maybe_instrument_member_call (stmt); } } + break; + + default: + if (IS_TYPE_OR_DECL_P (stmt)) + *walk_subtrees = 0; + break; } p_set->add (*stmt_p); -- cgit v1.1 From 909263f855ae056b49b8fbbbcf594d7e9b90b434 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 14 Jun 2017 11:40:20 +0000 Subject: re PR middle-end/81088 (UBSAN: false positive as a result of reassosiation) 2017-06-14 Richard Biener PR middle-end/81088 * fold-const.c (split_tree): Drop TREE_OVERFLOW flag from literal constants. (fold_binary_loc): When associating do not treat pre-existing TREE_OVERFLOW on literal constants as a reason to allow TREE_OVERFLOW on associated literal constants. * c-c++-common/ubsan/pr81088.c: New testcase. From-SVN: r249192 --- gcc/ChangeLog | 9 +++++++++ gcc/fold-const.c | 17 +++++++++-------- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/c-c++-common/ubsan/pr81088.c | 11 +++++++++++ 4 files changed, 34 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/ubsan/pr81088.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 11e3533..09a1b98 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2017-06-14 Richard Biener + + PR middle-end/81088 + * fold-const.c (split_tree): Drop TREE_OVERFLOW flag from + literal constants. + (fold_binary_loc): When associating do not treat pre-existing + TREE_OVERFLOW on literal constants as a reason to allow + TREE_OVERFLOW on associated literal constants. + 2017-06-14 Eric Botcazou * config/sparc/sparc.h (MASK_ISA): Add MASK_LEON and MASK_LEON3. diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 74bbdb0..8559b1d 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -880,6 +880,13 @@ split_tree (location_t loc, tree in, tree type, enum tree_code code, } } + if (*litp + && TREE_OVERFLOW_P (*litp)) + *litp = drop_tree_overflow (*litp); + if (*minus_litp + && TREE_OVERFLOW_P (*minus_litp)) + *minus_litp = drop_tree_overflow (*minus_litp); + return var; } @@ -9703,11 +9710,6 @@ fold_binary_loc (location_t loc, + (lit0 != 0) + (lit1 != 0) + (minus_lit0 != 0) + (minus_lit1 != 0)))) { - bool any_overflows = false; - if (lit0) any_overflows |= TREE_OVERFLOW (lit0); - if (lit1) any_overflows |= TREE_OVERFLOW (lit1); - if (minus_lit0) any_overflows |= TREE_OVERFLOW (minus_lit0); - if (minus_lit1) any_overflows |= TREE_OVERFLOW (minus_lit1); var0 = associate_trees (loc, var0, var1, code, atype); con0 = associate_trees (loc, con0, con1, code, atype); lit0 = associate_trees (loc, lit0, lit1, code, atype); @@ -9738,9 +9740,8 @@ fold_binary_loc (location_t loc, } /* Don't introduce overflows through reassociation. */ - if (!any_overflows - && ((lit0 && TREE_OVERFLOW_P (lit0)) - || (minus_lit0 && TREE_OVERFLOW_P (minus_lit0)))) + if ((lit0 && TREE_OVERFLOW_P (lit0)) + || (minus_lit0 && TREE_OVERFLOW_P (minus_lit0))) return NULL_TREE; if (minus_lit0) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d6fdd84..bd241de 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-14 Richard Biener + + PR middle-end/81088 + * c-c++-common/ubsan/pr81088.c: New testcase. + 2017-06-14 Eric Botcazou * gcc.target/sparc/overflow-4.c: Add -mno-vis3. diff --git a/gcc/testsuite/c-c++-common/ubsan/pr81088.c b/gcc/testsuite/c-c++-common/ubsan/pr81088.c new file mode 100644 index 0000000..6753d77 --- /dev/null +++ b/gcc/testsuite/c-c++-common/ubsan/pr81088.c @@ -0,0 +1,11 @@ +/* { dg-do run } */ +/* { dg-options "-fsanitize=undefined -fsanitize-undefined-trap-on-error" } */ + +short s = 2; +short y = 1; +int i; +int main() +{ + i = -(s + (int)(~(unsigned)(0 / y))) + 0x7fffffff; + return 0; +} -- cgit v1.1 From 26fda5f59aa242dcf11cf4dd7ef837c635c02673 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 14 Jun 2017 11:43:31 +0000 Subject: re PR tree-optimization/81083 (ICE: Unable to coalesce ssa_names 4 and 13 which are marked as MUST COALESCE) 2017-06-14 Richard Biener PR tree-optimization/81083 * gcc.dg/torture/pr81083.c: Add prototypes. From-SVN: r249193 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/torture/pr81083.c | 2 ++ 2 files changed, 7 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index bd241de..a0c522e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2017-06-14 Richard Biener + PR tree-optimization/81083 + * gcc.dg/torture/pr81083.c: Add prototypes. + +2017-06-14 Richard Biener + PR middle-end/81088 * c-c++-common/ubsan/pr81088.c: New testcase. diff --git a/gcc/testsuite/gcc.dg/torture/pr81083.c b/gcc/testsuite/gcc.dg/torture/pr81083.c index 39c3f63..53f96a3 100644 --- a/gcc/testsuite/gcc.dg/torture/pr81083.c +++ b/gcc/testsuite/gcc.dg/torture/pr81083.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ +void setjmp(); +void func(); void a(int arg) { extern struct { int x; } obj; -- cgit v1.1 From 6916d6104ff448f07130597473356334c3d73501 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 14 Jun 2017 13:37:48 +0000 Subject: compiler: remove "DIR/../" when joining relative import path Otherwise if DIR does not exist, the path does not work. This matches what the gc cmd/compile tool does, because it calls path.Join. The test for this is the cmd/go tests, to be added in a follow-up CL. Reviewed-on: https://go-review.googlesource.com/45691 From-SVN: r249194 --- gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/import.cc | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 2d9adaf..4365d6e 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -be5fa26b2b1b5d0755bc1c7ce25f3aa26bea9d9c +c0840d5826abb713487b2d8a04ab249764b21010 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. diff --git a/gcc/go/gofrontend/import.cc b/gcc/go/gofrontend/import.cc index f6b4e0c..20b077f 100644 --- a/gcc/go/gofrontend/import.cc +++ b/gcc/go/gofrontend/import.cc @@ -82,6 +82,25 @@ Import::open_package(const std::string& filename, Location location, // A special case. fn = relative_import_path; } + else if (fn[0] == '.' && fn[1] == '.' + && (fn[2] == '\0' || IS_DIR_SEPARATOR(fn[2]))) + { + // We are going to join relative_import_path and fn, and it + // will look like DIR/../PATH. But DIR does not necessarily + // exist in this case, and if it doesn't the use of .. will + // fail although it shouldn't. The gc compiler uses + // path.Join here, which cleans up the .., so we need to do + // the same. + size_t index; + for (index = relative_import_path.length() - 1; + index > 0 && !IS_DIR_SEPARATOR(relative_import_path[index]); + index--) + ; + if (index > 0) + fn = relative_import_path.substr(0, index) + fn.substr(2); + else + fn = relative_import_path + '/' + fn; + } else fn = relative_import_path + '/' + fn; is_local = false; -- cgit v1.1 From 0818233f800920bf4d5c384718b6fb328bba81fe Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 14 Jun 2017 13:47:28 +0000 Subject: internal/testenv: support testing gccgo If GO_TESTING_GOTOOLS is set in the environment, permit tests using gccgo to run the go tool. Like GO_BUILDER_NAME, this should not be set normally. But it is needed when testing the go tool itself, and will be set by the gotools Makefile in a future CL. Reviewed-on: https://go-review.googlesource.com/45693 From-SVN: r249195 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 4365d6e..21bf5f2 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -c0840d5826abb713487b2d8a04ab249764b21010 +6d1d558109b5f5e53b31cc3325485dbb9f06d430 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From b205ec303fc93ba64c0991f64a44e7773f68c38a Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 14 Jun 2017 13:50:53 +0000 Subject: go/build: use GCCGOTOOLDIR to find gccgo tools Add the environment variable GCCGOTOOLDIR to permit overriding the default directory where tools like cgo are found when building with gccgo. This will be used by the cmd/go tests in a future CL. Reviewed-on: https://go-review.googlesource.com/45694 From-SVN: r249196 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 21bf5f2..b73c3e1 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -6d1d558109b5f5e53b31cc3325485dbb9f06d430 +a790c5fec06ced726c7f0f597186883ce61d0a45 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 8ba20d7eb85ac1703d97c9a6660f055788a7a7a6 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 14 Jun 2017 13:53:43 +0000 Subject: cmd/go: skip tests that do not work with gccgo These tests fail for various reasons, most commonly because gccgo doesn't really have GOROOT, so things like `go build errors` fail. Reviewed-on: https://go-review.googlesource.com/45696 From-SVN: r249197 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index b73c3e1..0c1a5cf 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -a790c5fec06ced726c7f0f597186883ce61d0a45 +6b08348d905bf84a91b8d693ee01b30e8bf18ccf The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 1279f21fc520cc8c91ef4dd3a8938b7aa256d799 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 14 Jun 2017 13:56:04 +0000 Subject: cmd/go: gccgo: consistent results, fix vendoring Pass the -fdebug-prefix-map and -gno-record-gcc-switches compiler options to gccgo to generate consistent results. Fix the vendoring code to look for /vendor/, not just /vendor, to avoid being confused by something like vendor/vendor.org. Tested by the cmd/go tests in a followup CL. Reviewed-on: https://go-review.googlesource.com/45695 From-SVN: r249198 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 0c1a5cf..f1055bc 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -6b08348d905bf84a91b8d693ee01b30e8bf18ccf +bc785455a35bfa7d4b0a66781c7c3ef08a24a845 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From ea9a08f5dfbab28de2eabfeb684b42c0615cd99d Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 14 Jun 2017 13:59:02 +0000 Subject: cmd/cgo: make _cgo_flags consistent across runs The go tool will pass -I objdir as one of the flags, where objdir is the temporary build directory. Remove that from _cgo_flags: we don't need it, and it will be different each time. Sort the flags to avoid the unpredictable map iteration order. This matters for gccgo because for a package that uses cgo, the go tool when building for gccgo will store the _cgo_flags file in the archive. That means that we want to generate identical _cgo_flags for every run. The test for this is the cmd/go testsuite, to follow in a future CL. Reviewed-on: https://go-review.googlesource.com/45692 From-SVN: r249199 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index f1055bc..1f600d3 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -bc785455a35bfa7d4b0a66781c7c3ef08a24a845 +372e75503c1dc9a38d9978aa6b67631283d5d6dd The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 4524009c09ac5148643c1226f6868ef38cc44e6c Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Wed, 14 Jun 2017 14:51:46 +0000 Subject: Improve Cortex-A53 FP scheduler The Cortex-A53 scheduler model of FMAC bypass is not quite right for FMAC to FMAC forwarding. Experiments also show the latencies of FP operations are too high as well. Rather than adding more bypasses, adjust the latencies of FP instructions to get a better schedule on average. As a result SPECFP2006 is 1.1% faster. gcc/ * config/arm/cortex-a53.md (cortex_a53_fpalu) Adjust latency. (cortex_a53_fconst): Likewise. (cortex_a53_fpmul): Likewise. (cortex_a53_f_load_64): Likewise. (cortex_a53_f_load_many): Likewise. (cortex_a53_advsimd_alu): Likewise. (cortex_a53_advsimd_alu_q): Likewise. (cortex_a53_advsimd_mul): Likewise. (cortex_a53_advsimd_mul_q): Likewise. (fpmac bypass): Add new bypass for fpmac-fpmac case. Add missing fmul, r2f_cvt and fconst cases. From-SVN: r249200 --- gcc/ChangeLog | 14 ++++++++++++++ gcc/config/arm/cortex-a53.md | 34 ++++++++++++++++------------------ 2 files changed, 30 insertions(+), 18 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 09a1b98..59ca506 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2017-06-14 Wilco Dijkstra + + * config/arm/cortex-a53.md (cortex_a53_fpalu) Adjust latency. + (cortex_a53_fconst): Likewise. + (cortex_a53_fpmul): Likewise. + (cortex_a53_f_load_64): Likewise. + (cortex_a53_f_load_many): Likewise. + (cortex_a53_advsimd_alu): Likewise. + (cortex_a53_advsimd_alu_q): Likewise. + (cortex_a53_advsimd_mul): Likewise. + (cortex_a53_advsimd_mul_q): Likewise. + (fpmac bypass): Add new bypass for fpmac-fpmac case. + Add missing fmul, r2f_cvt and fconst cases. + 2017-06-14 Richard Biener PR middle-end/81088 diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index b7e0c92..ff16e36 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -511,19 +511,19 @@ ;; Floating-point arithmetic. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn_reservation "cortex_a53_fpalu" 5 +(define_insn_reservation "cortex_a53_fpalu" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, f_cvt, fcmps, fcmpd, fccmps, fccmpd, fcsel, f_rints, f_rintd, f_minmaxs, f_minmaxd")) "cortex_a53_slot_any,cortex_a53_fp_alu") -(define_insn_reservation "cortex_a53_fconst" 3 +(define_insn_reservation "cortex_a53_fconst" 2 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "fconsts,fconstd")) "cortex_a53_slot_any,cortex_a53_fp_alu") -(define_insn_reservation "cortex_a53_fpmul" 5 +(define_insn_reservation "cortex_a53_fpmul" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "fmuls,fmuld")) "cortex_a53_slot_any,cortex_a53_fp_mul") @@ -574,7 +574,7 @@ ;; Floating-point load/store. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn_reservation "cortex_a53_f_load_64" 4 +(define_insn_reservation "cortex_a53_f_load_64" 3 (and (eq_attr "tune" "cortexa53") (ior (eq_attr "type" "f_loads,f_loadd") (eq_attr "cortex_a53_advsimd_type" @@ -582,7 +582,7 @@ "cortex_a53_slot_any+cortex_a53_ls_agen, cortex_a53_load") -(define_insn_reservation "cortex_a53_f_load_many" 5 +(define_insn_reservation "cortex_a53_f_load_many" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "cortex_a53_advsimd_type" "advsimd_load_128,advsimd_load_lots")) @@ -616,22 +616,22 @@ ;; or a 128-bit operation in which case we require in our model that we ;; issue from slot 0. -(define_insn_reservation "cortex_a53_advsimd_alu" 5 +(define_insn_reservation "cortex_a53_advsimd_alu" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "cortex_a53_advsimd_type" "advsimd_alu")) "cortex_a53_slot_any,cortex_a53_fp_alu") -(define_insn_reservation "cortex_a53_advsimd_alu_q" 5 +(define_insn_reservation "cortex_a53_advsimd_alu_q" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "cortex_a53_advsimd_type" "advsimd_alu_q")) "cortex_a53_slot0,cortex_a53_fp_alu_q") -(define_insn_reservation "cortex_a53_advsimd_mul" 5 +(define_insn_reservation "cortex_a53_advsimd_mul" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "cortex_a53_advsimd_type" "advsimd_mul")) "cortex_a53_slot_any,cortex_a53_fp_mul") -(define_insn_reservation "cortex_a53_advsimd_mul_q" 5 +(define_insn_reservation "cortex_a53_advsimd_mul_q" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "cortex_a53_advsimd_type" "advsimd_mul_q")) "cortex_a53_slot0,cortex_a53_fp_mul_q") @@ -710,20 +710,18 @@ ;; multiply-accumulate operations as a bypass reducing the latency ;; of producing instructions to near zero. -(define_bypass 1 "cortex_a53_fp*, +(define_bypass 1 "cortex_a53_fpalu, + cortex_a53_fpmul, cortex_a53_r2f, + cortex_a53_r2f_cvt, + cortex_a53_fconst, cortex_a53_f_load*" "cortex_a53_fpmac" "aarch_accumulator_forwarding") -;; Model a bypass from the result of an FP operation to a use. - -(define_bypass 4 "cortex_a53_fpalu, - cortex_a53_fpmul" - "cortex_a53_fpalu, - cortex_a53_fpmul, - cortex_a53_fpmac, - cortex_a53_advsimd_div*") +(define_bypass 4 "cortex_a53_fpmac" + "cortex_a53_fpmac" + "aarch_accumulator_forwarding") ;; We want AESE and AESMC to end up consecutive to one another. -- cgit v1.1 From e72c4afd99c06e29b4f73f61ee0ff9091bf7fa02 Mon Sep 17 00:00:00 2001 From: Boris Kolpackov Date: Wed, 14 Jun 2017 16:05:57 +0000 Subject: Recognize '-' as special -MF argument (write to stdout) Sometimes it is useful to generate pre-processed output to a file and the dependency information to stdout for further analysis/processing. For example: g++ -E -MD -fdirectives-only -o test.ii test.cxx This will generate the dependency information to test.d (as per the documentation). While changing this behavior is probably unwise, one traditional (e.g., supported by -o) way to handle this is to recognize the special '-' file name as an instruction to write to stdout: g++ -E -MD -fdirectives-only -o test.ii -MF - test.cxx Currently this will create a file named '-'. The included patch changes this behavior to write to stdout. Note also that Clang has supported this from at least version 3.5. gcc: 2017-06-14 Boris Kolpackov * doc/cppopts.texi: Document '-' special value to -MF. gcc/c-family: 2017-06-14 Boris Kolpackov * c-opts.c (c_common_finish): Handle '-' special value to -MF. From-SVN: r249201 --- gcc/ChangeLog | 4 ++++ gcc/c-family/ChangeLog | 4 ++++ gcc/c-family/c-opts.c | 4 +++- gcc/doc/cppopts.texi | 2 ++ 4 files changed, 13 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 59ca506..2987e5e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2017-06-14 Boris Kolpackov + + * doc/cppopts.texi: Document '-' special value to -MF. + 2017-06-14 Wilco Dijkstra * config/arm/cortex-a53.md (cortex_a53_fpalu) Adjust latency. diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 9387bb0..1eba1c6 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,7 @@ +2017-06-14 Boris Kolpackov + + * c-opts.c (c_common_finish): Handle '-' special value to -MF. + 2017-06-13 Marek Polacek PR objc/80949 diff --git a/gcc/c-family/c-opts.c b/gcc/c-family/c-opts.c index be4478f..1657e7a 100644 --- a/gcc/c-family/c-opts.c +++ b/gcc/c-family/c-opts.c @@ -1150,6 +1150,8 @@ c_common_finish (void) output stream. */ if (!deps_file) deps_stream = out_stream; + else if (deps_file[0] == '-' && deps_file[1] == '\0') + deps_stream = stdout; else { deps_stream = fopen (deps_file, deps_append ? "a": "w"); @@ -1163,7 +1165,7 @@ c_common_finish (void) with cpp_destroy (). */ cpp_finish (parse_in, deps_stream); - if (deps_stream && deps_stream != out_stream + if (deps_stream && deps_stream != out_stream && deps_stream != stdout && (ferror (deps_stream) || fclose (deps_stream))) fatal_error (input_location, "closing dependency file %s: %m", deps_file); diff --git a/gcc/doc/cppopts.texi b/gcc/doc/cppopts.texi index 0497712..16bf22a 100644 --- a/gcc/doc/cppopts.texi +++ b/gcc/doc/cppopts.texi @@ -125,6 +125,8 @@ preprocessed output. When used with the driver options @option{-MD} or @option{-MMD}, @option{-MF} overrides the default dependency output file. +If @var{file} is @file{-}, then the dependencies are written to @file{stdout}. + @item -MG @opindex MG In conjunction with an option such as @option{-M} requesting -- cgit v1.1 From 1a711a0b5cb291d875acc4b46a4a39ea9185eff3 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 14 Jun 2017 17:19:44 +0000 Subject: gcc: xtensa: allow XCHAL_* macros to be non-constant XCHAL_* macros from the xtensa-config.h are used in a number of places that require them to be preprocessor constants. Rewrite these places so that non-constant XCHAL_* definitions could be used there. 2017-06-14 Max Filippov gcc/ * config/xtensa/xtensa.c (xtensa_option_override): Append MASK_CONST16 to target_flags in the absence of TARGET_L32R. (hwloop_optimize, hwloop_fail, hwloop_pattern_reg, xtensa_doloop_hooks): Define unconditionally. (xtensa_reorg_loops): Only call reorg_loops in the presence of TARGET_LOOPS. * config/xtensa/xtensa.h (TARGET_L32R): New definition. (TARGET_DEFAULT): Remove XCHAL_HAVE_L32R condition and account for it in xtensa_option_override. (HARD_FRAME_POINTER_IS_FRAME_POINTER, HARD_FRAME_POINTER_IS_ARG_POINTER): New definitions. From-SVN: r249202 --- gcc/ChangeLog | 14 ++++++++++++++ gcc/config/xtensa/xtensa.c | 18 +++++++++--------- gcc/config/xtensa/xtensa.h | 11 ++++++++--- 3 files changed, 31 insertions(+), 12 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2987e5e..09435d0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2017-06-14 Max Filippov + + * config/xtensa/xtensa.c (xtensa_option_override): Append + MASK_CONST16 to target_flags in the absence of TARGET_L32R. + (hwloop_optimize, hwloop_fail, hwloop_pattern_reg, + xtensa_doloop_hooks): Define unconditionally. + (xtensa_reorg_loops): Only call reorg_loops in the presence of + TARGET_LOOPS. + * config/xtensa/xtensa.h (TARGET_L32R): New definition. + (TARGET_DEFAULT): Remove XCHAL_HAVE_L32R condition and account + for it in xtensa_option_override. + (HARD_FRAME_POINTER_IS_FRAME_POINTER, + HARD_FRAME_POINTER_IS_ARG_POINTER): New definitions. + 2017-06-14 Boris Kolpackov * doc/cppopts.texi: Document '-' special value to -MF. diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c index 16f8311..cf9a3a7 100644 --- a/gcc/config/xtensa/xtensa.c +++ b/gcc/config/xtensa/xtensa.c @@ -2182,6 +2182,13 @@ xtensa_option_override (void) int regno; machine_mode mode; + /* Use CONST16 in the absence of L32R. + Set it in the TARGET_OPTION_OVERRIDE to avoid dependency on xtensa + configuration in the xtensa-common.c */ + + if (!TARGET_L32R) + target_flags |= MASK_CONST16; + if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT) error ("boolean registers required for the floating-point option"); @@ -4078,8 +4085,6 @@ xtensa_invalid_within_doloop (const rtx_insn *insn) /* Optimize LOOP. */ -#if TARGET_LOOPS - static bool hwloop_optimize (hwloop_info loop) { @@ -4266,14 +4271,9 @@ static struct hw_doloop_hooks xtensa_doloop_hooks = static void xtensa_reorg_loops (void) { - reorg_loops (false, &xtensa_doloop_hooks); -} -#else -static inline void -xtensa_reorg_loops (void) -{ + if (TARGET_LOOPS) + reorg_loops (false, &xtensa_doloop_hooks); } -#endif /* Implement the TARGET_MACHINE_DEPENDENT_REORG pass. */ diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index 08457a4..06dc82c 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -66,10 +66,9 @@ along with GCC; see the file COPYING3. If not see #define TARGET_LOOPS XCHAL_HAVE_LOOPS #define TARGET_WINDOWED_ABI (XSHAL_ABI == XTHAL_ABI_WINDOWED) #define TARGET_DEBUG XCHAL_HAVE_DEBUG +#define TARGET_L32R XCHAL_HAVE_L32R -#define TARGET_DEFAULT \ - ((XCHAL_HAVE_L32R ? 0 : MASK_CONST16) | \ - MASK_SERIALIZE_VOLATILE) +#define TARGET_DEFAULT (MASK_SERIALIZE_VOLATILE) #ifndef HAVE_AS_TLS #define HAVE_AS_TLS 0 @@ -362,6 +361,12 @@ extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17) +/* Hard frame pointer is neither frame nor arg pointer. + The definitions are here because actual hard frame pointer register + definition is not a preprocessor constant. */ +#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 +#define HARD_FRAME_POINTER_IS_ARG_POINTER 0 + /* For now we don't try to use the full set of boolean registers. Without software pipelining of FP operations, there's not much to gain and it's a real pain to get them reloaded. */ -- cgit v1.1 From 3466430f382b6adc2363721056b9abde3acd790a Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Wed, 14 Jun 2017 23:26:40 +0000 Subject: MIPS16/GCC: Emit bounds checking as RTL in `casesi' gcc/ * config/mips/mips.md (MIPS16_T_REGNUM): Remove constant. (casesi): Emit bounds checking as RTL. (casesi_internal_mips16_): Remove bounds checking. gcc/testsuite/ * gcc.target/mips/data-sym-jump.c: Adjust for whitespace changes. * gcc.target/mips/pr51513-1.c: New test. * gcc.target/mips/pr51513-2.c: New test. From-SVN: r249207 --- gcc/ChangeLog | 6 +++ gcc/config/mips/mips.md | 58 +++++++++++---------------- gcc/testsuite/ChangeLog | 6 +++ gcc/testsuite/gcc.target/mips/data-sym-jump.c | 4 +- gcc/testsuite/gcc.target/mips/pr51513-1.c | 48 ++++++++++++++++++++++ gcc/testsuite/gcc.target/mips/pr51513-2.c | 56 ++++++++++++++++++++++++++ 6 files changed, 141 insertions(+), 37 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/pr51513-1.c create mode 100644 gcc/testsuite/gcc.target/mips/pr51513-2.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 09435d0..2d5110c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-14 Maciej W. Rozycki + + * config/mips/mips.md (MIPS16_T_REGNUM): Remove constant. + (casesi): Emit bounds checking as RTL. + (casesi_internal_mips16_): Remove bounds checking. + 2017-06-14 Max Filippov * config/xtensa/xtensa.c (xtensa_option_override): Append diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 28e0a44..971af6f 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -162,7 +162,6 @@ [(TLS_GET_TP_REGNUM 3) (GET_FCSR_REGNUM 2) (SET_FCSR_REGNUM 4) - (MIPS16_T_REGNUM 24) (PIC_FUNCTION_ADDR_REGNUM 25) (RETURN_ADDR_REGNUM 31) (CPRESTORE_SLOT_REGNUM 76) @@ -6389,68 +6388,57 @@ if (!arith_operand (operands[0], SImode)) operands[0] = force_reg (SImode, operands[0]); - operands[2] = GEN_INT (INTVAL (operands[2]) + 1); - + emit_cmp_and_jump_insns (operands[0], operands[2], GTU, + NULL_RTX, SImode, 1, operands[4]); emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16, - (operands[0], operands[2], - operands[3], operands[4]))); - + (operands[0], operands[3]))); DONE; }) (define_insn "casesi_internal_mips16_" [(set (pc) - (if_then_else - (ltu (match_operand:SI 0 "register_operand" "d") - (match_operand:SI 1 "arith_operand" "dI")) - (unspec:P - [(match_dup 0) - (label_ref (match_operand 2 "" ""))] - UNSPEC_CASESI_DISPATCH) - (label_ref (match_operand 3 "" "")))) - (clobber (match_scratch:P 4 "=d")) - (clobber (match_scratch:P 5 "=d")) - (clobber (reg:SI MIPS16_T_REGNUM))] + (unspec:P [(match_operand:SI 0 "register_operand" "d") + (label_ref (match_operand 1 "" ""))] + UNSPEC_CASESI_DISPATCH)) + (clobber (match_scratch:P 2 "=d")) + (clobber (match_scratch:P 3 "=d"))] "TARGET_MIPS16_SHORT_JUMP_TABLES" { - rtx diff_vec = PATTERN (NEXT_INSN (as_a (operands[2]))); + rtx diff_vec = PATTERN (NEXT_INSN (as_a (operands[1]))); gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); - - output_asm_insn ("sltu\t%0, %1", operands); - output_asm_insn ("bteqz\t%3", operands); - + switch (GET_MODE (diff_vec)) { case HImode: - output_asm_insn ("sll\t%5, %0, 1", operands); - output_asm_insn ("la\t%4, %2", operands); - output_asm_insn ("addu\t%5, %4, %5", operands); - output_asm_insn ("lh\t%5, 0(%5)", operands); + output_asm_insn ("sll\t%3,%0,1", operands); + output_asm_insn ("la\t%2,%1", operands); + output_asm_insn ("addu\t%3,%2,%3", operands); + output_asm_insn ("lh\t%3,0(%3)", operands); break; case SImode: - output_asm_insn ("sll\t%5, %0, 2", operands); - output_asm_insn ("la\t%4, %2", operands); - output_asm_insn ("addu\t%5, %4, %5", operands); - output_asm_insn ("lw\t%5, 0(%5)", operands); + output_asm_insn ("sll\t%3,%0,2", operands); + output_asm_insn ("la\t%2,%1", operands); + output_asm_insn ("addu\t%3,%2,%3", operands); + output_asm_insn ("lw\t%3,0(%3)", operands); break; default: gcc_unreachable (); } - output_asm_insn ("addu\t%4, %4, %5", operands); + output_asm_insn ("addu\t%2,%2,%3", operands); if (GENERATE_MIPS16E) - return "jrc\t%4"; + return "jrc\t%2"; else - return "jr\t%4"; + return "jr\t%2"; } [(set (attr "insn_count") (if_then_else (match_test "GENERATE_MIPS16E") - (const_string "10") - (const_string "11")))]) + (const_string "6") + (const_string "7")))]) ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well. ;; While it is possible to either pull it off the stack (in the diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a0c522e..dc82af0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-06-14 Maciej W. Rozycki + + * gcc.target/mips/data-sym-jump.c: Adjust for whitespace changes. + * gcc.target/mips/pr51513-1.c: New test. + * gcc.target/mips/pr51513-2.c: New test. + 2017-06-14 Richard Biener PR tree-optimization/81083 diff --git a/gcc/testsuite/gcc.target/mips/data-sym-jump.c b/gcc/testsuite/gcc.target/mips/data-sym-jump.c index c3ba294..ae48c0b 100644 --- a/gcc/testsuite/gcc.target/mips/data-sym-jump.c +++ b/gcc/testsuite/gcc.target/mips/data-sym-jump.c @@ -25,7 +25,7 @@ frob (int i) /* Expect assembly like: - la $2, $L4 + la $2,$L4 # Anything goes here. .type __jump_frob_4, @object # Symbol # must match label. __jump_frob_4: # The symbol must match. @@ -47,4 +47,4 @@ __jend_frob_4: # The symbol must match. that is `__jump_*'/`__jend_*' symbols inserted around a jump table. */ -/* { dg-final { scan-assembler "\tla\t\\\$\[0-9\]+, (.L(\[0-9\]+))\n.*\t\\.type\t(__jump_frob_\\2), @object\n\\3:\n\\1:\n(?:\t\\.(?:half|word)\t.L\[0-9\]+-\\1\n)\{11\}\t\\.type\t(__jend_frob_\\2), @function\n\\4:\n\t\\.insn\n" } } */ +/* { dg-final { scan-assembler "\tla\t\\\$\[0-9\]+,(.L(\[0-9\]+))\n.*\t\\.type\t(__jump_frob_\\2), @object\n\\3:\n\\1:\n(?:\t\\.(?:half|word)\t.L\[0-9\]+-\\1\n)\{11\}\t\\.type\t(__jend_frob_\\2), @function\n\\4:\n\t\\.insn\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/pr51513-1.c b/gcc/testsuite/gcc.target/mips/pr51513-1.c new file mode 100644 index 0000000..b5e0d69 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr51513-1.c @@ -0,0 +1,48 @@ +/* { dg-do compile } */ +/* { dg-options "-mips16 -mcode-readable=yes" } */ + +/* PR tree-optimization/51513 verification variant for MIPS16, #1. */ + +int __attribute__ ((weak)) +frob (int i) +{ + switch (i) + { + case -5: + return -2; + case -3: + return -1; + case 0: + return 0; + case 3: + return 1; + case 5: + break; + default: + __builtin_unreachable (); + } + return i; +} + +/* Without the fix for PR tree-optimization/51513 truncated code + would be emitted for `frob', like: + + .text + .align 2 + .weak frob + .set mips16 + .set nomicromips + .ent frob + .type frob, @function +frob: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + addiu $2,$4,5 + .end frob + .size frob, .-frob + + meaning `frob' will have no chance to return, let alone produce + the result expected. */ + +/* { dg-final { scan-assembler "\tjrc?\t\\\$31\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/pr51513-2.c b/gcc/testsuite/gcc.target/mips/pr51513-2.c new file mode 100644 index 0000000..b921904 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr51513-2.c @@ -0,0 +1,56 @@ +/* { dg-do run } */ +/* { dg-options "-mips16 -mcode-readable=yes" } */ + +/* PR tree-optimization/51513 verification variant for MIPS16, #2. */ + +int __attribute__ ((weak)) +frob (int i) +{ + switch (i) + { + case -5: + return -2; + case -3: + return -1; + case 0: + return 0; + case 3: + return 1; + case 5: + break; + default: + __builtin_unreachable (); + } + return i; +} + +int +main (void) +{ + return !(frob (-5) == -2 + & frob (-3) == -1 + & frob (0) == 0 + & frob (3) == 1 + & frob (5) == 5); +} + +/* Without the fix for PR tree-optimization/51513 truncated code + would be emitted for `frob', like: + + .text + .align 2 + .weak frob + .set mips16 + .set nomicromips + .ent frob + .type frob, @function +frob: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + addiu $2,$4,5 + .end frob + .size frob, .-frob + + meaning `frob' will have no chance to return, let alone produce + the result expected. */ -- cgit v1.1 From b901cf9dd9d20c6e0fe0b2eb32063a9b4930d1f6 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 14 Jun 2017 23:42:53 +0000 Subject: compiler: avoid crash on erroneous type If there is an error constructing the backend type, the GCC backend will report that the size is 1. That will then cause construction of the ptrmask to crash. Avoid that case by just generating an empty ptrmask. Noticed while compiling a broken package. The policy I've been following is to not commit a test case for a compiler crash on invalid code, so no test case. Reviewed-on: https://go-review.googlesource.com/45775 From-SVN: r249208 --- gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/types.cc | 16 +++++++++++----- 2 files changed, 12 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 1f600d3..0eeac9b 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -372e75503c1dc9a38d9978aa6b67631283d5d6dd +6449e2832eef94eacf89c88fa16bede637f729ba The first line of this file holds the git revision number of the last merge done from the gofrontend repository. diff --git a/gcc/go/gofrontend/types.cc b/gcc/go/gofrontend/types.cc index 61a3363..912a23e 100644 --- a/gcc/go/gofrontend/types.cc +++ b/gcc/go/gofrontend/types.cc @@ -2570,16 +2570,16 @@ Type::make_gc_symbol_var(Gogo* gogo) bool Type::needs_gcprog(Gogo* gogo, int64_t* ptrsize, int64_t* ptrdata) { + Type* voidptr = Type::make_pointer_type(Type::make_void_type()); + if (!voidptr->backend_type_size(gogo, ptrsize)) + go_unreachable(); + if (!this->backend_type_ptrdata(gogo, ptrdata)) { go_assert(saw_errors()); return false; } - Type* voidptr = Type::make_pointer_type(Type::make_void_type()); - if (!voidptr->backend_type_size(gogo, ptrsize)) - go_unreachable(); - return *ptrdata / *ptrsize > max_ptrmask_bytes; } @@ -2795,7 +2795,13 @@ Bvariable* Type::gc_ptrmask_var(Gogo* gogo, int64_t ptrsize, int64_t ptrdata) { Ptrmask ptrmask(ptrdata / ptrsize); - ptrmask.set_from(gogo, this, ptrsize, 0); + if (ptrdata >= ptrsize) + ptrmask.set_from(gogo, this, ptrsize, 0); + else + { + // This can happen in error cases. Just build an empty gcbits. + go_assert(saw_errors()); + } std::string sym_name = "runtime.gcbits." + ptrmask.symname(); Bvariable* bvnull = NULL; std::pair ins = -- cgit v1.1 From 0f25124435030c3e788ce4425d799648ff906743 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Thu, 15 Jun 2017 00:16:20 +0000 Subject: Daily bump. From-SVN: r249212 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 8df707d..34e59ee 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170614 +20170615 -- cgit v1.1 From dfc107627c31c493e4ed089aea79bc398738a27b Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Thu, 15 Jun 2017 08:49:17 +0200 Subject: rs6000: Don't use REGNO in the add3 expander The argument could be a subreg of reg instead, which means we have to use reg_or_subregno instead of REGNO. * config/rs6000/rs6000.md (add3): Use reg_or_subregno instead of REGNO. From-SVN: r249213 --- gcc/ChangeLog | 5 +++++ gcc/config/rs6000/rs6000.md | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2d5110c..f460df6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-15 Segher Boessenkool + + * config/rs6000/rs6000.md (add3): Use reg_or_subregno instead + of REGNO. + 2017-06-14 Maciej W. Rozycki * config/mips/mips.md (MIPS16_T_REGNUM): Remove constant. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index dedb2e3..8e1b460 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1631,7 +1631,7 @@ /* Adding a constant to r0 is not a valid insn, so use a different strategy in that case. */ - if (REGNO (operands[1]) == 0 || REGNO (tmp) == 0) + if (reg_or_subregno (operands[1]) == 0 || reg_or_subregno (tmp) == 0) { if (operands[0] == operands[1]) FAIL; -- cgit v1.1 From 41c540fc0f9673fbd37cc6e8fd4e1db1da4ef3c5 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Thu, 15 Jun 2017 09:23:28 +0000 Subject: sdiv_costs_1.c: Use dg-add-options. 2017-06-15 Tamar Christina * gcc.target/arm/sdiv_costs_1.c: Use dg-add-options. From-SVN: r249214 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/arm/sdiv_costs_1.c | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dc82af0..5e05a35 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-15 Tamar Christina + + * gcc.target/arm/sdiv_costs_1.c: + Use dg-add-options. + 2017-06-14 Maciej W. Rozycki * gcc.target/mips/data-sym-jump.c: Adjust for whitespace changes. diff --git a/gcc/testsuite/gcc.target/arm/sdiv_costs_1.c b/gcc/testsuite/gcc.target/arm/sdiv_costs_1.c index 9d094ac..64b7e24 100644 --- a/gcc/testsuite/gcc.target/arm/sdiv_costs_1.c +++ b/gcc/testsuite/gcc.target/arm/sdiv_costs_1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=armv8-a" } */ +/* { dg-options "-O3" } */ /* { dg-require-effective-target arm_arch_v8a_ok } */ +/* { dg-add-options arm_arch_v8a } */ /* Both sdiv and udiv can be used here, so prefer udiv. */ int f1 (unsigned char *p) -- cgit v1.1 From 6820664ac6c49245baec9e9a76945cf6991c13e2 Mon Sep 17 00:00:00 2001 From: Thomas Preud'homme Date: Thu, 15 Jun 2017 09:31:04 +0000 Subject: [ARM] Make gcc.target/arm/its.c more robust 2017-06-15 Thomas Preud'homme gcc/testsuite/ * gcc.target/arm/its.c: Check that no IT blocks has more than 2 instructions in it rather than the number of IT blocks being 2. Transfer scan directive arm_thumb2 restriction to the whole testcase and restrict further to Thumb-only targets. From-SVN: r249215 --- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/arm/its.c | 6 +++++- 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5e05a35..4b7433e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2017-06-15 Thomas Preud'homme + + * gcc.target/arm/its.c: Check that no IT blocks has more than 2 + instructions in it rather than the number of IT blocks being 2. + Transfer scan directive arm_thumb2 restriction to the whole + testcase and restrict further to Thumb-only targets. + 2017-06-15 Tamar Christina * gcc.target/arm/sdiv_costs_1.c: diff --git a/gcc/testsuite/gcc.target/arm/its.c b/gcc/testsuite/gcc.target/arm/its.c index 5425f1e..f81a0df 100644 --- a/gcc/testsuite/gcc.target/arm/its.c +++ b/gcc/testsuite/gcc.target/arm/its.c @@ -1,4 +1,6 @@ /* { dg-do compile } */ +/* { dg-require-effective-target arm_cortex_m } */ +/* { dg-require-effective-target arm_thumb2 } */ /* { dg-options "-O2" } */ int test (int a, int b) { @@ -17,4 +19,6 @@ int test (int a, int b) r -= 3; return r; } -/* { dg-final { scan-assembler-times "\tit" 2 { target arm_thumb2 } } } */ +/* Ensure there is no IT block with more than 2 instructions, ie. we only allow + IT, ITT and ITE. */ +/* { dg-final { scan-assembler-not "\\sit\[te\]{2}" } } */ -- cgit v1.1 From 0948d23fffba754853cc93984e106d2aaf9a3897 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Thu, 15 Jun 2017 13:24:53 +0000 Subject: re PR rtl-optimization/80474 (ipa-cp wrongly adding LO(symbol) twice) PR rtl-optimization/80474 * reorg.c (update_block): Do not ignore instructions in a delay slot. From-SVN: r249219 --- gcc/ChangeLog | 5 +++++ gcc/reorg.c | 11 ++--------- 2 files changed, 7 insertions(+), 9 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f460df6..fc9554f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-15 Eric Botcazou + + PR rtl-optimization/80474 + * reorg.c (update_block): Do not ignore instructions in a delay slot. + 2017-06-15 Segher Boessenkool * config/rs6000/rs6000.md (add3): Use reg_or_subregno instead diff --git a/gcc/reorg.c b/gcc/reorg.c index 1a6fd86..dbd74ab 100644 --- a/gcc/reorg.c +++ b/gcc/reorg.c @@ -1694,9 +1694,8 @@ own_thread_p (rtx thread, rtx label, int allow_fallthrough) } /* Called when INSN is being moved from a location near the target of a jump. - We leave a marker of the form (use (INSN)) immediately in front - of WHERE for mark_target_live_regs. These markers will be deleted when - reorg finishes. + We leave a marker of the form (use (INSN)) immediately in front of WHERE + for mark_target_live_regs. These markers will be deleted at the end. We used to try to update the live status of registers if WHERE is at the start of a basic block, but that can't work since we may remove a @@ -1705,16 +1704,10 @@ own_thread_p (rtx thread, rtx label, int allow_fallthrough) static void update_block (rtx_insn *insn, rtx_insn *where) { - /* Ignore if this was in a delay slot and it came from the target of - a branch. */ - if (INSN_FROM_TARGET_P (insn)) - return; - emit_insn_before (gen_rtx_USE (VOIDmode, insn), where); /* INSN might be making a value live in a block where it didn't use to be. So recompute liveness information for this block. */ - incr_ticks_for_insn (insn); } -- cgit v1.1 From 61f5d85294a6a2757a1ab870c6f335e092c0c83a Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Thu, 15 Jun 2017 13:38:52 +0000 Subject: Fix problems with the MSP430 port's handling of persistent data. PR target/78818 gcc * config/msp430/msp430.c (msp430_data_attr): Check that it's possible for a variable to have a section before checking if the section has a name. Set section to.persistent if persistent attribute is set. Warn if .persistent attribute is used on an automatic variable. tests * gcc.target/msp430/pr78818-real.c: New template for tests. * gcc.target/msp430/pr78818-auto.c: New test. * gcc.target/msp430/pr78818-data-region.c: New test. * gcc.target/msp430/pr78818-data-sec.c: New test. * gcc.target/msp430/pr78818-auto-warn.c: New test. From-SVN: r249222 --- gcc/ChangeLog | 9 +++++++++ gcc/config/msp430/msp430.c | 23 ++++++++++++++++++---- gcc/testsuite/ChangeLog | 9 +++++++++ .../gcc.target/msp430/pr78818-auto-warn.c | 16 +++++++++++++++ gcc/testsuite/gcc.target/msp430/pr78818-auto.c | 5 +++++ .../gcc.target/msp430/pr78818-data-region.c | 6 ++++++ gcc/testsuite/gcc.target/msp430/pr78818-data-sec.c | 7 +++++++ gcc/testsuite/gcc.target/msp430/pr78818-real.c | 9 +++++++++ 8 files changed, 80 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/msp430/pr78818-auto-warn.c create mode 100644 gcc/testsuite/gcc.target/msp430/pr78818-auto.c create mode 100644 gcc/testsuite/gcc.target/msp430/pr78818-data-region.c create mode 100644 gcc/testsuite/gcc.target/msp430/pr78818-data-sec.c create mode 100644 gcc/testsuite/gcc.target/msp430/pr78818-real.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fc9554f..3f2f344 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2017-06-15 Jozef Lawrynowicz + + PR target/78818 + * config/msp430/msp430.c (msp430_data_attr): Check that it's possible + for a variable to have a section before checking if the section has a + name. + Set section to.persistent if persistent attribute is set. + Warn if .persistent attribute is used on an automatic variable. + 2017-06-15 Eric Botcazou PR rtl-optimization/80474 diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c index dd53dea..6acab1e 100644 --- a/gcc/config/msp430/msp430.c +++ b/gcc/config/msp430/msp430.c @@ -40,6 +40,7 @@ #include "expr.h" #include "langhooks.h" #include "builtins.h" +#include "intl.h" /* This file should be included last. */ #include "target-def.h" @@ -1993,10 +1994,24 @@ msp430_data_attr (tree * node, gcc_assert (args == NULL); if (TREE_CODE (* node) != VAR_DECL) - message = "%qE attribute only applies to variables"; - - if (DECL_SECTION_NAME (* node)) - message = "%qE attribute cannot be applied to variables with specific sections"; + message = G_("%qE attribute only applies to variables"); + + /* Check that it's possible for the variable to have a section. */ + if ((TREE_STATIC (* node) || DECL_EXTERNAL (* node) || in_lto_p) + && DECL_SECTION_NAME (* node)) + message = G_("%qE attribute cannot be applied to variables with specific sections"); + + if (!message && TREE_NAME_EQ (name, ATTR_PERSIST) && !TREE_STATIC (* node) + && !TREE_PUBLIC (* node) && !DECL_EXTERNAL (* node)) + message = G_("%qE attribute has no effect on automatic variables"); + + /* It's not clear if there is anything that can be set here to prevent the + front end placing the variable before the back end can handle it, in a + similar way to how DECL_COMMON is used below. + So just place the variable in the .persistent section now. */ + if ((TREE_STATIC (* node) || DECL_EXTERNAL (* node) || in_lto_p) + && TREE_NAME_EQ (name, ATTR_PERSIST)) + set_decl_section_name (* node, ".persistent"); /* If this var is thought to be common, then change this. Common variables are assigned to sections before the backend has a chance to process them. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4b7433e..3677d15 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2017-06-15 Jozef Lawrynowicz + + PR target/78818 + * gcc.target/msp430/pr78818-real.c: New template for tests. + * gcc.target/msp430/pr78818-auto.c: New test. + * gcc.target/msp430/pr78818-data-region.c: New test. + * gcc.target/msp430/pr78818-data-sec.c: New test. + * gcc.target/msp430/pr78818-auto-warn.c: New test. + 2017-06-15 Thomas Preud'homme * gcc.target/arm/its.c: Check that no IT blocks has more than 2 diff --git a/gcc/testsuite/gcc.target/msp430/pr78818-auto-warn.c b/gcc/testsuite/gcc.target/msp430/pr78818-auto-warn.c new file mode 100644 index 0000000..3dba361 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/pr78818-auto-warn.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ + +__attribute__((persistent)) int persistent_1_g = 1; +__attribute__((persistent)) int persistent_2_g = 0; +static __attribute__((persistent)) int persistent_3_g = 1; +static __attribute__((persistent)) int persistent_4_g = 0; + +int +main (void) +{ + __attribute__((persistent)) int persistent_1 = 1; /* { dg-warning "attribute has no effect on automatic" } */ + __attribute__((persistent)) int persistent_2 = 0; /* { dg-warning "attribute has no effect on automatic" } */ + static __attribute__((persistent)) int persistent_3 = 1; + static __attribute__((persistent)) int persistent_4 = 0; + return 0; +} diff --git a/gcc/testsuite/gcc.target/msp430/pr78818-auto.c b/gcc/testsuite/gcc.target/msp430/pr78818-auto.c new file mode 100644 index 0000000..1fb0b28 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/pr78818-auto.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ + +/* { dg-final { scan-assembler-not "\\.comm" } } */ + +#include "pr78818-real.c" diff --git a/gcc/testsuite/gcc.target/msp430/pr78818-data-region.c b/gcc/testsuite/gcc.target/msp430/pr78818-data-region.c new file mode 100644 index 0000000..22b1fa2 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/pr78818-data-region.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mdata-region=either" } */ + +/* { dg-final { scan-assembler-not "\\.either" } } */ + +#include "pr78818-real.c" diff --git a/gcc/testsuite/gcc.target/msp430/pr78818-data-sec.c b/gcc/testsuite/gcc.target/msp430/pr78818-data-sec.c new file mode 100644 index 0000000..6367e01 --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/pr78818-data-sec.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-fdata-sections" } */ + +/* { dg-final { scan-assembler-not "\\.data" } } */ +/* { dg-final { scan-assembler-not "\\.bss" } } */ + +#include "pr78818-real.c" diff --git a/gcc/testsuite/gcc.target/msp430/pr78818-real.c b/gcc/testsuite/gcc.target/msp430/pr78818-real.c new file mode 100644 index 0000000..504ed4a --- /dev/null +++ b/gcc/testsuite/gcc.target/msp430/pr78818-real.c @@ -0,0 +1,9 @@ +__attribute__((persistent)) int persistent_1 = 1; +__attribute__((persistent)) int persistent_2 = 0; +static __attribute__((persistent)) int persistent_3 = 1; +static __attribute__((persistent)) int persistent_4 = 0; + +int main (void) +{ + return 0; +} -- cgit v1.1 From 55dabf65f039c3a5635f01dccb9e4de767f89323 Mon Sep 17 00:00:00 2001 From: Ramana Radhakrishnan Date: Thu, 15 Jun 2017 14:17:04 +0000 Subject: Update comment about is_leaf crtl->is_leaf has a comment above it referring to "Local Register Allocation". However this is set by IRA and not LRA since the meaning of Local Register Allocator in GCC has changed quite drastically since 1999 when this comment was introduced above the variable current_function_is_leaf. From memory gcc in those days had "local" and "global" register allocation - however all of this has changed quite a bit drastically since. This patch merely updates the comment as I did some head scratching this morning about how this could be set before Local Register Allocator especially given the comment in ira.c as below. /* Determine if the current function is a leaf before running IRA since this can impact optimizations done by the prologue and epilogue thus changing register elimination offsets. */ crtl->is_leaf = leaf_function_p (); From-SVN: r249223 --- gcc/ChangeLog | 5 +++++ gcc/emit-rtl.h | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3f2f344..b8c2f05 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-15 Ramana Radhakrishnan + + * emit-rtl.h (is_leaf): Update comment about local + register allocator. + 2017-06-15 Jozef Lawrynowicz PR target/78818 diff --git a/gcc/emit-rtl.h b/gcc/emit-rtl.h index da60a2d..b455b4c 100644 --- a/gcc/emit-rtl.h +++ b/gcc/emit-rtl.h @@ -267,7 +267,7 @@ struct GTY(()) rtl_data { /* Nonzero if function being compiled doesn't contain any calls (ignoring the prologue and epilogue). This is set prior to - local register allocation and is valid for the remaining + register allocation in IRA and is valid for the remaining compiler passes. */ bool is_leaf; -- cgit v1.1 From d1eed638ed170a22a3feb9515b82b125fd203727 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Thu, 15 Jun 2017 18:42:10 +0000 Subject: re PR lto/69866 (lto1: internal compiler error: in add_symbol_to_partition_1, at lto/lto-partition.c:158) PR lto/69866 * lto-symtab.c (lto_symtab_merge_symbols): Drop useless definitions that resolved externally. * gcc.dg/lto/pr69866_0.c: New test. * gcc.dg/lto/pr69866_1.c: Likewise. From-SVN: r249224 --- gcc/lto/ChangeLog | 7 +++++++ gcc/lto/lto-partition.c | 2 +- gcc/lto/lto-symtab.c | 36 ++++++++++++++++++++++++++++++++++++ gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.dg/lto/pr69866_0.c | 13 +++++++++++++ gcc/testsuite/gcc.dg/lto/pr69866_1.c | 6 ++++++ 6 files changed, 69 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/lto/pr69866_0.c create mode 100644 gcc/testsuite/gcc.dg/lto/pr69866_1.c (limited to 'gcc') diff --git a/gcc/lto/ChangeLog b/gcc/lto/ChangeLog index e63f203..58601c5 100644 --- a/gcc/lto/ChangeLog +++ b/gcc/lto/ChangeLog @@ -1,3 +1,10 @@ +2017-06-15 Jan Hubicka + Thomas Preud'homme + + PR lto/69866 + * lto-symtab.c (lto_symtab_merge_symbols): Drop useless definitions + that resolved externally. + 2017-05-23 Jan Hubicka * lto.c (do_whole_program_analysis): Replace inline_free_summary diff --git a/gcc/lto/lto-partition.c b/gcc/lto/lto-partition.c index 3600ab2..620deac 100644 --- a/gcc/lto/lto-partition.c +++ b/gcc/lto/lto-partition.c @@ -132,7 +132,7 @@ add_symbol_to_partition_1 (ltrans_partition part, symtab_node *node) /* Be sure that we never try to duplicate partitioned symbol or add external symbol. */ - gcc_assert (c != SYMBOL_EXTERNAL + gcc_assert ((c != SYMBOL_EXTERNAL || node->alias) && (c == SYMBOL_DUPLICATE || !symbol_partitioned_p (node))); part->symbols++; diff --git a/gcc/lto/lto-symtab.c b/gcc/lto/lto-symtab.c index 9fd9486..019677e 100644 --- a/gcc/lto/lto-symtab.c +++ b/gcc/lto/lto-symtab.c @@ -952,6 +952,42 @@ lto_symtab_merge_symbols (void) if (tgt) node->resolve_alias (tgt, true); } + /* If the symbol was preempted outside IR, see if we want to get rid + of the definition. */ + if (node->analyzed + && !DECL_EXTERNAL (node->decl) + && (node->resolution == LDPR_PREEMPTED_REG + || node->resolution == LDPR_RESOLVED_IR + || node->resolution == LDPR_RESOLVED_EXEC + || node->resolution == LDPR_RESOLVED_DYN)) + { + DECL_EXTERNAL (node->decl) = 1; + /* If alias to local symbol was preempted by external definition, + we know it is not pointing to the local symbol. Remove it. */ + if (node->alias + && !node->weakref + && !node->transparent_alias + && node->get_alias_target ()->binds_to_current_def_p ()) + { + node->alias = false; + node->remove_all_references (); + node->definition = false; + node->analyzed = false; + node->cpp_implicit_alias = false; + } + else if (!node->alias + && node->definition + && node->get_availability () <= AVAIL_INTERPOSABLE) + { + if ((cnode = dyn_cast (node)) != NULL) + cnode->reset (); + else + { + node->analyzed = node->definition = false; + node->remove_all_references (); + } + } + } if (!(cnode = dyn_cast (node)) || !cnode->clone_of diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3677d15..a79f533 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-06-15 Thomas Preud'homme + + PR lto/69866 + * gcc.dg/lto/pr69866_0.c: New test. + * gcc.dg/lto/pr69866_1.c: Likewise. + 2017-06-15 Jozef Lawrynowicz PR target/78818 diff --git a/gcc/testsuite/gcc.dg/lto/pr69866_0.c b/gcc/testsuite/gcc.dg/lto/pr69866_0.c new file mode 100644 index 0000000..f49ef8d --- /dev/null +++ b/gcc/testsuite/gcc.dg/lto/pr69866_0.c @@ -0,0 +1,13 @@ +/* { dg-lto-do link } */ + +int _umh(int i) +{ + return i+1; +} + +int weaks(int i) __attribute__((weak, alias("_umh"))); + +int main() +{ + return weaks(10); +} diff --git a/gcc/testsuite/gcc.dg/lto/pr69866_1.c b/gcc/testsuite/gcc.dg/lto/pr69866_1.c new file mode 100644 index 0000000..3a14f85 --- /dev/null +++ b/gcc/testsuite/gcc.dg/lto/pr69866_1.c @@ -0,0 +1,6 @@ +/* { dg-options { -fno-lto } } */ + +int weaks(int i) +{ + return i+1; +} -- cgit v1.1 From 3a849280c70fb896a35dd006ffe1a37171eed81e Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Thu, 15 Jun 2017 18:45:47 +0000 Subject: Revert accidental checkin. From-SVN: r249225 --- gcc/lto/lto-partition.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/lto/lto-partition.c b/gcc/lto/lto-partition.c index 620deac..3600ab2 100644 --- a/gcc/lto/lto-partition.c +++ b/gcc/lto/lto-partition.c @@ -132,7 +132,7 @@ add_symbol_to_partition_1 (ltrans_partition part, symtab_node *node) /* Be sure that we never try to duplicate partitioned symbol or add external symbol. */ - gcc_assert ((c != SYMBOL_EXTERNAL || node->alias) + gcc_assert (c != SYMBOL_EXTERNAL && (c == SYMBOL_DUPLICATE || !symbol_partitioned_p (node))); part->symbols++; -- cgit v1.1 From d0e7a9fdfc21c858d4131052cf38dea4fa8f44b2 Mon Sep 17 00:00:00 2001 From: Janus Weil Date: Thu, 15 Jun 2017 23:17:48 +0200 Subject: re PR fortran/80983 ([F03] memory leak when calling procedure-pointer component with allocatable result) 2017-06-15 Janus Weil PR fortran/80983 * trans-expr.c (gfc_conv_procedure_call): Deallocate the result of scalar allocatable procedure-pointer components. 2017-06-15 Janus Weil PR fortran/80983 * gfortran.dg/proc_ptr_comp_51.f90: New test. From-SVN: r249227 --- gcc/fortran/ChangeLog | 6 +++++ gcc/fortran/trans-expr.c | 3 ++- gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/gfortran.dg/proc_ptr_comp_51.f90 | 35 ++++++++++++++++++++++++++ 4 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gfortran.dg/proc_ptr_comp_51.f90 (limited to 'gcc') diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index ec28113..8e9e9a6 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,9 @@ +2017-06-15 Janus Weil + + PR fortran/80983 + * trans-expr.c (gfc_conv_procedure_call): Deallocate the result of + scalar allocatable procedure-pointer components. + 2017-06-10 Thomas Koenig PR fortran/80988 diff --git a/gcc/fortran/trans-expr.c b/gcc/fortran/trans-expr.c index 6af287e..acd0428 100644 --- a/gcc/fortran/trans-expr.c +++ b/gcc/fortran/trans-expr.c @@ -6132,7 +6132,8 @@ gfc_conv_procedure_call (gfc_se * se, gfc_symbol * sym, after use. This necessitates the creation of a temporary to hold the result to prevent duplicate calls. */ if (!byref && sym->ts.type != BT_CHARACTER - && sym->attr.allocatable && !sym->attr.dimension && !comp) + && ((sym->attr.allocatable && !sym->attr.dimension && !comp) + || (comp && comp->attr.allocatable && !comp->attr.dimension))) { tmp = gfc_create_var (TREE_TYPE (se->expr), NULL); gfc_add_modify (&se->pre, tmp, se->expr); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a79f533..34b6a9d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-15 Janus Weil + + PR fortran/80983 + * gfortran.dg/proc_ptr_comp_51.f90: New test. + 2017-06-15 Thomas Preud'homme PR lto/69866 diff --git a/gcc/testsuite/gfortran.dg/proc_ptr_comp_51.f90 b/gcc/testsuite/gfortran.dg/proc_ptr_comp_51.f90 new file mode 100644 index 0000000..530872b --- /dev/null +++ b/gcc/testsuite/gfortran.dg/proc_ptr_comp_51.f90 @@ -0,0 +1,35 @@ +! { dg-do compile } +! +! PR 80983: [F03] memory leak when calling procedure-pointer component with allocatable result +! +! Contributed by Janus Weil + +program test + implicit none + + type :: concrete_type + procedure (alloc_integer), pointer, nopass :: alloc + end type + + procedure (alloc_integer), pointer :: pp + + type(concrete_type) :: concrete + + print *, alloc_integer() ! case #1: plain function + + pp => alloc_integer + print *, pp() ! case #2: procedure pointer + + concrete % alloc => alloc_integer + print *, concrete % alloc() ! case #3: procedure-pointer component + +contains + + function alloc_integer() result(res) + integer, allocatable :: res + allocate(res, source=13) + end function + +end + +! { dg-final { scan-tree-dump-times "__builtin_free" 3 "original" } } -- cgit v1.1 From cb55f77df1442a9f2b364b85f0d859383736fb07 Mon Sep 17 00:00:00 2001 From: Nicolas Boulenguez Date: Fri, 16 Jun 2017 00:21:56 +0200 Subject: re PR ada/81105 (system-freebsd-x86.ads renamed but referenced by gcc/ada/gcc-interface/Makefile.in) PR ada/81105 * gcc-interface/Makefile.in (x86 kfreebsd): Adjust system.ads setting. (i[3456]86-pc-gnu): Likewise. (x86_64 kfreebsd): Likewise. From-SVN: r249228 --- gcc/ada/ChangeLog | 7 +++++++ gcc/ada/gcc-interface/Makefile.in | 6 +++--- 2 files changed, 10 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 30290fa..5fb0cdf 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,10 @@ +2017-06-15 Nicolas Boulenguez + + PR ada/81105 + * gcc-interface/Makefile.in (x86 kfreebsd): Adjust system.ads setting. + (i[3456]86-pc-gnu): Likewise. + (x86_64 kfreebsd): Likewise. + 2017-06-12 Eric Botcazou PR bootstrap/80897 diff --git a/gcc/ada/gcc-interface/Makefile.in b/gcc/ada/gcc-interface/Makefile.in index 1030a67..1c17203 100644 --- a/gcc/ada/gcc-interface/Makefile.in +++ b/gcc/ada/gcc-interface/Makefile.in @@ -1435,7 +1435,7 @@ ifeq ($(strip $(filter-out %86 kfreebsd%,$(target_cpu) $(target_os))),) s-tpopsp.adb Date: Fri, 16 Jun 2017 00:16:24 +0000 Subject: Daily bump. From-SVN: r249233 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 34e59ee..a36783b 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170615 +20170616 -- cgit v1.1 From c3684b7b86da9b6b01f6fb274227fc6401df053e Mon Sep 17 00:00:00 2001 From: Martin Sebor Date: Fri, 16 Jun 2017 03:48:59 +0000 Subject: PR c++/80560 - warn on undefined memory operations involving non-trivial types gcc/c-family/ChangeLog: PR c++/80560 * c.opt (-Wclass-memaccess): New option. gcc/cp/ChangeLog: PR c++/80560 * call.c (first_non_public_field, maybe_warn_class_memaccess): New functions. (has_trivial_copy_assign_p, has_trivial_copy_p): Ditto. (build_cxx_call): Call maybe_warn_class_memaccess. gcc/ChangeLog: PR c++/80560 * dumpfile.c (dump_register): Avoid calling memset to initialize a class with a default ctor. * gcc.c (struct compiler): Remove const qualification. * genattrtab.c (gen_insn_reserv): Replace memset with initialization. * hash-table.h: Ditto. * ipa-cp.c (allocate_and_init_ipcp_value): Replace memset with assignment. * ipa-prop.c (ipa_free_edge_args_substructures): Ditto. * omp-low.c (lower_omp_ordered_clauses): Replace memset with default ctor. * params.h (struct param_info): Make struct members non-const. * tree-switch-conversion.c (emit_case_bit_tests): Replace memset with default initialization. * vec.h (vec_copy_construct, vec_default_construct): New helper functions. (vec::copy, vec::splice, vec::reserve): Replace memcpy with vec_copy_construct. (vect::quick_grow_cleared): Replace memset with default ctor. (vect::vec_safe_grow_cleared, vec_safe_grow_cleared): Same. * doc/invoke.texi (-Wclass-memaccess): Document. libcpp/ChangeLog: PR c++/80560 * line-map.c (line_maps::~line_maps): Avoid calling htab_delete with a null pointer. (linemap_init): Avoid calling memset on an object of a non-trivial type. libitm/ChangeLog: PR c++/80560 * beginend.cc (GTM::gtm_thread::rollback): Avoid calling memset on an object of a non-trivial type. (GTM::gtm_transaction_cp::commit): Use assignment instead of memcpy to copy an object. * method-ml.cc (orec_iterator::reinit): Avoid -Wclass-memaccess. gcc/testsuite/ChangeLog: PR c++/80560 * g++.dg/Wclass-memaccess.C: New test. From-SVN: r249234 --- gcc/ChangeLog | 24 + gcc/c-family/ChangeLog | 5 + gcc/c-family/c.opt | 4 + gcc/cp/ChangeLog | 8 + gcc/cp/call.c | 391 ++++++++ gcc/doc/invoke.texi | 20 +- gcc/dumpfile.c | 9 +- gcc/gcc.c | 4 +- gcc/genattrtab.c | 4 +- gcc/hash-table.h | 5 +- gcc/ipa-cp.c | 7 +- gcc/ipa-prop.c | 2 +- gcc/omp-low.c | 6 +- gcc/params.h | 4 +- gcc/testsuite/ChangeLog | 5 + gcc/testsuite/g++.dg/Wclass-memaccess.C | 1671 +++++++++++++++++++++++++++++++ gcc/tree-switch-conversion.c | 4 +- gcc/vec.h | 41 +- 18 files changed, 2185 insertions(+), 29 deletions(-) create mode 100644 gcc/testsuite/g++.dg/Wclass-memaccess.C (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b8c2f05..df4da47 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,27 @@ +2017-06-15 Martin Sebor + + PR c++/80560 + * dumpfile.c (dump_register): Avoid calling memset to initialize + a class with a default ctor. + * gcc.c (struct compiler): Remove const qualification. + * genattrtab.c (gen_insn_reserv): Replace memset with initialization. + * hash-table.h: Ditto. + * ipa-cp.c (allocate_and_init_ipcp_value): Replace memset with + assignment. + * ipa-prop.c (ipa_free_edge_args_substructures): Ditto. + * omp-low.c (lower_omp_ordered_clauses): Replace memset with + default ctor. + * params.h (struct param_info): Make struct members non-const. + * tree-switch-conversion.c (emit_case_bit_tests): Replace memset + with default initialization. + * vec.h (vec_copy_construct, vec_default_construct): New helper + functions. + (vec::copy, vec::splice, vec::reserve): Replace memcpy + with vec_copy_construct. + (vect::quick_grow_cleared): Replace memset with default ctor. + (vect::vec_safe_grow_cleared, vec_safe_grow_cleared): Same. + * doc/invoke.texi (-Wclass-memaccess): Document. + 2017-06-15 Ramana Radhakrishnan * emit-rtl.h (is_leaf): Update comment about local diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 1eba1c6..e8d1d57 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,8 @@ +2017-06-15 Martin Sebor + + PR c++/80560 + * c.opt (-Wclass-memaccess): New option. + 2017-06-14 Boris Kolpackov * c-opts.c (c_common_finish): Handle '-' special value to -MF. diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt index 37bb236..363d104 100644 --- a/gcc/c-family/c.opt +++ b/gcc/c-family/c.opt @@ -804,6 +804,10 @@ Wnon-template-friend C++ ObjC++ Var(warn_nontemplate_friend) Init(1) Warning Warn when non-templatized friend functions are declared within a template. +Wclass-memaccess +C++ ObjC++ Var(warn_class_memaccess) Warning LangEnabledBy(C++ ObjC++, Wall) +Warn for unsafe raw memory writes to objects of class types. + Wnon-virtual-dtor C++ ObjC++ Var(warn_nonvdtor) Warning LangEnabledBy(C++ ObjC++,Weffc++) Warn about non-virtual destructors. diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index b933392..ed307b6 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,11 @@ +2017-06-15 Martin Sebor + + PR c++/80560 + * call.c (first_non_public_field, maybe_warn_class_memaccess): New + functions. + (has_trivial_copy_assign_p, has_trivial_copy_p): Ditto. + (build_cxx_call): Call maybe_warn_class_memaccess. + 2017-06-14 Jakub Jelinek * cp-gimplify.c (cp_genericize_r): Turn most of the function diff --git a/gcc/cp/call.c b/gcc/cp/call.c index ef99683..9c3f1eb 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -8184,6 +8184,393 @@ build_over_call (struct z_candidate *cand, int flags, tsubst_flags_t complain) return call; } +/* Return the DECL of the first non-public data member of class TYPE + or null if none can be found. */ + +static tree +first_non_public_field (tree type) +{ + if (!CLASS_TYPE_P (type)) + return NULL_TREE; + + for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) + { + if (TREE_CODE (field) != FIELD_DECL) + continue; + if (TREE_STATIC (field)) + continue; + if (TREE_PRIVATE (field) || TREE_PROTECTED (field)) + return field; + } + + int i = 0; + + for (tree base_binfo, binfo = TYPE_BINFO (type); + BINFO_BASE_ITERATE (binfo, i, base_binfo); i++) + { + tree base = TREE_TYPE (base_binfo); + + if (tree field = first_non_public_field (base)) + return field; + } + + return NULL_TREE; +} + +/* Return true if all copy and move assignment operator overloads for + class TYPE are trivial and at least one of them is not deleted and, + when ACCESS is set, accessible. Return false otherwise. Set + HASASSIGN to true when the TYPE has a (not necessarily trivial) + copy or move assignment. */ + +static bool +has_trivial_copy_assign_p (tree type, bool access, bool *hasassign) +{ + tree fns = cp_assignment_operator_id (NOP_EXPR); + fns = lookup_fnfields_slot (type, fns); + + bool all_trivial = true; + + /* Iterate over overloads of the assignment operator, checking + accessible copy assignments for triviality. */ + + for (ovl_iterator oi (fns); oi; ++oi) + { + tree f = *oi; + + /* Skip operators that aren't copy assignments. */ + if (!copy_fn_p (f)) + continue; + + bool accessible = (!access || !(TREE_PRIVATE (f) || TREE_PROTECTED (f)) + || accessible_p (TYPE_BINFO (type), f, true)); + + /* Skip template assignment operators and deleted functions. */ + if (TREE_CODE (f) != FUNCTION_DECL || DECL_DELETED_FN (f)) + continue; + + if (accessible) + *hasassign = true; + + if (!accessible || !trivial_fn_p (f)) + all_trivial = false; + + /* Break early when both properties have been determined. */ + if (*hasassign && !all_trivial) + break; + } + + /* Return true if they're all trivial and one of the expressions + TYPE() = TYPE() or TYPE() = (TYPE&)() is valid. */ + tree ref = cp_build_reference_type (type, false); + return (all_trivial + && (is_trivially_xible (MODIFY_EXPR, type, type) + || is_trivially_xible (MODIFY_EXPR, type, ref))); +} + +/* Return true if all copy and move ctor overloads for class TYPE are + trivial and at least one of them is not deleted and, when ACCESS is + set, accessible. Return false otherwise. Set each element of HASCTOR[] + to true when the TYPE has a (not necessarily trivial) default and copy + (or move) ctor, respectively. */ + +static bool +has_trivial_copy_p (tree type, bool access, bool hasctor[2]) +{ + tree fns = lookup_fnfields_slot (type, complete_ctor_identifier); + + bool all_trivial = true; + + for (ovl_iterator oi (fns); oi; ++oi) + { + tree f = *oi; + + /* Skip template constructors. */ + if (TREE_CODE (f) != FUNCTION_DECL) + continue; + + bool cpy_or_move_ctor_p = copy_fn_p (f); + + /* Skip ctors other than default, copy, and move. */ + if (!cpy_or_move_ctor_p && !default_ctor_p (f)) + continue; + + if (DECL_DELETED_FN (f)) + continue; + + bool accessible = (!access || !(TREE_PRIVATE (f) || TREE_PROTECTED (f)) + || accessible_p (TYPE_BINFO (type), f, true)); + + if (accessible) + hasctor[cpy_or_move_ctor_p] = true; + + if (cpy_or_move_ctor_p && (!accessible || !trivial_fn_p (f))) + all_trivial = false; + + /* Break early when both properties have been determined. */ + if (hasctor[0] && hasctor[1] && !all_trivial) + break; + } + + return all_trivial; +} + +/* Issue a warning on a call to the built-in function FNDECL if it is + a raw memory write whose destination is not an object of (something + like) trivial or standard layout type with a non-deleted assignment + and copy ctor. Detects const correctness violations, corrupting + references, virtual table pointers, and bypassing non-trivial + assignments. */ + +static void +maybe_warn_class_memaccess (location_t loc, tree fndecl, tree *args) +{ + /* Except for bcopy where it's second, the destination pointer is + the first argument for all functions handled here. Compute + the index of the destination and source arguments. */ + unsigned dstidx = DECL_FUNCTION_CODE (fndecl) == BUILT_IN_BCOPY; + unsigned srcidx = !dstidx; + + tree dest = args[dstidx]; + if (!dest || !TREE_TYPE (dest) || !POINTER_TYPE_P (TREE_TYPE (dest))) + return; + + STRIP_NOPS (dest); + + tree srctype = NULL_TREE; + + /* Determine the type of the pointed-to object and whether it's + a complete class type. */ + tree desttype = TREE_TYPE (TREE_TYPE (dest)); + + if (!desttype || !COMPLETE_TYPE_P (desttype) || !CLASS_TYPE_P (desttype)) + return; + + /* Check to see if the raw memory call is made by a ctor or dtor + with this as the destination argument for the destination type. + If so, be more permissive. */ + if (current_function_decl + && (DECL_CONSTRUCTOR_P (current_function_decl) + || DECL_DESTRUCTOR_P (current_function_decl)) + && is_this_parameter (dest)) + { + tree ctx = DECL_CONTEXT (current_function_decl); + bool special = same_type_ignoring_top_level_qualifiers_p (ctx, desttype); + + tree binfo = TYPE_BINFO (ctx); + + /* A ctor and dtor for a class with no bases and no virtual functions + can do whatever they want. Bail early with no further checking. */ + if (special && !BINFO_VTABLE (binfo) && !BINFO_N_BASE_BINFOS (binfo)) + return; + } + + /* True if the class is trivial. */ + bool trivial = trivial_type_p (desttype); + + /* Set to true if DESTYPE has an accessible copy assignment. */ + bool hasassign = false; + /* True if all of the class' overloaded copy assignment operators + are all trivial (and not deleted) and at least one of them is + accessible. */ + bool trivassign = has_trivial_copy_assign_p (desttype, true, &hasassign); + + /* Set to true if DESTTYPE has an accessible default and copy ctor, + respectively. */ + bool hasctors[2] = { false, false }; + + /* True if all of the class' overloaded copy constructors are all + trivial (and not deleted) and at least one of them is accessible. */ + bool trivcopy = has_trivial_copy_p (desttype, true, hasctors); + + /* Set FLD to the first private/protected member of the class. */ + tree fld = trivial ? first_non_public_field (desttype) : NULL_TREE; + + /* The warning format string. */ + const char *warnfmt = NULL; + /* A suggested alternative to offer instead of the raw memory call. + Empty string when none can be come up with. */ + const char *suggest = ""; + bool warned = false; + + switch (DECL_FUNCTION_CODE (fndecl)) + { + case BUILT_IN_MEMSET: + if (!integer_zerop (args[1])) + { + /* Diagnose setting non-copy-assignable or non-trivial types, + or types with a private member, to (potentially) non-zero + bytes. Since the value of the bytes being written is unknown, + suggest using assignment instead (if one exists). Also warn + for writes into objects for which zero-initialization doesn't + mean all bits clear (pointer-to-member data, where null is all + bits set). Since the value being written is (most likely) + non-zero, simply suggest assignment (but not copy assignment). */ + suggest = "; use assignment instead"; + if (!trivassign) + warnfmt = G_("%qD writing to an object of type %#qT with " + "no trivial copy-assignment"); + else if (!trivial) + warnfmt = G_("%qD writing to an object of non-trivial type %#qT%s"); + else if (fld) + { + const char *access = TREE_PRIVATE (fld) ? "private" : "protected"; + warned = warning_at (loc, OPT_Wclass_memaccess, + "%qD writing to an object of type %#qT with " + "%qs member %qD", + fndecl, desttype, access, fld); + } + else if (!zero_init_p (desttype)) + warnfmt = G_("%qD writing to an object of type %#qT containing " + "a pointer to data member%s"); + + break; + } + /* Fall through. */ + + case BUILT_IN_BZERO: + /* Similarly to the above, diagnose clearing non-trivial or non- + standard layout objects, or objects of types with no assignmenmt. + Since the value being written is known to be zero, suggest either + copy assignment, copy ctor, or default ctor as an alternative, + depending on what's available. */ + + if (hasassign && hasctors[0]) + suggest = G_("; use assignment or value-initialization instead"); + else if (hasassign) + suggest = G_("; use assignment instead"); + else if (hasctors[0]) + suggest = G_("; use value-initialization instead"); + + if (!trivassign) + warnfmt = G_("%qD clearing an object of type %#qT with " + "no trivial copy-assignment%s"); + else if (!trivial) + warnfmt = G_("%qD clearing an object of non-trivial type %#qT%s"); + else if (!zero_init_p (desttype)) + warnfmt = G_("%qD clearing an object of type %#qT containing " + "a pointer-to-member%s"); + break; + + case BUILT_IN_BCOPY: + case BUILT_IN_MEMCPY: + case BUILT_IN_MEMMOVE: + case BUILT_IN_MEMPCPY: + /* Determine the type of the source object. */ + srctype = STRIP_NOPS (args[srcidx]); + srctype = TREE_TYPE (TREE_TYPE (srctype)); + + /* Since it's impossible to determine wheter the byte copy is + being used in place of assignment to an existing object or + as a substitute for initialization, assume it's the former. + Determine the best alternative to use instead depending on + what's not deleted. */ + if (hasassign && hasctors[1]) + suggest = G_("; use copy-assignment or copy-initialization instead"); + else if (hasassign) + suggest = G_("; use copy-assignment instead"); + else if (hasctors[1]) + suggest = G_("; use copy-initialization instead"); + + if (!trivassign) + warnfmt = G_("%qD writing to an object of type %#qT with no trivial " + "copy-assignment%s"); + else if (!trivially_copyable_p (desttype)) + warnfmt = G_("%qD writing to an object of non-trivially copyable " + "type %#qT%s"); + else if (!trivcopy) + warnfmt = G_("%qD writing to an object with a deleted copy constructor"); + + else if (!trivial + && !VOID_TYPE_P (srctype) + && !char_type_p (TYPE_MAIN_VARIANT (srctype)) + && !same_type_ignoring_top_level_qualifiers_p (desttype, + srctype)) + { + /* Warn when copying into a non-trivial object from an object + of a different type other than void or char. */ + warned = warning_at (loc, OPT_Wclass_memaccess, + "%qD copying an object of non-trivial type " + "%#qT from an array of %#qT", + fndecl, desttype, srctype); + } + else if (fld + && !VOID_TYPE_P (srctype) + && !char_type_p (TYPE_MAIN_VARIANT (srctype)) + && !same_type_ignoring_top_level_qualifiers_p (desttype, + srctype)) + { + const char *access = TREE_PRIVATE (fld) ? "private" : "protected"; + warned = warning_at (loc, OPT_Wclass_memaccess, + "%qD copying an object of type %#qT with " + "%qs member %qD from an array of %#qT; use " + "assignment or copy-initialization instead", + fndecl, desttype, access, fld, srctype); + } + else if (!trivial && TREE_CODE (args[2]) == INTEGER_CST) + { + /* Finally, warn on partial copies. */ + unsigned HOST_WIDE_INT typesize + = tree_to_uhwi (TYPE_SIZE_UNIT (desttype)); + if (unsigned HOST_WIDE_INT partial + = tree_to_uhwi (args[2]) % typesize) + warned = warning_at (loc, OPT_Wclass_memaccess, + (typesize - partial > 1 + ? G_("%qD writing to an object of " + "a non-trivial type %#qT leaves %wu " + "bytes unchanged") + : G_("%qD writing to an object of " + "a non-trivial type %#qT leaves %wu " + "byte unchanged")), + fndecl, desttype, typesize - partial); + } + break; + + case BUILT_IN_REALLOC: + + if (!trivially_copyable_p (desttype)) + warnfmt = G_("%qD moving an object of non-trivially copyable type " + "%#qT; use % and % instead"); + else if (!trivcopy) + warnfmt = G_("%qD moving an object of type %#qT with deleted copy " + "constructor; use % and % instead"); + else if (!get_dtor (desttype, tf_none)) + warnfmt = G_("%qD moving an object of type %#qT with deleted " + "destructor"); + else if (!trivial + && TREE_CODE (args[1]) == INTEGER_CST + && tree_int_cst_lt (args[1], TYPE_SIZE_UNIT (desttype))) + { + /* Finally, warn on reallocation into insufficient space. */ + warned = warning_at (loc, OPT_Wclass_memaccess, + "%qD moving an object of non-trivial type " + "%#qT and size %E into a region of size %E", + fndecl, desttype, TYPE_SIZE_UNIT (desttype), + args[1]); + } + break; + + default: + return; + } + + if (!warned && !warnfmt) + return; + + if (warnfmt) + { + if (suggest) + warned = warning_at (loc, OPT_Wclass_memaccess, + warnfmt, fndecl, desttype, suggest); + else + warned = warning_at (loc, OPT_Wclass_memaccess, + warnfmt, fndecl, desttype); + } + + if (warned) + inform (location_of (desttype), "%#qT declared here", desttype); +} + /* Build and return a call to FN, using NARGS arguments in ARGARRAY. This function performs no overload resolution, conversion, or other high-level operations. */ @@ -8216,6 +8603,10 @@ build_cxx_call (tree fn, int nargs, tree *argarray, if (!check_builtin_function_arguments (EXPR_LOCATION (fn), vNULL, fndecl, nargs, argarray)) return error_mark_node; + + /* Warn if the built-in writes to an object of a non-trivial type. */ + if (nargs) + maybe_warn_class_memaccess (loc, fndecl, argarray); } /* If it is a built-in array notation function, then the return type of diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 653bc07..d7027aa 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -215,7 +215,8 @@ in the following sections. -Wabi=@var{n} -Wabi-tag -Wconversion-null -Wctor-dtor-privacy @gol -Wdelete-non-virtual-dtor -Wliteral-suffix -Wmultiple-inheritance @gol -Wnamespaces -Wnarrowing @gol --Wnoexcept -Wnoexcept-type -Wnon-virtual-dtor -Wreorder -Wregister @gol +-Wnoexcept -Wnoexcept-type -Wclass-memaccess @gol +-Wnon-virtual-dtor -Wreorder -Wregister @gol -Weffc++ -Wstrict-null-sentinel -Wtemplates @gol -Wno-non-template-friend -Wold-style-cast @gol -Woverloaded-virtual -Wno-pmf-conversions @gol @@ -2920,6 +2921,23 @@ void g() noexcept; void h() @{ f(g); @} // in C++14 calls f, in C++1z calls f @end smallexample +@item -Wclass-memaccess @r{(C++ and Objective-C++ only)} +@opindex Wclass-memaccess +Warn when the destination of a call to a raw memory function such as +@code{memset} or @code{memcpy} is an object of class type writing into which +might bypass the class non-trivial or deleted constructor or copy assignment, +violate const-correctness or encapsulation, or corrupt the virtual table. +Modifying the representation of such objects may violate invariants maintained +by member functions of the class. For example, the call to @code{memset} +below is undefined becase it modifies a non-trivial class object and is, +therefore, diagnosed. The safe way to either initialize or clear the storage +of objects of such types is by using the appropriate constructor or assignment +operator, if one is available. +@smallexample +std::string str = "abc"; +memset (&str, 0, 3); +@end smallexample +The @option{-Wclass-memaccess} option is enabled by @option{-Wall}. @item -Wnon-virtual-dtor @r{(C++ and Objective-C++ only)} @opindex Wnon-virtual-dtor diff --git a/gcc/dumpfile.c b/gcc/dumpfile.c index c746d0b..6c55f05 100644 --- a/gcc/dumpfile.c +++ b/gcc/dumpfile.c @@ -187,9 +187,16 @@ dump_register (const char *suffix, const char *swtch, const char *glob, m_extra_dump_files = XRESIZEVEC (struct dump_file_info, m_extra_dump_files, m_extra_dump_files_alloced); + + /* Construct a new object in the space allocated above. */ + new (m_extra_dump_files + count) dump_file_info (); + } + else + { + /* Zero out the already constructed object. */ + m_extra_dump_files[count] = dump_file_info (); } - memset (&m_extra_dump_files[count], 0, sizeof (struct dump_file_info)); m_extra_dump_files[count].suffix = suffix; m_extra_dump_files[count].swtch = swtch; m_extra_dump_files[count].glob = glob; diff --git a/gcc/gcc.c b/gcc/gcc.c index 3292532..6d724b2 100644 --- a/gcc/gcc.c +++ b/gcc/gcc.c @@ -1259,9 +1259,9 @@ struct compiler const char *cpp_spec; /* If non-NULL, substitute this spec for `%C', rather than the usual cpp_spec. */ - const int combinable; /* If nonzero, compiler can deal with + int combinable; /* If nonzero, compiler can deal with multiple source files at once (IMA). */ - const int needs_preprocessing; /* If nonzero, source files need to + int needs_preprocessing; /* If nonzero, source files need to be run through a preprocessor. */ }; diff --git a/gcc/genattrtab.c b/gcc/genattrtab.c index 3629b5f..51dfe77 100644 --- a/gcc/genattrtab.c +++ b/gcc/genattrtab.c @@ -4703,8 +4703,8 @@ gen_insn_reserv (md_rtx_info *info) struct insn_reserv *decl = oballoc (struct insn_reserv); rtx def = info->def; - struct attr_desc attr; - memset (&attr, 0, sizeof (attr)); + struct attr_desc attr = { }; + attr.name = DEF_ATTR_STRING (XSTR (def, 0)); attr.loc = info->loc; diff --git a/gcc/hash-table.h b/gcc/hash-table.h index 0f7e21a..443d16c 100644 --- a/gcc/hash-table.h +++ b/gcc/hash-table.h @@ -803,7 +803,10 @@ hash_table::empty_slow () m_size_prime_index = nindex; } else - memset (entries, 0, size * sizeof (value_type)); + { + for ( ; size; ++entries, --size) + *entries = value_type (); + } m_n_deleted = 0; m_n_elements = 0; } diff --git a/gcc/ipa-cp.c b/gcc/ipa-cp.c index 3c9c3f2..c7e3c71 100644 --- a/gcc/ipa-cp.c +++ b/gcc/ipa-cp.c @@ -1471,8 +1471,7 @@ allocate_and_init_ipcp_value (tree source) { ipcp_value *val; - val = ipcp_cst_values_pool.allocate (); - memset (val, 0, sizeof (*val)); + val = new (ipcp_cst_values_pool.allocate ()) ipcp_value(); val->value = source; return val; } @@ -1486,8 +1485,8 @@ allocate_and_init_ipcp_value (ipa_polymorphic_call_context source) ipcp_value *val; // TODO - val = ipcp_poly_ctx_values_pool.allocate (); - memset (val, 0, sizeof (*val)); + val = new (ipcp_poly_ctx_values_pool.allocate ()) + ipcp_value(); val->value = source; return val; } diff --git a/gcc/ipa-prop.c b/gcc/ipa-prop.c index c73ffd7..292f3e2 100644 --- a/gcc/ipa-prop.c +++ b/gcc/ipa-prop.c @@ -3711,7 +3711,7 @@ void ipa_free_edge_args_substructures (struct ipa_edge_args *args) { vec_free (args->jump_functions); - memset (args, 0, sizeof (*args)); + *args = ipa_edge_args (); } /* Free all ipa_edge structures. */ diff --git a/gcc/omp-low.c b/gcc/omp-low.c index 9a16248..dd4a092 100644 --- a/gcc/omp-low.c +++ b/gcc/omp-low.c @@ -6320,7 +6320,11 @@ lower_omp_ordered_clauses (gimple_stmt_iterator *gsi_p, gomp_ordered *ord_stmt, return; wide_int *folded_deps = XALLOCAVEC (wide_int, 2 * len - 1); - memset (folded_deps, 0, sizeof (*folded_deps) * (2 * len - 1)); + + /* wide_int is not a POD so it must be default-constructed. */ + for (unsigned i = 0; i != 2 * len - 1; ++i) + new (static_cast(folded_deps + i)) wide_int (); + tree folded_dep = NULL_TREE; /* TRUE if the first dimension's offset is negative. */ bool neg_offset_p = false; diff --git a/gcc/params.h b/gcc/params.h index b61cff9..8b91660 100644 --- a/gcc/params.h +++ b/gcc/params.h @@ -42,7 +42,7 @@ struct param_info { /* The name used with the `--param =' switch to set this value. */ - const char *const option; + const char *option; /* The default value. */ int default_value; @@ -54,7 +54,7 @@ struct param_info int max_value; /* A short description of the option. */ - const char *const help; + const char *help; /* The optional names corresponding to the values. */ const char **value_names; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 34b6a9d..7e48992 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-15 Martin Sebor + + PR c++/80560 + * g++.dg/Wclass-memaccess.C: New test. + 2017-06-15 Janus Weil PR fortran/80983 diff --git a/gcc/testsuite/g++.dg/Wclass-memaccess.C b/gcc/testsuite/g++.dg/Wclass-memaccess.C new file mode 100644 index 0000000..4783438 --- /dev/null +++ b/gcc/testsuite/g++.dg/Wclass-memaccess.C @@ -0,0 +1,1671 @@ +/* PR c++/80560 - warn on undefined memory operations involving non-trivial + types + { dg-do compile } + { dg-options "-Wclass-memaccess -ftrack-macro-expansion=0" } */ + +typedef __SIZE_TYPE__ size_t; + +extern "C" +{ +void* memcpy (void*, const void*, size_t); +void* memmove (void*, const void*, size_t); +void* mempcpy (void*, const void*, size_t); +void* memset (void*, int, size_t); +void* realloc (void*, size_t); +} + +/* Ordinary bzcopy and bzero aren't recognized as special. */ +#define bcopy __builtin_bcopy +#define bzero __builtin_bzero + +void sink (void*); + +#define T(fn, arglist) ((fn arglist), sink (p)) + +#if !defined TEST || TEST == TEST_TRIVIAL + +/* Trivial can be manipulated by raw memory functions. */ +struct Trivial +{ + int i; unsigned bf: 1; char *s; char a[4]; + + // Non-copy assignment doesn't make the class non-trivial or not + // trivially assignable. + Trivial& operator= (int); + + // Likewise, template assignment doesn't make the class non-trivial + // or not trivially assignable. + template + Trivial& operator= (U); +}; + +void test (Trivial *p, void *q, int x) +{ + const size_t n = x; + + T (bzero, (p, 1)); + T (bzero, (p, n)); + T (bzero, (p, sizeof *p)); + T (bzero, (q, 1)); + T (bzero, (q, n)); + T (bzero, (q, sizeof *p)); + + T (bcopy, (p, q, 1)); + T (bcopy, (p, q, n)); + T (bcopy, (p, q, sizeof *p)); + T (bcopy, (q, p, 1)); + T (bcopy, (q, p, n)); + T (bcopy, (q, p, sizeof *p)); + + T (memcpy, (p, q, 1)); + T (memcpy, (p, q, n)); + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (q, p, 1)); + T (memcpy, (q, p, n)); + T (memcpy, (q, p, sizeof *p)); + + T (memset, (p, 0, 1)); + T (memset, (p, 0, n)); + T (memset, (p, 0, sizeof *p)); + T (memset, (q, 0, 1)); + T (memset, (q, 0, n)); + T (memset, (q, 0, sizeof *p)); + + T (memset, (p, 1, 1)); + T (memset, (p, 1, n)); + T (memset, (p, 1, sizeof *p)); + T (memset, (q, 1, 1)); + T (memset, (q, 1, n)); + T (memset, (q, 1, sizeof *p)); + + T (memset, (p, x, 1)); + T (memset, (p, x, n)); + T (memset, (p, x, sizeof *p)); + T (memset, (q, x, 1)); + T (memset, (q, x, n)); + T (memset, (q, x, sizeof *p)); + + T (memmove, (p, q, 1)); + T (memmove, (p, q, n)); + T (memmove, (p, q, sizeof *p)); + T (memmove, (q, p, 1)); + T (memmove, (q, p, n)); + T (memmove, (q, p, sizeof *p)); + + T (q = realloc, (p, 1)); + T (q = realloc, (p, n)); + T (q = realloc, (p, sizeof *p)); + + T (q = realloc, (q, 1)); + T (q = realloc, (q, n)); + T (q = realloc, (q, sizeof *p)); +} + +#endif + +#if !defined TEST || TEST == TEST_TRIVIAL_ACCESS + +/* TrivialAccess can be manipulated by raw memory functions in contexts + that have access to the trivial specia functions. */ +struct TrivialAccess +{ + int i; unsigned bf: 1; char *s; char a[4]; + +private: + TrivialAccess () = default; + TrivialAccess (const TrivialAccess&) = default; +protected: + TrivialAccess& operator= (const TrivialAccess&) = default; + + void test_member (const TrivialAccess*, int); + + friend void test_friend (TrivialAccess*, const TrivialAccess*, int); +}; + +void test (TrivialAccess *p, const TrivialAccess *q, int i) +{ + void *pv; + (void)&pv; + + /* Verify that a warning is issued when the copy ctor and copy + assignment are inaccessible. */ + T (bzero, (p, sizeof *p)); // { dg-warning "bzero" } + T (bcopy, (q, p, sizeof *p)); // { dg-warning "bcopy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (pv = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +void test_friend (TrivialAccess *p, const TrivialAccess *q, int i) +{ + void *pv; + (void)&pv; + + /* Verify that no warning is issued when the otherwise inaccessible + copy ctor and copy assignment can be accessed within the current + context. */ + T (bzero, (p, sizeof *p)); + T (bcopy, (q, p, sizeof *p)); + T (memcpy, (p, q, sizeof *p)); + T (memset, (p, i, sizeof *p)); + T (memmove, (p, q, sizeof *p)); + T (pv = realloc, (p, sizeof *p)); +} + +void TrivialAccess::test_member (const TrivialAccess *q, int i) +{ + void *pv; + (void)&pv; + + TrivialAccess *p = this; + + /* Verify that no warning is issued when the otherwise inaccessible + copy ctor and copy assignment can be accessed within the current + context. */ + T (bzero, (p, sizeof *p)); + T (bcopy, (q, p, sizeof *p)); + T (memcpy, (p, q, sizeof *p)); + T (memset, (p, i, sizeof *p)); + T (memmove, (p, q, sizeof *p)); + T (pv = realloc, (p, sizeof *p)); +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_DEFAULT + +/* HasDefault is trivially copyable but should be initialized by + the ctor, not bzero or memset. */ +struct HasDefault { char a[4]; HasDefault (); }; + +void test (HasDefault *p, const HasDefault &x, + void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // HasDefault is neither trivial nor standard-layout. The warning + // should mention the former since it's more permissive than the latter + // and so more informative. + T (bzero, (p, sizeof *p)); // { dg-warning "bzero(\[^\n\r\]*). clearing an object of non-trivial type .struct HasDefault.; use assignment or value-initialization instead" } + + T (memset, (p, 0, sizeof *p)); // { dg-warning ".void\\* memset(\[^\n\r\]*). clearing an object of non-trivial type .struct HasDefault.; use assignment or value-initialization instead" } + + T (memset, (p, 1, sizeof *p)); // { dg-warning ".void\\* memset(\[^\n\r\]*). writing to an object of non-trivial type .struct HasDefault.; use assignment instead" } + + T (memset, (p, i, sizeof *p)); // { dg-warning ".void\\* memset(\[^\n\r\]*). writing to an object of non-trivial type .struct HasDefault.; use assignment instead" } + + // Copying from another object of the same type is fine. + T (bcopy, (&x, p, sizeof *p)); + T (bcopy, (&x, p, n)); + + T (memcpy, (p, &x, sizeof *p)); + T (memcpy, (p, &x, n)); + + // Copying from a void* or character buffer is also fine. + T (bcopy, (q, p, sizeof *p)); + T (bcopy, (q, p, n)); + T (bcopy, (s, p, sizeof *p)); + T (bcopy, (s, p, n)); + + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (p, q, n)); + T (memcpy, (p, s, sizeof *p)); + T (memcpy, (p, s, n)); + + T (memmove, (p, q, sizeof *p)); + T (memmove, (p, q, n)); + T (memmove, (p, s, sizeof *p)); + T (memmove, (p, s, n)); + + T (mempcpy, (p, q, sizeof *p)); + T (mempcpy, (p, q, n)); + T (mempcpy, (p, s, sizeof *p)); + T (mempcpy, (p, s, n)); + + // ...but partial copies are diagnosed. + T (memcpy, (p, &x, 1)); // { dg-warning "writing to an object of a non-trivial type .struct HasDefault. leaves 3 bytes unchanged" } */ + T (memmove, (p, q, 2)); // { dg-warning "writing to an object of a non-trivial type .struct HasDefault. leaves 2 bytes unchanged" } */ + T (mempcpy, (p, q, 3)); // { dg-warning "writing to an object of a non-trivial type .struct HasDefault. leaves 1 byte unchanged" } */ + + // Otherwise, copying from an object of an unrelated type is diagnosed. + T (memcpy, (p, ia, sizeof *p)); // { dg-warning ".void\\* memcpy(\[^\n\r\]*). copying an object of non-trivial type .struct HasDefault. from an array of .const int." } + extern long *ip; + T (memcpy, (p, ip, sizeof *p)); // { dg-warning ".void\\* memcpy(\[^\n\r\]*). copying an object of non-trivial type .struct HasDefault. from an array of .long." } + + T (memmove, (p, ia, sizeof *p)); // { dg-warning ".void\\* memmove(\[^\n\r\]*). copying an object of non-trivial type .struct HasDefault. from an array of .const int." } + + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning ".void\\* mempcpy(\[^\n\r\]*). copying an object of non-trivial type .struct HasDefault. from an array of .const int." } + + // Reallocating is the same as calling memcpy except that only + // shrinking reallocation is diagnosed. + T (q = realloc, (p, 1)); // { dg-warning "moving an object of non-trivial type .struct HasDefault. and size 4 into a region of size 1" } + T (q = realloc, (p, n)); + T (q = realloc, (p, sizeof *p)); + T (q = realloc, (p, sizeof *p + 1)); +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_TEMPLATE_DEFAULT + +/* HasTemplateDefault should be initialized by means of the ctor, + not zeroed out by bzero/memset. */ +struct HasTemplateDefault +{ + template + HasTemplateDefault (U); +}; + +void test (HasTemplateDefault *p, const HasTemplateDefault &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because value initialization is + // invalid (the template ctor makes default ctor unavailable). + T (bzero, (p, sizeof *p)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying from an object of any type is okay. + T (bcopy, (&x, p, sizeof *p)); + T (bcopy, (q, p, sizeof *p)); + T (bcopy, (s, p, sizeof *p)); + T (bcopy, (ia, p, sizeof *p)); // { dg-warning "bcopy" } + + T (memcpy, (p, &x, sizeof *p)); + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (p, s, sizeof *p)); + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); + T (memmove, (p, q, sizeof *p)); + T (memmove, (p, s, sizeof *p)); + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); + T (mempcpy, (p, q, sizeof *p)); + T (mempcpy, (p, s, sizeof *p)); + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); + T (q = realloc, (p, n)); + T (q = realloc, (p, sizeof *p)); +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_COPY + +/* HasCopy should be copied using the copy ctor or assignment, not + by memcpy or memmove. Since it's non-trivial, it should not be zeroed + out by bzero/memset either and should instead use assignment and/or + value initialization. */ +struct HasCopy { int i; HasCopy (const HasCopy&); }; + +void test (HasCopy *p, const HasCopy &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because value initialization is invalid + // (the copy ctor makes no default ctor unavailable). Since the type + // has no default ctor verify that the suggested alternative does not + // include value-initialization. + T (bzero, (p, sizeof *p)); // { dg-warning "clearing an object of non-trivial type .struct HasCopy.; use assignment instead" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying from an object of any type is diagnosed. + T (bcopy, (&x, p, sizeof *p)); // { dg-warning "bcopy" } + T (bcopy, (q, p, sizeof *p)); // { dg-warning "bcopy" } + T (bcopy, (s, p, sizeof *p)); // { dg-warning "bcopy" } + T (bcopy, (ia, p, sizeof *p)); // { dg-warning "bcopy" } + + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_DEFAULT_AND_COPY + +/* HasDefaultAndCopy is like HasCopy above but its default ctor takes + a default argument to verify that the suggested alternative offered + by the warning includes the default ctor (i.e., the test verifies + that the default ctor is recognized as such despite taking an argument. */ + +struct HasDefaultAndCopy +{ + HasDefaultAndCopy (int = 0); // default ctor + HasDefaultAndCopy (const HasDefaultAndCopy&); +}; + +void test (HasDefaultAndCopy *p, const HasDefaultAndCopy &x) +{ + T (bzero, (p, sizeof *p)); // { dg-warning "clearing an object of non-trivial type .struct HasDefaultAndCopy.; use assignment or value-initialization instead" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "clearing an object of non-trivial type .struct HasDefaultAndCopy.; use assignment or value-initialization instead" } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_PRIVATE_COPY + +/* HasPrivateCopy cannot be copied using memcpy or memmove. Since it's + non-trivial, it it should not be zeroed out by bzero/memset either + and should instead use assignment and/or value initialization. */ +struct HasPrivateCopy { + int i; +private: + HasPrivateCopy (const HasPrivateCopy&); +}; + +void test (HasPrivateCopy *p, const HasPrivateCopy &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because value initialization is + // invalid (the copy ctor makes no default ctor unavailable). + // Verify also that the suggestion offers assignment but not + // value initialization (since the lattare is not available). + T (bzero, (p, sizeof *p)); // { dg-warning "clearing an object of non-trivial type .struct HasPrivateCopy.; use assignment instead" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying from an object of any type is diagnosed. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning ".void\\* memcpy(\[^\n\r\]*). writing to an object of non-trivially copyable type .struct HasPrivateCopy.; use copy-assignment instead" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_DTOR + +/* HasDtor should be initialized using aggregate or memberwise intialization, + not bzero or memset. */ +struct HasDtor { int i; ~HasDtor (); }; + +void test (HasDtor *p, const HasDtor &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed only because it's difficult not to. + // Otherwise, a class that's non-trivial only because it has + // a non-trivial dtor can be safely zeroed out (that's what + // value-initializing it does). + T (bzero, (p, sizeof *p)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying from an object of any type is diagnosed simply because + // a class with a user-defined dtor is not trivially copyable. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_DELETED_DTOR + +// HasDeletedDtor is trivial so clearing and cpying it is okay. +// Relocation would bypass the deleted dtor and so it's diagnosed. + +struct HasDeletedDtor +{ + int i; + ~HasDeletedDtor () = delete; +}; + +void test (HasDeletedDtor *p, const HasDeletedDtor &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + T (bzero, (p, sizeof *p)); + T (memset, (p, 0, sizeof *p)); + T (memset, (p, 1, sizeof *p)); + T (memset, (p, i, sizeof *p)); + + T (memcpy, (p, &x, sizeof *p)); + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (p, s, sizeof *p)); + T (memcpy, (p, ia, sizeof *p)); + + T (memmove, (p, &x, sizeof *p)); + T (memmove, (p, q, sizeof *p)); + T (memmove, (p, s, sizeof *p)); + T (memmove, (p, ia, sizeof *p)); + + T (mempcpy, (p, &x, sizeof *p)); + T (mempcpy, (p, q, sizeof *p)); + T (mempcpy, (p, s, sizeof *p)); + T (mempcpy, (p, ia, sizeof *p)); + + // Reallocating is diagnosed. + T (q = realloc, (p, 1)); // { dg-warning "moving an object of type .struct HasDeletedDtor. with deleted destructor" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_PRIVATE_DTOR + +// Unlike HasDeletedDtor, HasPrivateDtor is okay to zero-out and copy +// but not relocate because doing so would bypass the deleted dtor.. + +struct HasPrivateDtor +{ + int i; +private: + ~HasPrivateDtor (); +}; + +void test (HasPrivateDtor *p, const HasPrivateDtor &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + T (bzero, (p, sizeof *p)); // { dg-warning "clearing an object of non-trivial type .struct HasPrivateDtor.; use assignment or value-initialization instead" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "writing to an object of non-trivially copyable type .struct HasPrivateDtor.; use copy-assignment or copy-initialization instead" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is diagnosed. + T (q = realloc, (p, 1)); // { dg-warning "moving an object of non-trivially copyable type .struct HasPrivateDtor." } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_COPY_ASSIGN + +/* HasCopyAssign should be copied using the copy ctor or assignment, not + by memcpy or memmove. */ +struct HasCopyAssign { void operator= (HasCopyAssign&); }; + +void test (HasCopyAssign *p, const HasCopyAssign &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because it when used with an existing + // (already constructed) object in lieu of assigning a new value + // to it would bypass the user-defined assignment. + T (bzero, (p, sizeof *p)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying from an object of any type is diagnosed. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_MOVE_ASSIGN + +/* Like HasCopyAssign, HasMoveAssign should be copied using the copy + ctor or assignment, not by memcpy or memmove. */ +struct HasMoveAssign +{ +#if __cplusplus > 199711L + void operator= (HasMoveAssign&&); +#else + // C++ 98 has no reference references. Simply repeat the HasCopyAssign + // test to avoid having to add a conditional to every dg-warning directive. + void operator= (const HasMoveAssign&); +#endif +}; + +void test (HasMoveAssign *p, const HasMoveAssign &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because it when used with an existing + // (already constructed) object in lieu of assigning a new value + // to it would bypass the user-defined assignment. + T (bzero, (p, sizeof *p)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying from an object of any type is diagnosed. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_TRIVIAL_COPY_HAS_MOVE_ASSIGN + +/* TrivialCopyHasMoveAssign should be copied using the copy ctor + or assignment, not by memcpy or memmove. */ +struct TrivialCopyHasMoveAssign +{ + typedef TrivialCopyHasMoveAssign Self; + + Self& operator= (const Self&) = default; + +#if __cplusplus > 199711L + Self& operator= (Self&&); +#else + // C++ 98 has no reference references. Fake the test by adding + // a non-const overload of the assignment operator (which should + // have the same effect). + Self& operator= (Self&); +#endif +}; + +void test (TrivialCopyHasMoveAssign *p, const TrivialCopyHasMoveAssign &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because it when used with an existing + // (already constructed) object in lieu of assigning a new value + // to it would bypass the user-defined assignment. + T (bzero, (p, sizeof *p)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying from an object of any type is diagnosed. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_TRIVIAL_MOVE_HAS_COPY_ASSIGN + +/* TrivialMoveNontrivialCopyAssign should be copied using the copy ctor + or assignment, not by memcpy or memmove. */ +struct TrivialMoveNontrivialCopyAssign +{ + typedef TrivialMoveNontrivialCopyAssign Self; + + Self& operator= (const Self&); +#if __cplusplus > 199711L + // C++ 98 has no reference references. Fake the test by simply + // not declaring the move assignment. + Self& operator= (Self&&) = default; +#endif +}; + +void test (TrivialMoveNontrivialCopyAssign *p, + const TrivialMoveNontrivialCopyAssign &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because it when used with an existing + // (already constructed) object in lieu of assigning a new value + // to it would bypass the user-defined assignment. + T (bzero, (p, sizeof *p)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying from an object of any type is diagnosed. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_TRIVIAL_ASSIGN_REF_OVERLOAD + +/* TrivialAssignRefOverload is a trivial type. */ +struct TrivialAssignRefOverload { + int i; + typedef TrivialAssignRefOverload Self; + + Self& operator= (Self&) = default; + Self& operator= (const Self&) = delete; + Self& operator= (volatile Self&) = delete; + Self& operator= (const volatile Self&) = delete; +}; + +void test (TrivialAssignRefOverload *p, const TrivialAssignRefOverload &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + T (bzero, (p, sizeof *p)); + T (memset, (p, 0, sizeof *p)); + T (memset, (p, 1, sizeof *p)); + T (memset, (p, i, sizeof *p)); + + T (memcpy, (p, &x, sizeof *p)); + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (p, s, sizeof *p)); + T (memcpy, (p, ia, sizeof *p)); + + T (memmove, (p, &x, sizeof *p)); + T (memmove, (p, q, sizeof *p)); + T (memmove, (p, s, sizeof *p)); + T (memmove, (p, ia, sizeof *p)); + + T (mempcpy, (p, &x, sizeof *p)); + T (mempcpy, (p, q, sizeof *p)); + T (mempcpy, (p, s, sizeof *p)); + T (mempcpy, (p, ia, sizeof *p)); + + T (q = realloc, (p, 1)); + T (q = realloc, (p, n)); + T (q = realloc, (p, sizeof *p)); +} + +#endif + +#if !defined TEST || TEST == TEST_TRIVIAL_ASSIGN_CSTREF_OVERLOAD + +/* TrivialAssignCstOverload is a trivial type. */ +struct TrivialAssignCstRefOverload { + int i; + typedef TrivialAssignCstRefOverload Self; + + Self& operator= (Self&) = delete; + Self& operator= (const Self&) = default; + Self& operator= (volatile Self&) = delete; + Self& operator= (const volatile Self&) = delete; +}; + +void test (TrivialAssignCstRefOverload *p, + const TrivialAssignCstRefOverload &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + T (bzero, (p, sizeof *p)); + T (memset, (p, 0, sizeof *p)); + T (memset, (p, 1, sizeof *p)); + T (memset, (p, i, sizeof *p)); + + T (memcpy, (p, &x, sizeof *p)); + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (p, s, sizeof *p)); + T (memcpy, (p, ia, sizeof *p)); + + T (memmove, (p, &x, sizeof *p)); + T (memmove, (p, q, sizeof *p)); + T (memmove, (p, s, sizeof *p)); + T (memmove, (p, ia, sizeof *p)); + + T (mempcpy, (p, &x, sizeof *p)); + T (mempcpy, (p, q, sizeof *p)); + T (mempcpy, (p, s, sizeof *p)); + T (mempcpy, (p, ia, sizeof *p)); + + T (q = realloc, (p, 1)); + T (q = realloc, (p, n)); + T (q = realloc, (p, sizeof *p)); +} + +#endif + +#if !defined TEST || TEST == TEST_TRIVIAL_REF_HAS_VOLREF_ASSIGN + +struct TrivialRefHasVolRefAssign +{ + typedef TrivialRefHasVolRefAssign Self; + + Self& operator= (Self&) = default; + Self& operator= (volatile Self&); +}; + +void test (TrivialRefHasVolRefAssign *p, + const TrivialRefHasVolRefAssign &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because it when used with an existing + // (already constructed) object in lieu of assigning a new value + // to it would bypass the user-defined assignment. + T (bzero, (p, sizeof *p)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying from an object of any type is diagnosed. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_VOLREF_ASSIGN + +struct HasVolRefAssign { + int i; + typedef HasVolRefAssign Self; + + Self& operator= (volatile Self&); +}; + +void test (HasVolRefAssign *p, const HasVolRefAssign &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because it when used with an existing + // (already constructed) object in lieu of assigning a new value + // to it would bypass the user-defined assignment. + T (bzero, (p, sizeof *p)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying from an object of any type is diagnosed. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_VIRTUALS + +/* HasVirtuals should only be manipulated by the special member functions + and not by bzero, memcpy, or any other raw memory function. Doing + otherwse might corrupt the the vtable pointer. */ +struct HasVirtuals { int i; virtual void foo (); }; + +void test (HasVirtuals *p, const HasVirtuals &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because it corrupts the vtable. + T (bzero, (p, sizeof *p)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying is diagnosed because when used to initialize an object + // could incorrectly initialize the vtable. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_CONST_DATA + +/* HasConstData should only be initialized using aggregate initializatoon + and not cleared by bzero, or copied into using memcpy. Since it's not + assignable allowing, raw memory functions to write into it would defeat + const-correctness. */ +struct HasConstData { const char a[4]; }; + +void test (HasConstData *p, const HasConstData &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // The following is ill-formed because HasConstData's cannot + // be assigned (the assignment is implicitly deleted). For + // that reason all raw memory operations are diagnosed. + // *p = x; + + // Zeroing out is diagnosed because if used with an existing + // (already initialized) object could break const correctness. + // Since the default ctor and copy assignment are both deleted, + // verify that they're not suggested as a possible alternative. + T (bzero, (p, sizeof *p)); // { dg-warning "clearing an object of type .struct HasConstData. with no trivial copy-assignment \\\[" "c++ 11 and later" { target { c++11 } } } + // { dg-warning "clearing an object of type .struct HasConstData. with no trivial copy-assignment" "c++ 98" { target { c++98_only } } .-1 } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Copying is also diagnosed. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "writing to an object of type .struct HasConstData. with no trivial copy-assignment; use copy-initialization instead" "c++ 11 and later" { target { c++11 } } } + // { dg-warning "writing to an object of type .struct HasConstData. with no trivial copy-assignment" "c++ 98" { target { c++98_only } } .-1 } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is not diagnosed except in C++ 98 due to a bug. + T (q = realloc, (p, 1)); // { dg-warning "moving an object of non-trivially copyable type .struct HasConstData.; use .new. and .delete. instead" "c++98" { target { c++98_only } } } + T (q = realloc, (p, n)); // { dg-warning "realloc" "c++98" { target { c++98_only } } } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" "c++98" { target { c++98_only } } } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_REFERENCE + +/* HasReference should only be initialized using aggregate initializatoon + and not cleared by bzero, or copied into using memcpy. Since it's not + assignable, allowing raw memory functions to write into it could + corrupt the reference. */ +struct HasReference { int &ci; }; + +void test (HasReference *p, const HasReference &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Similarly to HasConstData, the following is ill-formed because + // Hasreference cannot be assigned (the assignment is implicitly + // deleted). For that reason all raw memory operations are diagnosed. + // *p = x; + + // Zeroing out is diagnosed because if used with an existing + // (already initialized) object would invalidate the reference. + // Since copy-assignment is deleted verify it's not suggested + // as an alternative. (C++ 11 and later only; C++ 98 is broken). + T (bzero, (p, sizeof *p)); // { dg-warning "clearing an object of type .struct HasReference. with no trivial copy-assignment \\\[" "c++ 11 and later" { target { c++11 } } } + // { dg-warning "clearing an object of type .struct HasReference. with no trivial copy-assignment" "c++ 98" { target { c++98_only } } .-1 } + T (bzero, (p, n)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 0, n)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, n)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, n)); // { dg-warning "memset" } + + // Copying is also diagnosed. + T (memcpy, (p, &x, sizeof *p)); // { dg-warning "writing to an object of type .struct HasReference. with no trivial copy-assignment; use copy-initialization instead" "c++ 11 and later" { target { c++11 } } } + // { dg-warning "writing to an object of type .struct HasReference. with no trivial copy-assignment" "c++ 98" { target { c++98_only } } .-1 } + T (memcpy, (p, &x, n)); // { dg-warning "memcpy" } + T (memcpy, (p, q, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, q, n)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, n)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, n)); // { dg-warning "memcpy" } + + T (memmove, (p, &x, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + + T (mempcpy, (p, &x, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is not diagnosed because a type with a reference + // is (perhaps surprisingly) trivially copyable. It is diagnosed + // in C++ 98 because of a bug, but it seems like it should be + // diagnosed in all modes. + T (q = realloc, (p, 1)); // { dg-warning "realloc" "c++ 98" { target { c++98_only } } } + T (q = realloc, (p, n)); // { dg-warning "realloc" "c++ 98" { target { c++98_only } } } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" "c++ 98" { target { c++98_only } } } +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_MEM_DATA_PTR + +/* HasMemDataPtr should only be initialized using aggregate initializatoon + and not cleared by bzero or written into using memset because its + representation is different from ordinary scalars (a null member data + pointer is all ones). It can be copied into using memcpy from an object + of the same type or from a character buffer. */ +struct HasMemDataPtr { int HasMemDataPtr::*p; }; + +void test (HasMemDataPtr *p, const HasMemDataPtr &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is diagnosed because a null member data pointer has + // a representation that's all bits set. + T (bzero, (p, sizeof *p)); // { dg-warning "clearing an object of type .struct HasMemDataPtr. containing a pointer-to-member" } + T (bzero, (p, n)); // { dg-warning "bzero" } + T (memset, (p, 0, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 0, n)); // { dg-warning "memset" } + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, 1, n)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, n)); // { dg-warning "memset" } + + // Copying is not diagnosed. + T (memcpy, (p, &x, sizeof *p)); + T (memcpy, (p, &x, n)); + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (p, q, n)); + T (memcpy, (p, s, sizeof *p)); + T (memcpy, (p, s, n)); + T (memcpy, (p, ia, sizeof *p)); + T (memcpy, (p, ia, n)); + + T (memmove, (p, &x, sizeof *p)); + T (memmove, (p, q, sizeof *p)); + T (memmove, (p, s, sizeof *p)); + T (memmove, (p, ia, sizeof *p)); + + T (mempcpy, (p, &x, sizeof *p)); + T (mempcpy, (p, q, sizeof *p)); + T (mempcpy, (p, s, sizeof *p)); + T (mempcpy, (p, ia, sizeof *p)); + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); + T (q = realloc, (p, n)); + T (q = realloc, (p, sizeof *p)); + T (q = realloc, (p, sizeof *p + 1)); +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_SOME_PRIVATE_DATA + +/* HasSomePrivateData can be initialized using value initialization + and should not be written to using memset with a non-zero argument. + Doing otherwise would break encapsulation. */ +struct HasSomePrivateData { char a[2]; private: char b[2]; }; + +void test (HasSomePrivateData *p, const HasSomePrivateData &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is not diagnosed because it's equivalent to value + // initialization. + T (bzero, (p, sizeof *p)); + T (memset, (p, 0, sizeof *p)); + // Calling memset with a (possibly) non-zero argument is diagnosed + // because it breaks encapsulation. + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Calling memcpy to copy from an object of the same type or from + // a character or void buffer is not diagnosed because that's what + // copy construction and copy assignment do. + T (memcpy, (p, &x, sizeof *p)); + T (memcpy, (p, &x, n)); + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (p, s, sizeof *p)); + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, n)); // { dg-warning "memcpy" } + + // Same as memcpy above. + T (memmove, (p, &x, sizeof *p)); + T (memmove, (p, &x, n)); + T (memmove, (p, q, sizeof *p)); + T (memmove, (p, s, sizeof *p)); + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, n)); // { dg-warning "memmove" } + + // Same as memcpy above. + T (mempcpy, (p, &x, sizeof *p)); + T (mempcpy, (p, &x, n)); + T (mempcpy, (p, q, sizeof *p)); + T (mempcpy, (p, q, n)); + T (mempcpy, (p, s, sizeof *p)); + T (mempcpy, (p, s, n)); + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, n)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy except that partial + // copies are not diagnosed. + T (q = realloc, (p, 1)); + T (q = realloc, (p, n)); + T (q = realloc, (p, sizeof *p)); + T (q = realloc, (p, sizeof *p + 1)); +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_SOME_PROTECTED_DATA + +/* Similarly to HasSomePrivateData, HasSomeProtectedData can be + initialized using value initialization and should not be written + to using memset with a non-zero argument. Doing otherwise would + break encapsulation. */ +struct HasSomeProtectedData { char a[2]; protected: char b[2]; }; + +void test (HasSomeProtectedData *p, const HasSomeProtectedData &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is not diagnosed because it's equivalent to value + // initialization. + T (bzero, (p, sizeof *p)); + T (memset, (p, 0, sizeof *p)); + // Calling memset with a (possibly) non-zero argument is diagnosed + // because it breaks encapsulation. + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Calling memcpy to copy from an object of the same type or from + // a character or void buffer is not diagnosed because that's what + // copy construction and copy assignment do. + T (memcpy, (p, &x, sizeof *p)); + T (memcpy, (p, &x, n)); + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (p, s, sizeof *p)); + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, n)); // { dg-warning "memcpy" } + + // Same as memcpy above. + T (memmove, (p, &x, sizeof *p)); + T (memmove, (p, &x, n)); + T (memmove, (p, q, sizeof *p)); + T (memmove, (p, s, sizeof *p)); + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, n)); // { dg-warning "memmove" } + + // Same as memcpy above. + T (mempcpy, (p, &x, sizeof *p)); + T (mempcpy, (p, &x, n)); + T (mempcpy, (p, q, sizeof *p)); + T (mempcpy, (p, q, n)); + T (mempcpy, (p, s, sizeof *p)); + T (mempcpy, (p, s, n)); + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, n)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy except that partial + // copies are not diagnosed. + T (q = realloc, (p, 1)); + T (q = realloc, (p, n)); + T (q = realloc, (p, sizeof *p)); + T (q = realloc, (p, sizeof *p + 1)); +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_ALL_PRIVATE_DATA + +/* Similarly to HasSomePrivateData, HasAllPrivateData should only be + initialized using value initializatoon and should not be written + to using memset with non-zero argument. They are tested separately + because unlike the former classes, these are standard layout. */ +struct HasAllPrivateData { private: char a[4]; }; + +void test (HasAllPrivateData *p, const HasAllPrivateData &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is not diagnosed because it's equivalent to value + // initialization. + T (bzero, (p, sizeof *p)); + T (memset, (p, 0, sizeof *p)); + // Calling memset with a (possibly) non-zero argument is diagnosed + // because it breaks encapsulation. + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Calling memcpy to copy from an object of the same type or from + // a character or void buffer is not diagnosed because that's what + // copy construction and copy assignment do. + T (memcpy, (p, &x, sizeof *p)); + T (memcpy, (p, &x, n)); + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (p, s, sizeof *p)); + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, n)); // { dg-warning "memcpy" } + + // Same as memcpy above. + T (memmove, (p, &x, sizeof *p)); + T (memmove, (p, &x, n)); + T (memmove, (p, q, sizeof *p)); + T (memmove, (p, s, sizeof *p)); + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, n)); // { dg-warning "memmove" } + + // Same as memcpy above. + T (mempcpy, (p, &x, sizeof *p)); + T (mempcpy, (p, &x, n)); + T (mempcpy, (p, q, sizeof *p)); + T (mempcpy, (p, q, n)); + T (mempcpy, (p, s, sizeof *p)); + T (mempcpy, (p, s, n)); + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, n)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy except that partial + // copies are not diagnosed. + T (q = realloc, (p, 1)); + T (q = realloc, (p, n)); + T (q = realloc, (p, sizeof *p)); + T (q = realloc, (p, sizeof *p + 1)); +} + +#endif + +#if !defined TEST || TEST == TEST_HAS_ALL_PROTECTED_DATA + +/* Similarly to HasSomeProtectedData, HasAllProtectedData should only + be initialized using value initializatoon and should not be written + to using memset with non-zero argument. They are tested separately + because unlike the former classes, these are standard layout. */ +struct HasAllProtectedData { protected: char a[4]; }; + +void test (HasAllProtectedData *p, const HasAllProtectedData &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // Zeroing out is not diagnosed because it's equivalent to value + // initialization. + T (bzero, (p, sizeof *p)); + T (memset, (p, 0, sizeof *p)); + // Calling memset with a (possibly) non-zero argument is diagnosed + // because it breaks encapsulation. + T (memset, (p, 1, sizeof *p)); // { dg-warning "memset" } + T (memset, (p, i, sizeof *p)); // { dg-warning "memset" } + + // Calling memcpy to copy from an object of the same type or from + // a character or void buffer is not diagnosed because that's what + // copy construction and copy assignment do. + T (memcpy, (p, &x, sizeof *p)); + T (memcpy, (p, &x, n)); + T (memcpy, (p, q, sizeof *p)); + T (memcpy, (p, s, sizeof *p)); + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, ia, n)); // { dg-warning "memcpy" } + + // Same as memcpy above. + T (memmove, (p, &x, sizeof *p)); + T (memmove, (p, &x, n)); + T (memmove, (p, q, sizeof *p)); + T (memmove, (p, s, sizeof *p)); + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, ia, n)); // { dg-warning "memmove" } + + // Same as memcpy above. + T (mempcpy, (p, &x, sizeof *p)); + T (mempcpy, (p, &x, n)); + T (mempcpy, (p, q, sizeof *p)); + T (mempcpy, (p, q, n)); + T (mempcpy, (p, s, sizeof *p)); + T (mempcpy, (p, s, n)); + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, ia, n)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy except that partial + // copies are not diagnosed. + T (q = realloc, (p, 1)); + T (q = realloc, (p, n)); + T (q = realloc, (p, sizeof *p)); + T (q = realloc, (p, sizeof *p + 1)); +} + +#endif + +#if !defined TEST || TEST == TEST_DEFAULT_CTOR_PRIVATE_ASSIGN + +/* Used to verify suggested alternatives. */ +struct HasDefaultPrivateAssign +{ + char a[4]; + HasDefaultPrivateAssign (); +private: + void operator= (HasDefaultPrivateAssign&); +}; + +void test (HasDefaultPrivateAssign *p, const HasDefaultPrivateAssign &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // HasDefaultPrivateAssign isn't trivial or assignable. Verify + // that the alternative suggested in the warning is to use copy or + // default but not assignment. + T (bzero, (p, sizeof *p)); // { dg-warning "bzero(\[^\n\r\]*). clearing an object of type .struct HasDefaultPrivateAssign. with no trivial copy-assignment; use value-initialization instead" "c++ 11 and later" { target { c++11 } } } + // { dg-warning "bzero(\[^\n\r\]*). clearing an object of type .struct HasDefaultPrivateAssign. with no trivial copy-assignment; use value-initialization instead" "c++ 98" { target { c++98_only } } .-1 } + + T (memset, (p, 0, sizeof *p)); // { dg-warning ".void\\* memset(\[^\n\r\]*). clearing an object of type .struct HasDefaultPrivateAssign. with (deleted|no trivial) copy-assignment; use value-initialization instead" } + + T (memset, (p, 1, sizeof *p)); // { dg-warning ".void\\* memset(\[^\n\r\]*). writing to an object of type .struct HasDefaultPrivateAssign. with (deleted|no trivial) copy-assignment" } + + T (memset, (p, i, sizeof *p)); // { dg-warning ".void\\* memset(\[^\n\r\]*). writing to an object of type .struct HasDefaultPrivateAssign. with (deleted|no trivial) copy-assignment" } + + // Copying from another object of the same type is diagnosed because + // the copy assignment is inaccessible. Verify that the suggested + // alternative is not copy assignment (C++ 98 is busted). + T (memcpy, (p, &x, sizeof *p)); // { dg-warning ".void\\* memcpy(\[^\n\r\]*). writing to an object of type .struct HasDefaultPrivateAssign. with no trivial copy-assignment; use copy-initialization instead" "c++11 and later" { target c++11 } } + // { dg-warning ".void\\* memcpy(\[^\n\r\]*). writing to an object of type .struct HasDefaultPrivateAssign. with no trivial copy-assignment" "c++98" { target c++98_only } .-1 } + T (memcpy, (p, &x, n)); // { dg-warning "memcpy" } + + // Similarly for copying from a void* or character buffer. + T (memcpy, (p, q, sizeof *p)); // { dg-warning ".void\\* memcpy(\[^\n\r\]*). writing to an object of type .struct HasDefaultPrivateAssign. with no trivial copy-assignment; use copy-initialization instead" "c++11 and later" { target c++11 } } + // { dg-warning ".void\\* memcpy(\[^\n\r\]*). writing to an object of type .struct HasDefaultPrivateAssign. with no trivial copy-assignment" "c++98" { target c++98_only } ,-1 } + T (memcpy, (p, q, n)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, n)); // { dg-warning "memcpy" } + + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, n)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, n)); // { dg-warning "memmove" } + + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, n)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, n)); // { dg-warning "mempcpy" } + + // Same for partial copies are diagnosed. + T (memcpy, (p, &x, 1)); // { dg-warning "writing to an object of type .struct HasDefaultPrivateAssign. with (deleted|no trivial) copy-assignment" } */ + T (memmove, (p, q, 2)); // { dg-warning "memmove" } */ + T (mempcpy, (p, q, 3)); // { dg-warning "mempcpy" } */ + + // Otherwise, copying from an object of an unrelated type is diagnosed. + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "writing to an object of type .struct HasDefaultPrivateAssign. with (deleted|no trivial) copy-assignment." } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_DEFAULT_CTOR_DELETED_ASSIGN + +/* Used to verify suggested alternatives. */ +struct HasDefaultDeletedAssign +{ + char a[4]; + HasDefaultDeletedAssign (); +private: + void operator= (HasDefaultDeletedAssign&); +}; + +void test (HasDefaultDeletedAssign *p, const HasDefaultDeletedAssign &x, + const void *q, const unsigned char *s, const int ia[]) +{ + const int i = *ia; + const size_t n = *ia; + + // HasDefaultDeletedAssign isn't trivial or assignable. Verify + // that the alternative suggested in the warning is to use copy or + // default but not assignment. + T (bzero, (p, sizeof *p)); // { dg-warning "bzero(\[^\n\r\]*). clearing an object of type .struct HasDefaultDeletedAssign. with no trivial copy-assignment; use value-initialization instead" "c++ 11 and later" { target { c++11 } } } + // { dg-warning "bzero(\[^\n\r\]*). clearing an object of type .struct HasDefaultDeletedAssign. with no trivial copy-assignment; use value-initialization instead" "c++ 98" { target { c++98_only } } .-1 } + + T (memset, (p, 0, sizeof *p)); // { dg-warning ".void\\* memset(\[^\n\r\]*). clearing an object of type .struct HasDefaultDeletedAssign. with (deleted|no trivial) copy-assignment; use value-initialization instead" } + + T (memset, (p, 1, sizeof *p)); // { dg-warning ".void\\* memset(\[^\n\r\]*). writing to an object of type .struct HasDefaultDeletedAssign. with (deleted|no trivial) copy-assignment" } + + T (memset, (p, i, sizeof *p)); // { dg-warning ".void\\* memset(\[^\n\r\]*). writing to an object of type .struct HasDefaultDeletedAssign. with (deleted|no trivial) copy-assignment" } + + // Copying from another object of the same type is diagnosed because + // the copy assignment is inaccessible. Verify that the suggested + // alternative is not copy assignment (C++ 98 is busted). + T (memcpy, (p, &x, sizeof *p)); // { dg-warning ".void\\* memcpy(\[^\n\r\]*). writing to an object of type .struct HasDefaultDeletedAssign. with no trivial copy-assignment; use copy-initialization instead" "c++11 and later" { target c++11 } } + // { dg-warning ".void\\* memcpy(\[^\n\r\]*). writing to an object of type .struct HasDefaultDeletedAssign. with no trivial copy-assignment" "c++98" { target c++98_only } .-1 } + T (memcpy, (p, &x, n)); // { dg-warning "memcpy" } + + // Similarly for copying from a void* or character buffer. + T (memcpy, (p, q, sizeof *p)); // { dg-warning ".void\\* memcpy(\[^\n\r\]*). writing to an object of type .struct HasDefaultDeletedAssign. with no trivial copy-assignment; use copy-initialization instead" "c++11 and later" { target c++11 } } + // { dg-warning ".void\\* memcpy(\[^\n\r\]*). writing to an object of type .struct HasDefaultDeletedAssign. with no trivial copy-assignment" "c++98" { target c++98_only } ,-1 } + T (memcpy, (p, q, n)); // { dg-warning "memcpy" } + T (memcpy, (p, s, sizeof *p)); // { dg-warning "memcpy" } + T (memcpy, (p, s, n)); // { dg-warning "memcpy" } + + T (memmove, (p, q, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, q, n)); // { dg-warning "memmove" } + T (memmove, (p, s, sizeof *p)); // { dg-warning "memmove" } + T (memmove, (p, s, n)); // { dg-warning "memmove" } + + T (mempcpy, (p, q, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, q, n)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, sizeof *p)); // { dg-warning "mempcpy" } + T (mempcpy, (p, s, n)); // { dg-warning "mempcpy" } + + // Same for partial copies are diagnosed. + T (memcpy, (p, &x, 1)); // { dg-warning "writing to an object of type .struct HasDefaultDeletedAssign. with (deleted|no trivial) copy-assignment" } */ + T (memmove, (p, q, 2)); // { dg-warning "memmove" } */ + T (mempcpy, (p, q, 3)); // { dg-warning "mempcpy" } */ + + // Otherwise, copying from an object of an unrelated type is diagnosed. + T (memcpy, (p, ia, sizeof *p)); // { dg-warning "writing to an object of type .struct HasDefaultDeletedAssign. with (deleted|no trivial) copy-assignment." } + T (memmove, (p, ia, sizeof *p)); // { dg-warning "memmove" } + T (mempcpy, (p, ia, sizeof *p)); // { dg-warning "mempcpy" } + + // Reallocating is the same as calling memcpy. + T (q = realloc, (p, 1)); // { dg-warning "realloc" } + T (q = realloc, (p, n)); // { dg-warning "realloc" } + T (q = realloc, (p, sizeof *p)); // { dg-warning "realloc" } +} + +#endif + +#if !defined TEST || TEST == TEST_EXPRESSION + +void test_expr (int i) +{ + struct TestClass { TestClass () { } }; + TestClass a, b; + + static void *p; + + T (bzero, (i < 0 ? &a : &b, 1)); // { dg-warning "bzero" } +} + +#endif + +#if !defined TEST || TEST == TEST_CTOR + +void test_ctor () +{ +#undef T +#define T(fn, arglist) (fn arglist, sink (this)) + + static void *p; + + struct TestBase + { + TestBase () + { + /* A ctor of a base class with no virtual function can do whatever + it wants. */ + T (bzero, (this, sizeof *this)); + T (memset, (this, 0, sizeof *this)); + T (memcpy, (this, p, sizeof *this)); + T (memmove, (this, p, sizeof *this)); + T (mempcpy, (this, p, sizeof *this)); + } + + ~TestBase () + { + /* A dtor of a base class with no virtual function can do whatever + it wants. */ + T (bzero, (this, sizeof *this)); + T (memset, (this, 0, sizeof *this)); + T (memcpy, (this, p, sizeof *this)); + T (memmove, (this, p, sizeof *this)); + T (mempcpy, (this, p, sizeof *this)); + } + }; + + struct TestBaseVtable + { + TestBaseVtable () + { + /* A ctor of a base class with virtual function is treated + as an ordinary function. */ + T (bzero, (this, sizeof *this)); // { dg-warning "bzero" } + T (memset, (this, 0, sizeof *this)); // { dg-warning "memset" } + T (memcpy, (this, p, sizeof *this)); // { dg-warning "memcpy" } + T (memmove, (this, p, sizeof *this)); // { dg-warning "memmove" } + T (mempcpy, (this, p, sizeof *this)); // { dg-warning "mempcpy" } + } + + ~TestBaseVtable () + { + /* A dtor of a base class with virtual function is treated + as an ordinary function. */ + T (bzero, (this, sizeof *this)); // { dg-warning "bzero" } + T (memset, (this, 0, sizeof *this)); // { dg-warning "memset" } + T (memcpy, (this, p, sizeof *this)); // { dg-warning "memcpy" } + T (memmove, (this, p, sizeof *this)); // { dg-warning "memmove" } + T (mempcpy, (this, p, sizeof *this)); // { dg-warning "mempcpy" } + } + + virtual void foo (); + }; + + struct TestDerived: HasDefault + { + TestDerived () + { + /* A derived class ctor is treated as an ordinary function. */ + T (bzero, (this, sizeof *this)); // { dg-warning "bzero" } + T (memset, (this, 0, sizeof *this)); // { dg-warning "memset" } + T (memcpy, (this, p, sizeof *this)); + T (memmove, (this, p, sizeof *this)); + T (mempcpy, (this, p, sizeof *this)); + } + }; + + struct TestDerivedDtor: HasDefault + { + ~TestDerivedDtor () + { + /* A derived class dtor is treated as an ordinary function though + it probably shouldn't be unless the base dtor is trivial. But + it doesn't seem worth the trouble. */ + T (bzero, (this, sizeof *this)); // { dg-warning "bzero" } + T (memset, (this, 0, sizeof *this)); // { dg-warning "memset" } + T (memcpy, (this, p, sizeof *this)); // { dg-warning "memcpy" } + T (memmove, (this, p, sizeof *this)); // { dg-warning "memmove" } + T (mempcpy, (this, p, sizeof *this)); // { dg-warning "mempcpy" } + } + }; +} + +#endif + +// { dg-prune-output "defaulted and deleted functions" } diff --git a/gcc/tree-switch-conversion.c b/gcc/tree-switch-conversion.c index 66db20f..72927bf 100644 --- a/gcc/tree-switch-conversion.c +++ b/gcc/tree-switch-conversion.c @@ -268,7 +268,7 @@ static void emit_case_bit_tests (gswitch *swtch, tree index_expr, tree minval, tree range, tree maxval) { - struct case_bit_test test[MAX_CASE_BIT_TESTS]; + struct case_bit_test test[MAX_CASE_BIT_TESTS] = { }; unsigned int i, j, k; unsigned int count; @@ -293,8 +293,6 @@ emit_case_bit_tests (gswitch *swtch, tree index_expr, int prec = TYPE_PRECISION (word_type_node); wide_int wone = wi::one (prec); - memset (&test, 0, sizeof (test)); - /* Get the edge for the default case. */ tmp = gimple_switch_default_label (swtch); default_bb = label_to_block (CASE_LABEL (tmp)); diff --git a/gcc/vec.h b/gcc/vec.h index 755a1f8..cbdd439 100644 --- a/gcc/vec.h +++ b/gcc/vec.h @@ -407,6 +407,26 @@ struct GTY((user)) vec { }; +/* Default-construct N elements in DST. */ + +template +inline void +vec_default_construct (T *dst, unsigned n) +{ + for ( ; n; ++dst, --n) + ::new (static_cast(dst)) T (); +} + +/* Copy-construct N elements in DST from *SRC. */ + +template +inline void +vec_copy_construct (T *dst, const T *src, unsigned n) +{ + for ( ; n; ++dst, ++src, --n) + ::new (static_cast(dst)) T (*src); +} + /* Type to provide NULL values for vec. This is used to provide nil initializers for vec instances. Since vec must be a POD, we cannot have proper ctor/dtor for it. To initialize @@ -612,7 +632,7 @@ vec_safe_grow_cleared (vec *&v, unsigned len CXX_MEM_STAT_INFO) { unsigned oldlen = vec_safe_length (v); vec_safe_grow (v, len PASS_MEM_STAT); - memset (&(v->address ()[oldlen]), 0, sizeof (T) * (len - oldlen)); + vec_default_construct (v->address () + oldlen, len - oldlen); } @@ -818,7 +838,7 @@ vec::copy (ALONE_MEM_STAT_DECL) const { vec_alloc (new_vec, len PASS_MEM_STAT); new_vec->embedded_init (len, len); - memcpy (new_vec->address (), m_vecdata, sizeof (T) * len); + vec_copy_construct (new_vec->address (), m_vecdata, len); } return new_vec; } @@ -835,7 +855,7 @@ vec::splice (const vec &src) if (len) { gcc_checking_assert (space (len)); - memcpy (address () + length (), src.address (), len * sizeof (T)); + vec_copy_construct (end (), src.address (), len); m_vecpfx.m_num += len; } } @@ -1089,13 +1109,12 @@ inline void vec::quick_grow_cleared (unsigned len) { unsigned oldlen = length (); - size_t sz = sizeof (T) * (len - oldlen); + size_t growby = len - oldlen; quick_grow (len); - if (sz != 0) - memset (&(address ()[oldlen]), 0, sz); + if (growby != 0) + vec_default_construct (address () + oldlen, growby); } - /* Garbage collection support for vec. */ template @@ -1454,7 +1473,7 @@ vec::reserve (unsigned nelems, bool exact MEM_STAT_DECL) va_heap::reserve (m_vec, nelems, exact PASS_MEM_STAT); if (handle_auto_vec) { - memcpy (m_vec->address (), oldvec->address (), sizeof (T) * oldsize); + vec_copy_construct (m_vec->address (), oldvec->address (), oldsize); m_vec->m_vecpfx.m_num = oldsize; } @@ -1616,10 +1635,10 @@ inline void vec::safe_grow_cleared (unsigned len MEM_STAT_DECL) { unsigned oldlen = length (); - size_t sz = sizeof (T) * (len - oldlen); + size_t growby = len - oldlen; safe_grow (len PASS_MEM_STAT); - if (sz != 0) - memset (&(address ()[oldlen]), 0, sz); + if (growby != 0) + vec_default_construct (address () + oldlen, growby); } -- cgit v1.1 From 32e37414af3e1e236a2c7400c9d7178ede77ce4d Mon Sep 17 00:00:00 2001 From: Yury Gribov Date: Fri, 16 Jun 2017 07:16:34 +0000 Subject: re PR tree-optimization/81089 (ICE: tree check: expected ssa_name, have integer_cst in register_edge_assert_for_2, at tree-vrp.c:5023) 2017-06-16 Yury Gribov PR tree-optimization/81089 * tree-vrp.c (is_masked_range_test): Validate operands of subexpression. From-SVN: r249237 --- gcc/ChangeLog | 6 ++++++ gcc/tree-vrp.c | 7 +++---- 2 files changed, 9 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index df4da47..3f883c2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-16 Yury Gribov + + PR tree-optimization/81089 + * tree-vrp.c (is_masked_range_test): Validate operands of + subexpression. + 2017-06-15 Martin Sebor PR c++/80560 diff --git a/gcc/tree-vrp.c b/gcc/tree-vrp.c index a7424a3..9ca3924 100644 --- a/gcc/tree-vrp.c +++ b/gcc/tree-vrp.c @@ -5651,8 +5651,9 @@ is_masked_range_test (tree name, tree valt, enum tree_code cond_code, || gimple_assign_rhs_code (def_stmt) != BIT_AND_EXPR) return false; + tree t = gimple_assign_rhs1 (def_stmt); tree maskt = gimple_assign_rhs2 (def_stmt); - if (TREE_CODE (maskt) != INTEGER_CST) + if (TREE_CODE (t) != SSA_NAME || TREE_CODE (maskt) != INTEGER_CST) return false; wide_int mask = maskt; @@ -5663,11 +5664,9 @@ is_masked_range_test (tree name, tree valt, enum tree_code cond_code, || (val & mask) != val) return false; - tree t = gimple_assign_rhs1 (def_stmt); - tree type = TREE_TYPE (t); - bool is_range = cond_code == EQ_EXPR; + tree type = TREE_TYPE (t); wide_int min = wi::min_value (type), max = wi::max_value (type); -- cgit v1.1 From b783399af92647bd0765b9d51afab04dea31344b Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 16 Jun 2017 11:13:28 +0200 Subject: re PR sanitizer/81094 (-fsanitize=object-size does not instrument aggregate call arguments) PR sanitizer/81094 * ubsan.c (instrument_null): Add T argument, use it instead of computing it based on IS_LHS. (instrument_object_size): Likewise. (pass_ubsan::execute): Adjust instrument_null and instrument_object_size callers to pass gimple_get_lhs or gimple_assign_rhs1 result to it. Use instrument_null instead of calling get_base_address and instrument_mem_ref. Handle aggregate call arguments for object-size sanitization. * c-c++-common/ubsan/object-size-11.c: New test. From-SVN: r249239 --- gcc/ChangeLog | 12 +++++ gcc/testsuite/ChangeLog | 5 +++ gcc/testsuite/c-c++-common/ubsan/object-size-11.c | 53 +++++++++++++++++++++++ gcc/ubsan.c | 32 ++++++++------ 4 files changed, 89 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/ubsan/object-size-11.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3f883c2..d6f2d72 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2017-06-16 Jakub Jelinek + + PR sanitizer/81094 + * ubsan.c (instrument_null): Add T argument, use it instead + of computing it based on IS_LHS. + (instrument_object_size): Likewise. + (pass_ubsan::execute): Adjust instrument_null and + instrument_object_size callers to pass gimple_get_lhs or + gimple_assign_rhs1 result to it. Use instrument_null instead of + calling get_base_address and instrument_mem_ref. Handle + aggregate call arguments for object-size sanitization. + 2017-06-16 Yury Gribov PR tree-optimization/81089 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7e48992..2257edc 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-16 Jakub Jelinek + + PR sanitizer/81094 + * c-c++-common/ubsan/object-size-11.c: New test. + 2017-06-15 Martin Sebor PR c++/80560 diff --git a/gcc/testsuite/c-c++-common/ubsan/object-size-11.c b/gcc/testsuite/c-c++-common/ubsan/object-size-11.c new file mode 100644 index 0000000..866c7ed --- /dev/null +++ b/gcc/testsuite/c-c++-common/ubsan/object-size-11.c @@ -0,0 +1,53 @@ +/* PR sanitizer/81094 */ +/* { dg-do run } */ +/* { dg-skip-if "" { *-*-* } { "*" } { "-O2" } } */ +/* { dg-options "-fsanitize=object-size" } */ + +#define N 20 + +struct S { int i; }; + +__attribute__((noinline, noclone)) void +f0 (struct S s) +{ + asm volatile ("" : : "r" (s.i) : "memory"); +} + +__attribute__((noinline, noclone)) void +f1 (int i) +{ + char *orig; + struct S *p; + orig = (char *) __builtin_calloc (N, sizeof (struct S)); + p = (struct S *) orig; + f0 (*(p + i)); + f0 (p[i]); + p++; + f0 (p[i - 1]); + f0 (*(p + i - 1)); + __builtin_free (orig); +} + +/* { dg-output "load of address \[^\n\r]* with insufficient space for an object of type 'struct S'\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*note: pointer points here\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*\\^\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*load of address \[^\n\r]* with insufficient space for an object of type 'struct S'\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*note: pointer points here\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*\\^\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*load of address \[^\n\r]* with insufficient space for an object of type 'struct S'\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*note: pointer points here\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*\\^\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*load of address \[^\n\r]* with insufficient space for an object of type 'struct S'\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*note: pointer points here\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*\\^" } */ + +int +main () +{ + f1 (N); + return 0; +} diff --git a/gcc/ubsan.c b/gcc/ubsan.c index cee525c..52ba5b5 100644 --- a/gcc/ubsan.c +++ b/gcc/ubsan.c @@ -1204,10 +1204,8 @@ instrument_mem_ref (tree mem, tree base, gimple_stmt_iterator *iter, /* Perform the pointer instrumentation. */ static void -instrument_null (gimple_stmt_iterator gsi, bool is_lhs) +instrument_null (gimple_stmt_iterator gsi, tree t, bool is_lhs) { - gimple *stmt = gsi_stmt (gsi); - tree t = is_lhs ? gimple_get_lhs (stmt) : gimple_assign_rhs1 (stmt); /* Handle also e.g. &s->i. */ if (TREE_CODE (t) == ADDR_EXPR) t = TREE_OPERAND (t, 0); @@ -1754,11 +1752,10 @@ instrument_nonnull_return (gimple_stmt_iterator *gsi) points to an out-of-bounds location. */ static void -instrument_object_size (gimple_stmt_iterator *gsi, bool is_lhs) +instrument_object_size (gimple_stmt_iterator *gsi, tree t, bool is_lhs) { gimple *stmt = gsi_stmt (*gsi); location_t loc = gimple_location (stmt); - tree t = is_lhs ? gimple_get_lhs (stmt) : gimple_assign_rhs1 (stmt); tree type; tree index = NULL_TREE; HOST_WIDE_INT size_in_bytes; @@ -1989,9 +1986,9 @@ pass_ubsan::execute (function *fun) if (sanitize_flags_p (SANITIZE_NULL | SANITIZE_ALIGNMENT, fun->decl)) { if (gimple_store_p (stmt)) - instrument_null (gsi, true); + instrument_null (gsi, gimple_get_lhs (stmt), true); if (gimple_assign_single_p (stmt)) - instrument_null (gsi, false); + instrument_null (gsi, gimple_assign_rhs1 (stmt), false); if (is_gimple_call (stmt)) { unsigned args_num = gimple_call_num_args (stmt); @@ -2000,10 +1997,7 @@ pass_ubsan::execute (function *fun) tree arg = gimple_call_arg (stmt, i); if (is_gimple_reg (arg) || is_gimple_min_invariant (arg)) continue; - tree base = get_base_address (arg); - if (TREE_CODE (base) == MEM_REF - && TREE_CODE (TREE_OPERAND (base, 0)) == SSA_NAME) - instrument_mem_ref (arg, base, &gsi, false); + instrument_null (gsi, arg, false); } } } @@ -2033,9 +2027,21 @@ pass_ubsan::execute (function *fun) if (sanitize_flags_p (SANITIZE_OBJECT_SIZE, fun->decl)) { if (gimple_store_p (stmt)) - instrument_object_size (&gsi, true); + instrument_object_size (&gsi, gimple_get_lhs (stmt), true); if (gimple_assign_load_p (stmt)) - instrument_object_size (&gsi, false); + instrument_object_size (&gsi, gimple_assign_rhs1 (stmt), + false); + if (is_gimple_call (stmt)) + { + unsigned args_num = gimple_call_num_args (stmt); + for (unsigned i = 0; i < args_num; ++i) + { + tree arg = gimple_call_arg (stmt, i); + if (is_gimple_reg (arg) || is_gimple_min_invariant (arg)) + continue; + instrument_object_size (&gsi, arg, false); + } + } } gsi_next (&gsi); -- cgit v1.1 From 9d2c6e2eb72324b10160ce1117a8ab600be94bad Mon Sep 17 00:00:00 2001 From: Maxim Kuvyrkov Date: Fri, 16 Jun 2017 09:30:43 +0000 Subject: Add prefetch configuration to aarch64 backend. * config/aarch64/aarch64-protos.h (struct cpu_prefetch_tune): New tune structure. (struct tune_params): Use cpu_prefetch_tune instead of cache_line_size. [Unrelated to main purpose of the patch] Place the pointer field last to enable type checking errors when tune structure are wrongly merged. * config/aarch64/aarch64.c (generic_prefetch_tune,) (exynosm1_prefetch_tune, qdf24xx_prefetch_tune,) (thunderx2t99_prefetch_tune): New tune constants. (tune_params *_tunings): Update all tunings (no functional change). (aarch64_override_options_internal): Set PARAM_SIMULTANEOUS_PREFETCHES, PARAM_L1_CACHE_SIZE, PARAM_L1_CACHE_LINE_SIZE, and PARAM_L2_CACHE_SIZE from tunings structures. Change-Id: I1ddbac1863dcf078a2e5b14dd904debc76a7da94 From-SVN: r249240 --- gcc/ChangeLog | 15 ++++++ gcc/config/aarch64/aarch64-protos.h | 16 ++++-- gcc/config/aarch64/aarch64.c | 102 +++++++++++++++++++++++++++--------- 3 files changed, 105 insertions(+), 28 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d6f2d72..a78e736 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2017-06-16 Maxim Kuvyrkov + + * config/aarch64/aarch64-protos.h (struct cpu_prefetch_tune): + New tune structure. + (struct tune_params): Use cpu_prefetch_tune instead of cache_line_size. + [Unrelated to main purpose of the patch] Place the pointer field last + to enable type checking errors when tune structure are wrongly merged. + * config/aarch64/aarch64.c (generic_prefetch_tune,) + (exynosm1_prefetch_tune, qdf24xx_prefetch_tune,) + (thunderx2t99_prefetch_tune): New tune constants. + (tune_params *_tunings): Update all tunings (no functional change). + (aarch64_override_options_internal): Set PARAM_SIMULTANEOUS_PREFETCHES, + PARAM_L1_CACHE_SIZE, PARAM_L1_CACHE_LINE_SIZE, and PARAM_L2_CACHE_SIZE + from tunings structures. + 2017-06-16 Jakub Jelinek PR sanitizer/81094 diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index ac91865..bb06139 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -203,6 +203,15 @@ struct cpu_approx_modes const unsigned int recip_sqrt; /* Reciprocal square root. */ }; +/* Cache prefetch settings for prefetch-loop-arrays. */ +struct cpu_prefetch_tune +{ + const int num_slots; + const int l1_cache_size; + const int l1_cache_line_size; + const int l2_cache_size; +}; + struct tune_params { const struct cpu_cost_table *insn_extra_cost; @@ -224,9 +233,6 @@ struct tune_params int min_div_recip_mul_df; /* Value for aarch64_case_values_threshold; or 0 for the default. */ unsigned int max_case_values; - /* Value for PARAM_L1_CACHE_LINE_SIZE; or 0 to use the default. */ - unsigned int cache_line_size; - /* An enum specifying how to take into account CPU autoprefetch capabilities during instruction scheduling: - AUTOPREFETCHER_OFF: Do not take autoprefetch capabilities into account. @@ -244,6 +250,10 @@ struct tune_params } autoprefetcher_model; unsigned int extra_tuning_flags; + + /* Place prefetch struct pointer at the end to enable type checking + errors when tune_params misses elements (e.g., from erroneous merges). */ + const struct cpu_prefetch_tune *prefetch; }; #define AARCH64_FUSION_PAIR(x, name) \ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 239ba72..e3296c0 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -526,6 +526,39 @@ static const cpu_approx_modes xgene1_approx_modes = AARCH64_APPROX_ALL /* recip_sqrt */ }; +/* Generic prefetch settings (which disable prefetch). */ +static const cpu_prefetch_tune generic_prefetch_tune = +{ + 0, /* num_slots */ + -1, /* l1_cache_size */ + -1, /* l1_cache_line_size */ + -1 /* l2_cache_size */ +}; + +static const cpu_prefetch_tune exynosm1_prefetch_tune = +{ + 0, /* num_slots */ + -1, /* l1_cache_size */ + 64, /* l1_cache_line_size */ + -1 /* l2_cache_size */ +}; + +static const cpu_prefetch_tune qdf24xx_prefetch_tune = +{ + 0, /* num_slots */ + -1, /* l1_cache_size */ + 64, /* l1_cache_line_size */ + -1 /* l2_cache_size */ +}; + +static const cpu_prefetch_tune thunderx2t99_prefetch_tune = +{ + 0, /* num_slots */ + -1, /* l1_cache_size */ + 64, /* l1_cache_line_size */ + -1 /* l2_cache_size */ +}; + static const struct tune_params generic_tunings = { &cortexa57_extra_costs, @@ -546,9 +579,9 @@ static const struct tune_params generic_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &generic_prefetch_tune }; static const struct tune_params cortexa35_tunings = @@ -572,9 +605,9 @@ static const struct tune_params cortexa35_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &generic_prefetch_tune }; static const struct tune_params cortexa53_tunings = @@ -598,9 +631,9 @@ static const struct tune_params cortexa53_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &generic_prefetch_tune }; static const struct tune_params cortexa57_tunings = @@ -624,9 +657,9 @@ static const struct tune_params cortexa57_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_RENAME_FMA_REGS) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_RENAME_FMA_REGS), /* tune_flags. */ + &generic_prefetch_tune }; static const struct tune_params cortexa72_tunings = @@ -650,9 +683,9 @@ static const struct tune_params cortexa72_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &generic_prefetch_tune }; static const struct tune_params cortexa73_tunings = @@ -676,11 +709,13 @@ static const struct tune_params cortexa73_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &generic_prefetch_tune }; + + static const struct tune_params exynosm1_tunings = { &exynosm1_extra_costs, @@ -701,9 +736,9 @@ static const struct tune_params exynosm1_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 48, /* max_case_values. */ - 64, /* cache_line_size. */ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &exynosm1_prefetch_tune }; static const struct tune_params thunderx_tunings = @@ -726,9 +761,9 @@ static const struct tune_params thunderx_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW), /* tune_flags. */ + &generic_prefetch_tune }; static const struct tune_params xgene1_tunings = @@ -751,9 +786,9 @@ static const struct tune_params xgene1_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - 0, /* cache_line_size. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &generic_prefetch_tune }; static const struct tune_params qdf24xx_tunings = @@ -777,9 +812,9 @@ static const struct tune_params qdf24xx_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - 64, /* cache_line_size. */ tune_params::AUTOPREFETCHER_STRONG, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &qdf24xx_prefetch_tune }; static const struct tune_params thunderx2t99_tunings = @@ -802,9 +837,9 @@ static const struct tune_params thunderx2t99_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - 64, /* cache_line_size. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &thunderx2t99_prefetch_tune }; /* Support for fine-grained override of the tuning structures. */ @@ -8747,10 +8782,27 @@ aarch64_override_options_internal (struct gcc_options *opts) opts->x_param_values, global_options_set.x_param_values); - /* Set the L1 cache line size. */ - if (selected_cpu->tune->cache_line_size != 0) + /* Set up parameters to be used in prefetching algorithm. Do not + override the defaults unless we are tuning for a core we have + researched values for. */ + if (aarch64_tune_params.prefetch->num_slots > 0) + maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, + aarch64_tune_params.prefetch->num_slots, + opts->x_param_values, + global_options_set.x_param_values); + if (aarch64_tune_params.prefetch->l1_cache_size >= 0) + maybe_set_param_value (PARAM_L1_CACHE_SIZE, + aarch64_tune_params.prefetch->l1_cache_size, + opts->x_param_values, + global_options_set.x_param_values); + if (aarch64_tune_params.prefetch->l1_cache_line_size >= 0) maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, - selected_cpu->tune->cache_line_size, + aarch64_tune_params.prefetch->l1_cache_line_size, + opts->x_param_values, + global_options_set.x_param_values); + if (aarch64_tune_params.prefetch->l2_cache_size >= 0) + maybe_set_param_value (PARAM_L2_CACHE_SIZE, + aarch64_tune_params.prefetch->l2_cache_size, opts->x_param_values, global_options_set.x_param_values); -- cgit v1.1 From 16b2cafd0088500dc098121ed6d1aa622f1dc8a5 Mon Sep 17 00:00:00 2001 From: Maxim Kuvyrkov Date: Fri, 16 Jun 2017 09:30:52 +0000 Subject: Enable -fprefetch-loop-arrays at given optimization level. * config/aarch64/aarch64.c (aarch64_override_options_internal): Set flag_prefetch_loop_arrays according to tuning data. Change-Id: Id41411e671e0a55dc7268e0ad0a4e8ff1421c90a From-SVN: r249241 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64.c | 21 +++++++++++++++++---- 3 files changed, 23 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a78e736..0ed2ac1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Maxim Kuvyrkov + * config/aarch64/aarch64.c (aarch64_override_options_internal): + Set flag_prefetch_loop_arrays according to tuning data. + +2017-06-16 Maxim Kuvyrkov + * config/aarch64/aarch64-protos.h (struct cpu_prefetch_tune): New tune structure. (struct tune_params): Use cpu_prefetch_tune instead of cache_line_size. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index bb06139..bfe44a7 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -210,6 +210,7 @@ struct cpu_prefetch_tune const int l1_cache_size; const int l1_cache_line_size; const int l2_cache_size; + const int default_opt_level; }; struct tune_params diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index e3296c0..324a0f1 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -532,7 +532,8 @@ static const cpu_prefetch_tune generic_prefetch_tune = 0, /* num_slots */ -1, /* l1_cache_size */ -1, /* l1_cache_line_size */ - -1 /* l2_cache_size */ + -1, /* l2_cache_size */ + -1 /* default_opt_level */ }; static const cpu_prefetch_tune exynosm1_prefetch_tune = @@ -540,7 +541,8 @@ static const cpu_prefetch_tune exynosm1_prefetch_tune = 0, /* num_slots */ -1, /* l1_cache_size */ 64, /* l1_cache_line_size */ - -1 /* l2_cache_size */ + -1, /* l2_cache_size */ + -1 /* default_opt_level */ }; static const cpu_prefetch_tune qdf24xx_prefetch_tune = @@ -548,7 +550,8 @@ static const cpu_prefetch_tune qdf24xx_prefetch_tune = 0, /* num_slots */ -1, /* l1_cache_size */ 64, /* l1_cache_line_size */ - -1 /* l2_cache_size */ + -1, /* l2_cache_size */ + -1 /* default_opt_level */ }; static const cpu_prefetch_tune thunderx2t99_prefetch_tune = @@ -556,7 +559,8 @@ static const cpu_prefetch_tune thunderx2t99_prefetch_tune = 0, /* num_slots */ -1, /* l1_cache_size */ 64, /* l1_cache_line_size */ - -1 /* l2_cache_size */ + -1, /* l2_cache_size */ + -1 /* default_opt_level */ }; static const struct tune_params generic_tunings = @@ -8806,6 +8810,15 @@ aarch64_override_options_internal (struct gcc_options *opts) opts->x_param_values, global_options_set.x_param_values); + /* Enable sw prefetching at specified optimization level for + CPUS that have prefetch. Lower optimization level threshold by 1 + when profiling is enabled. */ + if (opts->x_flag_prefetch_loop_arrays < 0 + && !opts->x_optimize_size + && aarch64_tune_params.prefetch->default_opt_level >= 0 + && opts->x_optimize >= aarch64_tune_params.prefetch->default_opt_level) + opts->x_flag_prefetch_loop_arrays = 1; + aarch64_override_options_after_change_1 (opts); } -- cgit v1.1 From 70c51b58911fe391e3c3bca6f73c274fab512a18 Mon Sep 17 00:00:00 2001 From: Maxim Kuvyrkov Date: Fri, 16 Jun 2017 09:31:00 +0000 Subject: Update prefetch tuning parameters for qdf24xx. * config/aarch64/aarch64.c (qdf24xx_prefetch_tune): Update prefetch settings, and enable prefetching by default at -O3. Change-Id: I2f0da54a8c262f6fbd0dcfde4584141bb09f1013 From-SVN: r249242 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64.c | 8 ++++---- 2 files changed, 9 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0ed2ac1..219dc12 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Maxim Kuvyrkov + * config/aarch64/aarch64.c (qdf24xx_prefetch_tune): Update + prefetch settings, and enable prefetching by default at -O3. + +2017-06-16 Maxim Kuvyrkov + * config/aarch64/aarch64.c (aarch64_override_options_internal): Set flag_prefetch_loop_arrays according to tuning data. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 324a0f1..04417dc 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -547,11 +547,11 @@ static const cpu_prefetch_tune exynosm1_prefetch_tune = static const cpu_prefetch_tune qdf24xx_prefetch_tune = { - 0, /* num_slots */ - -1, /* l1_cache_size */ + 4, /* num_slots */ + 32, /* l1_cache_size */ 64, /* l1_cache_line_size */ - -1, /* l2_cache_size */ - -1 /* default_opt_level */ + 1024, /* l2_cache_size */ + 3 /* default_opt_level */ }; static const cpu_prefetch_tune thunderx2t99_prefetch_tune = -- cgit v1.1 From 8d94f9324a2c79c6f93e5eea37776b2a27c3532c Mon Sep 17 00:00:00 2001 From: Janus Weil Date: Fri, 16 Jun 2017 12:15:42 +0200 Subject: re PR fortran/80983 ([F03] memory leak when calling procedure-pointer component with allocatable result) 2017-06-16 Janus Weil PR fortran/80983 * gfortran.dg/proc_ptr_comp_51.f90: Repair test case. From-SVN: r249243 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gfortran.dg/proc_ptr_comp_51.f90 | 1 + 2 files changed, 6 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2257edc..a0c2723 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-16 Janus Weil + + PR fortran/80983 + * gfortran.dg/proc_ptr_comp_51.f90: Repair test case. + 2017-06-16 Jakub Jelinek PR sanitizer/81094 diff --git a/gcc/testsuite/gfortran.dg/proc_ptr_comp_51.f90 b/gcc/testsuite/gfortran.dg/proc_ptr_comp_51.f90 index 530872b..cfe9818 100644 --- a/gcc/testsuite/gfortran.dg/proc_ptr_comp_51.f90 +++ b/gcc/testsuite/gfortran.dg/proc_ptr_comp_51.f90 @@ -1,4 +1,5 @@ ! { dg-do compile } +! { dg-options "-fdump-tree-original" } ! ! PR 80983: [F03] memory leak when calling procedure-pointer component with allocatable result ! -- cgit v1.1 From 7d72a77f93da14f52b2244d9bbd19dea52bcea26 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Fri, 16 Jun 2017 13:41:19 +0200 Subject: ipa-inline-transform.c (update_noncloned_frequencies): Update also counts. * ipa-inline-transform.c (update_noncloned_frequencies): Update also counts. (clone_inlined_nodes): Update. From-SVN: r249244 --- gcc/ChangeLog | 6 ++++++ gcc/ipa-inline-transform.c | 17 +++++++++++++---- 2 files changed, 19 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 219dc12..0fed0dc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-16 Jan Hubicka + + * ipa-inline-transform.c (update_noncloned_frequencies): Update also + counts. + (clone_inlined_nodes): Update. + 2017-06-16 Maxim Kuvyrkov * config/aarch64/aarch64.c (qdf24xx_prefetch_tune): Update diff --git a/gcc/ipa-inline-transform.c b/gcc/ipa-inline-transform.c index 9866a55..dc224f7 100644 --- a/gcc/ipa-inline-transform.c +++ b/gcc/ipa-inline-transform.c @@ -54,10 +54,12 @@ int nfunctions_inlined; /* Scale frequency of NODE edges by FREQ_SCALE. */ static void -update_noncloned_frequencies (struct cgraph_node *node, - int freq_scale) +update_noncloned_frequencies (struct cgraph_node *node, + int freq_scale, profile_count num, + profile_count den) { struct cgraph_edge *e; + bool scale = (num == profile_count::zero () || den > 0); /* We do not want to ignore high loop nest after freq drops to 0. */ if (!freq_scale) @@ -68,14 +70,20 @@ update_noncloned_frequencies (struct cgraph_node *node, if (e->frequency > CGRAPH_FREQ_MAX) e->frequency = CGRAPH_FREQ_MAX; if (!e->inline_failed) - update_noncloned_frequencies (e->callee, freq_scale); + update_noncloned_frequencies (e->callee, freq_scale, num, den); + if (scale) + e->count = e->count.apply_scale (num, den); } for (e = node->indirect_calls; e; e = e->next_callee) { e->frequency = e->frequency * (gcov_type) freq_scale / CGRAPH_FREQ_BASE; if (e->frequency > CGRAPH_FREQ_MAX) e->frequency = CGRAPH_FREQ_MAX; + if (scale) + e->count = e->count.apply_scale (num, den); } + if (scale) + node->count = node->count.apply_scale (num, den); } /* We removed or are going to remove the last call to NODE. @@ -212,7 +220,8 @@ clone_inlined_nodes (struct cgraph_edge *e, bool duplicate, } duplicate = false; e->callee->externally_visible = false; - update_noncloned_frequencies (e->callee, e->frequency); + update_noncloned_frequencies (e->callee, e->frequency, + e->count, e->callee->count); dump_callgraph_transformation (e->callee, inlining_into, "inlining to"); -- cgit v1.1 From 66846c079410498d0d836ebb112dad60f75c8edd Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Fri, 16 Jun 2017 11:47:00 +0000 Subject: tree-switch-conversion.c (emit_case_bit_tests): Adjust initializer to workaround ICE in host GCC 4.8. 2017-06-16 Richard Biener * tree-switch-conversion.c (emit_case_bit_tests): Adjust initializer to workaround ICE in host GCC 4.8. From-SVN: r249245 --- gcc/ChangeLog | 5 +++++ gcc/tree-switch-conversion.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0fed0dc..258f6cb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-16 Richard Biener + + * tree-switch-conversion.c (emit_case_bit_tests): Adjust + initializer to workaround ICE in host GCC 4.8. + 2017-06-16 Jan Hubicka * ipa-inline-transform.c (update_noncloned_frequencies): Update also diff --git a/gcc/tree-switch-conversion.c b/gcc/tree-switch-conversion.c index 72927bf..72e53af 100644 --- a/gcc/tree-switch-conversion.c +++ b/gcc/tree-switch-conversion.c @@ -268,7 +268,7 @@ static void emit_case_bit_tests (gswitch *swtch, tree index_expr, tree minval, tree range, tree maxval) { - struct case_bit_test test[MAX_CASE_BIT_TESTS] = { }; + struct case_bit_test test[MAX_CASE_BIT_TESTS] = { {} }; unsigned int i, j, k; unsigned int count; -- cgit v1.1 From 01f1c24e423755d237e6c13ff81da1356b153caa Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Fri, 16 Jun 2017 12:19:24 +0000 Subject: re PR tree-optimization/81090 ([graphite] ICE in loop_preheader_edge) 2017-06-16 Richard Biener PR tree-optimization/81090 * passes.def (pass_record_bounds): Remove. * tree-pass.h (make_pass_record_bounds): Likewise. * tree-ssa-loop.c (pass_data_record_bounds, pass_record_bounds, make_pass_record_bounds): Likewise. * tree-ssa-loop-ivcanon.c (canonicalize_induction_variables): Do not free niter estimates at the beginning but at the end. * tree-scalar-evolution.c (scev_finalize): Free niter estimates. * gcc.dg/graphite/pr81090.c: New testcase. From-SVN: r249249 --- gcc/ChangeLog | 11 ++++++++ gcc/passes.def | 1 - gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/gcc.dg/graphite/pr81090.c | 27 +++++++++++++++++++ gcc/tree-pass.h | 1 - gcc/tree-scalar-evolution.c | 1 + gcc/tree-ssa-loop-ivcanon.c | 2 +- gcc/tree-ssa-loop.c | 48 --------------------------------- 8 files changed, 45 insertions(+), 51 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/graphite/pr81090.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 258f6cb..b55b0ce 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,16 @@ 2017-06-16 Richard Biener + PR tree-optimization/81090 + * passes.def (pass_record_bounds): Remove. + * tree-pass.h (make_pass_record_bounds): Likewise. + * tree-ssa-loop.c (pass_data_record_bounds, pass_record_bounds, + make_pass_record_bounds): Likewise. + * tree-ssa-loop-ivcanon.c (canonicalize_induction_variables): Do + not free niter estimates at the beginning but at the end. + * tree-scalar-evolution.c (scev_finalize): Free niter estimates. + +2017-06-16 Richard Biener + * tree-switch-conversion.c (emit_case_bit_tests): Adjust initializer to workaround ICE in host GCC 4.8. diff --git a/gcc/passes.def b/gcc/passes.def index 25e9d97..c14f6b9 100644 --- a/gcc/passes.def +++ b/gcc/passes.def @@ -276,7 +276,6 @@ along with GCC; see the file COPYING3. If not see /* All unswitching, final value replacement and splitting can expose empty loops. Remove them now. */ NEXT_PASS (pass_cd_dce); - NEXT_PASS (pass_record_bounds); NEXT_PASS (pass_iv_canon); NEXT_PASS (pass_loop_distribution); NEXT_PASS (pass_copy_prop); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a0c2723..f6b56ad 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-16 Richard Biener + + PR tree-optimization/81090 + * gcc.dg/graphite/pr81090.c: New testcase. + 2017-06-16 Janus Weil PR fortran/80983 diff --git a/gcc/testsuite/gcc.dg/graphite/pr81090.c b/gcc/testsuite/gcc.dg/graphite/pr81090.c new file mode 100644 index 0000000..b5ebd43 --- /dev/null +++ b/gcc/testsuite/gcc.dg/graphite/pr81090.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -floop-nest-optimize" } */ + +int x3, za; +int hg[1]; + +void +yw (int dq) +{ + const int r7 = 2; + + while (dq < 1) + { + for (x3 = 0; x3 < r7; ++x3) + for (za = 0; za < r7; ++za) + hg[1] = 0; + ++dq; + } + + x3 = 0; + while (x3 < r7) + { + ++x3; + if (x3 == 0) + break; + } +} diff --git a/gcc/tree-pass.h b/gcc/tree-pass.h index 0f7d936..2863f76 100644 --- a/gcc/tree-pass.h +++ b/gcc/tree-pass.h @@ -373,7 +373,6 @@ extern gimple_opt_pass *make_pass_predcom (gcc::context *ctxt); extern gimple_opt_pass *make_pass_iv_canon (gcc::context *ctxt); extern gimple_opt_pass *make_pass_scev_cprop (gcc::context *ctxt); extern gimple_opt_pass *make_pass_empty_loop (gcc::context *ctxt); -extern gimple_opt_pass *make_pass_record_bounds (gcc::context *ctxt); extern gimple_opt_pass *make_pass_graphite (gcc::context *ctxt); extern gimple_opt_pass *make_pass_graphite_transforms (gcc::context *ctxt); extern gimple_opt_pass *make_pass_if_conversion (gcc::context *ctxt); diff --git a/gcc/tree-scalar-evolution.c b/gcc/tree-scalar-evolution.c index 95f65b0..8459793 100644 --- a/gcc/tree-scalar-evolution.c +++ b/gcc/tree-scalar-evolution.c @@ -3636,6 +3636,7 @@ scev_finalize (void) return; scalar_evolution_info->empty (); scalar_evolution_info = NULL; + free_numbers_of_iterations_estimates (cfun); } /* Returns true if the expression EXPR is considered to be too expensive diff --git a/gcc/tree-ssa-loop-ivcanon.c b/gcc/tree-ssa-loop-ivcanon.c index 91787af..f4ebe48 100644 --- a/gcc/tree-ssa-loop-ivcanon.c +++ b/gcc/tree-ssa-loop-ivcanon.c @@ -1212,7 +1212,6 @@ canonicalize_induction_variables (void) bool irred_invalidated = false; bitmap loop_closed_ssa_invalidated = BITMAP_ALLOC (NULL); - free_numbers_of_iterations_estimates (cfun); estimate_numbers_of_iterations (); FOR_EACH_LOOP (loop, LI_FROM_INNERMOST) @@ -1230,6 +1229,7 @@ canonicalize_induction_variables (void) /* Clean up the information about numbers of iterations, since brute force evaluation could reveal new information. */ + free_numbers_of_iterations_estimates (cfun); scev_reset (); if (!bitmap_empty_p (loop_closed_ssa_invalidated)) diff --git a/gcc/tree-ssa-loop.c b/gcc/tree-ssa-loop.c index 10c43f3..19a0f30 100644 --- a/gcc/tree-ssa-loop.c +++ b/gcc/tree-ssa-loop.c @@ -459,54 +459,6 @@ make_pass_scev_cprop (gcc::context *ctxt) return new pass_scev_cprop (ctxt); } -/* Record bounds on numbers of iterations of loops. */ - -namespace { - -const pass_data pass_data_record_bounds = -{ - GIMPLE_PASS, /* type */ - "*record_bounds", /* name */ - OPTGROUP_NONE, /* optinfo_flags */ - TV_TREE_LOOP_BOUNDS, /* tv_id */ - ( PROP_cfg | PROP_ssa ), /* properties_required */ - 0, /* properties_provided */ - 0, /* properties_destroyed */ - 0, /* todo_flags_start */ - 0, /* todo_flags_finish */ -}; - -class pass_record_bounds : public gimple_opt_pass -{ -public: - pass_record_bounds (gcc::context *ctxt) - : gimple_opt_pass (pass_data_record_bounds, ctxt) - {} - - /* opt_pass methods: */ - virtual unsigned int execute (function *); - -}; // class pass_record_bounds - -unsigned int -pass_record_bounds::execute (function *fun) -{ - if (number_of_loops (fun) <= 1) - return 0; - - estimate_numbers_of_iterations (); - scev_reset (); - return 0; -} - -} // anon namespace - -gimple_opt_pass * -make_pass_record_bounds (gcc::context *ctxt) -{ - return new pass_record_bounds (ctxt); -} - /* Induction variable optimizations. */ namespace { -- cgit v1.1 From ac9a1c7ec54f41e5d470593ce982bc55ab9dcb19 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 16 Jun 2017 14:16:20 +0000 Subject: Make rtti lazier Make rtti lazier * rtti.c (enum tinfo_kind): Add TK_DERIVED_TYPES, TK_VMI_CLASS_TYPES, TK_MAX. Delete TK_FIXED. (tinfo_names): New. (typeid_ok_p): Add quotes to error messages. Use get_tinfo_desc. (get_tinfo_decl): Use get_tinfo_desc. (get_pseudo_ti_init): Likewise. Adjust VMI construction. (create_pseudo_type_info): Delete. (get_pseudo_ti_index): Just determine the index. (get_tinfo_desc): New. Create all types lazily. (create_tinfo_types): Just allocate the descriptor array. (emit_support_tinfos): Use non-inserting type lookup. Set builtin location. From-SVN: r249258 --- gcc/cp/ChangeLog | 16 ++ gcc/cp/rtti.c | 469 ++++++++++++++++++++++++++++--------------------------- 2 files changed, 254 insertions(+), 231 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index ed307b6..7bf7ed1 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,19 @@ +2017-06-16 Nathan Sidwell + + Make rtti lazier + * rtti.c (enum tinfo_kind): Add TK_DERIVED_TYPES, + TK_VMI_CLASS_TYPES, TK_MAX. Delete TK_FIXED. + (tinfo_names): New. + (typeid_ok_p): Add quotes to error messages. Use get_tinfo_desc. + (get_tinfo_decl): Use get_tinfo_desc. + (get_pseudo_ti_init): Likewise. Adjust VMI construction. + (create_pseudo_type_info): Delete. + (get_pseudo_ti_index): Just determine the index. + (get_tinfo_desc): New. Create all types lazily. + (create_tinfo_types): Just allocate the descriptor array. + (emit_support_tinfos): Use non-inserting type lookup. Set builtin + location. + 2017-06-15 Martin Sebor PR c++/80560 diff --git a/gcc/cp/rtti.c b/gcc/cp/rtti.c index 89d1891..6d0316f 100644 --- a/gcc/cp/rtti.c +++ b/gcc/cp/rtti.c @@ -75,7 +75,8 @@ enum tinfo_kind { TK_TYPE_INFO_TYPE, /* abi::__type_info_pseudo */ TK_BASE_TYPE, /* abi::__base_class_type_info */ - TK_BUILTIN_TYPE, /* abi::__fundamental_type_info */ + TK_DERIVED_TYPES, /* Start of types derived from abi::__type_info */ + TK_BUILTIN_TYPE = TK_DERIVED_TYPES, /* abi::__fundamental_type_info */ TK_ARRAY_TYPE, /* abi::__array_type_info */ TK_FUNCTION_TYPE, /* abi::__function_type_info */ TK_ENUMERAL_TYPE, /* abi::__enum_type_info */ @@ -83,8 +84,26 @@ enum tinfo_kind TK_POINTER_MEMBER_TYPE, /* abi::__pointer_to_member_type_info */ TK_CLASS_TYPE, /* abi::__class_type_info */ TK_SI_CLASS_TYPE, /* abi::__si_class_type_info */ - TK_FIXED /* end of fixed descriptors. */ - /* ... abi::__vmi_type_info */ + TK_VMI_CLASS_TYPES, /* abi::__vmi_class_type_info */ + TK_MAX +}; + +/* Names of the tinfo types. Must be same order as TK enumeration + above. */ + +static const char *const tinfo_names[TK_MAX] = +{ + "__type_info", + "__base_class_type_info", + "__fundamental_type_info", + "__array_type_info", + "__function_type_info", + "__enum_type_info", + "__pointer_type_info", + "__pointer_to_member_type_info", + "__class_type_info", + "__si_class_type_info", + "__vmi_class_type_info" }; /* Helper macro to get maximum scalar-width of pointer or of the 'long'-type. @@ -115,9 +134,9 @@ static tree generic_initializer (tinfo_s *, tree); static tree ptr_initializer (tinfo_s *, tree); static tree ptm_initializer (tinfo_s *, tree); static tree class_initializer (tinfo_s *, tree, unsigned, ...); -static void create_pseudo_type_info (int, const char *, ...); static tree get_pseudo_ti_init (tree, unsigned); static unsigned get_pseudo_ti_index (tree); +static tinfo_s *get_tinfo_desc (unsigned); static void create_tinfo_types (void); static bool typeinfo_in_lib_p (tree); @@ -289,30 +308,27 @@ get_tinfo_decl_dynamic (tree exp, tsubst_flags_t complain) static bool typeid_ok_p (void) { - tree pseudo_type_info, type_info_type; - if (! flag_rtti) { - error ("cannot use typeid with -fno-rtti"); + error ("cannot use % with -fno-rtti"); return false; } if (!COMPLETE_TYPE_P (const_type_info_type_node)) { - error ("must #include before using typeid"); + error ("must %<#include %> before using %"); return false; } - pseudo_type_info = (*tinfo_descs)[TK_TYPE_INFO_TYPE].type; - type_info_type = TYPE_MAIN_VARIANT (const_type_info_type_node); + tree pseudo = TYPE_MAIN_VARIANT (get_tinfo_desc (TK_TYPE_INFO_TYPE)->type); + tree real = TYPE_MAIN_VARIANT (const_type_info_type_node); /* Make sure abi::__type_info_pseudo has the same alias set as std::type_info. */ - if (! TYPE_ALIAS_SET_KNOWN_P (pseudo_type_info)) - TYPE_ALIAS_SET (pseudo_type_info) = get_alias_set (type_info_type); + if (! TYPE_ALIAS_SET_KNOWN_P (pseudo)) + TYPE_ALIAS_SET (pseudo) = get_alias_set (real); else - gcc_assert (TYPE_ALIAS_SET (pseudo_type_info) - == get_alias_set (type_info_type)); + gcc_assert (TYPE_ALIAS_SET (pseudo) == get_alias_set (real)); return true; } @@ -428,8 +444,8 @@ get_tinfo_decl (tree type) if (!d) { int ix = get_pseudo_ti_index (type); - tinfo_s *ti = &(*tinfo_descs)[ix]; - + const tinfo_s *ti = get_tinfo_desc (ix); + d = build_lang_decl (VAR_DECL, name, ti->type); SET_DECL_ASSEMBLER_NAME (d, name); /* Remember the type it is for. */ @@ -1105,7 +1121,7 @@ typeinfo_in_lib_p (tree type) static tree get_pseudo_ti_init (tree type, unsigned tk_index) { - tinfo_s *ti = &(*tinfo_descs)[tk_index]; + tinfo_s *ti = get_tinfo_desc (tk_index); gcc_assert (at_eof); switch (tk_index) @@ -1140,22 +1156,18 @@ get_pseudo_ti_init (tree type, unsigned tk_index) int hint = ((CLASSTYPE_REPEATED_BASE_P (type) << 0) | (CLASSTYPE_DIAMOND_SHAPED_P (type) << 1)); tree binfo = TYPE_BINFO (type); - int nbases = BINFO_N_BASE_BINFOS (binfo); + unsigned nbases = BINFO_N_BASE_BINFOS (binfo); vec *base_accesses = BINFO_BASE_ACCESSES (binfo); tree offset_type = LONGPTR_T; - tree base_inits = NULL_TREE; - int ix; vec *init_vec = NULL; - constructor_elt *e; - gcc_assert (tk_index >= TK_FIXED); + gcc_assert (tk_index - TK_VMI_CLASS_TYPES + 1 == nbases); vec_safe_grow (init_vec, nbases); /* Generate the base information initializer. */ - for (ix = nbases; ix--;) + for (unsigned ix = nbases; ix--;) { tree base_binfo = BINFO_BASE_BINFO (binfo, ix); - tree base_init; int flags = 0; tree tinfo; tree offset; @@ -1185,12 +1197,12 @@ get_pseudo_ti_init (tree type, unsigned tk_index) vec_alloc (v, 2); CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, tinfo); CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, offset); - base_init = build_constructor (init_list_type_node, v); - e = &(*init_vec)[ix]; + tree base_init = build_constructor (init_list_type_node, v); + constructor_elt *e = &(*init_vec)[ix]; e->index = NULL_TREE; e->value = base_init; } - base_inits = build_constructor (init_list_type_node, init_vec); + tree base_inits = build_constructor (init_list_type_node, init_vec); /* get_tinfo_ptr might have reallocated the tinfo_descs vector. */ ti = &(*tinfo_descs)[tk_index]; @@ -1202,69 +1214,6 @@ get_pseudo_ti_init (tree type, unsigned tk_index) } } -/* Generate the RECORD_TYPE containing the data layout of a type_info - derivative as used by the runtime. This layout must be consistent with - that defined in the runtime support. Also generate the VAR_DECL for the - type's vtable. We explicitly manage the vtable member, and name it for - real type as used in the runtime. The RECORD type has a different name, - to avoid collisions. Return a TREE_LIST who's TINFO_PSEUDO_TYPE - is the generated type and TINFO_VTABLE_NAME is the name of the - vtable. We have to delay generating the VAR_DECL of the vtable - until the end of the translation, when we'll have seen the library - definition, if there was one. - - REAL_NAME is the runtime's name of the type. Trailing arguments are - additional FIELD_DECL's for the structure. The final argument must be - NULL. */ - -static void -create_pseudo_type_info (int tk, const char *real_name, ...) -{ - tinfo_s *ti; - tree pseudo_type; - char *pseudo_name; - tree fields; - tree field_decl; - va_list ap; - - va_start (ap, real_name); - - /* Generate the pseudo type name. */ - pseudo_name = (char *) alloca (strlen (real_name) + 30); - strcpy (pseudo_name, real_name); - strcat (pseudo_name, "_pseudo"); - if (tk >= TK_FIXED) - sprintf (pseudo_name + strlen (pseudo_name), "%d", tk - TK_FIXED); - - /* First field is the pseudo type_info base class. */ - fields = build_decl (input_location, - FIELD_DECL, NULL_TREE, - (*tinfo_descs)[TK_TYPE_INFO_TYPE].type); - - /* Now add the derived fields. */ - while ((field_decl = va_arg (ap, tree))) - { - DECL_CHAIN (field_decl) = fields; - fields = field_decl; - } - - /* Create the pseudo type. */ - pseudo_type = make_class_type (RECORD_TYPE); - finish_builtin_struct (pseudo_type, pseudo_name, fields, NULL_TREE); - CLASSTYPE_AS_BASE (pseudo_type) = pseudo_type; - - ti = &(*tinfo_descs)[tk]; - ti->type = cp_build_qualified_type (pseudo_type, TYPE_QUAL_CONST); - ti->name = get_identifier (real_name); - ti->vtable = NULL_TREE; - - /* Pretend this is public so determine_visibility doesn't give vtables - internal linkage. */ - TREE_PUBLIC (TYPE_MAIN_DECL (ti->type)) = 1; - - va_end (ap); -} - /* Return the index of a pseudo type info type node used to describe TYPE. TYPE must be a complete type (or cv void), except at the end of the translation unit. */ @@ -1299,23 +1248,16 @@ get_pseudo_ti_index (tree type) case UNION_TYPE: case RECORD_TYPE: if (TYPE_PTRMEMFUNC_P (type)) - { - ix = TK_POINTER_MEMBER_TYPE; - break; - } + ix = TK_POINTER_MEMBER_TYPE; else if (!COMPLETE_TYPE_P (type)) { if (!at_eof) cxx_incomplete_type_error (NULL_TREE, type); ix = TK_CLASS_TYPE; - break; } else if (!TYPE_BINFO (type) || !BINFO_N_BASE_BINFOS (TYPE_BINFO (type))) - { - ix = TK_CLASS_TYPE; - break; - } + ix = TK_CLASS_TYPE; else { tree binfo = TYPE_BINFO (type); @@ -1327,49 +1269,13 @@ get_pseudo_ti_index (tree type) && (*base_accesses)[0] == access_public_node && !BINFO_VIRTUAL_P (base_binfo) && integer_zerop (BINFO_OFFSET (base_binfo))) - { - /* single non-virtual public. */ - ix = TK_SI_CLASS_TYPE; - break; - } + /* single non-virtual public. */ + ix = TK_SI_CLASS_TYPE; else - { - tinfo_s *ti; - tree array_domain, base_array; - - ix = TK_FIXED + num_bases; - if (vec_safe_length (tinfo_descs) <= ix) - { - /* too short, extend. */ - unsigned len = vec_safe_length (tinfo_descs); - - vec_safe_grow (tinfo_descs, ix + 1); - while (tinfo_descs->iterate (len++, &ti)) - ti->type = ti->vtable = ti->name = NULL_TREE; - } - else if ((*tinfo_descs)[ix].type) - /* already created. */ - break; - - /* Create the array of __base_class_type_info entries. */ - array_domain = build_index_type (size_int (num_bases - 1)); - base_array = build_array_type ((*tinfo_descs)[TK_BASE_TYPE].type, - array_domain); - - push_abi_namespace (); - create_pseudo_type_info - (ix, "__vmi_class_type_info", - build_decl (input_location, - FIELD_DECL, NULL_TREE, integer_type_node), - build_decl (input_location, - FIELD_DECL, NULL_TREE, integer_type_node), - build_decl (input_location, - FIELD_DECL, NULL_TREE, base_array), - NULL); - pop_abi_namespace (); - break; - } + ix = TK_VMI_CLASS_TYPES + num_bases - 1; } + break; + default: ix = TK_BUILTIN_TYPE; break; @@ -1377,107 +1283,202 @@ get_pseudo_ti_index (tree type) return ix; } -/* Make sure the required builtin types exist for generating the type_info - variable definitions. */ +/* Return pointer to tinfo descriptor. Possibly creating the tinfo + descriptor in the first place. */ -static void -create_tinfo_types (void) +static tinfo_s * +get_tinfo_desc (unsigned ix) { - tinfo_s *ti; + unsigned len = tinfo_descs->length (); - gcc_assert (!tinfo_descs); + if (len <= ix) + { + /* too short, extend. */ + len = ix + 1 - len; + vec_safe_reserve (tinfo_descs, len); + tinfo_s elt; + elt.type = elt.vtable = elt.name = NULL_TREE; + while (len--) + tinfo_descs->quick_push (elt); + } - vec_safe_grow (tinfo_descs, TK_FIXED); + tinfo_s *res = &(*tinfo_descs)[ix]; - push_abi_namespace (); + if (res->type) + return res; - /* Create the internal type_info structure. This is used as a base for - the other structures. */ - { - tree field, fields; - - field = build_decl (BUILTINS_LOCATION, - FIELD_DECL, NULL_TREE, const_ptr_type_node); - fields = field; - - field = build_decl (BUILTINS_LOCATION, - FIELD_DECL, NULL_TREE, const_string_type_node); - DECL_CHAIN (field) = fields; - fields = field; - - ti = &(*tinfo_descs)[TK_TYPE_INFO_TYPE]; - ti->type = make_class_type (RECORD_TYPE); - ti->vtable = NULL_TREE; - ti->name = NULL_TREE; - finish_builtin_struct (ti->type, "__type_info_pseudo", - fields, NULL_TREE); - } + /* Ok, we have to create it. This layout must be consistent with + that defined in the runtime support. We explicitly manage the + vtable member, and name it for real type as used in the runtime. + The RECORD type has a different name, to avoid collisions. We + have to delay generating the VAR_DECL of the vtable until the end + of the translation, when we'll have seen the library definition, + if there was one. */ - /* Fundamental type_info */ - create_pseudo_type_info (TK_BUILTIN_TYPE, "__fundamental_type_info", NULL); + /* Fields to add, chained in reverse order. */ + tree fields = NULL_TREE; - /* Array, function and enum type_info. No additional fields. */ - create_pseudo_type_info (TK_ARRAY_TYPE, "__array_type_info", NULL); - create_pseudo_type_info (TK_FUNCTION_TYPE, "__function_type_info", NULL); - create_pseudo_type_info (TK_ENUMERAL_TYPE, "__enum_type_info", NULL); + if (ix >= TK_DERIVED_TYPES) + { + /* First field is the pseudo type_info base class. */ + tree fld_base = build_decl (BUILTINS_LOCATION, FIELD_DECL, NULL_TREE, + get_tinfo_desc (TK_TYPE_INFO_TYPE)->type); - /* Class type_info. No additional fields. */ - create_pseudo_type_info (TK_CLASS_TYPE, "__class_type_info", NULL); + DECL_CHAIN (fld_base) = fields; + fields = fld_base; + } - /* Single public non-virtual base class. Add pointer to base class. - This is really a descendant of __class_type_info. */ - create_pseudo_type_info (TK_SI_CLASS_TYPE, "__si_class_type_info", - build_decl (BUILTINS_LOCATION, - FIELD_DECL, NULL_TREE, type_info_ptr_type), - NULL); + switch (ix) + { + case TK_TYPE_INFO_TYPE: + { + tree fld_ptr = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, const_ptr_type_node); + fields = fld_ptr; + + tree fld_str = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, const_string_type_node); + DECL_CHAIN (fld_str) = fields; + fields = fld_str; + break; + } - /* Base class internal helper. Pointer to base type, offset to base, - flags. */ - { - tree field, fields; + case TK_BASE_TYPE: + { + /* Base class internal helper. Pointer to base type, offset to + base, flags. */ + tree fld_ptr = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, type_info_ptr_type); + DECL_CHAIN (fld_ptr) = fields; + fields = fld_ptr; + + tree fld_flag = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, LONGPTR_T); + DECL_CHAIN (fld_flag) = fields; + fields = fld_flag; + break; + } - field = build_decl (BUILTINS_LOCATION, - FIELD_DECL, NULL_TREE, type_info_ptr_type); - fields = field; + case TK_BUILTIN_TYPE: + /* Fundamental type_info */ + break; - field = build_decl (BUILTINS_LOCATION, - FIELD_DECL, NULL_TREE, LONGPTR_T); - DECL_CHAIN (field) = fields; - fields = field; + case TK_ARRAY_TYPE: + break; - ti = &(*tinfo_descs)[TK_BASE_TYPE]; + case TK_FUNCTION_TYPE: + break; - ti->type = make_class_type (RECORD_TYPE); - ti->vtable = NULL_TREE; - ti->name = NULL_TREE; - finish_builtin_struct (ti->type, "__base_class_type_info_pseudo", - fields, NULL_TREE); - } + case TK_ENUMERAL_TYPE: + break; + + case TK_POINTER_TYPE: + case TK_POINTER_MEMBER_TYPE: + { + /* Pointer type_info. Adds two fields, qualification mask and + pointer to the pointed to type. This is really a + descendant of __pbase_type_info. */ + tree fld_mask = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, integer_type_node); + DECL_CHAIN (fld_mask) = fields; + fields = fld_mask; + + tree fld_ptr = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, type_info_ptr_type); + DECL_CHAIN (fld_ptr) = fields; + fields = fld_ptr; + + if (ix == TK_POINTER_MEMBER_TYPE) + { + /* Add a pointer to the class too. */ + tree fld_cls = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, type_info_ptr_type); + DECL_CHAIN (fld_cls) = fields; + fields = fld_cls; + } + break; + } + + case TK_CLASS_TYPE: + /* Class type_info. No additional fields. */ + break; + + case TK_SI_CLASS_TYPE: + { + /* Single public non-virtual base class. Add pointer to base + class. This is really a descendant of + __class_type_info. */ + tree fld_ptr = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, type_info_ptr_type); + DECL_CHAIN (fld_ptr) = fields; + fields = fld_ptr; + break; + } + + default: /* Multiple inheritance. */ + { + unsigned num_bases = ix - TK_VMI_CLASS_TYPES + 1; + + tree fld_flg = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, integer_type_node); + DECL_CHAIN (fld_flg) = fields; + fields = fld_flg; + + tree fld_cnt = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, integer_type_node); + DECL_CHAIN (fld_cnt) = fields; + fields = fld_cnt; + + /* Create the array of __base_class_type_info entries. */ + tree domain = build_index_type (size_int (num_bases - 1)); + tree array = build_array_type (get_tinfo_desc (TK_BASE_TYPE)->type, + domain); + tree fld_ary = build_decl (BUILTINS_LOCATION, FIELD_DECL, + NULL_TREE, array); + DECL_CHAIN (fld_ary) = fields; + fields = fld_ary; + break; + } + } + + push_abi_namespace (); + + /* Generate the pseudo type name. */ + const char *real_name = tinfo_names[ix < TK_VMI_CLASS_TYPES + ? ix : unsigned (TK_VMI_CLASS_TYPES)]; + size_t name_len = strlen (real_name); + char *pseudo_name = (char *) alloca (name_len + 30); + memcpy (pseudo_name, real_name, name_len); + /* Those >= TK_VMI_CLASS_TYPES need a discriminator, may as well + apply it to all. See get_peudo_tinfo_index where we make use of + this. */ + sprintf (pseudo_name + name_len, "_pseudo_%d", ix); - /* Pointer type_info. Adds two fields, qualification mask - and pointer to the pointed to type. This is really a descendant of - __pbase_type_info. */ - create_pseudo_type_info (TK_POINTER_TYPE, "__pointer_type_info", - build_decl (BUILTINS_LOCATION, - FIELD_DECL, NULL_TREE, integer_type_node), - build_decl (BUILTINS_LOCATION, - FIELD_DECL, NULL_TREE, type_info_ptr_type), - NULL); - - /* Pointer to member data type_info. Add qualifications flags, - pointer to the member's type info and pointer to the class. - This is really a descendant of __pbase_type_info. */ - create_pseudo_type_info (TK_POINTER_MEMBER_TYPE, - "__pointer_to_member_type_info", - build_decl (BUILTINS_LOCATION, - FIELD_DECL, NULL_TREE, integer_type_node), - build_decl (BUILTINS_LOCATION, - FIELD_DECL, NULL_TREE, type_info_ptr_type), - build_decl (BUILTINS_LOCATION, - FIELD_DECL, NULL_TREE, type_info_ptr_type), - NULL); + /* Create the pseudo type. */ + tree pseudo_type = make_class_type (RECORD_TYPE); + /* Pass the fields chained in reverse. */ + finish_builtin_struct (pseudo_type, pseudo_name, fields, NULL_TREE); + CLASSTYPE_AS_BASE (pseudo_type) = pseudo_type; + + res->type = cp_build_qualified_type (pseudo_type, TYPE_QUAL_CONST); + res->name = get_identifier (real_name); + + /* Pretend this is public so determine_visibility doesn't give vtables + internal linkage. */ + TREE_PUBLIC (TYPE_MAIN_DECL (res->type)) = 1; pop_abi_namespace (); + return res; +} + +/* We lazily create the type info types. */ + +static void +create_tinfo_types (void) +{ + gcc_assert (!tinfo_descs); + + vec_alloc (tinfo_descs, TK_MAX + 20); } /* Helper for emit_support_tinfos. Emits the type_info descriptor of @@ -1545,18 +1546,23 @@ emit_support_tinfos (void) 0 }; int ix; - tree bltn_type, dtor; - push_abi_namespace (); - bltn_type = xref_tag (class_type, - get_identifier ("__fundamental_type_info"), - /*tag_scope=*/ts_current, false); - pop_abi_namespace (); + /* Look for a defined class. */ + tree bltn_type = lookup_qualified_name + (abi_node, get_identifier ("__fundamental_type_info"), true, false, false); + if (TREE_CODE (bltn_type) != TYPE_DECL) + return; + + bltn_type = TREE_TYPE (bltn_type); if (!COMPLETE_TYPE_P (bltn_type)) return; - dtor = CLASSTYPE_DESTRUCTORS (bltn_type); + tree dtor = CLASSTYPE_DESTRUCTORS (bltn_type); if (!dtor || DECL_EXTERNAL (dtor)) return; + + /* All these are really builtins. So set the location. */ + location_t saved_loc = input_location; + input_location = BUILTINS_LOCATION; doing_runtime = 1; for (ix = 0; fundamentals[ix]; ix++) emit_support_tinfo_1 (*fundamentals[ix]); @@ -1568,6 +1574,7 @@ emit_support_tinfos (void) } for (tree t = registered_builtin_types; t; t = TREE_CHAIN (t)) emit_support_tinfo_1 (TREE_VALUE (t)); + input_location = saved_loc; } /* Finish a type info decl. DECL_PTR is a pointer to an unemitted @@ -1606,7 +1613,7 @@ emit_tinfo_decl (tree decl) TREE_PUBLIC (decl) = 0; DECL_EXTERNAL (decl) = 0; DECL_INTERFACE_KNOWN (decl) = 1; - } + }u import_export_decl (decl); if (DECL_NOT_REALLY_EXTERN (decl) && decl_needed_p (decl)) -- cgit v1.1 From 8c1ca7ee3a35bf00201c6a82ccd5b663575328a7 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 16 Jun 2017 14:33:28 +0000 Subject: Fix keyboard flub. From-SVN: r249262 --- gcc/cp/rtti.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/cp/rtti.c b/gcc/cp/rtti.c index 6d0316f..ff72ce5 100644 --- a/gcc/cp/rtti.c +++ b/gcc/cp/rtti.c @@ -1613,7 +1613,7 @@ emit_tinfo_decl (tree decl) TREE_PUBLIC (decl) = 0; DECL_EXTERNAL (decl) = 0; DECL_INTERFACE_KNOWN (decl) = 1; - }u + } import_export_decl (decl); if (DECL_NOT_REALLY_EXTERN (decl) && decl_needed_p (decl)) -- cgit v1.1 From 6a2dfd9a66a678b26c762d0fc614fea267ea706b Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 16 Jun 2017 14:33:45 +0000 Subject: Make keyed_classes a vector. * cp-tree.h (CPTI_KEYED_CLASSES, keyed_classes): Delete. (keyed_classes): Declare as vector. * decl.c (keyed_classes): Define. (cxx_init_decl_processing): Allocate it. (record_key_method_defined): Use vec_safe_push. * class.c (finish_struct_1): Likewise. * pt.c (instantiate_class_template_1): Likewise. * decl2.c (c_parse_final_cleanups): Reverse iterate keyed_classes. From-SVN: r249263 --- gcc/cp/class.c | 4 ++-- gcc/cp/cp-tree.h | 11 ++++------- gcc/cp/decl.c | 8 +++++++- gcc/cp/decl2.c | 37 +++++++++---------------------------- gcc/cp/pt.c | 4 ++-- 5 files changed, 24 insertions(+), 40 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/class.c b/gcc/cp/class.c index dd1051e..ebb46fb 100644 --- a/gcc/cp/class.c +++ b/gcc/cp/class.c @@ -7189,8 +7189,8 @@ finish_struct_1 (tree t) in every translation unit where the class definition appears. If we're devirtualizing, we can look into the vtable even if we aren't emitting it. */ - if (CLASSTYPE_KEY_METHOD (t) == NULL_TREE) - keyed_classes = tree_cons (NULL_TREE, t, keyed_classes); + if (!CLASSTYPE_KEY_METHOD (t)) + vec_safe_push (keyed_classes, t); } /* Layout the class itself. */ diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 5dd6023..1125073 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -169,8 +169,6 @@ enum cp_tree_index CPTI_DSO_HANDLE, CPTI_DCAST, - CPTI_KEYED_CLASSES, - CPTI_NULLPTR, CPTI_NULLPTR_TYPE, @@ -290,11 +288,6 @@ extern GTY(()) tree cp_global_trees[CPTI_MAX]; destructors. */ #define vtt_parm_type cp_global_trees[CPTI_VTT_PARM_TYPE] -/* A TREE_LIST of the dynamic classes whose vtables may have to be - emitted in this translation unit. */ - -#define keyed_classes cp_global_trees[CPTI_KEYED_CLASSES] - /* A node which matches any template argument. */ #define any_targ_node cp_global_trees[CPTI_ANY_TARG] @@ -5107,6 +5100,10 @@ extern GTY(()) vec *local_classes; /* An array of static vars & fns. */ extern GTY(()) vec *static_decls; +/* An array of vtable-needing types that have no key function, or have + an emitted key function. */ +extern GTY(()) vec *keyed_classes; + /* Here's where we control how name mangling takes place. */ diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index 3711476..04418a1 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -160,6 +160,9 @@ tree integer_two_node; /* vector of static decls. */ vec *static_decls; +/* vector of keyed classes. */ +vec *keyed_classes; + /* Used only for jumps to as-yet undefined labels, since jumps to defined labels can have their validity checked immediately. */ @@ -4064,6 +4067,9 @@ cxx_init_decl_processing (void) /* Guess at the initial static decls size. */ vec_alloc (static_decls, 500); + /* ... and keyed classes. */ + vec_alloc (keyed_classes, 100); + record_builtin_type (RID_BOOL, "bool", boolean_type_node); truthvalue_type_node = boolean_type_node; truthvalue_false_node = boolean_false_node; @@ -15438,7 +15444,7 @@ record_key_method_defined (tree fndecl) { tree fnclass = DECL_CONTEXT (fndecl); if (fndecl == CLASSTYPE_KEY_METHOD (fnclass)) - keyed_classes = tree_cons (NULL_TREE, fnclass, keyed_classes); + vec_safe_push (keyed_classes, fnclass); } } diff --git a/gcc/cp/decl2.c b/gcc/cp/decl2.c index ab32b71..f9d5887 100644 --- a/gcc/cp/decl2.c +++ b/gcc/cp/decl2.c @@ -4511,37 +4511,18 @@ c_parse_final_cleanups (void) instantiate_pending_templates (retries); ggc_collect (); - /* Write out virtual tables as required. Note that writing out - the virtual table for a template class may cause the + /* Write out virtual tables as required. Writing out the + virtual table for a template class may cause the instantiation of members of that class. If we write out vtables then we remove the class from our list so we don't have to look at it again. */ - - while (keyed_classes != NULL_TREE - && maybe_emit_vtables (TREE_VALUE (keyed_classes))) - { - reconsider = true; - keyed_classes = TREE_CHAIN (keyed_classes); - } - - t = keyed_classes; - if (t != NULL_TREE) - { - tree next = TREE_CHAIN (t); - - while (next) - { - if (maybe_emit_vtables (TREE_VALUE (next))) - { - reconsider = true; - TREE_CHAIN (t) = TREE_CHAIN (next); - } - else - t = next; - - next = TREE_CHAIN (t); - } - } + for (i = keyed_classes->length (); + keyed_classes->iterate (--i, &t);) + if (maybe_emit_vtables (t)) + { + reconsider = true; + keyed_classes->unordered_remove (i); + } /* Write out needed type info variables. We have to be careful looping through unemitted decls, because emit_tinfo_decl may diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 8a61b74..91b98d4 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -10864,9 +10864,9 @@ instantiate_class_template_1 (tree type) /* The vtable for a template class can be emitted in any translation unit in which the class is instantiated. When there is no key method, however, finish_struct_1 will already have added TYPE to - the keyed_classes list. */ + the keyed_classes. */ if (TYPE_CONTAINS_VPTR_P (type) && CLASSTYPE_KEY_METHOD (type)) - keyed_classes = tree_cons (NULL_TREE, type, keyed_classes); + vec_safe_push (keyed_classes, type); return type; } -- cgit v1.1 From 0d1dc5862f978beb28c76b91b137ccc23f747498 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 16 Jun 2017 14:43:20 +0000 Subject: Don't defer noexcept_deferred_spec. * cp-tree.h (unevaluated_noexcept_spec): Don't declare. * decl.c (cxx_init_decl_processing): Initialize noexcept_deferred_spec. * except.c (unevaluated_noexcept_spec): Delete. * class.c (deduce_noexcept_on_destructor): Use noexcept_deferred_spec directly. * method.c (implicitly_declare_fn): Likewise. From-SVN: r249264 --- gcc/cp/ChangeLog | 19 +++++++++++++++++++ gcc/cp/class.c | 6 ++---- gcc/cp/cp-tree.h | 1 - gcc/cp/decl.c | 2 ++ gcc/cp/except.c | 12 ------------ gcc/cp/method.c | 2 +- 6 files changed, 24 insertions(+), 18 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 7bf7ed1..ff832f8 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,24 @@ 2017-06-16 Nathan Sidwell + Don't defer noexcept_deferred_spec. + * cp-tree.h (unevaluated_noexcept_spec): Don't declare. + * decl.c (cxx_init_decl_processing): Initialize + noexcept_deferred_spec. + * except.c (unevaluated_noexcept_spec): Delete. + * class.c (deduce_noexcept_on_destructor): Use + noexcept_deferred_spec directly. + * method.c (implicitly_declare_fn): Likewise. + + Make keyed_classes a vector. + * cp-tree.h (CPTI_KEYED_CLASSES, keyed_classes): Delete. + (keyed_classes): Declare as vector. + * decl.c (keyed_classes): Define. + (cxx_init_decl_processing): Allocate it. + (record_key_method_defined): Use vec_safe_push. + * class.c (finish_struct_1): Likewise. + * pt.c (instantiate_class_template_1): Likewise. + * decl2.c (c_parse_final_cleanups): Reverse iterate keyed_classes. + Make rtti lazier * rtti.c (enum tinfo_kind): Add TK_DERIVED_TYPES, TK_VMI_CLASS_TYPES, TK_MAX. Delete TK_FIXED. diff --git a/gcc/cp/class.c b/gcc/cp/class.c index ebb46fb..054dd3e 100644 --- a/gcc/cp/class.c +++ b/gcc/cp/class.c @@ -5025,10 +5025,8 @@ void deduce_noexcept_on_destructor (tree dtor) { if (!TYPE_RAISES_EXCEPTIONS (TREE_TYPE (dtor))) - { - tree eh_spec = unevaluated_noexcept_spec (); - TREE_TYPE (dtor) = build_exception_variant (TREE_TYPE (dtor), eh_spec); - } + TREE_TYPE (dtor) = build_exception_variant (TREE_TYPE (dtor), + noexcept_deferred_spec); } /* For each destructor in T, deduce noexcept: diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 1125073..c56e59c 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -6317,7 +6317,6 @@ extern tree forward_parm (tree); extern bool is_trivially_xible (enum tree_code, tree, tree); extern bool is_xible (enum tree_code, tree, tree); extern tree get_defaulted_eh_spec (tree); -extern tree unevaluated_noexcept_spec (void); extern void after_nsdmi_defaulted_late_checks (tree); extern bool maybe_explain_implicit_delete (tree); extern void explain_implicit_non_constexpr (tree); diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index 04418a1..b6e8547 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -4078,6 +4078,8 @@ cxx_init_decl_processing (void) empty_except_spec = build_tree_list (NULL_TREE, NULL_TREE); noexcept_true_spec = build_tree_list (boolean_true_node, NULL_TREE); noexcept_false_spec = build_tree_list (boolean_false_node, NULL_TREE); + noexcept_deferred_spec = build_tree_list (make_node (DEFERRED_NOEXCEPT), + NULL_TREE); #if 0 record_builtin_type (RID_MAX, NULL, string_type_node); diff --git a/gcc/cp/except.c b/gcc/cp/except.c index ab7ab5d..9e41ec4 100644 --- a/gcc/cp/except.c +++ b/gcc/cp/except.c @@ -1197,18 +1197,6 @@ build_noexcept_spec (tree expr, int complain) } } -/* Returns a noexcept-specifier to be evaluated later, for an - implicitly-declared or explicitly defaulted special member function. */ - -tree -unevaluated_noexcept_spec (void) -{ - if (!noexcept_deferred_spec) - noexcept_deferred_spec - = build_noexcept_spec (make_node (DEFERRED_NOEXCEPT), tf_none); - return noexcept_deferred_spec; -} - /* Returns a TRY_CATCH_EXPR that will put TRY_LIST and CATCH_LIST in the TRY and CATCH locations. CATCH_LIST must be a STATEMENT_LIST */ diff --git a/gcc/cp/method.c b/gcc/cp/method.c index aa607d5..98d36da 100644 --- a/gcc/cp/method.c +++ b/gcc/cp/method.c @@ -2023,7 +2023,7 @@ implicitly_declare_fn (special_function_kind kind, tree type, } else if (cxx_dialect >= cxx11) { - raises = unevaluated_noexcept_spec (); + raises = noexcept_deferred_spec; synthesized_method_walk (type, kind, const_p, NULL, &trivial_p, &deleted_p, &constexpr_p, false, inherited_ctor, inherited_parms); -- cgit v1.1 From ba27a39d379b3ac69bd81944b65a99a0f02f240d Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 16 Jun 2017 14:49:35 +0000 Subject: class.c (resort_type_method_vec): Avoid potential unsigned overflow. * class.c (resort_type_method_vec): Avoid potential unsigned overflow. From-SVN: r249265 --- gcc/cp/ChangeLog | 3 +++ gcc/cp/class.c | 34 +++++++++++++++++----------------- 2 files changed, 20 insertions(+), 17 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index ff832f8..2d7ee17 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,8 @@ 2017-06-16 Nathan Sidwell + * class.c (resort_type_method_vec): Avoid potential unsigned + overflow. + Don't defer noexcept_deferred_spec. * cp-tree.h (unevaluated_noexcept_spec): Don't declare. * decl.c (cxx_init_decl_processing): Initialize diff --git a/gcc/cp/class.c b/gcc/cp/class.c index 054dd3e..1243f33 100644 --- a/gcc/cp/class.c +++ b/gcc/cp/class.c @@ -2328,25 +2328,25 @@ resort_type_method_vec (void* obj, gt_pointer_operator new_value, void* cookie) { - vec *method_vec = (vec *) obj; - int len = vec_safe_length (method_vec); - size_t slot; - tree fn; + if (vec *method_vec = (vec *) obj) + { + int len = method_vec->length (); + int slot; - /* The type conversion ops have to live at the front of the vec, so we - can't sort them. */ - for (slot = CLASSTYPE_FIRST_CONVERSION_SLOT; - vec_safe_iterate (method_vec, slot, &fn); - ++slot) - if (!DECL_CONV_FN_P (OVL_FIRST (fn))) - break; + /* The type conversion ops have to live at the front of the vec, so we + can't sort them. */ + for (slot = CLASSTYPE_FIRST_CONVERSION_SLOT; + slot < len; slot++) + if (!DECL_CONV_FN_P (OVL_FIRST ((*method_vec)[slot]))) + break; - if (len - slot > 1) - { - resort_data.new_value = new_value; - resort_data.cookie = cookie; - qsort (method_vec->address () + slot, len - slot, sizeof (tree), - resort_method_name_cmp); + if (len > slot + 1) + { + resort_data.new_value = new_value; + resort_data.cookie = cookie; + qsort (method_vec->address () + slot, len - slot, sizeof (tree), + resort_method_name_cmp); + } } } -- cgit v1.1 From d7b11178c4579f9c109c77609ef60dd0d6448598 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 16 Jun 2017 14:54:39 +0000 Subject: Symbol tables are insert only. * cp-tree.h (default_hash_traits ): Don't derive from pointer_hash. Make undeletable. From-SVN: r249266 --- gcc/cp/ChangeLog | 4 ++++ gcc/cp/cp-tree.h | 8 ++++++-- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 2d7ee17..7f9ddb0 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,9 @@ 2017-06-16 Nathan Sidwell + Symbol tables are insert only. + * cp-tree.h (default_hash_traits ): Don't + derive from pointer_hash. Make undeletable. + * class.c (resort_type_method_vec): Avoid potential unsigned overflow. diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index c56e59c..6c236ae 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -550,7 +550,7 @@ identifier_p (tree t) template <> struct default_hash_traits - : pointer_hash , ggc_remove + : pointer_hash { /* Use a regular tree as the type, to make using the hash table simpler. We'll get dynamic type checking with the hash function @@ -558,10 +558,14 @@ struct default_hash_traits GTY((skip)) typedef tree value_type; GTY((skip)) typedef tree compare_type; - static hashval_t hash (const value_type &id) + static hashval_t hash (const value_type id) { return IDENTIFIER_HASH_VALUE (id); } + + /* Nothing is deletable. Everything is insertable. */ + static bool is_deleted (value_type) { return false; } + static void remove (value_type) { gcc_unreachable (); } }; /* In an IDENTIFIER_NODE, nonzero if this identifier is actually a -- cgit v1.1 From e249fcad3aea469b27d92ba9ef435ee79fd932d4 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 16 Jun 2017 15:42:33 +0000 Subject: cp-tree.h (build_this_parm, [...]): Add FN parm. gcc/cp/ * cp-tree.h (build_this_parm, cp_build_parm_decl) build_artificial_parm): Add FN parm. * decl.c (start_cleanup_fn): Adjust. (build_this_parm): Add FN parm, pass it through. (grokfndecl): Adjust parm building. * decl2.c (cp_build_parm_decl): Add FN parm, set context. (build_artificial_parm): Add FN parm, pass through. (maybe_retrofit_in_chrg): Adjust parm building. (start_static_storage_duration_function): Likwise. * lambda.c (maybe_aadd_lambda_conv_op): Likewise. * method.c (implicitly_declare_fn): Likewise. * parser.c (inject_this_parameter): Likewise. libcc1/ * libcp1plugin.cc (plugin_build_decl): Adjust parm building. (--This line, and those below, will be ignored-- M gcc/cp/parser.c M gcc/cp/ChangeLog M gcc/cp/decl.c M gcc/cp/lambda.c M gcc/cp/cp-tree.h M gcc/cp/method.c M gcc/cp/decl2.c M libcc1/libcp1plugin.cc M libcc1/ChangeLog From-SVN: r249268 --- gcc/cp/ChangeLog | 13 +++++++++++++ gcc/cp/cp-tree.h | 6 +++--- gcc/cp/decl.c | 19 ++++++++----------- gcc/cp/decl2.c | 22 +++++++++++----------- gcc/cp/lambda.c | 3 ++- gcc/cp/method.c | 7 +++---- gcc/cp/parser.c | 2 +- 7 files changed, 41 insertions(+), 31 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 7f9ddb0..11f2d03 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,18 @@ 2017-06-16 Nathan Sidwell + * cp-tree.h (build_this_parm, cp_build_parm_decl, + build_artificial_parm): Add FN parm. + * decl.c (start_cleanup_fn): Adjust. + (build_this_parm): Add FN parm, pass it through. + (grokfndecl): Adjust parm building. + * decl2.c (cp_build_parm_decl): Add FN parm, set context. + (build_artificial_parm): Add FN parm, pass through. + (maybe_retrofit_in_chrg): Adjust parm building. + (start_static_storage_duration_function): Likwise. + * lambda.c (maybe_aadd_lambda_conv_op): Likewise. + * method.c (implicitly_declare_fn): Likewise. + * parser.c (inject_this_parameter): Likewise. + Symbol tables are insert only. * cp-tree.h (default_hash_traits ): Don't derive from pointer_hash. Make undeletable. diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 6c236ae..e33bda6 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -6078,7 +6078,7 @@ extern int cp_complete_array_type_or_error (tree *, tree, bool, tsubst_flags_t); extern tree build_ptrmemfunc_type (tree); extern tree build_ptrmem_type (tree, tree); /* the grokdeclarator prototype is in decl.h */ -extern tree build_this_parm (tree, cp_cv_quals); +extern tree build_this_parm (tree, tree, cp_cv_quals); extern tree grokparms (tree, tree *); extern int copy_fn_p (const_tree); extern bool move_fn_p (const_tree); @@ -6179,7 +6179,7 @@ extern void check_default_args (tree); extern bool mark_used (tree); extern bool mark_used (tree, tsubst_flags_t); extern void finish_static_data_member_decl (tree, tree, bool, tree, int); -extern tree cp_build_parm_decl (tree, tree); +extern tree cp_build_parm_decl (tree, tree, tree); extern tree get_guard (tree); extern tree get_guard_cond (tree, bool); extern tree set_guard (tree); @@ -6188,7 +6188,7 @@ extern void mark_needed (tree); extern bool decl_needed_p (tree); extern void note_vague_linkage_fn (tree); extern void note_variable_template_instantiation (tree); -extern tree build_artificial_parm (tree, tree); +extern tree build_artificial_parm (tree, tree, tree); extern bool possibly_inlined_p (tree); extern int parm_index (tree); extern tree vtv_start_verification_constructor_init_function (void); diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index b6e8547..16cd2a5 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -7823,10 +7823,7 @@ start_cleanup_fn (void) /* Build the parameter. */ if (use_cxa_atexit) { - tree parmdecl; - - parmdecl = cp_build_parm_decl (NULL_TREE, ptr_type_node); - DECL_CONTEXT (parmdecl) = fndecl; + tree parmdecl = cp_build_parm_decl (fndecl, NULL_TREE, ptr_type_node); TREE_USED (parmdecl) = 1; DECL_READ_P (parmdecl) = 1; DECL_ARGUMENTS (fndecl) = parmdecl; @@ -8367,12 +8364,12 @@ check_class_member_definition_namespace (tree decl) decl, DECL_CONTEXT (decl)); } -/* Build a PARM_DECL for the "this" parameter. TYPE is the +/* Build a PARM_DECL for the "this" parameter of FN. TYPE is the METHOD_TYPE for a non-static member function; QUALS are the cv-qualifiers that apply to the function. */ tree -build_this_parm (tree type, cp_cv_quals quals) +build_this_parm (tree fn, tree type, cp_cv_quals quals) { tree this_type; tree qual_type; @@ -8391,7 +8388,7 @@ build_this_parm (tree type, cp_cv_quals quals) assigned to. */ this_quals = (quals & TYPE_QUAL_RESTRICT) | TYPE_QUAL_CONST; qual_type = cp_build_qualified_type (this_type, this_quals); - parm = build_artificial_parm (this_identifier, qual_type); + parm = build_artificial_parm (fn, this_identifier, qual_type); cp_apply_type_quals_to_decl (this_quals, parm); return parm; } @@ -8525,8 +8522,7 @@ grokfndecl (tree ctype, if (TREE_CODE (type) == METHOD_TYPE) { - tree parm; - parm = build_this_parm (type, quals); + tree parm = build_this_parm (decl, type, quals); DECL_CHAIN (parm) = parms; parms = parm; @@ -11625,7 +11621,8 @@ grokdeclarator (const cp_declarator *declarator, args && args != void_list_node; args = TREE_CHAIN (args)) { - tree decl = cp_build_parm_decl (NULL_TREE, TREE_VALUE (args)); + tree decl = cp_build_parm_decl (NULL_TREE, NULL_TREE, + TREE_VALUE (args)); DECL_CHAIN (decl) = decls; decls = decl; @@ -11794,7 +11791,7 @@ grokdeclarator (const cp_declarator *declarator, if (decl_context == PARM) { - decl = cp_build_parm_decl (unqualified_id, type); + decl = cp_build_parm_decl (NULL_TREE, unqualified_id, type); DECL_ARRAY_PARAMETER_P (decl) = array_parameter_p; bad_specifiers (decl, BSP_PARM, virtualp, diff --git a/gcc/cp/decl2.c b/gcc/cp/decl2.c index f9d5887..53412e9 100644 --- a/gcc/cp/decl2.c +++ b/gcc/cp/decl2.c @@ -192,14 +192,16 @@ change_return_type (tree new_ret, tree fntype) return newtype; } -/* Build a PARM_DECL with NAME and TYPE, and set DECL_ARG_TYPE +/* Build a PARM_DECL of FN with NAME and TYPE, and set DECL_ARG_TYPE appropriately. */ tree -cp_build_parm_decl (tree name, tree type) +cp_build_parm_decl (tree fn, tree name, tree type) { tree parm = build_decl (input_location, PARM_DECL, name, type); + DECL_CONTEXT (parm) = fn; + /* DECL_ARG_TYPE is only used by the back end and the back end never sees templates. */ if (!processing_template_decl) @@ -208,13 +210,13 @@ cp_build_parm_decl (tree name, tree type) return parm; } -/* Returns a PARM_DECL for a parameter of the indicated TYPE, with the +/* Returns a PARM_DECL of FN for a parameter of the indicated TYPE, with the indicated NAME. */ tree -build_artificial_parm (tree name, tree type) +build_artificial_parm (tree fn, tree name, tree type) { - tree parm = cp_build_parm_decl (name, type); + tree parm = cp_build_parm_decl (fn, name, type); DECL_ARTIFICIAL (parm) = 1; /* All our artificial parms are implicitly `const'; they cannot be assigned to. */ @@ -265,7 +267,7 @@ maybe_retrofit_in_chrg (tree fn) pass us a pointer to our VTT. */ if (CLASSTYPE_VBASECLASSES (DECL_CONTEXT (fn))) { - parm = build_artificial_parm (vtt_parm_identifier, vtt_parm_type); + parm = build_artificial_parm (fn, vtt_parm_identifier, vtt_parm_type); /* First add it to DECL_ARGUMENTS between 'this' and the real args... */ DECL_CHAIN (parm) = parms; @@ -278,7 +280,7 @@ maybe_retrofit_in_chrg (tree fn) } /* Then add the in-charge parm (before the VTT parm). */ - parm = build_artificial_parm (in_charge_identifier, integer_type_node); + parm = build_artificial_parm (fn, in_charge_identifier, integer_type_node); DECL_CHAIN (parm) = parms; parms = parm; arg_types = hash_tree_chain (integer_type_node, arg_types); @@ -3502,12 +3504,10 @@ start_static_storage_duration_function (unsigned count) /* Create the argument list. */ initialize_p_decl = cp_build_parm_decl - (get_identifier (INITIALIZE_P_IDENTIFIER), integer_type_node); - DECL_CONTEXT (initialize_p_decl) = ssdf_decl; + (ssdf_decl, get_identifier (INITIALIZE_P_IDENTIFIER), integer_type_node); TREE_USED (initialize_p_decl) = 1; priority_decl = cp_build_parm_decl - (get_identifier (PRIORITY_IDENTIFIER), integer_type_node); - DECL_CONTEXT (priority_decl) = ssdf_decl; + (ssdf_decl, get_identifier (PRIORITY_IDENTIFIER), integer_type_node); TREE_USED (priority_decl) = 1; DECL_CHAIN (initialize_p_decl) = priority_decl; diff --git a/gcc/cp/lambda.c b/gcc/cp/lambda.c index 52e1fb7..ee8784c 100644 --- a/gcc/cp/lambda.c +++ b/gcc/cp/lambda.c @@ -1102,7 +1102,8 @@ maybe_add_lambda_conv_op (tree type) DECL_ARTIFICIAL (fn) = 1; DECL_NOT_REALLY_EXTERN (fn) = 1; DECL_DECLARED_INLINE_P (fn) = 1; - DECL_ARGUMENTS (fn) = build_this_parm (fntype, TYPE_QUAL_CONST); + DECL_ARGUMENTS (fn) = build_this_parm (fn, fntype, TYPE_QUAL_CONST); + if (nested_def) DECL_INTERFACE_KNOWN (fn) = 1; diff --git a/gcc/cp/method.c b/gcc/cp/method.c index 98d36da..9541fcb 100644 --- a/gcc/cp/method.c +++ b/gcc/cp/method.c @@ -2072,7 +2072,7 @@ implicitly_declare_fn (special_function_kind kind, tree type, /* Note that this parameter is *not* marked DECL_ARTIFICIAL; we want its type to be included in the mangled function name. */ - tree decl = cp_build_parm_decl (NULL_TREE, rhs_parm_type); + tree decl = cp_build_parm_decl (fn, NULL_TREE, rhs_parm_type); TREE_READONLY (decl) = 1; retrofit_lang_decl (decl); DECL_PARM_INDEX (decl) = DECL_PARM_LEVEL (decl) = 1; @@ -2085,11 +2085,10 @@ implicitly_declare_fn (special_function_kind kind, tree type, for (tree parm = inherited_parms; parm && parm != void_list_node; parm = TREE_CHAIN (parm)) { - *p = cp_build_parm_decl (NULL_TREE, TREE_VALUE (parm)); + *p = cp_build_parm_decl (fn, NULL_TREE, TREE_VALUE (parm)); retrofit_lang_decl (*p); DECL_PARM_LEVEL (*p) = 1; DECL_PARM_INDEX (*p) = index++; - DECL_CONTEXT (*p) = fn; p = &DECL_CHAIN (*p); } SET_DECL_INHERITED_CTOR (fn, inherited_ctor); @@ -2103,7 +2102,7 @@ implicitly_declare_fn (special_function_kind kind, tree type, constexpr_p = DECL_DECLARED_CONSTEXPR_P (inherited_ctor); } /* Add the "this" parameter. */ - this_parm = build_this_parm (fn_type, TYPE_UNQUALIFIED); + this_parm = build_this_parm (fn, fn_type, TYPE_UNQUALIFIED); DECL_CHAIN (this_parm) = DECL_ARGUMENTS (fn); DECL_ARGUMENTS (fn) = this_parm; diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index d02ad36..4adf9aa 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -20451,7 +20451,7 @@ inject_this_parameter (tree ctype, cp_cv_quals quals) return; } - this_parm = build_this_parm (ctype, quals); + this_parm = build_this_parm (NULL_TREE, ctype, quals); /* Clear this first to avoid shortcut in cp_build_indirect_ref. */ current_class_ptr = NULL_TREE; current_class_ref -- cgit v1.1 From 28ae04d46ea61a77b5a41267fc09b9478d4fb3cc Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Fri, 16 Jun 2017 18:08:36 +0200 Subject: profile.c (compare_freqs): New function. * profile.c (compare_freqs): New function. (branch_prob): Sort edge list. (find_spanning_tree): Assume that the list is priority sorted. From-SVN: r249270 --- gcc/ChangeLog | 6 ++++++ gcc/profile.c | 40 ++++++++++++++++++++++++---------------- 2 files changed, 30 insertions(+), 16 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b55b0ce..169f014 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-16 Jan Hubicka + + * profile.c (compare_freqs): New function. + (branch_prob): Sort edge list. + (find_spanning_tree): Assume that the list is priority sorted. + 2017-06-16 Richard Biener PR tree-optimization/81090 diff --git a/gcc/profile.c b/gcc/profile.c index 69a2c47..51ca248 100644 --- a/gcc/profile.c +++ b/gcc/profile.c @@ -987,6 +987,27 @@ output_location (char const *file_name, int line, } } +/* Helper for qsort so edges get sorted from highest frequency to smallest. + This controls the weight for minimal spanning tree algorithm */ +static int +compare_freqs (const void *p1, const void *p2) +{ + const_edge e1 = *(const const_edge *)p1; + const_edge e2 = *(const const_edge *)p2; + + /* Critical edges needs to be split which introduce extra control flow. + Make them more heavy. */ + int m1 = EDGE_CRITICAL_P (e1) ? 2 : 1; + int m2 = EDGE_CRITICAL_P (e2) ? 2 : 1; + + if (EDGE_FREQUENCY (e1) * m1 + m1 != EDGE_FREQUENCY (e2) * m2 + m2) + return EDGE_FREQUENCY (e2) * m2 + m2 - EDGE_FREQUENCY (e1) * m1 - m1; + /* Stabilize sort. */ + if (e1->src->index != e2->src->index) + return e2->src->index - e1->src->index; + return e2->dest->index - e1->dest->index; +} + /* Instrument and/or analyze program behavior based on program the CFG. This function creates a representation of the control flow graph (of @@ -1140,6 +1161,7 @@ branch_prob (void) el = create_edge_list (); num_edges = NUM_EDGES (el); + qsort (el->index_to_edge, num_edges, sizeof (edge), compare_freqs); alloc_aux_for_edges (sizeof (struct edge_profile_info)); /* The basic blocks are expected to be numbered sequentially. */ @@ -1431,22 +1453,8 @@ find_spanning_tree (struct edge_list *el) } } - /* Now insert all critical edges to the tree unless they form a cycle. */ - for (i = 0; i < num_edges; i++) - { - edge e = INDEX_EDGE (el, i); - if (EDGE_CRITICAL_P (e) && !EDGE_INFO (e)->ignore - && find_group (e->src) != find_group (e->dest)) - { - if (dump_file) - fprintf (dump_file, "Critical edge %d to %d put to tree\n", - e->src->index, e->dest->index); - EDGE_INFO (e)->on_tree = 1; - union_groups (e->src, e->dest); - } - } - - /* And now the rest. */ + /* And now the rest. Edge list is sorted according to frequencies and + thus we will produce minimal spanning tree. */ for (i = 0; i < num_edges; i++) { edge e = INDEX_EDGE (el, i); -- cgit v1.1 From ec73e54d0a0d2f14f1bde8f30bdb4c089dd19857 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Fri, 16 Jun 2017 19:19:50 +0200 Subject: * gcc.dg/tree-ssa/ssa-lim-11.c: Disable branch prediction. From-SVN: r249271 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/tree-ssa/ssa-lim-11.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f6b56ad..3f91cab 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-16 Jan Hubicka + + * gcc.dg/tree-ssa/ssa-lim-11.c: Disable branch prediction. + 2017-06-16 Richard Biener PR tree-optimization/81090 diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-lim-11.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-lim-11.c index 4c38982..f35c0f3 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-lim-11.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-lim-11.c @@ -22,4 +22,4 @@ void access_buf(struct thread_param* p) } } -/* { dg-final { scan-tree-dump-times "Executing store motion of __gcov0.access_buf\\\[\[01\]\\\] from loop 1" 2 "lim2" } } */ +/* { dg-final { scan-tree-dump-times "Executing store motion of __gcov0.access_buf\\\[\[12\]\\\] from loop 1" 2 "lim2" } } */ -- cgit v1.1 From 56960fd6d17aa4dcec9e8e261389337374cc738f Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Fri, 16 Jun 2017 17:29:56 +0000 Subject: [Patch ARM] Fix PR71778 gcc/ PR target/71778 * config/arm/arm-builtins.c (arm_expand_builtin_args): Return TARGET if given a non-constant argument for an intrinsic which requires a constant. gcc/testsuite/ PR target/71778 * gcc.target/arm/pr71778.c: New. From-SVN: r249272 --- gcc/ChangeLog | 7 +++++++ gcc/config/arm/arm-builtins.c | 7 ++++++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/arm/pr71778.c | 24 ++++++++++++++++++++++++ 4 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/pr71778.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 169f014..2a4b3b7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-06-16 James Greenhalgh + + PR target/71778 + * config/arm/arm-builtins.c (arm_expand_builtin_args): Return TARGET + if given a non-constant argument for an intrinsic which requires a + constant. + 2017-06-16 Jan Hubicka * profile.c (compare_freqs): New function. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index a0569ed..8ecf581 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -2245,7 +2245,12 @@ constant_arg: { error ("%Kargument %d must be a constant immediate", exp, argc + 1); - return const0_rtx; + /* We have failed to expand the pattern, and are safely + in to invalid code. But the mid-end will still try to + build an assignment for this node while it expands, + before stopping for the error, just pass it back + TARGET to ensure a valid assignment. */ + return target; } break; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3f91cab..84d81d3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-16 James Greenhalgh + + PR target/71778 + * gcc.target/arm/pr71778.c: New. + 2017-06-16 Jan Hubicka * gcc.dg/tree-ssa/ssa-lim-11.c: Disable branch prediction. diff --git a/gcc/testsuite/gcc.target/arm/pr71778.c b/gcc/testsuite/gcc.target/arm/pr71778.c new file mode 100644 index 0000000..d5b0d04 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr71778.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +typedef __simd128_int32_t int32x4_t; + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vshrq_n_s32 (int32x4_t __a, const int __b) +{ + /* Errors for arm_neon.h intrinsics using constants end up on the line + in arm_neon.h rather than the source file line. That means we + need to put the dg-error up here, rather than on line 22 where we'd + like it. */ + return (int32x4_t)__builtin_neon_vshrs_nv4si (__a, __b); /* { dg-error "argument 2 must be a constant immediate" } */ +} + +int32x4_t +shift (int32x4_t a, int b) +{ + return vshrq_n_s32 (a, b); +} + -- cgit v1.1 From 4086ef7d8979cf55a8908a3a100f2c2b9377f295 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Fri, 16 Jun 2017 18:38:28 +0000 Subject: * pt.c (tsubst_baselink): Fix & clarify formatting. From-SVN: r249273 --- gcc/cp/ChangeLog | 2 + gcc/cp/pt.c | 148 +++++++++++++++++++++++++++---------------------------- 2 files changed, 74 insertions(+), 76 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 11f2d03..ce1e8d0 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,7 @@ 2017-06-16 Nathan Sidwell + * pt.c (tsubst_baselink): Fix & clarify formatting. + * cp-tree.h (build_this_parm, cp_build_parm_decl, build_artificial_parm): Add FN parm. * decl.c (start_cleanup_fn): Adjust. diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 91b98d4..3dad0fc 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -14215,93 +14215,89 @@ tsubst (tree t, tree args, tsubst_flags_t complain, tree in_decl) } } -/* Like tsubst_expr for a BASELINK. OBJECT_TYPE, if non-NULL, is the - type of the expression on the left-hand side of the "." or "->" - operator. */ +/* tsubst a BASELINK. OBJECT_TYPE, if non-NULL, is the type of the + expression on the left-hand side of the "." or "->" operator. A + baselink indicates a function from a base class. Both the + BASELINK_ACCESS_BINFO and the base class referenced may indicate + bases of the template class, rather than the instantiated class. + In addition, lookups that were not ambiguous before may be + ambiguous now. Therefore, we perform the lookup again. */ static tree tsubst_baselink (tree baselink, tree object_type, tree args, tsubst_flags_t complain, tree in_decl) { - tree name; - tree qualifying_scope; - tree fns; - tree optype; - tree template_args = 0; - bool template_id_p = false; - bool qualified = BASELINK_QUALIFIED_P (baselink); - - /* A baselink indicates a function from a base class. Both the - BASELINK_ACCESS_BINFO and the base class referenced may - indicate bases of the template class, rather than the - instantiated class. In addition, lookups that were not - ambiguous before may be ambiguous now. Therefore, we perform - the lookup again. */ - qualifying_scope = BINFO_TYPE (BASELINK_ACCESS_BINFO (baselink)); - qualifying_scope = tsubst (qualifying_scope, args, - complain, in_decl); - fns = BASELINK_FUNCTIONS (baselink); - optype = tsubst (BASELINK_OPTYPE (baselink), args, complain, in_decl); - if (TREE_CODE (fns) == TEMPLATE_ID_EXPR) - { - template_id_p = true; - template_args = TREE_OPERAND (fns, 1); - fns = TREE_OPERAND (fns, 0); - if (template_args) - template_args = tsubst_template_args (template_args, args, - complain, in_decl); - } - name = OVL_NAME (fns); - if (IDENTIFIER_TYPENAME_P (name)) - name = mangle_conv_op_name_for_type (optype); - baselink = lookup_fnfields (qualifying_scope, name, /*protect=*/1); - if (!baselink) - { - if (constructor_name_p (name, qualifying_scope)) - { - if (complain & tf_error) - error ("cannot call constructor %<%T::%D%> directly", - qualifying_scope, name); - } - return error_mark_node; - } + bool qualified = BASELINK_QUALIFIED_P (baselink); + + tree qualifying_scope = BINFO_TYPE (BASELINK_ACCESS_BINFO (baselink)); + qualifying_scope = tsubst (qualifying_scope, args, complain, in_decl); + + tree optype = BASELINK_OPTYPE (baselink); + optype = tsubst (optype, args, complain, in_decl); + + tree template_args = NULL_TREE; + bool template_id_p = false; + tree fns = BASELINK_FUNCTIONS (baselink); + if (TREE_CODE (fns) == TEMPLATE_ID_EXPR) + { + template_id_p = true; + template_args = TREE_OPERAND (fns, 1); + fns = TREE_OPERAND (fns, 0); + if (template_args) + template_args = tsubst_template_args (template_args, args, + complain, in_decl); + } - /* If lookup found a single function, mark it as used at this - point. (If it lookup found multiple functions the one selected - later by overload resolution will be marked as used at that - point.) */ - if (BASELINK_P (baselink)) - fns = BASELINK_FUNCTIONS (baselink); - if (!template_id_p && !really_overloaded_fn (fns) - && !mark_used (OVL_FIRST (fns), complain) && !(complain & tf_error)) + tree name = OVL_NAME (fns); + if (IDENTIFIER_TYPENAME_P (name)) + name = mangle_conv_op_name_for_type (optype); + + baselink = lookup_fnfields (qualifying_scope, name, /*protect=*/1); + if (!baselink) + { + if ((complain & tf_error) && constructor_name_p (name, qualifying_scope)) + error ("cannot call constructor %<%T::%D%> directly", + qualifying_scope, name); return error_mark_node; + } + + /* If lookup found a single function, mark it as used at this point. + (If it lookup found multiple functions the one selected later by + overload resolution will be marked as used at that point.) */ + if (BASELINK_P (baselink)) + fns = BASELINK_FUNCTIONS (baselink); + if (!template_id_p && !really_overloaded_fn (fns) + && !mark_used (OVL_FIRST (fns), complain) && !(complain & tf_error)) + return error_mark_node; - /* Add back the template arguments, if present. */ - if (BASELINK_P (baselink) && template_id_p) - BASELINK_FUNCTIONS (baselink) - = build2 (TEMPLATE_ID_EXPR, - unknown_type_node, - BASELINK_FUNCTIONS (baselink), - template_args); - /* Update the conversion operator type. */ - if (BASELINK_P (baselink)) + if (BASELINK_P (baselink)) + { + /* Add back the template arguments, if present. */ + if (template_id_p) + BASELINK_FUNCTIONS (baselink) + = build2 (TEMPLATE_ID_EXPR, unknown_type_node, + BASELINK_FUNCTIONS (baselink), template_args); + + /* Update the conversion operator type. */ BASELINK_OPTYPE (baselink) = optype; + } - if (!object_type) - object_type = current_class_type; + if (!object_type) + object_type = current_class_type; - if (qualified || name == complete_dtor_identifier) - { - baselink = adjust_result_of_qualified_name_lookup (baselink, - qualifying_scope, - object_type); - if (!qualified) - /* We need to call adjust_result_of_qualified_name_lookup in case the - destructor names a base class, but we unset BASELINK_QUALIFIED_P - so that we still get virtual function binding. */ - BASELINK_QUALIFIED_P (baselink) = false; - } - return baselink; + if (qualified || name == complete_dtor_identifier) + { + baselink = adjust_result_of_qualified_name_lookup (baselink, + qualifying_scope, + object_type); + if (!qualified) + /* We need to call adjust_result_of_qualified_name_lookup in case the + destructor names a base class, but we unset BASELINK_QUALIFIED_P + so that we still get virtual function binding. */ + BASELINK_QUALIFIED_P (baselink) = false; + } + + return baselink; } /* Like tsubst_expr for a SCOPE_REF, given by QUALIFIED_ID. DONE is -- cgit v1.1 From deca6d60723728562b179f501d3bb3b840e51ebc Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Fri, 16 Jun 2017 21:01:01 +0200 Subject: * tree-ssa-tail-merge.c (replace_block_by): Fix profile updating. From-SVN: r249274 --- gcc/ChangeLog | 4 ++++ gcc/tree-ssa-tail-merge.c | 46 ++++++++++++++++++++++++++++++++++------------ 2 files changed, 38 insertions(+), 12 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2a4b3b7..eb688d2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2017-06-16 Jan Hubicka + + * tree-ssa-tail-merge.c (replace_block_by): Fix profile updating. + 2017-06-16 James Greenhalgh PR target/71778 diff --git a/gcc/tree-ssa-tail-merge.c b/gcc/tree-ssa-tail-merge.c index c86148b..f6c9878 100644 --- a/gcc/tree-ssa-tail-merge.c +++ b/gcc/tree-ssa-tail-merge.c @@ -1555,29 +1555,51 @@ replace_block_by (basic_block bb1, basic_block bb2) pred_edge, UNKNOWN_LOCATION); } - bb2->frequency += bb1->frequency; - if (bb2->frequency > BB_FREQ_MAX) - bb2->frequency = BB_FREQ_MAX; - bb2->count += bb1->count; /* Merge the outgoing edge counts from bb1 onto bb2. */ profile_count out_sum = profile_count::zero (); + int out_freq_sum = 0; + + /* Recompute the edge probabilities from the new merged edge count. + Use the sum of the new merged edge counts computed above instead + of bb2's merged count, in case there are profile count insanities + making the bb count inconsistent with the edge weights. */ + FOR_EACH_EDGE (e1, ei, bb1->succs) + { + if (e1->count.initialized_p ()) + out_sum += e1->count; + out_freq_sum += EDGE_FREQUENCY (e1); + } + FOR_EACH_EDGE (e1, ei, bb2->succs) + { + if (e1->count.initialized_p ()) + out_sum += e1->count; + out_freq_sum += EDGE_FREQUENCY (e1); + } + FOR_EACH_EDGE (e1, ei, bb1->succs) { e2 = find_edge (bb2, e1->dest); gcc_assert (e2); e2->count += e1->count; + if (out_sum > 0 && e2->count.initialized_p ()) + { + e2->probability = e2->count.probability_in (bb2->count); + } + else if (bb1->frequency && bb2->frequency) + e2->probability = e1->probability; + else if (bb2->frequency && !bb1->frequency) + ; + else if (out_freq_sum) + e2->probability = GCOV_COMPUTE_SCALE (EDGE_FREQUENCY (e1) + + EDGE_FREQUENCY (e2), + out_freq_sum); out_sum += e2->count; } - /* Recompute the edge probabilities from the new merged edge count. - Use the sum of the new merged edge counts computed above instead - of bb2's merged count, in case there are profile count insanities - making the bb count inconsistent with the edge weights. */ - FOR_EACH_EDGE (e2, ei, bb2->succs) - { - e2->probability = e2->count.probability_in (out_sum); - } + bb2->frequency += bb1->frequency; + if (bb2->frequency > BB_FREQ_MAX) + bb2->frequency = BB_FREQ_MAX; /* Move over any user labels from bb1 after the bb2 labels. */ gimple_stmt_iterator gsi1 = gsi_start_bb (bb1); -- cgit v1.1 From 8fb0ae8223ee3529675d2f66aa4ca94af776e943 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Fri, 16 Jun 2017 21:01:39 +0200 Subject: tree-ssa-loop-ivcanon.c (remove_exits_and_undefined_stmts): Update profile. * tree-ssa-loop-ivcanon.c (remove_exits_and_undefined_stmts): Update profile. (try_unroll_loop_completely): Fix reporting. From-SVN: r249275 --- gcc/ChangeLog | 6 ++++++ gcc/tree-ssa-loop-ivcanon.c | 7 +++++-- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eb688d2..44ef857 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2017-06-16 Jan Hubicka + * tree-ssa-loop-ivcanon.c (remove_exits_and_undefined_stmts): Update + profile. + (try_unroll_loop_completely): Fix reporting. + +2017-06-16 Jan Hubicka + * tree-ssa-tail-merge.c (replace_block_by): Fix profile updating. 2017-06-16 James Greenhalgh diff --git a/gcc/tree-ssa-loop-ivcanon.c b/gcc/tree-ssa-loop-ivcanon.c index f4ebe48..82ad59c 100644 --- a/gcc/tree-ssa-loop-ivcanon.c +++ b/gcc/tree-ssa-loop-ivcanon.c @@ -529,6 +529,8 @@ remove_exits_and_undefined_stmts (struct loop *loop, unsigned int npeeled) } if (!loop_exit_edge_p (loop, exit_edge)) exit_edge = EDGE_SUCC (bb, 1); + exit_edge->probability = REG_BR_PROB_BASE; + exit_edge->count = exit_edge->src->count; gcc_checking_assert (loop_exit_edge_p (loop, exit_edge)); gcond *cond_stmt = as_a (elt->stmt); if (exit_edge->flags & EDGE_TRUE_VALUE) @@ -853,8 +855,9 @@ try_unroll_loop_completely (struct loop *loop, loop->num); return false; } - dump_printf_loc (report_flags, locus, - "loop turned into non-loop; it never loops.\n"); + if (!n_unroll) + dump_printf_loc (report_flags, locus, + "loop turned into non-loop; it never loops.\n"); initialize_original_copy_tables (); auto_sbitmap wont_exit (n_unroll + 1); -- cgit v1.1 From 8d71d7cd025d5b0b62a8cb9fd99c38f1b37fcc7d Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Fri, 16 Jun 2017 21:02:11 +0200 Subject: predict.c (force_edge_cold): Handle declaring edges impossible more aggresively. * predict.c (force_edge_cold): Handle declaring edges impossible more aggresively. From-SVN: r249276 --- gcc/ChangeLog | 5 +++++ gcc/predict.c | 33 ++++++++++++++++++++++++++++++++- 2 files changed, 37 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 44ef857..b22b567 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Jan Hubicka + * predict.c (force_edge_cold): Handle declaring edges impossible + more aggresively. + +2017-06-16 Jan Hubicka + * tree-ssa-loop-ivcanon.c (remove_exits_and_undefined_stmts): Update profile. (try_unroll_loop_completely): Fix reporting. diff --git a/gcc/predict.c b/gcc/predict.c index 1cb7dc5..60d1a09 100644 --- a/gcc/predict.c +++ b/gcc/predict.c @@ -3968,6 +3968,7 @@ force_edge_cold (edge e, bool impossible) profile_count old_count = e->count; int old_probability = e->probability; int prob_scale = REG_BR_PROB_BASE; + bool uninitialized_exit = false; /* If edge is already improbably or cold, just return. */ if (e->probability <= (impossible ? PROB_VERY_UNLIKELY : 0) @@ -3978,6 +3979,8 @@ force_edge_cold (edge e, bool impossible) { if (e2->count.initialized_p ()) count_sum += e2->count; + else + uninitialized_exit = true; prob_sum += e2->probability; } @@ -3989,7 +3992,7 @@ force_edge_cold (edge e, bool impossible) = MIN (e->probability, impossible ? 0 : PROB_VERY_UNLIKELY); if (impossible) e->count = profile_count::zero (); - if (old_probability) + else if (old_probability) e->count = e->count.apply_scale (e->probability, old_probability); else e->count = e->count.apply_scale (1, REG_BR_PROB_BASE); @@ -4016,6 +4019,34 @@ force_edge_cold (edge e, bool impossible) else { e->probability = REG_BR_PROB_BASE; + if (e->src->count == profile_count::zero ()) + return; + if (count_sum == profile_count::zero () && !uninitialized_exit + && impossible) + { + bool found = false; + for (gimple_stmt_iterator gsi = gsi_start_bb (e->src); + !gsi_end_p (gsi); gsi_next (&gsi)) + { + if (stmt_can_terminate_bb_p (gsi_stmt (gsi))) + { + found = true; + break; + } + } + if (!found) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, + "Making bb %i impossible and dropping count to 0.\n", + e->src->index); + e->count = profile_count::zero (); + e->src->count = profile_count::zero (); + FOR_EACH_EDGE (e2, ei, e->src->preds) + force_edge_cold (e2, impossible); + return; + } + } /* If we did not adjusting, the source basic block has no likely edeges leaving other direction. In that case force that bb cold, too. -- cgit v1.1 From aa11163b181893ed79dc1c75547b0109b342372e Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Fri, 16 Jun 2017 21:02:46 +0200 Subject: gimple-ssa-isolate-paths.c (isolate_path): Set edge leading to path as unlikely; update profile. * gimple-ssa-isolate-paths.c (isolate_path): Set edge leading to path as unlikely; update profile. From-SVN: r249277 --- gcc/ChangeLog | 5 +++++ gcc/gimple-ssa-isolate-paths.c | 13 +++++++++++++ 2 files changed, 18 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b22b567..dfabe17 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Jan Hubicka + * gimple-ssa-isolate-paths.c (isolate_path): Set edge leading to path + as unlikely; update profile. + +2017-06-16 Jan Hubicka + * predict.c (force_edge_cold): Handle declaring edges impossible more aggresively. diff --git a/gcc/gimple-ssa-isolate-paths.c b/gcc/gimple-ssa-isolate-paths.c index 7babe09..7ad39b4 100644 --- a/gcc/gimple-ssa-isolate-paths.c +++ b/gcc/gimple-ssa-isolate-paths.c @@ -137,6 +137,15 @@ isolate_path (basic_block bb, basic_block duplicate, gimple_stmt_iterator si, si2; edge_iterator ei; edge e2; + bool impossible = true; + + for (si = gsi_start_bb (bb); gsi_stmt (si) != stmt; gsi_next (&si)) + if (stmt_can_terminate_bb_p (gsi_stmt (si))) + { + impossible = false; + break; + } + force_edge_cold (e, impossible); /* First duplicate BB if we have not done so already and remove all the duplicate's outgoing edges as duplicate is going to unconditionally @@ -145,10 +154,14 @@ isolate_path (basic_block bb, basic_block duplicate, if (!duplicate) { duplicate = duplicate_block (bb, NULL, NULL); + bb->frequency = 0; + bb->count = profile_count::zero (); if (!ret_zero) for (ei = ei_start (duplicate->succs); (e2 = ei_safe_edge (ei)); ) remove_edge (e2); } + bb->frequency += EDGE_FREQUENCY (e); + bb->count += e->count; /* Complete the isolation step by redirecting E to reach DUPLICATE. */ e2 = redirect_edge_and_branch (e, duplicate); -- cgit v1.1 From b3d8d88efa4d8467d3b0657cc8a4a3e1913d939c Mon Sep 17 00:00:00 2001 From: Martin Sebor Date: Fri, 16 Jun 2017 20:52:03 +0000 Subject: PR tree-optimization/80934 - bzero should be assumed not to escape pointer argument PR tree-optimization/80934 - bzero should be assumed not to escape pointer argument PR tree-optimization/80933 - redundant bzero/bcopy calls not eliminated gcc/ChangeLog: PR tree-optimization/80933 PR tree-optimization/80934 * builtins.c (fold_builtin_3): Do not handle bcmp here. * gimple-fold.c (gimple_fold_builtin_bcmp): New function. (gimple_fold_builtin_bcopy, gimple_fold_builtin_bzero): Likewise. (gimple_fold_builtin): Call them. gcc/testsuite/ChangeLog: PR tree-optimization/80933 PR tree-optimization/80934 * gcc.dg/fold-bcopy.c: New test. * gcc.dg/tree-ssa/ssa-dse-30.c: Likewise.. * gcc.dg/tree-ssa/alias-36.c: Likewise. * gcc/testsuite/gcc.dg/pr79214.c: Adjust. * gcc.dg/tree-prof/val-prof-7.c: Likewise. * gcc.dg/Wsizeof-pointer-memaccess1.c: Likewise. * gcc.dg/builtins-nonnull.c: Likewise. From-SVN: r249278 --- gcc/ChangeLog | 9 +++ gcc/builtins.c | 1 - gcc/gimple-fold.c | 88 +++++++++++++++++++++-- gcc/testsuite/ChangeLog | 12 ++++ gcc/testsuite/gcc.dg/Wsizeof-pointer-memaccess1.c | 2 +- gcc/testsuite/gcc.dg/builtins-nonnull.c | 5 +- gcc/testsuite/gcc.dg/fold-bcopy.c | 54 ++++++++++++++ gcc/testsuite/gcc.dg/pr79214.c | 2 +- gcc/testsuite/gcc.dg/tree-prof/val-prof-7.c | 13 +--- gcc/testsuite/gcc.dg/tree-ssa/alias-36.c | 28 ++++++++ gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-30.c | 31 ++++++++ 11 files changed, 224 insertions(+), 21 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/fold-bcopy.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/alias-36.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-30.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dfabe17..f8412af 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2017-06-16 Martin Sebor + + PR tree-optimization/80933 + PR tree-optimization/80934 + * builtins.c (fold_builtin_3): Do not handle bcmp here. + * gimple-fold.c (gimple_fold_builtin_bcmp): New function. + (gimple_fold_builtin_bcopy, gimple_fold_builtin_bzero): Likewise. + (gimple_fold_builtin): Call them. + 2017-06-16 Jan Hubicka * gimple-ssa-isolate-paths.c (isolate_path): Set edge leading to path diff --git a/gcc/builtins.c b/gcc/builtins.c index 30462ad..ce657bf 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -9034,7 +9034,6 @@ fold_builtin_3 (location_t loc, tree fndecl, return do_mpfr_remquo (arg0, arg1, arg2); break; - case BUILT_IN_BCMP: case BUILT_IN_MEMCMP: return fold_builtin_memcmp (loc, arg0, arg1, arg2);; diff --git a/gcc/gimple-fold.c b/gcc/gimple-fold.c index 0f8e326..a00c2c8 100644 --- a/gcc/gimple-fold.c +++ b/gcc/gimple-fold.c @@ -1077,6 +1077,83 @@ done: return true; } +/* Transform a call to built-in bcmp(a, b, len) at *GSI into one + to built-in memcmp (a, b, len). */ + +static bool +gimple_fold_builtin_bcmp (gimple_stmt_iterator *gsi) +{ + tree fn = builtin_decl_implicit (BUILT_IN_MEMCMP); + + if (!fn) + return false; + + /* Transform bcmp (a, b, len) into memcmp (a, b, len). */ + + gimple *stmt = gsi_stmt (*gsi); + tree a = gimple_call_arg (stmt, 0); + tree b = gimple_call_arg (stmt, 1); + tree len = gimple_call_arg (stmt, 2); + + gimple *repl = gimple_build_call (fn, 3, a, b, len); + replace_call_with_call_and_fold (gsi, repl); + + return true; +} + +/* Transform a call to built-in bcopy (src, dest, len) at *GSI into one + to built-in memmove (dest, src, len). */ + +static bool +gimple_fold_builtin_bcopy (gimple_stmt_iterator *gsi) +{ + tree fn = builtin_decl_implicit (BUILT_IN_MEMMOVE); + + if (!fn) + return false; + + /* bcopy has been removed from POSIX in Issue 7 but Issue 6 specifies + it's quivalent to memmove (not memcpy). Transform bcopy (src, dest, + len) into memmove (dest, src, len). */ + + gimple *stmt = gsi_stmt (*gsi); + tree src = gimple_call_arg (stmt, 0); + tree dest = gimple_call_arg (stmt, 1); + tree len = gimple_call_arg (stmt, 2); + + gimple *repl = gimple_build_call (fn, 3, dest, src, len); + gimple_call_set_fntype (as_a (stmt), TREE_TYPE (fn)); + replace_call_with_call_and_fold (gsi, repl); + + return true; +} + +/* Transform a call to built-in bzero (dest, len) at *GSI into one + to built-in memset (dest, 0, len). */ + +static bool +gimple_fold_builtin_bzero (gimple_stmt_iterator *gsi) +{ + tree fn = builtin_decl_implicit (BUILT_IN_MEMSET); + + if (!fn) + return false; + + /* Transform bzero (dest, len) into memset (dest, 0, len). */ + + gimple *stmt = gsi_stmt (*gsi); + tree dest = gimple_call_arg (stmt, 0); + tree len = gimple_call_arg (stmt, 1); + + gimple_seq seq = NULL; + gimple *repl = gimple_build_call (fn, 3, dest, integer_zero_node, len); + gimple_seq_add_stmt_without_update (&seq, repl); + gsi_replace_with_seq_vops (gsi, seq); + fold_stmt (gsi); + + return true; +} + /* Fold function call to builtin memset or bzero at *GSI setting the memory of size LEN to VAL. Return whether a simplification was made. */ @@ -3288,16 +3365,17 @@ gimple_fold_builtin (gimple_stmt_iterator *gsi) enum built_in_function fcode = DECL_FUNCTION_CODE (callee); switch (fcode) { + case BUILT_IN_BCMP: + return gimple_fold_builtin_bcmp (gsi); + case BUILT_IN_BCOPY: + return gimple_fold_builtin_bcopy (gsi); case BUILT_IN_BZERO: - return gimple_fold_builtin_memset (gsi, integer_zero_node, - gimple_call_arg (stmt, 1)); + return gimple_fold_builtin_bzero (gsi); + case BUILT_IN_MEMSET: return gimple_fold_builtin_memset (gsi, gimple_call_arg (stmt, 1), gimple_call_arg (stmt, 2)); - case BUILT_IN_BCOPY: - return gimple_fold_builtin_memory_op (gsi, gimple_call_arg (stmt, 1), - gimple_call_arg (stmt, 0), 3); case BUILT_IN_MEMCPY: return gimple_fold_builtin_memory_op (gsi, gimple_call_arg (stmt, 0), gimple_call_arg (stmt, 1), 0); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 84d81d3..962c388 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,15 @@ +2017-06-16 Martin Sebor + + PR tree-optimization/80933 + PR tree-optimization/80934 + * gcc.dg/fold-bcopy.c: New test. + * gcc.dg/tree-ssa/ssa-dse-30.c: Likewise.. + * gcc.dg/tree-ssa/alias-36.c: Likewise. + * gcc/testsuite/gcc.dg/pr79214.c: Adjust. + * gcc.dg/tree-prof/val-prof-7.c: Likewise. + * gcc.dg/Wsizeof-pointer-memaccess1.c: Likewise. + * gcc.dg/builtins-nonnull.c: Likewise. + 2017-06-16 James Greenhalgh PR target/71778 diff --git a/gcc/testsuite/gcc.dg/Wsizeof-pointer-memaccess1.c b/gcc/testsuite/gcc.dg/Wsizeof-pointer-memaccess1.c index 7feb122..f4e8552 100644 --- a/gcc/testsuite/gcc.dg/Wsizeof-pointer-memaccess1.c +++ b/gcc/testsuite/gcc.dg/Wsizeof-pointer-memaccess1.c @@ -1,6 +1,6 @@ /* Test -Wsizeof-pointer-memaccess warnings. */ /* { dg-do compile } */ -/* { dg-options "-Wall -Wno-sizeof-array-argument" } */ +/* { dg-options "-Wall -Wno-sizeof-array-argument -Wno-stringop-overflow" } */ /* { dg-require-effective-target alloca } */ typedef __SIZE_TYPE__ size_t; diff --git a/gcc/testsuite/gcc.dg/builtins-nonnull.c b/gcc/testsuite/gcc.dg/builtins-nonnull.c index fa9eaf2..726f8e1 100644 --- a/gcc/testsuite/gcc.dg/builtins-nonnull.c +++ b/gcc/testsuite/gcc.dg/builtins-nonnull.c @@ -24,8 +24,9 @@ void sink (int, ...); void test_memfuncs (void *s, unsigned n) { - /* Bzero is not declared attribute nonnull. */ - bzero (null (), n); + /* Bzero is not declared attribute nonnull (maybe it should be?) + but it's transformed into a call to memset() which is. */ + bzero (null (), n); /* { dg-warning "argument 1 null where non-null expected" } */ T (memcpy (null (), s, n)); /* { dg-warning "argument 1 null where non-null expected" } */ T (memcpy (s, null (), n)); /* { dg-warning "argument 2 null where non-null expected" } */ diff --git a/gcc/testsuite/gcc.dg/fold-bcopy.c b/gcc/testsuite/gcc.dg/fold-bcopy.c new file mode 100644 index 0000000..ed6cd06 --- /dev/null +++ b/gcc/testsuite/gcc.dg/fold-bcopy.c @@ -0,0 +1,54 @@ +/* PR tree-optimization/80933 - redundant bzero/bcopy calls not eliminated + { dg-do compile } + { dg-options "-O0 -Wall -fdump-tree-gimple" } */ + +void f0 (void *dst, const void *src, unsigned n) +{ + /* Bcopy(src, dst, ...) corresponds to memmove(dst, src, ...), + with the first two arguments transposed, not memcpy. */ + __builtin_bcopy (src, dst, n); +} + +void f1 (void *p, const void *q, unsigned n) +{ + /* A call with zero size should be eliminated. */ + __builtin_bcopy (q, p, 0); +} + +int f2 (const void *p, const void *q, unsigned n) +{ + return __builtin_bcmp (p, q, n); +} + +int f3 (const void *p, const void *q) +{ + /* A call with zero size should be folded into 0. */ + return __builtin_bcmp (p, q, 0); +} + +int f4 (const void *p, unsigned n) +{ + /* A call with the same argument should also be folded into 0. */ + return __builtin_bcmp (p, p, n); +} + +void f5 (void *p, unsigned n) +{ + __builtin_bzero (p, n); +} + +void f6 (void *p) +{ + /* A call with zero size should be eliminated. */ + __builtin_bzero (p, 0); +} + +/* Verify that calls to bcmp, bcopy, and bzero have all been removed + and one of each replaced with memcmp, memmove, and memset, respectively. + The remaining three should be eliminated. + { dg-final { scan-tree-dump-not "bcmp|bcopy|bzero" "gimple" } } + { dg-final { scan-tree-dump-times "memcmp|memmove|memset" 3 "gimple" } } + + Verify that the bcopy to memmove transformation correctly transposed + the source and destination pointer arguments. + { dg-final { scan-tree-dump-times "memmove \\(dst, src" 1 "gimple" } } */ diff --git a/gcc/testsuite/gcc.dg/pr79214.c b/gcc/testsuite/gcc.dg/pr79214.c index 79d2a25..6cf254fb 100644 --- a/gcc/testsuite/gcc.dg/pr79214.c +++ b/gcc/testsuite/gcc.dg/pr79214.c @@ -22,7 +22,7 @@ size_t range (void) void test_bzero (void) { - bzero (d, range ()); /* { dg-warning ".__builtin_bzero. writing 4 or more bytes into a region of size 3 overflows the destination" } */ + bzero (d, range ()); /* { dg-warning ".__builtin_(bzero|memset). writing 4 or more bytes into a region of size 3 overflows the destination" } */ } void test_memcpy (void) diff --git a/gcc/testsuite/gcc.dg/tree-prof/val-prof-7.c b/gcc/testsuite/gcc.dg/tree-prof/val-prof-7.c index 84ec9fb..5a4e777 100644 --- a/gcc/testsuite/gcc.dg/tree-prof/val-prof-7.c +++ b/gcc/testsuite/gcc.dg/tree-prof/val-prof-7.c @@ -4,14 +4,10 @@ char *buffer1; char *buffer2; +/* Bzero is not tested because it gets transformed into memset. */ + #define DEFINE_TEST(N) \ __attribute__((noinline)) \ -void bzero_test_ ## N (int len) \ -{ \ - __builtin_bzero (buffer1, len); \ -} \ - \ -__attribute__((noinline)) \ void memcpy_test_ ## N (int len) \ { \ __builtin_memcpy (buffer1, buffer2, len); \ @@ -31,7 +27,6 @@ void memset_test_ ## N (int len) \ \ void test_stringops_ ## N(int len) \ { \ - bzero_test_ ## N (len); \ memcpy_test_## N (len); \ mempcpy_test_ ## N (len); \ memset_test_ ## N (len); \ @@ -64,10 +59,6 @@ int main() { return 0; } -/* { dg-final-use-not-autofdo { scan-ipa-dump "Single value 8 stringop transformation on __builtin_bzero" "profile" } } */ -/* { dg-final-use-not-autofdo { scan-ipa-dump "Single value 55 stringop transformation on __builtin_bzero" "profile" } } */ -/* { dg-final-use-not-autofdo { scan-ipa-dump-times "Single value 32 stringop transformation on __builtin_bzero" 0 "profile" } } */ - /* { dg-final-use-not-autofdo { scan-ipa-dump "Single value 8 stringop transformation on __builtin_memcpy" "profile" } } */ /* { dg-final-use-not-autofdo { scan-ipa-dump "Single value 55 stringop transformation on __builtin_memcpy" "profile" } } */ /* { dg-final-use-not-autofdo { scan-ipa-dump-times "Single value 32 stringop transformation on __builtin_memcpy" 0 "profile" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/alias-36.c b/gcc/testsuite/gcc.dg/tree-ssa/alias-36.c new file mode 100644 index 0000000..61b601a --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/alias-36.c @@ -0,0 +1,28 @@ +/* PR tree-optimization/80934 - bzero should be assumed not to escape + pointer argument + { dg-do compile } + { dg-options "-O2 -fdump-tree-alias" } */ + +void foobar (void); + +void f (void); + +void g (void) +{ + char d[32]; + __builtin_memset (d, 0, sizeof d); + f (); + if (*d != 0) + foobar (); +} + +void h (void) +{ + char d[32]; + __builtin_bzero (d, sizeof d); + f (); + if (*d != 0) + foobar (); +} + +/* { dg-final { scan-tree-dump-not "memset|foobar|bzero" "alias" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-30.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-30.c new file mode 100644 index 0000000..ece8cb2 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-30.c @@ -0,0 +1,31 @@ +/* PR tree-optimization/80933 - redundant bzero/bcopy calls not eliminated + { dg-do compile } + { dg-options "-O2 -fdump-tree-dse1" } */ + +void sink (void*); + +void test_bcopy (const void *s) +{ + char d[33]; + + /* Bcopy is transformed into memcpy and those calls are expanded + inline in EVRP, before DSE runs, so this test doesn't actually + verify that DSE does its job. */ + __builtin_bcopy (s, d, sizeof d); + __builtin_bcopy (s, d, sizeof d); + + sink (d); +} + +void test_bzero (void) +{ + char d[33]; + + __builtin_bzero (d, sizeof d); + __builtin_bzero (d, sizeof d); + + sink (d); +} + +/* { dg-final { scan-tree-dump-times "builtin_memset" 1 "dse1" } } */ +/* { dg-final { scan-tree-dump-not "builtin_(bcopy|bzero|memcpy)" "dse1" } } */ -- cgit v1.1 From 80448ef60264c49c8b08e700b64a5d338d3806ba Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:01:22 +0000 Subject: [arm] Use strings for -march, -mcpu and -mtune options In order to support more complex specifications for cpus and architectures we need to move away from using enumerations to represent the set of permitted options. This basic change just moves the option parsing infrastructure over to that, but changes nothing more beyond generating a hint when the specified option does not match a known target (previously the help option was able to print out all the permitted values, but we can no-longer do that. * config/arm/arm.opt (x_arm_arch_string): New TargetSave option. (x_arm_cpu_string, x_arm_tune_string): Likewise. (march, mcpu, mtune): Convert to string-based options. * config/arm/arm.c (arm_print_hint_for_core_or_arch): New function. (arm_parse_arch_cpu_name): New function. (arm_configure_build_target): Use arm_parse_arch_cpu_name to identify selected architecture or CPU. (arm_option_save): New function. (TARGET_OPTION_SAVE): Redefine. (arm_option_restore): Restore string options. (arm_option_print): Print string options. From-SVN: r249279 --- gcc/ChangeLog | 14 ++++++++ gcc/config/arm/arm.c | 92 ++++++++++++++++++++++++++++++++++++++++++++------ gcc/config/arm/arm.opt | 15 ++++++-- 3 files changed, 108 insertions(+), 13 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f8412af..6123692 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2017-06-16 Richard Earnshaw + + * config/arm/arm.opt (x_arm_arch_string): New TargetSave option. + (x_arm_cpu_string, x_arm_tune_string): Likewise. + (march, mcpu, mtune): Convert to string-based options. + * config/arm/arm.c (arm_print_hint_for_core_or_arch): New function. + (arm_parse_arch_cpu_name): New function. + (arm_configure_build_target): Use arm_parse_arch_cpu_name to + identify selected architecture or CPU. + (arm_option_save): New function. + (TARGET_OPTION_SAVE): Redefine. + (arm_option_restore): Restore string options. + (arm_option_print): Print string options. + 2017-06-16 Martin Sebor PR tree-optimization/80933 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 259597d..2502eb8 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -233,6 +233,7 @@ static tree arm_build_builtin_va_list (void); static void arm_expand_builtin_va_start (tree, rtx); static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); static void arm_option_override (void); +static void arm_option_save (struct cl_target_option *, struct gcc_options *); static void arm_option_restore (struct gcc_options *, struct cl_target_option *); static void arm_override_options_after_change (void); @@ -413,6 +414,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE arm_override_options_after_change +#undef TARGET_OPTION_SAVE +#define TARGET_OPTION_SAVE arm_option_save + #undef TARGET_OPTION_RESTORE #define TARGET_OPTION_RESTORE arm_option_restore @@ -2902,9 +2906,22 @@ arm_override_options_after_change (void) arm_override_options_after_change_1 (&global_options); } +/* Implement TARGET_OPTION_SAVE. */ +static void +arm_option_save (struct cl_target_option *ptr, struct gcc_options *opts) +{ + ptr->x_arm_arch_string = opts->x_arm_arch_string; + ptr->x_arm_cpu_string = opts->x_arm_cpu_string; + ptr->x_arm_tune_string = opts->x_arm_tune_string; +} + +/* Implement TARGET_OPTION_RESTORE. */ static void -arm_option_restore (struct gcc_options *, struct cl_target_option *ptr) +arm_option_restore (struct gcc_options *opts, struct cl_target_option *ptr) { + opts->x_arm_arch_string = ptr->x_arm_arch_string; + opts->x_arm_cpu_string = ptr->x_arm_cpu_string; + opts->x_arm_tune_string = ptr->x_arm_tune_string; arm_configure_build_target (&arm_active_target, ptr, &global_options_set, false); } @@ -3022,6 +3039,46 @@ arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits) bitmap_set_bit (isa, *(isa_bits++)); } +/* List the permitted CPU or architecture names. If TARGET is a near + miss for an entry, print out the suggested alternative. */ +static void +arm_print_hint_for_core_or_arch (const char *target, + const struct processors *list) +{ + auto_vec candidates; + for (; list->name != NULL; list++) + candidates.safe_push (list->name); + char *s; + const char *hint = candidates_list_and_hint (target, s, candidates); + if (hint) + inform (input_location, "valid arguments are: %s; did you mean %qs?", + s, hint); + else + inform (input_location, "valid arguments are: %s", s); + + XDELETEVEC (s); +} + +/* Parse the base component of a CPU or architecture selection in + LIST. Return a pointer to the entry in the architecture table. + OPTNAME is the name of the option we are parsing and can be used if + a diagnostic is needed. */ +static const struct processors * +arm_parse_arch_cpu_name (const struct processors *list, const char *optname, + const char *target) +{ + const struct processors *entry; + for (entry = list; entry->name != NULL; entry++) + { + if (streq (entry->name, target)) + return entry; + } + + error_at (input_location, "unrecognized %s target: %s", optname, target); + arm_print_hint_for_core_or_arch (target, list); + return NULL; +} + static sbitmap isa_all_fpubits; static sbitmap isa_quirkbits; @@ -3043,17 +3100,20 @@ arm_configure_build_target (struct arm_build_target *target, target->core_name = NULL; target->arch_name = NULL; - if (opts_set->x_arm_arch_option) - arm_selected_arch = &all_architectures[opts->x_arm_arch_option]; - - if (opts_set->x_arm_cpu_option) + if (opts_set->x_arm_arch_string) + arm_selected_arch = arm_parse_arch_cpu_name (all_architectures, + "-march", + opts->x_arm_arch_string); + if (opts_set->x_arm_cpu_string) { - arm_selected_cpu = &all_cores[(int) opts->x_arm_cpu_option]; - arm_selected_tune = &all_cores[(int) opts->x_arm_cpu_option]; + arm_selected_cpu = arm_parse_arch_cpu_name (all_cores, "-mcpu", + opts->x_arm_cpu_string); + arm_selected_tune = arm_selected_cpu; } - if (opts_set->x_arm_tune_option) - arm_selected_tune = &all_cores[(int) opts->x_arm_tune_option]; + if (opts_set->x_arm_tune_string) + arm_selected_tune = arm_parse_arch_cpu_name (all_cores, "-mtune", + opts->x_arm_tune_string); if (arm_selected_arch) { @@ -30368,11 +30428,23 @@ arm_option_print (FILE *file, int indent, struct cl_target_option *ptr) fpu_name = (ptr->x_arm_fpu_index == TARGET_FPU_auto ? "auto" : all_fpus[ptr->x_arm_fpu_index].name); - fprintf (file, "%*sselected arch %s\n", indent, "", + fprintf (file, "%*sselected isa %s\n", indent, "", TARGET_THUMB2_P (flags) ? "thumb2" : TARGET_THUMB_P (flags) ? "thumb1" : "arm"); + if (ptr->x_arm_arch_string) + fprintf (file, "%*sselected architecture %s\n", indent, "", + ptr->x_arm_arch_string); + + if (ptr->x_arm_cpu_string) + fprintf (file, "%*sselected CPU %s\n", indent, "", + ptr->x_arm_cpu_string); + + if (ptr->x_arm_tune_string) + fprintf (file, "%*sselected tune %s\n", indent, "", + ptr->x_arm_tune_string); + fprintf (file, "%*sselected fpu %s\n", indent, "", fpu_name); } diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 9f8116d..efee1be 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -21,6 +21,15 @@ HeaderInclude config/arm/arm-opts.h +TargetSave +const char *x_arm_arch_string + +TargetSave +const char *x_arm_cpu_string + +TargetSave +const char *x_arm_tune_string + Enum Name(tls_type) Type(enum arm_tls_type) TLS dialect to use: @@ -73,7 +82,7 @@ mapcs-stack-check Target Report Mask(APCS_STACK) Undocumented march= -Target RejectNegative ToLower Joined Enum(arm_arch) Var(arm_arch_option) Save +Target RejectNegative ToLower Joined Var(arm_arch_string) Specify the name of the target architecture. ; Other arm_arch values are loaded from arm-tables.opt @@ -98,7 +107,7 @@ Target Report Mask(CALLER_INTERWORKING) Thumb: Assume function pointers may go to non-Thumb aware code. mcpu= -Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_cpu_option) Init(TARGET_CPU_arm_none) Save +Target RejectNegative ToLower Joined Var(arm_cpu_string) Specify the name of the target CPU. mfloat-abi= @@ -223,7 +232,7 @@ Target Report Mask(TPCS_LEAF_FRAME) Thumb: Generate (leaf) stack frames even if not needed. mtune= -Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_tune_option) Init(TARGET_CPU_arm_none) Save +Target RejectNegative ToLower Joined Var(arm_tune_string) Tune code for the given processor. mprint-tune-info -- cgit v1.1 From 867944533b944953804d3dc88bae280160599a04 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:01:29 +0000 Subject: [arm] Rewrite -march and -mcpu options for passing to The assembler does not understand all the '+' options accepted by the compiler. The best solution to this is to simply strip the extensions and just pass the raw architecture or cpu name through to the assembler. We will use .arch and .arch_extension directives anyway to turn on or off individual features. We already do something similar for big.little combinations and this just extends this principle a bit further. This patch also fixes a possible bug by ensuring that the limited string copy is correctly NUL-terminated. While messing with this code I've also taken the opportunity to clean up the duplicate definitions of EXTRA_SPEC_FUNCTIONS by moving it outside of the ifdef wrapper. * config/arm/arm.h (BIG_LITTLE_SPEC): Delete macro. (ASM_REWRITE_SPEC_FUNCTIONS): New macro. (BIG_LITTLE_CPU_SPEC_FUNCTIONS): Delete macro. (ASM_CPU_SPEC): Rewrite. (MCPU_MTUNE_NATIVE_FUNCTIONS): New macro. (EXTRA_SPEC_FUNCTIONS): Move outside of ifdef. Use MCPU_MTUNE_NATIVE_FUNCTIONS and ASM_REWRITE_SPEC_FUNCTIONS. Remove reference to BIG_LITTLE_CPU_SPEC_FUNCTIONS. * common/config/arm/arm-common.c (arm_rewrite_selected_cpu): Ensure copied string is NUL-terminated. Also strip any characters prefixed by '+'. (arm_rewrite_selected_arch): New function. (arm_rewrite_march): New function. From-SVN: r249280 --- gcc/ChangeLog | 16 ++++++++++++++ gcc/common/config/arm/arm-common.c | 45 +++++++++++++++++++++++++++++++++++++- gcc/config/arm/arm.h | 42 +++++++++++++++++------------------ 3 files changed, 81 insertions(+), 22 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6123692..1542ae3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,21 @@ 2017-06-16 Richard Earnshaw + * config/arm/arm.h (BIG_LITTLE_SPEC): Delete macro. + (ASM_REWRITE_SPEC_FUNCTIONS): New macro. + (BIG_LITTLE_CPU_SPEC_FUNCTIONS): Delete macro. + (ASM_CPU_SPEC): Rewrite. + (MCPU_MTUNE_NATIVE_FUNCTIONS): New macro. + (EXTRA_SPEC_FUNCTIONS): Move outside of ifdef. Use + MCPU_MTUNE_NATIVE_FUNCTIONS and ASM_REWRITE_SPEC_FUNCTIONS. Remove + reference to BIG_LITTLE_CPU_SPEC_FUNCTIONS. + * common/config/arm/arm-common.c (arm_rewrite_selected_cpu): Ensure + copied string is NUL-terminated. Also strip any characters prefixed + by '+'. + (arm_rewrite_selected_arch): New function. + (arm_rewrite_march): New function. + +2017-06-16 Richard Earnshaw + * config/arm/arm.opt (x_arm_arch_string): New TargetSave option. (x_arm_cpu_string, x_arm_tune_string): Likewise. (march, mcpu, mtune): Convert to string-based options. diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index 7ecc68d..fd0c616 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -66,7 +66,7 @@ arm_except_unwind_info (struct gcc_options *opts) #define ARM_CPU_NAME_LENGTH 20 -/* Truncate NAME at the first '.' character seen, or return +/* Truncate NAME at the first '.' or '+' character seen, or return NAME unmodified. */ const char * @@ -76,12 +76,20 @@ arm_rewrite_selected_cpu (const char *name) char *arg_pos; strncpy (output_buf, name, ARM_CPU_NAME_LENGTH); + output_buf[ARM_CPU_NAME_LENGTH] = 0; + arg_pos = strchr (output_buf, '.'); /* If we found a '.' truncate the entry at that point. */ if (arg_pos) *arg_pos = '\0'; + arg_pos = strchr (output_buf, '+'); + + /* If we found a '+' truncate the entry at that point. */ + if (arg_pos) + *arg_pos = '\0'; + return output_buf; } @@ -98,6 +106,41 @@ arm_rewrite_mcpu (int argc, const char **argv) return arm_rewrite_selected_cpu (argv[argc - 1]); } +/* Truncate NAME at the first '+' character seen, or return + NAME unmodified. Similar to arm_rewrite_selected_cpu, but we must + preserve '.' as that is part of some architecture names. */ + +const char * +arm_rewrite_selected_arch (const char *name) +{ + static char output_buf[ARM_CPU_NAME_LENGTH + 1] = {0}; + char *arg_pos; + + strncpy (output_buf, name, ARM_CPU_NAME_LENGTH); + output_buf[ARM_CPU_NAME_LENGTH] = 0; + + arg_pos = strchr (output_buf, '+'); + + /* If we found a '+' truncate the entry at that point. */ + if (arg_pos) + *arg_pos = '\0'; + + return output_buf; +} + +/* Called by the driver to rewrite a name passed to the -march + argument in preparation to be passed to the assembler. The + names passed from the command line will be in ARGV, we want + to use the right-most argument, which should be in + ARGV[ARGC - 1]. ARGC should always be greater than 0. */ + +const char * +arm_rewrite_march (int argc, const char **argv) +{ + gcc_assert (argc); + return arm_rewrite_selected_arch (argv[argc - 1]); +} + struct arm_arch_core_flag { const char *const name; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index f9e4356..d398b99 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2219,42 +2219,42 @@ extern int making_const_table; instruction. */ #define MAX_LDM_STM_OPS 4 -#define BIG_LITTLE_SPEC \ - " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" - extern const char *arm_rewrite_mcpu (int argc, const char **argv); -#define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ - { "rewrite_mcpu", arm_rewrite_mcpu }, +extern const char *arm_rewrite_march (int argc, const char **argv); +#define ASM_CPU_SPEC_FUNCTIONS \ + { "rewrite_mcpu", arm_rewrite_mcpu }, \ + { "rewrite_march", arm_rewrite_march }, -#define ASM_CPU_SPEC \ - " %{mcpu=generic-*:-march=%*;" \ - " :%{march=*:-march=%*}}" \ - BIG_LITTLE_SPEC +#define ASM_CPU_SPEC \ + " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ + " march=*:-march=%:rewrite_march(%{march=*:%*});" \ + " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ + " }" extern const char *arm_target_thumb_only (int argc, const char **argv); -#define TARGET_MODE_SPEC_FUNCTIONS \ +#define TARGET_MODE_SPEC_FUNCTIONS \ { "target_mode_check", arm_target_thumb_only }, /* -mcpu=native handling only makes sense with compiler running on an ARM chip. */ #if defined(__arm__) extern const char *host_detect_local_cpu (int argc, const char **argv); -# define EXTRA_SPEC_FUNCTIONS \ - { "local_cpu_detect", host_detect_local_cpu }, \ - BIG_LITTLE_CPU_SPEC_FUNCTIONS \ - TARGET_MODE_SPEC_FUNCTIONS - -# define MCPU_MTUNE_NATIVE_SPECS \ - " %{march=native:% Date: Fri, 16 Jun 2017 21:01:51 +0000 Subject: [arm] Don't pass -mfpu=auto through to the assembler. The assembler doesn't understand -mfpu=auto. The easiest way to handle this is to surpress this value from being passed through, while still passing through legacy values. * config/arm/elf.h (ASM_SPEC): Only pass -mfpu through to the assembler when it is not -mfpu=auto. From-SVN: r249281 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/elf.h | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1542ae3..5ea21b7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Richard Earnshaw + * config/arm/elf.h (ASM_SPEC): Only pass -mfpu through to the + assembler when it is not -mfpu=auto. + +2017-06-16 Richard Earnshaw + * config/arm/arm.h (BIG_LITTLE_SPEC): Delete macro. (ASM_REWRITE_SPEC_FUNCTIONS): New macro. (BIG_LITTLE_CPU_SPEC_FUNCTIONS): Delete macro. diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index f119b87..fcc4f3f 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -64,7 +64,7 @@ %{mapcs-*:-mapcs-%*} \ %(subtarget_asm_float_spec) \ %{mthumb-interwork:-mthumb-interwork} \ -%{mfloat-abi=*} %{mfpu=*} \ +%{mfloat-abi=*} %{!mfpu=auto: %{mfpu=*}} \ %(subtarget_extra_asm_spec)" #endif -- cgit v1.1 From 250e088bc454927486f988aecbb0ec381ca7e76e Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:02:10 +0000 Subject: [arm] Allow +opt on arbitrary cpu and architecture This is the main patch to provide the infrastructure for adding feature extensions to CPU and architecture specifications. It does not, however, add all the extensions that we intend to support (just a small number to permit some basic testing). Now, instead of having specific entries in the architecture table for variants such as armv8-a+crc, the crc extension is specified as an optional component of the armv8-a architecture entry. Similar control can be added to CPU option names. In both cases the list of permitted options is controlled by the main architecture or CPU name to prevent arbitrary cross-products of options. * config/arm/arm-cpus.in (armv8-a): Add options crc, simd crypto and nofp. (armv8-a+crc): Delete. (armv8.1-a): Add options simd, crypto and nofp. (armv8.2-a): Add options fp16, simd, crypto and nofp. (armv8.2-a+fp16): Delete. (armv8-m.main): Add option dsp. (armv8-m.main+dsp): Delete. (cortex-a8): Add fpu. Add nofp option. (cortex-a9): Add fpu. Add nofp and nosimd options. * config/arm/parsecpu.awk (gen_data): Generate option tables and link to main cpu and architecture data structures. (gen_comm_data): Only put isa attributes from the main architecture in common tables. (option): New statement for architecture and CPU entries. * arm.c (struct cpu_option): New structure. (struct processors): Add entry for options. (arm_unrecognized_feature): New function. (arm_parse_arch_cpu_name): Ignore any characters after the first '+' character. (arm_parse_arch_cpu_feature): New function. (arm_configure_build_target): Separate out any CPU and architecture features and parse separately. Don't error out if -mfpu=auto is used with only an architecture string. (arm_print_asm_arch_directives): New function. (arm_file_start): Call it. * config/arm/arm-cpu-cdata.h: Regenerated. * config/arm/arm-cpu-data.h: Likewise. * config/arm/arm-tables.opt: Likewise. From-SVN: r249282 --- gcc/ChangeLog | 32 +++++ gcc/config/arm/arm-cpu-cdata.h | 47 ++----- gcc/config/arm/arm-cpu-data.h | 297 +++++++++++++++++++++++++++++++++++------ gcc/config/arm/arm-cpus.in | 39 +++--- gcc/config/arm/arm-tables.opt | 21 +-- gcc/config/arm/arm.c | 191 +++++++++++++++++++++----- gcc/config/arm/parsecpu.awk | 110 +++++++++++++-- 7 files changed, 579 insertions(+), 158 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5ea21b7..67ebd1c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,37 @@ 2017-06-16 Richard Earnshaw + * config/arm/arm-cpus.in (armv8-a): Add options crc, simd crypto and + nofp. + (armv8-a+crc): Delete. + (armv8.1-a): Add options simd, crypto and nofp. + (armv8.2-a): Add options fp16, simd, crypto and nofp. + (armv8.2-a+fp16): Delete. + (armv8-m.main): Add option dsp. + (armv8-m.main+dsp): Delete. + (cortex-a8): Add fpu. Add nofp option. + (cortex-a9): Add fpu. Add nofp and nosimd options. + * config/arm/parsecpu.awk (gen_data): Generate option tables and + link to main cpu and architecture data structures. + (gen_comm_data): Only put isa attributes from the main architecture + in common tables. + (option): New statement for architecture and CPU entries. + * arm.c (struct cpu_option): New structure. + (struct processors): Add entry for options. + (arm_unrecognized_feature): New function. + (arm_parse_arch_cpu_name): Ignore any characters after the first + '+' character. + (arm_parse_arch_cpu_feature): New function. + (arm_configure_build_target): Separate out any CPU and architecture + features and parse separately. Don't error out if -mfpu=auto is + used with only an architecture string. + (arm_print_asm_arch_directives): New function. + (arm_file_start): Call it. + * config/arm/arm-cpu-cdata.h: Regenerated. + * config/arm/arm-cpu-data.h: Likewise. + * config/arm/arm-tables.opt: Likewise. + +2017-06-16 Richard Earnshaw + * config/arm/elf.h (ASM_SPEC): Only pass -mfpu through to the assembler when it is not -mfpu=auto. diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index b00d833..a64413d 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -577,6 +577,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a8", { ISA_ARMv7a, + ISA_VFPv3,ISA_NEON, isa_nobit }, }, @@ -584,6 +585,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a9", { ISA_ARMv7a, + ISA_VFPv3,ISA_NEON, isa_nobit }, }, @@ -693,49 +695,49 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = { "cortex-a32", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, { "cortex-a35", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, { "cortex-a53", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, { "cortex-a57", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, { "cortex-a72", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, { "cortex-a73", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, { "exynos-m1", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, @@ -749,28 +751,28 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = { "cortex-a57.cortex-a53", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, { "cortex-a72.cortex-a53", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, { "cortex-a73.cortex-a35", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, { "cortex-a73.cortex-a53", { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, isa_nobit }, }, @@ -784,7 +786,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = { "cortex-m33", { - ISA_ARMv8m_main,isa_bit_ARMv7em, + ISA_ARMv8m_main, isa_nobit }, }, @@ -978,13 +980,6 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = }, }, { - "armv8-a+crc", - { - ISA_ARMv8a,isa_bit_crc32, - isa_nobit - }, - }, - { "armv8.1-a", { ISA_ARMv8_1a, @@ -999,13 +994,6 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = }, }, { - "armv8.2-a+fp16", - { - ISA_ARMv8_2a,isa_bit_fp16, - isa_nobit - }, - }, - { "armv8-m.base", { ISA_ARMv8m_base, @@ -1020,13 +1008,6 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = }, }, { - "armv8-m.main+dsp", - { - ISA_ARMv8m_main,isa_bit_ARMv7em, - isa_nobit - }, - }, - { "iwmmxt", { ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h index 78421ad..6ec0d3b 100644 --- a/gcc/config/arm/arm-cpu-data.h +++ b/gcc/config/arm/arm-cpu-data.h @@ -20,6 +20,26 @@ License along with GCC; see the file COPYING3. If not see . */ +static const struct cpu_option cpu_opttab_cortexa8[] = { + { + "nofp", true, + { ISA_NEON,ISA_VFPv3, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa9[] = { + { + "nofp", true, + { ISA_NEON,ISA_VFPv3, isa_nobit } + }, + { + "nosimd", true, + { ISA_NEON, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + static const struct processors all_cores[] = { { @@ -31,6 +51,7 @@ static const struct processors all_cores[] = ISA_ARMv2,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -42,6 +63,7 @@ static const struct processors all_cores[] = ISA_ARMv2,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -53,6 +75,7 @@ static const struct processors all_cores[] = ISA_ARMv2,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -64,6 +87,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -75,6 +99,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -86,6 +111,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -97,6 +123,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -108,6 +135,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -119,6 +147,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -130,6 +159,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -141,6 +171,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -152,6 +183,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -163,6 +195,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -174,6 +207,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -185,6 +219,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -196,6 +231,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -207,6 +243,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -218,6 +255,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -229,6 +267,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -240,6 +279,7 @@ static const struct processors all_cores[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, &arm_slowmul_tune }, { @@ -251,6 +291,7 @@ static const struct processors all_cores[] = ISA_ARMv3m,isa_bit_mode26, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -262,6 +303,7 @@ static const struct processors all_cores[] = ISA_ARMv3m,isa_bit_mode26, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -273,6 +315,7 @@ static const struct processors all_cores[] = ISA_ARMv3m,isa_bit_mode26, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -284,6 +327,7 @@ static const struct processors all_cores[] = ISA_ARMv4,isa_bit_mode26, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -295,6 +339,7 @@ static const struct processors all_cores[] = ISA_ARMv4,isa_bit_mode26, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -306,6 +351,7 @@ static const struct processors all_cores[] = ISA_ARMv4,isa_bit_mode26, isa_nobit }, + NULL, &arm_strongarm_tune }, { @@ -317,6 +363,7 @@ static const struct processors all_cores[] = ISA_ARMv4,isa_bit_mode26, isa_nobit }, + NULL, &arm_strongarm_tune }, { @@ -328,6 +375,7 @@ static const struct processors all_cores[] = ISA_ARMv4,isa_bit_mode26, isa_nobit }, + NULL, &arm_strongarm_tune }, { @@ -339,6 +387,7 @@ static const struct processors all_cores[] = ISA_ARMv4,isa_bit_mode26, isa_nobit }, + NULL, &arm_strongarm_tune }, { @@ -350,6 +399,7 @@ static const struct processors all_cores[] = ISA_ARMv4,isa_bit_mode26, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -361,6 +411,7 @@ static const struct processors all_cores[] = ISA_ARMv4,isa_bit_mode26, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -372,6 +423,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -383,6 +435,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -394,6 +447,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -405,6 +459,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -416,6 +471,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -427,6 +483,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -438,6 +495,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -449,6 +507,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -460,6 +519,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -471,6 +531,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -482,6 +543,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -493,6 +555,7 @@ static const struct processors all_cores[] = ISA_ARMv4t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -504,6 +567,7 @@ static const struct processors all_cores[] = ISA_ARMv5t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -515,6 +579,7 @@ static const struct processors all_cores[] = ISA_ARMv5t, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -526,6 +591,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -537,6 +603,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -548,6 +615,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -559,6 +627,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -570,6 +639,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -581,6 +651,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -592,6 +663,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_fastmul_tune }, { @@ -604,6 +676,7 @@ static const struct processors all_cores[] = isa_bit_xscale, isa_nobit }, + NULL, &arm_xscale_tune }, { @@ -615,6 +688,7 @@ static const struct processors all_cores[] = ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, isa_nobit }, + NULL, &arm_xscale_tune }, { @@ -626,6 +700,7 @@ static const struct processors all_cores[] = ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, isa_nobit }, + NULL, &arm_xscale_tune }, { @@ -637,6 +712,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -648,6 +724,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -659,6 +736,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -670,6 +748,7 @@ static const struct processors all_cores[] = ISA_ARMv5te, isa_nobit }, + NULL, &arm_fa726te_tune }, { @@ -681,6 +760,7 @@ static const struct processors all_cores[] = ISA_ARMv5tej, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -692,6 +772,7 @@ static const struct processors all_cores[] = ISA_ARMv5tej, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -703,6 +784,7 @@ static const struct processors all_cores[] = ISA_ARMv6j, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -715,6 +797,7 @@ static const struct processors all_cores[] = ISA_VFPv2,ISA_FP_DBL, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -726,6 +809,7 @@ static const struct processors all_cores[] = ISA_ARMv6kz, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -738,6 +822,7 @@ static const struct processors all_cores[] = ISA_VFPv2,ISA_FP_DBL, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -749,6 +834,7 @@ static const struct processors all_cores[] = ISA_ARMv6k, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -761,6 +847,7 @@ static const struct processors all_cores[] = ISA_VFPv2,ISA_FP_DBL, isa_nobit }, + NULL, &arm_9e_tune }, { @@ -772,6 +859,7 @@ static const struct processors all_cores[] = ISA_ARMv6t2, isa_nobit }, + NULL, &arm_v6t2_tune }, { @@ -784,6 +872,7 @@ static const struct processors all_cores[] = ISA_VFPv2,ISA_FP_DBL, isa_nobit }, + NULL, &arm_v6t2_tune }, { @@ -795,6 +884,7 @@ static const struct processors all_cores[] = ISA_ARMv6m, isa_nobit }, + NULL, &arm_v6m_tune }, { @@ -806,6 +896,7 @@ static const struct processors all_cores[] = ISA_ARMv6m, isa_nobit }, + NULL, &arm_v6m_tune }, { @@ -817,6 +908,7 @@ static const struct processors all_cores[] = ISA_ARMv6m, isa_nobit }, + NULL, &arm_v6m_tune }, { @@ -828,6 +920,7 @@ static const struct processors all_cores[] = ISA_ARMv6m, isa_nobit }, + NULL, &arm_v6m_tune }, { @@ -839,6 +932,7 @@ static const struct processors all_cores[] = ISA_ARMv6m, isa_nobit }, + NULL, &arm_v6m_tune }, { @@ -850,6 +944,7 @@ static const struct processors all_cores[] = ISA_ARMv6m, isa_nobit }, + NULL, &arm_v6m_tune }, { @@ -861,6 +956,7 @@ static const struct processors all_cores[] = ISA_ARMv7a, isa_nobit }, + NULL, &arm_cortex_tune }, { @@ -872,6 +968,7 @@ static const struct processors all_cores[] = ISA_ARMv7a, isa_nobit }, + NULL, &arm_cortex_a5_tune }, { @@ -883,6 +980,7 @@ static const struct processors all_cores[] = ISA_ARMv7ve, isa_nobit }, + NULL, &arm_cortex_a7_tune }, { @@ -892,8 +990,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7a, + ISA_VFPv3,ISA_NEON, isa_nobit }, + cpu_opttab_cortexa8, &arm_cortex_a8_tune }, { @@ -903,8 +1003,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7a, + ISA_VFPv3,ISA_NEON, isa_nobit }, + cpu_opttab_cortexa9, &arm_cortex_a9_tune }, { @@ -916,6 +1018,7 @@ static const struct processors all_cores[] = ISA_ARMv7ve, isa_nobit }, + NULL, &arm_cortex_a12_tune }, { @@ -927,6 +1030,7 @@ static const struct processors all_cores[] = ISA_ARMv7ve, isa_nobit }, + NULL, &arm_cortex_a15_tune }, { @@ -938,6 +1042,7 @@ static const struct processors all_cores[] = ISA_ARMv7ve, isa_nobit }, + NULL, &arm_cortex_a12_tune }, { @@ -949,6 +1054,7 @@ static const struct processors all_cores[] = ISA_ARMv7r, isa_nobit }, + NULL, &arm_cortex_tune }, { @@ -960,6 +1066,7 @@ static const struct processors all_cores[] = ISA_ARMv7r, isa_nobit }, + NULL, &arm_cortex_tune }, { @@ -972,6 +1079,7 @@ static const struct processors all_cores[] = isa_bit_adiv, isa_nobit }, + NULL, &arm_cortex_tune }, { @@ -984,6 +1092,7 @@ static const struct processors all_cores[] = isa_bit_adiv, isa_nobit }, + NULL, &arm_cortex_tune }, { @@ -996,6 +1105,7 @@ static const struct processors all_cores[] = isa_bit_adiv, isa_nobit }, + NULL, &arm_cortex_tune }, { @@ -1008,6 +1118,7 @@ static const struct processors all_cores[] = isa_quirk_no_volatile_ce, isa_nobit }, + NULL, &arm_cortex_m7_tune }, { @@ -1019,6 +1130,7 @@ static const struct processors all_cores[] = ISA_ARMv7em, isa_nobit }, + NULL, &arm_v7m_tune }, { @@ -1031,6 +1143,7 @@ static const struct processors all_cores[] = isa_quirk_cm3_ldrd, isa_nobit }, + NULL, &arm_v7m_tune }, { @@ -1042,6 +1155,7 @@ static const struct processors all_cores[] = ISA_ARMv7a, isa_nobit }, + NULL, &arm_marvell_pj4_tune }, { @@ -1053,6 +1167,7 @@ static const struct processors all_cores[] = ISA_ARMv7ve, isa_nobit }, + NULL, &arm_cortex_a15_tune }, { @@ -1064,6 +1179,7 @@ static const struct processors all_cores[] = ISA_ARMv7ve, isa_nobit }, + NULL, &arm_cortex_a12_tune }, { @@ -1072,9 +1188,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_cortex_a35_tune }, { @@ -1083,9 +1201,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_cortex_a35_tune }, { @@ -1094,9 +1214,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_cortex_a53_tune }, { @@ -1105,9 +1227,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_cortex_a57_tune }, { @@ -1116,9 +1240,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_cortex_a57_tune }, { @@ -1127,9 +1253,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_cortex_a73_tune }, { @@ -1138,9 +1266,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_exynosm1_tune }, { @@ -1152,6 +1282,7 @@ static const struct processors all_cores[] = ISA_ARMv8a, isa_nobit }, + NULL, &arm_xgene1_tune }, { @@ -1160,9 +1291,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_cortex_a57_tune }, { @@ -1171,9 +1304,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_cortex_a57_tune }, { @@ -1182,9 +1317,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_cortex_a73_tune }, { @@ -1193,9 +1330,11 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8A", BASE_ARCH_8A, { - ISA_ARMv8a,isa_bit_crc32, + ISA_ARMv8a, + isa_bit_crc32, isa_nobit }, + NULL, &arm_cortex_a73_tune }, { @@ -1207,6 +1346,7 @@ static const struct processors all_cores[] = ISA_ARMv8m_base, isa_nobit }, + NULL, &arm_v6m_tune }, { @@ -1215,12 +1355,78 @@ static const struct processors all_cores[] = (TF_LDSCHED), "8M_MAIN", BASE_ARCH_8M_MAIN, { - ISA_ARMv8m_main,isa_bit_ARMv7em, + ISA_ARMv8m_main, + isa_bit_ARMv7em, isa_nobit }, + NULL, &arm_v7m_tune }, - {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL} + {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL, NULL} +}; + +static const struct cpu_option arch_opttab_armv8_a[] = { + { + "crc", false, + { isa_bit_crc32, isa_nobit } + }, + { + "simd", false, + { ISA_FP_ARMv8,ISA_NEON, isa_nobit } + }, + { + "crypto", false, + { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv8_1_a[] = { + { + "simd", false, + { ISA_FP_ARMv8,ISA_NEON, isa_nobit } + }, + { + "crypto", false, + { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv8_2_a[] = { + { + "fp16", false, + { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit } + }, + { + "simd", false, + { ISA_FP_ARMv8,ISA_NEON, isa_nobit } + }, + { + "crypto", false, + { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv8_m_main[] = { + { + "dsp", false, + { isa_bit_ARMv7em, isa_nobit } + }, + { NULL, false, {isa_nobit}} }; static const struct processors all_architectures[] = @@ -1233,6 +1439,7 @@ static const struct processors all_architectures[] = ISA_ARMv2,isa_bit_mode26, isa_nobit }, + NULL, NULL }, { @@ -1243,6 +1450,7 @@ static const struct processors all_architectures[] = ISA_ARMv2,isa_bit_mode26, isa_nobit }, + NULL, NULL }, { @@ -1253,6 +1461,7 @@ static const struct processors all_architectures[] = ISA_ARMv3,isa_bit_mode26, isa_nobit }, + NULL, NULL }, { @@ -1263,6 +1472,7 @@ static const struct processors all_architectures[] = ISA_ARMv3m,isa_bit_mode26, isa_nobit }, + NULL, NULL }, { @@ -1273,6 +1483,7 @@ static const struct processors all_architectures[] = ISA_ARMv4,isa_bit_mode26, isa_nobit }, + NULL, NULL }, { @@ -1283,6 +1494,7 @@ static const struct processors all_architectures[] = ISA_ARMv4t, isa_nobit }, + NULL, NULL }, { @@ -1293,6 +1505,7 @@ static const struct processors all_architectures[] = ISA_ARMv5, isa_nobit }, + NULL, NULL }, { @@ -1303,6 +1516,7 @@ static const struct processors all_architectures[] = ISA_ARMv5t, isa_nobit }, + NULL, NULL }, { @@ -1313,6 +1527,7 @@ static const struct processors all_architectures[] = ISA_ARMv5e, isa_nobit }, + NULL, NULL }, { @@ -1323,6 +1538,7 @@ static const struct processors all_architectures[] = ISA_ARMv5te, isa_nobit }, + NULL, NULL }, { @@ -1333,6 +1549,7 @@ static const struct processors all_architectures[] = ISA_ARMv5tej, isa_nobit }, + NULL, NULL }, { @@ -1343,6 +1560,7 @@ static const struct processors all_architectures[] = ISA_ARMv6, isa_nobit }, + NULL, NULL }, { @@ -1353,6 +1571,7 @@ static const struct processors all_architectures[] = ISA_ARMv6j, isa_nobit }, + NULL, NULL }, { @@ -1363,6 +1582,7 @@ static const struct processors all_architectures[] = ISA_ARMv6k, isa_nobit }, + NULL, NULL }, { @@ -1373,6 +1593,7 @@ static const struct processors all_architectures[] = ISA_ARMv6z, isa_nobit }, + NULL, NULL }, { @@ -1383,6 +1604,7 @@ static const struct processors all_architectures[] = ISA_ARMv6kz, isa_nobit }, + NULL, NULL }, { @@ -1393,6 +1615,7 @@ static const struct processors all_architectures[] = ISA_ARMv6kz, isa_nobit }, + NULL, NULL }, { @@ -1403,6 +1626,7 @@ static const struct processors all_architectures[] = ISA_ARMv6t2, isa_nobit }, + NULL, NULL }, { @@ -1413,6 +1637,7 @@ static const struct processors all_architectures[] = ISA_ARMv6m, isa_nobit }, + NULL, NULL }, { @@ -1423,6 +1648,7 @@ static const struct processors all_architectures[] = ISA_ARMv6m, isa_nobit }, + NULL, NULL }, { @@ -1433,6 +1659,7 @@ static const struct processors all_architectures[] = ISA_ARMv7, isa_nobit }, + NULL, NULL }, { @@ -1443,6 +1670,7 @@ static const struct processors all_architectures[] = ISA_ARMv7a, isa_nobit }, + NULL, NULL }, { @@ -1453,6 +1681,7 @@ static const struct processors all_architectures[] = ISA_ARMv7ve, isa_nobit }, + NULL, NULL }, { @@ -1463,6 +1692,7 @@ static const struct processors all_architectures[] = ISA_ARMv7r, isa_nobit }, + NULL, NULL }, { @@ -1473,6 +1703,7 @@ static const struct processors all_architectures[] = ISA_ARMv7m, isa_nobit }, + NULL, NULL }, { @@ -1483,6 +1714,7 @@ static const struct processors all_architectures[] = ISA_ARMv7em, isa_nobit }, + NULL, NULL }, { @@ -1493,16 +1725,7 @@ static const struct processors all_architectures[] = ISA_ARMv8a, isa_nobit }, - NULL - }, - { - "armv8-a+crc", TARGET_CPU_cortexa53, - (TF_CO_PROC), - "8A", BASE_ARCH_8A, - { - ISA_ARMv8a,isa_bit_crc32, - isa_nobit - }, + arch_opttab_armv8_a, NULL }, { @@ -1513,6 +1736,7 @@ static const struct processors all_architectures[] = ISA_ARMv8_1a, isa_nobit }, + arch_opttab_armv8_1_a, NULL }, { @@ -1523,16 +1747,7 @@ static const struct processors all_architectures[] = ISA_ARMv8_2a, isa_nobit }, - NULL - }, - { - "armv8.2-a+fp16", TARGET_CPU_cortexa53, - (TF_CO_PROC), - "8A", BASE_ARCH_8A, - { - ISA_ARMv8_2a,isa_bit_fp16, - isa_nobit - }, + arch_opttab_armv8_2_a, NULL }, { @@ -1543,6 +1758,7 @@ static const struct processors all_architectures[] = ISA_ARMv8m_base, isa_nobit }, + NULL, NULL }, { @@ -1553,16 +1769,7 @@ static const struct processors all_architectures[] = ISA_ARMv8m_main, isa_nobit }, - NULL - }, - { - "armv8-m.main+dsp", TARGET_CPU_cortexm33, - (TF_CO_PROC), - "8M_MAIN", BASE_ARCH_8M_MAIN, - { - ISA_ARMv8m_main,isa_bit_ARMv7em, - isa_nobit - }, + arch_opttab_armv8_m_main, NULL }, { @@ -1573,6 +1780,7 @@ static const struct processors all_architectures[] = ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, isa_nobit }, + NULL, NULL }, { @@ -1583,9 +1791,10 @@ static const struct processors all_architectures[] = ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, isa_nobit }, + NULL, NULL }, - {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL} + {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL, NULL} }; const struct arm_fpu_desc all_fpus[] = diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 1100f3a..6c9346c 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -237,20 +237,20 @@ begin arch armv8-a tune flags CO_PROC base 8A isa ARMv8a + option crc add bit_crc32 + option simd add FP_ARMv8 NEON + option crypto add FP_ARMv8 NEON CRYPTO + option nofp remove FP_ARMv8 NEON CRYPTO end arch armv8-a -begin arch armv8-a+crc - tune for cortex-a53 - tune flags CO_PROC - base 8A - isa ARMv8a bit_crc32 -end arch armv8-a+crc - begin arch armv8.1-a tune for cortex-a53 tune flags CO_PROC base 8A isa ARMv8_1a + option simd add FP_ARMv8 NEON + option crypto add FP_ARMv8 NEON CRYPTO + option nofp remove FP_ARMv8 NEON CRYPTO end arch armv8.1-a begin arch armv8.2-a @@ -258,15 +258,12 @@ begin arch armv8.2-a tune flags CO_PROC base 8A isa ARMv8_2a + option fp16 add bit_fp16 FP_ARMv8 NEON + option simd add FP_ARMv8 NEON + option crypto add FP_ARMv8 NEON CRYPTO + option nofp remove bit_fp16 FP_ARMv8 NEON CRYPTO end arch armv8.2-a -begin arch armv8.2-a+fp16 - tune for cortex-a53 - tune flags CO_PROC - base 8A - isa ARMv8_2a bit_fp16 -end arch armv8.2-a+fp16 - begin arch armv8-m.base tune for cortex-m23 base 8M_BASE @@ -278,15 +275,9 @@ begin arch armv8-m.main tune flags CO_PROC base 8M_MAIN isa ARMv8m_main + option dsp add bit_ARMv7em end arch armv8-m.main -begin arch armv8-m.main+dsp - tune for cortex-m33 - tune flags CO_PROC - base 8M_MAIN - isa ARMv8m_main bit_ARMv7em -end arch armv8-m.main+dsp - begin arch iwmmxt tune for iwmmxt tune flags LDSCHED STRONG XSCALE @@ -310,6 +301,7 @@ end arch iwmmxt2 # architecture # [fpu ] # [isa ] +# [option add|remove ]* # [costs ] # end cpu # @@ -847,6 +839,8 @@ begin cpu cortex-a8 cname cortexa8 tune flags LDSCHED architecture armv7-a + fpu neon-vfpv3 + option nofp remove NEON VFPv3 costs cortex_a8 end cpu cortex-a8 @@ -854,6 +848,9 @@ begin cpu cortex-a9 cname cortexa9 tune flags LDSCHED architecture armv7-a + fpu neon-vfpv3 + option nofp remove NEON VFPv3 + option nosimd remove NEON costs cortex_a9 end cpu cortex-a9 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index cb45e09..0f50c64 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -434,31 +434,22 @@ EnumValue Enum(arm_arch) String(armv8-a) Value(26) EnumValue -Enum(arm_arch) String(armv8-a+crc) Value(27) +Enum(arm_arch) String(armv8.1-a) Value(27) EnumValue -Enum(arm_arch) String(armv8.1-a) Value(28) +Enum(arm_arch) String(armv8.2-a) Value(28) EnumValue -Enum(arm_arch) String(armv8.2-a) Value(29) +Enum(arm_arch) String(armv8-m.base) Value(29) EnumValue -Enum(arm_arch) String(armv8.2-a+fp16) Value(30) +Enum(arm_arch) String(armv8-m.main) Value(30) EnumValue -Enum(arm_arch) String(armv8-m.base) Value(31) +Enum(arm_arch) String(iwmmxt) Value(31) EnumValue -Enum(arm_arch) String(armv8-m.main) Value(32) - -EnumValue -Enum(arm_arch) String(armv8-m.main+dsp) Value(33) - -EnumValue -Enum(arm_arch) String(iwmmxt) Value(34) - -EnumValue -Enum(arm_arch) String(iwmmxt2) Value(35) +Enum(arm_arch) String(iwmmxt2) Value(32) Enum Name(arm_fpu) Type(enum fpu_type) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 2502eb8..f35a1c2 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -975,6 +975,13 @@ int arm_regs_in_sequence[] = /* Initialization code. */ +struct cpu_option +{ + const char *const name; + bool remove; + const enum isa_feature isa_bits[isa_num_bits]; +}; + struct processors { const char *const name; @@ -982,7 +989,8 @@ struct processors unsigned int tune_flags; const char *arch; enum base_architecture base_arch; - enum isa_feature isa_bits[isa_num_bits]; + const enum isa_feature isa_bits[isa_num_bits]; + const struct cpu_option* const opttab; const struct tune_params *const tune; }; @@ -3068,9 +3076,13 @@ arm_parse_arch_cpu_name (const struct processors *list, const char *optname, const char *target) { const struct processors *entry; + const char *end = strchr (target, '+'); + size_t len = end ? end - target : strlen (target); + for (entry = list; entry->name != NULL; entry++) { - if (streq (entry->name, target)) + if (strncmp (entry->name, target, len) == 0 + && entry->name[len] == '\0') return entry; } @@ -3079,6 +3091,92 @@ arm_parse_arch_cpu_name (const struct processors *list, const char *optname, return NULL; } +/* OPT isn't a recognized feature. Print a suitable error message and + suggest a possible value. Always print the list of permitted + values. */ +static void +arm_unrecognized_feature (const char *opt, size_t len, + const struct processors *target) +{ + char *this_opt = XALLOCAVEC (char, len+1); + auto_vec candidates; + + strncpy (this_opt, opt, len); + this_opt[len] = 0; + + error_at (input_location, "%qs does not support feature %qs", target->name, + this_opt); + for (const cpu_option *list = target->opttab; list->name != NULL; list++) + candidates.safe_push (list->name); + + char *s; + const char *hint = candidates_list_and_hint (this_opt, s, candidates); + + if (hint) + inform (input_location, "valid feature names are: %s; did you mean %qs?", + s, hint); + else + inform (input_location, "valid feature names are: %s", s); + + XDELETEVEC (s); +} + +/* Parse any feature extensions to add to (or remove from) the + permitted ISA selection. */ +static void +arm_parse_arch_cpu_features (sbitmap isa, const struct processors *target, + const char *opts_in) +{ + const char *opts = opts_in; + + if (!opts) + return; + + if (!target->opttab) + { + error_at (input_location, "%s does not take any feature options", + target->name); + return; + } + + while (opts) + { + gcc_assert (*opts == '+'); + const struct cpu_option *entry; + const char *end = strchr (++opts, '+'); + size_t len = end ? end - opts : strlen (opts); + bool matched = false; + + for (entry = target->opttab; !matched && entry->name != NULL; entry++) + { + if (strncmp (entry->name, opts, len) == 0 + && entry->name[len] == '\0') + { + if (isa) + { + const enum isa_feature *f = entry->isa_bits; + if (entry->remove) + { + while (*f != isa_nobit) + bitmap_clear_bit (isa, *(f++)); + } + else + { + while (*f != isa_nobit) + bitmap_set_bit (isa, *(f++)); + } + } + matched = true; + } + } + + if (!matched) + arm_unrecognized_feature (opts, len, target); + + opts = end; + } +} + static sbitmap isa_all_fpubits; static sbitmap isa_quirkbits; @@ -3095,35 +3193,50 @@ arm_configure_build_target (struct arm_build_target *target, const struct processors *arm_selected_arch = NULL; const struct processors *arm_selected_cpu = NULL; const struct arm_fpu_desc *arm_selected_fpu = NULL; + const char *tune_opts = NULL; + const char *arch_opts = NULL; + const char *cpu_opts = NULL; bitmap_clear (target->isa); target->core_name = NULL; target->arch_name = NULL; if (opts_set->x_arm_arch_string) - arm_selected_arch = arm_parse_arch_cpu_name (all_architectures, - "-march", - opts->x_arm_arch_string); + { + arm_selected_arch = arm_parse_arch_cpu_name (all_architectures, + "-march", + opts->x_arm_arch_string); + arch_opts = strchr (opts->x_arm_arch_string, '+'); + } + if (opts_set->x_arm_cpu_string) { arm_selected_cpu = arm_parse_arch_cpu_name (all_cores, "-mcpu", opts->x_arm_cpu_string); + cpu_opts = strchr (opts->x_arm_cpu_string, '+'); arm_selected_tune = arm_selected_cpu; + /* If taking the tuning from -mcpu, we don't need to rescan the + options for tuning. */ } if (opts_set->x_arm_tune_string) - arm_selected_tune = arm_parse_arch_cpu_name (all_cores, "-mtune", - opts->x_arm_tune_string); + { + arm_selected_tune = arm_parse_arch_cpu_name (all_cores, "-mtune", + opts->x_arm_tune_string); + tune_opts = strchr (opts->x_arm_tune_string, '+'); + } if (arm_selected_arch) { arm_initialize_isa (target->isa, arm_selected_arch->isa_bits); + arm_parse_arch_cpu_features (target->isa, arm_selected_arch, arch_opts); if (arm_selected_cpu) { auto_sbitmap cpu_isa (isa_num_bits); arm_initialize_isa (cpu_isa, arm_selected_cpu->isa_bits); + arm_parse_arch_cpu_features (cpu_isa, arm_selected_cpu, cpu_opts); bitmap_xor (cpu_isa, cpu_isa, target->isa); /* Ignore any bits that are quirk bits. */ bitmap_and_compl (cpu_isa, cpu_isa, isa_quirkbits); @@ -3163,6 +3276,7 @@ arm_configure_build_target (struct arm_build_target *target, { target->core_name = arm_selected_cpu->name; arm_initialize_isa (target->isa, arm_selected_cpu->isa_bits); + arm_parse_arch_cpu_features (target->isa, arm_selected_cpu, cpu_opts); } /* If the user did not specify a processor, choose one for them. */ else @@ -3283,14 +3397,12 @@ arm_configure_build_target (struct arm_build_target *target, bitmap_and_compl (target->isa, target->isa, isa_all_fpubits); bitmap_ior (target->isa, target->isa, fpu_bits); } - else if (target->core_name == NULL) - /* To support this we need to be able to parse FPU feature options - from the architecture string. */ - sorry ("-mfpu=auto not currently supported without an explicit CPU."); /* The selected cpu may be an architecture, so lookup tuning by core ID. */ if (!arm_selected_tune) arm_selected_tune = &all_cores[arm_selected_cpu->core]; + else /* Validate the features passed to -mtune. */ + arm_parse_arch_cpu_features (NULL, arm_selected_tune, tune_opts); /* Finish initializing the target structure. */ target->arch_pp_name = arm_selected_cpu->arch; @@ -26165,6 +26277,39 @@ arm_print_tune_info (void) (int) current_tune->sched_autopref); } +/* Print .arch and .arch_extension directives corresponding to the + current architecture configuration. */ +static void +arm_print_asm_arch_directives () +{ + const struct processors *arch + = arm_parse_arch_cpu_name (all_architectures, "-march", + arm_active_target.arch_name); + auto_sbitmap opt_bits (isa_num_bits); + + gcc_assert (arch); + + asm_fprintf (asm_out_file, "\t.arch %s\n", arm_active_target.arch_name); + if (!arch->opttab) + return; + + for (const struct cpu_option *opt = arch->opttab; opt->name != NULL; opt++) + { + if (!opt->remove) + { + arm_initialize_isa (opt_bits, opt->isa_bits); + + /* If every feature bit of this option is set in the target + ISA specification, print out the option name. However, + don't print anything if all the bits are part of the + FPU specification. */ + if (bitmap_subset_p (opt_bits, arm_active_target.isa) + && !bitmap_subset_p (opt_bits, isa_all_fpubits)) + asm_fprintf (asm_out_file, "\t.arch_extension %s\n", opt->name); + } + } +} + static void arm_file_start (void) { @@ -26179,7 +26324,7 @@ arm_file_start (void) assembler would not need to know about all new CPU names as they are added. */ if (!arm_active_target.core_name) - { + { /* armv7ve doesn't support any extensions. */ if (strcmp (arm_active_target.arch_name, "armv7ve") == 0) { @@ -26192,24 +26337,8 @@ arm_file_start (void) asm_fprintf (asm_out_file, "\t.arch_extension mp\n"); } else - { - const char* pos = strchr (arm_active_target.arch_name, '+'); - if (pos) - { - char buf[32]; - gcc_assert (strlen (arm_active_target.arch_name) - <= sizeof (buf) / sizeof (*pos)); - strncpy (buf, arm_active_target.arch_name, - (pos - arm_active_target.arch_name) * sizeof (*pos)); - buf[pos - arm_active_target.arch_name] = '\0'; - asm_fprintf (asm_out_file, "\t.arch %s\n", buf); - asm_fprintf (asm_out_file, "\t.arch_extension %s\n", pos + 1); - } - else - asm_fprintf (asm_out_file, "\t.arch %s\n", - arm_active_target.arch_name); - } - } + arm_print_asm_arch_directives (); + } else if (strncmp (arm_active_target.core_name, "generic", 7) == 0) asm_fprintf (asm_out_file, "\t.arch %s\n", arm_active_target.core_name + 8); @@ -26233,7 +26362,7 @@ arm_file_start (void) } /* Some of these attributes only apply when the corresponding features - are used. However we don't have any easy way of figuring this out. + are used. However we don't have any easy way of figuring this out. Conservatively record the setting that would have been used. */ if (flag_rounding_math) diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index dac11a0..c95d922 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -117,11 +117,28 @@ function gen_headers () { function gen_data () { boilerplate("C") + ncpus = split (cpu_list, cpus) + + for (n = 1; n <= ncpus; n++) { + if (cpus[n] in cpu_opts) { + print "static const struct cpu_option cpu_opttab_" \ + cpu_cnames[cpus[n]] "[] = {" + nopts = split (cpu_opts[cpus[n]], opts) + for (opt = 1; opt <= nopts; opt++) { + print " {" + print " \"" opts[opt] "\", " \ + cpu_opt_remove[cpus[n],opts[opt]] "," + print " { " cpu_opt_isa[cpus[n],opts[opt]] ", isa_nobit }" + print " }," + } + print " { NULL, false, {isa_nobit}}" + print "};\n" + } + } + print "static const struct processors all_cores[] =" print "{" - ncpus = split (cpu_list, cpus) - for (n = 1; n <= ncpus; n++) { print " {" print " \"" cpus[n] "\"," @@ -137,30 +154,60 @@ function gen_data () { if (cpus[n] in cpu_tune_flags) { print " (" cpu_tune_flags[cpus[n]] ")," } else print " 0," - if (! (cpu_arch[cpus[n]] in arch_isa)) { - fatal("unknown arch " cpu_arch[cpus[n]] " for cpu " cpus[n]) + nfeats = split (cpu_arch[cpus[n]], feats, "+") + if (! (feats[1] in arch_isa)) { + fatal("unknown arch " feats[1] " for cpu " cpus[n]) } - print " \"" arch_base[cpu_arch[cpus[n]]] "\", BASE_ARCH_" \ - arch_base[cpu_arch[cpus[n]]] "," + print " \"" arch_base[feats[1]] "\", BASE_ARCH_" \ + arch_base[feats[1]] "," print " {" - print " " arch_isa[cpu_arch[cpus[n]]] "," + print " " arch_isa[feats[1]] "," + for (m = 2; m <= nfeats; m++) { + if (! ((feats[1], feats[m]) in arch_opt_isa)) { + fatal("unknown feature " feats[m] " for architecture " feats[1]) + } + if (arch_opt_remove[feats[1],feats[m]] == "true") { + fatal("cannot remove features from architecture specs") + } + print " " arch_opt_isa[feats[1],feats[m]] "," + } if (cpus[n] in cpu_fpu) print " " fpu_isa[cpu_fpu[cpus[n]]] "," if (cpus[n] in cpu_isa) print " " cpu_isa[cpus[n]] "," print " isa_nobit" print " }," + if (cpus[n] in cpu_opts) { + print " cpu_opttab_" cpu_cnames[cpus[n]] "," + } else print " NULL," print " &arm_" cpu_cost[cpus[n]] "_tune" print " }," } print " {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0," \ - " {isa_nobit}, NULL}" + " {isa_nobit}, NULL, NULL}" print "};\n" + narchs = split (arch_list, archs) + + for (n = 1; n <= narchs; n++) { + if (archs[n] in arch_opts) { + print "static const struct cpu_option arch_opttab_" \ + arch_cnames[archs[n]] "[] = {" + nopts = split (arch_opts[archs[n]], opts) + for (opt = 1; opt <= nopts; opt++) { + print " {" + print " \"" opts[opt] "\", " \ + arch_opt_remove[archs[n],opts[opt]] "," + print " { " arch_opt_isa[archs[n],opts[opt]] ", isa_nobit }" + print " }," + } + print " { NULL, false, {isa_nobit}}" + print "};\n" + } + } + print "static const struct processors all_architectures[] =" print "{" - narchs = split (arch_list, archs) - for (n = 1; n <= narchs; n++) { print " {" if (! (arch_tune_for[archs[n]] in cpu_cnames)) { @@ -178,12 +225,15 @@ function gen_data () { print " " arch_isa[archs[n]] "," print " isa_nobit" print " }," + if (archs[n] in arch_opts) { + print " arch_opttab_" arch_cnames[archs[n]] "," + } else print " NULL," print " NULL" print " }," } print " {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0," \ - " {isa_nobit}, NULL}" + " {isa_nobit}, NULL, NULL}" print "};\n" print "const struct arm_fpu_desc all_fpus[] =" @@ -215,11 +265,15 @@ function gen_comm_data () { for (n = 1; n <= ncpus; n++) { print " {" print " \"" cpus[n] "\"," - if (! (cpu_arch[cpus[n]] in arch_isa)) { - fatal("unknown arch " cpu_arch[cpus[n]] " for cpu " cpus[n]) + # Just truncate the architecture name at the beginning of the + # extensions. We don't need any of those here (at present). + arch_name = cpu_arch[cpus[n]]; + sub("+.*", "", arch_name) + if (! (arch_name in arch_isa)) { + fatal("unknown arch " arch_name " for cpu " cpus[n]) } print " {" - print " " arch_isa[cpu_arch[cpus[n]]] "," + print " " arch_isa[arch_name] "," if (cpus[n] in cpu_fpu) print " " fpu_isa[cpu_fpu[cpus[n]]] "," if (cpus[n] in cpu_isa) print " " cpu_isa[cpus[n]] "," print " isa_nobit" @@ -382,6 +436,8 @@ BEGIN { fatal("arch definition lacks an \"isa\" statement") } arch_list = arch_list " " arch_name + arch_cnames[arch_name] = arch_name + gsub(/[-+.]/, "_", arch_cnames[arch_name]) arch_name = "" parse_ok = 1 } @@ -453,6 +509,32 @@ BEGIN { parse_ok = 1 } +/^[ ]*option / { + name=$2 + if ($3 == "add") { + remove = "false" + } else if ($3 == "remove") { + remove = "true" + } else fatal("syntax: option add|remove isa-list") + flags="" + flag_count = NF + for (n = 4; n <= flag_count; n++) { + if (n == 4) { + flags = isa_pfx($n) + } else flags = flags "," isa_pfx($n) + } + if (cpu_name != "") { + cpu_opts[cpu_name] = cpu_opts[cpu_name] " " name + cpu_opt_remove[cpu_name,name] = remove + cpu_opt_isa[cpu_name,name] = flags + } else if (arch_name != "") { + arch_opts[arch_name] = arch_opts[arch_name] " " name + arch_opt_remove[arch_name,name] = remove + arch_opt_isa[arch_name,name] = flags + } else fatal("\"option\" outside of cpu or arch block") + parse_ok = 1 +} + /^[ ]*costs / { if (cpu_name == "") fatal("\"costs\" outside of cpu block") cpu_cost[cpu_name] = $2 -- cgit v1.1 From 76d7d5334991a5646026e5aa8c3e7d23629f383a Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:02:19 +0000 Subject: [arm] Add architectural options This patch adds the currently supported architecture options to the individual architectures. For floating point and SIMD we only permit variants that the relevant versions of the architecture permit. We also add short-hand versions (+fp, +simd, etc) that allows the user to describe using floating point without having to know the precise version of the floating point sub-architecture that that architecture requires. In a small number of cases we need to provide more precise versions of the floating point architecture. In those cases we permit traditional -mfpu style names in the architecture description. * arm-cpus.in (armv5e): Add options fp, vfpv2 and nofp. (armv5te, armv5tej): Likewise. (armv6, armv6j, armv6k, armv6z, armv6kz, armv6zk, armv6t2): Likewise. (armv7): Add options fp and vfpv3-d16. (armv7-a): Add options fp, simd, vfpv3, vfpv3-d16, vfpv3-d16-fp16, vfpv3-fp16, vfpv4, vfpv4-d16, neon, neon-vfpv3, neon-fp16, neon-vfpv4, nofp and nosimd. (armv7ve): Likewise. (armv7-r): Add options fp, fp.sp, idiv, nofp and noidiv. (armv7e-m): Add options fp, fpv5, fp.dp and nofp. (armv8-a): Add nocrypto option. (armv8.1-a, armv8.2-a): Likewise. (armv8-m.main): add options fp, fp.dp and nofp. From-SVN: r249283 --- gcc/ChangeLog | 16 ++ gcc/config/arm/arm-cpu-data.h | 390 ++++++++++++++++++++++++++++++++++++++++-- gcc/config/arm/arm-cpus.in | 83 +++++++++ 3 files changed, 474 insertions(+), 15 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 67ebd1c..2878289 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,21 @@ 2017-06-16 Richard Earnshaw + * arm-cpus.in (armv5e): Add options fp, vfpv2 and nofp. + (armv5te, armv5tej): Likewise. + (armv6, armv6j, armv6k, armv6z, armv6kz, armv6zk, armv6t2): Likewise. + (armv7): Add options fp and vfpv3-d16. + (armv7-a): Add options fp, simd, vfpv3, vfpv3-d16, vfpv3-d16-fp16, + vfpv3-fp16, vfpv4, vfpv4-d16, neon, neon-vfpv3, neon-fp16, neon-vfpv4, + nofp and nosimd. + (armv7ve): Likewise. + (armv7-r): Add options fp, fp.sp, idiv, nofp and noidiv. + (armv7e-m): Add options fp, fpv5, fp.dp and nofp. + (armv8-a): Add nocrypto option. + (armv8.1-a, armv8.2-a): Likewise. + (armv8-m.main): add options fp, fp.dp and nofp. + +2017-06-16 Richard Earnshaw + * config/arm/arm-cpus.in (armv8-a): Add options crc, simd crypto and nofp. (armv8-a+crc): Delete. diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h index 6ec0d3b..2a65ec6 100644 --- a/gcc/config/arm/arm-cpu-data.h +++ b/gcc/config/arm/arm-cpu-data.h @@ -1365,6 +1365,342 @@ static const struct processors all_cores[] = {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL, NULL} }; +static const struct cpu_option arch_opttab_armv5e[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv5te[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv5tej[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv6[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv6j[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv6k[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv6z[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv6kz[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv6zk[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv6t2[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv7[] = { + { + "fp", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv7_a[] = { + { + "fp", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "simd", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "vfpv3", false, + { ISA_VFPv3,ISA_FP_D32, isa_nobit } + }, + { + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv3-d16-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv3-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv4", false, + { ISA_VFPv4,ISA_FP_D32, isa_nobit } + }, + { + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { + "neon", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-vfpv3", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-fp16", false, + { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } + }, + { + "neon-vfpv4", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "nosimd", true, + { ISA_NEON, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv7ve[] = { + { + "fp", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { + "simd", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "vfpv3", false, + { ISA_VFPv3,ISA_FP_D32, isa_nobit } + }, + { + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv3-d16-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv3-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv4", false, + { ISA_VFPv4,ISA_FP_D32, isa_nobit } + }, + { + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { + "neon", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-vfpv3", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-fp16", false, + { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } + }, + { + "neon-vfpv4", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "nosimd", true, + { ISA_NEON, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv7_r[] = { + { + "fp", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "fp.sp", false, + { ISA_VFPv3, isa_nobit } + }, + { + "idiv", false, + { isa_bit_adiv, isa_nobit } + }, + { + "nofp", true, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "noidiv", true, + { isa_bit_adiv, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option arch_opttab_armv7e_m[] = { + { + "fp", false, + { ISA_VFPv4, isa_nobit } + }, + { + "fpv5", false, + { ISA_FPv5, isa_nobit } + }, + { + "fp.dp", false, + { ISA_FPv5,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_FPv5,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + static const struct cpu_option arch_opttab_armv8_a[] = { { "crc", false, @@ -1382,6 +1718,10 @@ static const struct cpu_option arch_opttab_armv8_a[] = { "nofp", true, { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } }, + { + "nocrypto", true, + { ISA_CRYPTO, isa_nobit } + }, { NULL, false, {isa_nobit}} }; @@ -1398,6 +1738,10 @@ static const struct cpu_option arch_opttab_armv8_1_a[] = { "nofp", true, { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } }, + { + "nocrypto", true, + { ISA_CRYPTO, isa_nobit } + }, { NULL, false, {isa_nobit}} }; @@ -1418,6 +1762,10 @@ static const struct cpu_option arch_opttab_armv8_2_a[] = { "nofp", true, { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } }, + { + "nocrypto", true, + { ISA_CRYPTO, isa_nobit } + }, { NULL, false, {isa_nobit}} }; @@ -1426,6 +1774,18 @@ static const struct cpu_option arch_opttab_armv8_m_main[] = { "dsp", false, { isa_bit_ARMv7em, isa_nobit } }, + { + "fp", false, + { ISA_FPv5, isa_nobit } + }, + { + "fp.dp", false, + { ISA_FPv5,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_FPv5, isa_nobit } + }, { NULL, false, {isa_nobit}} }; @@ -1527,7 +1887,7 @@ static const struct processors all_architectures[] = ISA_ARMv5e, isa_nobit }, - NULL, + arch_opttab_armv5e, NULL }, { @@ -1538,7 +1898,7 @@ static const struct processors all_architectures[] = ISA_ARMv5te, isa_nobit }, - NULL, + arch_opttab_armv5te, NULL }, { @@ -1549,7 +1909,7 @@ static const struct processors all_architectures[] = ISA_ARMv5tej, isa_nobit }, - NULL, + arch_opttab_armv5tej, NULL }, { @@ -1560,7 +1920,7 @@ static const struct processors all_architectures[] = ISA_ARMv6, isa_nobit }, - NULL, + arch_opttab_armv6, NULL }, { @@ -1571,7 +1931,7 @@ static const struct processors all_architectures[] = ISA_ARMv6j, isa_nobit }, - NULL, + arch_opttab_armv6j, NULL }, { @@ -1582,7 +1942,7 @@ static const struct processors all_architectures[] = ISA_ARMv6k, isa_nobit }, - NULL, + arch_opttab_armv6k, NULL }, { @@ -1593,7 +1953,7 @@ static const struct processors all_architectures[] = ISA_ARMv6z, isa_nobit }, - NULL, + arch_opttab_armv6z, NULL }, { @@ -1604,7 +1964,7 @@ static const struct processors all_architectures[] = ISA_ARMv6kz, isa_nobit }, - NULL, + arch_opttab_armv6zk, NULL }, { @@ -1615,7 +1975,7 @@ static const struct processors all_architectures[] = ISA_ARMv6kz, isa_nobit }, - NULL, + arch_opttab_armv6kz, NULL }, { @@ -1626,7 +1986,7 @@ static const struct processors all_architectures[] = ISA_ARMv6t2, isa_nobit }, - NULL, + arch_opttab_armv6t2, NULL }, { @@ -1659,7 +2019,7 @@ static const struct processors all_architectures[] = ISA_ARMv7, isa_nobit }, - NULL, + arch_opttab_armv7, NULL }, { @@ -1670,7 +2030,7 @@ static const struct processors all_architectures[] = ISA_ARMv7a, isa_nobit }, - NULL, + arch_opttab_armv7_a, NULL }, { @@ -1681,7 +2041,7 @@ static const struct processors all_architectures[] = ISA_ARMv7ve, isa_nobit }, - NULL, + arch_opttab_armv7ve, NULL }, { @@ -1692,7 +2052,7 @@ static const struct processors all_architectures[] = ISA_ARMv7r, isa_nobit }, - NULL, + arch_opttab_armv7_r, NULL }, { @@ -1714,7 +2074,7 @@ static const struct processors all_architectures[] = ISA_ARMv7em, isa_nobit }, - NULL, + arch_opttab_armv7e_m, NULL }, { diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 6c9346c..7a1fede 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -113,6 +113,9 @@ begin arch armv5e tune flags CO_PROC base 5E isa ARMv5e + option fp add VFPv2 FP_DBL + option vfpv2 add VFPv2 FP_DBL + option nofp remove VFPv2 FP_DBL end arch armv5e begin arch armv5te @@ -120,6 +123,9 @@ begin arch armv5te tune flags CO_PROC base 5TE isa ARMv5te + option fp add VFPv2 FP_DBL + option vfpv2 add VFPv2 FP_DBL + option nofp remove VFPv2 FP_DBL end arch armv5te begin arch armv5tej @@ -127,6 +133,9 @@ begin arch armv5tej tune flags CO_PROC base 5TEJ isa ARMv5tej + option fp add VFPv2 FP_DBL + option vfpv2 add VFPv2 FP_DBL + option nofp remove VFPv2 FP_DBL end arch armv5tej begin arch armv6 @@ -134,6 +143,9 @@ begin arch armv6 tune flags CO_PROC base 6 isa ARMv6 + option fp add VFPv2 FP_DBL + option vfpv2 add VFPv2 FP_DBL + option nofp remove VFPv2 FP_DBL end arch armv6 begin arch armv6j @@ -141,6 +153,9 @@ begin arch armv6j tune flags CO_PROC base 6J isa ARMv6j + option fp add VFPv2 FP_DBL + option vfpv2 add VFPv2 FP_DBL + option nofp remove VFPv2 FP_DBL end arch armv6j begin arch armv6k @@ -148,6 +163,9 @@ begin arch armv6k tune flags CO_PROC base 6K isa ARMv6k + option fp add VFPv2 FP_DBL + option vfpv2 add VFPv2 FP_DBL + option nofp remove VFPv2 FP_DBL end arch armv6k begin arch armv6z @@ -155,6 +173,9 @@ begin arch armv6z tune flags CO_PROC base 6Z isa ARMv6z + option fp add VFPv2 FP_DBL + option vfpv2 add VFPv2 FP_DBL + option nofp remove VFPv2 FP_DBL end arch armv6z begin arch armv6kz @@ -162,6 +183,9 @@ begin arch armv6kz tune flags CO_PROC base 6KZ isa ARMv6kz + option fp add VFPv2 FP_DBL + option vfpv2 add VFPv2 FP_DBL + option nofp remove VFPv2 FP_DBL end arch armv6kz begin arch armv6zk @@ -169,6 +193,9 @@ begin arch armv6zk tune flags CO_PROC base 6KZ isa ARMv6kz + option fp add VFPv2 FP_DBL + option vfpv2 add VFPv2 FP_DBL + option nofp remove VFPv2 FP_DBL end arch armv6zk begin arch armv6t2 @@ -176,6 +203,9 @@ begin arch armv6t2 tune flags CO_PROC base 6T2 isa ARMv6t2 + option fp add VFPv2 FP_DBL + option vfpv2 add VFPv2 FP_DBL + option nofp remove VFPv2 FP_DBL end arch armv6t2 begin arch armv6-m @@ -195,6 +225,9 @@ begin arch armv7 tune flags CO_PROC base 7 isa ARMv7 +# fp => VFPv3-d16 (only useful for the A+R profile subset). + option fp add VFPv3 FP_DBL + option vfpv3-d16 add VFPv3 FP_DBL end arch armv7 begin arch armv7-a @@ -202,6 +235,21 @@ begin arch armv7-a tune flags CO_PROC base 7A isa ARMv7a +# fp => VFPv3-d16, simd => neon-vfpv3 + option fp add VFPv3 FP_DBL + option simd add VFPv3 NEON + option vfpv3 add VFPv3 FP_D32 + option vfpv3-d16 add VFPv3 FP_DBL + option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv + option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv + option vfpv4 add VFPv4 FP_D32 + option vfpv4-d16 add VFPv4 FP_DBL + option neon add VFPv3 NEON + option neon-vfpv3 add VFPv3 NEON + option neon-fp16 add VFPv3 NEON bit_fp16conv + option neon-vfpv4 add VFPv4 NEON + option nofp remove VFPv4 NEON + option nosimd remove NEON end arch armv7-a begin arch armv7ve @@ -209,6 +257,21 @@ begin arch armv7ve tune flags CO_PROC base 7A isa ARMv7ve +# fp => VFPv4-d16, simd => neon-vfpv4 + option fp add VFPv4 FP_DBL + option simd add VFPv4 NEON + option vfpv3 add VFPv3 FP_D32 + option vfpv3-d16 add VFPv3 FP_DBL + option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv + option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv + option vfpv4 add VFPv4 FP_D32 + option vfpv4-d16 add VFPv4 FP_DBL + option neon add VFPv3 NEON + option neon-vfpv3 add VFPv3 NEON + option neon-fp16 add VFPv3 NEON bit_fp16conv + option neon-vfpv4 add VFPv4 NEON + option nofp remove VFPv4 NEON + option nosimd remove NEON end arch armv7ve begin arch armv7-r @@ -216,6 +279,12 @@ begin arch armv7-r tune flags CO_PROC base 7R isa ARMv7r +# ARMv7-r uses VFPv3-d16 + option fp add VFPv3 FP_DBL + option fp.sp add VFPv3 + option idiv add bit_adiv + option nofp remove VFPv3 FP_DBL + option noidiv remove bit_adiv end arch armv7-r begin arch armv7-m @@ -223,6 +292,8 @@ begin arch armv7-m tune flags CO_PROC base 7M isa ARMv7m +# In theory FP is permitted in v7-m, but in practice no implementations exist. +# leave it out for now. end arch armv7-m begin arch armv7e-m @@ -230,6 +301,11 @@ begin arch armv7e-m tune flags CO_PROC base 7EM isa ARMv7em +# fp => VFPv4-sp-d16; fpv5 => FPv5-sp-d16; fp.dp => FPv5-d16 + option fp add VFPv4 + option fpv5 add FPv5 + option fp.dp add FPv5 FP_DBL + option nofp remove FPv5 FP_DBL end arch armv7e-m begin arch armv8-a @@ -241,6 +317,7 @@ begin arch armv8-a option simd add FP_ARMv8 NEON option crypto add FP_ARMv8 NEON CRYPTO option nofp remove FP_ARMv8 NEON CRYPTO + option nocrypto remove CRYPTO end arch armv8-a begin arch armv8.1-a @@ -251,6 +328,7 @@ begin arch armv8.1-a option simd add FP_ARMv8 NEON option crypto add FP_ARMv8 NEON CRYPTO option nofp remove FP_ARMv8 NEON CRYPTO + option nocrypto remove CRYPTO end arch armv8.1-a begin arch armv8.2-a @@ -262,6 +340,7 @@ begin arch armv8.2-a option simd add FP_ARMv8 NEON option crypto add FP_ARMv8 NEON CRYPTO option nofp remove bit_fp16 FP_ARMv8 NEON CRYPTO + option nocrypto remove CRYPTO end arch armv8.2-a begin arch armv8-m.base @@ -276,6 +355,10 @@ begin arch armv8-m.main base 8M_MAIN isa ARMv8m_main option dsp add bit_ARMv7em +# fp => FPv5-sp-d16; fp.dp => FPv5-d16 + option fp add FPv5 + option fp.dp add FPv5 FP_DBL + option nofp remove FPv5 end arch armv8-m.main begin arch iwmmxt -- cgit v1.1 From e87afe54b86c478ae63569e51e7abb67d3fe3fce Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:02:52 +0000 Subject: [arm] Add default FPUs for CPUs. This patch adds the default CPUs for each cpu and provides options for changing the FPU variant when appropriate. It turns out to be easier to describe removal options using general mask operations that disable a concept rather than specific bits. Sometimes the helper definitions for enabling a feature are not excat duals when it comes to disabling them - for example, +simd forcibly turns on double-precision capabilities in the FPU, but disabling just simd (+nosimd) should not forcibly disable that. * config/arm/arm-isa.h (ISA_ALL_FPU_INTERNAL): Renamed from ISA_ALL_FPU. (ISA_ALL_CRYPTO): New macro. (ISA_ALL_SIMD): New macro (ISA_ALL_FP): New macro. * config/arm/arm.c (fpu_bitlist): Update initializer. * config/arm/arm-cpus.in: Use new ISA_ALL macros to disable crypto, simd or fp. (arm9e): Add fpu. Add option for nofp (arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e): Likewise. (arm926ej-s, arm1026ej-s): Likewise. (generic-armv7-a): Add fpu. Add options for simd, vfpv3, vfpv3-d16, vfpv3-fp16, vfpv3-d16-fp16, vfpv4, vfpv4-d16, neon, neon-vfp3, neon-fp16, neon-vfpv4, nofp and nosimd. (cortex-a5, cortex-a7): Add fpu. Add options for nosimd and nofp. (cortex-a8): Add fpu. Add option for nofp. (cortex-a9): Add fpu. Add options for nosimd and nofp. (cortex-a12, cortex-a15, cortex-a17): Add fpu. Add option for nofp. (cortex-r4f): Add fpu. (cortex-r5): Add fpu. Add options for nofp.dp and nofp. (cortex-r7): Use idiv option from architecture. Add fpu. Add option for nofp. (cortex-r8): Likewise. (cortex-m4): Add fpu. Add option for nofp. (cortex-a15.cortex-a7): Add fpu. Add option for nofp. (cortex-a17.cortex-a7): Likewise. (cortex-a32): Add fpu. Add options for crypto and nofp. (cortex-a35, cortex-a53): Likewise. (cortex-a57): Add fpu. Add option for crypto. (cortex-a72, cortex-a73): Likewise. (exynos-m1): Likewise. (cortex-a57.cortex-a53, cortex-a72.cortex-a53): Likewise. (cortex-a73.cortex-a35, cortex-a73.cortex-a53): Likewise. (cortex-m33): Add fpu. Add option for nofp. * config/arm/arm-cpu-cdata.h: Regenerated * config/arm/arm-cpu-data.h: Regenerated. From-SVN: r249284 --- gcc/ChangeLog | 38 +++ gcc/config/arm/arm-cpu-cdata.h | 41 ++- gcc/config/arm/arm-cpu-data.h | 584 ++++++++++++++++++++++++++++++++++------- gcc/config/arm/arm-cpus.in | 208 ++++++++++----- gcc/config/arm/arm-isa.h | 20 +- gcc/config/arm/arm.c | 3 +- 6 files changed, 730 insertions(+), 164 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2878289..9eadbce 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,43 @@ 2017-06-16 Richard Earnshaw + * config/arm/arm-isa.h (ISA_ALL_FPU_INTERNAL): Renamed from ISA_ALL_FPU. + (ISA_ALL_CRYPTO): New macro. + (ISA_ALL_SIMD): New macro + (ISA_ALL_FP): New macro. + * config/arm/arm.c (fpu_bitlist): Update initializer. + * config/arm/arm-cpus.in: Use new ISA_ALL macros to disable crypto, + simd or fp. + (arm9e): Add fpu. Add option for nofp + (arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e): Likewise. + (arm926ej-s, arm1026ej-s): Likewise. + (generic-armv7-a): Add fpu. Add options for simd, vfpv3, vfpv3-d16, + vfpv3-fp16, vfpv3-d16-fp16, vfpv4, vfpv4-d16, neon, neon-vfp3, + neon-fp16, neon-vfpv4, nofp and nosimd. + (cortex-a5, cortex-a7): Add fpu. Add options for nosimd and nofp. + (cortex-a8): Add fpu. Add option for nofp. + (cortex-a9): Add fpu. Add options for nosimd and nofp. + (cortex-a12, cortex-a15, cortex-a17): Add fpu. Add option for nofp. + (cortex-r4f): Add fpu. + (cortex-r5): Add fpu. Add options for nofp.dp and nofp. + (cortex-r7): Use idiv option from architecture. Add fpu. Add option + for nofp. + (cortex-r8): Likewise. + (cortex-m4): Add fpu. Add option for nofp. + (cortex-a15.cortex-a7): Add fpu. Add option for nofp. + (cortex-a17.cortex-a7): Likewise. + (cortex-a32): Add fpu. Add options for crypto and nofp. + (cortex-a35, cortex-a53): Likewise. + (cortex-a57): Add fpu. Add option for crypto. + (cortex-a72, cortex-a73): Likewise. + (exynos-m1): Likewise. + (cortex-a57.cortex-a53, cortex-a72.cortex-a53): Likewise. + (cortex-a73.cortex-a35, cortex-a73.cortex-a53): Likewise. + (cortex-m33): Add fpu. Add option for nofp. + * config/arm/arm-cpu-cdata.h: Regenerated + * config/arm/arm-cpu-data.h: Regenerated. + +2017-06-16 Richard Earnshaw + * arm-cpus.in (armv5e): Add options fp, vfpv2 and nofp. (armv5te, armv5tej): Likewise. (armv6, armv6j, armv6k, armv6z, armv6kz, armv6zk, armv6t2): Likewise. diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index a64413d..aced3ac 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -341,6 +341,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm9e", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -348,6 +349,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm946e-s", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -355,6 +357,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm966e-s", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -362,6 +365,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm968e-s", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -369,6 +373,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm10e", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -376,6 +381,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm1020e", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -383,6 +389,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm1022e", { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -440,6 +447,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm926ej-s", { ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -447,6 +455,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "arm1026ej-s", { ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, }, @@ -556,6 +565,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "generic-armv7-a", { ISA_ARMv7a, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, }, @@ -563,6 +573,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a5", { ISA_ARMv7a, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }, }, @@ -570,6 +581,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a7", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -585,7 +597,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a9", { ISA_ARMv7a, - ISA_VFPv3,ISA_NEON, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }, }, @@ -593,6 +605,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a12", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -600,6 +613,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a15", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -607,6 +621,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a17", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -621,6 +636,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-r4f", { ISA_ARMv7r, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, }, @@ -628,7 +644,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-r5", { ISA_ARMv7r, - isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, }, @@ -636,7 +652,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-r7", { ISA_ARMv7r, - isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, }, @@ -644,7 +660,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-r8", { ISA_ARMv7r, - isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, }, @@ -652,6 +668,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-m7", { ISA_ARMv7em, + ISA_FPv5,ISA_FP_DBL, isa_quirk_no_volatile_ce, isa_nobit }, @@ -660,6 +677,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-m4", { ISA_ARMv7em, + ISA_VFPv4, isa_nobit }, }, @@ -682,6 +700,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a15.cortex-a7", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -689,6 +708,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a17.cortex-a7", { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, }, @@ -696,6 +716,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a32", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -703,6 +724,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a35", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -710,6 +732,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a53", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -717,6 +740,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a57", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -724,6 +748,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a72", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -731,6 +756,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a73", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -738,6 +764,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "exynos-m1", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -745,6 +772,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "xgene1", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -752,6 +780,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a57.cortex-a53", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -759,6 +788,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a72.cortex-a53", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -766,6 +796,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a73.cortex-a35", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -773,6 +804,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-a73.cortex-a53", { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, }, @@ -787,6 +819,7 @@ static const struct arm_arch_core_flag arm_arch_core_flags[] = "cortex-m33", { ISA_ARMv8m_main, + ISA_FPv5, isa_nobit }, }, diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h index 2a65ec6..b34247c 100644 --- a/gcc/config/arm/arm-cpu-data.h +++ b/gcc/config/arm/arm-cpu-data.h @@ -20,10 +20,162 @@ License along with GCC; see the file COPYING3. If not see . */ +static const struct cpu_option cpu_opttab_arm9e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm946es[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm966es[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm968es[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm10e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm1020e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm1022e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm926ejs[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_arm1026ejs[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_genericv7a[] = { + { + "simd", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "vfpv3", false, + { ISA_VFPv3,ISA_FP_D32, isa_nobit } + }, + { + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv3-fp16", false, + { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv3-d16-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv4", false, + { ISA_VFPv4,ISA_FP_D32, isa_nobit } + }, + { + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { + "neon", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-vfpv3", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-fp16", false, + { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } + }, + { + "neon-vfpv4", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa5[] = { + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa7[] = { + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + static const struct cpu_option cpu_opttab_cortexa8[] = { { "nofp", true, - { ISA_NEON,ISA_VFPv3, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -31,11 +183,215 @@ static const struct cpu_option cpu_opttab_cortexa8[] = { static const struct cpu_option cpu_opttab_cortexa9[] = { { "nofp", true, - { ISA_NEON,ISA_VFPv3, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nosimd", true, - { ISA_NEON, isa_nobit } + { ISA_ALL_SIMD, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa12[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa15[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa17[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexr5[] = { + { + "nofp.dp", true, + { ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexr7[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexr8[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexm7[] = { + { + "nofp.dp", true, + { ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexm4[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa15cortexa7[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa17cortexa7[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa32[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa35[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa57[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa72[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa73[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_exynosm1[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_xgene1[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa57cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa72cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa73cortexa35[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexa73cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_option cpu_opttab_cortexm33[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -589,9 +945,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm9e, &arm_9e_tune }, { @@ -601,9 +958,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm946es, &arm_9e_tune }, { @@ -613,9 +971,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm966es, &arm_9e_tune }, { @@ -625,9 +984,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm968es, &arm_9e_tune }, { @@ -637,9 +997,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm10e, &arm_fastmul_tune }, { @@ -649,9 +1010,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm1020e, &arm_fastmul_tune }, { @@ -661,9 +1023,10 @@ static const struct processors all_cores[] = "5TE", BASE_ARCH_5TE, { ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm1022e, &arm_fastmul_tune }, { @@ -758,9 +1121,10 @@ static const struct processors all_cores[] = "5TEJ", BASE_ARCH_5TEJ, { ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm926ejs, &arm_9e_tune }, { @@ -770,9 +1134,10 @@ static const struct processors all_cores[] = "5TEJ", BASE_ARCH_5TEJ, { ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_arm1026ejs, &arm_9e_tune }, { @@ -954,9 +1319,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7a, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_genericv7a, &arm_cortex_tune }, { @@ -966,9 +1332,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7a, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }, - NULL, + cpu_opttab_cortexa5, &arm_cortex_a5_tune }, { @@ -978,9 +1345,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa7, &arm_cortex_a7_tune }, { @@ -1003,7 +1371,7 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7a, - ISA_VFPv3,ISA_NEON, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit }, cpu_opttab_cortexa9, @@ -1016,9 +1384,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa12, &arm_cortex_a12_tune }, { @@ -1028,9 +1397,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa15, &arm_cortex_a15_tune }, { @@ -1040,9 +1410,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa17, &arm_cortex_a12_tune }, { @@ -1064,6 +1435,7 @@ static const struct processors all_cores[] = "7R", BASE_ARCH_7R, { ISA_ARMv7r, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, NULL, @@ -1077,9 +1449,10 @@ static const struct processors all_cores[] = { ISA_ARMv7r, isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_cortexr5, &arm_cortex_tune }, { @@ -1090,9 +1463,10 @@ static const struct processors all_cores[] = { ISA_ARMv7r, isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_cortexr7, &arm_cortex_tune }, { @@ -1103,9 +1477,10 @@ static const struct processors all_cores[] = { ISA_ARMv7r, isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, isa_nobit }, - NULL, + cpu_opttab_cortexr8, &arm_cortex_tune }, { @@ -1115,10 +1490,11 @@ static const struct processors all_cores[] = "7EM", BASE_ARCH_7EM, { ISA_ARMv7em, + ISA_FPv5,ISA_FP_DBL, isa_quirk_no_volatile_ce, isa_nobit }, - NULL, + cpu_opttab_cortexm7, &arm_cortex_m7_tune }, { @@ -1128,9 +1504,10 @@ static const struct processors all_cores[] = "7EM", BASE_ARCH_7EM, { ISA_ARMv7em, + ISA_VFPv4, isa_nobit }, - NULL, + cpu_opttab_cortexm4, &arm_v7m_tune }, { @@ -1165,9 +1542,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa15cortexa7, &arm_cortex_a15_tune }, { @@ -1177,9 +1555,10 @@ static const struct processors all_cores[] = "7A", BASE_ARCH_7A, { ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa17cortexa7, &arm_cortex_a12_tune }, { @@ -1190,9 +1569,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa32, &arm_cortex_a35_tune }, { @@ -1203,9 +1583,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa35, &arm_cortex_a35_tune }, { @@ -1216,9 +1597,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa53, &arm_cortex_a53_tune }, { @@ -1229,9 +1611,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa57, &arm_cortex_a57_tune }, { @@ -1242,9 +1625,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa72, &arm_cortex_a57_tune }, { @@ -1255,9 +1639,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa73, &arm_cortex_a73_tune }, { @@ -1268,9 +1653,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_exynosm1, &arm_exynosm1_tune }, { @@ -1280,9 +1666,10 @@ static const struct processors all_cores[] = "8A", BASE_ARCH_8A, { ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_xgene1, &arm_xgene1_tune }, { @@ -1293,9 +1680,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa57cortexa53, &arm_cortex_a57_tune }, { @@ -1306,9 +1694,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa72cortexa53, &arm_cortex_a57_tune }, { @@ -1319,9 +1708,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa73cortexa35, &arm_cortex_a73_tune }, { @@ -1332,9 +1722,10 @@ static const struct processors all_cores[] = { ISA_ARMv8a, isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, isa_nobit }, - NULL, + cpu_opttab_cortexa73cortexa53, &arm_cortex_a73_tune }, { @@ -1357,9 +1748,10 @@ static const struct processors all_cores[] = { ISA_ARMv8m_main, isa_bit_ARMv7em, + ISA_FPv5, isa_nobit }, - NULL, + cpu_opttab_cortexm33, &arm_v7m_tune }, {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL, NULL} @@ -1376,7 +1768,7 @@ static const struct cpu_option arch_opttab_armv5e[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1392,7 +1784,7 @@ static const struct cpu_option arch_opttab_armv5te[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1408,7 +1800,7 @@ static const struct cpu_option arch_opttab_armv5tej[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1424,7 +1816,7 @@ static const struct cpu_option arch_opttab_armv6[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1440,7 +1832,7 @@ static const struct cpu_option arch_opttab_armv6j[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1456,7 +1848,7 @@ static const struct cpu_option arch_opttab_armv6k[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1472,7 +1864,7 @@ static const struct cpu_option arch_opttab_armv6z[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1488,7 +1880,7 @@ static const struct cpu_option arch_opttab_armv6kz[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1504,7 +1896,7 @@ static const struct cpu_option arch_opttab_armv6zk[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1520,7 +1912,7 @@ static const struct cpu_option arch_opttab_armv6t2[] = { }, { "nofp", true, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1543,18 +1935,14 @@ static const struct cpu_option arch_opttab_armv7_a[] = { { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { - "simd", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { "vfpv3", false, { ISA_VFPv3,ISA_FP_D32, isa_nobit } }, { - "vfpv3-d16", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { "vfpv3-d16-fp16", false, { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } }, @@ -1563,12 +1951,16 @@ static const struct cpu_option arch_opttab_armv7_a[] = { { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } }, { + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { "vfpv4", false, { ISA_VFPv4,ISA_FP_D32, isa_nobit } }, { - "vfpv4-d16", false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + "simd", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } }, { "neon", false, @@ -1588,33 +1980,25 @@ static const struct cpu_option arch_opttab_armv7_a[] = { }, { "nofp", true, - { ISA_VFPv4,ISA_NEON, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nosimd", true, - { ISA_NEON, isa_nobit } + { ISA_ALL_SIMD, isa_nobit } }, { NULL, false, {isa_nobit}} }; static const struct cpu_option arch_opttab_armv7ve[] = { { - "fp", false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "simd", false, - { ISA_VFPv4,ISA_NEON, isa_nobit } + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { "vfpv3", false, { ISA_VFPv3,ISA_FP_D32, isa_nobit } }, { - "vfpv3-d16", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { "vfpv3-d16-fp16", false, { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } }, @@ -1623,14 +2007,18 @@ static const struct cpu_option arch_opttab_armv7ve[] = { { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } }, { - "vfpv4", false, - { ISA_VFPv4,ISA_FP_D32, isa_nobit } + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } }, { - "vfpv4-d16", false, + "fp", false, { ISA_VFPv4,ISA_FP_DBL, isa_nobit } }, { + "vfpv4", false, + { ISA_VFPv4,ISA_FP_D32, isa_nobit } + }, + { "neon", false, { ISA_VFPv3,ISA_NEON, isa_nobit } }, @@ -1643,36 +2031,40 @@ static const struct cpu_option arch_opttab_armv7ve[] = { { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } }, { + "simd", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { "neon-vfpv4", false, { ISA_VFPv4,ISA_NEON, isa_nobit } }, { "nofp", true, - { ISA_VFPv4,ISA_NEON, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nosimd", true, - { ISA_NEON, isa_nobit } + { ISA_ALL_SIMD, isa_nobit } }, { NULL, false, {isa_nobit}} }; static const struct cpu_option arch_opttab_armv7_r[] = { { - "fp", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { "fp.sp", false, { ISA_VFPv3, isa_nobit } }, { + "fp", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { "idiv", false, { isa_bit_adiv, isa_nobit } }, { "nofp", true, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "noidiv", true, @@ -1696,7 +2088,7 @@ static const struct cpu_option arch_opttab_armv7e_m[] = { }, { "nofp", true, - { ISA_FPv5,ISA_FP_DBL, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1712,15 +2104,15 @@ static const struct cpu_option arch_opttab_armv8_a[] = { }, { "crypto", false, - { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { "nofp", true, - { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nocrypto", true, - { ISA_CRYPTO, isa_nobit } + { ISA_ALL_CRYPTO, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1732,39 +2124,39 @@ static const struct cpu_option arch_opttab_armv8_1_a[] = { }, { "crypto", false, - { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { "nofp", true, - { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nocrypto", true, - { ISA_CRYPTO, isa_nobit } + { ISA_ALL_CRYPTO, isa_nobit } }, { NULL, false, {isa_nobit}} }; static const struct cpu_option arch_opttab_armv8_2_a[] = { { - "fp16", false, - { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit } - }, - { "simd", false, { ISA_FP_ARMv8,ISA_NEON, isa_nobit } }, { + "fp16", false, + { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit } + }, + { "crypto", false, - { ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { "nofp", true, - { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON,ISA_CRYPTO, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { "nocrypto", true, - { ISA_CRYPTO, isa_nobit } + { ISA_ALL_CRYPTO, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1784,7 +2176,7 @@ static const struct cpu_option arch_opttab_armv8_m_main[] = { }, { "nofp", true, - { ISA_FPv5, isa_nobit } + { ISA_ALL_FP, isa_nobit } }, { NULL, false, {isa_nobit}} }; @@ -1964,7 +2356,7 @@ static const struct processors all_architectures[] = ISA_ARMv6kz, isa_nobit }, - arch_opttab_armv6zk, + arch_opttab_armv6kz, NULL }, { @@ -1975,7 +2367,7 @@ static const struct processors all_architectures[] = ISA_ARMv6kz, isa_nobit }, - arch_opttab_armv6kz, + arch_opttab_armv6zk, NULL }, { diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 7a1fede..fdd5e83 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -115,7 +115,7 @@ begin arch armv5e isa ARMv5e option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv5e begin arch armv5te @@ -125,7 +125,7 @@ begin arch armv5te isa ARMv5te option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv5te begin arch armv5tej @@ -135,7 +135,7 @@ begin arch armv5tej isa ARMv5tej option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv5tej begin arch armv6 @@ -145,7 +145,7 @@ begin arch armv6 isa ARMv6 option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6 begin arch armv6j @@ -155,7 +155,7 @@ begin arch armv6j isa ARMv6j option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6j begin arch armv6k @@ -165,7 +165,7 @@ begin arch armv6k isa ARMv6k option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6k begin arch armv6z @@ -175,7 +175,7 @@ begin arch armv6z isa ARMv6z option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6z begin arch armv6kz @@ -185,7 +185,7 @@ begin arch armv6kz isa ARMv6kz option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6kz begin arch armv6zk @@ -195,7 +195,7 @@ begin arch armv6zk isa ARMv6kz option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6zk begin arch armv6t2 @@ -205,7 +205,7 @@ begin arch armv6t2 isa ARMv6t2 option fp add VFPv2 FP_DBL option vfpv2 add VFPv2 FP_DBL - option nofp remove VFPv2 FP_DBL + option nofp remove ALL_FP end arch armv6t2 begin arch armv6-m @@ -236,20 +236,20 @@ begin arch armv7-a base 7A isa ARMv7a # fp => VFPv3-d16, simd => neon-vfpv3 - option fp add VFPv3 FP_DBL - option simd add VFPv3 NEON - option vfpv3 add VFPv3 FP_D32 - option vfpv3-d16 add VFPv3 FP_DBL + option fp add VFPv3 FP_DBL + option vfpv3-d16 add VFPv3 FP_DBL + option vfpv3 add VFPv3 FP_D32 option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv - option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv - option vfpv4 add VFPv4 FP_D32 - option vfpv4-d16 add VFPv4 FP_DBL - option neon add VFPv3 NEON - option neon-vfpv3 add VFPv3 NEON - option neon-fp16 add VFPv3 NEON bit_fp16conv - option neon-vfpv4 add VFPv4 NEON - option nofp remove VFPv4 NEON - option nosimd remove NEON + option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv + option vfpv4-d16 add VFPv4 FP_DBL + option vfpv4 add VFPv4 FP_D32 + option simd add VFPv3 NEON + option neon add VFPv3 NEON + option neon-vfpv3 add VFPv3 NEON + option neon-fp16 add VFPv3 NEON bit_fp16conv + option neon-vfpv4 add VFPv4 NEON + option nofp remove ALL_FP + option nosimd remove ALL_SIMD end arch armv7-a begin arch armv7ve @@ -258,20 +258,20 @@ begin arch armv7ve base 7A isa ARMv7ve # fp => VFPv4-d16, simd => neon-vfpv4 - option fp add VFPv4 FP_DBL - option simd add VFPv4 NEON - option vfpv3 add VFPv3 FP_D32 - option vfpv3-d16 add VFPv3 FP_DBL + option vfpv3-d16 add VFPv3 FP_DBL + option vfpv3 add VFPv3 FP_D32 option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv - option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv - option vfpv4 add VFPv4 FP_D32 - option vfpv4-d16 add VFPv4 FP_DBL - option neon add VFPv3 NEON - option neon-vfpv3 add VFPv3 NEON - option neon-fp16 add VFPv3 NEON bit_fp16conv - option neon-vfpv4 add VFPv4 NEON - option nofp remove VFPv4 NEON - option nosimd remove NEON + option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv + option vfpv4-d16 add VFPv4 FP_DBL + option fp add VFPv4 FP_DBL + option vfpv4 add VFPv4 FP_D32 + option neon add VFPv3 NEON + option neon-vfpv3 add VFPv3 NEON + option neon-fp16 add VFPv3 NEON bit_fp16conv + option simd add VFPv4 NEON + option neon-vfpv4 add VFPv4 NEON + option nofp remove ALL_FP + option nosimd remove ALL_SIMD end arch armv7ve begin arch armv7-r @@ -280,10 +280,10 @@ begin arch armv7-r base 7R isa ARMv7r # ARMv7-r uses VFPv3-d16 - option fp add VFPv3 FP_DBL option fp.sp add VFPv3 + option fp add VFPv3 FP_DBL option idiv add bit_adiv - option nofp remove VFPv3 FP_DBL + option nofp remove ALL_FP option noidiv remove bit_adiv end arch armv7-r @@ -305,7 +305,7 @@ begin arch armv7e-m option fp add VFPv4 option fpv5 add FPv5 option fp.dp add FPv5 FP_DBL - option nofp remove FPv5 FP_DBL + option nofp remove ALL_FP end arch armv7e-m begin arch armv8-a @@ -315,9 +315,9 @@ begin arch armv8-a isa ARMv8a option crc add bit_crc32 option simd add FP_ARMv8 NEON - option crypto add FP_ARMv8 NEON CRYPTO - option nofp remove FP_ARMv8 NEON CRYPTO - option nocrypto remove CRYPTO + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP + option nocrypto remove ALL_CRYPTO end arch armv8-a begin arch armv8.1-a @@ -326,9 +326,9 @@ begin arch armv8.1-a base 8A isa ARMv8_1a option simd add FP_ARMv8 NEON - option crypto add FP_ARMv8 NEON CRYPTO - option nofp remove FP_ARMv8 NEON CRYPTO - option nocrypto remove CRYPTO + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP + option nocrypto remove ALL_CRYPTO end arch armv8.1-a begin arch armv8.2-a @@ -336,11 +336,11 @@ begin arch armv8.2-a tune flags CO_PROC base 8A isa ARMv8_2a - option fp16 add bit_fp16 FP_ARMv8 NEON option simd add FP_ARMv8 NEON - option crypto add FP_ARMv8 NEON CRYPTO - option nofp remove bit_fp16 FP_ARMv8 NEON CRYPTO - option nocrypto remove CRYPTO + option fp16 add bit_fp16 FP_ARMv8 NEON + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP + option nocrypto remove ALL_CRYPTO end arch armv8.2-a begin arch armv8-m.base @@ -358,7 +358,7 @@ begin arch armv8-m.main # fp => FPv5-sp-d16; fp.dp => FPv5-d16 option fp add FPv5 option fp.dp add FPv5 FP_DBL - option nofp remove FPv5 + option nofp remove ALL_FP end arch armv8-m.main begin arch iwmmxt @@ -668,6 +668,7 @@ end cpu ep9312 # V5T Architecture Processors +# These used VFPv1 which isn't supported by GCC begin cpu arm10tdmi tune flags LDSCHED architecture armv5t @@ -685,6 +686,8 @@ end cpu arm1020t begin cpu arm9e tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm9e @@ -692,6 +695,8 @@ begin cpu arm946e-s cname arm946es tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm946e-s @@ -699,6 +704,8 @@ begin cpu arm966e-s cname arm966es tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm966e-s @@ -706,24 +713,32 @@ begin cpu arm968e-s cname arm968es tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm968e-s begin cpu arm10e tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs fastmul end cpu arm10e begin cpu arm1020e tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs fastmul end cpu arm1020e begin cpu arm1022e tune flags LDSCHED architecture armv5te + fpu vfpv2 + option nofp remove ALL_FP costs fastmul end cpu arm1022e @@ -776,6 +791,8 @@ begin cpu arm926ej-s cname arm926ejs tune flags LDSCHED architecture armv5tej + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm926ej-s @@ -783,6 +800,8 @@ begin cpu arm1026ej-s cname arm1026ejs tune flags LDSCHED architecture armv5tej + fpu vfpv2 + option nofp remove ALL_FP costs 9e end cpu arm1026ej-s @@ -901,6 +920,20 @@ begin cpu generic-armv7-a cname genericv7a tune flags LDSCHED architecture armv7-a + fpu vfpv3-d16 + option simd add VFPv3 NEON + option vfpv3 add VFPv3 FP_D32 + option vfpv3-d16 add VFPv3 FP_DBL + option vfpv3-fp16 add VFPv3 FP_D32 bit_fp16conv + option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv + option vfpv4 add VFPv4 FP_D32 + option vfpv4-d16 add VFPv4 FP_DBL + option neon add VFPv3 NEON + option neon-vfpv3 add VFPv3 NEON + option neon-fp16 add VFPv3 NEON bit_fp16conv + option neon-vfpv4 add VFPv4 NEON + option nofp remove ALL_FP + option nosimd remove ALL_SIMD costs cortex end cpu generic-armv7-a @@ -908,6 +941,9 @@ begin cpu cortex-a5 cname cortexa5 tune flags LDSCHED architecture armv7-a + fpu neon-fp16 + option nosimd remove ALL_SIMD + option nofp remove ALL_FP costs cortex_a5 end cpu cortex-a5 @@ -915,6 +951,9 @@ begin cpu cortex-a7 cname cortexa7 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nosimd remove ALL_SIMD + option nofp remove ALL_FP costs cortex_a7 end cpu cortex-a7 @@ -923,7 +962,7 @@ begin cpu cortex-a8 tune flags LDSCHED architecture armv7-a fpu neon-vfpv3 - option nofp remove NEON VFPv3 + option nofp remove ALL_FP costs cortex_a8 end cpu cortex-a8 @@ -931,9 +970,9 @@ begin cpu cortex-a9 cname cortexa9 tune flags LDSCHED architecture armv7-a - fpu neon-vfpv3 - option nofp remove NEON VFPv3 - option nosimd remove NEON + fpu neon-fp16 + option nofp remove ALL_FP + option nosimd remove ALL_SIMD costs cortex_a9 end cpu cortex-a9 @@ -942,6 +981,8 @@ begin cpu cortex-a12 tune for cortex-a17 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nofp remove ALL_FP costs cortex_a12 end cpu cortex-a12 @@ -949,6 +990,8 @@ begin cpu cortex-a15 cname cortexa15 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nofp remove ALL_FP costs cortex_a15 end cpu cortex-a15 @@ -956,6 +999,8 @@ begin cpu cortex-a17 cname cortexa17 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nofp remove ALL_FP costs cortex_a12 end cpu cortex-a17 @@ -970,22 +1015,26 @@ begin cpu cortex-r4f cname cortexr4f tune flags LDSCHED architecture armv7-r + fpu vfpv3-d16 costs cortex end cpu cortex-r4f begin cpu cortex-r5 cname cortexr5 tune flags LDSCHED - architecture armv7-r - isa bit_adiv + architecture armv7-r+idiv + fpu vfpv3-d16 + option nofp.dp remove FP_DBL + option nofp remove ALL_FP costs cortex end cpu cortex-r5 begin cpu cortex-r7 cname cortexr7 tune flags LDSCHED - architecture armv7-r - isa bit_adiv + architecture armv7-r+idiv + fpu vfpv3-d16 + option nofp remove ALL_FP costs cortex end cpu cortex-r7 @@ -993,8 +1042,9 @@ begin cpu cortex-r8 cname cortexr8 tune for cortex-r7 tune flags LDSCHED - architecture armv7-r - isa bit_adiv + architecture armv7-r+idiv + fpu vfpv3-d16 + option nofp remove ALL_FP costs cortex end cpu cortex-r8 @@ -1003,6 +1053,9 @@ begin cpu cortex-m7 tune flags LDSCHED architecture armv7e-m isa quirk_no_volatile_ce + fpu fpv5-d16 + option nofp.dp remove FP_DBL + option nofp remove ALL_FP costs cortex_m7 end cpu cortex-m7 @@ -1010,6 +1063,8 @@ begin cpu cortex-m4 cname cortexm4 tune flags LDSCHED architecture armv7e-m + fpu fpv4-sp-d16 + option nofp remove ALL_FP costs v7m end cpu cortex-m4 @@ -1034,6 +1089,8 @@ begin cpu cortex-a15.cortex-a7 tune for cortex-a7 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nofp remove ALL_FP costs cortex_a15 end cpu cortex-a15.cortex-a7 @@ -1042,6 +1099,8 @@ begin cpu cortex-a17.cortex-a7 tune for cortex-a7 tune flags LDSCHED architecture armv7ve + fpu neon-vfpv4 + option nofp remove ALL_FP costs cortex_a12 end cpu cortex-a17.cortex-a7 @@ -1052,6 +1111,9 @@ begin cpu cortex-a32 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP costs cortex_a35 end cpu cortex-a32 @@ -1060,6 +1122,9 @@ begin cpu cortex-a35 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP costs cortex_a35 end cpu cortex-a35 @@ -1067,6 +1132,9 @@ begin cpu cortex-a53 cname cortexa53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO + option nofp remove ALL_FP costs cortex_a53 end cpu cortex-a53 @@ -1074,6 +1142,8 @@ begin cpu cortex-a57 cname cortexa57 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a57 end cpu cortex-a57 @@ -1082,6 +1152,8 @@ begin cpu cortex-a72 tune for cortex-a57 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a57 end cpu cortex-a72 @@ -1090,6 +1162,8 @@ begin cpu cortex-a73 tune for cortex-a57 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a73 end cpu cortex-a73 @@ -1097,12 +1171,16 @@ begin cpu exynos-m1 cname exynosm1 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs exynosm1 end cpu exynos-m1 begin cpu xgene1 tune flags LDSCHED architecture armv8-a + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs xgene1 end cpu xgene1 @@ -1113,6 +1191,8 @@ begin cpu cortex-a57.cortex-a53 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a57 end cpu cortex-a57.cortex-a53 @@ -1121,6 +1201,8 @@ begin cpu cortex-a72.cortex-a53 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a57 end cpu cortex-a72.cortex-a53 @@ -1129,6 +1211,8 @@ begin cpu cortex-a73.cortex-a35 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a73 end cpu cortex-a73.cortex-a35 @@ -1137,6 +1221,8 @@ begin cpu cortex-a73.cortex-a53 tune for cortex-a53 tune flags LDSCHED architecture armv8-a+crc + fpu neon-fp-armv8 + option crypto add FP_ARMv8 CRYPTO costs cortex_a73 end cpu cortex-a73.cortex-a53 @@ -1153,6 +1239,8 @@ begin cpu cortex-m33 cname cortexm33 tune flags LDSCHED architecture armv8-m.main+dsp + fpu fpv5-sp-d16 + option nofp remove ALL_FP costs v7m end cpu cortex-m33 diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h index 7d1e23b..4b5a0f6 100644 --- a/gcc/config/arm/arm-isa.h +++ b/gcc/config/arm/arm-isa.h @@ -127,11 +127,25 @@ enum isa_feature #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse +/* List of all cryptographic extensions to stripout if crypto is + disabled. Currently, that's trivial, but we define it anyway for + consistency with the SIMD and FP disable lists. */ +#define ISA_ALL_CRYPTO isa_bit_crypto + +/* List of all SIMD bits to strip out if SIMD is disabled. This does + strip off 32 D-registers, but does not remove support for + double-precision FP. */ +#define ISA_ALL_SIMD isa_bit_fp_d32, isa_bit_neon, ISA_ALL_CRYPTO + /* List of all FPU bits to strip out if -mfpu is used to override the default. isa_bit_fp16 is deliberately missing from this list. */ -#define ISA_ALL_FPU isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, \ - isa_bit_FPv5, isa_bit_FP_ARMv8, isa_bit_neon, isa_bit_fp16conv, \ - isa_bit_fp_dbl, isa_bit_fp_d32, isa_bit_crypto +#define ISA_ALL_FPU_INTERNAL \ + isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, isa_bit_FPv5, \ + isa_bit_FP_ARMv8, isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD + +/* Similarly, but including fp16 and other extensions that aren't part of + -mfpu support. */ +#define ISA_ALL_FP isa_bit_fp16, ISA_ALL_FPU_INTERNAL /* Useful combinations. */ #define ISA_VFPv2 isa_bit_VFPv2 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index f35a1c2..2cffd49 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3418,7 +3418,8 @@ arm_configure_build_target (struct arm_build_target *target, static void arm_option_override (void) { - static const enum isa_feature fpu_bitlist[] = { ISA_ALL_FPU, isa_nobit }; + static const enum isa_feature fpu_bitlist[] + = { ISA_ALL_FPU_INTERNAL, isa_nobit }; static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit}; cl_target_option opts; -- cgit v1.1 From 9ef88abef4a75cea3c48bd32f65b0c0fd18d4f6b Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:02:59 +0000 Subject: [build] Make sbitmap code available to the driver The ARM option parsing code uses sbitmap data structures to manage features and upcoming patches will shortly need to use these bitmaps within the driver. This patch moves sbitmap.o from OBJS to OBJS-libcommon to facilitate this. The patch has no impact on targets that don't need this functionality, since the object is part of an archive and will only be extracted if needed. * Makefile.in (OBJS): Move sbitmap.o from here ... (OBJS-libcommon): ... to here. From-SVN: r249285 --- gcc/ChangeLog | 5 +++++ gcc/Makefile.in | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9eadbce..d436d36 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Richard Earnshaw + * Makefile.in (OBJS): Move sbitmap.o from here ... + (OBJS-libcommon): ... to here. + +2017-06-16 Richard Earnshaw + * config/arm/arm-isa.h (ISA_ALL_FPU_INTERNAL): Renamed from ISA_ALL_FPU. (ISA_ALL_CRYPTO): New macro. (ISA_ALL_SIMD): New macro diff --git a/gcc/Makefile.in b/gcc/Makefile.in index da98c8e..67d69c1 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -1441,7 +1441,6 @@ OBJS = \ rtlanal.o \ rtlhooks.o \ run-rtl-passes.o \ - sbitmap.o \ sched-deps.o \ sched-ebb.o \ sched-rgn.o \ @@ -1587,6 +1586,7 @@ OBJS = \ OBJS-libcommon = diagnostic.o diagnostic-color.o diagnostic-show-locus.o \ edit-context.o \ pretty-print.o intl.o \ + sbitmap.o \ vec.o input.o version.o hash-table.o ggc-none.o memory-block.o \ selftest.o -- cgit v1.1 From 050809ed8af639d385251b95bf0d8d11fd7d3863 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:03:08 +0000 Subject: [arm] Split CPU, architecture and tuning data tables. The driver really needs to handle some canonicalization of the new -mcpu and -march options in order to make multilib selection tractable. This will require moving much of the logic to parse the new options into the common code file. However, the tuning data definitely does not want to be there as it is very specific to the compiler passes. To facilitate this we need to split up the generated configuration data into architectural and tuning related tables. This patch starts that process, but does not yet move any code out of the compiler backend. Since I'm reworking all that code I took the opportunity to also separate out the CPU data tables from the architecture data tables. Although they are related, there is a lot of redundancy in the CPU options that is best handled by simply indirecting to the architecture entry. * config/arm/arm-protos.h (arm_build_target): Remove arch_core. (cpu_arch_extension): New structure. (cpu_arch_option, arch_option, cpu_option): New structures. * config/arm/parsecpu.awk (gen_headers): Build an enumeration of architecture types. (gen_data): Generate new format data tables. * config/arm/arm.c (cpu_tune): New structure. (cpu_option, processors): Delete. (arm_print_hint_for_core_or_arch): Delete. Replace with ... (arm_print_hint_for_cpu_option): ... this and ... (arm_print_hint_for_arch_option): ... this. (arm_parse_arch_cpu_name): Delete. Replace with ... (arm_parse_cpu_option_name): ... this and ... (arm_parse_arch_option_name): ... this. (arm_unrecognized_feature): Change type of target parameter to cpu_arch_option. (arm_parse_arch_cpu_features): Delete. Replace with ... (arm_parse_option_features): ... this. (arm_configure_build_target): Rework to use new configuration data tables. (arm_print_tune_info): Rework for new configuration data tables. * config/arm/arm-cpu-data.h: Regenerated. * config/arm/arm-cpu.h: Regenerated. From-SVN: r249286 --- gcc/ChangeLog | 26 + gcc/config/arm/arm-cpu-data.h | 2701 +++++++++++++++++++++++------------------ gcc/config/arm/arm-cpu.h | 38 + gcc/config/arm/arm-protos.h | 38 +- gcc/config/arm/arm.c | 231 ++-- gcc/config/arm/parsecpu.awk | 119 +- 6 files changed, 1866 insertions(+), 1287 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d436d36..59eafb9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,31 @@ 2017-06-16 Richard Earnshaw + * config/arm/arm-protos.h (arm_build_target): Remove arch_core. + (cpu_arch_extension): New structure. + (cpu_arch_option, arch_option, cpu_option): New structures. + * config/arm/parsecpu.awk (gen_headers): Build an enumeration of + architecture types. + (gen_data): Generate new format data tables. + * config/arm/arm.c (cpu_tune): New structure. + (cpu_option, processors): Delete. + (arm_print_hint_for_core_or_arch): Delete. Replace with ... + (arm_print_hint_for_cpu_option): ... this and ... + (arm_print_hint_for_arch_option): ... this. + (arm_parse_arch_cpu_name): Delete. Replace with ... + (arm_parse_cpu_option_name): ... this and ... + (arm_parse_arch_option_name): ... this. + (arm_unrecognized_feature): Change type of target parameter to + cpu_arch_option. + (arm_parse_arch_cpu_features): Delete. Replace with ... + (arm_parse_option_features): ... this. + (arm_configure_build_target): Rework to use new configuration data + tables. + (arm_print_tune_info): Rework for new configuration data tables. + * config/arm/arm-cpu-data.h: Regenerated. + * config/arm/arm-cpu.h: Regenerated. + +2017-06-16 Richard Earnshaw + * Makefile.in (OBJS): Move sbitmap.o from here ... (OBJS-libcommon): ... to here. diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h index b34247c..646f8e1 100644 --- a/gcc/config/arm/arm-cpu-data.h +++ b/gcc/config/arm/arm-cpu-data.h @@ -20,7 +20,7 @@ License along with GCC; see the file COPYING3. If not see . */ -static const struct cpu_option cpu_opttab_arm9e[] = { +static const cpu_arch_extension cpu_opttab_arm9e[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -28,7 +28,7 @@ static const struct cpu_option cpu_opttab_arm9e[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_arm946es[] = { +static const cpu_arch_extension cpu_opttab_arm946es[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -36,7 +36,7 @@ static const struct cpu_option cpu_opttab_arm946es[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_arm966es[] = { +static const cpu_arch_extension cpu_opttab_arm966es[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -44,7 +44,7 @@ static const struct cpu_option cpu_opttab_arm966es[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_arm968es[] = { +static const cpu_arch_extension cpu_opttab_arm968es[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -52,7 +52,7 @@ static const struct cpu_option cpu_opttab_arm968es[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_arm10e[] = { +static const cpu_arch_extension cpu_opttab_arm10e[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -60,7 +60,7 @@ static const struct cpu_option cpu_opttab_arm10e[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_arm1020e[] = { +static const cpu_arch_extension cpu_opttab_arm1020e[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -68,7 +68,7 @@ static const struct cpu_option cpu_opttab_arm1020e[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_arm1022e[] = { +static const cpu_arch_extension cpu_opttab_arm1022e[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -76,7 +76,7 @@ static const struct cpu_option cpu_opttab_arm1022e[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_arm926ejs[] = { +static const cpu_arch_extension cpu_opttab_arm926ejs[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -84,7 +84,7 @@ static const struct cpu_option cpu_opttab_arm926ejs[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_arm1026ejs[] = { +static const cpu_arch_extension cpu_opttab_arm1026ejs[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -92,7 +92,7 @@ static const struct cpu_option cpu_opttab_arm1026ejs[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_genericv7a[] = { +static const cpu_arch_extension cpu_opttab_genericv7a[] = { { "simd", false, { ISA_VFPv3,ISA_NEON, isa_nobit } @@ -148,7 +148,7 @@ static const struct cpu_option cpu_opttab_genericv7a[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa5[] = { +static const cpu_arch_extension cpu_opttab_cortexa5[] = { { "nosimd", true, { ISA_ALL_SIMD, isa_nobit } @@ -160,7 +160,7 @@ static const struct cpu_option cpu_opttab_cortexa5[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa7[] = { +static const cpu_arch_extension cpu_opttab_cortexa7[] = { { "nosimd", true, { ISA_ALL_SIMD, isa_nobit } @@ -172,7 +172,7 @@ static const struct cpu_option cpu_opttab_cortexa7[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa8[] = { +static const cpu_arch_extension cpu_opttab_cortexa8[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -180,7 +180,7 @@ static const struct cpu_option cpu_opttab_cortexa8[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa9[] = { +static const cpu_arch_extension cpu_opttab_cortexa9[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -192,7 +192,7 @@ static const struct cpu_option cpu_opttab_cortexa9[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa12[] = { +static const cpu_arch_extension cpu_opttab_cortexa12[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -200,7 +200,7 @@ static const struct cpu_option cpu_opttab_cortexa12[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa15[] = { +static const cpu_arch_extension cpu_opttab_cortexa15[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -208,7 +208,7 @@ static const struct cpu_option cpu_opttab_cortexa15[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa17[] = { +static const cpu_arch_extension cpu_opttab_cortexa17[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -216,7 +216,7 @@ static const struct cpu_option cpu_opttab_cortexa17[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexr5[] = { +static const cpu_arch_extension cpu_opttab_cortexr5[] = { { "nofp.dp", true, { ISA_FP_DBL, isa_nobit } @@ -228,7 +228,7 @@ static const struct cpu_option cpu_opttab_cortexr5[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexr7[] = { +static const cpu_arch_extension cpu_opttab_cortexr7[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -236,7 +236,7 @@ static const struct cpu_option cpu_opttab_cortexr7[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexr8[] = { +static const cpu_arch_extension cpu_opttab_cortexr8[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -244,7 +244,7 @@ static const struct cpu_option cpu_opttab_cortexr8[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexm7[] = { +static const cpu_arch_extension cpu_opttab_cortexm7[] = { { "nofp.dp", true, { ISA_FP_DBL, isa_nobit } @@ -256,7 +256,7 @@ static const struct cpu_option cpu_opttab_cortexm7[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexm4[] = { +static const cpu_arch_extension cpu_opttab_cortexm4[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -264,7 +264,7 @@ static const struct cpu_option cpu_opttab_cortexm4[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa15cortexa7[] = { +static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -272,7 +272,7 @@ static const struct cpu_option cpu_opttab_cortexa15cortexa7[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa17cortexa7[] = { +static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -280,7 +280,7 @@ static const struct cpu_option cpu_opttab_cortexa17cortexa7[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa32[] = { +static const cpu_arch_extension cpu_opttab_cortexa32[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -292,7 +292,7 @@ static const struct cpu_option cpu_opttab_cortexa32[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa35[] = { +static const cpu_arch_extension cpu_opttab_cortexa35[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -304,7 +304,7 @@ static const struct cpu_option cpu_opttab_cortexa35[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa53[] = { +static const cpu_arch_extension cpu_opttab_cortexa53[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -316,7 +316,7 @@ static const struct cpu_option cpu_opttab_cortexa53[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa57[] = { +static const cpu_arch_extension cpu_opttab_cortexa57[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -324,7 +324,7 @@ static const struct cpu_option cpu_opttab_cortexa57[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa72[] = { +static const cpu_arch_extension cpu_opttab_cortexa72[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -332,7 +332,7 @@ static const struct cpu_option cpu_opttab_cortexa72[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa73[] = { +static const cpu_arch_extension cpu_opttab_cortexa73[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -340,7 +340,7 @@ static const struct cpu_option cpu_opttab_cortexa73[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_exynosm1[] = { +static const cpu_arch_extension cpu_opttab_exynosm1[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -348,7 +348,7 @@ static const struct cpu_option cpu_opttab_exynosm1[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_xgene1[] = { +static const cpu_arch_extension cpu_opttab_xgene1[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -356,7 +356,7 @@ static const struct cpu_option cpu_opttab_xgene1[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa57cortexa53[] = { +static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -364,7 +364,7 @@ static const struct cpu_option cpu_opttab_cortexa57cortexa53[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa72cortexa53[] = { +static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -372,7 +372,7 @@ static const struct cpu_option cpu_opttab_cortexa72cortexa53[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa73cortexa35[] = { +static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -380,7 +380,7 @@ static const struct cpu_option cpu_opttab_cortexa73cortexa35[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexa73cortexa53[] = { +static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = { { "crypto", false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } @@ -388,7 +388,7 @@ static const struct cpu_option cpu_opttab_cortexa73cortexa53[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option cpu_opttab_cortexm33[] = { +static const cpu_arch_extension cpu_opttab_cortexm33[] = { { "nofp", true, { ISA_ALL_FP, isa_nobit } @@ -396,1368 +396,1803 @@ static const struct cpu_option cpu_opttab_cortexm33[] = { { NULL, false, {isa_nobit}} }; -static const struct processors all_cores[] = +static const cpu_option all_cores[] = { { - "arm2", - TARGET_CPU_arm2, - (TF_CO_PROC | TF_NO_MODE32), - "2", BASE_ARCH_2, { - ISA_ARMv2,isa_bit_mode26, - isa_nobit + "arm2", + NULL, + { + ISA_ARMv2,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv2 }, { - "arm250", - TARGET_CPU_arm250, - (TF_CO_PROC | TF_NO_MODE32), - "2", BASE_ARCH_2, { - ISA_ARMv2,isa_bit_mode26, - isa_nobit + "arm250", + NULL, + { + ISA_ARMv2,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv2 }, { - "arm3", - TARGET_CPU_arm3, - (TF_CO_PROC | TF_NO_MODE32), - "2", BASE_ARCH_2, { - ISA_ARMv2,isa_bit_mode26, - isa_nobit + "arm3", + NULL, + { + ISA_ARMv2,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv2 }, { - "arm6", - TARGET_CPU_arm6, - (TF_CO_PROC), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm6", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm60", - TARGET_CPU_arm60, - (TF_CO_PROC), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm60", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm600", - TARGET_CPU_arm600, - (TF_CO_PROC | TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm600", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm610", - TARGET_CPU_arm610, - (TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm610", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm620", - TARGET_CPU_arm620, - (TF_CO_PROC | TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm620", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm7", - TARGET_CPU_arm7, - (TF_CO_PROC), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm7", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm7d", - TARGET_CPU_arm7d, - (TF_CO_PROC), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm7d", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm7di", - TARGET_CPU_arm7di, - (TF_CO_PROC), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm7di", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm70", - TARGET_CPU_arm70, - (TF_CO_PROC), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm70", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm700", - TARGET_CPU_arm700, - (TF_CO_PROC | TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm700", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm700i", - TARGET_CPU_arm700i, - (TF_CO_PROC | TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm700i", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm710", - TARGET_CPU_arm710, - (TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm710", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm720", - TARGET_CPU_arm720, - (TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm720", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm710c", - TARGET_CPU_arm710c, - (TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm710c", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm7100", - TARGET_CPU_arm7100, - (TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm7100", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm7500", - TARGET_CPU_arm7500, - (TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm7500", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm7500fe", - TARGET_CPU_arm7500fe, - (TF_CO_PROC | TF_WBUF), - "3", BASE_ARCH_3, { - ISA_ARMv3,isa_bit_mode26, - isa_nobit + "arm7500fe", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_slowmul_tune + TARGET_ARCH_armv3 }, { - "arm7m", - TARGET_CPU_arm7m, - (TF_CO_PROC), - "3M", BASE_ARCH_3M, { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit + "arm7m", + NULL, + { + ISA_ARMv3m,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv3m }, { - "arm7dm", - TARGET_CPU_arm7dm, - (TF_CO_PROC), - "3M", BASE_ARCH_3M, { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit + "arm7dm", + NULL, + { + ISA_ARMv3m,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv3m }, { - "arm7dmi", - TARGET_CPU_arm7dmi, - (TF_CO_PROC), - "3M", BASE_ARCH_3M, { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit + "arm7dmi", + NULL, + { + ISA_ARMv3m,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv3m }, { - "arm8", - TARGET_CPU_arm8, - (TF_LDSCHED), - "4", BASE_ARCH_4, { - ISA_ARMv4,isa_bit_mode26, - isa_nobit + "arm8", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4 }, { - "arm810", - TARGET_CPU_arm810, - (TF_LDSCHED), - "4", BASE_ARCH_4, { - ISA_ARMv4,isa_bit_mode26, - isa_nobit + "arm810", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4 }, { - "strongarm", - TARGET_CPU_strongarm, - (TF_LDSCHED | TF_STRONG), - "4", BASE_ARCH_4, { - ISA_ARMv4,isa_bit_mode26, - isa_nobit + "strongarm", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_strongarm_tune + TARGET_ARCH_armv4 }, { - "strongarm110", - TARGET_CPU_strongarm110, - (TF_LDSCHED | TF_STRONG), - "4", BASE_ARCH_4, { - ISA_ARMv4,isa_bit_mode26, - isa_nobit + "strongarm110", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_strongarm_tune + TARGET_ARCH_armv4 }, { - "strongarm1100", - TARGET_CPU_strongarm1100, - (TF_LDSCHED | TF_STRONG), - "4", BASE_ARCH_4, { - ISA_ARMv4,isa_bit_mode26, - isa_nobit + "strongarm1100", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_strongarm_tune + TARGET_ARCH_armv4 }, { - "strongarm1110", - TARGET_CPU_strongarm1110, - (TF_LDSCHED | TF_STRONG), - "4", BASE_ARCH_4, { - ISA_ARMv4,isa_bit_mode26, - isa_nobit + "strongarm1110", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_strongarm_tune + TARGET_ARCH_armv4 }, { - "fa526", - TARGET_CPU_fa526, - (TF_LDSCHED), - "4", BASE_ARCH_4, { - ISA_ARMv4,isa_bit_mode26, - isa_nobit + "fa526", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4 }, { - "fa626", - TARGET_CPU_fa626, - (TF_LDSCHED), - "4", BASE_ARCH_4, { - ISA_ARMv4,isa_bit_mode26, - isa_nobit + "fa626", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4 }, { - "arm7tdmi", - TARGET_CPU_arm7tdmi, - (TF_CO_PROC), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm7tdmi", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm7tdmi-s", - TARGET_CPU_arm7tdmis, - (TF_CO_PROC), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm7tdmi-s", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm710t", - TARGET_CPU_arm710t, - (TF_WBUF), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm710t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm720t", - TARGET_CPU_arm720t, - (TF_WBUF), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm720t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm740t", - TARGET_CPU_arm740t, - (TF_WBUF), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm740t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm9", - TARGET_CPU_arm9, - (TF_LDSCHED), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm9", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm9tdmi", - TARGET_CPU_arm9tdmi, - (TF_LDSCHED), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm9tdmi", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm920", - TARGET_CPU_arm920, - (TF_LDSCHED), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm920", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm920t", - TARGET_CPU_arm920t, - (TF_LDSCHED), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm920t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm922t", - TARGET_CPU_arm922t, - (TF_LDSCHED), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm922t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm940t", - TARGET_CPU_arm940t, - (TF_LDSCHED), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "arm940t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "ep9312", - TARGET_CPU_ep9312, - (TF_LDSCHED), - "4T", BASE_ARCH_4T, { - ISA_ARMv4t, - isa_nobit + "ep9312", + NULL, + { + ISA_ARMv4t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv4t }, { - "arm10tdmi", - TARGET_CPU_arm10tdmi, - (TF_LDSCHED), - "5T", BASE_ARCH_5T, { - ISA_ARMv5t, - isa_nobit + "arm10tdmi", + NULL, + { + ISA_ARMv5t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv5t }, { - "arm1020t", - TARGET_CPU_arm1020t, - (TF_LDSCHED), - "5T", BASE_ARCH_5T, { - ISA_ARMv5t, - isa_nobit + "arm1020t", + NULL, + { + ISA_ARMv5t, + isa_nobit + } }, - NULL, - &arm_fastmul_tune + TARGET_ARCH_armv5t }, { - "arm9e", - TARGET_CPU_arm9e, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm9e", + cpu_opttab_arm9e, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_arm9e, - &arm_9e_tune + TARGET_ARCH_armv5te }, { - "arm946e-s", - TARGET_CPU_arm946es, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm946e-s", + cpu_opttab_arm946es, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_arm946es, - &arm_9e_tune + TARGET_ARCH_armv5te }, { - "arm966e-s", - TARGET_CPU_arm966es, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm966e-s", + cpu_opttab_arm966es, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_arm966es, - &arm_9e_tune + TARGET_ARCH_armv5te }, { - "arm968e-s", - TARGET_CPU_arm968es, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm968e-s", + cpu_opttab_arm968es, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_arm968es, - &arm_9e_tune + TARGET_ARCH_armv5te }, { - "arm10e", - TARGET_CPU_arm10e, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm10e", + cpu_opttab_arm10e, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_arm10e, - &arm_fastmul_tune + TARGET_ARCH_armv5te }, { - "arm1020e", - TARGET_CPU_arm1020e, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm1020e", + cpu_opttab_arm1020e, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_arm1020e, - &arm_fastmul_tune + TARGET_ARCH_armv5te }, { - "arm1022e", - TARGET_CPU_arm1022e, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm1022e", + cpu_opttab_arm1022e, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_arm1022e, - &arm_fastmul_tune + TARGET_ARCH_armv5te }, { - "xscale", - TARGET_CPU_xscale, - (TF_LDSCHED | TF_XSCALE), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - isa_bit_xscale, - isa_nobit + "xscale", + NULL, + { + ISA_ARMv5te, + isa_bit_xscale, + isa_nobit + } }, - NULL, - &arm_xscale_tune + TARGET_ARCH_armv5te }, { - "iwmmxt", - TARGET_CPU_iwmmxt, - (TF_LDSCHED | TF_XSCALE), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, - isa_nobit + "iwmmxt", + NULL, + { + ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, + isa_nobit + } }, - NULL, - &arm_xscale_tune + TARGET_ARCH_iwmmxt }, { - "iwmmxt2", - TARGET_CPU_iwmmxt2, - (TF_LDSCHED | TF_XSCALE), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, - isa_nobit + "iwmmxt2", + NULL, + { + ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, + isa_nobit + } }, - NULL, - &arm_xscale_tune + TARGET_ARCH_iwmmxt2 }, { - "fa606te", - TARGET_CPU_fa606te, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - isa_nobit + "fa606te", + NULL, + { + ISA_ARMv5te, + isa_nobit + } }, - NULL, - &arm_9e_tune + TARGET_ARCH_armv5te }, { - "fa626te", - TARGET_CPU_fa626te, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - isa_nobit + "fa626te", + NULL, + { + ISA_ARMv5te, + isa_nobit + } }, - NULL, - &arm_9e_tune + TARGET_ARCH_armv5te }, { - "fmp626", - TARGET_CPU_fmp626, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - isa_nobit + "fmp626", + NULL, + { + ISA_ARMv5te, + isa_nobit + } }, - NULL, - &arm_9e_tune + TARGET_ARCH_armv5te }, { - "fa726te", - TARGET_CPU_fa726te, - (TF_LDSCHED), - "5TE", BASE_ARCH_5TE, { - ISA_ARMv5te, - isa_nobit + "fa726te", + NULL, + { + ISA_ARMv5te, + isa_nobit + } }, - NULL, - &arm_fa726te_tune + TARGET_ARCH_armv5te }, { - "arm926ej-s", - TARGET_CPU_arm926ejs, - (TF_LDSCHED), - "5TEJ", BASE_ARCH_5TEJ, { - ISA_ARMv5tej, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm926ej-s", + cpu_opttab_arm926ejs, + { + ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_arm926ejs, - &arm_9e_tune + TARGET_ARCH_armv5tej }, { - "arm1026ej-s", - TARGET_CPU_arm1026ejs, - (TF_LDSCHED), - "5TEJ", BASE_ARCH_5TEJ, { - ISA_ARMv5tej, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm1026ej-s", + cpu_opttab_arm1026ejs, + { + ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_arm1026ejs, - &arm_9e_tune + TARGET_ARCH_armv5tej }, { - "arm1136j-s", - TARGET_CPU_arm1136js, - (TF_LDSCHED), - "6J", BASE_ARCH_6J, { - ISA_ARMv6j, - isa_nobit + "arm1136j-s", + NULL, + { + ISA_ARMv6j, + isa_nobit + } }, - NULL, - &arm_9e_tune + TARGET_ARCH_armv6j }, { - "arm1136jf-s", - TARGET_CPU_arm1136jfs, - (TF_LDSCHED), - "6J", BASE_ARCH_6J, { - ISA_ARMv6j, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm1136jf-s", + NULL, + { + ISA_ARMv6j, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - NULL, - &arm_9e_tune + TARGET_ARCH_armv6j }, { - "arm1176jz-s", - TARGET_CPU_arm1176jzs, - (TF_LDSCHED), - "6KZ", BASE_ARCH_6KZ, { - ISA_ARMv6kz, - isa_nobit + "arm1176jz-s", + NULL, + { + ISA_ARMv6kz, + isa_nobit + } }, - NULL, - &arm_9e_tune + TARGET_ARCH_armv6kz }, { - "arm1176jzf-s", - TARGET_CPU_arm1176jzfs, - (TF_LDSCHED), - "6KZ", BASE_ARCH_6KZ, { - ISA_ARMv6kz, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm1176jzf-s", + NULL, + { + ISA_ARMv6kz, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - NULL, - &arm_9e_tune + TARGET_ARCH_armv6kz }, { - "mpcorenovfp", - TARGET_CPU_mpcorenovfp, - (TF_LDSCHED), - "6K", BASE_ARCH_6K, { - ISA_ARMv6k, - isa_nobit + "mpcorenovfp", + NULL, + { + ISA_ARMv6k, + isa_nobit + } }, - NULL, - &arm_9e_tune + TARGET_ARCH_armv6k }, { - "mpcore", - TARGET_CPU_mpcore, - (TF_LDSCHED), - "6K", BASE_ARCH_6K, { - ISA_ARMv6k, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "mpcore", + NULL, + { + ISA_ARMv6k, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - NULL, - &arm_9e_tune + TARGET_ARCH_armv6k }, { - "arm1156t2-s", - TARGET_CPU_arm1156t2s, - (TF_LDSCHED), - "6T2", BASE_ARCH_6T2, { - ISA_ARMv6t2, - isa_nobit + "arm1156t2-s", + NULL, + { + ISA_ARMv6t2, + isa_nobit + } }, - NULL, - &arm_v6t2_tune + TARGET_ARCH_armv6t2 }, { - "arm1156t2f-s", - TARGET_CPU_arm1156t2fs, - (TF_LDSCHED), - "6T2", BASE_ARCH_6T2, { - ISA_ARMv6t2, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit + "arm1156t2f-s", + NULL, + { + ISA_ARMv6t2, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } }, - NULL, - &arm_v6t2_tune + TARGET_ARCH_armv6t2 }, { - "cortex-m1", - TARGET_CPU_cortexm1, - (TF_LDSCHED), - "6M", BASE_ARCH_6M, { - ISA_ARMv6m, - isa_nobit + "cortex-m1", + NULL, + { + ISA_ARMv6m, + isa_nobit + } }, - NULL, - &arm_v6m_tune + TARGET_ARCH_armv6_m }, { - "cortex-m0", - TARGET_CPU_cortexm0, - (TF_LDSCHED), - "6M", BASE_ARCH_6M, { - ISA_ARMv6m, - isa_nobit + "cortex-m0", + NULL, + { + ISA_ARMv6m, + isa_nobit + } }, - NULL, - &arm_v6m_tune + TARGET_ARCH_armv6_m }, { - "cortex-m0plus", - TARGET_CPU_cortexm0plus, - (TF_LDSCHED), - "6M", BASE_ARCH_6M, { - ISA_ARMv6m, - isa_nobit + "cortex-m0plus", + NULL, + { + ISA_ARMv6m, + isa_nobit + } }, - NULL, - &arm_v6m_tune + TARGET_ARCH_armv6_m }, { - "cortex-m1.small-multiply", - TARGET_CPU_cortexm1, - (TF_LDSCHED | TF_SMALLMUL), - "6M", BASE_ARCH_6M, { - ISA_ARMv6m, - isa_nobit + "cortex-m1.small-multiply", + NULL, + { + ISA_ARMv6m, + isa_nobit + } }, - NULL, - &arm_v6m_tune + TARGET_ARCH_armv6_m }, { - "cortex-m0.small-multiply", - TARGET_CPU_cortexm0, - (TF_LDSCHED | TF_SMALLMUL), - "6M", BASE_ARCH_6M, { - ISA_ARMv6m, - isa_nobit + "cortex-m0.small-multiply", + NULL, + { + ISA_ARMv6m, + isa_nobit + } }, - NULL, - &arm_v6m_tune + TARGET_ARCH_armv6_m }, { - "cortex-m0plus.small-multiply", - TARGET_CPU_cortexm0plus, - (TF_LDSCHED | TF_SMALLMUL), - "6M", BASE_ARCH_6M, { - ISA_ARMv6m, - isa_nobit + "cortex-m0plus.small-multiply", + NULL, + { + ISA_ARMv6m, + isa_nobit + } }, - NULL, - &arm_v6m_tune + TARGET_ARCH_armv6_m }, { - "generic-armv7-a", - TARGET_CPU_genericv7a, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7a, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit + "generic-armv7-a", + cpu_opttab_genericv7a, + { + ISA_ARMv7a, + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_genericv7a, - &arm_cortex_tune + TARGET_ARCH_armv7_a }, { - "cortex-a5", - TARGET_CPU_cortexa5, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, - isa_nobit + "cortex-a5", + cpu_opttab_cortexa5, + { + ISA_ARMv7a, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, + isa_nobit + } }, - cpu_opttab_cortexa5, - &arm_cortex_a5_tune + TARGET_ARCH_armv7_a }, { - "cortex-a7", - TARGET_CPU_cortexa7, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit + "cortex-a7", + cpu_opttab_cortexa7, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa7, - &arm_cortex_a7_tune + TARGET_ARCH_armv7ve }, { - "cortex-a8", - TARGET_CPU_cortexa8, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON, - isa_nobit + "cortex-a8", + cpu_opttab_cortexa8, + { + ISA_ARMv7a, + ISA_VFPv3,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa8, - &arm_cortex_a8_tune + TARGET_ARCH_armv7_a }, { - "cortex-a9", - TARGET_CPU_cortexa9, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, - isa_nobit + "cortex-a9", + cpu_opttab_cortexa9, + { + ISA_ARMv7a, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, + isa_nobit + } }, - cpu_opttab_cortexa9, - &arm_cortex_a9_tune + TARGET_ARCH_armv7_a }, { - "cortex-a12", - TARGET_CPU_cortexa17, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit + "cortex-a12", + cpu_opttab_cortexa12, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa12, - &arm_cortex_a12_tune + TARGET_ARCH_armv7ve }, { - "cortex-a15", - TARGET_CPU_cortexa15, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit + "cortex-a15", + cpu_opttab_cortexa15, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa15, - &arm_cortex_a15_tune + TARGET_ARCH_armv7ve }, { - "cortex-a17", - TARGET_CPU_cortexa17, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit + "cortex-a17", + cpu_opttab_cortexa17, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa17, - &arm_cortex_a12_tune + TARGET_ARCH_armv7ve }, { - "cortex-r4", - TARGET_CPU_cortexr4, - (TF_LDSCHED), - "7R", BASE_ARCH_7R, { - ISA_ARMv7r, - isa_nobit + "cortex-r4", + NULL, + { + ISA_ARMv7r, + isa_nobit + } }, - NULL, - &arm_cortex_tune + TARGET_ARCH_armv7_r }, { - "cortex-r4f", - TARGET_CPU_cortexr4f, - (TF_LDSCHED), - "7R", BASE_ARCH_7R, { - ISA_ARMv7r, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit + "cortex-r4f", + NULL, + { + ISA_ARMv7r, + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } }, - NULL, - &arm_cortex_tune + TARGET_ARCH_armv7_r }, { - "cortex-r5", - TARGET_CPU_cortexr5, - (TF_LDSCHED), - "7R", BASE_ARCH_7R, { - ISA_ARMv7r, - isa_bit_adiv, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit + "cortex-r5", + cpu_opttab_cortexr5, + { + ISA_ARMv7r, + isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_cortexr5, - &arm_cortex_tune + TARGET_ARCH_armv7_r }, { - "cortex-r7", - TARGET_CPU_cortexr7, - (TF_LDSCHED), - "7R", BASE_ARCH_7R, { - ISA_ARMv7r, - isa_bit_adiv, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit + "cortex-r7", + cpu_opttab_cortexr7, + { + ISA_ARMv7r, + isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_cortexr7, - &arm_cortex_tune + TARGET_ARCH_armv7_r }, { - "cortex-r8", - TARGET_CPU_cortexr7, - (TF_LDSCHED), - "7R", BASE_ARCH_7R, { - ISA_ARMv7r, - isa_bit_adiv, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit + "cortex-r8", + cpu_opttab_cortexr8, + { + ISA_ARMv7r, + isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } }, - cpu_opttab_cortexr8, - &arm_cortex_tune + TARGET_ARCH_armv7_r }, { - "cortex-m7", - TARGET_CPU_cortexm7, - (TF_LDSCHED), - "7EM", BASE_ARCH_7EM, { - ISA_ARMv7em, - ISA_FPv5,ISA_FP_DBL, - isa_quirk_no_volatile_ce, - isa_nobit + "cortex-m7", + cpu_opttab_cortexm7, + { + ISA_ARMv7em, + ISA_FPv5,ISA_FP_DBL, + isa_quirk_no_volatile_ce, + isa_nobit + } }, - cpu_opttab_cortexm7, - &arm_cortex_m7_tune + TARGET_ARCH_armv7e_m }, { - "cortex-m4", - TARGET_CPU_cortexm4, - (TF_LDSCHED), - "7EM", BASE_ARCH_7EM, { - ISA_ARMv7em, - ISA_VFPv4, - isa_nobit + "cortex-m4", + cpu_opttab_cortexm4, + { + ISA_ARMv7em, + ISA_VFPv4, + isa_nobit + } }, - cpu_opttab_cortexm4, - &arm_v7m_tune + TARGET_ARCH_armv7e_m }, { - "cortex-m3", - TARGET_CPU_cortexm3, - (TF_LDSCHED), - "7M", BASE_ARCH_7M, { - ISA_ARMv7m, - isa_quirk_cm3_ldrd, - isa_nobit + "cortex-m3", + NULL, + { + ISA_ARMv7m, + isa_quirk_cm3_ldrd, + isa_nobit + } }, - NULL, - &arm_v7m_tune + TARGET_ARCH_armv7_m }, { - "marvell-pj4", - TARGET_CPU_marvell_pj4, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7a, - isa_nobit + "marvell-pj4", + NULL, + { + ISA_ARMv7a, + isa_nobit + } }, - NULL, - &arm_marvell_pj4_tune + TARGET_ARCH_armv7_a }, { - "cortex-a15.cortex-a7", - TARGET_CPU_cortexa7, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit + "cortex-a15.cortex-a7", + cpu_opttab_cortexa15cortexa7, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa15cortexa7, - &arm_cortex_a15_tune + TARGET_ARCH_armv7ve }, { - "cortex-a17.cortex-a7", - TARGET_CPU_cortexa7, - (TF_LDSCHED), - "7A", BASE_ARCH_7A, { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit + "cortex-a17.cortex-a7", + cpu_opttab_cortexa17cortexa7, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa17cortexa7, - &arm_cortex_a12_tune + TARGET_ARCH_armv7ve }, { - "cortex-a32", - TARGET_CPU_cortexa53, - (TF_LDSCHED), - "8A", BASE_ARCH_8A, { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit + "cortex-a32", + cpu_opttab_cortexa32, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa32, - &arm_cortex_a35_tune + TARGET_ARCH_armv8_a }, { - "cortex-a35", - TARGET_CPU_cortexa53, - (TF_LDSCHED), - "8A", BASE_ARCH_8A, { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit + "cortex-a35", + cpu_opttab_cortexa35, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa35, - &arm_cortex_a35_tune + TARGET_ARCH_armv8_a }, { - "cortex-a53", - TARGET_CPU_cortexa53, - (TF_LDSCHED), - "8A", BASE_ARCH_8A, { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit + "cortex-a53", + cpu_opttab_cortexa53, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa53, - &arm_cortex_a53_tune + TARGET_ARCH_armv8_a }, { - "cortex-a57", - TARGET_CPU_cortexa57, - (TF_LDSCHED), - "8A", BASE_ARCH_8A, { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit + "cortex-a57", + cpu_opttab_cortexa57, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa57, - &arm_cortex_a57_tune + TARGET_ARCH_armv8_a }, { - "cortex-a72", - TARGET_CPU_cortexa57, - (TF_LDSCHED), - "8A", BASE_ARCH_8A, { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit + "cortex-a72", + cpu_opttab_cortexa72, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } }, - cpu_opttab_cortexa72, - &arm_cortex_a57_tune + TARGET_ARCH_armv8_a }, { - "cortex-a73", - TARGET_CPU_cortexa57, - (TF_LDSCHED), - "8A", BASE_ARCH_8A, { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit + "cortex-a73", + cpu_opttab_cortexa73, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "exynos-m1", + cpu_opttab_exynosm1, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "xgene1", + cpu_opttab_xgene1, + { + ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a57.cortex-a53", + cpu_opttab_cortexa57cortexa53, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a72.cortex-a53", + cpu_opttab_cortexa72cortexa53, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a73.cortex-a35", + cpu_opttab_cortexa73cortexa35, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a73.cortex-a53", + cpu_opttab_cortexa73cortexa53, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-m23", + NULL, + { + ISA_ARMv8m_base, + isa_nobit + } + }, + TARGET_ARCH_armv8_m_base + }, + { + { + "cortex-m33", + cpu_opttab_cortexm33, + { + ISA_ARMv8m_main, + isa_bit_ARMv7em, + ISA_FPv5, + isa_nobit + } }, - cpu_opttab_cortexa73, + TARGET_ARCH_armv8_m_main + }, + {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none} +}; +static const cpu_tune all_tunes[] = +{ + { /* arm2. */ + TARGET_CPU_arm2, + (TF_CO_PROC | TF_NO_MODE32), + &arm_slowmul_tune + }, + { /* arm250. */ + TARGET_CPU_arm250, + (TF_CO_PROC | TF_NO_MODE32), + &arm_slowmul_tune + }, + { /* arm3. */ + TARGET_CPU_arm3, + (TF_CO_PROC | TF_NO_MODE32), + &arm_slowmul_tune + }, + { /* arm6. */ + TARGET_CPU_arm6, + (TF_CO_PROC), + &arm_slowmul_tune + }, + { /* arm60. */ + TARGET_CPU_arm60, + (TF_CO_PROC), + &arm_slowmul_tune + }, + { /* arm600. */ + TARGET_CPU_arm600, + (TF_CO_PROC | TF_WBUF), + &arm_slowmul_tune + }, + { /* arm610. */ + TARGET_CPU_arm610, + (TF_WBUF), + &arm_slowmul_tune + }, + { /* arm620. */ + TARGET_CPU_arm620, + (TF_CO_PROC | TF_WBUF), + &arm_slowmul_tune + }, + { /* arm7. */ + TARGET_CPU_arm7, + (TF_CO_PROC), + &arm_slowmul_tune + }, + { /* arm7d. */ + TARGET_CPU_arm7d, + (TF_CO_PROC), + &arm_slowmul_tune + }, + { /* arm7di. */ + TARGET_CPU_arm7di, + (TF_CO_PROC), + &arm_slowmul_tune + }, + { /* arm70. */ + TARGET_CPU_arm70, + (TF_CO_PROC), + &arm_slowmul_tune + }, + { /* arm700. */ + TARGET_CPU_arm700, + (TF_CO_PROC | TF_WBUF), + &arm_slowmul_tune + }, + { /* arm700i. */ + TARGET_CPU_arm700i, + (TF_CO_PROC | TF_WBUF), + &arm_slowmul_tune + }, + { /* arm710. */ + TARGET_CPU_arm710, + (TF_WBUF), + &arm_slowmul_tune + }, + { /* arm720. */ + TARGET_CPU_arm720, + (TF_WBUF), + &arm_slowmul_tune + }, + { /* arm710c. */ + TARGET_CPU_arm710c, + (TF_WBUF), + &arm_slowmul_tune + }, + { /* arm7100. */ + TARGET_CPU_arm7100, + (TF_WBUF), + &arm_slowmul_tune + }, + { /* arm7500. */ + TARGET_CPU_arm7500, + (TF_WBUF), + &arm_slowmul_tune + }, + { /* arm7500fe. */ + TARGET_CPU_arm7500fe, + (TF_CO_PROC | TF_WBUF), + &arm_slowmul_tune + }, + { /* arm7m. */ + TARGET_CPU_arm7m, + (TF_CO_PROC), + &arm_fastmul_tune + }, + { /* arm7dm. */ + TARGET_CPU_arm7dm, + (TF_CO_PROC), + &arm_fastmul_tune + }, + { /* arm7dmi. */ + TARGET_CPU_arm7dmi, + (TF_CO_PROC), + &arm_fastmul_tune + }, + { /* arm8. */ + TARGET_CPU_arm8, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm810. */ + TARGET_CPU_arm810, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* strongarm. */ + TARGET_CPU_strongarm, + (TF_LDSCHED | TF_STRONG), + &arm_strongarm_tune + }, + { /* strongarm110. */ + TARGET_CPU_strongarm110, + (TF_LDSCHED | TF_STRONG), + &arm_strongarm_tune + }, + { /* strongarm1100. */ + TARGET_CPU_strongarm1100, + (TF_LDSCHED | TF_STRONG), + &arm_strongarm_tune + }, + { /* strongarm1110. */ + TARGET_CPU_strongarm1110, + (TF_LDSCHED | TF_STRONG), + &arm_strongarm_tune + }, + { /* fa526. */ + TARGET_CPU_fa526, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* fa626. */ + TARGET_CPU_fa626, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm7tdmi. */ + TARGET_CPU_arm7tdmi, + (TF_CO_PROC), + &arm_fastmul_tune + }, + { /* arm7tdmi-s. */ + TARGET_CPU_arm7tdmis, + (TF_CO_PROC), + &arm_fastmul_tune + }, + { /* arm710t. */ + TARGET_CPU_arm710t, + (TF_WBUF), + &arm_fastmul_tune + }, + { /* arm720t. */ + TARGET_CPU_arm720t, + (TF_WBUF), + &arm_fastmul_tune + }, + { /* arm740t. */ + TARGET_CPU_arm740t, + (TF_WBUF), + &arm_fastmul_tune + }, + { /* arm9. */ + TARGET_CPU_arm9, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm9tdmi. */ + TARGET_CPU_arm9tdmi, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm920. */ + TARGET_CPU_arm920, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm920t. */ + TARGET_CPU_arm920t, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm922t. */ + TARGET_CPU_arm922t, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm940t. */ + TARGET_CPU_arm940t, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* ep9312. */ + TARGET_CPU_ep9312, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm10tdmi. */ + TARGET_CPU_arm10tdmi, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm1020t. */ + TARGET_CPU_arm1020t, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm9e. */ + TARGET_CPU_arm9e, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* arm946e-s. */ + TARGET_CPU_arm946es, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* arm966e-s. */ + TARGET_CPU_arm966es, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* arm968e-s. */ + TARGET_CPU_arm968es, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* arm10e. */ + TARGET_CPU_arm10e, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm1020e. */ + TARGET_CPU_arm1020e, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* arm1022e. */ + TARGET_CPU_arm1022e, + (TF_LDSCHED), + &arm_fastmul_tune + }, + { /* xscale. */ + TARGET_CPU_xscale, + (TF_LDSCHED | TF_XSCALE), + &arm_xscale_tune + }, + { /* iwmmxt. */ + TARGET_CPU_iwmmxt, + (TF_LDSCHED | TF_XSCALE), + &arm_xscale_tune + }, + { /* iwmmxt2. */ + TARGET_CPU_iwmmxt2, + (TF_LDSCHED | TF_XSCALE), + &arm_xscale_tune + }, + { /* fa606te. */ + TARGET_CPU_fa606te, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* fa626te. */ + TARGET_CPU_fa626te, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* fmp626. */ + TARGET_CPU_fmp626, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* fa726te. */ + TARGET_CPU_fa726te, + (TF_LDSCHED), + &arm_fa726te_tune + }, + { /* arm926ej-s. */ + TARGET_CPU_arm926ejs, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* arm1026ej-s. */ + TARGET_CPU_arm1026ejs, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* arm1136j-s. */ + TARGET_CPU_arm1136js, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* arm1136jf-s. */ + TARGET_CPU_arm1136jfs, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* arm1176jz-s. */ + TARGET_CPU_arm1176jzs, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* arm1176jzf-s. */ + TARGET_CPU_arm1176jzfs, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* mpcorenovfp. */ + TARGET_CPU_mpcorenovfp, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* mpcore. */ + TARGET_CPU_mpcore, + (TF_LDSCHED), + &arm_9e_tune + }, + { /* arm1156t2-s. */ + TARGET_CPU_arm1156t2s, + (TF_LDSCHED), + &arm_v6t2_tune + }, + { /* arm1156t2f-s. */ + TARGET_CPU_arm1156t2fs, + (TF_LDSCHED), + &arm_v6t2_tune + }, + { /* cortex-m1. */ + TARGET_CPU_cortexm1, + (TF_LDSCHED), + &arm_v6m_tune + }, + { /* cortex-m0. */ + TARGET_CPU_cortexm0, + (TF_LDSCHED), + &arm_v6m_tune + }, + { /* cortex-m0plus. */ + TARGET_CPU_cortexm0plus, + (TF_LDSCHED), + &arm_v6m_tune + }, + { /* cortex-m1.small-multiply. */ + TARGET_CPU_cortexm1, + (TF_LDSCHED | TF_SMALLMUL), + &arm_v6m_tune + }, + { /* cortex-m0.small-multiply. */ + TARGET_CPU_cortexm0, + (TF_LDSCHED | TF_SMALLMUL), + &arm_v6m_tune + }, + { /* cortex-m0plus.small-multiply. */ + TARGET_CPU_cortexm0plus, + (TF_LDSCHED | TF_SMALLMUL), + &arm_v6m_tune + }, + { /* generic-armv7-a. */ + TARGET_CPU_genericv7a, + (TF_LDSCHED), + &arm_cortex_tune + }, + { /* cortex-a5. */ + TARGET_CPU_cortexa5, + (TF_LDSCHED), + &arm_cortex_a5_tune + }, + { /* cortex-a7. */ + TARGET_CPU_cortexa7, + (TF_LDSCHED), + &arm_cortex_a7_tune + }, + { /* cortex-a8. */ + TARGET_CPU_cortexa8, + (TF_LDSCHED), + &arm_cortex_a8_tune + }, + { /* cortex-a9. */ + TARGET_CPU_cortexa9, + (TF_LDSCHED), + &arm_cortex_a9_tune + }, + { /* cortex-a12. */ + TARGET_CPU_cortexa17, + (TF_LDSCHED), + &arm_cortex_a12_tune + }, + { /* cortex-a15. */ + TARGET_CPU_cortexa15, + (TF_LDSCHED), + &arm_cortex_a15_tune + }, + { /* cortex-a17. */ + TARGET_CPU_cortexa17, + (TF_LDSCHED), + &arm_cortex_a12_tune + }, + { /* cortex-r4. */ + TARGET_CPU_cortexr4, + (TF_LDSCHED), + &arm_cortex_tune + }, + { /* cortex-r4f. */ + TARGET_CPU_cortexr4f, + (TF_LDSCHED), + &arm_cortex_tune + }, + { /* cortex-r5. */ + TARGET_CPU_cortexr5, + (TF_LDSCHED), + &arm_cortex_tune + }, + { /* cortex-r7. */ + TARGET_CPU_cortexr7, + (TF_LDSCHED), + &arm_cortex_tune + }, + { /* cortex-r8. */ + TARGET_CPU_cortexr7, + (TF_LDSCHED), + &arm_cortex_tune + }, + { /* cortex-m7. */ + TARGET_CPU_cortexm7, + (TF_LDSCHED), + &arm_cortex_m7_tune + }, + { /* cortex-m4. */ + TARGET_CPU_cortexm4, + (TF_LDSCHED), + &arm_v7m_tune + }, + { /* cortex-m3. */ + TARGET_CPU_cortexm3, + (TF_LDSCHED), + &arm_v7m_tune + }, + { /* marvell-pj4. */ + TARGET_CPU_marvell_pj4, + (TF_LDSCHED), + &arm_marvell_pj4_tune + }, + { /* cortex-a15.cortex-a7. */ + TARGET_CPU_cortexa7, + (TF_LDSCHED), + &arm_cortex_a15_tune + }, + { /* cortex-a17.cortex-a7. */ + TARGET_CPU_cortexa7, + (TF_LDSCHED), + &arm_cortex_a12_tune + }, + { /* cortex-a32. */ + TARGET_CPU_cortexa53, + (TF_LDSCHED), + &arm_cortex_a35_tune + }, + { /* cortex-a35. */ + TARGET_CPU_cortexa53, + (TF_LDSCHED), + &arm_cortex_a35_tune + }, + { /* cortex-a53. */ + TARGET_CPU_cortexa53, + (TF_LDSCHED), + &arm_cortex_a53_tune + }, + { /* cortex-a57. */ + TARGET_CPU_cortexa57, + (TF_LDSCHED), + &arm_cortex_a57_tune + }, + { /* cortex-a72. */ + TARGET_CPU_cortexa57, + (TF_LDSCHED), + &arm_cortex_a57_tune + }, + { /* cortex-a73. */ + TARGET_CPU_cortexa57, + (TF_LDSCHED), &arm_cortex_a73_tune }, - { - "exynos-m1", + { /* exynos-m1. */ TARGET_CPU_exynosm1, (TF_LDSCHED), - "8A", BASE_ARCH_8A, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - cpu_opttab_exynosm1, &arm_exynosm1_tune }, - { - "xgene1", + { /* xgene1. */ TARGET_CPU_xgene1, (TF_LDSCHED), - "8A", BASE_ARCH_8A, - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - cpu_opttab_xgene1, &arm_xgene1_tune }, - { - "cortex-a57.cortex-a53", + { /* cortex-a57.cortex-a53. */ TARGET_CPU_cortexa53, (TF_LDSCHED), - "8A", BASE_ARCH_8A, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - cpu_opttab_cortexa57cortexa53, &arm_cortex_a57_tune }, - { - "cortex-a72.cortex-a53", + { /* cortex-a72.cortex-a53. */ TARGET_CPU_cortexa53, (TF_LDSCHED), - "8A", BASE_ARCH_8A, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - cpu_opttab_cortexa72cortexa53, &arm_cortex_a57_tune }, - { - "cortex-a73.cortex-a35", + { /* cortex-a73.cortex-a35. */ TARGET_CPU_cortexa53, (TF_LDSCHED), - "8A", BASE_ARCH_8A, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - cpu_opttab_cortexa73cortexa35, &arm_cortex_a73_tune }, - { - "cortex-a73.cortex-a53", + { /* cortex-a73.cortex-a53. */ TARGET_CPU_cortexa53, (TF_LDSCHED), - "8A", BASE_ARCH_8A, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - cpu_opttab_cortexa73cortexa53, &arm_cortex_a73_tune }, - { - "cortex-m23", + { /* cortex-m23. */ TARGET_CPU_cortexm23, (TF_LDSCHED), - "8M_BASE", BASE_ARCH_8M_BASE, - { - ISA_ARMv8m_base, - isa_nobit - }, - NULL, &arm_v6m_tune }, - { - "cortex-m33", + { /* cortex-m33. */ TARGET_CPU_cortexm33, (TF_LDSCHED), - "8M_MAIN", BASE_ARCH_8M_MAIN, - { - ISA_ARMv8m_main, - isa_bit_ARMv7em, - ISA_FPv5, - isa_nobit - }, - cpu_opttab_cortexm33, &arm_v7m_tune }, - {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL, NULL} + {TARGET_CPU_arm_none, 0, NULL} }; - -static const struct cpu_option arch_opttab_armv5e[] = { +static const struct cpu_arch_extension arch_opttab_armv5e[] = { { "fp", false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } @@ -1773,7 +2208,7 @@ static const struct cpu_option arch_opttab_armv5e[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv5te[] = { +static const struct cpu_arch_extension arch_opttab_armv5te[] = { { "fp", false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } @@ -1789,7 +2224,7 @@ static const struct cpu_option arch_opttab_armv5te[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv5tej[] = { +static const struct cpu_arch_extension arch_opttab_armv5tej[] = { { "fp", false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } @@ -1805,7 +2240,7 @@ static const struct cpu_option arch_opttab_armv5tej[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv6[] = { +static const struct cpu_arch_extension arch_opttab_armv6[] = { { "fp", false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } @@ -1821,7 +2256,7 @@ static const struct cpu_option arch_opttab_armv6[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv6j[] = { +static const struct cpu_arch_extension arch_opttab_armv6j[] = { { "fp", false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } @@ -1837,7 +2272,7 @@ static const struct cpu_option arch_opttab_armv6j[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv6k[] = { +static const struct cpu_arch_extension arch_opttab_armv6k[] = { { "fp", false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } @@ -1853,7 +2288,7 @@ static const struct cpu_option arch_opttab_armv6k[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv6z[] = { +static const struct cpu_arch_extension arch_opttab_armv6z[] = { { "fp", false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } @@ -1869,7 +2304,7 @@ static const struct cpu_option arch_opttab_armv6z[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv6kz[] = { +static const struct cpu_arch_extension arch_opttab_armv6kz[] = { { "fp", false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } @@ -1885,7 +2320,7 @@ static const struct cpu_option arch_opttab_armv6kz[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv6zk[] = { +static const struct cpu_arch_extension arch_opttab_armv6zk[] = { { "fp", false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } @@ -1901,7 +2336,7 @@ static const struct cpu_option arch_opttab_armv6zk[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv6t2[] = { +static const struct cpu_arch_extension arch_opttab_armv6t2[] = { { "fp", false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } @@ -1917,7 +2352,7 @@ static const struct cpu_option arch_opttab_armv6t2[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv7[] = { +static const struct cpu_arch_extension arch_opttab_armv7[] = { { "fp", false, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } @@ -1929,7 +2364,7 @@ static const struct cpu_option arch_opttab_armv7[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv7_a[] = { +static const struct cpu_arch_extension arch_opttab_armv7_a[] = { { "fp", false, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } @@ -1989,7 +2424,7 @@ static const struct cpu_option arch_opttab_armv7_a[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv7ve[] = { +static const struct cpu_arch_extension arch_opttab_armv7ve[] = { { "vfpv3-d16", false, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } @@ -2049,7 +2484,7 @@ static const struct cpu_option arch_opttab_armv7ve[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv7_r[] = { +static const struct cpu_arch_extension arch_opttab_armv7_r[] = { { "fp.sp", false, { ISA_VFPv3, isa_nobit } @@ -2073,7 +2508,7 @@ static const struct cpu_option arch_opttab_armv7_r[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv7e_m[] = { +static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { { "fp", false, { ISA_VFPv4, isa_nobit } @@ -2093,7 +2528,7 @@ static const struct cpu_option arch_opttab_armv7e_m[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv8_a[] = { +static const struct cpu_arch_extension arch_opttab_armv8_a[] = { { "crc", false, { isa_bit_crc32, isa_nobit } @@ -2117,7 +2552,7 @@ static const struct cpu_option arch_opttab_armv8_a[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv8_1_a[] = { +static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { { "simd", false, { ISA_FP_ARMv8,ISA_NEON, isa_nobit } @@ -2137,7 +2572,7 @@ static const struct cpu_option arch_opttab_armv8_1_a[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv8_2_a[] = { +static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = { { "simd", false, { ISA_FP_ARMv8,ISA_NEON, isa_nobit } @@ -2161,7 +2596,7 @@ static const struct cpu_option arch_opttab_armv8_2_a[] = { { NULL, false, {isa_nobit}} }; -static const struct cpu_option arch_opttab_armv8_m_main[] = { +static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { { "dsp", false, { isa_bit_ARMv7em, isa_nobit } @@ -2181,372 +2616,340 @@ static const struct cpu_option arch_opttab_armv8_m_main[] = { { NULL, false, {isa_nobit}} }; -static const struct processors all_architectures[] = +static const struct arch_option all_architectures[] = { { - "armv2", TARGET_CPU_arm2, - (TF_CO_PROC | TF_NO_MODE32), - "2", BASE_ARCH_2, + "armv2", + NULL, { ISA_ARMv2,isa_bit_mode26, isa_nobit }, - NULL, - NULL + "2", BASE_ARCH_2, + TARGET_CPU_arm2, }, { - "armv2a", TARGET_CPU_arm2, - (TF_CO_PROC | TF_NO_MODE32), - "2", BASE_ARCH_2, + "armv2a", + NULL, { ISA_ARMv2,isa_bit_mode26, isa_nobit }, - NULL, - NULL + "2", BASE_ARCH_2, + TARGET_CPU_arm2, }, { - "armv3", TARGET_CPU_arm6, - (TF_CO_PROC), - "3", BASE_ARCH_3, + "armv3", + NULL, { ISA_ARMv3,isa_bit_mode26, isa_nobit }, - NULL, - NULL + "3", BASE_ARCH_3, + TARGET_CPU_arm6, }, { - "armv3m", TARGET_CPU_arm7m, - (TF_CO_PROC), - "3M", BASE_ARCH_3M, + "armv3m", + NULL, { ISA_ARMv3m,isa_bit_mode26, isa_nobit }, - NULL, - NULL + "3M", BASE_ARCH_3M, + TARGET_CPU_arm7m, }, { - "armv4", TARGET_CPU_arm7tdmi, - (TF_CO_PROC), - "4", BASE_ARCH_4, + "armv4", + NULL, { ISA_ARMv4,isa_bit_mode26, isa_nobit }, - NULL, - NULL + "4", BASE_ARCH_4, + TARGET_CPU_arm7tdmi, }, { - "armv4t", TARGET_CPU_arm7tdmi, - (TF_CO_PROC), - "4T", BASE_ARCH_4T, + "armv4t", + NULL, { ISA_ARMv4t, isa_nobit }, - NULL, - NULL + "4T", BASE_ARCH_4T, + TARGET_CPU_arm7tdmi, }, { - "armv5", TARGET_CPU_arm10tdmi, - (TF_CO_PROC), - "5", BASE_ARCH_5, + "armv5", + NULL, { ISA_ARMv5, isa_nobit }, - NULL, - NULL + "5", BASE_ARCH_5, + TARGET_CPU_arm10tdmi, }, { - "armv5t", TARGET_CPU_arm10tdmi, - (TF_CO_PROC), - "5T", BASE_ARCH_5T, + "armv5t", + NULL, { ISA_ARMv5t, isa_nobit }, - NULL, - NULL + "5T", BASE_ARCH_5T, + TARGET_CPU_arm10tdmi, }, { - "armv5e", TARGET_CPU_arm1026ejs, - (TF_CO_PROC), - "5E", BASE_ARCH_5E, + "armv5e", + arch_opttab_armv5e, { ISA_ARMv5e, isa_nobit }, - arch_opttab_armv5e, - NULL + "5E", BASE_ARCH_5E, + TARGET_CPU_arm1026ejs, }, { - "armv5te", TARGET_CPU_arm1026ejs, - (TF_CO_PROC), - "5TE", BASE_ARCH_5TE, + "armv5te", + arch_opttab_armv5te, { ISA_ARMv5te, isa_nobit }, - arch_opttab_armv5te, - NULL + "5TE", BASE_ARCH_5TE, + TARGET_CPU_arm1026ejs, }, { - "armv5tej", TARGET_CPU_arm1026ejs, - (TF_CO_PROC), - "5TEJ", BASE_ARCH_5TEJ, + "armv5tej", + arch_opttab_armv5tej, { ISA_ARMv5tej, isa_nobit }, - arch_opttab_armv5tej, - NULL + "5TEJ", BASE_ARCH_5TEJ, + TARGET_CPU_arm1026ejs, }, { - "armv6", TARGET_CPU_arm1136js, - (TF_CO_PROC), - "6", BASE_ARCH_6, + "armv6", + arch_opttab_armv6, { ISA_ARMv6, isa_nobit }, - arch_opttab_armv6, - NULL + "6", BASE_ARCH_6, + TARGET_CPU_arm1136js, }, { - "armv6j", TARGET_CPU_arm1136js, - (TF_CO_PROC), - "6J", BASE_ARCH_6J, + "armv6j", + arch_opttab_armv6j, { ISA_ARMv6j, isa_nobit }, - arch_opttab_armv6j, - NULL + "6J", BASE_ARCH_6J, + TARGET_CPU_arm1136js, }, { - "armv6k", TARGET_CPU_mpcore, - (TF_CO_PROC), - "6K", BASE_ARCH_6K, + "armv6k", + arch_opttab_armv6k, { ISA_ARMv6k, isa_nobit }, - arch_opttab_armv6k, - NULL + "6K", BASE_ARCH_6K, + TARGET_CPU_mpcore, }, { - "armv6z", TARGET_CPU_arm1176jzs, - (TF_CO_PROC), - "6Z", BASE_ARCH_6Z, + "armv6z", + arch_opttab_armv6z, { ISA_ARMv6z, isa_nobit }, - arch_opttab_armv6z, - NULL + "6Z", BASE_ARCH_6Z, + TARGET_CPU_arm1176jzs, }, { - "armv6kz", TARGET_CPU_arm1176jzs, - (TF_CO_PROC), - "6KZ", BASE_ARCH_6KZ, + "armv6kz", + arch_opttab_armv6kz, { ISA_ARMv6kz, isa_nobit }, - arch_opttab_armv6kz, - NULL + "6KZ", BASE_ARCH_6KZ, + TARGET_CPU_arm1176jzs, }, { - "armv6zk", TARGET_CPU_arm1176jzs, - (TF_CO_PROC), - "6KZ", BASE_ARCH_6KZ, + "armv6zk", + arch_opttab_armv6zk, { ISA_ARMv6kz, isa_nobit }, - arch_opttab_armv6zk, - NULL + "6KZ", BASE_ARCH_6KZ, + TARGET_CPU_arm1176jzs, }, { - "armv6t2", TARGET_CPU_arm1156t2s, - (TF_CO_PROC), - "6T2", BASE_ARCH_6T2, + "armv6t2", + arch_opttab_armv6t2, { ISA_ARMv6t2, isa_nobit }, - arch_opttab_armv6t2, - NULL + "6T2", BASE_ARCH_6T2, + TARGET_CPU_arm1156t2s, }, { - "armv6-m", TARGET_CPU_cortexm1, - 0, - "6M", BASE_ARCH_6M, + "armv6-m", + NULL, { ISA_ARMv6m, isa_nobit }, - NULL, - NULL + "6M", BASE_ARCH_6M, + TARGET_CPU_cortexm1, }, { - "armv6s-m", TARGET_CPU_cortexm1, - 0, - "6M", BASE_ARCH_6M, + "armv6s-m", + NULL, { ISA_ARMv6m, isa_nobit }, - NULL, - NULL + "6M", BASE_ARCH_6M, + TARGET_CPU_cortexm1, }, { - "armv7", TARGET_CPU_cortexa8, - (TF_CO_PROC), - "7", BASE_ARCH_7, + "armv7", + arch_opttab_armv7, { ISA_ARMv7, isa_nobit }, - arch_opttab_armv7, - NULL + "7", BASE_ARCH_7, + TARGET_CPU_cortexa8, }, { - "armv7-a", TARGET_CPU_cortexa8, - (TF_CO_PROC), - "7A", BASE_ARCH_7A, + "armv7-a", + arch_opttab_armv7_a, { ISA_ARMv7a, isa_nobit }, - arch_opttab_armv7_a, - NULL + "7A", BASE_ARCH_7A, + TARGET_CPU_cortexa8, }, { - "armv7ve", TARGET_CPU_cortexa8, - (TF_CO_PROC), - "7A", BASE_ARCH_7A, + "armv7ve", + arch_opttab_armv7ve, { ISA_ARMv7ve, isa_nobit }, - arch_opttab_armv7ve, - NULL + "7A", BASE_ARCH_7A, + TARGET_CPU_cortexa8, }, { - "armv7-r", TARGET_CPU_cortexr4, - (TF_CO_PROC), - "7R", BASE_ARCH_7R, + "armv7-r", + arch_opttab_armv7_r, { ISA_ARMv7r, isa_nobit }, - arch_opttab_armv7_r, - NULL + "7R", BASE_ARCH_7R, + TARGET_CPU_cortexr4, }, { - "armv7-m", TARGET_CPU_cortexm3, - (TF_CO_PROC), - "7M", BASE_ARCH_7M, + "armv7-m", + NULL, { ISA_ARMv7m, isa_nobit }, - NULL, - NULL + "7M", BASE_ARCH_7M, + TARGET_CPU_cortexm3, }, { - "armv7e-m", TARGET_CPU_cortexm4, - (TF_CO_PROC), - "7EM", BASE_ARCH_7EM, + "armv7e-m", + arch_opttab_armv7e_m, { ISA_ARMv7em, isa_nobit }, - arch_opttab_armv7e_m, - NULL + "7EM", BASE_ARCH_7EM, + TARGET_CPU_cortexm4, }, { - "armv8-a", TARGET_CPU_cortexa53, - (TF_CO_PROC), - "8A", BASE_ARCH_8A, + "armv8-a", + arch_opttab_armv8_a, { ISA_ARMv8a, isa_nobit }, - arch_opttab_armv8_a, - NULL + "8A", BASE_ARCH_8A, + TARGET_CPU_cortexa53, }, { - "armv8.1-a", TARGET_CPU_cortexa53, - (TF_CO_PROC), - "8A", BASE_ARCH_8A, + "armv8.1-a", + arch_opttab_armv8_1_a, { ISA_ARMv8_1a, isa_nobit }, - arch_opttab_armv8_1_a, - NULL + "8A", BASE_ARCH_8A, + TARGET_CPU_cortexa53, }, { - "armv8.2-a", TARGET_CPU_cortexa53, - (TF_CO_PROC), - "8A", BASE_ARCH_8A, + "armv8.2-a", + arch_opttab_armv8_2_a, { ISA_ARMv8_2a, isa_nobit }, - arch_opttab_armv8_2_a, - NULL + "8A", BASE_ARCH_8A, + TARGET_CPU_cortexa53, }, { - "armv8-m.base", TARGET_CPU_cortexm23, - 0, - "8M_BASE", BASE_ARCH_8M_BASE, + "armv8-m.base", + NULL, { ISA_ARMv8m_base, isa_nobit }, - NULL, - NULL + "8M_BASE", BASE_ARCH_8M_BASE, + TARGET_CPU_cortexm23, }, { - "armv8-m.main", TARGET_CPU_cortexm7, - (TF_CO_PROC), - "8M_MAIN", BASE_ARCH_8M_MAIN, + "armv8-m.main", + arch_opttab_armv8_m_main, { ISA_ARMv8m_main, isa_nobit }, - arch_opttab_armv8_m_main, - NULL + "8M_MAIN", BASE_ARCH_8M_MAIN, + TARGET_CPU_cortexm7, }, { - "iwmmxt", TARGET_CPU_iwmmxt, - (TF_LDSCHED | TF_STRONG | TF_XSCALE), - "5TE", BASE_ARCH_5TE, + "iwmmxt", + NULL, { ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, isa_nobit }, - NULL, - NULL + "5TE", BASE_ARCH_5TE, + TARGET_CPU_iwmmxt, }, { - "iwmmxt2", TARGET_CPU_iwmmxt2, - (TF_LDSCHED | TF_STRONG | TF_XSCALE), - "5TE", BASE_ARCH_5TE, + "iwmmxt2", + NULL, { ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, isa_nobit }, - NULL, - NULL + "5TE", BASE_ARCH_5TE, + TARGET_CPU_iwmmxt2, }, - {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL, NULL} + {{NULL, NULL, {isa_nobit}}, + NULL, BASE_ARCH_0, TARGET_CPU_arm_none} }; const struct arm_fpu_desc all_fpus[] = diff --git a/gcc/config/arm/arm-cpu.h b/gcc/config/arm/arm-cpu.h index cc0cb00..e27634c 100644 --- a/gcc/config/arm/arm-cpu.h +++ b/gcc/config/arm/arm-cpu.h @@ -133,6 +133,44 @@ enum processor_type TARGET_CPU_arm_none }; +enum arch_type +{ + TARGET_ARCH_armv2, + TARGET_ARCH_armv2a, + TARGET_ARCH_armv3, + TARGET_ARCH_armv3m, + TARGET_ARCH_armv4, + TARGET_ARCH_armv4t, + TARGET_ARCH_armv5, + TARGET_ARCH_armv5t, + TARGET_ARCH_armv5e, + TARGET_ARCH_armv5te, + TARGET_ARCH_armv5tej, + TARGET_ARCH_armv6, + TARGET_ARCH_armv6j, + TARGET_ARCH_armv6k, + TARGET_ARCH_armv6z, + TARGET_ARCH_armv6kz, + TARGET_ARCH_armv6zk, + TARGET_ARCH_armv6t2, + TARGET_ARCH_armv6_m, + TARGET_ARCH_armv6s_m, + TARGET_ARCH_armv7, + TARGET_ARCH_armv7_a, + TARGET_ARCH_armv7ve, + TARGET_ARCH_armv7_r, + TARGET_ARCH_armv7_m, + TARGET_ARCH_armv7e_m, + TARGET_ARCH_armv8_a, + TARGET_ARCH_armv8_1_a, + TARGET_ARCH_armv8_2_a, + TARGET_ARCH_armv8_m_base, + TARGET_ARCH_armv8_m_main, + TARGET_ARCH_iwmmxt, + TARGET_ARCH_iwmmxt2, + TARGET_ARCH_arm_none +}; + enum fpu_type { TARGET_FPU_vfp, diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index cf8b437..ada2503 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -462,8 +462,6 @@ struct arm_build_target const char *arch_name; /* Preprocessor substring (never NULL). */ const char *arch_pp_name; - /* CPU identifier for the core we're compiling for (architecturally). */ - enum processor_type arch_core; /* The base architecture value. */ enum base_architecture base_arch; /* Bitmap encapsulating the isa_bits for the target environment. */ @@ -478,5 +476,41 @@ struct arm_build_target extern struct arm_build_target arm_active_target; +struct cpu_arch_extension +{ + const char *const name; + bool remove; + const enum isa_feature isa_bits[isa_num_bits]; +}; + +struct cpu_arch_option +{ + /* Name for this option. */ + const char *name; + /* List of feature extensions permitted. */ + const struct cpu_arch_extension *extensions; + /* Standard feature bits. */ + enum isa_feature isa_bits[isa_num_bits]; +}; + +struct arch_option +{ + /* Common option fields. */ + cpu_arch_option common; + /* Short string for this architecture. */ + const char *arch; + /* Base architecture, from which this specific architecture is derived. */ + enum base_architecture base_arch; + /* Default tune target (in the absence of any more specific data). */ + enum processor_type tune_id; +}; + +struct cpu_option +{ + /* Common option fields. */ + cpu_arch_option common; + /* Architecture upon which this CPU is based. */ + enum arch_type arch; +}; #endif /* ! GCC_ARM_PROTOS_H */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 2cffd49..dbba1d3 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -975,26 +975,13 @@ int arm_regs_in_sequence[] = /* Initialization code. */ -struct cpu_option +struct cpu_tune { - const char *const name; - bool remove; - const enum isa_feature isa_bits[isa_num_bits]; -}; - -struct processors -{ - const char *const name; - enum processor_type core; + enum processor_type scheduler; unsigned int tune_flags; - const char *arch; - enum base_architecture base_arch; - const enum isa_feature isa_bits[isa_num_bits]; - const struct cpu_option* const opttab; - const struct tune_params *const tune; + const struct tune_params *tune; }; - #define ARM_PREFETCH_NOT_BENEFICIAL { 0, -1, -1 } #define ARM_PREFETCH_BENEFICIAL(num_slots,l1_size,l1_line_size) \ { \ @@ -3047,15 +3034,59 @@ arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits) bitmap_set_bit (isa, *(isa_bits++)); } -/* List the permitted CPU or architecture names. If TARGET is a near +/* List the permitted CPU option names. If TARGET is a near miss for an + entry, print out the suggested alternative. */ +static void +arm_print_hint_for_cpu_option (const char *target, + const cpu_option *list) +{ + auto_vec candidates; + for (; list->common.name != NULL; list++) + candidates.safe_push (list->common.name); + char *s; + const char *hint = candidates_list_and_hint (target, s, candidates); + if (hint) + inform (input_location, "valid arguments are: %s; did you mean %qs?", + s, hint); + else + inform (input_location, "valid arguments are: %s", s); + + XDELETEVEC (s); +} + +/* Parse the base component of a CPU selection in LIST. Return a + pointer to the entry in the architecture table. OPTNAME is the + name of the option we are parsing and can be used if a diagnostic + is needed. */ +static const cpu_option * +arm_parse_cpu_option_name (const cpu_option *list, const char *optname, + const char *target) +{ + const cpu_option *entry; + const char *end = strchr (target, '+'); + size_t len = end ? end - target : strlen (target); + + for (entry = list; entry->common.name != NULL; entry++) + { + if (strncmp (entry->common.name, target, len) == 0 + && entry->common.name[len] == '\0') + return entry; + } + + error_at (input_location, "unrecognized %s target: %s", optname, target); + arm_print_hint_for_cpu_option (target, list); + return NULL; +} + +/* List the permitted architecture option names. If TARGET is a near miss for an entry, print out the suggested alternative. */ static void -arm_print_hint_for_core_or_arch (const char *target, - const struct processors *list) +arm_print_hint_for_arch_option (const char *target, + const arch_option *list) { auto_vec candidates; - for (; list->name != NULL; list++) - candidates.safe_push (list->name); + for (; list->common.name != NULL; list++) + candidates.safe_push (list->common.name); char *s; const char *hint = candidates_list_and_hint (target, s, candidates); if (hint) @@ -3071,23 +3102,23 @@ arm_print_hint_for_core_or_arch (const char *target, LIST. Return a pointer to the entry in the architecture table. OPTNAME is the name of the option we are parsing and can be used if a diagnostic is needed. */ -static const struct processors * -arm_parse_arch_cpu_name (const struct processors *list, const char *optname, - const char *target) +static const arch_option * +arm_parse_arch_option_name (const arch_option *list, const char *optname, + const char *target) { - const struct processors *entry; + const arch_option *entry; const char *end = strchr (target, '+'); size_t len = end ? end - target : strlen (target); - for (entry = list; entry->name != NULL; entry++) + for (entry = list; entry->common.name != NULL; entry++) { - if (strncmp (entry->name, target, len) == 0 - && entry->name[len] == '\0') + if (strncmp (entry->common.name, target, len) == 0 + && entry->common.name[len] == '\0') return entry; } error_at (input_location, "unrecognized %s target: %s", optname, target); - arm_print_hint_for_core_or_arch (target, list); + arm_print_hint_for_arch_option (target, list); return NULL; } @@ -3096,7 +3127,7 @@ arm_parse_arch_cpu_name (const struct processors *list, const char *optname, values. */ static void arm_unrecognized_feature (const char *opt, size_t len, - const struct processors *target) + const cpu_arch_option *target) { char *this_opt = XALLOCAVEC (char, len+1); auto_vec candidates; @@ -3106,7 +3137,9 @@ arm_unrecognized_feature (const char *opt, size_t len, error_at (input_location, "%qs does not support feature %qs", target->name, this_opt); - for (const cpu_option *list = target->opttab; list->name != NULL; list++) + for (const cpu_arch_extension *list = target->extensions; + list->name != NULL; + list++) candidates.safe_push (list->name); char *s; @@ -3124,15 +3157,15 @@ arm_unrecognized_feature (const char *opt, size_t len, /* Parse any feature extensions to add to (or remove from) the permitted ISA selection. */ static void -arm_parse_arch_cpu_features (sbitmap isa, const struct processors *target, - const char *opts_in) +arm_parse_option_features (sbitmap isa, const cpu_arch_option *target, + const char *opts_in) { const char *opts = opts_in; if (!opts) return; - if (!target->opttab) + if (!target->extensions) { error_at (input_location, "%s does not take any feature options", target->name); @@ -3142,12 +3175,14 @@ arm_parse_arch_cpu_features (sbitmap isa, const struct processors *target, while (opts) { gcc_assert (*opts == '+'); - const struct cpu_option *entry; + const struct cpu_arch_extension *entry; const char *end = strchr (++opts, '+'); size_t len = end ? end - opts : strlen (opts); bool matched = false; - for (entry = target->opttab; !matched && entry->name != NULL; entry++) + for (entry = target->extensions; + !matched && entry->name != NULL; + entry++) { if (strncmp (entry->name, opts, len) == 0 && entry->name[len] == '\0') @@ -3189,10 +3224,10 @@ arm_configure_build_target (struct arm_build_target *target, struct gcc_options *opts_set, bool warn_compatible) { - const struct processors *arm_selected_tune = NULL; - const struct processors *arm_selected_arch = NULL; - const struct processors *arm_selected_cpu = NULL; - const struct arm_fpu_desc *arm_selected_fpu = NULL; + const cpu_option *arm_selected_tune = NULL; + const arch_option *arm_selected_arch = NULL; + const cpu_option *arm_selected_cpu = NULL; + const arm_fpu_desc *arm_selected_fpu = NULL; const char *tune_opts = NULL; const char *arch_opts = NULL; const char *cpu_opts = NULL; @@ -3203,16 +3238,16 @@ arm_configure_build_target (struct arm_build_target *target, if (opts_set->x_arm_arch_string) { - arm_selected_arch = arm_parse_arch_cpu_name (all_architectures, - "-march", - opts->x_arm_arch_string); + arm_selected_arch = arm_parse_arch_option_name (all_architectures, + "-march", + opts->x_arm_arch_string); arch_opts = strchr (opts->x_arm_arch_string, '+'); } if (opts_set->x_arm_cpu_string) { - arm_selected_cpu = arm_parse_arch_cpu_name (all_cores, "-mcpu", - opts->x_arm_cpu_string); + arm_selected_cpu = arm_parse_cpu_option_name (all_cores, "-mcpu", + opts->x_arm_cpu_string); cpu_opts = strchr (opts->x_arm_cpu_string, '+'); arm_selected_tune = arm_selected_cpu; /* If taking the tuning from -mcpu, we don't need to rescan the @@ -3221,73 +3256,83 @@ arm_configure_build_target (struct arm_build_target *target, if (opts_set->x_arm_tune_string) { - arm_selected_tune = arm_parse_arch_cpu_name (all_cores, "-mtune", - opts->x_arm_tune_string); + arm_selected_tune = arm_parse_cpu_option_name (all_cores, "-mtune", + opts->x_arm_tune_string); tune_opts = strchr (opts->x_arm_tune_string, '+'); } if (arm_selected_arch) { - arm_initialize_isa (target->isa, arm_selected_arch->isa_bits); - arm_parse_arch_cpu_features (target->isa, arm_selected_arch, arch_opts); + arm_initialize_isa (target->isa, arm_selected_arch->common.isa_bits); + arm_parse_option_features (target->isa, &arm_selected_arch->common, + arch_opts); if (arm_selected_cpu) { auto_sbitmap cpu_isa (isa_num_bits); + auto_sbitmap isa_delta (isa_num_bits); - arm_initialize_isa (cpu_isa, arm_selected_cpu->isa_bits); - arm_parse_arch_cpu_features (cpu_isa, arm_selected_cpu, cpu_opts); - bitmap_xor (cpu_isa, cpu_isa, target->isa); + arm_initialize_isa (cpu_isa, arm_selected_cpu->common.isa_bits); + arm_parse_option_features (cpu_isa, &arm_selected_cpu->common, + cpu_opts); + bitmap_xor (isa_delta, cpu_isa, target->isa); /* Ignore any bits that are quirk bits. */ - bitmap_and_compl (cpu_isa, cpu_isa, isa_quirkbits); + bitmap_and_compl (isa_delta, isa_delta, isa_quirkbits); /* Ignore (for now) any bits that might be set by -mfpu. */ - bitmap_and_compl (cpu_isa, cpu_isa, isa_all_fpubits); + bitmap_and_compl (isa_delta, isa_delta, isa_all_fpubits); - if (!bitmap_empty_p (cpu_isa)) + if (!bitmap_empty_p (isa_delta)) { if (warn_compatible) warning (0, "switch -mcpu=%s conflicts with -march=%s switch", - arm_selected_cpu->name, arm_selected_arch->name); + arm_selected_cpu->common.name, + arm_selected_arch->common.name); /* -march wins for code generation. -mcpu wins for default tuning. */ if (!arm_selected_tune) arm_selected_tune = arm_selected_cpu; - arm_selected_cpu = arm_selected_arch; - target->arch_name = arm_selected_arch->name; + arm_selected_cpu = all_cores + arm_selected_arch->tune_id; + target->arch_name = arm_selected_arch->common.name; } else { /* Architecture and CPU are essentially the same. Prefer the CPU setting. */ - arm_selected_arch = NULL; - target->core_name = arm_selected_cpu->name; + arm_selected_arch = all_architectures + arm_selected_cpu->arch; + target->core_name = arm_selected_cpu->common.name; + /* Copy the CPU's capabilities, so that we inherit the + appropriate extensions and quirks. */ + bitmap_copy (target->isa, cpu_isa); } } else { /* Pick a CPU based on the architecture. */ - arm_selected_cpu = arm_selected_arch; - target->arch_name = arm_selected_arch->name; + arm_selected_cpu = all_cores + arm_selected_arch->tune_id; + target->arch_name = arm_selected_arch->common.name; /* Note: target->core_name is left unset in this path. */ } } else if (arm_selected_cpu) { - target->core_name = arm_selected_cpu->name; - arm_initialize_isa (target->isa, arm_selected_cpu->isa_bits); - arm_parse_arch_cpu_features (target->isa, arm_selected_cpu, cpu_opts); + target->core_name = arm_selected_cpu->common.name; + arm_initialize_isa (target->isa, arm_selected_cpu->common.isa_bits); + arm_parse_option_features (target->isa, &arm_selected_cpu->common, + cpu_opts); + arm_selected_arch = all_architectures + arm_selected_cpu->arch; } - /* If the user did not specify a processor, choose one for them. */ + /* If the user did not specify a processor or architecture, choose + one for them. */ else { - const struct processors * sel; + const cpu_option *sel; auto_sbitmap sought_isa (isa_num_bits); bitmap_clear (sought_isa); auto_sbitmap default_isa (isa_num_bits); arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT]; - gcc_assert (arm_selected_cpu->name); + gcc_assert (arm_selected_cpu->common.name); /* RWE: All of the selection logic below (to the end of this 'if' clause) looks somewhat suspect. It appears to be mostly @@ -3296,7 +3341,7 @@ arm_configure_build_target (struct arm_build_target *target, user might be expecting). I think it should be removed once support for the pre-thumb era cores is removed. */ sel = arm_selected_cpu; - arm_initialize_isa (default_isa, sel->isa_bits); + arm_initialize_isa (default_isa, sel->common.isa_bits); /* Now check to see if the user has specified any command line switches that require certain abilities from the cpu. */ @@ -3329,18 +3374,18 @@ arm_configure_build_target (struct arm_build_target *target, /* Try to locate a CPU type that supports all of the abilities of the default CPU, plus the extra abilities requested by the user. */ - for (sel = all_cores; sel->name != NULL; sel++) + for (sel = all_cores; sel->common.name != NULL; sel++) { - arm_initialize_isa (candidate_isa, sel->isa_bits); + arm_initialize_isa (candidate_isa, sel->common.isa_bits); /* An exact match? */ if (bitmap_equal_p (default_isa, candidate_isa)) break; } - if (sel->name == NULL) + if (sel->common.name == NULL) { unsigned current_bit_count = isa_num_bits; - const struct processors * best_fit = NULL; + const cpu_option *best_fit = NULL; /* Ideally we would like to issue an error message here saying that it was not possible to find a CPU compatible @@ -3354,9 +3399,9 @@ arm_configure_build_target (struct arm_build_target *target, command line options we scan the array again looking for a best match. The best match must have at least the capabilities of the perfect match. */ - for (sel = all_cores; sel->name != NULL; sel++) + for (sel = all_cores; sel->common.name != NULL; sel++) { - arm_initialize_isa (candidate_isa, sel->isa_bits); + arm_initialize_isa (candidate_isa, sel->common.isa_bits); if (bitmap_subset_p (default_isa, candidate_isa)) { @@ -3382,11 +3427,13 @@ arm_configure_build_target (struct arm_build_target *target, /* Now we know the CPU, we can finally initialize the target structure. */ - target->core_name = arm_selected_cpu->name; - arm_initialize_isa (target->isa, arm_selected_cpu->isa_bits); + target->core_name = arm_selected_cpu->common.name; + arm_initialize_isa (target->isa, arm_selected_cpu->common.isa_bits); + arm_selected_arch = all_architectures + arm_selected_cpu->arch; } gcc_assert (arm_selected_cpu); + gcc_assert (arm_selected_arch); if (opts->x_arm_fpu_index != TARGET_FPU_auto) { @@ -3398,20 +3445,20 @@ arm_configure_build_target (struct arm_build_target *target, bitmap_ior (target->isa, target->isa, fpu_bits); } - /* The selected cpu may be an architecture, so lookup tuning by core ID. */ if (!arm_selected_tune) - arm_selected_tune = &all_cores[arm_selected_cpu->core]; + arm_selected_tune = arm_selected_cpu; else /* Validate the features passed to -mtune. */ - arm_parse_arch_cpu_features (NULL, arm_selected_tune, tune_opts); + arm_parse_option_features (NULL, &arm_selected_tune->common, tune_opts); + + const cpu_tune *tune_data = &all_tunes[arm_selected_tune - all_cores]; /* Finish initializing the target structure. */ - target->arch_pp_name = arm_selected_cpu->arch; - target->base_arch = arm_selected_cpu->base_arch; - target->arch_core = arm_selected_cpu->core; + target->arch_pp_name = arm_selected_arch->arch; + target->base_arch = arm_selected_arch->base_arch; - target->tune_flags = arm_selected_tune->tune_flags; - target->tune = arm_selected_tune->tune; - target->tune_core = arm_selected_tune->core; + target->tune_flags = tune_data->tune_flags; + target->tune = tune_data->tune; + target->tune_core = tune_data->scheduler; } /* Fix up any incompatible options that the user has specified. */ @@ -26283,18 +26330,20 @@ arm_print_tune_info (void) static void arm_print_asm_arch_directives () { - const struct processors *arch - = arm_parse_arch_cpu_name (all_architectures, "-march", - arm_active_target.arch_name); + const arch_option *arch + = arm_parse_arch_option_name (all_architectures, "-march", + arm_active_target.arch_name); auto_sbitmap opt_bits (isa_num_bits); gcc_assert (arch); asm_fprintf (asm_out_file, "\t.arch %s\n", arm_active_target.arch_name); - if (!arch->opttab) + if (!arch->common.extensions) return; - for (const struct cpu_option *opt = arch->opttab; opt->name != NULL; opt++) + for (const struct cpu_arch_extension *opt = arch->common.extensions; + opt->name != NULL; + opt++) { if (!opt->remove) { diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index c95d922..57565bd 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -102,6 +102,17 @@ function gen_headers () { print " TARGET_CPU_arm_none" print "};\n" + print "enum arch_type" + print "{" + + narchs = split (arch_list, archs) + + for (n = 1; n <= narchs; n++) { + print " TARGET_ARCH_"arch_cnames[archs[n]]"," + } + print " TARGET_ARCH_arm_none" + print "};\n" + print "enum fpu_type" print "{" @@ -121,7 +132,7 @@ function gen_data () { for (n = 1; n <= ncpus; n++) { if (cpus[n] in cpu_opts) { - print "static const struct cpu_option cpu_opttab_" \ + print "static const cpu_arch_extension cpu_opttab_" \ cpu_cnames[cpus[n]] "[] = {" nopts = split (cpu_opts[cpus[n]], opts) for (opt = 1; opt <= nopts; opt++) { @@ -136,32 +147,25 @@ function gen_data () { } } - print "static const struct processors all_cores[] =" + print "static const cpu_option all_cores[] =" print "{" for (n = 1; n <= ncpus; n++) { print " {" - print " \"" cpus[n] "\"," - if (cpus[n] in cpu_tune_for) { - if (! (cpu_tune_for[cpus[n]] in cpu_cnames)) { - fatal("unknown \"tune for\" target " cpu_tune_for[cpus[n]] \ - " for CPU " cpus[n]) - } - print " TARGET_CPU_" cpu_cnames[cpu_tune_for[cpus[n]]] "," - } else { - print " TARGET_CPU_" cpu_cnames[cpus[n]] "," - } - if (cpus[n] in cpu_tune_flags) { - print " (" cpu_tune_flags[cpus[n]] ")," - } else print " 0," + print " {" + # common.name + print " \"" cpus[n] "\"," + # common.extensions + if (cpus[n] in cpu_opts) { + print " cpu_opttab_" cpu_cnames[cpus[n]] "," + } else print " NULL," + # common.isa_bits nfeats = split (cpu_arch[cpus[n]], feats, "+") if (! (feats[1] in arch_isa)) { fatal("unknown arch " feats[1] " for cpu " cpus[n]) } - print " \"" arch_base[feats[1]] "\", BASE_ARCH_" \ - arch_base[feats[1]] "," - print " {" - print " " arch_isa[feats[1]] "," + print " {" + print " " arch_isa[feats[1]] "," for (m = 2; m <= nfeats; m++) { if (! ((feats[1], feats[m]) in arch_opt_isa)) { fatal("unknown feature " feats[m] " for architecture " feats[1]) @@ -169,28 +173,52 @@ function gen_data () { if (arch_opt_remove[feats[1],feats[m]] == "true") { fatal("cannot remove features from architecture specs") } - print " " arch_opt_isa[feats[1],feats[m]] "," + print " " arch_opt_isa[feats[1],feats[m]] "," } - if (cpus[n] in cpu_fpu) print " " fpu_isa[cpu_fpu[cpus[n]]] "," - if (cpus[n] in cpu_isa) print " " cpu_isa[cpus[n]] "," - print " isa_nobit" + if (cpus[n] in cpu_fpu) print " " fpu_isa[cpu_fpu[cpus[n]]] "," + if (cpus[n] in cpu_isa) print " " cpu_isa[cpus[n]] "," + print " isa_nobit" + print " }" print " }," - if (cpus[n] in cpu_opts) { - print " cpu_opttab_" cpu_cnames[cpus[n]] "," - } else print " NULL," - print " &arm_" cpu_cost[cpus[n]] "_tune" + # arch + print " TARGET_ARCH_" arch_cnames[feats[1]] print " }," } - print " {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0," \ - " {isa_nobit}, NULL, NULL}" - print "};\n" + print " {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}" + print "};" + print "static const cpu_tune all_tunes[] =" + print "{" + + for (n = 1; n <= ncpus; n++) { + print " { /* " cpus[n] ". */" + # scheduler + if (cpus[n] in cpu_tune_for) { + if (! (cpu_tune_for[cpus[n]] in cpu_cnames)) { + fatal("unknown \"tune for\" target " cpu_tune_for[cpus[n]] \ + " for CPU " cpus[n]) + } + print " TARGET_CPU_" cpu_cnames[cpu_tune_for[cpus[n]]] "," + } else { + print " TARGET_CPU_" cpu_cnames[cpus[n]] "," + } + # tune_flags + if (cpus[n] in cpu_tune_flags) { + print " (" cpu_tune_flags[cpus[n]] ")," + } else print " 0," + # tune + print " &arm_" cpu_cost[cpus[n]] "_tune" + print " }," + } + print " {TARGET_CPU_arm_none, 0, NULL}" + print "};" + narchs = split (arch_list, archs) for (n = 1; n <= narchs; n++) { if (archs[n] in arch_opts) { - print "static const struct cpu_option arch_opttab_" \ + print "static const struct cpu_arch_extension arch_opttab_" \ arch_cnames[archs[n]] "[] = {" nopts = split (arch_opts[archs[n]], opts) for (opt = 1; opt <= nopts; opt++) { @@ -205,7 +233,7 @@ function gen_data () { } } - print "static const struct processors all_architectures[] =" + print "static const struct arch_option all_architectures[] =" print "{" for (n = 1; n <= narchs; n++) { @@ -214,26 +242,27 @@ function gen_data () { fatal("unknown \"tune for\" target " arch_tune_for[archs[n]] \ " for architecture " archs[n]) } - print " \"" archs[n] \ - "\", TARGET_CPU_" cpu_cnames[arch_tune_for[archs[n]]] "," - if (archs[n] in arch_tune_flags) { - print " (" arch_tune_flags[archs[n]] ")," - } else print " 0," - print " \"" arch_base[archs[n]] "\", BASE_ARCH_" \ - arch_base[archs[n]] "," + # common.name + print " \"" archs[n] "\"," + # common.extensions + if (archs[n] in arch_opts) { + print " arch_opttab_" arch_cnames[archs[n]] "," + } else print " NULL," + # common.isa_bits print " {" print " " arch_isa[archs[n]] "," print " isa_nobit" print " }," - if (archs[n] in arch_opts) { - print " arch_opttab_" arch_cnames[archs[n]] "," - } else print " NULL," - print " NULL" + # arch, base_arch + print " \"" arch_base[archs[n]] "\", BASE_ARCH_" \ + arch_base[archs[n]] "," + # tune_id + print " TARGET_CPU_" cpu_cnames[arch_tune_for[archs[n]]] "," print " }," } - print " {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0," \ - " {isa_nobit}, NULL, NULL}" + print " {{NULL, NULL, {isa_nobit}}," + print " NULL, BASE_ARCH_0, TARGET_CPU_arm_none}" print "};\n" print "const struct arm_fpu_desc all_fpus[] =" -- cgit v1.1 From 435d12725b9d75e508c5508964d4b03cdcb80cb7 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:03:17 +0000 Subject: [arm] Move cpu and architecture option name parsing This patch has no functional change. The code used for parsing -mcpu, -mtune and -march options is simply moved from arm.c arm-common.c. The list of FPU options is also moved. Subsequent patches will make use of this within the driver. Some small adjustments are needed as a consequence of moving the definitions of the data objects to another object file, in that we no-longer have direct access to the size of the object. * common/config/arm/arm-common.c (arm_initialize_isa): Moved here from config/arm/arm.c. (arm_print_hint_for_cpu_option): Likewise. (arm_print_hint_for_arch_option): Likewise. (arm_parse_cpu_option_name): Likewise. (arm_parse_arch_option_name): Likewise. * config/arm/arm.c (arm_identify_fpu_from_isa): Use the computed number of entries in the all_fpus list. * config/arm/arm-protos.h (all_architectures, all_cores): Declare. (arm_parse_cpu_option_name): Declare. (arm_parse_arch_option_name): Declare. (arm_parse_option_features): Declare. (arm_intialize_isa): Declare. * config/arm/parsecpu.awk (gen_data): Move CPU and architecture data tables to ... (gen_comm_data): ... here. Make definitions non-static. * config/arm/arm-cpu-data.h: Regenerated. * config/arm/arm-cpu-cdata.h: Regenerated. From-SVN: r249287 --- gcc/ChangeLog | 21 + gcc/common/config/arm/arm-common.c | 190 +++ gcc/config/arm/arm-cpu-cdata.h | 2580 ++++++++++++++++++++++++++++++++++++ gcc/config/arm/arm-cpu-data.h | 2538 ----------------------------------- gcc/config/arm/arm-protos.h | 12 + gcc/config/arm/arm.c | 190 +-- gcc/config/arm/parsecpu.awk | 69 +- 7 files changed, 2840 insertions(+), 2760 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 59eafb9..626b6d7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,26 @@ 2017-06-16 Richard Earnshaw + * common/config/arm/arm-common.c (arm_initialize_isa): Moved here from + config/arm/arm.c. + (arm_print_hint_for_cpu_option): Likewise. + (arm_print_hint_for_arch_option): Likewise. + (arm_parse_cpu_option_name): Likewise. + (arm_parse_arch_option_name): Likewise. + * config/arm/arm.c (arm_identify_fpu_from_isa): Use the computed number + of entries in the all_fpus list. + * config/arm/arm-protos.h (all_architectures, all_cores): Declare. + (arm_parse_cpu_option_name): Declare. + (arm_parse_arch_option_name): Declare. + (arm_parse_option_features): Declare. + (arm_intialize_isa): Declare. + * config/arm/parsecpu.awk (gen_data): Move CPU and architecture + data tables to ... + (gen_comm_data): ... here. Make definitions non-static. + * config/arm/arm-cpu-data.h: Regenerated. + * config/arm/arm-cpu-cdata.h: Regenerated. + +2017-06-16 Richard Earnshaw + * config/arm/arm-protos.h (arm_build_target): Remove arch_core. (cpu_arch_extension): New structure. (cpu_arch_option, arch_option, cpu_option): New structures. diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index fd0c616..f44ba1f 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -27,6 +27,8 @@ #include "common/common-target-def.h" #include "opts.h" #include "flags.h" +#include "sbitmap.h" +#include "diagnostic.h" /* Set default optimization options. */ static const struct default_options arm_option_optimization_table[] = @@ -187,6 +189,194 @@ arm_target_thumb_only (int argc, const char **argv) return NULL; } +/* List the permitted CPU option names. If TARGET is a near miss for an + entry, print out the suggested alternative. */ +static void +arm_print_hint_for_cpu_option (const char *target, + const cpu_option *list) +{ + auto_vec candidates; + for (; list->common.name != NULL; list++) + candidates.safe_push (list->common.name); + char *s; + const char *hint = candidates_list_and_hint (target, s, candidates); + if (hint) + inform (input_location, "valid arguments are: %s; did you mean %qs?", + s, hint); + else + inform (input_location, "valid arguments are: %s", s); + + XDELETEVEC (s); +} + +/* Parse the base component of a CPU selection in LIST. Return a + pointer to the entry in the architecture table. OPTNAME is the + name of the option we are parsing and can be used if a diagnostic + is needed. */ +const cpu_option * +arm_parse_cpu_option_name (const cpu_option *list, const char *optname, + const char *target) +{ + const cpu_option *entry; + const char *end = strchr (target, '+'); + size_t len = end ? end - target : strlen (target); + + for (entry = list; entry->common.name != NULL; entry++) + { + if (strncmp (entry->common.name, target, len) == 0 + && entry->common.name[len] == '\0') + return entry; + } + + error_at (input_location, "unrecognized %s target: %s", optname, target); + arm_print_hint_for_cpu_option (target, list); + return NULL; +} + +/* List the permitted architecture option names. If TARGET is a near + miss for an entry, print out the suggested alternative. */ +static void +arm_print_hint_for_arch_option (const char *target, + const arch_option *list) +{ + auto_vec candidates; + for (; list->common.name != NULL; list++) + candidates.safe_push (list->common.name); + char *s; + const char *hint = candidates_list_and_hint (target, s, candidates); + if (hint) + inform (input_location, "valid arguments are: %s; did you mean %qs?", + s, hint); + else + inform (input_location, "valid arguments are: %s", s); + + XDELETEVEC (s); +} + +/* Parse the base component of a CPU or architecture selection in + LIST. Return a pointer to the entry in the architecture table. + OPTNAME is the name of the option we are parsing and can be used if + a diagnostic is needed. */ +const arch_option * +arm_parse_arch_option_name (const arch_option *list, const char *optname, + const char *target) +{ + const arch_option *entry; + const char *end = strchr (target, '+'); + size_t len = end ? end - target : strlen (target); + + for (entry = list; entry->common.name != NULL; entry++) + { + if (strncmp (entry->common.name, target, len) == 0 + && entry->common.name[len] == '\0') + return entry; + } + + error_at (input_location, "unrecognized %s target: %s", optname, target); + arm_print_hint_for_arch_option (target, list); + return NULL; +} + +/* Convert a static initializer array of feature bits to sbitmap + representation. */ +void +arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits) +{ + bitmap_clear (isa); + while (*isa_bits != isa_nobit) + bitmap_set_bit (isa, *(isa_bits++)); +} + +/* OPT isn't a recognized feature. Print a suitable error message and + suggest a possible value. Always print the list of permitted + values. */ +static void +arm_unrecognized_feature (const char *opt, size_t len, + const cpu_arch_option *target) +{ + char *this_opt = XALLOCAVEC (char, len+1); + auto_vec candidates; + + strncpy (this_opt, opt, len); + this_opt[len] = 0; + + error_at (input_location, "%qs does not support feature %qs", target->name, + this_opt); + for (const cpu_arch_extension *list = target->extensions; + list->name != NULL; + list++) + candidates.safe_push (list->name); + + char *s; + const char *hint = candidates_list_and_hint (this_opt, s, candidates); + + if (hint) + inform (input_location, "valid feature names are: %s; did you mean %qs?", + s, hint); + else + inform (input_location, "valid feature names are: %s", s); + + XDELETEVEC (s); +} + +/* Parse any feature extensions to add to (or remove from) the + permitted ISA selection. */ +void +arm_parse_option_features (sbitmap isa, const cpu_arch_option *target, + const char *opts_in) +{ + const char *opts = opts_in; + + if (!opts) + return; + + if (!target->extensions) + { + error_at (input_location, "%s does not take any feature options", + target->name); + return; + } + + while (opts) + { + gcc_assert (*opts == '+'); + const struct cpu_arch_extension *entry; + const char *end = strchr (++opts, '+'); + size_t len = end ? end - opts : strlen (opts); + bool matched = false; + + for (entry = target->extensions; + !matched && entry->name != NULL; + entry++) + { + if (strncmp (entry->name, opts, len) == 0 + && entry->name[len] == '\0') + { + if (isa) + { + const enum isa_feature *f = entry->isa_bits; + if (entry->remove) + { + while (*f != isa_nobit) + bitmap_clear_bit (isa, *(f++)); + } + else + { + while (*f != isa_nobit) + bitmap_set_bit (isa, *(f++)); + } + } + matched = true; + } + } + + if (!matched) + arm_unrecognized_feature (opts, len, target); + + opts = end; + } +} + #undef ARM_CPU_NAME_LENGTH diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index aced3ac..5329bd6 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -20,6 +20,2586 @@ License along with GCC; see the file COPYING3. If not see . */ +static const cpu_arch_extension cpu_opttab_arm9e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_arm946es[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_arm966es[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_arm968es[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_arm10e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_arm1020e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_arm1022e[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_arm926ejs[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_arm1026ejs[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_genericv7a[] = { + { + "simd", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "vfpv3", false, + { ISA_VFPv3,ISA_FP_D32, isa_nobit } + }, + { + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv3-fp16", false, + { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv3-d16-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv4", false, + { ISA_VFPv4,ISA_FP_D32, isa_nobit } + }, + { + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { + "neon", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-vfpv3", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-fp16", false, + { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } + }, + { + "neon-vfpv4", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa5[] = { + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa7[] = { + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa8[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa9[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa12[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa15[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa17[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexr5[] = { + { + "nofp.dp", true, + { ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexr7[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexr8[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexm7[] = { + { + "nofp.dp", true, + { ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexm4[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa32[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa35[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa57[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa72[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa73[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_exynosm1[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_falkor[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_qdf24xx[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_xgene1[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = { + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const cpu_arch_extension cpu_opttab_cortexm33[] = { + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +const cpu_option all_cores[] = +{ + { + { + "arm2", + NULL, + { + ISA_ARMv2,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv2 + }, + { + { + "arm250", + NULL, + { + ISA_ARMv2,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv2 + }, + { + { + "arm3", + NULL, + { + ISA_ARMv2,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv2 + }, + { + { + "arm6", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm60", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm600", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm610", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm620", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm7", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm7d", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm7di", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm70", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm700", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm700i", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm710", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm720", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm710c", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm7100", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm7500", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm7500fe", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3 + }, + { + { + "arm7m", + NULL, + { + ISA_ARMv3m,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3m + }, + { + { + "arm7dm", + NULL, + { + ISA_ARMv3m,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3m + }, + { + { + "arm7dmi", + NULL, + { + ISA_ARMv3m,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv3m + }, + { + { + "arm8", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv4 + }, + { + { + "arm810", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv4 + }, + { + { + "strongarm", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv4 + }, + { + { + "strongarm110", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv4 + }, + { + { + "strongarm1100", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv4 + }, + { + { + "strongarm1110", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv4 + }, + { + { + "fa526", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv4 + }, + { + { + "fa626", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + } + }, + TARGET_ARCH_armv4 + }, + { + { + "arm7tdmi", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm7tdmi-s", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm710t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm720t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm740t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm9", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm9tdmi", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm920", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm920t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm922t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm940t", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "ep9312", + NULL, + { + ISA_ARMv4t, + isa_nobit + } + }, + TARGET_ARCH_armv4t + }, + { + { + "arm10tdmi", + NULL, + { + ISA_ARMv5t, + isa_nobit + } + }, + TARGET_ARCH_armv5t + }, + { + { + "arm1020t", + NULL, + { + ISA_ARMv5t, + isa_nobit + } + }, + TARGET_ARCH_armv5t + }, + { + { + "arm9e", + cpu_opttab_arm9e, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "arm946e-s", + cpu_opttab_arm946es, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "arm966e-s", + cpu_opttab_arm966es, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "arm968e-s", + cpu_opttab_arm968es, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "arm10e", + cpu_opttab_arm10e, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "arm1020e", + cpu_opttab_arm1020e, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "arm1022e", + cpu_opttab_arm1022e, + { + ISA_ARMv5te, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "xscale", + NULL, + { + ISA_ARMv5te, + isa_bit_xscale, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "iwmmxt", + NULL, + { + ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, + isa_nobit + } + }, + TARGET_ARCH_iwmmxt + }, + { + { + "iwmmxt2", + NULL, + { + ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, + isa_nobit + } + }, + TARGET_ARCH_iwmmxt2 + }, + { + { + "fa606te", + NULL, + { + ISA_ARMv5te, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "fa626te", + NULL, + { + ISA_ARMv5te, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "fmp626", + NULL, + { + ISA_ARMv5te, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "fa726te", + NULL, + { + ISA_ARMv5te, + isa_nobit + } + }, + TARGET_ARCH_armv5te + }, + { + { + "arm926ej-s", + cpu_opttab_arm926ejs, + { + ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv5tej + }, + { + { + "arm1026ej-s", + cpu_opttab_arm1026ejs, + { + ISA_ARMv5tej, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv5tej + }, + { + { + "arm1136j-s", + NULL, + { + ISA_ARMv6j, + isa_nobit + } + }, + TARGET_ARCH_armv6j + }, + { + { + "arm1136jf-s", + NULL, + { + ISA_ARMv6j, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv6j + }, + { + { + "arm1176jz-s", + NULL, + { + ISA_ARMv6kz, + isa_nobit + } + }, + TARGET_ARCH_armv6kz + }, + { + { + "arm1176jzf-s", + NULL, + { + ISA_ARMv6kz, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv6kz + }, + { + { + "mpcorenovfp", + NULL, + { + ISA_ARMv6k, + isa_nobit + } + }, + TARGET_ARCH_armv6k + }, + { + { + "mpcore", + NULL, + { + ISA_ARMv6k, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv6k + }, + { + { + "arm1156t2-s", + NULL, + { + ISA_ARMv6t2, + isa_nobit + } + }, + TARGET_ARCH_armv6t2 + }, + { + { + "arm1156t2f-s", + NULL, + { + ISA_ARMv6t2, + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv6t2 + }, + { + { + "cortex-m1", + NULL, + { + ISA_ARMv6m, + isa_nobit + } + }, + TARGET_ARCH_armv6_m + }, + { + { + "cortex-m0", + NULL, + { + ISA_ARMv6m, + isa_nobit + } + }, + TARGET_ARCH_armv6_m + }, + { + { + "cortex-m0plus", + NULL, + { + ISA_ARMv6m, + isa_nobit + } + }, + TARGET_ARCH_armv6_m + }, + { + { + "cortex-m1.small-multiply", + NULL, + { + ISA_ARMv6m, + isa_nobit + } + }, + TARGET_ARCH_armv6_m + }, + { + { + "cortex-m0.small-multiply", + NULL, + { + ISA_ARMv6m, + isa_nobit + } + }, + TARGET_ARCH_armv6_m + }, + { + { + "cortex-m0plus.small-multiply", + NULL, + { + ISA_ARMv6m, + isa_nobit + } + }, + TARGET_ARCH_armv6_m + }, + { + { + "generic-armv7-a", + cpu_opttab_genericv7a, + { + ISA_ARMv7a, + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv7_a + }, + { + { + "cortex-a5", + cpu_opttab_cortexa5, + { + ISA_ARMv7a, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, + isa_nobit + } + }, + TARGET_ARCH_armv7_a + }, + { + { + "cortex-a7", + cpu_opttab_cortexa7, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv7ve + }, + { + { + "cortex-a8", + cpu_opttab_cortexa8, + { + ISA_ARMv7a, + ISA_VFPv3,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv7_a + }, + { + { + "cortex-a9", + cpu_opttab_cortexa9, + { + ISA_ARMv7a, + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, + isa_nobit + } + }, + TARGET_ARCH_armv7_a + }, + { + { + "cortex-a12", + cpu_opttab_cortexa12, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv7ve + }, + { + { + "cortex-a15", + cpu_opttab_cortexa15, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv7ve + }, + { + { + "cortex-a17", + cpu_opttab_cortexa17, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv7ve + }, + { + { + "cortex-r4", + NULL, + { + ISA_ARMv7r, + isa_nobit + } + }, + TARGET_ARCH_armv7_r + }, + { + { + "cortex-r4f", + NULL, + { + ISA_ARMv7r, + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv7_r + }, + { + { + "cortex-r5", + cpu_opttab_cortexr5, + { + ISA_ARMv7r, + isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv7_r + }, + { + { + "cortex-r7", + cpu_opttab_cortexr7, + { + ISA_ARMv7r, + isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv7_r + }, + { + { + "cortex-r8", + cpu_opttab_cortexr8, + { + ISA_ARMv7r, + isa_bit_adiv, + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } + }, + TARGET_ARCH_armv7_r + }, + { + { + "cortex-m7", + cpu_opttab_cortexm7, + { + ISA_ARMv7em, + ISA_FPv5,ISA_FP_DBL, + isa_quirk_no_volatile_ce, + isa_nobit + } + }, + TARGET_ARCH_armv7e_m + }, + { + { + "cortex-m4", + cpu_opttab_cortexm4, + { + ISA_ARMv7em, + ISA_VFPv4, + isa_nobit + } + }, + TARGET_ARCH_armv7e_m + }, + { + { + "cortex-m3", + NULL, + { + ISA_ARMv7m, + isa_quirk_cm3_ldrd, + isa_nobit + } + }, + TARGET_ARCH_armv7_m + }, + { + { + "marvell-pj4", + NULL, + { + ISA_ARMv7a, + isa_nobit + } + }, + TARGET_ARCH_armv7_a + }, + { + { + "cortex-a15.cortex-a7", + cpu_opttab_cortexa15cortexa7, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv7ve + }, + { + { + "cortex-a17.cortex-a7", + cpu_opttab_cortexa17cortexa7, + { + ISA_ARMv7ve, + ISA_VFPv4,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv7ve + }, + { + { + "cortex-a32", + cpu_opttab_cortexa32, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a35", + cpu_opttab_cortexa35, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a53", + cpu_opttab_cortexa53, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a57", + cpu_opttab_cortexa57, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a72", + cpu_opttab_cortexa72, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a73", + cpu_opttab_cortexa73, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "exynos-m1", + cpu_opttab_exynosm1, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "falkor", + cpu_opttab_falkor, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "qdf24xx", + cpu_opttab_qdf24xx, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "xgene1", + cpu_opttab_xgene1, + { + ISA_ARMv8a, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a57.cortex-a53", + cpu_opttab_cortexa57cortexa53, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a72.cortex-a53", + cpu_opttab_cortexa72cortexa53, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a73.cortex-a35", + cpu_opttab_cortexa73cortexa35, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-a73.cortex-a53", + cpu_opttab_cortexa73cortexa53, + { + ISA_ARMv8a, + isa_bit_crc32, + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + TARGET_ARCH_armv8_a + }, + { + { + "cortex-m23", + NULL, + { + ISA_ARMv8m_base, + isa_nobit + } + }, + TARGET_ARCH_armv8_m_base + }, + { + { + "cortex-m33", + cpu_opttab_cortexm33, + { + ISA_ARMv8m_main, + isa_bit_ARMv7em, + ISA_FPv5, + isa_nobit + } + }, + TARGET_ARCH_armv8_m_main + }, + {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none} +}; +static const struct cpu_arch_extension arch_opttab_armv5e[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv5te[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv5tej[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv6[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv6j[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv6k[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv6z[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv6kz[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv6zk[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv6t2[] = { + { + "fp", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv2", false, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv7[] = { + { + "fp", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv7_a[] = { + { + "fp", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv3", false, + { ISA_VFPv3,ISA_FP_D32, isa_nobit } + }, + { + "vfpv3-d16-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv3-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv4", false, + { ISA_VFPv4,ISA_FP_D32, isa_nobit } + }, + { + "simd", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-vfpv3", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-fp16", false, + { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } + }, + { + "neon-vfpv4", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv7ve[] = { + { + "vfpv3-d16", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv3", false, + { ISA_VFPv3,ISA_FP_D32, isa_nobit } + }, + { + "vfpv3-d16-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv3-fp16", false, + { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } + }, + { + "vfpv4-d16", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { + "fp", false, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } + }, + { + "vfpv4", false, + { ISA_VFPv4,ISA_FP_D32, isa_nobit } + }, + { + "neon", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-vfpv3", false, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-fp16", false, + { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } + }, + { + "simd", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "neon-vfpv4", false, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { + "nosimd", true, + { ISA_ALL_SIMD, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv7_r[] = { + { + "fp.sp", false, + { ISA_VFPv3, isa_nobit } + }, + { + "fp", false, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, + { + "idiv", false, + { isa_bit_adiv, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { + "noidiv", true, + { isa_bit_adiv, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { + { + "fp", false, + { ISA_VFPv4, isa_nobit } + }, + { + "fpv5", false, + { ISA_FPv5, isa_nobit } + }, + { + "fp.dp", false, + { ISA_FPv5,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv8_a[] = { + { + "crc", false, + { isa_bit_crc32, isa_nobit } + }, + { + "simd", false, + { ISA_FP_ARMv8,ISA_NEON, isa_nobit } + }, + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { + "nocrypto", true, + { ISA_ALL_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { + { + "simd", false, + { ISA_FP_ARMv8,ISA_NEON, isa_nobit } + }, + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { + "nocrypto", true, + { ISA_ALL_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = { + { + "simd", false, + { ISA_FP_ARMv8,ISA_NEON, isa_nobit } + }, + { + "fp16", false, + { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit } + }, + { + "crypto", false, + { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { + "nocrypto", true, + { ISA_ALL_CRYPTO, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { + { + "dsp", false, + { isa_bit_ARMv7em, isa_nobit } + }, + { + "fp", false, + { ISA_FPv5, isa_nobit } + }, + { + "fp.dp", false, + { ISA_FPv5,ISA_FP_DBL, isa_nobit } + }, + { + "nofp", true, + { ISA_ALL_FP, isa_nobit } + }, + { NULL, false, {isa_nobit}} +}; + +const arch_option all_architectures[] = +{ + { + "armv2", + NULL, + { + ISA_ARMv2,isa_bit_mode26, + isa_nobit + }, + "2", BASE_ARCH_2, + TARGET_CPU_arm2, + }, + { + "armv2a", + NULL, + { + ISA_ARMv2,isa_bit_mode26, + isa_nobit + }, + "2", BASE_ARCH_2, + TARGET_CPU_arm2, + }, + { + "armv3", + NULL, + { + ISA_ARMv3,isa_bit_mode26, + isa_nobit + }, + "3", BASE_ARCH_3, + TARGET_CPU_arm6, + }, + { + "armv3m", + NULL, + { + ISA_ARMv3m,isa_bit_mode26, + isa_nobit + }, + "3M", BASE_ARCH_3M, + TARGET_CPU_arm7m, + }, + { + "armv4", + NULL, + { + ISA_ARMv4,isa_bit_mode26, + isa_nobit + }, + "4", BASE_ARCH_4, + TARGET_CPU_arm7tdmi, + }, + { + "armv4t", + NULL, + { + ISA_ARMv4t, + isa_nobit + }, + "4T", BASE_ARCH_4T, + TARGET_CPU_arm7tdmi, + }, + { + "armv5", + NULL, + { + ISA_ARMv5, + isa_nobit + }, + "5", BASE_ARCH_5, + TARGET_CPU_arm10tdmi, + }, + { + "armv5t", + NULL, + { + ISA_ARMv5t, + isa_nobit + }, + "5T", BASE_ARCH_5T, + TARGET_CPU_arm10tdmi, + }, + { + "armv5e", + arch_opttab_armv5e, + { + ISA_ARMv5e, + isa_nobit + }, + "5E", BASE_ARCH_5E, + TARGET_CPU_arm1026ejs, + }, + { + "armv5te", + arch_opttab_armv5te, + { + ISA_ARMv5te, + isa_nobit + }, + "5TE", BASE_ARCH_5TE, + TARGET_CPU_arm1026ejs, + }, + { + "armv5tej", + arch_opttab_armv5tej, + { + ISA_ARMv5tej, + isa_nobit + }, + "5TEJ", BASE_ARCH_5TEJ, + TARGET_CPU_arm1026ejs, + }, + { + "armv6", + arch_opttab_armv6, + { + ISA_ARMv6, + isa_nobit + }, + "6", BASE_ARCH_6, + TARGET_CPU_arm1136js, + }, + { + "armv6j", + arch_opttab_armv6j, + { + ISA_ARMv6j, + isa_nobit + }, + "6J", BASE_ARCH_6J, + TARGET_CPU_arm1136js, + }, + { + "armv6k", + arch_opttab_armv6k, + { + ISA_ARMv6k, + isa_nobit + }, + "6K", BASE_ARCH_6K, + TARGET_CPU_mpcore, + }, + { + "armv6z", + arch_opttab_armv6z, + { + ISA_ARMv6z, + isa_nobit + }, + "6Z", BASE_ARCH_6Z, + TARGET_CPU_arm1176jzs, + }, + { + "armv6kz", + arch_opttab_armv6kz, + { + ISA_ARMv6kz, + isa_nobit + }, + "6KZ", BASE_ARCH_6KZ, + TARGET_CPU_arm1176jzs, + }, + { + "armv6zk", + arch_opttab_armv6zk, + { + ISA_ARMv6kz, + isa_nobit + }, + "6KZ", BASE_ARCH_6KZ, + TARGET_CPU_arm1176jzs, + }, + { + "armv6t2", + arch_opttab_armv6t2, + { + ISA_ARMv6t2, + isa_nobit + }, + "6T2", BASE_ARCH_6T2, + TARGET_CPU_arm1156t2s, + }, + { + "armv6-m", + NULL, + { + ISA_ARMv6m, + isa_nobit + }, + "6M", BASE_ARCH_6M, + TARGET_CPU_cortexm1, + }, + { + "armv6s-m", + NULL, + { + ISA_ARMv6m, + isa_nobit + }, + "6M", BASE_ARCH_6M, + TARGET_CPU_cortexm1, + }, + { + "armv7", + arch_opttab_armv7, + { + ISA_ARMv7, + isa_nobit + }, + "7", BASE_ARCH_7, + TARGET_CPU_cortexa8, + }, + { + "armv7-a", + arch_opttab_armv7_a, + { + ISA_ARMv7a, + isa_nobit + }, + "7A", BASE_ARCH_7A, + TARGET_CPU_cortexa8, + }, + { + "armv7ve", + arch_opttab_armv7ve, + { + ISA_ARMv7ve, + isa_nobit + }, + "7A", BASE_ARCH_7A, + TARGET_CPU_cortexa8, + }, + { + "armv7-r", + arch_opttab_armv7_r, + { + ISA_ARMv7r, + isa_nobit + }, + "7R", BASE_ARCH_7R, + TARGET_CPU_cortexr4, + }, + { + "armv7-m", + NULL, + { + ISA_ARMv7m, + isa_nobit + }, + "7M", BASE_ARCH_7M, + TARGET_CPU_cortexm3, + }, + { + "armv7e-m", + arch_opttab_armv7e_m, + { + ISA_ARMv7em, + isa_nobit + }, + "7EM", BASE_ARCH_7EM, + TARGET_CPU_cortexm4, + }, + { + "armv8-a", + arch_opttab_armv8_a, + { + ISA_ARMv8a, + isa_nobit + }, + "8A", BASE_ARCH_8A, + TARGET_CPU_cortexa53, + }, + { + "armv8.1-a", + arch_opttab_armv8_1_a, + { + ISA_ARMv8_1a, + isa_nobit + }, + "8A", BASE_ARCH_8A, + TARGET_CPU_cortexa53, + }, + { + "armv8.2-a", + arch_opttab_armv8_2_a, + { + ISA_ARMv8_2a, + isa_nobit + }, + "8A", BASE_ARCH_8A, + TARGET_CPU_cortexa53, + }, + { + "armv8-m.base", + NULL, + { + ISA_ARMv8m_base, + isa_nobit + }, + "8M_BASE", BASE_ARCH_8M_BASE, + TARGET_CPU_cortexm23, + }, + { + "armv8-m.main", + arch_opttab_armv8_m_main, + { + ISA_ARMv8m_main, + isa_nobit + }, + "8M_MAIN", BASE_ARCH_8M_MAIN, + TARGET_CPU_cortexm7, + }, + { + "iwmmxt", + NULL, + { + ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, + isa_nobit + }, + "5TE", BASE_ARCH_5TE, + TARGET_CPU_iwmmxt, + }, + { + "iwmmxt2", + NULL, + { + ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, + isa_nobit + }, + "5TE", BASE_ARCH_5TE, + TARGET_CPU_iwmmxt2, + }, + {{NULL, NULL, {isa_nobit}}, + NULL, BASE_ARCH_0, TARGET_CPU_arm_none} +}; + +const arm_fpu_desc all_fpus[] = +{ + { + "vfp", + { + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + { + "vfpv2", + { + ISA_VFPv2,ISA_FP_DBL, + isa_nobit + } + }, + { + "vfpv3", + { + ISA_VFPv3,ISA_FP_D32, + isa_nobit + } + }, + { + "vfpv3-fp16", + { + ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, + isa_nobit + } + }, + { + "vfpv3-d16", + { + ISA_VFPv3,ISA_FP_DBL, + isa_nobit + } + }, + { + "vfpv3-d16-fp16", + { + ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, + isa_nobit + } + }, + { + "vfpv3xd", + { + ISA_VFPv3, + isa_nobit + } + }, + { + "vfpv3xd-fp16", + { + ISA_VFPv3,isa_bit_fp16conv, + isa_nobit + } + }, + { + "neon", + { + ISA_VFPv3,ISA_NEON, + isa_nobit + } + }, + { + "neon-vfpv3", + { + ISA_VFPv3,ISA_NEON, + isa_nobit + } + }, + { + "neon-fp16", + { + ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, + isa_nobit + } + }, + { + "vfpv4", + { + ISA_VFPv4,ISA_FP_D32, + isa_nobit + } + }, + { + "neon-vfpv4", + { + ISA_VFPv4,ISA_NEON, + isa_nobit + } + }, + { + "vfpv4-d16", + { + ISA_VFPv4,ISA_FP_DBL, + isa_nobit + } + }, + { + "fpv4-sp-d16", + { + ISA_VFPv4, + isa_nobit + } + }, + { + "fpv5-sp-d16", + { + ISA_FPv5, + isa_nobit + } + }, + { + "fpv5-d16", + { + ISA_FPv5,ISA_FP_DBL, + isa_nobit + } + }, + { + "fp-armv8", + { + ISA_FP_ARMv8,ISA_FP_D32, + isa_nobit + } + }, + { + "neon-fp-armv8", + { + ISA_FP_ARMv8,ISA_NEON, + isa_nobit + } + }, + { + "crypto-neon-fp-armv8", + { + ISA_FP_ARMv8,ISA_CRYPTO, + isa_nobit + } + }, + { + "vfp3", + { + ISA_VFPv3,ISA_FP_D32, + isa_nobit + } + }, +}; static const struct arm_arch_core_flag arm_arch_core_flags[] = { { diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h index 646f8e1..d42021d 100644 --- a/gcc/config/arm/arm-cpu-data.h +++ b/gcc/config/arm/arm-cpu-data.h @@ -20,1634 +20,6 @@ License along with GCC; see the file COPYING3. If not see . */ -static const cpu_arch_extension cpu_opttab_arm9e[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm946es[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm966es[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm968es[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm10e[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm1020e[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm1022e[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm926ejs[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_arm1026ejs[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_genericv7a[] = { - { - "simd", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "vfpv3", false, - { ISA_VFPv3,ISA_FP_D32, isa_nobit } - }, - { - "vfpv3-d16", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv3-fp16", false, - { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv3-d16-fp16", false, - { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv4", false, - { ISA_VFPv4,ISA_FP_D32, isa_nobit } - }, - { - "vfpv4-d16", false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "neon", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-vfpv3", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-fp16", false, - { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } - }, - { - "neon-vfpv4", false, - { ISA_VFPv4,ISA_NEON, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { - "nosimd", true, - { ISA_ALL_SIMD, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa5[] = { - { - "nosimd", true, - { ISA_ALL_SIMD, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa7[] = { - { - "nosimd", true, - { ISA_ALL_SIMD, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa8[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa9[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { - "nosimd", true, - { ISA_ALL_SIMD, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa12[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa15[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa17[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexr5[] = { - { - "nofp.dp", true, - { ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexr7[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexr8[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexm7[] = { - { - "nofp.dp", true, - { ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexm4[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa32[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa35[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa53[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa57[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa72[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa73[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_exynosm1[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_xgene1[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_cortexm33[] = { - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_option all_cores[] = -{ - { - { - "arm2", - NULL, - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv2 - }, - { - { - "arm250", - NULL, - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv2 - }, - { - { - "arm3", - NULL, - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv2 - }, - { - { - "arm6", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm60", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm600", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm610", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm620", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7d", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7di", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm70", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm700", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm700i", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm710", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm720", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm710c", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7100", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7500", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7500fe", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3 - }, - { - { - "arm7m", - NULL, - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3m - }, - { - { - "arm7dm", - NULL, - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3m - }, - { - { - "arm7dmi", - NULL, - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv3m - }, - { - { - "arm8", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "arm810", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "strongarm", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "strongarm110", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "strongarm1100", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "strongarm1110", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "fa526", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "fa626", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - } - }, - TARGET_ARCH_armv4 - }, - { - { - "arm7tdmi", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm7tdmi-s", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm710t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm720t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm740t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm9", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm9tdmi", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm920", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm920t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm922t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm940t", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "ep9312", - NULL, - { - ISA_ARMv4t, - isa_nobit - } - }, - TARGET_ARCH_armv4t - }, - { - { - "arm10tdmi", - NULL, - { - ISA_ARMv5t, - isa_nobit - } - }, - TARGET_ARCH_armv5t - }, - { - { - "arm1020t", - NULL, - { - ISA_ARMv5t, - isa_nobit - } - }, - TARGET_ARCH_armv5t - }, - { - { - "arm9e", - cpu_opttab_arm9e, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm946e-s", - cpu_opttab_arm946es, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm966e-s", - cpu_opttab_arm966es, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm968e-s", - cpu_opttab_arm968es, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm10e", - cpu_opttab_arm10e, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm1020e", - cpu_opttab_arm1020e, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm1022e", - cpu_opttab_arm1022e, - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "xscale", - NULL, - { - ISA_ARMv5te, - isa_bit_xscale, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "iwmmxt", - NULL, - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, - isa_nobit - } - }, - TARGET_ARCH_iwmmxt - }, - { - { - "iwmmxt2", - NULL, - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, - isa_nobit - } - }, - TARGET_ARCH_iwmmxt2 - }, - { - { - "fa606te", - NULL, - { - ISA_ARMv5te, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "fa626te", - NULL, - { - ISA_ARMv5te, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "fmp626", - NULL, - { - ISA_ARMv5te, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "fa726te", - NULL, - { - ISA_ARMv5te, - isa_nobit - } - }, - TARGET_ARCH_armv5te - }, - { - { - "arm926ej-s", - cpu_opttab_arm926ejs, - { - ISA_ARMv5tej, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5tej - }, - { - { - "arm1026ej-s", - cpu_opttab_arm1026ejs, - { - ISA_ARMv5tej, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv5tej - }, - { - { - "arm1136j-s", - NULL, - { - ISA_ARMv6j, - isa_nobit - } - }, - TARGET_ARCH_armv6j - }, - { - { - "arm1136jf-s", - NULL, - { - ISA_ARMv6j, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv6j - }, - { - { - "arm1176jz-s", - NULL, - { - ISA_ARMv6kz, - isa_nobit - } - }, - TARGET_ARCH_armv6kz - }, - { - { - "arm1176jzf-s", - NULL, - { - ISA_ARMv6kz, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv6kz - }, - { - { - "mpcorenovfp", - NULL, - { - ISA_ARMv6k, - isa_nobit - } - }, - TARGET_ARCH_armv6k - }, - { - { - "mpcore", - NULL, - { - ISA_ARMv6k, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv6k - }, - { - { - "arm1156t2-s", - NULL, - { - ISA_ARMv6t2, - isa_nobit - } - }, - TARGET_ARCH_armv6t2 - }, - { - { - "arm1156t2f-s", - NULL, - { - ISA_ARMv6t2, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv6t2 - }, - { - { - "cortex-m1", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "cortex-m0", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "cortex-m0plus", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "cortex-m1.small-multiply", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "cortex-m0.small-multiply", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "cortex-m0plus.small-multiply", - NULL, - { - ISA_ARMv6m, - isa_nobit - } - }, - TARGET_ARCH_armv6_m - }, - { - { - "generic-armv7-a", - cpu_opttab_genericv7a, - { - ISA_ARMv7a, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv7_a - }, - { - { - "cortex-a5", - cpu_opttab_cortexa5, - { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, - isa_nobit - } - }, - TARGET_ARCH_armv7_a - }, - { - { - "cortex-a7", - cpu_opttab_cortexa7, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-a8", - cpu_opttab_cortexa8, - { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7_a - }, - { - { - "cortex-a9", - cpu_opttab_cortexa9, - { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, - isa_nobit - } - }, - TARGET_ARCH_armv7_a - }, - { - { - "cortex-a12", - cpu_opttab_cortexa12, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-a15", - cpu_opttab_cortexa15, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-a17", - cpu_opttab_cortexa17, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-r4", - NULL, - { - ISA_ARMv7r, - isa_nobit - } - }, - TARGET_ARCH_armv7_r - }, - { - { - "cortex-r4f", - NULL, - { - ISA_ARMv7r, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv7_r - }, - { - { - "cortex-r5", - cpu_opttab_cortexr5, - { - ISA_ARMv7r, - isa_bit_adiv, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv7_r - }, - { - { - "cortex-r7", - cpu_opttab_cortexr7, - { - ISA_ARMv7r, - isa_bit_adiv, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv7_r - }, - { - { - "cortex-r8", - cpu_opttab_cortexr8, - { - ISA_ARMv7r, - isa_bit_adiv, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - TARGET_ARCH_armv7_r - }, - { - { - "cortex-m7", - cpu_opttab_cortexm7, - { - ISA_ARMv7em, - ISA_FPv5,ISA_FP_DBL, - isa_quirk_no_volatile_ce, - isa_nobit - } - }, - TARGET_ARCH_armv7e_m - }, - { - { - "cortex-m4", - cpu_opttab_cortexm4, - { - ISA_ARMv7em, - ISA_VFPv4, - isa_nobit - } - }, - TARGET_ARCH_armv7e_m - }, - { - { - "cortex-m3", - NULL, - { - ISA_ARMv7m, - isa_quirk_cm3_ldrd, - isa_nobit - } - }, - TARGET_ARCH_armv7_m - }, - { - { - "marvell-pj4", - NULL, - { - ISA_ARMv7a, - isa_nobit - } - }, - TARGET_ARCH_armv7_a - }, - { - { - "cortex-a15.cortex-a7", - cpu_opttab_cortexa15cortexa7, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-a17.cortex-a7", - cpu_opttab_cortexa17cortexa7, - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv7ve - }, - { - { - "cortex-a32", - cpu_opttab_cortexa32, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a35", - cpu_opttab_cortexa35, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a53", - cpu_opttab_cortexa53, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a57", - cpu_opttab_cortexa57, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a72", - cpu_opttab_cortexa72, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a73", - cpu_opttab_cortexa73, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "exynos-m1", - cpu_opttab_exynosm1, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "xgene1", - cpu_opttab_xgene1, - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a57.cortex-a53", - cpu_opttab_cortexa57cortexa53, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a72.cortex-a53", - cpu_opttab_cortexa72cortexa53, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a73.cortex-a35", - cpu_opttab_cortexa73cortexa35, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-a73.cortex-a53", - cpu_opttab_cortexa73cortexa53, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "cortex-m23", - NULL, - { - ISA_ARMv8m_base, - isa_nobit - } - }, - TARGET_ARCH_armv8_m_base - }, - { - { - "cortex-m33", - cpu_opttab_cortexm33, - { - ISA_ARMv8m_main, - isa_bit_ARMv7em, - ISA_FPv5, - isa_nobit - } - }, - TARGET_ARCH_armv8_m_main - }, - {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none} -}; static const cpu_tune all_tunes[] = { { /* arm2. */ @@ -2192,913 +564,3 @@ static const cpu_tune all_tunes[] = }, {TARGET_CPU_arm_none, 0, NULL} }; -static const struct cpu_arch_extension arch_opttab_armv5e[] = { - { - "fp", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv5te[] = { - { - "fp", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv5tej[] = { - { - "fp", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6[] = { - { - "fp", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6j[] = { - { - "fp", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6k[] = { - { - "fp", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6z[] = { - { - "fp", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6kz[] = { - { - "fp", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6zk[] = { - { - "fp", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv6t2[] = { - { - "fp", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv7[] = { - { - "fp", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv3-d16", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv7_a[] = { - { - "fp", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv3-d16", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv3", false, - { ISA_VFPv3,ISA_FP_D32, isa_nobit } - }, - { - "vfpv3-d16-fp16", false, - { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv3-fp16", false, - { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv4-d16", false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv4", false, - { ISA_VFPv4,ISA_FP_D32, isa_nobit } - }, - { - "simd", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-vfpv3", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-fp16", false, - { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } - }, - { - "neon-vfpv4", false, - { ISA_VFPv4,ISA_NEON, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { - "nosimd", true, - { ISA_ALL_SIMD, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv7ve[] = { - { - "vfpv3-d16", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv3", false, - { ISA_VFPv3,ISA_FP_D32, isa_nobit } - }, - { - "vfpv3-d16-fp16", false, - { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv3-fp16", false, - { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } - }, - { - "vfpv4-d16", false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "fp", false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv4", false, - { ISA_VFPv4,ISA_FP_D32, isa_nobit } - }, - { - "neon", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-vfpv3", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-fp16", false, - { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } - }, - { - "simd", false, - { ISA_VFPv4,ISA_NEON, isa_nobit } - }, - { - "neon-vfpv4", false, - { ISA_VFPv4,ISA_NEON, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { - "nosimd", true, - { ISA_ALL_SIMD, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv7_r[] = { - { - "fp.sp", false, - { ISA_VFPv3, isa_nobit } - }, - { - "fp", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "idiv", false, - { isa_bit_adiv, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { - "noidiv", true, - { isa_bit_adiv, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { - { - "fp", false, - { ISA_VFPv4, isa_nobit } - }, - { - "fpv5", false, - { ISA_FPv5, isa_nobit } - }, - { - "fp.dp", false, - { ISA_FPv5,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv8_a[] = { - { - "crc", false, - { isa_bit_crc32, isa_nobit } - }, - { - "simd", false, - { ISA_FP_ARMv8,ISA_NEON, isa_nobit } - }, - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { - "nocrypto", true, - { ISA_ALL_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { - { - "simd", false, - { ISA_FP_ARMv8,ISA_NEON, isa_nobit } - }, - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { - "nocrypto", true, - { ISA_ALL_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = { - { - "simd", false, - { ISA_FP_ARMv8,ISA_NEON, isa_nobit } - }, - { - "fp16", false, - { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit } - }, - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { - "nocrypto", true, - { ISA_ALL_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { - { - "dsp", false, - { isa_bit_ARMv7em, isa_nobit } - }, - { - "fp", false, - { ISA_FPv5, isa_nobit } - }, - { - "fp.dp", false, - { ISA_FPv5,ISA_FP_DBL, isa_nobit } - }, - { - "nofp", true, - { ISA_ALL_FP, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const struct arch_option all_architectures[] = -{ - { - "armv2", - NULL, - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - }, - "2", BASE_ARCH_2, - TARGET_CPU_arm2, - }, - { - "armv2a", - NULL, - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - }, - "2", BASE_ARCH_2, - TARGET_CPU_arm2, - }, - { - "armv3", - NULL, - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - "3", BASE_ARCH_3, - TARGET_CPU_arm6, - }, - { - "armv3m", - NULL, - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - }, - "3M", BASE_ARCH_3M, - TARGET_CPU_arm7m, - }, - { - "armv4", - NULL, - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - "4", BASE_ARCH_4, - TARGET_CPU_arm7tdmi, - }, - { - "armv4t", - NULL, - { - ISA_ARMv4t, - isa_nobit - }, - "4T", BASE_ARCH_4T, - TARGET_CPU_arm7tdmi, - }, - { - "armv5", - NULL, - { - ISA_ARMv5, - isa_nobit - }, - "5", BASE_ARCH_5, - TARGET_CPU_arm10tdmi, - }, - { - "armv5t", - NULL, - { - ISA_ARMv5t, - isa_nobit - }, - "5T", BASE_ARCH_5T, - TARGET_CPU_arm10tdmi, - }, - { - "armv5e", - arch_opttab_armv5e, - { - ISA_ARMv5e, - isa_nobit - }, - "5E", BASE_ARCH_5E, - TARGET_CPU_arm1026ejs, - }, - { - "armv5te", - arch_opttab_armv5te, - { - ISA_ARMv5te, - isa_nobit - }, - "5TE", BASE_ARCH_5TE, - TARGET_CPU_arm1026ejs, - }, - { - "armv5tej", - arch_opttab_armv5tej, - { - ISA_ARMv5tej, - isa_nobit - }, - "5TEJ", BASE_ARCH_5TEJ, - TARGET_CPU_arm1026ejs, - }, - { - "armv6", - arch_opttab_armv6, - { - ISA_ARMv6, - isa_nobit - }, - "6", BASE_ARCH_6, - TARGET_CPU_arm1136js, - }, - { - "armv6j", - arch_opttab_armv6j, - { - ISA_ARMv6j, - isa_nobit - }, - "6J", BASE_ARCH_6J, - TARGET_CPU_arm1136js, - }, - { - "armv6k", - arch_opttab_armv6k, - { - ISA_ARMv6k, - isa_nobit - }, - "6K", BASE_ARCH_6K, - TARGET_CPU_mpcore, - }, - { - "armv6z", - arch_opttab_armv6z, - { - ISA_ARMv6z, - isa_nobit - }, - "6Z", BASE_ARCH_6Z, - TARGET_CPU_arm1176jzs, - }, - { - "armv6kz", - arch_opttab_armv6kz, - { - ISA_ARMv6kz, - isa_nobit - }, - "6KZ", BASE_ARCH_6KZ, - TARGET_CPU_arm1176jzs, - }, - { - "armv6zk", - arch_opttab_armv6zk, - { - ISA_ARMv6kz, - isa_nobit - }, - "6KZ", BASE_ARCH_6KZ, - TARGET_CPU_arm1176jzs, - }, - { - "armv6t2", - arch_opttab_armv6t2, - { - ISA_ARMv6t2, - isa_nobit - }, - "6T2", BASE_ARCH_6T2, - TARGET_CPU_arm1156t2s, - }, - { - "armv6-m", - NULL, - { - ISA_ARMv6m, - isa_nobit - }, - "6M", BASE_ARCH_6M, - TARGET_CPU_cortexm1, - }, - { - "armv6s-m", - NULL, - { - ISA_ARMv6m, - isa_nobit - }, - "6M", BASE_ARCH_6M, - TARGET_CPU_cortexm1, - }, - { - "armv7", - arch_opttab_armv7, - { - ISA_ARMv7, - isa_nobit - }, - "7", BASE_ARCH_7, - TARGET_CPU_cortexa8, - }, - { - "armv7-a", - arch_opttab_armv7_a, - { - ISA_ARMv7a, - isa_nobit - }, - "7A", BASE_ARCH_7A, - TARGET_CPU_cortexa8, - }, - { - "armv7ve", - arch_opttab_armv7ve, - { - ISA_ARMv7ve, - isa_nobit - }, - "7A", BASE_ARCH_7A, - TARGET_CPU_cortexa8, - }, - { - "armv7-r", - arch_opttab_armv7_r, - { - ISA_ARMv7r, - isa_nobit - }, - "7R", BASE_ARCH_7R, - TARGET_CPU_cortexr4, - }, - { - "armv7-m", - NULL, - { - ISA_ARMv7m, - isa_nobit - }, - "7M", BASE_ARCH_7M, - TARGET_CPU_cortexm3, - }, - { - "armv7e-m", - arch_opttab_armv7e_m, - { - ISA_ARMv7em, - isa_nobit - }, - "7EM", BASE_ARCH_7EM, - TARGET_CPU_cortexm4, - }, - { - "armv8-a", - arch_opttab_armv8_a, - { - ISA_ARMv8a, - isa_nobit - }, - "8A", BASE_ARCH_8A, - TARGET_CPU_cortexa53, - }, - { - "armv8.1-a", - arch_opttab_armv8_1_a, - { - ISA_ARMv8_1a, - isa_nobit - }, - "8A", BASE_ARCH_8A, - TARGET_CPU_cortexa53, - }, - { - "armv8.2-a", - arch_opttab_armv8_2_a, - { - ISA_ARMv8_2a, - isa_nobit - }, - "8A", BASE_ARCH_8A, - TARGET_CPU_cortexa53, - }, - { - "armv8-m.base", - NULL, - { - ISA_ARMv8m_base, - isa_nobit - }, - "8M_BASE", BASE_ARCH_8M_BASE, - TARGET_CPU_cortexm23, - }, - { - "armv8-m.main", - arch_opttab_armv8_m_main, - { - ISA_ARMv8m_main, - isa_nobit - }, - "8M_MAIN", BASE_ARCH_8M_MAIN, - TARGET_CPU_cortexm7, - }, - { - "iwmmxt", - NULL, - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, - isa_nobit - }, - "5TE", BASE_ARCH_5TE, - TARGET_CPU_iwmmxt, - }, - { - "iwmmxt2", - NULL, - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, - isa_nobit - }, - "5TE", BASE_ARCH_5TE, - TARGET_CPU_iwmmxt2, - }, - {{NULL, NULL, {isa_nobit}}, - NULL, BASE_ARCH_0, TARGET_CPU_arm_none} -}; - -const struct arm_fpu_desc all_fpus[] = -{ - { - "vfp", - { - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - { - "vfpv2", - { - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - } - }, - { - "vfpv3", - { - ISA_VFPv3,ISA_FP_D32, - isa_nobit - } - }, - { - "vfpv3-fp16", - { - ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, - isa_nobit - } - }, - { - "vfpv3-d16", - { - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - } - }, - { - "vfpv3-d16-fp16", - { - ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, - isa_nobit - } - }, - { - "vfpv3xd", - { - ISA_VFPv3, - isa_nobit - } - }, - { - "vfpv3xd-fp16", - { - ISA_VFPv3,isa_bit_fp16conv, - isa_nobit - } - }, - { - "neon", - { - ISA_VFPv3,ISA_NEON, - isa_nobit - } - }, - { - "neon-vfpv3", - { - ISA_VFPv3,ISA_NEON, - isa_nobit - } - }, - { - "neon-fp16", - { - ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, - isa_nobit - } - }, - { - "vfpv4", - { - ISA_VFPv4,ISA_FP_D32, - isa_nobit - } - }, - { - "neon-vfpv4", - { - ISA_VFPv4,ISA_NEON, - isa_nobit - } - }, - { - "vfpv4-d16", - { - ISA_VFPv4,ISA_FP_DBL, - isa_nobit - } - }, - { - "fpv4-sp-d16", - { - ISA_VFPv4, - isa_nobit - } - }, - { - "fpv5-sp-d16", - { - ISA_FPv5, - isa_nobit - } - }, - { - "fpv5-d16", - { - ISA_FPv5,ISA_FP_DBL, - isa_nobit - } - }, - { - "fp-armv8", - { - ISA_FP_ARMv8,ISA_FP_D32, - isa_nobit - } - }, - { - "neon-fp-armv8", - { - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - { - "crypto-neon-fp-armv8", - { - ISA_FP_ARMv8,ISA_CRYPTO, - isa_nobit - } - }, - { - "vfp3", - { - ISA_VFPv3,ISA_FP_D32, - isa_nobit - } - }, -}; diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index ada2503..f30b81e 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -513,4 +513,16 @@ struct cpu_option enum arch_type arch; }; +extern const arch_option all_architectures[]; +extern const cpu_option all_cores[]; + +const cpu_option *arm_parse_cpu_option_name (const cpu_option *, const char *, + const char *); +const arch_option *arm_parse_arch_option_name (const arch_option *, + const char *, const char *); +void arm_parse_option_features (sbitmap, const cpu_arch_option *, + const char *); + +void arm_initialize_isa (sbitmap, const enum isa_feature *); + #endif /* ! GCC_ARM_PROTOS_H */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index dbba1d3..6df7dc9 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3024,194 +3024,6 @@ arm_option_override_internal (struct gcc_options *opts, #endif } -/* Convert a static initializer array of feature bits to sbitmap - representation. */ -static void -arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits) -{ - bitmap_clear (isa); - while (*isa_bits != isa_nobit) - bitmap_set_bit (isa, *(isa_bits++)); -} - -/* List the permitted CPU option names. If TARGET is a near miss for an - entry, print out the suggested alternative. */ -static void -arm_print_hint_for_cpu_option (const char *target, - const cpu_option *list) -{ - auto_vec candidates; - for (; list->common.name != NULL; list++) - candidates.safe_push (list->common.name); - char *s; - const char *hint = candidates_list_and_hint (target, s, candidates); - if (hint) - inform (input_location, "valid arguments are: %s; did you mean %qs?", - s, hint); - else - inform (input_location, "valid arguments are: %s", s); - - XDELETEVEC (s); -} - -/* Parse the base component of a CPU selection in LIST. Return a - pointer to the entry in the architecture table. OPTNAME is the - name of the option we are parsing and can be used if a diagnostic - is needed. */ -static const cpu_option * -arm_parse_cpu_option_name (const cpu_option *list, const char *optname, - const char *target) -{ - const cpu_option *entry; - const char *end = strchr (target, '+'); - size_t len = end ? end - target : strlen (target); - - for (entry = list; entry->common.name != NULL; entry++) - { - if (strncmp (entry->common.name, target, len) == 0 - && entry->common.name[len] == '\0') - return entry; - } - - error_at (input_location, "unrecognized %s target: %s", optname, target); - arm_print_hint_for_cpu_option (target, list); - return NULL; -} - -/* List the permitted architecture option names. If TARGET is a near - miss for an entry, print out the suggested alternative. */ -static void -arm_print_hint_for_arch_option (const char *target, - const arch_option *list) -{ - auto_vec candidates; - for (; list->common.name != NULL; list++) - candidates.safe_push (list->common.name); - char *s; - const char *hint = candidates_list_and_hint (target, s, candidates); - if (hint) - inform (input_location, "valid arguments are: %s; did you mean %qs?", - s, hint); - else - inform (input_location, "valid arguments are: %s", s); - - XDELETEVEC (s); -} - -/* Parse the base component of a CPU or architecture selection in - LIST. Return a pointer to the entry in the architecture table. - OPTNAME is the name of the option we are parsing and can be used if - a diagnostic is needed. */ -static const arch_option * -arm_parse_arch_option_name (const arch_option *list, const char *optname, - const char *target) -{ - const arch_option *entry; - const char *end = strchr (target, '+'); - size_t len = end ? end - target : strlen (target); - - for (entry = list; entry->common.name != NULL; entry++) - { - if (strncmp (entry->common.name, target, len) == 0 - && entry->common.name[len] == '\0') - return entry; - } - - error_at (input_location, "unrecognized %s target: %s", optname, target); - arm_print_hint_for_arch_option (target, list); - return NULL; -} - -/* OPT isn't a recognized feature. Print a suitable error message and - suggest a possible value. Always print the list of permitted - values. */ -static void -arm_unrecognized_feature (const char *opt, size_t len, - const cpu_arch_option *target) -{ - char *this_opt = XALLOCAVEC (char, len+1); - auto_vec candidates; - - strncpy (this_opt, opt, len); - this_opt[len] = 0; - - error_at (input_location, "%qs does not support feature %qs", target->name, - this_opt); - for (const cpu_arch_extension *list = target->extensions; - list->name != NULL; - list++) - candidates.safe_push (list->name); - - char *s; - const char *hint = candidates_list_and_hint (this_opt, s, candidates); - - if (hint) - inform (input_location, "valid feature names are: %s; did you mean %qs?", - s, hint); - else - inform (input_location, "valid feature names are: %s", s); - - XDELETEVEC (s); -} - -/* Parse any feature extensions to add to (or remove from) the - permitted ISA selection. */ -static void -arm_parse_option_features (sbitmap isa, const cpu_arch_option *target, - const char *opts_in) -{ - const char *opts = opts_in; - - if (!opts) - return; - - if (!target->extensions) - { - error_at (input_location, "%s does not take any feature options", - target->name); - return; - } - - while (opts) - { - gcc_assert (*opts == '+'); - const struct cpu_arch_extension *entry; - const char *end = strchr (++opts, '+'); - size_t len = end ? end - opts : strlen (opts); - bool matched = false; - - for (entry = target->extensions; - !matched && entry->name != NULL; - entry++) - { - if (strncmp (entry->name, opts, len) == 0 - && entry->name[len] == '\0') - { - if (isa) - { - const enum isa_feature *f = entry->isa_bits; - if (entry->remove) - { - while (*f != isa_nobit) - bitmap_clear_bit (isa, *(f++)); - } - else - { - while (*f != isa_nobit) - bitmap_set_bit (isa, *(f++)); - } - } - matched = true; - } - } - - if (!matched) - arm_unrecognized_feature (opts, len, target); - - opts = end; - } -} - static sbitmap isa_all_fpubits; static sbitmap isa_quirkbits; @@ -30886,7 +30698,7 @@ arm_identify_fpu_from_isa (sbitmap isa) if (bitmap_empty_p (fpubits)) return "softvfp"; - for (unsigned int i = 0; i < ARRAY_SIZE (all_fpus); i++) + for (unsigned int i = 0; i < TARGET_FPU_auto; i++) { arm_initialize_isa (cand_fpubits, all_fpus[i].isa_bits); if (bitmap_equal_p (fpubits, cand_fpubits)) diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index 57565bd..70b8938 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -128,6 +128,39 @@ function gen_headers () { function gen_data () { boilerplate("C") + print "static const cpu_tune all_tunes[] =" + print "{" + + ncpus = split (cpu_list, cpus) + + for (n = 1; n <= ncpus; n++) { + print " { /* " cpus[n] ". */" + # scheduler + if (cpus[n] in cpu_tune_for) { + if (! (cpu_tune_for[cpus[n]] in cpu_cnames)) { + fatal("unknown \"tune for\" target " cpu_tune_for[cpus[n]] \ + " for CPU " cpus[n]) + } + print " TARGET_CPU_" cpu_cnames[cpu_tune_for[cpus[n]]] "," + } else { + print " TARGET_CPU_" cpu_cnames[cpus[n]] "," + } + # tune_flags + if (cpus[n] in cpu_tune_flags) { + print " (" cpu_tune_flags[cpus[n]] ")," + } else print " 0," + # tune + print " &arm_" cpu_cost[cpus[n]] "_tune" + print " }," + } + print " {TARGET_CPU_arm_none, 0, NULL}" + print "};" + +} + +function gen_comm_data () { + boilerplate("C") + ncpus = split (cpu_list, cpus) for (n = 1; n <= ncpus; n++) { @@ -147,7 +180,7 @@ function gen_data () { } } - print "static const cpu_option all_cores[] =" + print "const cpu_option all_cores[] =" print "{" for (n = 1; n <= ncpus; n++) { @@ -188,32 +221,6 @@ function gen_data () { print " {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}" print "};" - print "static const cpu_tune all_tunes[] =" - print "{" - - for (n = 1; n <= ncpus; n++) { - print " { /* " cpus[n] ". */" - # scheduler - if (cpus[n] in cpu_tune_for) { - if (! (cpu_tune_for[cpus[n]] in cpu_cnames)) { - fatal("unknown \"tune for\" target " cpu_tune_for[cpus[n]] \ - " for CPU " cpus[n]) - } - print " TARGET_CPU_" cpu_cnames[cpu_tune_for[cpus[n]]] "," - } else { - print " TARGET_CPU_" cpu_cnames[cpus[n]] "," - } - # tune_flags - if (cpus[n] in cpu_tune_flags) { - print " (" cpu_tune_flags[cpus[n]] ")," - } else print " 0," - # tune - print " &arm_" cpu_cost[cpus[n]] "_tune" - print " }," - } - print " {TARGET_CPU_arm_none, 0, NULL}" - print "};" - narchs = split (arch_list, archs) for (n = 1; n <= narchs; n++) { @@ -233,7 +240,7 @@ function gen_data () { } } - print "static const struct arch_option all_architectures[] =" + print "const arch_option all_architectures[] =" print "{" for (n = 1; n <= narchs; n++) { @@ -265,7 +272,7 @@ function gen_data () { print " NULL, BASE_ARCH_0, TARGET_CPU_arm_none}" print "};\n" - print "const struct arm_fpu_desc all_fpus[] =" + print "const arm_fpu_desc all_fpus[] =" print "{" nfpus = split (fpu_list, fpus) @@ -281,10 +288,6 @@ function gen_data () { } print "};" -} - -function gen_comm_data () { - boilerplate("C") print "static const struct arm_arch_core_flag arm_arch_core_flags[] =" print "{" -- cgit v1.1 From e53993efae201a6a65164a299e5305894ff1cb84 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:03:30 +0000 Subject: [arm] Use standard option parsing code for detecting Now that the standard CPU and architecture option parsing code is available in the driver we can use the main CPU and architecture data tables for driving the automatic enabling of Thumb code. Doing this requires that the driver script tell the parser whether or not the target string is a CPU name or an architecture, but beyond that it is just standard use of the new capabilities. We do, however, now get some error checking if the target isn't recognized, when previously we just ignored unknown targets and hoped that a later pass would pick up on this. * config/arm/arm.h (TARGET_MODE_SPECS): Add additional parameter to call to target_mode_check describing the type of option passed. * common/config/arm/arm-common.c (arm_arch_core_flag): Delete. (arm_target_thumb_only): Use arm_parse_arch_option_name or arm_parse_cpu_option_name to match parameters against list of available targets. * config/arm/parsecpu.awk (gen_comm_data): Don't generate arm_arch_core_flags data structure. * config/arm/arm-cpu_cdata.h: Regenerated. From-SVN: r249288 --- gcc/ChangeLog | 12 + gcc/common/config/arm/arm-common.c | 66 ++- gcc/config/arm/arm-cpu-cdata.h | 1078 ------------------------------------ gcc/config/arm/arm.h | 2 +- gcc/config/arm/parsecpu.awk | 38 -- 5 files changed, 60 insertions(+), 1136 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 626b6d7..9325207 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2017-06-16 Richard Earnshaw + * config/arm/arm.h (TARGET_MODE_SPECS): Add additional parameter to + call to target_mode_check describing the type of option passed. + * common/config/arm/arm-common.c (arm_arch_core_flag): Delete. + (arm_target_thumb_only): Use arm_parse_arch_option_name or + arm_parse_cpu_option_name to match parameters against list of + available targets. + * config/arm/parsecpu.awk (gen_comm_data): Don't generate + arm_arch_core_flags data structure. + * config/arm/arm-cpu_cdata.h: Regenerated. + +2017-06-16 Richard Earnshaw + * common/config/arm/arm-common.c (arm_initialize_isa): Moved here from config/arm/arm.c. (arm_print_hint_for_cpu_option): Likewise. diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index f44ba1f..42f1ad4 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -143,12 +143,6 @@ arm_rewrite_march (int argc, const char **argv) return arm_rewrite_selected_arch (argv[argc - 1]); } -struct arm_arch_core_flag -{ - const char *const name; - const enum isa_feature isa_bits[isa_num_bits]; -}; - #include "config/arm/arm-cpu-cdata.h" /* Scan over a raw feature array BITS checking for BIT being present. @@ -167,26 +161,60 @@ check_isa_bits_for (const enum isa_feature* bits, enum isa_feature bit) /* Called by the driver to check whether the target denoted by current command line options is a Thumb-only target. ARGV is an array of - -march and -mcpu values (ie. it contains the rhs after the equal - sign) and we use the last one of them to make a decision. The - number of elements in ARGV is given in ARGC. */ + tupples (normally only one) where the first element of the tupple + is 'cpu' or 'arch' and the second is the option passed to the + compiler for that. An architecture tupple is always taken in + preference to a cpu tupple and the last of each type always + overrides any earlier setting. */ + const char * arm_target_thumb_only (int argc, const char **argv) { - unsigned int opt; + const char *arch = NULL; + const char *cpu = NULL; + + if (argc % 2 != 0) + fatal_error (input_location, + "%%:target_mode_check takes an even number of parameters"); - if (argc) + while (argc) { - for (opt = 0; opt < (ARRAY_SIZE (arm_arch_core_flags)); opt++) - if ((strcmp (argv[argc - 1], arm_arch_core_flags[opt].name) == 0) - && !check_isa_bits_for (arm_arch_core_flags[opt].isa_bits, - isa_bit_notm)) - return "-mthumb"; + if (strcmp (argv[0], "arch") == 0) + arch = argv[1]; + else if (strcmp (argv[0], "cpu") == 0) + cpu = argv[1]; + else + fatal_error (input_location, + "unrecognized option passed to %%:target_mode_check"); + argc -= 2; + argv += 2; + } - return NULL; + /* No architecture, or CPU, has option extensions that change + whether or not we have a Thumb-only device, so there is no need + to scan any option extensions specified. */ + + /* If the architecture is specified, that overrides any CPU setting. */ + if (arch) + { + const arch_option *arch_opt + = arm_parse_arch_option_name (all_architectures, "-march", arch); + + if (arch_opt && !check_isa_bits_for (arch_opt->common.isa_bits, + isa_bit_notm)) + return "-mthumb"; } - else - return NULL; + else if (cpu) + { + const cpu_option *cpu_opt + = arm_parse_cpu_option_name (all_cores, "-mcpu", cpu); + + if (cpu_opt && !check_isa_bits_for (cpu_opt->common.isa_bits, + isa_bit_notm)) + return "-mthumb"; + } + + return NULL; } /* List the permitted CPU option names. If TARGET is a near miss for an diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index 5329bd6..6c674da 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -348,22 +348,6 @@ static const cpu_arch_extension cpu_opttab_exynosm1[] = { { NULL, false, {isa_nobit}} }; -static const cpu_arch_extension cpu_opttab_falkor[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - -static const cpu_arch_extension cpu_opttab_qdf24xx[] = { - { - "crypto", false, - { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } - }, - { NULL, false, {isa_nobit}} -}; - static const cpu_arch_extension cpu_opttab_xgene1[] = { { "crypto", false, @@ -1576,32 +1560,6 @@ const cpu_option all_cores[] = }, { { - "falkor", - cpu_opttab_falkor, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { - "qdf24xx", - cpu_opttab_qdf24xx, - { - ISA_ARMv8a, - isa_bit_crc32, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - } - }, - TARGET_ARCH_armv8_a - }, - { - { "xgene1", cpu_opttab_xgene1, { @@ -2600,1039 +2558,3 @@ const arm_fpu_desc all_fpus[] = } }, }; -static const struct arm_arch_core_flag arm_arch_core_flags[] = -{ - { - "arm2", - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm250", - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm3", - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm6", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm60", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm600", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm610", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm620", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm7", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm7d", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm7di", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm70", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm700", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm700i", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm710", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm720", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm710c", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm7100", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm7500", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm7500fe", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm7m", - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm7dm", - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm7dmi", - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm8", - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm810", - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - }, - { - "strongarm", - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - }, - { - "strongarm110", - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - }, - { - "strongarm1100", - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - }, - { - "strongarm1110", - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - }, - { - "fa526", - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - }, - { - "fa626", - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - }, - { - "arm7tdmi", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm7tdmi-s", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm710t", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm720t", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm740t", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm9", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm9tdmi", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm920", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm920t", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm922t", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm940t", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "ep9312", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "arm10tdmi", - { - ISA_ARMv5t, - isa_nobit - }, - }, - { - "arm1020t", - { - ISA_ARMv5t, - isa_nobit - }, - }, - { - "arm9e", - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "arm946e-s", - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "arm966e-s", - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "arm968e-s", - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "arm10e", - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "arm1020e", - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "arm1022e", - { - ISA_ARMv5te, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "xscale", - { - ISA_ARMv5te, - isa_bit_xscale, - isa_nobit - }, - }, - { - "iwmmxt", - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, - isa_nobit - }, - }, - { - "iwmmxt2", - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, - isa_nobit - }, - }, - { - "fa606te", - { - ISA_ARMv5te, - isa_nobit - }, - }, - { - "fa626te", - { - ISA_ARMv5te, - isa_nobit - }, - }, - { - "fmp626", - { - ISA_ARMv5te, - isa_nobit - }, - }, - { - "fa726te", - { - ISA_ARMv5te, - isa_nobit - }, - }, - { - "arm926ej-s", - { - ISA_ARMv5tej, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "arm1026ej-s", - { - ISA_ARMv5tej, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "arm1136j-s", - { - ISA_ARMv6j, - isa_nobit - }, - }, - { - "arm1136jf-s", - { - ISA_ARMv6j, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "arm1176jz-s", - { - ISA_ARMv6kz, - isa_nobit - }, - }, - { - "arm1176jzf-s", - { - ISA_ARMv6kz, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "mpcorenovfp", - { - ISA_ARMv6k, - isa_nobit - }, - }, - { - "mpcore", - { - ISA_ARMv6k, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "arm1156t2-s", - { - ISA_ARMv6t2, - isa_nobit - }, - }, - { - "arm1156t2f-s", - { - ISA_ARMv6t2, - ISA_VFPv2,ISA_FP_DBL, - isa_nobit - }, - }, - { - "cortex-m1", - { - ISA_ARMv6m, - isa_nobit - }, - }, - { - "cortex-m0", - { - ISA_ARMv6m, - isa_nobit - }, - }, - { - "cortex-m0plus", - { - ISA_ARMv6m, - isa_nobit - }, - }, - { - "cortex-m1.small-multiply", - { - ISA_ARMv6m, - isa_nobit - }, - }, - { - "cortex-m0.small-multiply", - { - ISA_ARMv6m, - isa_nobit - }, - }, - { - "cortex-m0plus.small-multiply", - { - ISA_ARMv6m, - isa_nobit - }, - }, - { - "generic-armv7-a", - { - ISA_ARMv7a, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - }, - }, - { - "cortex-a5", - { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, - isa_nobit - }, - }, - { - "cortex-a7", - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a8", - { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a9", - { - ISA_ARMv7a, - ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, - isa_nobit - }, - }, - { - "cortex-a12", - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a15", - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a17", - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-r4", - { - ISA_ARMv7r, - isa_nobit - }, - }, - { - "cortex-r4f", - { - ISA_ARMv7r, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - }, - }, - { - "cortex-r5", - { - ISA_ARMv7r, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - }, - }, - { - "cortex-r7", - { - ISA_ARMv7r, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - }, - }, - { - "cortex-r8", - { - ISA_ARMv7r, - ISA_VFPv3,ISA_FP_DBL, - isa_nobit - }, - }, - { - "cortex-m7", - { - ISA_ARMv7em, - ISA_FPv5,ISA_FP_DBL, - isa_quirk_no_volatile_ce, - isa_nobit - }, - }, - { - "cortex-m4", - { - ISA_ARMv7em, - ISA_VFPv4, - isa_nobit - }, - }, - { - "cortex-m3", - { - ISA_ARMv7m, - isa_quirk_cm3_ldrd, - isa_nobit - }, - }, - { - "marvell-pj4", - { - ISA_ARMv7a, - isa_nobit - }, - }, - { - "cortex-a15.cortex-a7", - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a17.cortex-a7", - { - ISA_ARMv7ve, - ISA_VFPv4,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a32", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a35", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a53", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a57", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a72", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a73", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "exynos-m1", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "xgene1", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a57.cortex-a53", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a72.cortex-a53", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a73.cortex-a35", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-a73.cortex-a53", - { - ISA_ARMv8a, - ISA_FP_ARMv8,ISA_NEON, - isa_nobit - }, - }, - { - "cortex-m23", - { - ISA_ARMv8m_base, - isa_nobit - }, - }, - { - "cortex-m33", - { - ISA_ARMv8m_main, - ISA_FPv5, - isa_nobit - }, - }, - { - "armv2", - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - }, - }, - { - "armv2a", - { - ISA_ARMv2,isa_bit_mode26, - isa_nobit - }, - }, - { - "armv3", - { - ISA_ARMv3,isa_bit_mode26, - isa_nobit - }, - }, - { - "armv3m", - { - ISA_ARMv3m,isa_bit_mode26, - isa_nobit - }, - }, - { - "armv4", - { - ISA_ARMv4,isa_bit_mode26, - isa_nobit - }, - }, - { - "armv4t", - { - ISA_ARMv4t, - isa_nobit - }, - }, - { - "armv5", - { - ISA_ARMv5, - isa_nobit - }, - }, - { - "armv5t", - { - ISA_ARMv5t, - isa_nobit - }, - }, - { - "armv5e", - { - ISA_ARMv5e, - isa_nobit - }, - }, - { - "armv5te", - { - ISA_ARMv5te, - isa_nobit - }, - }, - { - "armv5tej", - { - ISA_ARMv5tej, - isa_nobit - }, - }, - { - "armv6", - { - ISA_ARMv6, - isa_nobit - }, - }, - { - "armv6j", - { - ISA_ARMv6j, - isa_nobit - }, - }, - { - "armv6k", - { - ISA_ARMv6k, - isa_nobit - }, - }, - { - "armv6z", - { - ISA_ARMv6z, - isa_nobit - }, - }, - { - "armv6kz", - { - ISA_ARMv6kz, - isa_nobit - }, - }, - { - "armv6zk", - { - ISA_ARMv6kz, - isa_nobit - }, - }, - { - "armv6t2", - { - ISA_ARMv6t2, - isa_nobit - }, - }, - { - "armv6-m", - { - ISA_ARMv6m, - isa_nobit - }, - }, - { - "armv6s-m", - { - ISA_ARMv6m, - isa_nobit - }, - }, - { - "armv7", - { - ISA_ARMv7, - isa_nobit - }, - }, - { - "armv7-a", - { - ISA_ARMv7a, - isa_nobit - }, - }, - { - "armv7ve", - { - ISA_ARMv7ve, - isa_nobit - }, - }, - { - "armv7-r", - { - ISA_ARMv7r, - isa_nobit - }, - }, - { - "armv7-m", - { - ISA_ARMv7m, - isa_nobit - }, - }, - { - "armv7e-m", - { - ISA_ARMv7em, - isa_nobit - }, - }, - { - "armv8-a", - { - ISA_ARMv8a, - isa_nobit - }, - }, - { - "armv8.1-a", - { - ISA_ARMv8_1a, - isa_nobit - }, - }, - { - "armv8.2-a", - { - ISA_ARMv8_2a, - isa_nobit - }, - }, - { - "armv8-m.base", - { - ISA_ARMv8m_base, - isa_nobit - }, - }, - { - "armv8-m.main", - { - ISA_ARMv8m_main, - isa_nobit - }, - }, - { - "iwmmxt", - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt, - isa_nobit - }, - }, - { - "iwmmxt2", - { - ISA_ARMv5te,isa_bit_xscale,isa_bit_iwmmxt,isa_bit_iwmmxt2, - isa_nobit - }, - }, -}; - diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index d398b99..590755e 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2262,7 +2262,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); - an array of -mcpu values if any is given; - an empty array. */ #define TARGET_MODE_SPECS \ - " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:%*;mcpu=*:%*;:})}}" + " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS TARGET_MODE_SPECS #define TARGET_SUPPORTS_WIDE_INT 1 diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index 70b8938..3d6ca4d 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -288,44 +288,6 @@ function gen_comm_data () { } print "};" - - print "static const struct arm_arch_core_flag arm_arch_core_flags[] =" - print "{" - - ncpus = split (cpu_list, cpus) - - for (n = 1; n <= ncpus; n++) { - print " {" - print " \"" cpus[n] "\"," - # Just truncate the architecture name at the beginning of the - # extensions. We don't need any of those here (at present). - arch_name = cpu_arch[cpus[n]]; - sub("+.*", "", arch_name) - if (! (arch_name in arch_isa)) { - fatal("unknown arch " arch_name " for cpu " cpus[n]) - } - print " {" - print " " arch_isa[arch_name] "," - if (cpus[n] in cpu_fpu) print " " fpu_isa[cpu_fpu[cpus[n]]] "," - if (cpus[n] in cpu_isa) print " " cpu_isa[cpus[n]] "," - print " isa_nobit" - print " }," - print " }," - } - - narchs = split (arch_list, archs) - - for (n = 1; n <= narchs; n++) { - print " {" - print " \"" archs[n] "\"," - print " {" - print " " arch_isa[archs[n]] "," - print " isa_nobit" - print " }," - print " }," - } - - print "};\n" } function gen_md () { -- cgit v1.1 From 357e1023c9b10e98d1aa4d59fdb876078de47608 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:03:39 +0000 Subject: [arm] Allow CPU and architecture extensions to be A follow up patch to this one will start to canonicalize options to simplify generating multilib fragments. This patch is enabling work for that. If we have extension options that duplicate other options (done principally for back-wards compatibility purposes) we need to ensure that just one of them will be used consistently when generating a canonical form of the user-specified options. We do this by explicitly noting when an option is defined as an alias of another. Another aspect of canonicalization is to enforce a strict order in which the options are inspected, we do this by ensuring that no later option examined can be a subset of an earlier option (add and remove options are treated separtely). It's practically impossible to check all this in parsecpu.awk since that premits use of C macros in the ISA features list, so instead we enforce the ordering with a selftest function in the compiler, which is only run when self tests are enabled (it's not something that will change every day, so this should be sufficient). * config/arm/arm-protos.h (cpu_arch_extension): Add field to record when an option is an alias of another. * config/arm/parsecpu.awk (optalias): New parser token. (gen_comm_data): Mark non-alias options as such. Emit entries for extension aliases. * config/arm/arm-cpus.in (armv5e): Make vfpv2 an alias. (armv5te, armv5tej, armv6, armv6j, armv6k, armv6z): Likewise. (armv6kz, armv6zk, armv6t2): Likewise. (armv7): Make vfpv3-d16 an alias. (armv7-a): Make vfpv3-d16, neon and neon-vfpv3 aliases. Sort in canonical order. (armv7ve): Make vfpv4-d16, neon-vfpv3 and neon-vfpv4 aliases. Sort in canonical order. (armv8-a): Sort in canonical order. (armv8.1-a, armv8.2-a): Likewise. (generic-armv7-a): Make neon and neon-vfpv3 aliases. Sort in canonical order. (cortex-a9): Sort in canonical order. * config/arm/arm.c (selftests.h): Include it. (arm_test_cpu_arch_data): New function. (arm_run_self_tests): New function. (TARGET_RUN_TARGET_SELFTESTS): Redefine. (targetm): Move declaration to the end of the file. * arm-cpu-cdata.h: Regenerated. From-SVN: r249289 --- gcc/ChangeLog | 27 +++ gcc/config/arm/arm-cpu-cdata.h | 510 ++++++++++++++++++++--------------------- gcc/config/arm/arm-cpus.in | 77 ++++--- gcc/config/arm/arm-protos.h | 6 + gcc/config/arm/arm.c | 82 ++++++- gcc/config/arm/parsecpu.awk | 57 ++++- 6 files changed, 462 insertions(+), 297 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9325207..2764dda 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,32 @@ 2017-06-16 Richard Earnshaw + * config/arm/arm-protos.h (cpu_arch_extension): Add field to record + when an option is an alias of another. + * config/arm/parsecpu.awk (optalias): New parser token. + (gen_comm_data): Mark non-alias options as such. Emit entries + for extension aliases. + * config/arm/arm-cpus.in (armv5e): Make vfpv2 an alias. + (armv5te, armv5tej, armv6, armv6j, armv6k, armv6z): Likewise. + (armv6kz, armv6zk, armv6t2): Likewise. + (armv7): Make vfpv3-d16 an alias. + (armv7-a): Make vfpv3-d16, neon and neon-vfpv3 aliases. Sort in + canonical order. + (armv7ve): Make vfpv4-d16, neon-vfpv3 and neon-vfpv4 aliases. + Sort in canonical order. + (armv8-a): Sort in canonical order. + (armv8.1-a, armv8.2-a): Likewise. + (generic-armv7-a): Make neon and neon-vfpv3 aliases. Sort in + canonical order. + (cortex-a9): Sort in canonical order. + * config/arm/arm.c (selftests.h): Include it. + (arm_test_cpu_arch_data): New function. + (arm_run_self_tests): New function. + (TARGET_RUN_TARGET_SELFTESTS): Redefine. + (targetm): Move declaration to the end of the file. + * arm-cpu-cdata.h: Regenerated. + +2017-06-16 Richard Earnshaw + * config/arm/arm.h (TARGET_MODE_SPECS): Add additional parameter to call to target_mode_check describing the type of option passed. * common/config/arm/arm-common.c (arm_arch_core_flag): Delete. diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index 6c674da..5034dbb 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -22,378 +22,378 @@ static const cpu_arch_extension cpu_opttab_arm9e[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_arm946es[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_arm966es[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_arm968es[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_arm10e[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_arm1020e[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_arm1022e[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_arm926ejs[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_arm1026ejs[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_genericv7a[] = { { - "simd", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "vfpv3", false, - { ISA_VFPv3,ISA_FP_D32, isa_nobit } - }, - { - "vfpv3-d16", false, + "vfpv3-d16", false, false, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { - "vfpv3-fp16", false, - { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } + "vfpv3", false, false, + { ISA_VFPv3,ISA_FP_D32, isa_nobit } }, { - "vfpv3-d16-fp16", false, + "vfpv3-d16-fp16", false, false, { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } }, { - "vfpv4", false, - { ISA_VFPv4,ISA_FP_D32, isa_nobit } + "vfpv3-fp16", false, false, + { ISA_VFPv3,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } }, { - "vfpv4-d16", false, + "vfpv4-d16", false, false, { ISA_VFPv4,ISA_FP_DBL, isa_nobit } }, { - "neon", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } + "vfpv4", false, false, + { ISA_VFPv4,ISA_FP_D32, isa_nobit } }, { - "neon-vfpv3", false, + "simd", false, false, { ISA_VFPv3,ISA_NEON, isa_nobit } }, { - "neon-fp16", false, + "neon-fp16", false, false, { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } }, { - "neon-vfpv4", false, + "neon-vfpv4", false, false, { ISA_VFPv4,ISA_NEON, isa_nobit } }, { - "nofp", true, + "nosimd", true, false, + { ISA_ALL_SIMD, isa_nobit } + }, + { + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, { - "nosimd", true, - { ISA_ALL_SIMD, isa_nobit } + "neon", false, true, + { ISA_VFPv3,ISA_NEON, isa_nobit } }, - { NULL, false, {isa_nobit}} + { + "neon-vfpv3", false, true, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa5[] = { { - "nosimd", true, + "nosimd", true, false, { ISA_ALL_SIMD, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa7[] = { { - "nosimd", true, + "nosimd", true, false, { ISA_ALL_SIMD, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa8[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa9[] = { { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "nosimd", true, false, + { ISA_ALL_SIMD, isa_nobit } }, { - "nosimd", true, - { ISA_ALL_SIMD, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa12[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa15[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa17[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexr5[] = { { - "nofp.dp", true, + "nofp.dp", true, false, { ISA_FP_DBL, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexr7[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexr8[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexm7[] = { { - "nofp.dp", true, + "nofp.dp", true, false, { ISA_FP_DBL, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexm4[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa32[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa35[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa53[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa57[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa72[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa73[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_exynosm1[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_xgene1[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = { { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const cpu_arch_extension cpu_opttab_cortexm33[] = { { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; const cpu_option all_cores[] = @@ -1650,426 +1650,426 @@ const cpu_option all_cores[] = }; static const struct cpu_arch_extension arch_opttab_armv5e[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv2", false, true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv5te[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv2", false, true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv5tej[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv2", false, true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv6[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv2", false, true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv6j[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv2", false, true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv6k[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv2", false, true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv6z[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv2", false, true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv6kz[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv2", false, true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv6zk[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv2", false, true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv6t2[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, { - "vfpv2", false, - { ISA_VFPv2,ISA_FP_DBL, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv2", false, true, + { ISA_VFPv2,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv7[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { - "vfpv3-d16", false, + "vfpv3-d16", false, true, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv7_a[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { - "vfpv3-d16", false, - { ISA_VFPv3,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv3", false, + "vfpv3", false, false, { ISA_VFPv3,ISA_FP_D32, isa_nobit } }, { - "vfpv3-d16-fp16", false, + "vfpv3-d16-fp16", false, false, { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } }, { - "vfpv3-fp16", false, + "vfpv3-fp16", false, false, { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } }, { - "vfpv4-d16", false, + "vfpv4-d16", false, false, { ISA_VFPv4,ISA_FP_DBL, isa_nobit } }, { - "vfpv4", false, + "vfpv4", false, false, { ISA_VFPv4,ISA_FP_D32, isa_nobit } }, { - "simd", false, + "simd", false, false, { ISA_VFPv3,ISA_NEON, isa_nobit } }, { - "neon", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } + "neon-fp16", false, false, + { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } }, { - "neon-vfpv3", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } + "neon-vfpv4", false, false, + { ISA_VFPv4,ISA_NEON, isa_nobit } }, { - "neon-fp16", false, - { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } + "nosimd", true, false, + { ISA_ALL_SIMD, isa_nobit } }, { - "neon-vfpv4", false, - { ISA_VFPv4,ISA_NEON, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "vfpv3-d16", false, true, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { - "nosimd", true, - { ISA_ALL_SIMD, isa_nobit } + "neon", false, true, + { ISA_VFPv3,ISA_NEON, isa_nobit } }, - { NULL, false, {isa_nobit}} + { + "neon-vfpv3", false, true, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv7ve[] = { { - "vfpv3-d16", false, + "vfpv3-d16", false, false, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { - "vfpv3", false, + "vfpv3", false, false, { ISA_VFPv3,ISA_FP_D32, isa_nobit } }, { - "vfpv3-d16-fp16", false, + "vfpv3-d16-fp16", false, false, { ISA_VFPv3,ISA_FP_DBL,isa_bit_fp16conv, isa_nobit } }, { - "vfpv3-fp16", false, + "vfpv3-fp16", false, false, { ISA_VFPv3,ISA_FP_DBL,ISA_FP_D32,isa_bit_fp16conv, isa_nobit } }, { - "vfpv4-d16", false, + "fp", false, false, { ISA_VFPv4,ISA_FP_DBL, isa_nobit } }, { - "fp", false, - { ISA_VFPv4,ISA_FP_DBL, isa_nobit } - }, - { - "vfpv4", false, + "vfpv4", false, false, { ISA_VFPv4,ISA_FP_D32, isa_nobit } }, { - "neon", false, + "neon", false, false, { ISA_VFPv3,ISA_NEON, isa_nobit } }, { - "neon-vfpv3", false, - { ISA_VFPv3,ISA_NEON, isa_nobit } - }, - { - "neon-fp16", false, + "neon-fp16", false, false, { ISA_VFPv3,ISA_NEON,isa_bit_fp16conv, isa_nobit } }, { - "simd", false, + "simd", false, false, { ISA_VFPv4,ISA_NEON, isa_nobit } }, { - "neon-vfpv4", false, - { ISA_VFPv4,ISA_NEON, isa_nobit } + "nosimd", true, false, + { ISA_ALL_SIMD, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, { - "nosimd", true, - { ISA_ALL_SIMD, isa_nobit } + "vfpv4-d16", false, true, + { ISA_VFPv4,ISA_FP_DBL, isa_nobit } }, - { NULL, false, {isa_nobit}} + { + "neon-vfpv3", false, true, + { ISA_VFPv3,ISA_NEON, isa_nobit } + }, + { + "neon-vfpv4", false, true, + { ISA_VFPv4,ISA_NEON, isa_nobit } + }, + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv7_r[] = { { - "fp.sp", false, + "fp.sp", false, false, { ISA_VFPv3, isa_nobit } }, { - "fp", false, + "fp", false, false, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { - "idiv", false, + "idiv", false, false, { isa_bit_adiv, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, { - "noidiv", true, + "noidiv", true, false, { isa_bit_adiv, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { { - "fp", false, + "fp", false, false, { ISA_VFPv4, isa_nobit } }, { - "fpv5", false, + "fpv5", false, false, { ISA_FPv5, isa_nobit } }, { - "fp.dp", false, + "fp.dp", false, false, { ISA_FPv5,ISA_FP_DBL, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv8_a[] = { { - "crc", false, + "crc", false, false, { isa_bit_crc32, isa_nobit } }, { - "simd", false, + "simd", false, false, { ISA_FP_ARMv8,ISA_NEON, isa_nobit } }, { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "nocrypto", true, false, + { ISA_ALL_CRYPTO, isa_nobit } }, { - "nocrypto", true, - { ISA_ALL_CRYPTO, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { { - "simd", false, + "simd", false, false, { ISA_FP_ARMv8,ISA_NEON, isa_nobit } }, { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "nocrypto", true, false, + { ISA_ALL_CRYPTO, isa_nobit } }, { - "nocrypto", true, - { ISA_ALL_CRYPTO, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = { { - "simd", false, + "simd", false, false, { ISA_FP_ARMv8,ISA_NEON, isa_nobit } }, { - "fp16", false, + "fp16", false, false, { isa_bit_fp16,ISA_FP_ARMv8,ISA_NEON, isa_nobit } }, { - "crypto", false, + "crypto", false, false, { ISA_FP_ARMv8,ISA_CRYPTO, isa_nobit } }, { - "nofp", true, - { ISA_ALL_FP, isa_nobit } + "nocrypto", true, false, + { ISA_ALL_CRYPTO, isa_nobit } }, { - "nocrypto", true, - { ISA_ALL_CRYPTO, isa_nobit } + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { { - "dsp", false, + "dsp", false, false, { isa_bit_ARMv7em, isa_nobit } }, { - "fp", false, + "fp", false, false, { ISA_FPv5, isa_nobit } }, { - "fp.dp", false, + "fp.dp", false, false, { ISA_FPv5,ISA_FP_DBL, isa_nobit } }, { - "nofp", true, + "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, - { NULL, false, {isa_nobit}} + { NULL, false, false, {isa_nobit}} }; const arch_option all_architectures[] = diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index fdd5e83..14e49ec 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -114,7 +114,7 @@ begin arch armv5e base 5E isa ARMv5e option fp add VFPv2 FP_DBL - option vfpv2 add VFPv2 FP_DBL + optalias vfpv2 fp option nofp remove ALL_FP end arch armv5e @@ -124,7 +124,7 @@ begin arch armv5te base 5TE isa ARMv5te option fp add VFPv2 FP_DBL - option vfpv2 add VFPv2 FP_DBL + optalias vfpv2 fp option nofp remove ALL_FP end arch armv5te @@ -134,7 +134,7 @@ begin arch armv5tej base 5TEJ isa ARMv5tej option fp add VFPv2 FP_DBL - option vfpv2 add VFPv2 FP_DBL + optalias vfpv2 fp option nofp remove ALL_FP end arch armv5tej @@ -144,7 +144,7 @@ begin arch armv6 base 6 isa ARMv6 option fp add VFPv2 FP_DBL - option vfpv2 add VFPv2 FP_DBL + optalias vfpv2 fp option nofp remove ALL_FP end arch armv6 @@ -154,7 +154,7 @@ begin arch armv6j base 6J isa ARMv6j option fp add VFPv2 FP_DBL - option vfpv2 add VFPv2 FP_DBL + optalias vfpv2 fp option nofp remove ALL_FP end arch armv6j @@ -164,7 +164,7 @@ begin arch armv6k base 6K isa ARMv6k option fp add VFPv2 FP_DBL - option vfpv2 add VFPv2 FP_DBL + optalias vfpv2 fp option nofp remove ALL_FP end arch armv6k @@ -174,7 +174,7 @@ begin arch armv6z base 6Z isa ARMv6z option fp add VFPv2 FP_DBL - option vfpv2 add VFPv2 FP_DBL + optalias vfpv2 fp option nofp remove ALL_FP end arch armv6z @@ -184,7 +184,7 @@ begin arch armv6kz base 6KZ isa ARMv6kz option fp add VFPv2 FP_DBL - option vfpv2 add VFPv2 FP_DBL + optalias vfpv2 fp option nofp remove ALL_FP end arch armv6kz @@ -194,7 +194,7 @@ begin arch armv6zk base 6KZ isa ARMv6kz option fp add VFPv2 FP_DBL - option vfpv2 add VFPv2 FP_DBL + optalias vfpv2 fp option nofp remove ALL_FP end arch armv6zk @@ -204,7 +204,7 @@ begin arch armv6t2 base 6T2 isa ARMv6t2 option fp add VFPv2 FP_DBL - option vfpv2 add VFPv2 FP_DBL + optalias vfpv2 fp option nofp remove ALL_FP end arch armv6t2 @@ -227,7 +227,7 @@ begin arch armv7 isa ARMv7 # fp => VFPv3-d16 (only useful for the A+R profile subset). option fp add VFPv3 FP_DBL - option vfpv3-d16 add VFPv3 FP_DBL + optalias vfpv3-d16 fp end arch armv7 begin arch armv7-a @@ -236,20 +236,20 @@ begin arch armv7-a base 7A isa ARMv7a # fp => VFPv3-d16, simd => neon-vfpv3 - option fp add VFPv3 FP_DBL - option vfpv3-d16 add VFPv3 FP_DBL - option vfpv3 add VFPv3 FP_D32 + option fp add VFPv3 FP_DBL + optalias vfpv3-d16 fp + option vfpv3 add VFPv3 FP_D32 option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv option vfpv4-d16 add VFPv4 FP_DBL - option vfpv4 add VFPv4 FP_D32 - option simd add VFPv3 NEON - option neon add VFPv3 NEON - option neon-vfpv3 add VFPv3 NEON + option vfpv4 add VFPv4 FP_D32 + option simd add VFPv3 NEON + optalias neon simd + optalias neon-vfpv3 simd option neon-fp16 add VFPv3 NEON bit_fp16conv option neon-vfpv4 add VFPv4 NEON - option nofp remove ALL_FP - option nosimd remove ALL_SIMD + option nosimd remove ALL_SIMD + option nofp remove ALL_FP end arch armv7-a begin arch armv7ve @@ -262,16 +262,16 @@ begin arch armv7ve option vfpv3 add VFPv3 FP_D32 option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 bit_fp16conv - option vfpv4-d16 add VFPv4 FP_DBL option fp add VFPv4 FP_DBL + optalias vfpv4-d16 fp option vfpv4 add VFPv4 FP_D32 option neon add VFPv3 NEON - option neon-vfpv3 add VFPv3 NEON + optalias neon-vfpv3 neon option neon-fp16 add VFPv3 NEON bit_fp16conv option simd add VFPv4 NEON - option neon-vfpv4 add VFPv4 NEON - option nofp remove ALL_FP - option nosimd remove ALL_SIMD + optalias neon-vfpv4 simd + option nosimd remove ALL_SIMD + option nofp remove ALL_FP end arch armv7ve begin arch armv7-r @@ -316,8 +316,8 @@ begin arch armv8-a option crc add bit_crc32 option simd add FP_ARMv8 NEON option crypto add FP_ARMv8 CRYPTO - option nofp remove ALL_FP option nocrypto remove ALL_CRYPTO + option nofp remove ALL_FP end arch armv8-a begin arch armv8.1-a @@ -327,8 +327,8 @@ begin arch armv8.1-a isa ARMv8_1a option simd add FP_ARMv8 NEON option crypto add FP_ARMv8 CRYPTO - option nofp remove ALL_FP option nocrypto remove ALL_CRYPTO + option nofp remove ALL_FP end arch armv8.1-a begin arch armv8.2-a @@ -339,8 +339,8 @@ begin arch armv8.2-a option simd add FP_ARMv8 NEON option fp16 add bit_fp16 FP_ARMv8 NEON option crypto add FP_ARMv8 CRYPTO - option nofp remove ALL_FP option nocrypto remove ALL_CRYPTO + option nofp remove ALL_FP end arch armv8.2-a begin arch armv8-m.base @@ -385,6 +385,7 @@ end arch iwmmxt2 # [fpu ] # [isa ] # [option add|remove ]* +# [optalias ]* # [costs ] # end cpu # @@ -392,7 +393,9 @@ end arch iwmmxt2 # non-valid punctuation characters to '_'. # If specified, tune for specifies a CPU target to use for tuning this core. # isa flags are appended to those defined by the architecture. - +# Each add option must have a distinct feature set and each remove +# option must similarly have a distinct feature set. Option aliases can be +# added with the optalias statement # V2/V2A Architecture Processors begin cpu arm2 @@ -921,19 +924,19 @@ begin cpu generic-armv7-a tune flags LDSCHED architecture armv7-a fpu vfpv3-d16 - option simd add VFPv3 NEON - option vfpv3 add VFPv3 FP_D32 option vfpv3-d16 add VFPv3 FP_DBL - option vfpv3-fp16 add VFPv3 FP_D32 bit_fp16conv + option vfpv3 add VFPv3 FP_D32 option vfpv3-d16-fp16 add VFPv3 FP_DBL bit_fp16conv - option vfpv4 add VFPv4 FP_D32 + option vfpv3-fp16 add VFPv3 FP_D32 bit_fp16conv option vfpv4-d16 add VFPv4 FP_DBL - option neon add VFPv3 NEON - option neon-vfpv3 add VFPv3 NEON + option vfpv4 add VFPv4 FP_D32 + option simd add VFPv3 NEON + optalias neon simd + optalias neon-vfpv3 simd option neon-fp16 add VFPv3 NEON bit_fp16conv option neon-vfpv4 add VFPv4 NEON - option nofp remove ALL_FP option nosimd remove ALL_SIMD + option nofp remove ALL_FP costs cortex end cpu generic-armv7-a @@ -971,8 +974,8 @@ begin cpu cortex-a9 tune flags LDSCHED architecture armv7-a fpu neon-fp16 - option nofp remove ALL_FP option nosimd remove ALL_SIMD + option nofp remove ALL_FP costs cortex_a9 end cpu cortex-a9 diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index f30b81e..25210e2 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -478,8 +478,14 @@ extern struct arm_build_target arm_active_target; struct cpu_arch_extension { + /* Feature name. */ const char *const name; + /* True if the option is negative (removes extensions). */ bool remove; + /* True if the option is an alias for another option with identical effect; + the option will be ignored for canonicalization. */ + bool alias; + /* The modifier bits. */ const enum isa_feature isa_bits[isa_num_bits]; }; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 6df7dc9..55ea22e 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -65,6 +65,7 @@ #include "optabs-libfuncs.h" #include "gimplify.h" #include "gimple.h" +#include "selftest.h" /* This file should be included last. */ #include "target-def.h" @@ -774,7 +775,6 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 2 -struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ static struct obstack minipool_obstack; @@ -31208,4 +31208,84 @@ arm_coproc_ldc_stc_legitimate_address (rtx op) } return false; } + +#if CHECKING_P +namespace selftest { + +/* Scan the static data tables generated by parsecpu.awk looking for + potential issues with the data. We primarily check for + inconsistencies in the option extensions at present (extensions + that duplicate others but aren't marked as aliases). Furthermore, + for correct canonicalization later options must never be a subset + of an earlier option. */ +static void +arm_test_cpu_arch_data (void) +{ + const arch_option *arch; + const cpu_option *cpu; + auto_sbitmap isa1 (isa_num_bits); + auto_sbitmap isa2 (isa_num_bits); + + for (arch = all_architectures; arch->common.name != NULL; ++arch) + { + const cpu_arch_extension *ext1, *ext2; + + if (arch->common.extensions == NULL) + continue; + + for (ext1 = arch->common.extensions; ext1->name != NULL; ++ext1) + { + if (ext1->alias) + continue; + + arm_initialize_isa (isa1, ext1->isa_bits); + for (ext2 = ext1 + 1; ext2->name != NULL; ++ext2) + { + if (ext2->alias || ext1->remove != ext2->remove) + continue; + + arm_initialize_isa (isa2, ext2->isa_bits); + ASSERT_TRUE (!bitmap_subset_p (isa2, isa1)); + } + } + } + + for (cpu = all_cores; cpu->common.name != NULL; ++cpu) + { + const cpu_arch_extension *ext1, *ext2; + + if (cpu->common.extensions == NULL) + continue; + + for (ext1 = cpu->common.extensions; ext1->name != NULL; ++ext1) + { + if (ext1->alias) + continue; + + arm_initialize_isa (isa1, ext1->isa_bits); + for (ext2 = ext1 + 1; ext2->name != NULL; ++ext2) + { + if (ext2->alias || ext1->remove != ext2->remove) + continue; + + arm_initialize_isa (isa2, ext2->isa_bits); + ASSERT_TRUE (!bitmap_subset_p (isa2, isa1)); + } + } + } +} + +static void +arm_run_selftests (void) +{ + arm_test_cpu_arch_data (); +} +} /* Namespace selftest. */ + +#undef TARGET_RUN_TARGET_SELFTESTS +#define TARGET_RUN_TARGET_SELFTESTS selftest::arm_run_selftests +#endif /* CHECKING_P */ + +struct gcc_target targetm = TARGET_INITIALIZER; + #include "gt-arm.h" diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index 3d6ca4d..61e8bc2 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -171,11 +171,28 @@ function gen_comm_data () { for (opt = 1; opt <= nopts; opt++) { print " {" print " \"" opts[opt] "\", " \ - cpu_opt_remove[cpus[n],opts[opt]] "," + cpu_opt_remove[cpus[n],opts[opt]] ", false," print " { " cpu_opt_isa[cpus[n],opts[opt]] ", isa_nobit }" print " }," } - print " { NULL, false, {isa_nobit}}" + if (cpus[n] in cpu_optaliases) { + naliases = split (cpu_optaliases[cpus[n]], aliases) + for (alias = 1; alias <= naliases; alias++) { + if (! ((cpus[n], \ + cpu_opt_alias[cpus[n],aliases[alias]]) in \ + cpu_opt_isa)) { + fatal("Alias " aliases[alias] " target not defined " \ + "for CPU " cpus[n]) + } + equiv=cpu_opt_alias[cpus[n],aliases[alias]] + print " {" + print " \"" aliases[alias] "\", " \ + cpu_opt_remove[cpus[n],equiv] ", true, " + print " { " cpu_opt_isa[cpus[n],equiv] ", isa_nobit }" + print " }," + } + } + print " { NULL, false, false, {isa_nobit}}" print "};\n" } } @@ -231,12 +248,31 @@ function gen_comm_data () { for (opt = 1; opt <= nopts; opt++) { print " {" print " \"" opts[opt] "\", " \ - arch_opt_remove[archs[n],opts[opt]] "," + arch_opt_remove[archs[n],opts[opt]] ", false," print " { " arch_opt_isa[archs[n],opts[opt]] ", isa_nobit }" print " }," } - print " { NULL, false, {isa_nobit}}" + if (archs[n] in arch_optaliases) { + naliases = split (arch_optaliases[archs[n]], aliases) + for (alias = 1; alias <= naliases; alias++) { + if (! ((archs[n], \ + arch_opt_alias[archs[n],aliases[alias]]) in \ + arch_opt_isa)) { + fatal("Alias " aliases[alias] " target not defined " \ + "for architecture " archs[n]) + } + equiv=arch_opt_alias[archs[n],aliases[alias]] + print " {" + print " \"" aliases[alias] "\", " \ + arch_opt_remove[archs[n],equiv] ", true, " + print " { " arch_opt_isa[archs[n],equiv] ", isa_nobit }" + print " }," + } + } + print " { NULL, false, false, {isa_nobit}}" print "};\n" + } else if (archs[n] in arch_optaliases) { + fatal("Architecture " archs[n] " has option aliases but no options") } } @@ -529,6 +565,19 @@ BEGIN { parse_ok = 1 } +/^[ ]*optalias / { + name=$2 + alias=$3 + if (cpu_name != "") { + cpu_optaliases[cpu_name] = cpu_optaliases[cpu_name] " " name + cpu_opt_alias[cpu_name,name] = alias + } else if (arch_name != "") { + arch_optaliases[arch_name] = arch_optaliases[arch_name] " " name + arch_opt_alias[arch_name,name] = alias + } else fatal("\"optalias\" outside of cpu or arch block") + parse_ok = 1 +} + /^[ ]*costs / { if (cpu_name == "") fatal("\"costs\" outside of cpu block") cpu_cost[cpu_name] = $2 -- cgit v1.1 From bf35d17a30c0a476b6abc82e0b029029c5599104 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:03:46 +0000 Subject: [arm] Allow new extended syntax CPU and architecture This patch extends support for the new extended-style architecture strings to configure and the target default options. We validate any options passed by the user to configure against the permitted extensions for that CPU or architecture. * config.gcc (arm*-*-fucshia*): Set target_cpu_cname to the real cpu name. (arm*-*-*): Set target_cpu_default2 to a quoted string. * config/arm/parsecpu.awk (check_cpu): Validate any extension options. (check_arch): Likewise. * config/arm/arm.c (arm_configure_build_target): Handle TARGET_CPU_DEFAULT being a string constant. Scan any feature options in the default. From-SVN: r249290 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config.gcc | 6 +++--- gcc/config/arm/arm.c | 8 +++++++- gcc/config/arm/parsecpu.awk | 36 ++++++++++++++++++++++++++++-------- 4 files changed, 50 insertions(+), 12 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2764dda..3299cde 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2017-06-16 Richard Earnshaw + * config.gcc (arm*-*-fucshia*): Set target_cpu_cname to the real + cpu name. + (arm*-*-*): Set target_cpu_default2 to a quoted string. + * config/arm/parsecpu.awk (check_cpu): Validate any extension + options. + (check_arch): Likewise. + * config/arm/arm.c (arm_configure_build_target): Handle + TARGET_CPU_DEFAULT being a string constant. Scan any feature + options in the default. + +2017-06-16 Richard Earnshaw + * config/arm/arm-protos.h (cpu_arch_extension): Add field to record when an option is an alias of another. * config/arm/parsecpu.awk (optalias): New parser token. diff --git a/gcc/config.gcc b/gcc/config.gcc index 8b00e66..620a5b2 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1161,7 +1161,7 @@ arm*-*-eabi* | arm*-*-symbianelf* | arm*-*-rtems* | arm*-*-fuchsia*) arm*-*-fuchsia*) tm_file="${tm_file} fuchsia.h arm/fuchsia-elf.h glibc-stdint.h" tmake_file="${tmake_file} arm/t-bpabi" - target_cpu_cname="genericv7a" + target_cpu_cname="generic-armv7-a" ;; arm*-*-rtems*) tm_file="${tm_file} rtems.h arm/rtems.h newlib-stdint.h" @@ -4496,9 +4496,9 @@ case ${target} in arm*-*-*) if test x$target_cpu_cname = x then - target_cpu_default2=TARGET_CPU_arm6 + target_cpu_default2="\\\"arm6\\\"" else - target_cpu_default2=TARGET_CPU_$target_cpu_cname + target_cpu_default2="\\\"$target_cpu_cname\\\"" fi ;; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 55ea22e..9e857a2 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3143,7 +3143,9 @@ arm_configure_build_target (struct arm_build_target *target, bitmap_clear (sought_isa); auto_sbitmap default_isa (isa_num_bits); - arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT]; + arm_selected_cpu = arm_parse_cpu_option_name (all_cores, "default CPU", + TARGET_CPU_DEFAULT); + cpu_opts = strchr (TARGET_CPU_DEFAULT, '+'); gcc_assert (arm_selected_cpu->common.name); /* RWE: All of the selection logic below (to the end of this @@ -3154,6 +3156,8 @@ arm_configure_build_target (struct arm_build_target *target, support for the pre-thumb era cores is removed. */ sel = arm_selected_cpu; arm_initialize_isa (default_isa, sel->common.isa_bits); + arm_parse_option_features (default_isa, &arm_selected_cpu->common, + cpu_opts); /* Now check to see if the user has specified any command line switches that require certain abilities from the cpu. */ @@ -3241,6 +3245,8 @@ arm_configure_build_target (struct arm_build_target *target, structure. */ target->core_name = arm_selected_cpu->common.name; arm_initialize_isa (target->isa, arm_selected_cpu->common.isa_bits); + arm_parse_option_features (target->isa, &arm_selected_cpu->common, + cpu_opts); arm_selected_arch = all_architectures + arm_selected_cpu->arch; } diff --git a/gcc/config/arm/parsecpu.awk b/gcc/config/arm/parsecpu.awk index 61e8bc2..b6e5093 100644 --- a/gcc/config/arm/parsecpu.awk +++ b/gcc/config/arm/parsecpu.awk @@ -393,9 +393,19 @@ function gen_opt () { } function check_cpu (name) { - if (name in cpu_cnames) { - print cpu_cnames[name] - } else print "error" + exts = split (name, extensions, "+") + + if (! extensions[1] in cpu_cnames) { + return "error" + } + + for (n = 2; n <= exts; n++) { + if (!((extensions[1], extensions[n]) in cpu_opt_remove) \ + && !((extensions[1], extensions[n]) in cpu_optaliases)) { + return "error" + } + } + return name } function check_fpu (name) { @@ -405,9 +415,19 @@ function check_fpu (name) { } function check_arch (name) { - if (name in arch_isa) { - print name - } else print "error" + exts = split (name, extensions, "+") + + if (! extensions[1] in arch_isa) { + return "error" + } + + for (n = 2; n <= exts; n++) { + if (!((extensions[1], extensions[n]) in arch_opt_remove) \ + && !((extensions[1], extensions[n]) in arch_optaliases)) { + return "error" + } + } + return name } BEGIN { @@ -614,10 +634,10 @@ END { gen_opt() } else if (cmd ~ /^chk(cpu|tune) /) { split (cmd, target) - check_cpu(target[2]) + print check_cpu(target[2]) } else if (cmd ~ /^chkarch /) { split (cmd, target) - check_arch(target[2]) + print check_arch(target[2]) } else if (cmd ~ /^chkfpu /) { split (cmd, target) check_fpu(target[2]) -- cgit v1.1 From a4af8a1046d3c77ee1152c9dad08329a0dd51f49 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:03:55 +0000 Subject: [arm] Force a CPU default in the config args defaults Currently if the user does not specify a default CPU or architecture the compiler provieds no default values in the spec defaults. We can try to work from TARGET_CPU_DEFAULT but pulling that into the driver is a bit crufty and doesn't really work well with the general spec-processing model. A better way is to ensure that with_cpu is always set appropirately during configure. To avoid problems with the multilib fragment processing we defer this until after we have processed any required fragments before selecting the default. * config.gcc (arm*-*-*): Ensure both target_cpu_cname and with_cpu are set after handling multilib fragments. Set target_cpu_default2 from with_cpu. From-SVN: r249291 --- gcc/ChangeLog | 6 ++++++ gcc/config.gcc | 9 ++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3299cde..2cb85e8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2017-06-16 Richard Earnshaw + * config.gcc (arm*-*-*): Ensure both target_cpu_cname and with_cpu + are set after handling multilib fragments. Set target_cpu_default2 + from with_cpu. + +2017-06-16 Richard Earnshaw + * config.gcc (arm*-*-fucshia*): Set target_cpu_cname to the real cpu name. (arm*-*-*): Set target_cpu_default2 to a quoted string. diff --git a/gcc/config.gcc b/gcc/config.gcc index 620a5b2..f3923fd 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3861,6 +3861,8 @@ case "${target}" in TM_MULTILIB_CONFIG="$with_multilib_list" fi fi + target_cpu_cname=${target_cpu_cname:-arm6} + with_cpu=${with_cpu:-$target_cpu_cname} ;; fr*-*-*linux*) @@ -4494,11 +4496,12 @@ case ${target} in ;; arm*-*-*) - if test x$target_cpu_cname = x + if test x$with_cpu = x then - target_cpu_default2="\\\"arm6\\\"" + echo "Don't know the target cpu" 1>&2 + exit 1 else - target_cpu_default2="\\\"$target_cpu_cname\\\"" + target_cpu_default2="\\\"$with_cpu\\\"" fi ;; -- cgit v1.1 From 0b97b8f84a904dff92284e9899f53f9a1dbc177b Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:04:02 +0000 Subject: [arm] Generate a canonical form for -march This patch uses the driver and some spec rewrite rules to generate a canonicalized form of the -march= option. We want to do this for several reasons, all relating to making multi-lib selection sane. 1) It can remove redundant extension options to produce a minimal list. 2) The general syntax of the option permits a plethora of features, these are permitted in any order. Canonicalization ensures that there is a single ordering of the options that are needed. 3) It can use additional options to remove extensions that aren't relevant, such as removing all features that relate to the FPU when use of that is disabled. Once we have this information in a sensible form the multilib rules can be vastly simplified making for much more understandable Makefile fragments. * common/config/arm/arm-common.c: Define INCLUDE_LIST. (configargs.h): Include it. (arm_print_hint_for_fpu_option): New function. (arm_parse_fpu_option): New function. (candidate_extension): New class. (arm_canon_for_multilib): New function. * config/arm/arm.h (CANON_ARCH_SPEC_FUNCTION): New macro. (EXTRA_SPEC_FUNCTIONS): Add CANON_ARCH_SPEC_FUNCTION. (ARCH_CANONICAL_SPECS): New macro. (DRIVER_SELF_SPECS): Add ARCH_CANONICAL_SPECS. From-SVN: r249292 --- gcc/ChangeLog | 13 ++ gcc/common/config/arm/arm-common.c | 354 +++++++++++++++++++++++++++++++++++++ gcc/config/arm/arm.h | 20 ++- 3 files changed, 386 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2cb85e8..d1abcce 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,18 @@ 2017-06-16 Richard Earnshaw + * common/config/arm/arm-common.c: Define INCLUDE_LIST. + (configargs.h): Include it. + (arm_print_hint_for_fpu_option): New function. + (arm_parse_fpu_option): New function. + (candidate_extension): New class. + (arm_canon_for_multilib): New function. + * config/arm/arm.h (CANON_ARCH_SPEC_FUNCTION): New macro. + (EXTRA_SPEC_FUNCTIONS): Add CANON_ARCH_SPEC_FUNCTION. + (ARCH_CANONICAL_SPECS): New macro. + (DRIVER_SELF_SPECS): Add ARCH_CANONICAL_SPECS. + +2017-06-16 Richard Earnshaw + * config.gcc (arm*-*-*): Ensure both target_cpu_cname and with_cpu are set after handling multilib fragments. Set target_cpu_default2 from with_cpu. diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index 42f1ad4..30cb61e 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -17,6 +17,7 @@ along with GCC; see the file COPYING3. If not see . */ +#define INCLUDE_LIST #include "config.h" #include "system.h" #include "coretypes.h" @@ -305,6 +306,41 @@ arm_parse_arch_option_name (const arch_option *list, const char *optname, return NULL; } +/* List the permitted architecture option names. If TARGET is a near + miss for an entry, print out the suggested alternative. */ +static void +arm_print_hint_for_fpu_option (const char *target) +{ + auto_vec candidates; + for (int i = 0; i < TARGET_FPU_auto; i++) + candidates.safe_push (all_fpus[i].name); + char *s; + const char *hint = candidates_list_and_hint (target, s, candidates); + if (hint) + inform (input_location, "valid arguments are: %s; did you mean %qs?", + s, hint); + else + inform (input_location, "valid arguments are: %s", s); + + XDELETEVEC (s); +} + +static const arm_fpu_desc * +arm_parse_fpu_option (const char *opt) +{ + int i; + + for (i = 0; i < TARGET_FPU_auto; i++) + { + if (strcmp (all_fpus[i].name, opt) == 0) + return all_fpus + i; + } + + error_at (input_location, "unrecognized -mfpu target: %s", opt); + arm_print_hint_for_fpu_option (opt); + return NULL; +} + /* Convert a static initializer array of feature bits to sbitmap representation. */ void @@ -405,6 +441,324 @@ arm_parse_option_features (sbitmap isa, const cpu_arch_option *target, } } +class candidate_extension +{ +public: + const cpu_arch_extension *extension; + sbitmap isa_bits; + bool required; + + candidate_extension (const cpu_arch_extension *ext, sbitmap bits) + : extension (ext), isa_bits (bits), required (true) + {} + ~candidate_extension () + { + sbitmap_free (isa_bits); + } +}; + +/* Generate a canonical representation of the -march option from the + current -march string (if given) and other options on the command + line that might affect the architecture. This aids multilib selection + by ensuring that: + a) the option is always present + b) only the minimal set of options are used + c) when there are multiple extensions, they are in a consistent order. + + The options array consists of couplets of information where the + first item in each couplet is the string describing which option + name was selected (arch, cpu, fpu) and the second is the value + passed for that option. */ +const char * +arm_canon_arch_option (int argc, const char **argv) +{ + const char *arch = NULL; + const char *cpu = NULL; + const char *fpu = NULL; + const char *abi = NULL; + static char *canonical_arch = NULL; + + /* Just in case we're called more than once. */ + if (canonical_arch) + { + free (canonical_arch); + canonical_arch = NULL; + } + + if (argc & 1) + fatal_error (input_location, + "%%:canon_for_mlib takes 1 or more pairs of parameters"); + + while (argc) + { + if (strcmp (argv[0], "arch") == 0) + arch = argv[1]; + else if (strcmp (argv[0], "cpu") == 0) + cpu = argv[1]; + else if (strcmp (argv[0], "fpu") == 0) + fpu = argv[1]; + else if (strcmp (argv[0], "abi") == 0) + abi = argv[1]; + else + fatal_error (input_location, + "unrecognized operand to %%:canon_for_mlib"); + + argc -= 2; + argv += 2; + } + + auto_sbitmap target_isa (isa_num_bits); + auto_sbitmap base_isa (isa_num_bits); + auto_sbitmap fpu_isa (isa_num_bits); + + bitmap_clear (fpu_isa); + + const arch_option *selected_arch = NULL; + + /* At least one of these must be defined by either the specs or the + user. */ + gcc_assert (cpu || arch); + + if (!fpu) + fpu = FPUTYPE_DEFAULT; + + if (!abi) + { + if (TARGET_DEFAULT_FLOAT_ABI == ARM_FLOAT_ABI_SOFT) + abi = "soft"; + else if (TARGET_DEFAULT_FLOAT_ABI == ARM_FLOAT_ABI_SOFTFP) + abi = "softfp"; + else if (TARGET_DEFAULT_FLOAT_ABI == ARM_FLOAT_ABI_HARD) + abi = "hard"; + } + + /* First build up a bitmap describing the target architecture. */ + if (arch) + { + selected_arch = arm_parse_arch_option_name (all_architectures, + "-march", arch); + + if (selected_arch == NULL) + return ""; + + arm_initialize_isa (target_isa, selected_arch->common.isa_bits); + arm_parse_option_features (target_isa, &selected_arch->common, + strchr (arch, '+')); + if (fpu && strcmp (fpu, "auto") != 0) + { + /* We assume that architectures do not have any FPU bits + enabled by default. If they did, we would need to strip + these out first. */ + const arm_fpu_desc *target_fpu = arm_parse_fpu_option (fpu); + if (target_fpu == NULL) + return ""; + + arm_initialize_isa (fpu_isa, target_fpu->isa_bits); + bitmap_ior (target_isa, target_isa, fpu_isa); + } + } + else if (cpu) + { + const cpu_option *selected_cpu + = arm_parse_cpu_option_name (all_cores, "-mcpu", cpu); + + if (selected_cpu == NULL) + return ""; + + arm_initialize_isa (target_isa, selected_cpu->common.isa_bits); + arm_parse_option_features (target_isa, &selected_cpu->common, + strchr (cpu, '+')); + if (fpu && strcmp (fpu, "auto") != 0) + { + /* The easiest and safest way to remove the default fpu + capabilities is to look for a '+no..' option that removes + the base FPU bit (isa_bit_VFPv2). If that doesn't exist + then the best we can do is strip out all the bits that + might be part of the most capable FPU we know about, + which is "crypto-neon-fp-armv8". */ + bool default_fpu_found = false; + if (selected_cpu->common.extensions) + { + const cpu_arch_extension *ext; + for (ext = selected_cpu->common.extensions; ext->name != NULL; + ++ext) + { + if (ext->remove + && check_isa_bits_for (ext->isa_bits, isa_bit_VFPv2)) + { + arm_initialize_isa (fpu_isa, ext->isa_bits); + bitmap_and_compl (target_isa, target_isa, fpu_isa); + default_fpu_found = true; + } + } + + } + + if (!default_fpu_found) + { + arm_initialize_isa + (fpu_isa, + all_fpus[TARGET_FPU_crypto_neon_fp_armv8].isa_bits); + bitmap_and_compl (target_isa, target_isa, fpu_isa); + } + + const arm_fpu_desc *target_fpu = arm_parse_fpu_option (fpu); + if (target_fpu == NULL) + return ""; + + arm_initialize_isa (fpu_isa, target_fpu->isa_bits); + bitmap_ior (target_isa, target_isa, fpu_isa); + } + + selected_arch = all_architectures + selected_cpu->arch; + } + + /* If we have a soft-float ABI, disable the FPU. */ + if (abi && strcmp (abi, "soft") == 0) + { + /* Clearing the VFPv2 bit is sufficient to stop any extention that + builds on the FPU from matching. */ + bitmap_clear_bit (target_isa, isa_bit_VFPv2); + } + + /* If we don't have a selected architecture by now, something's + badly wrong. */ + gcc_assert (selected_arch); + + arm_initialize_isa (base_isa, selected_arch->common.isa_bits); + + /* Architecture has no extension options, so just return the canonical + architecture name. */ + if (selected_arch->common.extensions == NULL) + return selected_arch->common.name; + + /* We're only interested in extension bits. */ + bitmap_and_compl (target_isa, target_isa, base_isa); + + /* There are no extensions needed. Just return the canonical architecture + name. */ + if (bitmap_empty_p (target_isa)) + return selected_arch->common.name; + + /* What is left is the architecture that the compiler will target. We + now need to map that back into a suitable option+features list. + + The list is built in two passes. First we scan every additive + option feature supported by the architecture. If the option + provides a subset of the features we need we add it to the list + of candidates. We then scan backwards over the list of + candidates and if we find a feature that adds nothing to one that + was later in the list we mark it as redundant. The result is a + minimal list of required features for the target + architecture. */ + + std::list extensions; + + auto_sbitmap target_isa_unsatisfied (isa_num_bits); + bitmap_copy (target_isa_unsatisfied, target_isa); + + sbitmap isa_bits = NULL; + for (const cpu_arch_extension *cand = selected_arch->common.extensions; + cand->name != NULL; + cand++) + { + if (cand->remove || cand->alias) + continue; + + if (isa_bits == NULL) + isa_bits = sbitmap_alloc (isa_num_bits); + + arm_initialize_isa (isa_bits, cand->isa_bits); + if (bitmap_subset_p (isa_bits, target_isa)) + { + extensions.push_back (new candidate_extension (cand, isa_bits)); + bitmap_and_compl (target_isa_unsatisfied, target_isa_unsatisfied, + isa_bits); + isa_bits = NULL; + } + } + + /* There's one extra case to consider, which is that the user has + specified an FPU that is less capable than this architecture + supports. In that case the code above will fail to find a + suitable feature. We handle this by scanning the list of options + again, matching the first option that provides an FPU that is + more capable than the selected FPU. + + Note that the other case (user specified a more capable FPU than + this architecture supports) should end up selecting the most + capable FPU variant that we do support. This is sufficient for + multilib selection. */ + + if (bitmap_bit_p (target_isa_unsatisfied, isa_bit_VFPv2) + && bitmap_bit_p (fpu_isa, isa_bit_VFPv2)) + { + std::list::iterator ipoint = extensions.begin (); + + for (const cpu_arch_extension *cand = selected_arch->common.extensions; + cand->name != NULL; + cand++) + { + if (cand->remove || cand->alias) + continue; + + if (isa_bits == NULL) + isa_bits = sbitmap_alloc (isa_num_bits); + + /* We need to keep the features in canonical order, so move the + insertion point if this feature is a candidate. */ + if (ipoint != extensions.end () + && (*ipoint)->extension == cand) + ++ipoint; + + arm_initialize_isa (isa_bits, cand->isa_bits); + if (bitmap_subset_p (fpu_isa, isa_bits)) + { + extensions.insert (ipoint, + new candidate_extension (cand, isa_bits)); + isa_bits = NULL; + break; + } + } + } + + if (isa_bits) + sbitmap_free (isa_bits); + + bitmap_clear (target_isa); + size_t len = 1; + for (std::list::reverse_iterator riter + = extensions.rbegin (); + riter != extensions.rend (); ++riter) + { + if (bitmap_subset_p ((*riter)->isa_bits, target_isa)) + (*riter)->required = false; + else + { + bitmap_ior (target_isa, target_isa, (*riter)->isa_bits); + len += strlen ((*riter)->extension->name) + 1; + } + } + + canonical_arch + = (char *) xmalloc (len + strlen (selected_arch->common.name)); + + strcpy (canonical_arch, selected_arch->common.name); + + for (std::list::iterator iter = extensions.begin (); + iter != extensions.end (); ++iter) + { + if ((*iter)->required) + { + strcat (canonical_arch, "+"); + strcat (canonical_arch, (*iter)->extension->name); + } + delete (*iter); + } + + return canonical_arch; +} + #undef ARM_CPU_NAME_LENGTH diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 590755e..57f4958 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2250,9 +2250,15 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); # define MCPU_MTUNE_NATIVE_SPECS "" #endif +const char *arm_canon_arch_option (int argc, const char **argv); + +#define CANON_ARCH_SPEC_FUNCTION \ + { "canon_arch", arm_canon_arch_option }, + # define EXTRA_SPEC_FUNCTIONS \ MCPU_MTUNE_NATIVE_FUNCTIONS \ ASM_CPU_SPEC_FUNCTIONS \ + CANON_ARCH_SPEC_FUNCTION \ TARGET_MODE_SPEC_FUNCTIONS /* Automatically add -mthumb for Thumb-only targets if mode isn't specified @@ -2264,7 +2270,19 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define TARGET_MODE_SPECS \ " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" -#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS TARGET_MODE_SPECS +/* Generate a canonical string to represent the architecture selected. */ +#define ARCH_CANONICAL_SPECS \ + " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ + " %{march=*: arch %*} " \ + " %{mfpu=*: fpu %*} " \ + " %{mfloat-abi=*: abi %*}" \ + " % Date: Fri, 16 Jun 2017 21:04:07 +0000 Subject: [arm] Make -mfloat-abi=softfp work when there are no Before this patch series it wasn't really possible to not have an FPU; it was always there, even if the hardware didn't really support it. Now that we have -mfpu=auto, the concept of not having an FPU becomes real. Consequently, when the -mfloat-abi switch is set to softfp doing the Right Thing is much more important. In this case we have a soft-float ABI, but can use FP instructions if they are available. To support this we have to separate out TARGET_HARD_FLOAT into two use cases: one where the instructions exist and one when they don't. We preserve the original meaning of TARGET_HARD_FLOAT (but add an extra check) of meaning that we are generating HW FP instructions, and add a new macro for the special case when use of FP instructions is permitted, but might not be available at this time (the distinction is important because they might be enabled by an attribute during the compilation). TARGET_SOFT_FLOAT continues to be the exact inverse of TARGET_HARD_FLOAT, but we now define it as such. * config/arm/arm.h (TARGET_HARD_FLOAT): Also check that we have some floating-point instructions. (TARGET_SOFT_FLOAT): Define as inverse of TARGET_HARD_FLOAT. (TARGET_MAYBE_HARD_FLOAT): New macro. * config/arm/arm-builtins.c (arm_init_builtins): Use TARGET_MAYBE_HARD_FLOAT. * config/arm/arm.c (arm_option_override): Use TARGET_HARD_FLOAT_ABI. From-SVN: r249293 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/arm/arm-builtins.c | 4 ++-- gcc/config/arm/arm.c | 3 +-- gcc/config/arm/arm.h | 9 +++++++-- 4 files changed, 20 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d1abcce..c7b1bbb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,15 @@ 2017-06-16 Richard Earnshaw + * config/arm/arm.h (TARGET_HARD_FLOAT): Also check that we + have some floating-point instructions. + (TARGET_SOFT_FLOAT): Define as inverse of TARGET_HARD_FLOAT. + (TARGET_MAYBE_HARD_FLOAT): New macro. + * config/arm/arm-builtins.c (arm_init_builtins): Use + TARGET_MAYBE_HARD_FLOAT. + * config/arm/arm.c (arm_option_override): Use TARGET_HARD_FLOAT_ABI. + +2017-06-16 Richard Earnshaw + * common/config/arm/arm-common.c: Define INCLUDE_LIST. (configargs.h): Include it. (arm_print_hint_for_fpu_option): New function. diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 8ecf581..8d14e58 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -1876,7 +1876,7 @@ arm_init_builtins (void) arm_init_neon_builtins which uses it. */ arm_init_fp16_builtins (); - if (TARGET_HARD_FLOAT) + if (TARGET_MAYBE_HARD_FLOAT) { arm_init_neon_builtins (); arm_init_vfp_builtins (); @@ -1885,7 +1885,7 @@ arm_init_builtins (void) arm_init_acle_builtins (); - if (TARGET_HARD_FLOAT) + if (TARGET_MAYBE_HARD_FLOAT) { tree ftype_set_fpscr = build_function_type_list (void_type_node, unsigned_type_node, NULL); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9e857a2..385792d 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3449,8 +3449,7 @@ arm_option_override (void) { if (arm_abi == ARM_ABI_IWMMXT) arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; - else if (arm_float_abi == ARM_FLOAT_ABI_HARD - && TARGET_HARD_FLOAT) + else if (TARGET_HARD_FLOAT_ABI) { arm_pcs_default = ARM_PCS_AAPCS_VFP; if (!bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv2)) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 57f4958..92361fc 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -119,9 +119,14 @@ extern tree arm_fp16_type_node; #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) /* Run-time Target Specification. */ -#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) /* Use hardware floating point instructions. */ -#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) +#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ + && bitmap_bit_p (arm_active_target.isa, \ + isa_bit_VFPv2)) +#define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT) +/* User has permitted use of FP instructions, if they exist for this + target. */ +#define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) /* Use hardware floating point calling convention. */ #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) #define TARGET_IWMMXT (arm_arch_iwmmxt) -- cgit v1.1 From aaf8008ce7e980b8f04d6dfaaa2c5ec7f4da1c67 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:04:14 +0000 Subject: [genmultilib] Update basic multilib configuration The standard arm-eabi configuration comes with a basic set of multilibs that are suitable mostly for simple testing of the compiler in various configurations. We try to keep the number of libraries build small so that build times do not become too onerous. Using the new auto-fp selection code we can now cover all supported architectures except for those with single-precision only FP units with just 4 multilibs. This is done with the rewrite of t-arm-elf. Now that we canonicalize -mcpu into suitable -march definitions we don't need to match CPU names to architectures any more; the driver will do this for us. I also noticed whilst writing this patch that the existing MULTILIB_DEFAULTS setting in the compiler was causing more problems than it was worth; and furthermore was simply wrong if the compiler is ever configured with --with-mode, --with-float or --with-endian. The remaining options also pertained to pre-eabi builds and aren't interesting today either. It seemed best to just delete the definition entirely. * config/arm/elf.h (MULTILIB_DEFAULTS): Delete. * config/arm/t-arm-elf: Rewritten. From-SVN: r249294 --- gcc/ChangeLog | 5 ++ gcc/config/arm/elf.h | 4 -- gcc/config/arm/t-arm-elf | 173 ++++++++++++++++++++++++++++------------------- 3 files changed, 109 insertions(+), 73 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c7b1bbb..1330539 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Richard Earnshaw + * config/arm/elf.h (MULTILIB_DEFAULTS): Delete. + * config/arm/t-arm-elf: Rewritten. + +2017-06-16 Richard Earnshaw + * config/arm/arm.h (TARGET_HARD_FLOAT): Also check that we have some floating-point instructions. (TARGET_SOFT_FLOAT): Define as inverse of TARGET_HARD_FLOAT. diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index fcc4f3f..85fdee6 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -107,10 +107,6 @@ #define TARGET_DEFAULT (MASK_APCS_FRAME) #endif -#ifndef MULTILIB_DEFAULTS -#define MULTILIB_DEFAULTS \ - { "marm", "mlittle-endian", "mfloat-abi=soft", "mno-thumb-interwork", "fno-leading-underscore" } -#endif #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true diff --git a/gcc/config/arm/t-arm-elf b/gcc/config/arm/t-arm-elf index f3ad3f7..1337841 100644 --- a/gcc/config/arm/t-arm-elf +++ b/gcc/config/arm/t-arm-elf @@ -16,75 +16,110 @@ # along with GCC; see the file COPYING3. If not see # . -MULTILIB_OPTIONS = marm/mthumb -MULTILIB_DIRNAMES = arm thumb +# Build a very basic set of libraries that should cater for most cases. + +# Single-precision floating-point is NOT supported; we don't build a +# suitable library for that. Use the rm-profile config in that case. + +# PART 1 - Useful groups of options + +dp_fpus := vfp vfpv2 vfpv3 vfpv3-fp16 vfpv3-d16 vfpv3-d16-fp16 \ + neon neon-vfpv3 neon-fp16 vfpv4 neon-vfpv4 vfpv4-d16 \ + fpv5-d16 fp-armv8 neon-fp-armv8 crypto-neon-fp-armv8 \ + vfp3 + +sp_fpus := vfpv3xd vfpv3xd-fp16 fpv4-sp-d16 fpv5-sp-d16 + +v7a_fps := vfpv3 vfpv3-fp16 vfpv4 simd neon-fp16 neon-vfpv4 +v7ve_fps := vfpv3-d16 vfpv3 vfpv3-d16-fp16 vfpv3-fp16 vfpv4 neon \ + neon-fp16 simd + +# Not all these permutations exist for all architecture variants, but +# it seems to work ok. +v8_fps := simd fp16 crypto fp16+crypto + +# We don't do anything special with these. Pre-v4t probably doesn't work. +all_early_nofp := armv2 armv2a armv3 armv3m armv4 armv4t armv5 armv5t + +all_early_arch := armv5e armv5tej armv6 armv6j armv6k armv6z armv6kz \ + armv6zk armv6t2 iwmmxt iwmmxt2 + +all_v7_a_r := armv7-a armv7ve armv7-r + +all_v8_archs := armv8-a armv8-a+crc armv8.1-a armv8.2-a + +# No floating point variants, require thumb1 softfp +all_nofp_t := armv6-m armv6s-m armv8-m.base + +all_nofp_t2 := armv7-m + +all_sp_only := armv7e-m armv8-m.main + +MULTILIB_OPTIONS = +MULTILIB_DIRNAMES = MULTILIB_EXCEPTIONS = MULTILIB_MATCHES = +MULTILIB_REUSE = + +# PART 2 - multilib build rules + +MULTILIB_OPTIONS += marm/mthumb +MULTILIB_DIRNAMES += arm thumb + +MULTILIB_OPTIONS += mfpu=auto +MULTILIB_DIRNAMES += autofp + +MULTILIB_OPTIONS += march=armv5te+fp/march=armv7+fp +MULTILIB_DIRNAMES += v5te v7 + +MULTILIB_OPTIONS += mfloat-abi=hard +MULTILIB_DIRNAMES += fpu + +# Build a total of 4 library variants (base options plus the following): +MULTILIB_REQUIRED += mthumb +MULTILIB_REQUIRED += marm/mfpu=auto/march=armv5te+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/mfpu=auto/march=armv7+fp/mfloat-abi=hard + +# PART 3 - Match rules + +# Map all supported FPUs onto mfpu=auto +MULTILIB_MATCHES += $(foreach FPU, $(dp_fpus), \ + mfpu?auto=mfpu?$(FPU)) + +MULTILIB_MATCHES += march?armv5te+fp=march?armv5te + +MULTILIB_MATCHES += $(foreach ARCH, $(all_early_arch), \ + march?armv5te+fp=march?$(ARCH) \ + march?armv5te+fp=march?$(ARCH)+fp) + +MULTILIB_MATCHES += march?armv7+fp=march?armv7 + +MULTILIB_MATCHES += $(foreach FPARCH, $(v7a_fps), \ + march?armv7+fp=march?armv7-a+$(FPARCH)) + +MULTILIB_MATCHES += $(foreach FPARCH, $(v7ve_fps), \ + march?armv7+fp=march?armv7ve+$(FPARCH)) + +MULTILIB_MATCHES += $(foreach ARCH, $(all_v7_a_r), \ + march?armv7+fp=march?$(ARCH) \ + march?armv7+fp=march?$(ARCH)+fp) + +MULTILIB_MATCHES += $(foreach ARCH, $(all_v8_archs), \ + march?armv7+fp=march?$(ARCH) \ + $(foreach FPARCH, $(v8_fps), \ + march?armv7+fp=march?$(ARCH)+$(FPARCH))) + +MULTILIB_MATCHES += $(foreach ARCH, armv7e-m armv8-m.mainline, \ + march?armv7+fp=march?$(ARCH)+fp.dp) + +# PART 4 - Reuse rules -#MULTILIB_OPTIONS += mcpu=fa526/mcpu=fa626/mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te -#MULTILIB_DIRNAMES += fa526 fa626 fa606te fa626te fmp626 fa726te -#MULTILIB_EXCEPTIONS += *mthumb*/*mcpu=fa526 *mthumb*/*mcpu=fa626 - -#MULTILIB_OPTIONS += march=armv7 -#MULTILIB_DIRNAMES += thumb2 -#MULTILIB_EXCEPTIONS += march=armv7* marm/*march=armv7* -#MULTILIB_MATCHES += march?armv7=march?armv7-a -#MULTILIB_MATCHES += march?armv7=march?armv7-r -#MULTILIB_MATCHES += march?armv7=march?armv7-m -#MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8 -#MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4 -#MULTILIB_MATCHES += march?armv7=mcpu?cortex-m3 - -# Not quite true. We can support hard-vfp calling in Thumb2, but how do we -# express that here? Also, we really need architecture v5e or later -# (mcrr etc). -MULTILIB_OPTIONS += mfloat-abi=hard -MULTILIB_DIRNAMES += fpu -MULTILIB_EXCEPTIONS += *mthumb/*mfloat-abi=hard* -#MULTILIB_EXCEPTIONS += *mcpu=fa526/*mfloat-abi=hard* -#MULTILIB_EXCEPTIONS += *mcpu=fa626/*mfloat-abi=hard* - -# MULTILIB_OPTIONS += mcpu=ep9312 -# MULTILIB_DIRNAMES += ep9312 -# MULTILIB_EXCEPTIONS += *mthumb/*mcpu=ep9312* -# -# MULTILIB_OPTIONS += mlittle-endian/mbig-endian -# MULTILIB_DIRNAMES += le be -# MULTILIB_MATCHES += mbig-endian=mbe mlittle-endian=mle -# -# MULTILIB_OPTIONS += mfloat-abi=hard/mfloat-abi=soft -# MULTILIB_DIRNAMES += fpu soft -# MULTILIB_EXCEPTIONS += *mthumb/*mfloat-abi=hard* -# -# MULTILIB_OPTIONS += mno-thumb-interwork/mthumb-interwork -# MULTILIB_DIRNAMES += normal interwork -# -# MULTILIB_OPTIONS += fno-leading-underscore/fleading-underscore -# MULTILIB_DIRNAMES += elf under -# -# MULTILIB_OPTIONS += mcpu=arm7 -# MULTILIB_DIRNAMES += nofmult -# MULTILIB_EXCEPTIONS += *mthumb*/*mcpu=arm7* -# # Note: the multilib_exceptions matches both -mthumb and -# # -mthumb-interwork -# # -# # We have to match all the arm cpu variants which do not have the -# # multiply instruction and treat them as if the user had specified -# # -mcpu=arm7. Note that in the following the ? is interpreted as -# # an = for the purposes of matching command line options. -# # FIXME: There ought to be a better way to do this. -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm7d -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm7di -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm70 -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm700 -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm700i -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm710 -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm710c -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm7100 -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm7500 -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm7500fe -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm6 -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm60 -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm600 -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm610 -# MULTILIB_MATCHES += mcpu?arm7=mcpu?arm620 +MULTILIB_REUSE += mthumb=mthumb/mfpu.auto +MULTILIB_REUSE += mthumb=mthumb/mfpu.auto/march.armv5te+fp +MULTILIB_REUSE += mthumb=mthumb/march.armv5te+fp +MULTILIB_REUSE += marm/mfpu.auto/march.armv5te+fp/mfloat-abi.hard=marm/march.armv5te+fp/mfloat-abi.hard +MULTILIB_REUSE += marm/mfpu.auto/march.armv5te+fp/mfloat-abi.hard=march.armv5te+fp/mfloat-abi.hard +MULTILIB_REUSE += marm/mfpu.auto/march.armv5te+fp/mfloat-abi.hard=mfpu.auto/march.armv5te+fp/mfloat-abi.hard +MULTILIB_REUSE += mthumb/mfpu.auto/march.armv7+fp/mfloat-abi.hard=mthumb/march.armv7+fp/mfloat-abi.hard +MULTILIB_REUSE += mthumb/mfpu.auto/march.armv7+fp/mfloat-abi.hard=mfpu.auto/march.armv7+fp/mfloat-abi.hard +MULTILIB_REUSE += mthumb/mfpu.auto/march.armv7+fp/mfloat-abi.hard=march.armv7+fp/mfloat-abi.hard -- cgit v1.1 From 11389610242c157e43dd5c1f469970e514efe60a Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:04:23 +0000 Subject: [arm] Make 'auto' the default FPU selection option. Finally, we can make 'auto' the default choice for the FPU option. It's still possible to override this during configure, but we will eventually deprecate that, moving to the new cpu/architecture selection mechanism. * config/arm/arm.h (FPUTYPE_AUTO): Define. * config/arm/arm.c (arm_option_override): Use FPUTYPE_AUTO if the fpu is not specified by the user/command-line. * config/arm/bpabi.h (FPUTYPE_DEFAULT): Delete. * config/arm/netbsd-elf.h (FPUTYPE_DEFAULT): Delete. * config/arm/linux-elf.h (FPUTYPE_DEFAULT): Delete. * config/arm/vxworks.h (FPUTYPE_DEFAULT): Delete. * common/config/arm/arm-common.c (arm_canon_arch_option): Use FPUTYPE_AUTO insted of FPUTYPE_DEFAULT. From-SVN: r249295 --- gcc/ChangeLog | 12 ++++++++++++ gcc/common/config/arm/arm-common.c | 2 +- gcc/config/arm/arm.c | 9 +-------- gcc/config/arm/arm.h | 3 +++ gcc/config/arm/bpabi.h | 4 ---- gcc/config/arm/linux-elf.h | 3 --- gcc/config/arm/netbsd-elf.h | 4 ---- gcc/config/arm/vxworks.h | 2 -- 8 files changed, 17 insertions(+), 22 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1330539..d543614 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2017-06-16 Richard Earnshaw + * config/arm/arm.h (FPUTYPE_AUTO): Define. + * config/arm/arm.c (arm_option_override): Use FPUTYPE_AUTO if the + fpu is not specified by the user/command-line. + * config/arm/bpabi.h (FPUTYPE_DEFAULT): Delete. + * config/arm/netbsd-elf.h (FPUTYPE_DEFAULT): Delete. + * config/arm/linux-elf.h (FPUTYPE_DEFAULT): Delete. + * config/arm/vxworks.h (FPUTYPE_DEFAULT): Delete. + * common/config/arm/arm-common.c (arm_canon_arch_option): Use + FPUTYPE_AUTO insted of FPUTYPE_DEFAULT. + +2017-06-16 Richard Earnshaw + * config/arm/elf.h (MULTILIB_DEFAULTS): Delete. * config/arm/t-arm-elf: Rewritten. diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index 30cb61e..86170e1 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -520,7 +520,7 @@ arm_canon_arch_option (int argc, const char **argv) gcc_assert (cpu || arch); if (!fpu) - fpu = FPUTYPE_DEFAULT; + fpu = FPUTYPE_AUTO; if (!abi) { diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 385792d..f3b2715 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3298,17 +3298,10 @@ arm_option_override (void) if (!global_options_set.x_arm_fpu_index) { - const char *target_fpu_name; bool ok; int fpu_index; -#ifdef FPUTYPE_DEFAULT - target_fpu_name = FPUTYPE_DEFAULT; -#else - target_fpu_name = "vfp"; -#endif - - ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &fpu_index, + ok = opt_enum_arg_to_value (OPT_mfpu_, FPUTYPE_AUTO, &fpu_index, CL_TARGET); gcc_assert (ok); arm_fpu_index = (enum fpu_type) fpu_index; diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 92361fc..43d4477 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2220,6 +2220,9 @@ extern int making_const_table; (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ : 0) +/* Name of the automatic fpu-selection option. */ +#define FPUTYPE_AUTO "auto" + /* The maximum number of parallel loads or stores we support in an ldm/stm instruction. */ #define MAX_LDM_STM_OPS 4 diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index f9f9a92..d38863a 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -33,10 +33,6 @@ #undef ARM_UNWIND_INFO #define ARM_UNWIND_INFO 1 -/* Section 4.1 of the AAPCS requires the use of VFP format. */ -#undef FPUTYPE_DEFAULT -#define FPUTYPE_DEFAULT "vfp" - /* TARGET_BIG_ENDIAN_DEFAULT is set in config.gcc for big endian configurations. */ #if TARGET_BIG_ENDIAN_DEFAULT diff --git a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h index 3d62367..cd4fc3b 100644 --- a/gcc/config/arm/linux-elf.h +++ b/gcc/config/arm/linux-elf.h @@ -83,9 +83,6 @@ } \ while (0) -#undef FPUTYPE_DEFAULT -#define FPUTYPE_DEFAULT "vfp" - /* Call the function profiler with a given profile label. */ #undef ARM_FUNCTION_PROFILER #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ diff --git a/gcc/config/arm/netbsd-elf.h b/gcc/config/arm/netbsd-elf.h index 8811af7..02ff316 100644 --- a/gcc/config/arm/netbsd-elf.h +++ b/gcc/config/arm/netbsd-elf.h @@ -153,7 +153,3 @@ do \ (void) sysarch (0, &s); \ } \ while (0) - -#undef FPUTYPE_DEFAULT -#define FPUTYPE_DEFAULT "vfp" - diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h index 107863b..9af37c7 100644 --- a/gcc/config/arm/vxworks.h +++ b/gcc/config/arm/vxworks.h @@ -92,8 +92,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* There is no default multilib. */ #undef MULTILIB_DEFAULTS -#define FPUTYPE_DEFAULT "vfp" - #undef FUNCTION_PROFILER #define FUNCTION_PROFILER VXWORKS_FUNCTION_PROFILER -- cgit v1.1 From 93aa40fee604dea0c2d0bbac088b074cee119c68 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:04:41 +0000 Subject: [arm] Rewrite t-aprofile using new selector methodology Now that the default FPU is 'auto' we can finally rewrite (and simplify) the rules for mapping compiler options to multilibs. We no-longer need to know the specific CPU, since the driver will construct a suitable -march flag for us; this greatly simplifies the overall logic. This patch rewrites the library list for A-profile cores. We use various Make extention rules to simplify the logic even further. A couple of minor tweaks to the configure script and to the main driver ensures that we always know the setting of -mfloat-abi and -marm/-mthumb. Again, this helps simplify the logic further. The change to arm_target_thumb_only relies on the fact that this routine is only called if neither -marm nor -mthumb has been previously selected or specified by the user. A new testsuite module is added to check the libraries generated. The new tests are only run if the compiler is configured with the relevant multilibs enabled. gcc: * config.gcc: (arm*-*-*): When building a-profile libraries, force the driver to pass through the default setting of -mfloat-abi. * common/config/arm/arm-common.c (arm_target_thumb_only): Return -marm rather than NULL. * config/arm/t-multilib (MULTILIB_REUSE): Initialize to empty. (all_feat_combs): New rule. (MULTILIB_OPTIONS): Use explicit ARM and Thumb directories. Rework default libraries. * config/arm/t-aprofile: Rewrite. gcc/testsuite: * gcc.target/arm/multilibs.exp: New file. From-SVN: r249296 --- gcc/ChangeLog | 12 + gcc/common/config/arm/arm-common.c | 4 +- gcc/config.gcc | 4 +- gcc/config/arm/t-aprofile | 211 +++++++---------- gcc/config/arm/t-multilib | 48 ++-- gcc/testsuite/ChangeLog | 4 + gcc/testsuite/gcc.target/arm/multilib.exp | 381 ++++++++++++++++++++++++++++++ 7 files changed, 514 insertions(+), 150 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/multilib.exp (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d543614..35ded57 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2017-06-16 Richard Earnshaw + * config.gcc: (arm*-*-*): When building a-profile libraries, force + the driver to pass through the default setting of -mfloat-abi. + * common/config/arm/arm-common.c (arm_target_thumb_only): Return -marm + rather than NULL. + * config/arm/t-multilib (MULTILIB_REUSE): Initialize to empty. + (all_feat_combs): New rule. + (MULTILIB_OPTIONS): Use explicit ARM and Thumb directories. Rework + default libraries. + * config/arm/t-aprofile: Rewrite. + +2017-06-16 Richard Earnshaw + * config/arm/arm.h (FPUTYPE_AUTO): Define. * config/arm/arm.c (arm_option_override): Use FPUTYPE_AUTO if the fpu is not specified by the user/command-line. diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index 86170e1..d06c39b 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -215,7 +215,9 @@ arm_target_thumb_only (int argc, const char **argv) return "-mthumb"; } - return NULL; + /* Compiler hasn't been configured with a default, and the CPU + doesn't require Thumb, so default to ARM. */ + return "-marm"; } /* List the permitted CPU option names. If TARGET is a near miss for an diff --git a/gcc/config.gcc b/gcc/config.gcc index f3923fd..94a281d 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3856,7 +3856,9 @@ case "${target}" in echo "Error: You cannot use any of --with-arch/cpu/fpu/float/mode with --with-multilib-list=${with_multilib_list}" 1>&2 exit 1 fi - + # But pass the default value for float-abi + # through to the multilib selector + with_float="soft" tmake_file="${tmake_file} ${tmake_profile_file}" TM_MULTILIB_CONFIG="$with_multilib_list" fi diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index 10e2d34..2e3d4c8 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -24,145 +24,98 @@ # have their default values during the configure step. We enforce # this during the top-level configury. +# Variables used later in this file. + +v7_a_nosimd_variants := +fp +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +vfpv4-d16 +vfpv4 +v7_a_simd_variants := +simd +neon-fp16 +neon-vfpv4 +v7ve_nosimd_variants := +vfpv3-d16 +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +fp +vfpv4 +v7ve_vfpv3_simd_variants := +neon +neon-fp16 +v7ve_vfpv4_simd_variants := +simd +v8_a_nosimd_variants := +crc +v8_a_simd_variants := $(call all_feat_combs, simd crypto) +v8_1_a_simd_variants := $(call all_feat_combs, simd crypto) +v8_2_a_simd_variants := $(call all_feat_combs, simd fp16 crypto) + + # Arch and FPU variants to build libraries with -MULTI_ARCH_OPTS_A = march=armv7-a/march=armv7ve/march=armv8-a -MULTI_ARCH_DIRS_A = v7-a v7ve v8-a +MULTI_ARCH_OPTS_A = march=armv7-a/march=armv7-a+fp/march=armv7-a+simd/march=armv7ve+simd/march=armv8-a/march=armv8-a+simd +MULTI_ARCH_DIRS_A = v7-a v7-a+fp v7-a+simd v7ve+simd v8-a v8-a+simd -MULTI_FPU_OPTS_A = mfpu=vfpv3-d16/mfpu=neon/mfpu=vfpv4-d16/mfpu=neon-vfpv4/mfpu=neon-fp-armv8 -MULTI_FPU_DIRS_A = fpv3 simdv1 fpv4 simdvfpv4 simdv8 +# ARMv7-A - build nofp, fp-d16 and SIMD variants +MULTILIB_REQUIRED += mthumb/march=armv7-a/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv7-a+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7-a+fp/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv7-a+simd/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7-a+simd/mfloat-abi=softfp -# Option combinations to build library with +# ARMv7VE - only build a SIMD (+VFPv4) variant. +MULTILIB_REQUIRED += mthumb/march=armv7ve+simd/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7ve+simd/mfloat-abi=softfp -# Default CPU/Arch (ARM is implicitly included because it uses the default -# multilib) -MULTILIB_REQUIRED += mthumb +# ARMv8-A - build nofp and SIMD variants. +MULTILIB_REQUIRED += mthumb/march=armv8-a/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv8-a+simd/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv8-a+simd/mfloat-abi=softfp -# ARMv7-A -MULTILIB_REQUIRED += *march=armv7-a -MULTILIB_REQUIRED += *march=armv7-a/mfpu=vfpv3-d16/mfloat-abi=* -MULTILIB_REQUIRED += *march=armv7-a/mfpu=neon/mfloat-abi=* +# Matches -# ARMv7VE -MULTILIB_REQUIRED += *march=armv7ve -MULTILIB_REQUIRED += *march=armv7ve/mfpu=vfpv4-d16/mfloat-abi=* -MULTILIB_REQUIRED += *march=armv7ve/mfpu=neon-vfpv4/mfloat-abi=* +# Arch Matches +# Map all v7-a FP variants to vfpv3-d16 (+fp) +MULTILIB_MATCHES += $(foreach ARCH, $(filter-out +fp, $(v7_a_nosimd_variants)), \ + march?armv7-a+fp=march?armv7-a$(ARCH)) -# ARMv8-A -MULTILIB_REQUIRED += *march=armv8-a -MULTILIB_REQUIRED += *march=armv8-a/mfpu=neon-fp-armv8/mfloat-abi=* +# Map all v7-a SIMD variants to neon-vfpv3 (+simd) +MULTILIB_MATCHES += $(foreach ARCH, $(filter-out +simd, $(v7_a_simd_variants)), \ + march?armv7-a+simd=march?armv7-a$(ARCH)) +# Neither FP nor SIMD: map v7ve to v7-a +MULTILIB_MATCHES += march?armv7-a=march?armv7ve -# Matches +# ARMv7ve FP-only variants: map down to v7-a+fp +MULTILIB_MATCHES += $(foreach ARCH, $(v7ve_nosimd_variants), \ + march?armv7-a+fp=march?armv7ve$(ARCH)) -# CPU Matches -MULTILIB_MATCHES += march?armv7-a=mcpu?marvell-pj4 -MULTILIB_MATCHES += march?armv7-a=mcpu?generic-armv7-a -MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a8 -MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a9 -MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a5 -MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a7 -MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a15 -MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a12 -MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a17 -MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a15.cortex-a7 -MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a17.cortex-a7 -MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a32 -MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a35 -MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a53 -MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57 -MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57.cortex-a53 -MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a72 -MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a72.cortex-a53 -MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73 -MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a35 -MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a53 -MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1 -MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1 +# ARMv7ve with SIMD, but SIMD is less capable than the default - map down to v7-a+simd +MULTILIB_MATCHES += $(foreach ARCH, $(v7ve_vfpv3_simd_variants), \ + march?armv7-a+simd=march?armv7ve$(ARCH)) -# Arch Matches -MULTILIB_MATCHES += march?armv8-a=march?armv8-a+crc -MULTILIB_MATCHES += march?armv8-a=march?armv8.1-a -MULTILIB_MATCHES += march?armv8-a=march?armv8.1-a+crc -MULTILIB_MATCHES += march?armv8-a=march?armv8.2-a -MULTILIB_MATCHES += march?armv8-a=march?armv8.2-a+fp16 - -# FPU matches -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-d16-fp16 -MULTILIB_MATCHES += mfpu?neon=mfpu?neon-fp16 -MULTILIB_MATCHES += mfpu?vfpv4-d16=mfpu?vfpv4 -MULTILIB_MATCHES += mfpu?vfpv4-d16=mfpu?fpv5-d16 -MULTILIB_MATCHES += mfpu?vfpv4-d16=mfpu?fp-armv8 -MULTILIB_MATCHES += mfpu?neon-fp-armv8=mfpu?crypto-neon-fp-armv8 -MULTILIB_MATCHES += mfpu?vfp=mfpu?vfpv2 -MULTILIB_MATCHES += mfpu?neon=mfpu?neon-vfpv3 - - -# Map all requests for vfpv3 with a later CPU to vfpv3-d16 v7-a. -# So if new CPUs are added above at the newer architecture levels, -# do something to map them below here. -# We take the approach of mapping down to v7-a regardless of what -# the fp option is if the integer architecture brings things down. -# This applies to any similar combination at the v7ve and v8-a arch -# levels. - -MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7ve/mfpu.vfpv3-d16/mfloat-abi.hard -MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7ve/mfpu.vfpv3-d16/mfloat-abi.softfp -MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.hard -MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp -MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard -MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp - - -MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7ve/mfpu.neon/mfloat-abi.hard -MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7ve/mfpu.neon/mfloat-abi.softfp -MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv8-a/mfpu.neon/mfloat-abi.hard -MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv8-a/mfpu.neon/mfloat-abi.softfp -MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.hard -MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.softfp -MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.hard -MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp - - -MULTILIB_REUSE += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard -MULTILIB_REUSE += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp - - -MULTILIB_REUSE += march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.hard=march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.hard -MULTILIB_REUSE += march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.softfp=march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.softfp -MULTILIB_REUSE += march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.hard=march.armv7ve/mfpu.neon-fp-armv8/mfloat-abi.hard -MULTILIB_REUSE += march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.softfp=march.armv7ve/mfpu.neon-fp-armv8/mfloat-abi.softfp - - - -# And again for mthumb. - -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7ve/mfpu.vfpv3-d16/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7ve/mfpu.vfpv3-d16/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp - - -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7ve/mfpu.neon/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7ve/mfpu.neon/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.neon/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.neon/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-vfpv4/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp - - -MULTILIB_REUSE += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp - - -MULTILIB_REUSE += mthumb/march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.hard=mthumb/march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.neon-vfpv4/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.hard=mthumb/march.armv7ve/mfpu.neon-fp-armv8/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7ve/mfpu.neon-vfpv4/mfloat-abi.softfp=mthumb/march.armv7ve/mfpu.neon-fp-armv8/mfloat-abi.softfp +# ARMv8 without SIMD: map down to base architecture +MULTILIB_MATCHES += $(foreach ARCH, $(v8_a_nosimd_variants), \ + march?armv8-a=march?armv8-a$(ARCH)) + +# ARMv8 with SIMD: map down to base arch + simd +MULTILIB_MATCHES += march?armv8-a+simd=march?armv8-a+crc+simd \ + $(foreach ARCH, $(filter-out +simd, $(v8_a_simd_variants)), \ + march?armv8-a+simd=march?armv8-a$(ARCH) \ + march?armv8-a+simd=march?armv8-a+crc$(ARCH)) + +# Baseline v8.1-a: map down to baseline v8-a +MULTILIB_MATCHES += march?armv8-a=march?armv8.1-a + +# Map all v8.1-a SIMD variants to v8-a+simd +MULTILIB_MATCHES += $(foreach ARCH, $(v8_1_a_simd_variants), \ + march?armv8-a+simd=march?armv8.1-a$(ARCH)) + +# Baseline v8.2-a: map down to baseline v8-a +MULTILIB_MATCHES += march?armv8-a=march?armv8.2-a + +# Map all v8.2-a SIMD variants to v8-a+simd +MULTILIB_MATCHES += $(foreach ARCH, $(v8_2_a_simd_variants), \ + march?armv8-a+simd=march?armv8.2-a$(ARCH)) + +# Use Thumb libraries for everything. + +MULTILIB_REUSE += mthumb/march.armv7-a/mfloat-abi.soft=marm/march.armv7-a/mfloat-abi.soft + +MULTILIB_REUSE += mthumb/march.armv8-a/mfloat-abi.soft=marm/march.armv8-a/mfloat-abi.soft + +MULTILIB_REUSE += $(foreach ABI, hard softfp, \ + $(foreach ARCH, armv7-a+fp armv7-a+simd armv7ve+simd armv8-a+simd, \ + mthumb/march.$(ARCH)/mfloat-abi.$(ABI)=marm/march.$(ARCH)/mfloat-abi.$(ABI))) + +# Softfp but no FP, use the soft-float libraries. +MULTILIB_REUSE += $(foreach MODE, arm thumb, \ + $(foreach ARCH, armv7-a armv8-a, \ + mthumb/march.$(ARCH)/mfloat-abi.soft=m$(MODE)/march.$(ARCH)/mfloat-abi.softfp)) diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib index 642e731..77ce762 100644 --- a/gcc/config/arm/t-multilib +++ b/gcc/config/arm/t-multilib @@ -29,6 +29,7 @@ MULTILIB_DIRNAMES = MULTILIB_EXCEPTIONS = MULTILIB_MATCHES = MULTILIB_REUSE = +MULTILIB_REQUIRED = comma := , tm_multilib_list := $(subst $(comma), ,$(TM_MULTILIB_CONFIG)) @@ -36,6 +37,26 @@ tm_multilib_list := $(subst $(comma), ,$(TM_MULTILIB_CONFIG)) HAS_APROFILE := $(filter aprofile,$(tm_multilib_list)) HAS_RMPROFILE := $(filter rmprofile,$(tm_multilib_list)) +# Produce the combinatorial list of extensions. Where there are +# multiple permutations for a combination, the ordering is the +# selected by the forward ordering of the original list. This matches +# the canonical ordering generated by the canonicalizer in the driver. +# +# For example, +# $(call all_feat_combs, a b) +# will produce +# +a +a+b +b +# but will not include +# +b+a +# The rule is recursive and can be called with any (reasonable) list of +# extensions. +all_feat_combs = +$(firstword $(1)) \ + $(if $(wordlist 2, $(words $(1)), $(1)), \ + $(foreach OPT, \ + $(call all_feat_combs, \ + $(wordlist 2, $(words $(1)), $(1))), \ + +$(firstword $(1))$(OPT) $(OPT)),) + ifneq (,$(HAS_APROFILE)) include $(srcdir)/config/arm/t-aprofile endif @@ -45,25 +66,14 @@ endif SEP := $(and $(HAS_APROFILE),$(HAS_RMPROFILE),/) -# We have the following hierachy: -# ISA: A32 (.) or T16/T32 (thumb) -# Architecture: ARMv6-M (v6-m), ARMv7-M (v7-m), ARMv7E-M (v7e-m), -# ARMv7 (v7-ar), ARMv7-A (v7-a), ARMv7VE (v7ve), -# ARMv8-M Baseline (v8-m.base), ARMv8-M Mainline (v8-m.main) -# or ARMv8-A (v8-a). -# FPU: VFPv3-D16 (fpv3), NEONv1 (simdv1), FPV4-SP-D16 (fpv4-sp), -# VFPv4-D16 (fpv4), NEON-VFPV4 (simdvfpv4), FPV5-SP-D16 (fpv5-sp), -# VFPv5-D16 (fpv5), NEON for ARMv8 (simdv8), or None (.). -# Float-abi: Soft (.), softfp (softfp), or hard (hard). - -MULTILIB_OPTIONS += mthumb -MULTILIB_DIRNAMES += thumb +MULTILIB_OPTIONS += marm/mthumb +MULTILIB_DIRNAMES += arm thumb -MULTILIB_OPTIONS += $(MULTI_ARCH_OPTS_A)$(SEP)$(MULTI_ARCH_OPTS_RM) -MULTILIB_DIRNAMES += $(MULTI_ARCH_DIRS_A) $(MULTI_ARCH_DIRS_RM) +MULTILIB_OPTIONS += march=armv5te+fp/$(MULTI_ARCH_OPTS_A)$(SEP)$(MULTI_ARCH_OPTS_RM) +MULTILIB_DIRNAMES += v5te $(MULTI_ARCH_DIRS_A) $(MULTI_ARCH_DIRS_RM) -MULTILIB_OPTIONS += $(MULTI_FPU_OPTS_A)$(SEP)$(MULTI_FPU_OPTS_RM) -MULTILIB_DIRNAMES += $(MULTI_FPU_DIRS_A) $(MULTI_FPU_DIRS_RM) +MULTILIB_OPTIONS += mfloat-abi=soft/mfloat-abi=softfp/mfloat-abi=hard +MULTILIB_DIRNAMES += nofp softfp hard -MULTILIB_OPTIONS += mfloat-abi=softfp/mfloat-abi=hard -MULTILIB_DIRNAMES += softfp hard +MULTILIB_REQUIRED += mthumb/mfloat-abi=soft +MULTILIB_REQUIRED += marm/march=armv5te+fp/mfloat-abi=hard diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 962c388..13dffb3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-16 Richard Earnshaw + + * gcc.target/arm/multilibs.exp: New file. + 2017-06-16 Martin Sebor PR tree-optimization/80933 diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp new file mode 100644 index 0000000..bef5be8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/multilib.exp @@ -0,0 +1,381 @@ +# Copyright (C) 2017 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +load_lib gcc-dg.exp + +dg-init + +if { [board_info [target_info name] exists multilib_flags] + && [regexp {(-marm|-mthumb|-march=.*|-mcpu=.*|-mfpu=.*|-mfloat=abi=.*)\y} [board_info [target_info name] multilib_flags]] } { + + # Multilib flags override anything we can apply to a test, so + # skip if any of the above options are set there. + verbose "skipping multilib tests due to multilib_flags setting" 1 + return +} + +# We don't want to run this test multiple times in a parallel make check. +if ![gcc_parallel_test_run_p options] { + return +} +gcc_parallel_test_enable 0 + +proc multilib_config {profile} { + return [check_configured_with [join [list {with-multilib-list=([^ ]+,)?} $profile {(,[^ ]+)?}] ""]] +} + +proc check_multi_dir { gcc_opts multi_dir } { + global tool + + set gcc_output [${tool}_target_compile "--print-multi-directory $gcc_opts" "" "none" ""] + if { [string match "$multi_dir\n" $gcc_output] } { + pass "multilibdir $gcc_opts $multi_dir" + } else { + fail "multilibdir $gcc_opts $multi_dir" + } +} + +if {[multilib_config "aprofile"] } { + foreach {opts dir} { + {-mcpu=cortex-a8 -mfloat-abi=soft} "thumb/v7-a/nofp" + {-mcpu=cortex-a8 -mfloat-abi=softfp} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a8 -mfloat-abi=hard} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a15} "thumb/v7-a/nofp" + {-mcpu=cortex-a15 -mfloat-abi=hard} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a15 -marm -mfloat-abi=hard} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a15 -mthumb -mfloat-abi=hard} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a7+nosimd -mfloat-abi=hard} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7+nofp -mfloat-abi=softfp} "thumb/v7-a/nofp" + {-mcpu=generic-armv7-a+vfpv4 -mfloat-abi=softfp} "thumb/v7-a+fp/softfp" + {-march=armv7ve+vfpv3 -mfloat-abi=hard} "thumb/v7-a+fp/hard" + {-march=armv7ve -mfloat-abi=softfp -mfpu=neon} "thumb/v7-a+simd/softfp" + {-march=armv7ve -mfloat-abi=softfp -mfpu=neon-vfpv4} "thumb/v7ve+simd/softfp" + {-march=armv7ve -mfloat-abi=softfp -mfpu=vfpv4} "thumb/v7-a+fp/softfp" + {-march=armv8-a+crc+simd -mfloat-abi=soft} "thumb/v8-a/nofp" + {-march=armv8-a+crc+simd -mfloat-abi=softfp} "thumb/v8-a+simd/softfp" + {-march=armv8.1-a+crypto -mfloat-abi=soft} "thumb/v8-a/nofp" + {-march=armv8.1-a+crypto -mfloat-abi=softfp} "thumb/v8-a+simd/softfp" + {-march=armv8.2-a+crypto -mfloat-abi=soft} "thumb/v8-a/nofp" + {-march=armv8.2-a+simd+crypto -mfloat-abi=softfp} "thumb/v8-a+simd/softfp" + {-march=armv8.2-a+simd+crypto+nofp -mfloat-abi=softfp} "thumb/v8-a/nofp" + {-march=armv8.2-a+simd+nofp+crypto -mfloat-abi=softfp} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a53+crypto -mfloat-abi=hard} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a53+nofp -mfloat-abi=softfp} "thumb/v8-a/nofp" + {-march=armv8-a+crc -mfloat-abi=hard -mfpu=vfp} "thumb/v8-a+simd/hard" + {-march=armv8-a+crc+simd -mfloat-abi=soft -mfpu=neon} "thumb/v8-a/nofp" + {-mcpu=cortex-a8 -mfpu=vfpv3-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=vfpv3-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=vfpv3-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=vfpv3-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=vfpv3-d16 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=vfpv3 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=vfpv3 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=vfpv3 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=vfpv3 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=vfpv3 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=vfpv4-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=vfpv4-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=vfpv4-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=vfpv4-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=vfpv4-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=vfpv4-d16 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=vfpv4 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=vfpv4 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=vfpv4 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=vfpv4 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=vfpv4 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=vfpv4 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=neon -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a5 -mfpu=neon -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a9 -mfpu=neon -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a7 -mfpu=neon -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a15 -mfpu=neon -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a53 -mfpu=neon -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=neon-vfpv4 -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a5 -mfpu=neon-vfpv4 -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a9 -mfpu=neon-vfpv4 -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard -marm} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a15 -mfpu=neon-vfpv4 -mfloat-abi=hard -marm} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a53 -mfpu=neon-vfpv4 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=fp-armv8 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=neon-fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a5 -mfpu=neon-fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a9 -mfpu=neon-fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a7 -mfpu=neon-fp-armv8 -mfloat-abi=hard -marm} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a15 -mfpu=neon-fp-armv8 -mfloat-abi=hard -marm} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a53 -mfpu=neon-fp-armv8 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=vfpv3-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=vfpv3-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=vfpv3-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=vfpv3-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=vfpv3-d16 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=vfpv3 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=vfpv3 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=vfpv3 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=vfpv3 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=vfpv3 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=vfpv4-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=vfpv4-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=vfpv4-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=vfpv4-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=vfpv4-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=vfpv4-d16 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=vfpv4 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=vfpv4 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=vfpv4 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=vfpv4 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=vfpv4 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=vfpv4 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a5 -mfpu=neon -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a9 -mfpu=neon -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a7 -mfpu=neon -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a15 -mfpu=neon -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a53 -mfpu=neon -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=neon-vfpv4 -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a5 -mfpu=neon-vfpv4 -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a9 -mfpu=neon-vfpv4 -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=softfp -marm} "thumb/v7ve+simd/softfp" + {-mcpu=cortex-a15 -mfpu=neon-vfpv4 -mfloat-abi=softfp -marm} "thumb/v7ve+simd/softfp" + {-mcpu=cortex-a53 -mfpu=neon-vfpv4 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=fp-armv8 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a5 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a9 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a7 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7ve+simd/softfp" + {-mcpu=cortex-a15 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7ve+simd/softfp" + {-mcpu=cortex-a53 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=vfpv3-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=vfpv3-d16 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=vfpv3-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=vfpv3-d16 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=vfpv3 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=vfpv3 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=vfpv3 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=vfpv3 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=vfpv4-d16 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=vfpv4-d16 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=vfpv4-d16 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=vfpv4-d16 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=vfpv4 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=vfpv4 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=vfpv4 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=vfpv4 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=neon -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-march=armv8-a -mfpu=neon -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=neon -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-march=armv8-a -mfpu=neon -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-march=armv8-a -mfpu=neon-vfpv4 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-march=armv8-a -mfpu=neon-vfpv4 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=fp-armv8 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=fp-armv8 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=neon-fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=neon-fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=hard -marm} "thumb/v7-a+simd/hard" + {-march=armv8-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=hard -marm} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp -marm} "thumb/v7-a+simd/softfp" + {-march=armv8-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp -marm} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=vfpv3 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=vfpv3 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=vfpv3 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=vfpv3 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=vfpv3 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=vfpv4-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=vfpv4-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=vfpv4-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=vfpv4-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=vfpv4-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=vfpv4-d16 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=vfpv4 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=neon -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a5 -mfpu=neon -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a9 -mfpu=neon -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a7 -mfpu=neon -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a15 -mfpu=neon -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a53 -mfpu=neon -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=neon-vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a5 -mfpu=neon-vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a9 -mfpu=neon-vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a15 -mfpu=neon-vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a53 -mfpu=neon-vfpv4 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a5 -mfpu=fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a9 -mfpu=fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a7 -mfpu=fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a15 -mfpu=fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-mcpu=cortex-a53 -mfpu=fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=neon-fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a5 -mfpu=neon-fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a9 -mfpu=neon-fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-mcpu=cortex-a7 -mfpu=neon-fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a15 -mfpu=neon-fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7ve+simd/hard" + {-mcpu=cortex-a53 -mfpu=neon-fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-mcpu=cortex-a8 -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=vfpv3 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=vfpv3 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=vfpv3 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=vfpv3 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=vfpv3 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=vfpv4-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=vfpv4-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=vfpv4-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=vfpv4-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=vfpv4-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=vfpv4-d16 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a5 -mfpu=neon -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a9 -mfpu=neon -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a7 -mfpu=neon -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a15 -mfpu=neon -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a53 -mfpu=neon -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=neon-vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a5 -mfpu=neon-vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a9 -mfpu=neon-vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7ve+simd/softfp" + {-mcpu=cortex-a15 -mfpu=neon-vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7ve+simd/softfp" + {-mcpu=cortex-a53 -mfpu=neon-vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a5 -mfpu=fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a9 -mfpu=fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a7 -mfpu=fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a15 -mfpu=fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-mcpu=cortex-a53 -mfpu=fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-mcpu=cortex-a8 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a5 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a9 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-mcpu=cortex-a7 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7ve+simd/softfp" + {-mcpu=cortex-a15 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7ve+simd/softfp" + {-mcpu=cortex-a53 -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=vfpv3-d16 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=vfpv3-d16-fp16 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=vfpv3-d16-fp16 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=vfpv3 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=vfpv3 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=vfpv3 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=vfpv3 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=vfpv4-d16 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=vfpv4-d16 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=vfpv4-d16 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=vfpv4-d16 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=vfpv4 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=neon -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-march=armv8-a -mfpu=neon -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=neon -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-march=armv8-a -mfpu=neon -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-march=armv8-a -mfpu=neon-vfpv4 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-march=armv8-a -mfpu=neon-vfpv4 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+fp/hard" + {-march=armv8-a -mfpu=fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+fp/softfp" + {-march=armv8-a -mfpu=fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=neon-fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + {-march=armv7-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v7-a+simd/hard" + {-march=armv8-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=hard -mthumb} "thumb/v8-a+simd/hard" + {-march=armv7-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v7-a+simd/softfp" + {-march=armv8-a -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp -mthumb} "thumb/v8-a+simd/softfp" + } { + check_multi_dir $opts $dir + } +} + +gcc_parallel_test_enable 1 + -- cgit v1.1 From fa0b638fed271cbd26dcfba623e3fd51995470c8 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:05:08 +0000 Subject: [arm] Allow explicit periods to be escaped in The MULTILIB_REUSE mapping rules are built up using periods to represent the placement of '=' signs in the command line syntax. This presents a problem if the option contains an explicit period because that is translated unconditionally. The result is that it is not currently possible to write a reuse rule that would match the ARMv8-M mainline architecture: -march=armv8-m.main To fix this, this patch allows an explicit period to be escaped by writing \. and by then preserving the period into the generated multilib header. * genmultilib (multilib_reuse): Allow an explicit period to be escaped with a backslash. Remove the backslash after substituting unescaped periods. * doc/fragments.texi (MULTILIB_REUSE): Document it. From-SVN: r249298 --- gcc/ChangeLog | 7 +++++++ gcc/doc/fragments.texi | 10 ++++++---- gcc/genmultilib | 4 ++-- 3 files changed, 15 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 35ded57..d20d0aa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2017-06-16 Richard Earnshaw + * genmultilib (multilib_reuse): Allow an explicit period to be escaped + with a backslash. Remove the backslash after substituting unescaped + periods. + * doc/fragments.texi (MULTILIB_REUSE): Document it. + +2017-06-16 Richard Earnshaw + * config.gcc: (arm*-*-*): When building a-profile libraries, force the driver to pass through the default setting of -mfloat-abi. * common/config/arm/arm-common.c (arm_target_thumb_only): Return -marm diff --git a/gcc/doc/fragments.texi b/gcc/doc/fragments.texi index d68be7a..6aef553 100644 --- a/gcc/doc/fragments.texi +++ b/gcc/doc/fragments.texi @@ -160,10 +160,12 @@ A reuse rule is comprised of two parts connected by equality sign. The left part is the option set used to build multilib and the right part is the option set that will reuse this multilib. Both parts should only use options specified in @code{MULTILIB_OPTIONS} and the equality signs found in options -name should be replaced with periods. The order of options in the left part -matters and should be same with those specified in @code{MULTILIB_REQUIRED} or -aligned with the order in @code{MULTILIB_OPTIONS}. There is no such limitation -for options in the right part as we don't build multilib from them. +name should be replaced with periods. An explicit period in the rule can be +escaped by preceding it with a backslash. The order of options in the left +part matters and should be same with those specified in +@code{MULTILIB_REQUIRED} or aligned with the order in @code{MULTILIB_OPTIONS}. +There is no such limitation for options in the right part as we don't build +multilib from them. @code{MULTILIB_REUSE} is different from @code{MULTILIB_MATCHES} in that it sets up relations between two option sets rather than two options. Here is an diff --git a/gcc/genmultilib b/gcc/genmultilib index 2501f54..c8bcdf3 100644 --- a/gcc/genmultilib +++ b/gcc/genmultilib @@ -466,8 +466,8 @@ echo "static const char *const multilib_reuse_raw[] = {" for rrule in ${multilib_reuse}; do # The left part of the rule are the options we used to build multilib. # The right part of the rule are the options that can reuse this multilib. - combo=`echo ${rrule} | sed -e 's/=.*$//' -e 's/\./=/g'` - copts=`echo ${rrule} | sed -e 's/^.*=//' -e 's/\./=/g'` + combo=`echo ${rrule} | sed -e 's/=.*$//' -e 's/\([^\\]\)\./\1=/g' -e 's/\\\././g'` + copts=`echo ${rrule} | sed -e 's/^.*=//' -e 's/\([^\\]\)\./\1=/g' -e 's/\\\././g'` # The variable ${combinations} are the option combinations we will build # multilib from. If the combination in the left part of reuse rule isn't # in this variable, it means no multilib will be built for current reuse -- cgit v1.1 From c5742a17ac6d155f1f95b4685575b574eb09e8b4 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:05:26 +0000 Subject: [arm] Use -march=armv7-a+fp when testing hard-float Some tests explicitly test with -march=armv7-a and -mfloat-abi=hard. However, with the new -mfpu=auto code, this architectural specifiction lacks any floating-point capabilities. To rectify this, change the architecture to armv7-a+fp. gcc/testsuite: * gcc.dg/pr59418.c: On ARM, change architecture to armv7-a+fp. * gcc.target/arm/pr51915.c: Likewise. * gcc.target/arm/pr52006.c: Likewise. * gcc.target/arm/pr53187.c: Likewise. From-SVN: r249299 --- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.dg/pr59418.c | 2 +- gcc/testsuite/gcc.target/arm/pr51915.c | 2 +- gcc/testsuite/gcc.target/arm/pr52006.c | 2 +- gcc/testsuite/gcc.target/arm/pr53187.c | 2 +- 5 files changed, 11 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 13dffb3..b4408e6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,12 @@ 2017-06-16 Richard Earnshaw + * gcc.dg/pr59418.c: On ARM, change architecture to armv7-a+fp. + * gcc.target/arm/pr51915.c: Likewise. + * gcc.target/arm/pr52006.c: Likewise. + * gcc.target/arm/pr53187.c: Likewise. + +2017-06-16 Richard Earnshaw + * gcc.target/arm/multilibs.exp: New file. 2017-06-16 Martin Sebor diff --git a/gcc/testsuite/gcc.dg/pr59418.c b/gcc/testsuite/gcc.dg/pr59418.c index 12999aa..4b54ef2 100644 --- a/gcc/testsuite/gcc.dg/pr59418.c +++ b/gcc/testsuite/gcc.dg/pr59418.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-options "-Os -g" } */ -/* { dg-options "-march=armv7-a -mfloat-abi=hard -Os -g" { target { arm*-*-* && { ! arm_thumb1 } } } } */ +/* { dg-options "-march=armv7-a+fp -mfloat-abi=hard -Os -g" { target { arm*-*-* && { ! arm_thumb1 } } } } */ extern int printf (const char *__format, ...); double bar (const char *, int); diff --git a/gcc/testsuite/gcc.target/arm/pr51915.c b/gcc/testsuite/gcc.target/arm/pr51915.c index 144d522..f9ed305 100644 --- a/gcc/testsuite/gcc.target/arm/pr51915.c +++ b/gcc/testsuite/gcc.target/arm/pr51915.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ /* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ -/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2" } */ +/* { dg-options "-march=armv7-a+fp -mfloat-abi=hard -O2" } */ struct S { int s1; void *s2; }; struct T { struct S t1; unsigned long long t2; }; diff --git a/gcc/testsuite/gcc.target/arm/pr52006.c b/gcc/testsuite/gcc.target/arm/pr52006.c index c274449..dbbcfe0 100644 --- a/gcc/testsuite/gcc.target/arm/pr52006.c +++ b/gcc/testsuite/gcc.target/arm/pr52006.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "avoid conflicts with multilib flags" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ /* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ -/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2 -fPIC" } */ +/* { dg-options "-march=armv7-a+fp -mfloat-abi=hard -O2 -fPIC" } */ unsigned long a; static int b; diff --git a/gcc/testsuite/gcc.target/arm/pr53187.c b/gcc/testsuite/gcc.target/arm/pr53187.c index b40dbbb..5fbc52c 100644 --- a/gcc/testsuite/gcc.target/arm/pr53187.c +++ b/gcc/testsuite/gcc.target/arm/pr53187.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */ /* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ -/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2" } */ +/* { dg-options "-march=armv7-a+fp -mfloat-abi=hard -O2" } */ void bar (int); -- cgit v1.1 From 420938809a0ec729986e959a4c7bf8b1881f934a Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:05:35 +0000 Subject: [arm] Rewrite t-rmprofile multilib specification This is the R- & M-profile equivalent of the previous A-profile multilib rewrite. Additionally this patch adds some top-level rules to help find suitable multilibs for general cases when certain libraries are not built, or when building for legacy cores. gcc: * config/arm/t-aprofile (v7_a_nosimd_variants, v7_a_simd_variants) (v7ve_nosimd_variatns, v7ve_vfpv3_simd_variants) (v7ve_vfpv4_simd_variants, v8_a_nosimd_variants, v8_a_simd_variants) (v8_1_a_simd_variants, v8_2_a_simd_variants): Move to ... * config/arm/t-multilib: ... here. (MULTILIB_OPTIONS): Add armv7 and armv7+fp architectures. (MULTILIB_MATCHES): Use armv7 libraries for armv7-r. Also use for armv7-a and armv8*-a when A-profile libraries have not been built. * config/arm/t-rmprofile: Rewrite. gcc/testsuite: * gcc.target/arm/multilib.exp (rmprofile): New tests when rm-profile multilibs have been built. From-SVN: r249300 --- gcc/ChangeLog | 12 ++ gcc/config/arm/t-aprofile | 13 -- gcc/config/arm/t-multilib | 96 +++++++++- gcc/config/arm/t-rmprofile | 146 +++----------- gcc/testsuite/ChangeLog | 5 + gcc/testsuite/gcc.target/arm/multilib.exp | 304 ++++++++++++++++++++++++++++++ 6 files changed, 438 insertions(+), 138 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d20d0aa..730d7e9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2017-06-16 Richard Earnshaw + * config/arm/t-aprofile (v7_a_nosimd_variants, v7_a_simd_variants) + (v7ve_nosimd_variatns, v7ve_vfpv3_simd_variants) + (v7ve_vfpv4_simd_variants, v8_a_nosimd_variants, v8_a_simd_variants) + (v8_1_a_simd_variants, v8_2_a_simd_variants): Move to ... + * config/arm/t-multilib: ... here. + (MULTILIB_OPTIONS): Add armv7 and armv7+fp architectures. + (MULTILIB_MATCHES): Use armv7 libraries for armv7-r. Also use for + armv7-a and armv8*-a when A-profile libraries have not been built. + * config/arm/t-rmprofile: Rewrite. + +2017-06-16 Richard Earnshaw + * genmultilib (multilib_reuse): Allow an explicit period to be escaped with a backslash. Remove the backslash after substituting unescaped periods. diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index 2e3d4c8..0a36d05 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -24,19 +24,6 @@ # have their default values during the configure step. We enforce # this during the top-level configury. -# Variables used later in this file. - -v7_a_nosimd_variants := +fp +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +vfpv4-d16 +vfpv4 -v7_a_simd_variants := +simd +neon-fp16 +neon-vfpv4 -v7ve_nosimd_variants := +vfpv3-d16 +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +fp +vfpv4 -v7ve_vfpv3_simd_variants := +neon +neon-fp16 -v7ve_vfpv4_simd_variants := +simd -v8_a_nosimd_variants := +crc -v8_a_simd_variants := $(call all_feat_combs, simd crypto) -v8_1_a_simd_variants := $(call all_feat_combs, simd crypto) -v8_2_a_simd_variants := $(call all_feat_combs, simd fp16 crypto) - - # Arch and FPU variants to build libraries with MULTI_ARCH_OPTS_A = march=armv7-a/march=armv7-a+fp/march=armv7-a+simd/march=armv7ve+simd/march=armv8-a/march=armv8-a+simd diff --git a/gcc/config/arm/t-multilib b/gcc/config/arm/t-multilib index 77ce762..ec4b76d 100644 --- a/gcc/config/arm/t-multilib +++ b/gcc/config/arm/t-multilib @@ -57,6 +57,20 @@ all_feat_combs = +$(firstword $(1)) \ $(wordlist 2, $(words $(1)), $(1))), \ +$(firstword $(1))$(OPT) $(OPT)),) +# Variables used. +all_early_arch := armv5e armv5tej armv6 armv6j armv6k armv6z armv6kz \ + armv6zk armv6t2 iwmmxt iwmmxt2 +v7_a_nosimd_variants := +fp +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +vfpv4-d16 +vfpv4 +v7_a_simd_variants := +simd +neon-fp16 +neon-vfpv4 +v7ve_nosimd_variants := +vfpv3-d16 +vfpv3 +vfpv3-d16-fp16 +vfpv3-fp16 +fp +vfpv4 +v7ve_vfpv3_simd_variants := +neon +neon-fp16 +v7ve_vfpv4_simd_variants := +simd +v8_a_nosimd_variants := +crc +v8_a_simd_variants := $(call all_feat_combs, simd crypto) +v8_1_a_simd_variants := $(call all_feat_combs, simd crypto) +v8_2_a_simd_variants := $(call all_feat_combs, simd fp16 crypto) + + ifneq (,$(HAS_APROFILE)) include $(srcdir)/config/arm/t-aprofile endif @@ -66,14 +80,80 @@ endif SEP := $(and $(HAS_APROFILE),$(HAS_RMPROFILE),/) -MULTILIB_OPTIONS += marm/mthumb -MULTILIB_DIRNAMES += arm thumb +MULTILIB_OPTIONS += marm/mthumb +MULTILIB_DIRNAMES += arm thumb + +MULTILIB_OPTIONS += march=armv5te+fp/march=armv7/march=armv7+fp/$(MULTI_ARCH_OPTS_A)$(SEP)$(MULTI_ARCH_OPTS_RM) +MULTILIB_DIRNAMES += v5te v7 v7+fp $(MULTI_ARCH_DIRS_A) $(MULTI_ARCH_DIRS_RM) + +MULTILIB_OPTIONS += mfloat-abi=soft/mfloat-abi=softfp/mfloat-abi=hard +MULTILIB_DIRNAMES += nofp softfp hard + +MULTILIB_REQUIRED += mthumb/mfloat-abi=soft +MULTILIB_REQUIRED += marm/march=armv5te+fp/mfloat-abi=softfp +MULTILIB_REQUIRED += marm/march=armv5te+fp/mfloat-abi=hard + +MULTILIB_REQUIRED += mthumb/march=armv7/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv7+fp/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv7+fp/mfloat-abi=hard + +# Map v7-r down onto common v7 code. +MULTILIB_MATCHES += march?armv7=march?armv7-r +MULTILIB_MATCHES += march?armv7=march?armv7-r+idiv +MULTILIB_MATCHES += march?armv7+fp=march?armv7-r+fp +MULTILIB_MATCHES += march?armv7+fp=march?armv7-r+fp+idiv + +MULTILIB_MATCHES += $(foreach ARCH, $(all_early_arch), \ + march?armv5te+fp=march?$(ARCH)+fp) + +ifeq (,$(HAS_APROFILE)) +# Map all v7-a +MULTILIB_MATCHES += march?armv7=march?armv7-a +MULTILIB_MATCHES += $(foreach ARCH, $(v7_a_nosimd_variants) $(v7_a_simd_variants), \ + march?armv7+fp=march?armv7-a$(ARCH)) + +MULTILIB_MATCHES += march?armv7=march?armv7ve + +# ARMv7ve FP/SIMD variants: map down to v7+fp +MULTILIB_MATCHES += $(foreach ARCH, $(v7ve_nosimd_variants) $(v7ve_vfpv3_simd_variants) $(v7ve_vfpv4_simd_variants), \ + march?armv7+fp=march?armv7ve$(ARCH)) + +# ARMv8 +MULTILIB_MATCHES += march?armv7=march?armv8-a +MULTILIB_MATCHES += $(foreach ARCH, $(v8_a_nosimd_variants), \ + march?armv7=march?armv8-a$(ARCH)) + +# ARMv8 with SIMD +MULTILIB_MATCHES += march?armv7+fp=march?armv8-a+crc+simd \ + $(foreach ARCH, $(v8_a_simd_variants), \ + march?armv7+fp=march?armv8-a$(ARCH) \ + march?armv7+fp=march?armv8-a+crc$(ARCH)) + +# Baseline v8.1-a +MULTILIB_MATCHES += march?armv7=march?armv8.1-a + +# Map all v8.1-a SIMD variants +MULTILIB_MATCHES += $(foreach ARCH, $(v8_1_a_simd_variants), \ + march?armv7+fp=march?armv8.1-a$(ARCH)) + +# Baseline v8.2-a: map down to baseline v8-a +MULTILIB_MATCHES += march?armv7=march?armv8.2-a + +# Map all v8.2-a SIMD variants +MULTILIB_MATCHES += $(foreach ARCH, $(v8_2_a_simd_variants), \ + march?armv7+fp=march?armv8.2-a$(ARCH)) + +# Use Thumb libraries for everything. + +MULTILIB_REUSE += mthumb/march.armv7/mfloat-abi.soft=marm/march.armv7/mfloat-abi.soft -MULTILIB_OPTIONS += march=armv5te+fp/$(MULTI_ARCH_OPTS_A)$(SEP)$(MULTI_ARCH_OPTS_RM) -MULTILIB_DIRNAMES += v5te $(MULTI_ARCH_DIRS_A) $(MULTI_ARCH_DIRS_RM) +MULTILIB_REUSE += $(foreach ABI, hard softfp, \ + $(foreach ARCH, armv7+fp, \ + mthumb/march.$(ARCH)/mfloat-abi.$(ABI)=marm/march.$(ARCH)/mfloat-abi.$(ABI))) -MULTILIB_OPTIONS += mfloat-abi=soft/mfloat-abi=softfp/mfloat-abi=hard -MULTILIB_DIRNAMES += nofp softfp hard +# Softfp but no FP, use the soft-float libraries. +MULTILIB_REUSE += $(foreach MODE, arm thumb, \ + $(foreach ARCH, armv7, \ + mthumb/march.$(ARCH)/mfloat-abi.soft=m$(MODE)/march.$(ARCH)/mfloat-abi.softfp)) -MULTILIB_REQUIRED += mthumb/mfloat-abi=soft -MULTILIB_REQUIRED += marm/march=armv5te+fp/mfloat-abi=hard +endif # Not APROFILE. \ No newline at end of file diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile index ee869b7..1ad8eac 100644 --- a/gcc/config/arm/t-rmprofile +++ b/gcc/config/arm/t-rmprofile @@ -27,130 +27,42 @@ # Arch and FPU variants to build libraries with -MULTI_ARCH_OPTS_RM = march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7/march=armv8-m.base/march=armv8-m.main -MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7-ar v8-m.base v8-m.main +MULTI_ARCH_OPTS_RM = march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp +MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main v8-m.main+fp v8-m.main+dp -MULTI_FPU_OPTS_RM = mfpu=vfpv3-d16/mfpu=fpv4-sp-d16/mfpu=fpv5-sp-d16/mfpu=fpv5-d16 -MULTI_FPU_DIRS_RM = fpv3 fpv4-sp fpv5-sp fpv5 +# Base M-profile (no fp) +MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv7-m/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv8-m.base/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfloat-abi=soft +# ARMv7e-M with FP (single and double precision variants) +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=softfp -# Option combinations to build library with +# ARMv8-M with FP (single and double precision variants) +MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=softfp -# Default CPU/Arch -MULTILIB_REQUIRED += mthumb -MULTILIB_REQUIRED += mfloat-abi=hard -# ARMv6-M -MULTILIB_REQUIRED += mthumb/march=armv6s-m - -# ARMv8-M Baseline -MULTILIB_REQUIRED += mthumb/march=armv8-m.base - -# ARMv7-M -MULTILIB_REQUIRED += mthumb/march=armv7-m - -# ARMv7E-M -MULTILIB_REQUIRED += mthumb/march=armv7e-m -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv4-sp-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv7e-m/mfpu=fpv5-sp-d16/mfloat-abi=hard - -# ARMv8-M Mainline -MULTILIB_REQUIRED += mthumb/march=armv8-m.main -MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-sp-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv8-m.main/mfpu=fpv5-sp-d16/mfloat-abi=hard - -# ARMv7-R as well as ARMv7-A and ARMv8-A if aprofile was not specified -MULTILIB_REQUIRED += mthumb/march=armv7 -MULTILIB_REQUIRED += mthumb/march=armv7/mfpu=vfpv3-d16/mfloat-abi=softfp -MULTILIB_REQUIRED += mthumb/march=armv7/mfpu=vfpv3-d16/mfloat-abi=hard - - -# Matches - -# CPU Matches -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0 -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0.small-multiply -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0plus -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m0plus.small-multiply -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m1 -MULTILIB_MATCHES += march?armv6s-m=mcpu?cortex-m1.small-multiply -MULTILIB_MATCHES += march?armv7-m=mcpu?cortex-m3 -MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m4 -MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m7 -MULTILIB_MATCHES += march?armv8-m.base=mcpu?cortex-m23 -MULTILIB_MATCHES += march?armv8-m.main=mcpu?cortex-m33 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4f -MULTILIB_MATCHES += march?armv7=mcpu?cortex-r5 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-r7 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-r8 -MULTILIB_MATCHES += march?armv7=mcpu?marvell-pj4 -MULTILIB_MATCHES += march?armv7=mcpu?generic-armv7-a -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a9 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a5 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a7 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a15 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a12 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a17 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a15.cortex-a7 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a17.cortex-a7 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a32 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a35 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a53 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a57 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a57.cortex-a53 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a72 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a72.cortex-a53 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a35 -MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a53 -MULTILIB_MATCHES += march?armv7=mcpu?exynos-m1 -MULTILIB_MATCHES += march?armv7=mcpu?xgene1 # Arch Matches -MULTILIB_MATCHES += march?armv6s-m=march?armv6-m -MULTILIB_MATCHES += march?armv8-m.main=march?armv8-m.main+dsp -MULTILIB_MATCHES += march?armv7=march?armv7-r -ifeq (,$(HAS_APROFILE)) -MULTILIB_MATCHES += march?armv7=march?armv7-a -MULTILIB_MATCHES += march?armv7=march?armv7ve -MULTILIB_MATCHES += march?armv7=march?armv8-a -MULTILIB_MATCHES += march?armv7=march?armv8-a+crc -MULTILIB_MATCHES += march?armv7=march?armv8.1-a -MULTILIB_MATCHES += march?armv7=march?armv8.1-a+crc -MULTILIB_MATCHES += march?armv7=march?armv8.2-a -MULTILIB_MATCHES += march?armv7=march?armv8.2-a+fp16 -endif +MULTILIB_MATCHES += march?armv6s-m=march?armv6-m + +# Map all v8-m.main+dsp FP variants down the the variant without DSP. +MULTILIB_MATCHES += march?armv8-m.main=march?armv8-m.main+dsp \ + $(foreach FP, +fp +fp.dp, \ + march?armv8-m.main$(FP)=march?armv8-m.main+dsp$(FP)) -# FPU matches -ifeq (,$(HAS_APROFILE)) -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-d16-fp16 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon-fp16 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv4 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv4-d16 -MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?neon-vfpv4 -MULTILIB_MATCHES += mfpu?fpv5-d16=mfpu?fp-armv8 -MULTILIB_MATCHES += mfpu?fpv5-d16=mfpu?neon-fp-armv8 -MULTILIB_MATCHES += mfpu?fpv5-d16=mfpu?crypto-neon-fp-armv8 -endif +# For single-precision only fpv5, use the base fp libraries +MULTILIB_MATCHES += march?armv7e-m+fp=march?armv7e-m+fpv5 +# Softfp but no FP. Use the soft-float libraries. +MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv7e-m armv8-m\.base armv8-m\.main, \ + mthumb/march.$(ARCH)/mfloat-abi.soft=mthumb/march.$(ARCH)/mfloat-abi.softfp) -# We map all requests for ARMv7-R or ARMv7-A in ARM mode to Thumb mode and -# any FPU to VFPv3-d16 if possible. -MULTILIB_REUSE += mthumb/march.armv7=march.armv7 -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7/mfpu.fpv5-d16/mfloat-abi.hard -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.softfp -MULTILIB_REUSE += mthumb/march.armv7/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7/mfpu.fpv5-d16/mfloat-abi.hard diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b4408e6..53cd676 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Richard Earnshaw + * gcc.target/arm/multilib.exp (rmprofile): New tests when rm-profile + multilibs have been built. + +2017-06-16 Richard Earnshaw + * gcc.dg/pr59418.c: On ARM, change architecture to armv7-a+fp. * gcc.target/arm/pr51915.c: Likewise. * gcc.target/arm/pr52006.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp index bef5be8..8e9226a 100644 --- a/gcc/testsuite/gcc.target/arm/multilib.exp +++ b/gcc/testsuite/gcc.target/arm/multilib.exp @@ -376,6 +376,310 @@ if {[multilib_config "aprofile"] } { check_multi_dir $opts $dir } } +if {[multilib_config "rmprofile"] } { + foreach {opts dir} { + {-mcpu=cortex-m0 -mfpu=auto -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=auto -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=auto -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m0 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m0 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m0 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m0 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m0 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m23 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-mcpu=cortex-m4 -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m7 -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m4 -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m7 -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m33 -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m4 -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m7 -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m33 -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m7 -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m33 -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-mcpu=cortex-m4 -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-mcpu=cortex-m33 -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-mcpu=cortex-m0 -mfpu=auto -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=auto -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=auto -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m7 -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-mcpu=cortex-m23 -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m0 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m7 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m23 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m0 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m7 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m23 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m0 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m7 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m23 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m0 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m23 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-mcpu=cortex-m0 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m1 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-mcpu=cortex-m3 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-mcpu=cortex-m4 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-mcpu=cortex-m23 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-mcpu=cortex-m33 -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv6-m -mfpu=auto -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=auto -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=auto -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv6-m -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv6-m -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv6-m -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv6-m -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv6-m -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv7e-m+fp.dp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v7e-m/nofp" + {-march=armv8-m.main+fp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-d16 -mfloat-abi=soft} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv7e-m+fp.dp -mfpu=auto -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv8-m.main -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv7e-m+fp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv8-m.main -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv7e-m+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv8-m.main -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv7e-m+fp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv7e-m+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv7e-m+fp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+fp/hard" + {-march=armv7e-m+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+fp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv7e-m+fp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv7e-m+fp.dp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v7e-m+dp/hard" + {-march=armv8-m.main+fp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-d16 -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" + {-march=armv6-m -mfpu=auto -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=auto -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m/nofp" + {-march=armv8-m.base -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp" + {-march=armv7e-m+fp -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv7e-m+fp.dp -mfpu=auto -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv6-m -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv8-m.base -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv7e-m+fp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv6-m -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv8-m.base -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv7e-m+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv7e-m+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=vfpv3xd-fp16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv6-m -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv8-m.base -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv7e-m+fp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv7e-m+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv4-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv6-m -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv8-m.base -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv7e-m+fp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+fp/softfp" + {-march=armv7e-m+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+fp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-sp-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv6-m -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v6-m/nofp" + {-march=armv7-m -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7-m/nofp" + {-march=armv7e-m -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.base -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.base/nofp" + {-march=armv8-m.main -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv7e-m+fp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv7e-m+fp.dp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v7e-m+dp/softfp" + {-march=armv8-m.main+fp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp.dp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp+dsp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + {-march=armv8-m.main+fp.dp+dsp -mfpu=fpv5-d16 -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" + } { + check_multi_dir $opts $dir + } +} gcc_parallel_test_enable 1 -- cgit v1.1 From d59ee314a89863fa06f91eb59b2211585f3ebac9 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:05:46 +0000 Subject: [arm] Update t-rtems for new option framework [This patch has only been fairly lightly tested (I've built a compiler with all the relevant multilibs and smoke-tested a few combinations to check that the tools still produce a sensible object file).] This patch updates the RTEMS build to use the new option framework. It tries as far as possible to keep the existing supported options, but there are two necessary changes and one cleanup. I've also restructed the file slightly to make it slightly easier (IMO) to understand. Necessary changes: 1: ARMv4t does not support a hard-float ABI, the earliest supported architecture with floating-point support is ARMv5te, so I've rebased the original fpu/hard libraries to that revision of the architecture. 2: Similarly, the earliest version of the -m profile to support hardware floating-point is armv7e-m (not armv7-m), so the base architecture for m-profile with FP has been correspondingly updated. Clean-up: 1: For greater consistency I've changed the -mcpu=cortex-m7/-mfpu=fpv5-d16/-mhard-float to -march=armv7e-m+fp.dp/-mhard-float. The built-in -mcpu rewrite rules take care of mapping the existing option sets onto the architecture string to ensure compatibility. Since the existing rule set does not contain any MULTILIB_REUSE rules, I have not added any here this time around, but it would be worth the maintainers of this file considering whether adding some rules would make their toolchain more friendly to users. Finally, I've added lines to reset all the multilib variables at the head of the file. I found during testing that some definitions from t-arm-elf were leaking through and causing unexpected behviour. * config/arm/t-rtems: Rewrite for new option framework. From-SVN: r249301 --- gcc/ChangeLog | 4 ++++ gcc/config/arm/t-rtems | 49 ++++++++++++++++++++++++++++++++----------------- 2 files changed, 36 insertions(+), 17 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 730d7e9..f603df5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-06-16 Richard Earnshaw + * config/arm/t-rtems: Rewrite for new option framework. + +2017-06-16 Richard Earnshaw + * config/arm/t-aprofile (v7_a_nosimd_variants, v7_a_simd_variants) (v7ve_nosimd_variatns, v7ve_vfpv3_simd_variants) (v7ve_vfpv4_simd_variants, v8_a_nosimd_variants, v8_a_simd_variants) diff --git a/gcc/config/arm/t-rtems b/gcc/config/arm/t-rtems index 026a589..c073786 100644 --- a/gcc/config/arm/t-rtems +++ b/gcc/config/arm/t-rtems @@ -1,22 +1,37 @@ # Custom RTEMS multilibs for ARM -MULTILIB_OPTIONS = mbig-endian mthumb march=armv6-m/march=armv7-a/march=armv7-r/march=armv7-m/mcpu=cortex-m7 mfpu=neon/mfpu=vfp/mfpu=vfpv3-d16/mfpu=fpv4-sp-d16/mfpu=fpv5-d16 mfloat-abi=hard -MULTILIB_DIRNAMES = eb thumb armv6-m armv7-a armv7-r armv7-m cortex-m7 neon vfp vfpv3-d16 fpv4-sp-d16 fpv5-d16 hard +# Reset all MULTILIB variables + +MULTILIB_OPTIONS = +MULTILIB_DIRNAMES = +MULTILIB_EXCEPTIONS = +MULTILIB_REUSE = +MULTILIB_MATCHES = +MULTILIB_REQUIRED = # Enumeration of multilibs -MULTILIB_EXCEPTIONS = - -MULTILIB_REQUIRED = -MULTILIB_REQUIRED += mbig-endian/mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mbig-endian/mthumb/march=armv7-r -MULTILIB_REQUIRED += mfpu=vfp/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv6-m -MULTILIB_REQUIRED += mthumb/march=armv7-a/mfpu=neon/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7-a -MULTILIB_REQUIRED += mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7-r -MULTILIB_REQUIRED += mthumb/march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/mcpu=cortex-m7/mfpu=fpv5-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7-m -MULTILIB_REQUIRED += mthumb +MULTILIB_OPTIONS += mbig-endian +MULTILIB_DIRNAMES += eb + +MULTILIB_OPTIONS += mthumb +MULTILIB_DIRNAMES += thumb + +MULTILIB_OPTIONS += march=armv5te+fp/march=armv6-m/march=armv7-a/march=armv7-a+simd/march=armv7-r/march=armv7-r+fp/march=armv7-m/march=armv7e-m+fp/march=armv7e-m+fp.dp +MULTILIB_DIRNAMES += armv5te+fp armv6-m armv7-a armv7-a+simd armv7-r armv7-r+fp armv7-m armv7e-m+fp armv7e-m+fp.dp + +MULTILIB_OPTIONS += mfloat-abi=hard +MULTILIB_DIRNAMES += hard + +MULTILIB_REQUIRED += mbig-endian/mthumb/march=armv7-r+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mbig-endian/mthumb/march=armv7-r +MULTILIB_REQUIRED += march=armv5te+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv6-m +MULTILIB_REQUIRED += mthumb/march=armv7-a+simd/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7-a +MULTILIB_REQUIRED += mthumb/march=armv7-r+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7-r +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7-m +MULTILIB_REQUIRED += mthumb -- cgit v1.1 From e16743376816780960a4dc7aee7a973c6ac0a64c Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:05:55 +0000 Subject: [arm] Ensure all multilib variables are reset No real change, but for consistency reset all multilib related variables. * config/arm/t-linux-eabi (MULTILIB_EXCEPTIONS): Set to empty. (MULTILIB_RESUE): Likewise. (MULTILIB_MATCHES): Likewise. (MULTLIB_REQUIRED): Likewise. From-SVN: r249302 --- gcc/ChangeLog | 7 +++++++ gcc/config/arm/t-linux-eabi | 4 ++++ 2 files changed, 11 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f603df5..810cd75 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2017-06-16 Richard Earnshaw + * config/arm/t-linux-eabi (MULTILIB_EXCEPTIONS): Set to empty. + (MULTILIB_RESUE): Likewise. + (MULTILIB_MATCHES): Likewise. + (MULTLIB_REQUIRED): Likewise. + +2017-06-16 Richard Earnshaw + * config/arm/t-rtems: Rewrite for new option framework. 2017-06-16 Richard Earnshaw diff --git a/gcc/config/arm/t-linux-eabi b/gcc/config/arm/t-linux-eabi index 117c0eb..c11af7a 100644 --- a/gcc/config/arm/t-linux-eabi +++ b/gcc/config/arm/t-linux-eabi @@ -22,6 +22,10 @@ # MULTILIB_DEFAULTS in linux-elf.h. MULTILIB_OPTIONS = MULTILIB_DIRNAMES = +MULTILIB_EXCEPTIONS = +MULTILIB_REUSE = +MULTILIB_MATCHES = +MULTILIB_REQUIRED = #MULTILIB_OPTIONS += mcpu=fa606te/mcpu=fa626te/mcpu=fmp626/mcpu=fa726te #MULTILIB_DIRNAMES += fa606te fa626te fmp626 fa726te -- cgit v1.1 From 99d6bcf7ae8980e04dabe8b86df9c70ad04dc5ba Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:06:01 +0000 Subject: [arm] reset all multilib variables NB. This configuration does not build in GCC-7 and doesn't build now either. This patch resets a couple of multlib variables which previously were not cleared. It almost certainly needs further work to make it use the new option framework correctly, but since the library configurations are already clearly wrong, it's not clear what the changes need to be. In particular it tries to build a hard-float library for ARM7TDMI in both ARM and thumb modes, but ARMv4t does not support any floating-point instructions; furthermore, GCC has never supported a hard-float thumb1 library. * config/arm/t-phoenix (MULTILIB_REUSE): Clear variable. (MULTILIB_REQUIRED): Likewise. From-SVN: r249303 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/t-phoenix | 20 +++++++++++--------- 2 files changed, 16 insertions(+), 9 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 810cd75..fce3642 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Richard Earnshaw + * config/arm/t-phoenix (MULTILIB_REUSE): Clear variable. + (MULTILIB_REQUIRED): Likewise. + +2017-06-16 Richard Earnshaw + * config/arm/t-linux-eabi (MULTILIB_EXCEPTIONS): Set to empty. (MULTILIB_RESUE): Likewise. (MULTILIB_MATCHES): Likewise. diff --git a/gcc/config/arm/t-phoenix b/gcc/config/arm/t-phoenix index dea5257..4930ba8 100644 --- a/gcc/config/arm/t-phoenix +++ b/gcc/config/arm/t-phoenix @@ -16,14 +16,16 @@ # along with GCC; see the file COPYING3. If not see # . -MULTILIB_OPTIONS = marm/mthumb -MULTILIB_DIRNAMES = arm thumb -MULTILIB_EXCEPTIONS = -MULTILIB_MATCHES = +MULTILIB_OPTIONS = marm/mthumb +MULTILIB_DIRNAMES = arm thumb +MULTILIB_EXCEPTIONS = +MULTILIB_MATCHES = +MULTILIB_REUSE = +MULTILIB_REQUIRED = -MULTILIB_OPTIONS += mfloat-abi=hard -MULTILIB_DIRNAMES += fpu -MULTILIB_MATCHES += mfloat-abi?hard=mhard-float +MULTILIB_OPTIONS += mfloat-abi=hard +MULTILIB_DIRNAMES += fpu +MULTILIB_MATCHES += mfloat-abi?hard=mhard-float -MULTILIB_OPTIONS += mno-thumb-interwork/mthumb-interwork -MULTILIB_DIRNAMES += normal interwork +MULTILIB_OPTIONS += mno-thumb-interwork/mthumb-interwork +MULTILIB_DIRNAMES += normal interwork -- cgit v1.1 From e61a3cdd259de13884da900ecb5440a9cc466665 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:06:07 +0000 Subject: [arm] Rework multlib builds for symbianelf Symbianelf used to build multilib for armv5t with softfp, but that architecture doesn't really support floating point instructions. This patch reworks the multilib configuration to use armv5te as the base when building for floating point. I'm not sure just how useful the symbian port is these days, so this has only been very lightly tested (checks that libgcc builds for all multilib variants). Perhaps we should consider deprecating this config? * config/arm/t-symbian: Rewrite for new option infrastructure. From-SVN: r249304 --- gcc/ChangeLog | 4 ++++ gcc/config/arm/t-symbian | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 36 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fce3642..6f73286 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-06-16 Richard Earnshaw + * config/arm/t-symbian: Rewrite for new option infrastructure. + +2017-06-16 Richard Earnshaw + * config/arm/t-phoenix (MULTILIB_REUSE): Clear variable. (MULTILIB_REQUIRED): Likewise. diff --git a/gcc/config/arm/t-symbian b/gcc/config/arm/t-symbian index bc10b58..003651e 100644 --- a/gcc/config/arm/t-symbian +++ b/gcc/config/arm/t-symbian @@ -22,5 +22,35 @@ EXTRA_HEADERS += $(srcdir)/ginclude/unwind-arm-common.h # multilib for those without -- using the soft-float ABI in both # cases. Symbian OS object should be compiled with interworking # enabled, so there are no separate thumb-mode libraries. -MULTILIB_OPTIONS = mfloat-abi=softfp -MULTILIB_DIRNAMES = softfp + +# Reset all the multilib variables. +MULTILIB_OPTIONS = +MULTILIB_DIRNAMES = +MULTILIB_EXCEPTIONS = +MULTILIB_REUSE = +MULTILIB_MATCHES = +MULTILIB_REQUIRED = + +MULTILIB_OPTIONS += march=armv5te+fp +MULTILIB_DIRNAMES += v5te + +MULTILIB_OPTIONS += mfloat-abi=softfp +MULTILIB_DIRNAMES += softfp + +MULTLILIB_REQUIRED += march=armv5te+fp/mfloat-abi=softfp + +MULTILIB_MATCHES += $(foreach ARCH, $(all_early_arch), \ + march?armv5te+fp=march?$(ARCH)+fp) + +MULTILIB_MATCHES += $(foreach FPARCH, $(v7a_fps), \ + march?armv5te+fp=march?armv7-a+$(FPARCH)) + +MULTILIB_MATCHES += $(foreach FPARCH, $(v7ve_fps), \ + march?armv5te+fp=march?armv7ve+$(FPARCH)) + +MULTILIB_MATCHES += $(foreach ARCH, $(all_v7_a_r), \ + march?armv5te+fp=march?$(ARCH)+fp) + +MULTILIB_MATCHES += $(foreach ARCH, $(all_v8_archs), \ + $(foreach FPARCH, $(v8_fps), \ + march?armv5te+fp=march?$(ARCH)+$(FPARCH))) -- cgit v1.1 From be5c4e06871958f2cbd7f091b6b123fb5ee94151 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:06:14 +0000 Subject: [arm] Rework multilib support It looks like the fuchsia port relied on inheriting the multilib rules from the bare-metal port (the t-arm-elf makefile fragment), but that has now been rewritten on the assuption that the base architecture is ARMv4t; fuchsia has a base architecture of ARMv7-a. To account for this, I've cloned the original t-arm-elf rules into a new makefile fragment t-fuchsia and arranged for that to be used when targetting this system. * config/arm/t-fuchsia: New file. * config.gcc (arm*-*-fuchsia*): Use it. From-SVN: r249305 --- gcc/ChangeLog | 5 +++++ gcc/config.gcc | 2 +- gcc/config/arm/t-fuchsia | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 gcc/config/arm/t-fuchsia (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6f73286..3424581 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Richard Earnshaw + * config/arm/t-fuchsia: New file. + * config.gcc (arm*-*-fuchsia*): Use it. + +2017-06-16 Richard Earnshaw + * config/arm/t-symbian: Rewrite for new option infrastructure. 2017-06-16 Richard Earnshaw diff --git a/gcc/config.gcc b/gcc/config.gcc index 94a281d..0518cb7 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1160,7 +1160,7 @@ arm*-*-eabi* | arm*-*-symbianelf* | arm*-*-rtems* | arm*-*-fuchsia*) ;; arm*-*-fuchsia*) tm_file="${tm_file} fuchsia.h arm/fuchsia-elf.h glibc-stdint.h" - tmake_file="${tmake_file} arm/t-bpabi" + tmake_file="${tmake_file} arm/t-bpabi arm/t-fuchsia" target_cpu_cname="generic-armv7-a" ;; arm*-*-rtems*) diff --git a/gcc/config/arm/t-fuchsia b/gcc/config/arm/t-fuchsia new file mode 100644 index 0000000..18fc518 --- /dev/null +++ b/gcc/config/arm/t-fuchsia @@ -0,0 +1,33 @@ +# Copyright (C) 2017 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# Reset all the multilib variables. +MULTILIB_OPTIONS = +MULTILIB_DIRNAMES = +MULTILIB_EXCEPTIONS = +MULTILIB_REUSE = +MULTILIB_MATCHES = +MULTILIB_REQUIRED = + +# For compatibility with gcc-7 we build the following multilibs +MULTILIB_OPTIONS += marm/mthumb +MULTILIB_DIRNAMES += arm thumb + +MULTILIB_OPTIONS += mfloat-abi=hard +MULTILIB_DIRNAMES += fpu +MULTILIB_EXCEPTIONS += *mthumb/*mfloat-abi=hard* -- cgit v1.1 From ffc126904bb2352b55e987a4a8f0c614a84afd79 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:06:36 +0000 Subject: [arm] Add a few missing architecture extension options. Reviewing the list of options for the purposes of writing the documentation revealed that a small number of options were missing. Mostly these are aliases for existing options, but in a couple of cases we lacked the ability to disable certain other options. * config/arm/arm-cpus.in (armv7): Add extension +nofp. (armv7-r): Add aliases vfpv3xd and vfpv3-d16. (armv8-m.main): Add option +nodsp. * config/arm/arm-cpu-cdata.h: Regenerated. From-SVN: r249306 --- gcc/ChangeLog | 7 +++++++ gcc/config/arm/arm-cpu-cdata.h | 24 ++++++++++++++++++++++++ gcc/config/arm/arm-cpus.in | 6 ++++++ 3 files changed, 37 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3424581..88b1734 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2017-06-16 Richard Earnshaw + * config/arm/arm-cpus.in (armv7): Add extension +nofp. + (armv7-r): Add aliases vfpv3xd and vfpv3-d16. + (armv8-m.main): Add option +nodsp. + * config/arm/arm-cpu-cdata.h: Regenerated. + +2017-06-16 Richard Earnshaw + * config/arm/t-fuchsia: New file. * config.gcc (arm*-*-fuchsia*): Use it. diff --git a/gcc/config/arm/arm-cpu-cdata.h b/gcc/config/arm/arm-cpu-cdata.h index 5034dbb..8406fa0 100644 --- a/gcc/config/arm/arm-cpu-cdata.h +++ b/gcc/config/arm/arm-cpu-cdata.h @@ -1814,6 +1814,10 @@ static const struct cpu_arch_extension arch_opttab_armv7[] = { { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, { + "nofp", true, false, + { ISA_ALL_FP, isa_nobit } + }, + { "vfpv3-d16", false, true, { ISA_VFPv3,ISA_FP_DBL, isa_nobit } }, @@ -1961,6 +1965,14 @@ static const struct cpu_arch_extension arch_opttab_armv7_r[] = { "noidiv", true, false, { isa_bit_adiv, isa_nobit } }, + { + "vfpv3xd", false, true, + { ISA_VFPv3, isa_nobit } + }, + { + "vfpv3-d16", false, true, + { ISA_VFPv3,ISA_FP_DBL, isa_nobit } + }, { NULL, false, false, {isa_nobit}} }; @@ -2025,6 +2037,14 @@ static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, + { + "vfpv4-sp-d16", false, true, + { ISA_VFPv4, isa_nobit } + }, + { + "fpv5-d16", false, true, + { ISA_FPv5,ISA_FP_DBL, isa_nobit } + }, { NULL, false, false, {isa_nobit}} }; @@ -2069,6 +2089,10 @@ static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { "nofp", true, false, { ISA_ALL_FP, isa_nobit } }, + { + "nodsp", true, false, + { isa_bit_ARMv7em, isa_nobit } + }, { NULL, false, false, {isa_nobit}} }; diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 14e49ec..43f4ebc 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -228,6 +228,7 @@ begin arch armv7 # fp => VFPv3-d16 (only useful for the A+R profile subset). option fp add VFPv3 FP_DBL optalias vfpv3-d16 fp + option nofp remove ALL_FP end arch armv7 begin arch armv7-a @@ -281,7 +282,9 @@ begin arch armv7-r isa ARMv7r # ARMv7-r uses VFPv3-d16 option fp.sp add VFPv3 + optalias vfpv3xd fp.sp option fp add VFPv3 FP_DBL + optalias vfpv3-d16 fp option idiv add bit_adiv option nofp remove ALL_FP option noidiv remove bit_adiv @@ -303,8 +306,10 @@ begin arch armv7e-m isa ARMv7em # fp => VFPv4-sp-d16; fpv5 => FPv5-sp-d16; fp.dp => FPv5-d16 option fp add VFPv4 + optalias vfpv4-sp-d16 fp option fpv5 add FPv5 option fp.dp add FPv5 FP_DBL + optalias fpv5-d16 fp.dp option nofp remove ALL_FP end arch armv7e-m @@ -359,6 +364,7 @@ begin arch armv8-m.main option fp add FPv5 option fp.dp add FPv5 FP_DBL option nofp remove ALL_FP + option nodsp remove bit_ARMv7em end arch armv8-m.main begin arch iwmmxt -- cgit v1.1 From 6d2f99aae150b9458e2cef9b85a77b9814995b45 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:06:51 +0000 Subject: [arm][doc] Document new -march= syntax. This adds documentation for the new extension options to -march= on ARM. I tried a number of different ways of formatting the information, but this seems the best, given what can be achieved in texinfo format. * doc/invoke.texi (ARM Options, -march=): Document new syntax and permitted extensions. From-SVN: r249307 --- gcc/ChangeLog | 5 + gcc/doc/invoke.texi | 303 ++++++++++++++++++++++++++++++++++++++++++++++------ 2 files changed, 278 insertions(+), 30 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 88b1734..38b28ab 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Richard Earnshaw + * doc/invoke.texi (ARM Options, -march=): Document new syntax and + permitted extensions. + +2017-06-16 Richard Earnshaw + * config/arm/arm-cpus.in (armv7): Add extension +nofp. (armv7-r): Add aliases vfpv3xd and vfpv3-d16. (armv8-m.main): Add option +nodsp. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d7027aa..3567691 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15158,48 +15158,291 @@ the default for all standard configurations. Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor. -@item -march=@var{name} +@item -march=@var{name@r{[}+extension@dots{}@r{]}} @opindex march This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. This option can be used in conjunction with or instead -of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, -@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t}, -@samp{armv5}, @samp{armv5e}, @samp{armv5t}, @samp{armv5te}, -@samp{armv6}, @samp{armv6-m}, @samp{armv6j}, @samp{armv6k}, -@samp{armv6kz}, @samp{armv6s-m}, -@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, -@samp{armv7}, @samp{armv7-a}, @samp{armv7-m}, @samp{armv7-r}, @samp{armv7e-m}, -@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a}, -@samp{armv8.1-a+crc}, @samp{armv8-m.base}, @samp{armv8-m.main}, -@samp{armv8-m.main+dsp}, @samp{iwmmxt}, @samp{iwmmxt2}. +of the @option{-mcpu=} option. + +Permissible names are: +@samp{armv4t}, +@samp{armv5t}, @samp{armv5te}, +@samp{armv6}, @samp{armv6j}, @samp{armv6k}, @samp{armv6kz}, @samp{armv6t2}, +@samp{armv6z}, @samp{armv6zk}, +@samp{armv7}, @samp{armv7-a}, @samp{armv7ve}, +@samp{armv8-a}, @samp{armv8.1-a}, @samp{armv8.2-a}, +@samp{armv7-r}, +@samp{armv6-m}, @samp{armv6s-m}, +@samp{armv7-m}, @samp{armv7e-m}, +@samp{armv8-m.base}, @samp{armv8-m.main}, +@samp{iwmmxt} and @samp{iwmmxt2}. + +Additionally, the following architectures, which lack support for the +Thumb exection state, are recognized but support is deprecated: +@samp{armv2}, @samp{armv2a}, @samp{armv3}, @samp{armv3m}, +@samp{armv4}, @samp{armv5} and @samp{armv5e}. + +Many of the architectures support extensions. These can be added by +appending @samp{+@var{extension}} to the architecture name. Extension +options are processed in order and capabilities accumulate. An extension +will also enable any necessary base extensions +upon which it depends. For example, the @samp{+crypto} extension +will always enable the @samp{+simd} extension. The exception to the +additive construction is for extensions that are prefixed with +@samp{+no@dots{}}: these extensions disable the specified option and +any other extensions that may depend on the presence of that +extension. -Architecture revisions older than @samp{armv4t} are deprecated. +For example, @samp{-march=armv7-a+simd+nofp+vfpv4} is equivalent to +writing @samp{-march=armv7-a+vfpv4} since the @samp{+simd} option is +entirely disabled by the @samp{+nofp} option that follows it. -@option{-march=armv6s-m} is the @samp{armv6-m} architecture with support for -the (now mandatory) SVC instruction. +Most extension names are generically named, but have an effect that is +dependent upon the architecture to which it is applied. For example, +the @samp{+simd} option can be applied to both @samp{armv7-a} and +@samp{armv8-a} architectures, but will enable the original ARMv7 +Advanced SIMD (Neon) extensions for @samp{armv7-a} and the ARMv8-a +variant for @samp{armv8-a}. -@option{-march=armv6zk} is an alias for @samp{armv6kz}, existing for backwards -compatibility. +The table below lists the supported extensions for each architecture. +Architectures not mentioned do not support any extensions. -@option{-march=armv7ve} is the @samp{armv7-a} architecture with virtualization -extensions. +@table @samp +@item armv5e +@itemx armv5te +@itemx armv6 +@itemx armv6j +@itemx armv6k +@itemx armv6kz +@itemx armv6t2 +@itemx armv6z +@itemx armv6zk +@table @samp +@item +fp +The VFPv2 floating-point instructions. The extension @samp{+vfpv2} can be +used as an alias for this extension. -@option{-march=armv8-a+crc} enables code generation for the ARMv8-A -architecture together with the optional CRC32 extensions. +@item +nofp +Disable the floating-point instructions. +@end table -@option{-march=armv8.1-a} enables compiler support for the ARMv8.1-A -architecture. This also enables the features provided by -@option{-march=armv8-a+crc}. +@item armv7 +The common subset of the ARMv7-A, ARMv7-R and ARMv7-M architectures. +@table @samp +@item +fp +The VFPv3 floating-point instructions, with 16 double-precision +registers. The extension @samp{+vfpv3-d16} can be used as an alias +for this extension. Note that floating-point is not supported by the +base ARMv7-M architecture, but is compatible with both the ARMv7-A and +ARMv7-R architectures. + +@item +nofp +Disable the floating-point instructions. +@end table -@option{-march=armv8.2-a} enables compiler support for the ARMv8.2-A -architecture. This also enables the features provided by -@option{-march=armv8.1-a}. +@item armv7-a +@table @samp +@item +fp +The VFPv3 floating-point instructions, with 16 double-precision +registers. The extension @samp{+vfpv3-d16} can be used as an alias +for this extension. + +@item +simd +The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. +The extensions @samp{+neon} and @samp{+neon-vfpv3} can be used as aliases +for this extension. + +@item +vfpv3 +The VFPv3 floating-point instructions, with 32 double-precision +registers. + +@item +vfpv3-d16-fp16 +The VFPv3 floating-point instructions, with 16 double-precision +registers and the half-precision floating-point conversion operations. + +@item +vfpv3-fp16 +The VFPv3 floating-point instructions, with 32 double-precision +registers and the half-precision floating-point conversion operations. + +@item +vfpv4-d16 +The VFPv4 floating-point instructions, with 16 double-precision +registers. + +@item +vfpv4 +The VFPv4 floating-point instructions, with 32 double-precision +registers. + +@item +neon-fp16 +The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with +the half-precision floating-point conversion operations. + +@item +neon-vfpv4 +The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. + +@item +nosimd +Disable the Advanced SIMD instructions (does not disable floating point). + +@item +nofp +Disable the floating-point and Advanced SIMD instructions. +@end table + +@item armv7ve +The extended version of the ARMv7-A architecture with support for +virtualization. +@table @samp +@item +fp +The VFPv4 floating-point instructions, with 16 double-precision registers. +The extension @samp{+vfpv4-d16} can be used as an alias for this extension. + +@item +simd +The Advanced SIMD (Neon) v2 and the VFPv4 floating-point instructions. The +extension @samp{+neon-vfpv4} can be used as an alias for this extension. + +@item +vfpv3-d16 +The VFPv3 floating-point instructions, with 16 double-precision +registers. + +@item +vfpv3 +The VFPv3 floating-point instructions, with 32 double-precision +registers. + +@item +vfpv3-d16-fp16 +The VFPv3 floating-point instructions, with 16 double-precision +registers and the half-precision floating-point conversion operations. + +@item +vfpv3-fp16 +The VFPv3 floating-point instructions, with 32 double-precision +registers and the half-precision floating-point conversion operations. + +@item +vfpv4-d16 +The VFPv4 floating-point instructions, with 16 double-precision +registers. + +@item +vfpv4 +The VFPv4 floating-point instructions, with 32 double-precision +registers. + +@item +neon +The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions. +The extension @samp{+neon-vfpv3} can be used as an alias for this extension. + +@item +neon-fp16 +The Advanced SIMD (Neon) v1 and the VFPv3 floating-point instructions, with +the half-precision floating-point conversion operations. + +@item +nosimd +Disable the Advanced SIMD instructions (does not disable floating point). + +@item +nofp +Disable the floating-point and Advanced SIMD instructions. +@end table -@option{-march=armv8.2-a+fp16} enables compiler support for the -ARMv8.2-A architecture with the optional FP16 instructions extension. -This also enables the features provided by @option{-march=armv8.1-a} -and implies @option{-mfp16-format=ieee}. +@item armv8-a +@table @samp +@item +crc +The Cyclic Redundancy Check (CRC) instructions. +@item +simd +The ARMv8 Advanced SIMD and floating-point instructions. +@item +crypto +The cryptographic instructions. +@item +nocrypto +Disable the cryptographic isntructions. +@item +nofp +Disable the floating-point, Advanced SIMD and cryptographic instructions. +@end table + +@item armv8.1-a +@table @samp +@item +simd +The ARMv8.1 Advanced SIMD and floating-point instructions. + +@item +crypto +The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions. + +@item +nocrypto +Disable the cryptographic isntructions. + +@item +nofp +Disable the floating-point, Advanced SIMD and cryptographic instructions. +@end table + +@item armv8.2-a +@table @samp +@item +fp16 +The half-precision floating-point data processing instructions. +This also enables the Advanced SIMD and floating-point instructions. + +@item +simd +The ARMv8.1 Advanced SIMD and floating-point instructions. + +@item +crypto +The cryptographic instructions. This also enables the Advanced SIMD and +floating-point instructions. + +@item +nocrypto +Disable the cryptographic extension. + +@item +nofp +Disable the floating-point, Advanced SIMD and cryptographic instructions. +@end table + +@item armv7-r +@table @samp +@item +fp.sp +The single-precision VFPv3 floating-point instructions. The extension +@samp{+vfpv3xd} can be used as an alias for this extension. + +@item +fp +The VFPv3 floating-point instructions with 16 double-precision registers. +The extension +vfpv3-d16 can be used as an alias for this extension. + +@item +nofp +Disable the floating-point extension. + +@item +idiv +The ARM-state integer division instructions. + +@item +noidiv +Disable the ARM-state integer division extension. +@end table + +@item armv7e-m +@table @samp +@item +fp +The single-precision VFPv4 floating-point instructions. + +@item +fpv5 +The single-precision FPv5 floating-point instructions. + +@item +fp.dp +The single- and double-precision FPv5 floating-point instructions. + +@item +nofp +Disable the floating-point extensions. +@end table + +@item armv8-m.main +@table @samp +@item +dsp +The DSP instructions. + +@item +nodsp +Disable the DSP extension. + +@item +fp +The single-precision floating-point instructions. + +@item +fp.dp +The single- and double-precision floating-point instructions. + +@item +nofp +Disable the floating-point extension. + +@end table + +@end table @option{-march=native} causes the compiler to auto-detect the architecture of the build computer. At present, this feature is only supported on -- cgit v1.1 From f54133eaab45a20811d14e816ade220fe336a1cf Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:07:03 +0000 Subject: [arm][doc] Document changes to -mcpu, -mtune and -mfpu. This patch adds the remainder of the main documentation changes. It adds the changes for -mcpu, -mtune and -mfpu. I've chosen to document the extension options under -mcpu rather than under -mtune because, while they are permitted with -mtune, they do not affect the behaviour of the tuning done by the compiler. I've also inverted the sense of the table (making the primary index the extension name and then listing the CPU names to which it applies. This is because the extensions are much more orthoganal in meaning here and having a primary entry via the CPU name would lead to enormous duplication. Finally, it adds the relevant changes to -mfpu. I haven't stated yet that any setting of -mfpu other than 'auto' is deprecated, but that is certainly the long-term goal of this patch series. * doc/invoke.texi (ARM Options, -mcpu): Document supported extension options. (ARM Options, -mtune): Document that this accepts the same extension options as -mcpu. (ARM Options, -mfpu): Document addition of -mfpu=auto. From-SVN: r249308 --- gcc/ChangeLog | 8 ++++++ gcc/doc/invoke.texi | 70 +++++++++++++++++++++++++++++++++++++++++++++++------ 2 files changed, 71 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 38b28ab..5b468a8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2017-06-16 Richard Earnshaw + * doc/invoke.texi (ARM Options, -mcpu): Document supported + extension options. + (ARM Options, -mtune): Document that this accepts the same + extension options as -mcpu. + (ARM Options, -mfpu): Document addition of -mfpu=auto. + +2017-06-16 Richard Earnshaw + * doc/invoke.texi (ARM Options, -march=): Document new syntax and permitted extensions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3567691..86c8d62 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15489,8 +15489,6 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-m0.small-multiply}, @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, -@samp{falkor}, -@samp{qdf24xx}, @samp{marvell-pj4}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, @@ -15510,12 +15508,15 @@ processors, balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of other CPUs. The effects of this option may change in future GCC versions as CPU models come and go. +@option{-mtune} permits the same extension options as @option{-mcpu}, but +the extension options do not affect the tuning of the generated code. + @option{-mtune=native} causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -@item -mcpu=@var{name} +@item -mcpu=@var{name@r{[}+extension@dots{}@r{]}} @opindex mcpu This specifies the name of the target ARM processor. GCC uses this name to derive the name of the target ARM architecture (as if specified @@ -15524,9 +15525,62 @@ performance (as if specified by @option{-mtune}). Where this option is used in conjunction with @option{-march} or @option{-mtune}, those options take precedence over the appropriate part of this option. +Many of the supported CPUs implement optional architectural +extensions. Where this is so the architectural extensions are +normally enabled by default. If implementations that lack the +extension exist, then the extension syntax can be used to disable +those extensions that have been omitted. For floating-point and +Advanced SIMD (Neon) instructions, the settings of the options +@option{-mfloat-abi} and @option{-mfpu} must also be considered: +floating-point and Advanced SIMD instructions will only be used if +@option{-mfloat-abi} is not set to @samp{soft}; and any setting of +@option{-mfpu} other than @samp{auto} will override the available +floating-point and SIMD extension instructions. + +For example, @samp{cortex-a9} can be found in three major +configurations: integer only, with just a floating-point unit or with +floating-point and Advanced SIMD. The default is to enable all the +instructions, but the extensions @samp{+nosimd} and @samp{+nofp} can +be used to disable just the SIMD or both the SIMD and floating-point +instructions respectively. + Permissible names for this option are the same as those for @option{-mtune}. +The following extension options are common to the listed CPUs: + +@table @samp +@item +nofp +Disables the floating-point instructions on @samp{arm9e}, +@samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, +@samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s}, +@samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, +@samp{cortex-m4}, @samp{cortex-m7} and @samp{cortex-m33}. +Disables the floating-point and SIMD instructions on +@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, +@samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12}, +@samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a15.cortex-a7}, +@samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35} +and @samp{cortex-a53}. + +@item +nofp.dp +Disables the double-precision component of the floating-point instructions +on @samp{cortex-r5} and @samp{cortex-m7}. + +@item +nosimd +Disables the SIMD (but not floating-point) instructions on +@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7} +and @samp{cortex-a9}. +@end table + +Additionally the @samp{generic-armv7-a} pseudo target defaults to +VFPv3 with 16 double-precision registers. It supports the following +extension options: @samp{vfpv3-d16}, @samp{vfpv3}, +@samp{vfpv3-d16-fp16}, @samp{vfpv3-fp16}, @samp{vfpv4-d16}, +@samp{vfpv4}, @samp{neon}, @samp{neon-vfpv3}, @samp{neon-fp16}, +@samp{neon-vfpv4}. The meanings are the same as for the extensions to +@option{-march=armv7-a}. + @option{-mcpu=generic-@var{arch}} is also permissible, and is equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. See @option{-mtune} for more information. @@ -15539,7 +15593,8 @@ is unsuccessful the option has no effect. @item -mfpu=@var{name} @opindex mfpu This specifies what floating-point hardware (or hardware emulation) is -available on the target. Permissible names are: @samp{vfpv2}, @samp{vfpv3}, +available on the target. Permissible names are: @samp{auto}, @samp{vfpv2}, +@samp{vfpv3}, @samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16}, @samp{neon-vfpv3}, @samp{neon-fp16}, @samp{vfpv4}, @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4}, @@ -15548,11 +15603,12 @@ available on the target. Permissible names are: @samp{vfpv2}, @samp{vfpv3}, Note that @samp{neon} is an alias for @samp{neon-vfpv3} and @samp{vfp} is an alias for @samp{vfpv2}. -If @option{-msoft-float} is specified this specifies the format of -floating-point values. +The setting @samp{auto} is the default and is special. It causes the +compiler to select the floating-point and Advanced SIMD instructions +based on the settings of @option{-mcpu} and @option{-march}. If the selected floating-point hardware includes the NEON extension -(e.g. @option{-mfpu}=@samp{neon}), note that floating-point +(e.g. @option{-mfpu=neon}), note that floating-point operations are not generated by GCC's auto-vectorization pass unless @option{-funsafe-math-optimizations} is also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for -- cgit v1.1 From 718a3eab2906217c70f27077446fa0e8ddb1bf7b Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:07:11 +0000 Subject: [arm] Mark -marm and -mthumb as being inverse options -marm and -mthumb are opposites: one cancels out the other. This patch marks them as such so that the driver will eliminate all but the last option on the command line. This aids multilib selection which otherwise can get confused if both are present. * config/arm/arm.opt (marm): Mark as the negative of of -mthumb. (mthumb): Mark as the negative of -marm. From-SVN: r249309 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/arm.opt | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5b468a8..cbc2f52 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-16 Richard Earnshaw + * config/arm/arm.opt (marm): Mark as the negative of of -mthumb. + (mthumb): Mark as the negative of -marm. + +2017-06-16 Richard Earnshaw + * doc/invoke.texi (ARM Options, -mcpu): Document supported extension options. (ARM Options, -mtune): Document that this accepts the same diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index efee1be..dad5257 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -91,7 +91,7 @@ EnumValue Enum(arm_arch) String(native) Value(-1) DriverOnly marm -Target Report RejectNegative InverseMask(THUMB) +Target Report RejectNegative Negative(mthumb) InverseMask(THUMB) Generate code in 32 bit ARM state. mbig-endian @@ -195,7 +195,7 @@ Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFA Specify the minimum bit alignment of structures. mthumb -Target Report RejectNegative Mask(THUMB) Save +Target Report RejectNegative Negative(marm) Mask(THUMB) Save Generate code for Thumb state. mthumb-interwork -- cgit v1.1 From e3e266bfb1eb3e8c10f7461910529e0cb566343d Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Fri, 16 Jun 2017 21:07:20 +0000 Subject: [arm] Fix various tests The neon-thumb2-move.c test was overriding the options that had been detected as being necessary to enable Neon. The result was that the combination of the test's options and those auto-detected were not compatible with neon leading to a test failure. The correct fix here is to stick with the options that dg-add-options arm_neon has worked out. The thumb2-slow-flash-data tests were relying (incorrectly) on a particular FPU being enabled by default. These tests are fixed by adding +fp to the architecture selected. * gcc.target/arm/neon-thumb2-move.c (dg-options): Don't override the architecture options added by dg-add-options arm_neon. * gcc.target/arm/thumb2-slow-flash-data-2.c (dg-opitions): Add +fp to the architecture. * gcc.target/arm/thumb3-slow-flash-data-3.c (dg-opitions): Likewise. * gcc.target/arm/thumb4-slow-flash-data-3.c (dg-opitions): Likewise. * gcc.target/arm/thumb5-slow-flash-data-3.c (dg-opitions): Likewise. From-SVN: r249310 --- gcc/testsuite/ChangeLog | 10 ++++++++++ gcc/testsuite/gcc.target/arm/neon-thumb2-move.c | 2 +- gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c | 2 +- gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c | 2 +- gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c | 2 +- gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c | 2 +- 6 files changed, 15 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 53cd676..984aa70 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,15 @@ 2017-06-16 Richard Earnshaw + * gcc.target/arm/neon-thumb2-move.c (dg-options): Don't override + the architecture options added by dg-add-options arm_neon. + * gcc.target/arm/thumb2-slow-flash-data-2.c (dg-opitions): Add +fp + to the architecture. + * gcc.target/arm/thumb3-slow-flash-data-3.c (dg-opitions): Likewise. + * gcc.target/arm/thumb4-slow-flash-data-3.c (dg-opitions): Likewise. + * gcc.target/arm/thumb5-slow-flash-data-3.c (dg-opitions): Likewise. + +2017-06-16 Richard Earnshaw + * gcc.target/arm/multilib.exp (rmprofile): New tests when rm-profile multilibs have been built. diff --git a/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c b/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c index 9cf86dd..d8c6748 100644 --- a/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c +++ b/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ /* { dg-require-effective-target arm_thumb2_ok } */ -/* { dg-options "-O2 -mthumb -march=armv7-a" } */ +/* { dg-options "-O2 -mthumb" } */ /* { dg-add-options arm_neon } */ /* { dg-prune-output "switch .* conflicts with" } */ diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c index 6e76043..c87e050 100644 --- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c +++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-2.c @@ -3,7 +3,7 @@ /* { dg-require-effective-target arm_thumb2_ok } */ /* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */ /* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ -/* { dg-options "-march=armv7e-m -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */ +/* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */ float f (float); diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c index fe7a12b..8c6210e 100644 --- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c +++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-3.c @@ -3,7 +3,7 @@ /* { dg-require-effective-target arm_thumb2_ok } */ /* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */ /* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ -/* { dg-options "-march=armv7e-m -mfloat-abi=hard -mthumb -mslow-flash-data" } */ +/* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -mthumb -mslow-flash-data" } */ /* From PR71607 */ diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c index cc5aea4..1bcb692 100644 --- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c +++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-4.c @@ -3,7 +3,7 @@ /* { dg-require-effective-target arm_thumb2_ok } */ /* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */ /* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ -/* { dg-options "-march=armv7e-m -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */ +/* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */ double __attribute__ ((target ("fpu=fpv5-d16"))) foo (void) diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c index b9161c4..808fff0 100644 --- a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c +++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data-5.c @@ -3,7 +3,7 @@ /* { dg-require-effective-target arm_thumb2_ok } */ /* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" "-mcpu=cortex-m7" } } */ /* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */ -/* { dg-options "-march=armv7e-m -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */ +/* { dg-options "-march=armv7e-m+fp -mfloat-abi=hard -O2 -mthumb -mslow-flash-data" } */ double __attribute__ ((target ("fpu=fpv5-sp-d16"))) foo (void) -- cgit v1.1 From be1418c7a46db1719f830500eebebc2bf40efc04 Mon Sep 17 00:00:00 2001 From: Carl Love Date: Fri, 16 Jun 2017 22:34:28 +0000 Subject: rs6000-c.c (altivec_overloaded_builtins): Add definitions for vec_float, vec_float2, vec_floato, vec_floate built-ins. gcc/ChangeLog: 2017-06-16 Carl Love * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add definitions for vec_float, vec_float2, vec_floato, vec_floate built-ins. * config/rs6000/vsx.md (define_c_enum "unspec"): Add RTL code for instructions vsx_xvcvsxws vsx_xvcvuxwsp, float2, floato and floate. * config/rs6000/rs6000-builtin.def (FLOAT2_V2DI, FLOATE_V2DF, FLOATE_2DI, FLOATO_V2DF, FLOATEE_V2DI, XVCVSXWSP_V4SF, UNS_FLOATO_V2DI, UNS_FLOATE_V2DI): Add definitions. * config/altivec.md (define_insn "p8_vmrgew_", define_mode_attr VF_sxddp): Add V4SF type to p8_vmrgew. * config/rs6000/altivec.h (vec_float, vec_float2, vec_floate, vec_floato): Add builtin defines. * doc/extend.texi (vec_float, vec_float2, vec_floate, vec_floato): Update the built-in documentation file for the new built-in functions. gcc/testsuite/ChangeLog: 2017-06-16 Carl Love * gcc.target/powerpc/builtins-3-runnable.c (test_result_sp, main): Add runnable tests and test checker for vec_float, vec_float2, vec_floate and vec_floato builtins. From-SVN: r249311 --- gcc/config/rs6000/altivec.h | 4 + gcc/config/rs6000/altivec.md | 17 ++- gcc/config/rs6000/rs6000-builtin.def | 19 ++- gcc/config/rs6000/rs6000-c.c | 28 +++- gcc/config/rs6000/rs6000-protos.h | 1 + gcc/config/rs6000/rs6000.c | 45 +++++- gcc/config/rs6000/vsx.md | 158 +++++++++++++++++++++ gcc/doc/extend.texi | 14 ++ .../gcc.target/powerpc/builtins-3-runnable.c | 92 +++++++++++- 9 files changed, 361 insertions(+), 17 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 20050eb..d542315 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -133,6 +133,10 @@ #define vec_doublel __builtin_vec_doublel #define vec_doubleh __builtin_vec_doubleh #define vec_expte __builtin_vec_expte +#define vec_float __builtin_vec_float +#define vec_float2 __builtin_vec_float2 +#define vec_floate __builtin_vec_floate +#define vec_floato __builtin_vec_floato #define vec_floor __builtin_vec_floor #define vec_loge __builtin_vec_loge #define vec_madd __builtin_vec_madd diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 487b9a4..fd15286 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -207,6 +207,9 @@ ;; versus floating point (define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")]) +;; Mode attribute for vector floate and floato conversions +(define_mode_attr VF_sxddp [(V2DI "sxd") (V2DF "dp")]) + ;; Specific iterator for parity which does not have a byte/half-word form, but ;; does have a quad word form (define_mode_iterator VParity [V4SI @@ -1316,13 +1319,13 @@ } [(set_attr "type" "vecperm")]) -;; Power8 vector merge even/odd -(define_insn "p8_vmrgew" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (vec_select:V4SI - (vec_concat:V8SI - (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")) +;; Power8 vector merge two V4SF/V4SI even words to V4SF +(define_insn "p8_vmrgew_" + [(set (match_operand:VSX_W 0 "register_operand" "=v") + (vec_select:VSX_W + (vec_concat: + (match_operand:VSX_W 1 "register_operand" "v") + (match_operand:VSX_W 2 "register_operand" "v")) (parallel [(const_int 0) (const_int 4) (const_int 2) (const_int 6)])))] "TARGET_P8_VECTOR" diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 241c439..4682628 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1591,6 +1591,8 @@ BU_VSX_2 (CMPLE_U16QI, "cmple_u16qi", CONST, vector_ngtuv16qi) BU_VSX_2 (CMPLE_U8HI, "cmple_u8hi", CONST, vector_ngtuv8hi) BU_VSX_2 (CMPLE_U4SI, "cmple_u4si", CONST, vector_ngtuv4si) BU_VSX_2 (CMPLE_U2DI, "cmple_u2di", CONST, vector_ngtuv2di) +BU_VSX_2 (FLOAT2_V2DI, "float2_v2di", CONST, float2_v2di) +BU_VSX_2 (UNS_FLOAT2_V2DI, "uns_float2_v2di", CONST, uns_float2_v2di) /* VSX abs builtin functions. */ BU_VSX_A (XVABSDP, "xvabsdp", CONST, absv2df2) @@ -1648,6 +1650,16 @@ BU_VSX_1 (XVCVSPSXDS, "xvcvspsxds", CONST, vsx_xvcvspsxds) BU_VSX_1 (XVCVSPUXDS, "xvcvspuxds", CONST, vsx_xvcvspuxds) BU_VSX_1 (XVCVSXDSP, "xvcvsxdsp", CONST, vsx_xvcvsxdsp) BU_VSX_1 (XVCVUXDSP, "xvcvuxdsp", CONST, vsx_xvcvuxdsp) + +BU_VSX_1 (XVCVSXWSP_V4SF, "vsx_xvcvsxwsp", CONST, vsx_xvcvsxwsp) +BU_VSX_1 (XVCVUXWSP_V4SF, "vsx_xvcvuxwsp", CONST, vsx_xvcvuxwsp) +BU_VSX_1 (FLOATE_V2DI, "floate_v2di", CONST, floatev2di) +BU_VSX_1 (FLOATE_V2DF, "floate_v2df", CONST, floatev2df) +BU_VSX_1 (FLOATO_V2DI, "floato_v2di", CONST, floatov2di) +BU_VSX_1 (FLOATO_V2DF, "floato_v2df", CONST, floatov2df) +BU_VSX_1 (UNS_FLOATO_V2DI, "uns_floato_v2di", CONST, unsfloatov2di) +BU_VSX_1 (UNS_FLOATE_V2DI, "uns_floate_v2di", CONST, unsfloatev2di) + BU_VSX_1 (XVRSPI, "xvrspi", CONST, vsx_xvrspi) BU_VSX_1 (XVRSPIC, "xvrspic", CONST, vsx_xvrspic) BU_VSX_1 (XVRSPIM, "xvrspim", CONST, vsx_floorv4sf2) @@ -1760,6 +1772,8 @@ BU_VSX_OVERLOAD_2 (XXMRGHW, "xxmrghw") BU_VSX_OVERLOAD_2 (XXMRGLW, "xxmrglw") BU_VSX_OVERLOAD_2 (XXSPLTD, "xxspltd") BU_VSX_OVERLOAD_2 (XXSPLTW, "xxspltw") +BU_VSX_OVERLOAD_2 (FLOAT2, "float2") +BU_VSX_OVERLOAD_2 (UNS_FLOAT2, "uns_float2") /* 1 argument VSX overloaded builtin functions. */ BU_VSX_OVERLOAD_1 (DOUBLE, "double") @@ -1771,6 +1785,9 @@ BU_VSX_OVERLOAD_1 (DOUBLEH, "doubleh") BU_VSX_OVERLOAD_1 (UNS_DOUBLEH, "uns_doubleh") BU_VSX_OVERLOAD_1 (DOUBLEL, "doublel") BU_VSX_OVERLOAD_1 (UNS_DOUBLEL, "uns_doublel") +BU_VSX_OVERLOAD_1 (FLOAT, "float") +BU_VSX_OVERLOAD_1 (FLOATE, "floate") +BU_VSX_OVERLOAD_1 (FLOATO, "floato") /* VSX builtins that are handled as special cases. */ BU_VSX_OVERLOAD_X (LD, "ld") @@ -1812,7 +1829,7 @@ BU_P8V_AV_2 (VMINSD, "vminsd", CONST, sminv2di3) BU_P8V_AV_2 (VMAXSD, "vmaxsd", CONST, smaxv2di3) BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3) BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3) -BU_P8V_AV_2 (VMRGEW, "vmrgew", CONST, p8_vmrgew) +BU_P8V_AV_2 (VMRGEW_V4SI, "vmrgew_v4si", CONST, p8_vmrgew_v4si) BU_P8V_AV_2 (VMRGOW, "vmrgow", CONST, p8_vmrgow) BU_P8V_AV_2 (VBPERMQ, "vbpermq", CONST, altivec_vbpermq) BU_P8V_AV_2 (VBPERMQ2, "vbpermq2", CONST, altivec_vbpermq2) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index f1e8d3d..19f6d9c 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -1538,6 +1538,28 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, + { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 }, + { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF, + RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 }, + { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_FLOAT2_V2DI, + RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { VSX_BUILTIN_VEC_FLOAT2, VSX_BUILTIN_UNS_FLOAT2_V2DI, + RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, + RS6000_BTI_unsigned_V2DI, 0 }, + { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF, + RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, + { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI, + RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, + { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI, + RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF, + RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, + { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI, + RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, + { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI, + RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, @@ -5262,12 +5284,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, + { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, + { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, + { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 8a231f5..8165d04 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -72,6 +72,7 @@ extern void altivec_expand_stvex_be (rtx, rtx, machine_mode, unsigned); extern void rs6000_expand_extract_even (rtx, rtx, rtx); extern void rs6000_expand_interleave (rtx, rtx, rtx, bool); extern void rs6000_scale_v2df (rtx, rtx, int); +extern void rs6000_generate_float2_code (bool, rtx, rtx, rtx); extern int expand_block_clear (rtx[]); extern int expand_block_move (rtx[]); extern bool expand_block_compare (rtx[]); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6b28658..14b1778 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -36786,7 +36786,7 @@ altivec_expand_vec_perm_const (rtx operands[4]) (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct : CODE_FOR_altivec_vmrghw_direct), { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }, - { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgew, + { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgew_v4si, { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } }, { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgow, { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } } @@ -42375,6 +42375,49 @@ rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf); } +void +rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2) +{ + rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3; + + rtx_tmp0 = gen_reg_rtx (V2DImode); + rtx_tmp1 = gen_reg_rtx (V2DImode); + + /* The destination of the vmrgew instruction layout is: + rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0]. + Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the + vmrgew instruction will be correct. */ + if (VECTOR_ELT_ORDER_BIG) + { + emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0))); + emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3))); + } + else + { + emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3))); + emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0))); + } + + rtx_tmp2 = gen_reg_rtx (V4SFmode); + rtx_tmp3 = gen_reg_rtx (V4SFmode); + + if (signed_convert) + { + emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0)); + emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1)); + } + else + { + emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0)); + emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1)); + } + + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3)); + else + emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2)); +} + /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */ static bool diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 141aa42..284c87b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -331,6 +331,14 @@ UNSPEC_VSX_CVUXDSP UNSPEC_VSX_CVSPSXDS UNSPEC_VSX_CVSPUXDS + UNSPEC_VSX_CVSXWSP + UNSPEC_VSX_CVUXWSP + UNSPEC_VSX_FLOAT2 + UNSPEC_VSX_UNS_FLOAT2 + UNSPEC_VSX_FLOATE + UNSPEC_VSX_UNS_FLOATE + UNSPEC_VSX_FLOATO + UNSPEC_VSX_UNS_FLOATO UNSPEC_VSX_TDIV UNSPEC_VSX_TSQRT UNSPEC_VSX_SET @@ -1976,6 +1984,156 @@ "xvcvspuxds %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_insn "vsx_xvcvsxwsp" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") + (unspec:V4SF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_CVSXWSP))] + "VECTOR_UNIT_VSX_P (V4SFmode)" + "xvcvsxwsp %x0,%x1" + [(set_attr "type" "vecfloat")]) + +(define_insn "vsx_xvcvuxwsp" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") + (unspec:V4SF[(match_operand:V4SI 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_CVUXWSP))] + "VECTOR_UNIT_VSX_P (V4SFmode)" + "xvcvuxwsp %x0,%x1" + [(set_attr "type" "vecfloat")]) + +;; Generate float2 +;; convert two long long signed ints to float +(define_expand "float2_v2di" + [(use (match_operand:V4SF 0 "register_operand" "=wa")) + (use (match_operand:V2DI 1 "register_operand" "wa")) + (use (match_operand:V2DI 2 "register_operand" "wa"))] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + rtx rtx_src1, rtx_src2, rtx_dst; + + rtx_dst = operands[0]; + rtx_src1 = operands[1]; + rtx_src2 = operands[2]; + + rs6000_generate_float2_code (true, rtx_dst, rtx_src1, rtx_src2); + DONE; +}) + +;; Generate uns_float2 +;; convert two long long unsigned ints to float +(define_expand "uns_float2_v2di" + [(use (match_operand:V4SF 0 "register_operand" "=wa")) + (use (match_operand:V2DI 1 "register_operand" "wa")) + (use (match_operand:V2DI 2 "register_operand" "wa"))] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + rtx rtx_src1, rtx_src2, rtx_dst; + + rtx_dst = operands[0]; + rtx_src1 = operands[1]; + rtx_src2 = operands[2]; + + rs6000_generate_float2_code (true, rtx_dst, rtx_src1, rtx_src2); + DONE; +}) + +;; Generate floate +;; convert double or long long signed to float +;; (Only even words are valid, BE numbering) +(define_expand "floate" + [(use (match_operand:V4SF 0 "register_operand" "=wa")) + (use (match_operand:VSX_D 1 "register_operand" "wa"))] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + if (VECTOR_ELT_ORDER_BIG) + { + /* Shift left one word to put even word correct location */ + rtx rtx_tmp; + rtx rtx_val = GEN_INT (4); + + rtx_tmp = gen_reg_rtx (V4SFmode); + emit_insn (gen_vsx_xvcvsp (rtx_tmp, operands[1])); + emit_insn (gen_altivec_vsldoi_v4sf (operands[0], + rtx_tmp, rtx_tmp, rtx_val)); + } + else + emit_insn (gen_vsx_xvcvsp (operands[0], operands[1])); + + DONE; +}) + +;; Generate uns_floate +;; convert long long unsigned to float +;; (Only even words are valid, BE numbering) +(define_expand "unsfloatev2di" + [(use (match_operand:V4SF 0 "register_operand" "=wa")) + (use (match_operand:V2DI 1 "register_operand" "wa"))] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + if (VECTOR_ELT_ORDER_BIG) + { + /* Shift left one word to put even word correct location */ + rtx rtx_tmp; + rtx rtx_val = GEN_INT (4); + + rtx_tmp = gen_reg_rtx (V4SFmode); + emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp, operands[1])); + emit_insn (gen_altivec_vsldoi_v4sf (operands[0], + rtx_tmp, rtx_tmp, rtx_val)); + } + else + emit_insn (gen_vsx_xvcvuxdsp (operands[0], operands[1])); + + DONE; +}) + +;; Generate floato +;; convert double or long long signed to float +;; Only odd words are valid, BE numbering) +(define_expand "floato" + [(use (match_operand:V4SF 0 "register_operand" "=wa")) + (use (match_operand:VSX_D 1 "register_operand" "wa"))] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_vsx_xvcvsp (operands[0], operands[1])); + else + { + /* Shift left one word to put odd word correct location */ + rtx rtx_tmp; + rtx rtx_val = GEN_INT (4); + + rtx_tmp = gen_reg_rtx (V4SFmode); + emit_insn (gen_vsx_xvcvsp (rtx_tmp, operands[1])); + emit_insn (gen_altivec_vsldoi_v4sf (operands[0], + rtx_tmp, rtx_tmp, rtx_val)); + } + DONE; +}) + +;; Generate uns_floato +;; convert long long unsigned to float +;; (Only odd words are valid, BE numbering) +(define_expand "unsfloatov2di" + [(use (match_operand:V4SF 0 "register_operand" "=wa")) + (use (match_operand:V2DI 1 "register_operand" "wa"))] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_vsx_xvcvuxdsp (operands[0], operands[1])); + else + { + /* Shift left one word to put odd word correct location */ + rtx rtx_tmp; + rtx rtx_val = GEN_INT (4); + + rtx_tmp = gen_reg_rtx (V4SFmode); + emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp, operands[1])); + emit_insn (gen_altivec_vsldoi_v4sf (operands[0], + rtx_tmp, rtx_tmp, rtx_val)); + } + DONE; +}) + ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since ;; since the xvrdpiz instruction does not truncate the value if the floating ;; point value is < LONG_MIN or > LONG_MAX. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 1de17b4..43f9ecf 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -16002,6 +16002,20 @@ vector float vec_expte (vector float); vector float vec_floor (vector float); +vector float vec_float (vector signed int); +vector float vec_float (vector unsigned int); + +vector float vec_float2 (vector signed long long, vector signed long long); +vector float vec_float2 (vector unsigned long long, vector signed long long); + +vector float vec_floate (vector double); +vector float vec_floate (vector signed long long); +vector float vec_floate (vector unsigned long long); + +vector float vec_floato (vector double); +vector float vec_floato (vector signed long long); +vector float vec_floato (vector unsigned long long); + vector float vec_ld (int, const vector float *); vector float vec_ld (int, const float *); vector bool int vec_ld (int, const vector bool int *); diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c index 60ec617..08b7a53 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c @@ -5,8 +5,37 @@ #include // vector +#define ALL 1 +#define EVEN 2 +#define ODD 3 + void abort (void); +void test_result_sp(int check, vector float vec_result, vector float vec_expected) +{ + int i; + for(i = 0; i<4; i++) { + + switch (check) { + case ALL: + break; + case EVEN: + if (i%2 == 0) + break; + else + continue; + case ODD: + if (i%2 != 0) + break; + else + continue; + } + + if (vec_result[i] != vec_expected[i]) + abort(); + } +} + void test_result_dp(vector double vec_result, vector double vec_expected) { if (vec_result[0] != vec_expected[0]) @@ -21,11 +50,17 @@ int main() int i; vector unsigned int vec_unint; vector signed int vec_int; + vector long long int vec_ll_int0, vec_ll_int1; + vector long long unsigned int vec_ll_uns_int0, vec_ll_uns_int1; vector float vec_flt, vec_flt_result, vec_flt_expected; vector double vec_dble0, vec_dble1, vec_dble_result, vec_dble_expected; vec_int = (vector signed int){ -1, 3, -5, 1234567 }; + vec_ll_int0 = (vector long long int){ -12, -12345678901234 }; + vec_ll_int1 = (vector long long int){ 12, 9876543210 }; vec_unint = (vector unsigned int){ 9, 11, 15, 2468013579 }; + vec_ll_uns_int0 = (vector unsigned long long int){ 102, 9753108642 }; + vec_ll_uns_int1 = (vector unsigned long long int){ 23, 29 }; vec_flt = (vector float){ -21., 3.5, -53., 78. }; vec_dble0 = (vector double){ 34.0, 97.0 }; vec_dble1 = (vector double){ 214.0, -5.5 }; @@ -34,7 +69,7 @@ int main() vec_dble_expected = (vector double){-1.000000, -5.000000}; vec_dble_result = vec_doublee (vec_int); test_result_dp(vec_dble_result, vec_dble_expected); - + vec_dble_expected = (vector double){9.000000, 15.000000}; vec_dble_result = vec_doublee (vec_unint); test_result_dp(vec_dble_result, vec_dble_expected); @@ -48,7 +83,7 @@ int main() vec_dble_expected = (vector double){3.000000, 1234567.000000}; vec_dble_result = vec_doubleo (vec_int); test_result_dp(vec_dble_result, vec_dble_expected); - + vec_dble_expected = (vector double){11.000000, 2468013579.000000}; vec_dble_result = vec_doubleo (vec_unint); test_result_dp(vec_dble_result, vec_dble_expected); @@ -62,7 +97,7 @@ int main() vec_dble_expected = (vector double){-5.000000, 1234567.000000}; vec_dble_result = vec_doublel (vec_int); test_result_dp(vec_dble_result, vec_dble_expected); - + vec_dble_expected = (vector double){15.000000, 2468013579.000000}; vec_dble_result = vec_doublel (vec_unint); test_result_dp(vec_dble_result, vec_dble_expected); @@ -71,14 +106,61 @@ int main() vec_dble_result = vec_doublel (vec_flt); test_result_dp(vec_dble_result, vec_dble_expected); - + /* conversion of words 2 and 3 */ vec_dble_expected = (vector double){-1.000000, 3.000000}; vec_dble_result = vec_doubleh (vec_int); test_result_dp(vec_dble_result, vec_dble_expected); - + vec_dble_expected = (vector double){9.000000, 11.000000}; vec_dble_result = vec_doubleh (vec_unint); test_result_dp(vec_dble_result, vec_dble_expected); + vec_dble_expected = (vector double){-21.000000, 3.500000}; + vec_dble_result = vec_doubleh (vec_flt); + test_result_dp(vec_dble_result, vec_dble_expected); + + /* conversion of integer vector to single precision float vector */ + vec_flt_expected = (vector float){-1.00, 3.00, -5.00, 1234567.00}; + vec_flt_result = vec_float (vec_int); + test_result_sp(ALL, vec_flt_result, vec_flt_expected); + + vec_flt_expected = (vector float){9.00, 11.00, 15.00, 2468013579.0}; + vec_flt_result = vec_float (vec_unint); + test_result_sp(ALL, vec_flt_result, vec_flt_expected); + + /* conversion of two double precision vectors to single precision vector */ + vec_flt_expected = (vector float){-12.00, -12345678901234.00, 12.00, 9876543210.00}; + vec_flt_result = vec_float2 (vec_ll_int0, vec_ll_int1); + test_result_sp(ALL, vec_flt_result, vec_flt_expected); + + vec_flt_expected = (vector float){102.00, 9753108642.00, 23.00, 29.00}; + vec_flt_result = vec_float2 (vec_ll_uns_int0, vec_ll_uns_int1); + test_result_sp(ALL, vec_flt_result, vec_flt_expected); + + /* conversion of even words in double precision vector to single precision vector */ + vec_flt_expected = (vector float){-12.00, 00.00, -12345678901234.00, 0.00}; + vec_flt_result = vec_floate (vec_ll_int0); + test_result_sp(EVEN, vec_flt_result, vec_flt_expected); + + vec_flt_expected = (vector float){102.00, 0.00, 9753108642.00, 0.00}; + vec_flt_result = vec_floate (vec_ll_uns_int0); + test_result_sp(EVEN, vec_flt_result, vec_flt_expected); + + vec_flt_expected = (vector float){34.00, 0.00, 97.00, 0.00}; + vec_flt_result = vec_floate (vec_dble0); + test_result_sp(EVEN, vec_flt_result, vec_flt_expected); + + /* conversion of odd words in double precision vector to single precision vector */ + vec_flt_expected = (vector float){0.00, -12.00, 00.00, -12345678901234.00}; + vec_flt_result = vec_floato (vec_ll_int0); + test_result_sp(ODD, vec_flt_result, vec_flt_expected); + + vec_flt_expected = (vector float){0.00, 102.00, 0.00, 9753108642.00}; + vec_flt_result = vec_floato (vec_ll_uns_int0); + test_result_sp(ODD, vec_flt_result, vec_flt_expected); + + vec_flt_expected = (vector float){0.00, 34.00, 0.00, 97.00}; + vec_flt_result = vec_floato (vec_dble0); + test_result_sp(ODD, vec_flt_result, vec_flt_expected); } -- cgit v1.1 From c0a73a40e9fdde782237a5114872434ee35d60d6 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sat, 17 Jun 2017 00:16:27 +0000 Subject: Daily bump. From-SVN: r249316 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index a36783b..f777f12 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170616 +20170617 -- cgit v1.1 From b126bff44d96201be452bf3d1b220c515bc0e26a Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Fri, 16 Jun 2017 22:27:33 -0400 Subject: PR c++/80639 - ICE with invalid PMF initialization. PR c++/80043 - ICE with -fpermissive * typeck.c (convert_for_assignment): Recurse when instantiate_type returns without an error. From-SVN: r249317 --- gcc/cp/ChangeLog | 7 +++++++ gcc/cp/typeck.c | 5 +++-- gcc/testsuite/g++.dg/template/ptrmem31.C | 23 +++++++++++++++++++++++ 3 files changed, 33 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.dg/template/ptrmem31.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index ce1e8d0..a2144c2 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,10 @@ +2017-06-16 Jason Merrill + + PR c++/80639 - ICE with invalid PMF initialization. + PR c++/80043 - ICE with -fpermissive + * typeck.c (convert_for_assignment): Recurse when instantiate_type + returns without an error. + 2017-06-16 Nathan Sidwell * pt.c (tsubst_baselink): Fix & clarify formatting. diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c index 05b4fbb..0f22e64 100644 --- a/gcc/cp/typeck.c +++ b/gcc/cp/typeck.c @@ -8590,9 +8590,10 @@ convert_for_assignment (tree type, tree rhs, if (rhstype == unknown_type_node) { tree r = instantiate_type (type, rhs, tf_warning_or_error); - /* -fpermissive might allow this. */ + /* -fpermissive might allow this; recurse. */ if (!seen_error ()) - return r; + return convert_for_assignment (type, r, errtype, fndecl, + parmnum, complain, flags); } else if (fndecl) error ("cannot convert %qH to %qI for argument %qP to %qD", diff --git a/gcc/testsuite/g++.dg/template/ptrmem31.C b/gcc/testsuite/g++.dg/template/ptrmem31.C new file mode 100644 index 0000000..5c66b72 --- /dev/null +++ b/gcc/testsuite/g++.dg/template/ptrmem31.C @@ -0,0 +1,23 @@ +// PR c++/80639 +// { dg-do compile { target c++14 } } + +template < typename > struct A; + +struct B +{ + template < int > void m (); + template < int > struct K { static void n (); }; + void p () { K < 0 >::n (); } +}; + +template <> struct A < B > +{ + using T = void (A::*)(); + template < int u > static constexpr T h = &B::m < u >; // { dg-error "cannot convert" } +}; + +template < int v > void B::K < v >::n () +{ + using S = A < B >; + S::h < 0 >; +} -- cgit v1.1 From 3eec359d0ddf2cfbcc6454bb478ff417c697801e Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Fri, 16 Jun 2017 22:27:45 -0400 Subject: PR c++/80831 - ICE with -fsyntax-only. * decl2.c (c_parse_final_cleanups): Use cgraph_node::get_create. From-SVN: r249318 --- gcc/cp/ChangeLog | 3 ++ gcc/cp/decl2.c | 10 +++---- gcc/testsuite/g++.dg/other/fsyntax-only1.C | 45 ++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/g++.dg/other/fsyntax-only1.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index a2144c2..48a9cf6 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,8 @@ 2017-06-16 Jason Merrill + PR c++/80831 - ICE with -fsyntax-only. + * decl2.c (c_parse_final_cleanups): Use cgraph_node::get_create. + PR c++/80639 - ICE with invalid PMF initialization. PR c++/80043 - ICE with -fpermissive * typeck.c (convert_for_assignment): Recurse when instantiate_type diff --git a/gcc/cp/decl2.c b/gcc/cp/decl2.c index 53412e9..69cb40f 100644 --- a/gcc/cp/decl2.c +++ b/gcc/cp/decl2.c @@ -4627,6 +4627,8 @@ c_parse_final_cleanups (void) if (!DECL_SAVED_TREE (decl)) continue; + cgraph_node *node = cgraph_node::get_create (decl); + /* We lie to the back end, pretending that some functions are not defined when they really are. This keeps these functions from being put out unnecessarily. But, we must @@ -4647,9 +4649,6 @@ c_parse_final_cleanups (void) && DECL_INITIAL (decl) && decl_needed_p (decl)) { - struct cgraph_node *node, *next; - - node = cgraph_node::get (decl); if (node->cpp_implicit_alias) node = node->get_alias_target (); @@ -4659,7 +4658,8 @@ c_parse_final_cleanups (void) group, we need to mark all symbols in the same comdat group that way. */ if (node->same_comdat_group) - for (next = dyn_cast (node->same_comdat_group); + for (cgraph_node *next + = dyn_cast (node->same_comdat_group); next != node; next = dyn_cast (next->same_comdat_group)) next->call_for_symbol_thunks_and_aliases (clear_decl_external, @@ -4673,7 +4673,7 @@ c_parse_final_cleanups (void) if (!DECL_EXTERNAL (decl) && decl_needed_p (decl) && !TREE_ASM_WRITTEN (decl) - && !cgraph_node::get (decl)->definition) + && !node->definition) { /* We will output the function; no longer consider it in this loop. */ diff --git a/gcc/testsuite/g++.dg/other/fsyntax-only1.C b/gcc/testsuite/g++.dg/other/fsyntax-only1.C new file mode 100644 index 0000000..19adb7e6 --- /dev/null +++ b/gcc/testsuite/g++.dg/other/fsyntax-only1.C @@ -0,0 +1,45 @@ +// PR c++/80831 +// { dg-options -fsyntax-only } +// { dg-do compile { target c++11 } } + +class A +{ +public: + virtual ~A() { } +}; + +class B { }; + +class C : public A { }; + +template +class D : public C +{ +public: + D() { } + ~D() { } +}; + +class E +{ +public: + static E& p(); + B q(); + template + B q(void (J::*r)()) + { + new D(); + return q(); + } +}; + +void t() +{ + class F + { + public: + virtual void s() { } + }; + E& x = E::p(); + B y = x.q(&F::s); +} -- cgit v1.1 From 157420b4bd936f18b64d8143a6b3f32f89689412 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Fri, 16 Jun 2017 22:27:52 -0400 Subject: PR c++/80174 - ICE with partial specialization of member template. PR c++/71747 * pt.c (get_partial_spec_bindings): Only coerce innermost args. From-SVN: r249319 --- gcc/cp/ChangeLog | 4 ++++ gcc/cp/pt.c | 8 ++++--- .../g++.dg/template/partial-specialization6.C | 28 ++++++++++++++++++++++ 3 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/g++.dg/template/partial-specialization6.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 48a9cf6..330f0f2 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,9 @@ 2017-06-16 Jason Merrill + PR c++/80174 - ICE with partial specialization of member template. + PR c++/71747 + * pt.c (get_partial_spec_bindings): Only coerce innermost args. + PR c++/80831 - ICE with -fsyntax-only. * decl2.c (c_parse_final_cleanups): Use cgraph_node::get_create. diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 3dad0fc..0a58163 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -21672,9 +21672,11 @@ get_partial_spec_bindings (tree tmpl, tree spec_tmpl, tree args) `T' is `A' but unify () does not check whether `typename T::X' is `int'. */ spec_args = tsubst (spec_args, deduced_args, tf_none, NULL_TREE); - spec_args = coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (tmpl), - spec_args, tmpl, - tf_none, false, false); + + if (spec_args != error_mark_node) + spec_args = coerce_template_parms (DECL_INNERMOST_TEMPLATE_PARMS (tmpl), + INNERMOST_TEMPLATE_ARGS (spec_args), + tmpl, tf_none, false, false); pop_tinst_level (); diff --git a/gcc/testsuite/g++.dg/template/partial-specialization6.C b/gcc/testsuite/g++.dg/template/partial-specialization6.C new file mode 100644 index 0000000..51a1590 --- /dev/null +++ b/gcc/testsuite/g++.dg/template/partial-specialization6.C @@ -0,0 +1,28 @@ +// PR c++/80174 + +typedef unsigned char uint8_t; + +template +struct HighestMaxFieldIdx { + static const uint8_t maxFieldIdx = T::fieldIdx; +}; + +template +struct Outer { + + template + struct Varint {}; + + + template + struct Varint<_fieldIdx, uint8_t, field> { + static const uint8_t fieldIdx = _fieldIdx; + }; +}; + +struct Msg { + uint8_t a; + + static const uint8_t t + = HighestMaxFieldIdx::Varint<1, uint8_t, &Msg::a> >::maxFieldIdx; +}; -- cgit v1.1 From 3da557ec145823c3f51ff3fa7c619d0064134800 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Fri, 16 Jun 2017 22:27:59 -0400 Subject: PR c++/81102 - Wrong error with partial specialization. * pt.c (unify) [TEMPLATE_PARM_INDEX]: Strip reference when comparing types. Do type deduction later. From-SVN: r249320 --- gcc/cp/ChangeLog | 4 +++ gcc/cp/pt.c | 34 +++++++++--------- .../g++.dg/template/partial-specialization7.C | 40 ++++++++++++++++++++++ gcc/testsuite/g++.dg/template/partial5.C | 2 +- 4 files changed, 63 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/g++.dg/template/partial-specialization7.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 330f0f2..2d47d7b 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,9 @@ 2017-06-16 Jason Merrill + PR c++/81102 - Wrong error with partial specialization. + * pt.c (unify) [TEMPLATE_PARM_INDEX]: Strip reference when comparing + types. Do type deduction later. + PR c++/80174 - ICE with partial specialization of member template. PR c++/71747 * pt.c (get_partial_spec_bindings): Only coerce innermost args. diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 0a58163..d2b91b2 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -20628,18 +20628,6 @@ unify (tree tparms, tree targs, tree parm, tree arg, int strict, return x; } - if (cxx_dialect >= cxx1z - /* We deduce from array bounds in try_array_deduction. */ - && !(strict & UNIFY_ALLOW_INTEGER) - && uses_template_parms (TREE_TYPE (parm)) - && !type_uses_auto (TREE_TYPE (parm))) - { - tree atype = TREE_TYPE (arg); - RECUR_AND_CHECK_FAILURE (tparms, targs, - TREE_TYPE (parm), atype, - UNIFY_ALLOW_NONE, explain_p); - } - /* [temp.deduct.type] If, in the declaration of a function template with a non-type template-parameter, the non-type template-parameter is used in an expression in the function @@ -20660,7 +20648,8 @@ unify (tree tparms, tree targs, tree parm, tree arg, int strict, /* Template-parameter dependent expression. Just accept it for now. It will later be processed in convert_template_argument. */ ; - else if (same_type_p (TREE_TYPE (arg), tparm)) + else if (same_type_p (non_reference (TREE_TYPE (arg)), + non_reference (tparm))) /* OK */; else if ((strict & UNIFY_ALLOW_INTEGER) && CP_INTEGRAL_TYPE_P (tparm)) @@ -20669,9 +20658,22 @@ unify (tree tparms, tree targs, tree parm, tree arg, int strict, corresponding parameter. */ arg = fold (build_nop (tparm, arg)); else if (uses_template_parms (tparm)) - /* We haven't deduced the type of this parameter yet. Try again - later. */ - return unify_success (explain_p); + { + /* We haven't deduced the type of this parameter yet. */ + if (cxx_dialect >= cxx1z + /* We deduce from array bounds in try_array_deduction. */ + && !(strict & UNIFY_ALLOW_INTEGER)) + { + /* Deduce it from the non-type argument. */ + tree atype = TREE_TYPE (arg); + RECUR_AND_CHECK_FAILURE (tparms, targs, + tparm, atype, + UNIFY_ALLOW_NONE, explain_p); + } + else + /* Try again later. */ + return unify_success (explain_p); + } else return unify_type_mismatch (explain_p, tparm, TREE_TYPE (arg)); diff --git a/gcc/testsuite/g++.dg/template/partial-specialization7.C b/gcc/testsuite/g++.dg/template/partial-specialization7.C new file mode 100644 index 0000000..aa42191 --- /dev/null +++ b/gcc/testsuite/g++.dg/template/partial-specialization7.C @@ -0,0 +1,40 @@ +// PR c++/81102 + +template +struct HelperWrapper; + +// [...] + +template +struct HelperWrapper +{ + static inline int WrapFuncT(const int) + { + return 0; // Changed + } +}; + +// Unary +template +struct HelperWrapper +{ + static inline int WrapFuncT(const int) + { + return 1; // Changed + } +}; + +// Binary +template +struct HelperWrapper +{ + static inline int WrapFuncT(const int) + { + return 2; // Changed + } +}; + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/g++.dg/template/partial5.C b/gcc/testsuite/g++.dg/template/partial5.C index 1b56fb3..ee45a93 100644 --- a/gcc/testsuite/g++.dg/template/partial5.C +++ b/gcc/testsuite/g++.dg/template/partial5.C @@ -14,7 +14,7 @@ template struct Y { }; template -struct Y { }; // { dg-error "" } +struct Y { }; // { dg-error "" "" { target { ! c++1z } } } template -- cgit v1.1 From cc14602e32f0ba0b6b7628c487bfa1441c2d78f4 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Fri, 16 Jun 2017 22:28:06 -0400 Subject: PR c++/80614 - Wrong mangling for C++17 noexcept type * mangle.c (write_type): Put the eh spec back on the function type. From-SVN: r249321 --- gcc/cp/ChangeLog | 3 +++ gcc/cp/mangle.c | 5 +++++ gcc/testsuite/g++.dg/cpp1z/noexcept-type16.C | 11 +++++++++++ 3 files changed, 19 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp1z/noexcept-type16.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 2d47d7b..66dd044 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,8 @@ 2017-06-16 Jason Merrill + PR c++/80614 - Wrong mangling for C++17 noexcept type + * mangle.c (write_type): Put the eh spec back on the function type. + PR c++/81102 - Wrong error with partial specialization. * pt.c (unify) [TEMPLATE_PARM_INDEX]: Strip reference when comparing types. Do type deduction later. diff --git a/gcc/cp/mangle.c b/gcc/cp/mangle.c index e866675..c83aef5 100644 --- a/gcc/cp/mangle.c +++ b/gcc/cp/mangle.c @@ -2100,6 +2100,11 @@ write_type (tree type) || TREE_CODE (t) == METHOD_TYPE) { t = build_ref_qualified_type (t, type_memfn_rqual (type)); + if (flag_noexcept_type) + { + tree r = TYPE_RAISES_EXCEPTIONS (type); + t = build_exception_variant (t, r); + } if (abi_version_at_least (8) || type == TYPE_MAIN_VARIANT (type)) /* Avoid adding the unqualified function type as a substitution. */ diff --git a/gcc/testsuite/g++.dg/cpp1z/noexcept-type16.C b/gcc/testsuite/g++.dg/cpp1z/noexcept-type16.C new file mode 100644 index 0000000..8c763a5 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1z/noexcept-type16.C @@ -0,0 +1,11 @@ +// PR c++/80614 +// { dg-options -std=c++1z } + +template void fn() {} + +int main() { + // { dg-final { scan-assembler "_Z2fnIKFvvEEvv" } } + fn(); + // { dg-final { scan-assembler "_Z2fnIKDoFvvEEvv" } } + fn(); +} -- cgit v1.1 From d4b1d43cec7ff278e97e22d1b06d220b7aa86be8 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Fri, 16 Jun 2017 22:28:18 -0400 Subject: PR c++/80465 - ICE with generic lambda with noexcept-specifier. * lambda.c (maybe_add_lambda_conv_op): Keep processing_template_decl set longer for a generic lambda. From-SVN: r249322 --- gcc/cp/ChangeLog | 4 ++++ gcc/cp/lambda.c | 9 +++++---- gcc/testsuite/g++.dg/cpp1z/noexcept-type17.C | 7 +++++++ 3 files changed, 16 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp1z/noexcept-type17.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 66dd044..1ec3b22 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,9 @@ 2017-06-16 Jason Merrill + PR c++/80465 - ICE with generic lambda with noexcept-specifier. + * lambda.c (maybe_add_lambda_conv_op): Keep processing_template_decl + set longer for a generic lambda. + PR c++/80614 - Wrong mangling for C++17 noexcept type * mangle.c (write_type): Put the eh spec back on the function type. diff --git a/gcc/cp/lambda.c b/gcc/cp/lambda.c index ee8784c..41d4921 100644 --- a/gcc/cp/lambda.c +++ b/gcc/cp/lambda.c @@ -987,6 +987,8 @@ maybe_add_lambda_conv_op (tree type) null_pointer_node); if (generic_lambda_p) { + ++processing_template_decl; + /* Prepare the dependent member call for the static member function '_FUN' and, potentially, prepare another call to be used in a decltype return expression for a deduced return call op to allow for simple @@ -1036,9 +1038,7 @@ maybe_add_lambda_conv_op (tree type) if (generic_lambda_p) { - ++processing_template_decl; tree a = forward_parm (tgt); - --processing_template_decl; CALL_EXPR_ARG (call, ix) = a; if (decltype_call) @@ -1062,11 +1062,9 @@ maybe_add_lambda_conv_op (tree type) { if (decltype_call) { - ++processing_template_decl; fn_result = finish_decltype_type (decltype_call, /*id_expression_or_member_access_p=*/false, tf_warning_or_error); - --processing_template_decl; } } else @@ -1084,6 +1082,9 @@ maybe_add_lambda_conv_op (tree type) && TYPE_NOTHROW_P (TREE_TYPE (callop))) stattype = build_exception_variant (stattype, noexcept_true_spec); + if (generic_lambda_p) + --processing_template_decl; + /* First build up the conversion op. */ tree rettype = build_pointer_type (stattype); diff --git a/gcc/testsuite/g++.dg/cpp1z/noexcept-type17.C b/gcc/testsuite/g++.dg/cpp1z/noexcept-type17.C new file mode 100644 index 0000000..46aefdd --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1z/noexcept-type17.C @@ -0,0 +1,7 @@ +// PR c++/80465 +// { dg-options -std=c++1z } + +int foo(...); +int main() { + [](auto a) noexcept(noexcept(foo(a))){}(42); +} -- cgit v1.1 From ccb7042db8997440b8571405742e49b57787490e Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Fri, 16 Jun 2017 22:28:25 -0400 Subject: PR c++/81045 - Wrong type-dependence with auto return type. * pt.c (type_dependent_expression_p): An undeduced auto outside the template isn't dependent. * call.c (build_over_call): Instantiate undeduced auto even in a template. From-SVN: r249323 --- gcc/cp/ChangeLog | 6 +++++ gcc/cp/call.c | 3 +++ gcc/cp/pt.c | 36 ++++++++++++++++++------- gcc/testsuite/g++.dg/cpp1y/auto-fn27.C | 2 +- gcc/testsuite/g++.dg/cpp1y/auto-fn39.C | 48 ++++++++++++++++++++++++++++++++++ 5 files changed, 85 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp1y/auto-fn39.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 1ec3b22..88e148b 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,11 @@ 2017-06-16 Jason Merrill + PR c++/81045 - Wrong type-dependence with auto return type. + * pt.c (type_dependent_expression_p): An undeduced auto outside the + template isn't dependent. + * call.c (build_over_call): Instantiate undeduced auto even in a + template. + PR c++/80465 - ICE with generic lambda with noexcept-specifier. * lambda.c (maybe_add_lambda_conv_op): Keep processing_template_decl set longer for a generic lambda. diff --git a/gcc/cp/call.c b/gcc/cp/call.c index 9c3f1eb..d1f27dd 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -7584,6 +7584,9 @@ build_over_call (struct z_candidate *cand, int flags, tsubst_flags_t complain) const tree *argarray; unsigned int nargs; + if (undeduced_auto_decl (fn)) + mark_used (fn, complain); + return_type = TREE_TYPE (TREE_TYPE (fn)); nargs = vec_safe_length (args); if (first_arg == NULL_TREE) diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index d2b91b2..57be0ab 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -24011,17 +24011,35 @@ type_dependent_expression_p (tree expression) return true; /* A function or variable template-id is type-dependent if it has any - dependent template arguments. Note that we only consider the innermost - template arguments here, since those are the ones that come from the - template-id; the template arguments for the enclosing class do not make it - type-dependent, they only make a member function value-dependent. */ + dependent template arguments. */ if (VAR_OR_FUNCTION_DECL_P (expression) && DECL_LANG_SPECIFIC (expression) - && DECL_TEMPLATE_INFO (expression) - && PRIMARY_TEMPLATE_P (DECL_TI_TEMPLATE (expression)) - && (any_dependent_template_arguments_p - (INNERMOST_TEMPLATE_ARGS (DECL_TI_ARGS (expression))))) - return true; + && DECL_TEMPLATE_INFO (expression)) + { + /* Consider the innermost template arguments, since those are the ones + that come from the template-id; the template arguments for the + enclosing class do not make it type-dependent unless they are used in + the type of the decl. */ + if (PRIMARY_TEMPLATE_P (DECL_TI_TEMPLATE (expression)) + && (any_dependent_template_arguments_p + (INNERMOST_TEMPLATE_ARGS (DECL_TI_ARGS (expression))))) + return true; + + /* Otherwise, if the decl isn't from a dependent scope, it can't be + type-dependent. Checking this is important for functions with auto + return type, which looks like a dependent type. */ + if (TREE_CODE (expression) == FUNCTION_DECL + && (!DECL_CLASS_SCOPE_P (expression) + || !dependent_type_p (DECL_CONTEXT (expression))) + && (!DECL_FRIEND_CONTEXT (expression) + || !dependent_type_p (DECL_FRIEND_CONTEXT (expression))) + && !DECL_LOCAL_FUNCTION_P (expression)) + { + gcc_assert (!dependent_type_p (TREE_TYPE (expression)) + || undeduced_auto_decl (expression)); + return false; + } + } /* Always dependent, on the number of arguments if nothing else. */ if (TREE_CODE (expression) == EXPR_PACK_EXPANSION) diff --git a/gcc/testsuite/g++.dg/cpp1y/auto-fn27.C b/gcc/testsuite/g++.dg/cpp1y/auto-fn27.C index b114df2..c019d9e 100644 --- a/gcc/testsuite/g++.dg/cpp1y/auto-fn27.C +++ b/gcc/testsuite/g++.dg/cpp1y/auto-fn27.C @@ -31,7 +31,7 @@ F::bar (const G &) { auto s = I; typedef decltype (s) L; - auto u =[&](L) { auto t = foo (J::K (), 0); }; // { dg-error "25:'void t' has incomplete type" } + auto u =[&](L) { auto t = foo (J::K (), 0); }; // { dg-error "25:declared void" } } struct B { typedef int G; diff --git a/gcc/testsuite/g++.dg/cpp1y/auto-fn39.C b/gcc/testsuite/g++.dg/cpp1y/auto-fn39.C new file mode 100644 index 0000000..b4ba29e --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/auto-fn39.C @@ -0,0 +1,48 @@ +// PR c++/81045 +// { dg-do compile { target c++14 } } + +template class vectorIterator; + +template class vector { + public: + auto get(unsigned int i) { return data[i]; } + + auto begin() { return vectorIterator{*this, 0}; } + auto end() { return vectorIterator{*this, 10}; } + + private: + T data[10] = {}; +}; + +template class vectorIterator { + public: + vectorIterator(vector& self, unsigned int offset) : self(self), offset(offset) {} + + auto operator*() -> T& { return self.get(offset); } + auto operator!=(const vectorIterator& source) -> bool { return offset != source.offset; } + auto operator++() -> vectorIterator& { ++offset; return *this; } + + private: + vector& self; + unsigned int offset; +}; + +class Object { + public: + template auto cast() -> T { + return T(); + } +}; + +class Group : public Object { + public: + template auto objects() const -> void { + vector easyObjects; + for(auto obj : easyObjects) { + auto casted = obj.cast(); + } + } +}; + +int main() { return 0; } + -- cgit v1.1 From e8cc8c92f0f2fbcb5de346d2b932e99d882d1559 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Fri, 16 Jun 2017 22:48:52 -0400 Subject: fix ChangeLog From-SVN: r249334 --- gcc/cp/ChangeLog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 88e148b..dba5e4d 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -17,7 +17,7 @@ * pt.c (unify) [TEMPLATE_PARM_INDEX]: Strip reference when comparing types. Do type deduction later. - PR c++/80174 - ICE with partial specialization of member template. + PR c++/81074 - ICE with partial specialization of member template. PR c++/71747 * pt.c (get_partial_spec_bindings): Only coerce innermost args. -- cgit v1.1 From b36a612c99166cee8222ce257b62fcc0895d41b7 Mon Sep 17 00:00:00 2001 From: Carl Love Date: Sat, 17 Jun 2017 03:12:12 +0000 Subject: ChangeLog: Update for commit 249311 didn't get committed 2017-06-16 Carl Love * gcc/ChangeLog: Update for commit 249311 didn't get committed * gcc/testsuite/ChangeLog: Update for commit commit 249311 didn't get committed. From-SVN: r249336 --- gcc/ChangeLog | 19 +++++++++++++++++++ gcc/testsuite/ChangeLog | 6 ++++++ 2 files changed, 25 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cbc2f52..a741d75 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2017-06-16 Carl Love + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + definitions for vec_float, vec_float2, vec_floato, + vec_floate built-ins. + * config/rs6000/vsx.md (define_c_enum "unspec"): Add RTL code + for instructions vsx_xvcvsxws vsx_xvcvuxwsp, float2, floato and + floate. + * config/rs6000/rs6000-builtin.def (FLOAT2_V2DI, FLOATE_V2DF, + FLOATE_2DI, FLOATO_V2DF, FLOATEE_V2DI, XVCVSXWSP_V4SF, + UNS_FLOATO_V2DI, UNS_FLOATE_V2DI): Add definitions. + * config/altivec.md (define_insn "p8_vmrgew_", + define_mode_attr VF_sxddp): Add V4SF type to p8_vmrgew. + * config/rs6000/altivec.h (vec_float, vec_float2, vec_floate, + vec_floato): Add builtin defines. + * doc/extend.texi (vec_float, vec_float2, vec_floate, vec_floato): + Update the built-in documentation file for the new built-in + functions. + 2017-06-16 Richard Earnshaw * config/arm/arm.opt (marm): Mark as the negative of of -mthumb. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 984aa70..be06b90 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-06-16 Carl Love + + * gcc.target/powerpc/builtins-3-runnable.c (test_result_sp, + main): Add runnable tests and test checker for vec_float, + vec_float2, vec_floate and vec_floato builtins. + 2017-06-16 Richard Earnshaw * gcc.target/arm/neon-thumb2-move.c (dg-options): Don't override -- cgit v1.1 From 394a527f8556c4e3952b783e41d1d22b6589bec8 Mon Sep 17 00:00:00 2001 From: Carl Love Date: Sat, 17 Jun 2017 03:14:53 +0000 Subject: altivec.md (define_mode_attr VF_sxddp): Move to vsx.md. gcc/ChangeLog: 2017-06-16 Carl Love * config/rs6000/altivec.md (define_mode_attr VF_sxddp): Move to vsx.md. * config/rs6000/vsx.md (define_mode_attr VF_sxddp define_expand "floate", define_expand "floato"): Add VF_sxddp definition, replace undefined VFC_inst with VF_sxddp definition From-SVN: r249337 --- gcc/config/rs6000/altivec.md | 3 --- gcc/config/rs6000/vsx.md | 9 ++++++--- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index fd15286..25b2768 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -207,9 +207,6 @@ ;; versus floating point (define_mode_attr VS_sxwsp [(V4SI "sxw") (V4SF "sp")]) -;; Mode attribute for vector floate and floato conversions -(define_mode_attr VF_sxddp [(V2DI "sxd") (V2DF "dp")]) - ;; Specific iterator for parity which does not have a byte/half-word form, but ;; does have a quad word form (define_mode_iterator VParity [V4SI diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 284c87b..7aa6d32 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -21,6 +21,9 @@ ;; Iterator for comparison types (define_code_iterator CMP_TEST [eq lt gt unordered]) +;; Mode attribute for vector floate and floato conversions +(define_mode_attr VF_sxddp [(V2DI "sxd") (V2DF "dp")]) + ;; Iterator for both scalar and vector floating point types supported by VSX (define_mode_iterator VSX_B [DF V4SF V2DF]) @@ -2056,7 +2059,7 @@ rtx_tmp, rtx_tmp, rtx_val)); } else - emit_insn (gen_vsx_xvcvsp (operands[0], operands[1])); + emit_insn (gen_vsx_xvcvsp (operands[0], operands[1])); DONE; }) @@ -2095,7 +2098,7 @@ "VECTOR_UNIT_VSX_P (V4SFmode)" { if (VECTOR_ELT_ORDER_BIG) - emit_insn (gen_vsx_xvcvsp (operands[0], operands[1])); + emit_insn (gen_vsx_xvcvsp (operands[0], operands[1])); else { /* Shift left one word to put odd word correct location */ @@ -2103,7 +2106,7 @@ rtx rtx_val = GEN_INT (4); rtx_tmp = gen_reg_rtx (V4SFmode); - emit_insn (gen_vsx_xvcvsp (rtx_tmp, operands[1])); + emit_insn (gen_vsx_xvcvsp (rtx_tmp, operands[1])); emit_insn (gen_altivec_vsldoi_v4sf (operands[0], rtx_tmp, rtx_tmp, rtx_val)); } -- cgit v1.1 From 4f4b0ab85f7996ca5090e2649fc631906cd74e36 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Sat, 17 Jun 2017 15:32:28 +0000 Subject: Get rid of dg-skip-if etc. default args libstdc++-v3: * testsuite: Remove dg-skip-if, dg-xfail-if, dg-xfail-run-if default args. libgomp: * testsuite/libgomp.fortran/strassen.f90: Remove dg-skip-if default args. * testsuite/libgomp.oacc-c-c++-common/vprop.c: Remove dg-xfail-run-if default args. gcc/testsuite: Remove dg-skip-if, dg-xfail-if, dg-xfail-run-if default args. From-SVN: r249339 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/c-c++-common/Wconversion-real.c | 2 +- gcc/testsuite/c-c++-common/dfp/convert-bfp-11.c | 2 +- gcc/testsuite/c-c++-common/dfp/convert-bfp-6.c | 2 +- gcc/testsuite/c-c++-common/dfp/convert-bfp-9.c | 2 +- gcc/testsuite/c-c++-common/pr41779.c | 2 +- gcc/testsuite/c-c++-common/pr54486.c | 2 +- gcc/testsuite/g++.dg/abi/rtti3.C | 2 +- gcc/testsuite/g++.dg/abi/thunk4.C | 2 +- gcc/testsuite/g++.dg/cpp0x/cast.C | 2 +- gcc/testsuite/g++.dg/cpp0x/iop.C | 2 +- gcc/testsuite/g++.dg/cpp0x/named_refs.C | 2 +- gcc/testsuite/g++.dg/cpp0x/rv1p.C | 2 +- gcc/testsuite/g++.dg/cpp0x/rv2p.C | 2 +- gcc/testsuite/g++.dg/cpp0x/rv3p.C | 2 +- gcc/testsuite/g++.dg/cpp0x/rv4p.C | 2 +- gcc/testsuite/g++.dg/cpp0x/rv5p.C | 2 +- gcc/testsuite/g++.dg/cpp0x/rv6p.C | 2 +- gcc/testsuite/g++.dg/cpp0x/rv7p.C | 2 +- gcc/testsuite/g++.dg/cpp0x/rv8p.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/pr61433.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/pubnames-2.C | 2 +- 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gcc/testsuite/g++.dg/pr65240-2.C | 2 +- gcc/testsuite/g++.dg/pr65240-3.C | 2 +- gcc/testsuite/g++.dg/pr65240-4.C | 2 +- gcc/testsuite/g++.dg/pr65242.C | 2 +- gcc/testsuite/g++.dg/pr67211.C | 2 +- gcc/testsuite/g++.dg/pr69667.C | 2 +- gcc/testsuite/g++.dg/pr78112-2.C | 2 +- gcc/testsuite/g++.dg/torture/pr31863.C | 2 +- gcc/testsuite/g++.dg/torture/stackalign/eh-alloca-1.C | 2 +- gcc/testsuite/g++.dg/torture/stackalign/eh-global-1.C | 2 +- gcc/testsuite/g++.dg/torture/stackalign/eh-inline-1.C | 2 +- gcc/testsuite/g++.dg/torture/stackalign/eh-inline-2.C | 2 +- gcc/testsuite/g++.dg/torture/stackalign/eh-vararg-1.C | 2 +- gcc/testsuite/g++.dg/torture/stackalign/eh-vararg-2.C | 2 +- gcc/testsuite/g++.dg/torture/stackalign/throw-1.C | 2 +- gcc/testsuite/g++.dg/torture/stackalign/throw-2.C | 2 +- gcc/testsuite/g++.dg/torture/stackalign/throw-4.C | 2 +- gcc/testsuite/g++.dg/warn/weak1.C | 6 +++--- gcc/testsuite/g++.old-deja/g++.brendan/crash43.C | 2 +- gcc/testsuite/g++.old-deja/g++.brendan/synth1.C | 2 +- gcc/testsuite/g++.old-deja/g++.jason/thunk2.C | 2 +- gcc/testsuite/g++.old-deja/g++.jason/thunk3.C | 2 +- gcc/testsuite/g++.old-deja/g++.law/bit-fields2.C | 2 +- gcc/testsuite/g++.old-deja/g++.mike/eh46.C | 2 +- gcc/testsuite/g++.old-deja/g++.mike/ns15.C | 2 +- gcc/testsuite/g++.old-deja/g++.mike/p10416.C | 2 +- gcc/testsuite/g++.old-deja/g++.other/comdat5.C | 2 +- gcc/testsuite/g++.old-deja/g++.other/local-alloc1.C | 2 +- gcc/testsuite/g++.old-deja/g++.pt/asm1.C | 2 +- gcc/testsuite/g++.old-deja/g++.pt/crash16.C | 2 +- gcc/testsuite/g++.old-deja/g++.pt/static6.C | 2 +- gcc/testsuite/gcc.c-torture/compile/20000804-1.c | 6 +++--- gcc/testsuite/gcc.c-torture/compile/20001226-1.c | 6 +++--- gcc/testsuite/gcc.c-torture/compile/20060208-1.c | 2 +- gcc/testsuite/gcc.c-torture/compile/20080721-1.c | 2 +- gcc/testsuite/gcc.c-torture/compile/920520-1.c | 2 +- gcc/testsuite/gcc.c-torture/compile/980506-1.c | 2 +- gcc/testsuite/gcc.c-torture/compile/limits-externdecl.c | 2 +- gcc/testsuite/gcc.c-torture/compile/limits-fndefn.c | 4 ++-- gcc/testsuite/gcc.c-torture/compile/limits-stringlit.c | 2 +- gcc/testsuite/gcc.c-torture/compile/pr35318.c | 2 +- gcc/testsuite/gcc.c-torture/compile/pr41181.c | 2 +- gcc/testsuite/gcc.c-torture/compile/pr46534.c | 2 +- gcc/testsuite/gcc.c-torture/execute/20020404-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/20030222-1.c | 4 ++-- gcc/testsuite/gcc.c-torture/execute/20061220-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/990413-2.c | 2 +- gcc/testsuite/gcc.c-torture/execute/bf64-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/complex-6.c | 2 +- gcc/testsuite/gcc.c-torture/execute/fprintf-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/fprintf-chk-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/gofast.c | 2 +- gcc/testsuite/gcc.c-torture/execute/loop-2f.c | 2 +- gcc/testsuite/gcc.c-torture/execute/loop-2g.c | 2 +- gcc/testsuite/gcc.c-torture/execute/pr34456.c | 2 +- gcc/testsuite/gcc.c-torture/execute/pr35456.c | 2 +- gcc/testsuite/gcc.c-torture/execute/pr39228.c | 2 +- gcc/testsuite/gcc.c-torture/execute/pr47237.c | 2 +- gcc/testsuite/gcc.c-torture/execute/pr78622.c | 2 +- gcc/testsuite/gcc.c-torture/execute/printf-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/printf-chk-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/strncmp-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/vfprintf-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/vprintf-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/zerolen-2.c | 2 +- gcc/testsuite/gcc.dg/20020219-1.c | 4 ++-- gcc/testsuite/gcc.dg/20030702-1.c | 2 +- gcc/testsuite/gcc.dg/20050503-1.c | 2 +- gcc/testsuite/gcc.dg/Wconversion-complex-c99.c | 2 +- gcc/testsuite/gcc.dg/Wconversion-complex-gnu.c | 2 +- gcc/testsuite/gcc.dg/Wconversion-real-integer.c | 2 +- gcc/testsuite/gcc.dg/attr-alias-3.c | 2 +- gcc/testsuite/gcc.dg/attr-alias-5.c | 2 +- gcc/testsuite/gcc.dg/attr-weakref-1.c | 2 +- gcc/testsuite/gcc.dg/autopar/pr46799.c | 2 +- gcc/testsuite/gcc.dg/builtin-apply2.c | 6 +++--- gcc/testsuite/gcc.dg/builtin-object-size-10.c | 2 +- gcc/testsuite/gcc.dg/builtin-object-size-11.c | 2 +- gcc/testsuite/gcc.dg/builtin-return-1.c | 2 +- gcc/testsuite/gcc.dg/builtin-stringop-chk-1.c | 2 +- gcc/testsuite/gcc.dg/c11-align-4.c | 2 +- gcc/testsuite/gcc.dg/c11-true_min-1.c | 2 +- gcc/testsuite/gcc.dg/cdce2.c | 2 +- gcc/testsuite/gcc.dg/cleanup-12.c | 4 ++-- gcc/testsuite/gcc.dg/cleanup-13.c | 4 ++-- gcc/testsuite/gcc.dg/cleanup-5.c | 4 ++-- gcc/testsuite/gcc.dg/compat/struct-by-value-16_main.c | 2 +- gcc/testsuite/gcc.dg/compat/struct-by-value-17_main.c | 2 +- gcc/testsuite/gcc.dg/compat/struct-by-value-18_main.c | 2 +- gcc/testsuite/gcc.dg/constructor-1.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char1.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char2.c | 2 +- gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char3.c | 2 +- gcc/testsuite/gcc.dg/debug/pr35154.c | 2 +- gcc/testsuite/gcc.dg/dfp/convert-dfp-round.c | 2 +- gcc/testsuite/gcc.dg/dfp/fe-binop.c | 2 +- gcc/testsuite/gcc.dg/dfp/fe-convert-1.c | 2 +- gcc/testsuite/gcc.dg/format/dfp-printf-1.c | 2 +- gcc/testsuite/gcc.dg/graphite/run-id-pr47653.c | 2 +- gcc/testsuite/gcc.dg/loop-8.c | 2 +- gcc/testsuite/gcc.dg/lower-subreg-1.c | 2 +- gcc/testsuite/gcc.dg/lto/20081126_0.c | 2 +- gcc/testsuite/gcc.dg/lto/20081204-2_0.c | 2 +- gcc/testsuite/gcc.dg/lto/20090206-1_0.c | 2 +- gcc/testsuite/gcc.dg/lto/20090206-2_0.c | 2 +- gcc/testsuite/gcc.dg/lto/20090914-2_0.c | 6 +++--- gcc/testsuite/gcc.dg/lto/20091013-1_1.c | 2 +- gcc/testsuite/gcc.dg/lto/20091013-1_2.c | 2 +- gcc/testsuite/gcc.dg/lto/20100518_0.c | 2 +- gcc/testsuite/gcc.dg/lto/20120723_0.c | 2 +- gcc/testsuite/gcc.dg/lto/pr47259_0.c | 2 +- gcc/testsuite/gcc.dg/pr25805.c | 2 +- gcc/testsuite/gcc.dg/pr27531-1.c | 2 +- gcc/testsuite/gcc.dg/pr28243.c | 2 +- gcc/testsuite/gcc.dg/pr35045.c | 2 +- gcc/testsuite/gcc.dg/pr40172-3.c | 2 +- gcc/testsuite/gcc.dg/pr41241.c | 2 +- gcc/testsuite/gcc.dg/pr41345.c | 2 +- gcc/testsuite/gcc.dg/pr42629.c | 2 +- gcc/testsuite/gcc.dg/pr42630.c | 2 +- gcc/testsuite/gcc.dg/pr42631.c | 2 +- gcc/testsuite/gcc.dg/pr42719.c | 2 +- gcc/testsuite/gcc.dg/pr42728.c | 2 +- gcc/testsuite/gcc.dg/pr42889.c | 2 +- gcc/testsuite/gcc.dg/pr42916.c | 2 +- gcc/testsuite/gcc.dg/pr43084.c | 2 +- gcc/testsuite/gcc.dg/pr43670.c | 2 +- gcc/testsuite/gcc.dg/pr44023.c | 2 +- gcc/testsuite/gcc.dg/pr44606.c | 2 +- gcc/testsuite/gcc.dg/pr44971.c | 2 +- gcc/testsuite/gcc.dg/pr45416.c | 2 +- gcc/testsuite/gcc.dg/pr45449.c | 2 +- gcc/testsuite/gcc.dg/pr46771.c | 2 +- gcc/testsuite/gcc.dg/pr47684.c | 2 +- gcc/testsuite/gcc.dg/pr47881.c | 2 +- gcc/testsuite/gcc.dg/pr47893.c | 2 +- gcc/testsuite/gcc.dg/pr48768.c | 2 +- gcc/testsuite/gcc.dg/pr49551.c | 2 +- gcc/testsuite/gcc.dg/pr50017.c | 2 +- gcc/testsuite/gcc.dg/pr56023.c | 2 +- gcc/testsuite/gcc.dg/pr56228.c | 2 +- gcc/testsuite/gcc.dg/pr64434.c | 2 +- gcc/testsuite/gcc.dg/pr64935-1.c | 2 +- gcc/testsuite/gcc.dg/pr64935-2.c | 2 +- gcc/testsuite/gcc.dg/pr65521.c | 2 +- gcc/testsuite/gcc.dg/pr65779.c | 2 +- gcc/testsuite/gcc.dg/pr65980.c | 2 +- gcc/testsuite/gcc.dg/pr66688.c | 2 +- gcc/testsuite/gcc.dg/pr68671.c | 2 +- gcc/testsuite/gcc.dg/pr70405.c | 2 +- gcc/testsuite/gcc.dg/pubtypes-1.c | 2 +- gcc/testsuite/gcc.dg/pubtypes-2.c | 2 +- gcc/testsuite/gcc.dg/pubtypes-3.c | 2 +- gcc/testsuite/gcc.dg/pubtypes-4.c | 2 +- gcc/testsuite/gcc.dg/setjmp-1.c | 2 +- gcc/testsuite/gcc.dg/sibcall-6.c | 2 +- gcc/testsuite/gcc.dg/sms-12.c | 2 +- gcc/testsuite/gcc.dg/special/weak-2.c | 2 +- gcc/testsuite/gcc.dg/stack-usage-1.c | 2 +- gcc/testsuite/gcc.dg/torture/asm-subreg-1.c | 2 +- gcc/testsuite/gcc.dg/torture/builtin-math-7.c | 2 +- gcc/testsuite/gcc.dg/torture/c99-contract-1.c | 2 +- gcc/testsuite/gcc.dg/torture/pr26565.c | 2 +- gcc/testsuite/gcc.dg/torture/pr37868.c | 2 +- gcc/testsuite/gcc.dg/torture/pr45764.c | 2 +- gcc/testsuite/gcc.dg/torture/pr51106-2.c | 2 +- gcc/testsuite/gcc.dg/torture/pr53922.c | 8 ++++---- gcc/testsuite/gcc.dg/torture/pr59166.c | 2 +- gcc/testsuite/gcc.dg/torture/pr60092.c | 2 +- gcc/testsuite/gcc.dg/torture/stackalign/alloca-1.c | 2 +- gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c | 4 ++-- gcc/testsuite/gcc.dg/torture/stackalign/global-1.c | 4 ++-- gcc/testsuite/gcc.dg/torture/stackalign/inline-1.c | 4 ++-- gcc/testsuite/gcc.dg/torture/stackalign/inline-2.c | 2 +- gcc/testsuite/gcc.dg/torture/stackalign/nested-1.c | 4 ++-- gcc/testsuite/gcc.dg/torture/stackalign/nested-2.c | 4 ++-- gcc/testsuite/gcc.dg/torture/stackalign/nested-3.c | 2 +- gcc/testsuite/gcc.dg/torture/stackalign/nested-4.c | 4 ++-- gcc/testsuite/gcc.dg/torture/stackalign/pr16660-1.c | 4 ++-- gcc/testsuite/gcc.dg/torture/stackalign/pr16660-2.c | 2 +- gcc/testsuite/gcc.dg/torture/stackalign/pr16660-3.c | 2 +- gcc/testsuite/gcc.dg/torture/stackalign/ret-struct-1.c | 4 ++-- gcc/testsuite/gcc.dg/torture/stackalign/struct-1.c | 4 ++-- gcc/testsuite/gcc.dg/torture/stackalign/vararg-1.c | 2 +- gcc/testsuite/gcc.dg/torture/stackalign/vararg-2.c | 2 +- gcc/testsuite/gcc.dg/tree-prof/val-prof-7.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt-2.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/pr47286.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-store-ccp-3.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-store-ccp-4.c | 2 +- gcc/testsuite/gcc.dg/ucnid-10.c | 2 +- gcc/testsuite/gcc.dg/ucnid-11.c | 6 +++--- gcc/testsuite/gcc.dg/ucnid-12.c | 6 +++--- gcc/testsuite/gcc.dg/ucnid-13.c | 2 +- gcc/testsuite/gcc.dg/ucnid-2.c | 4 ++-- gcc/testsuite/gcc.dg/ucnid-3.c | 4 ++-- gcc/testsuite/gcc.dg/ucnid-4.c | 4 ++-- gcc/testsuite/gcc.dg/ucnid-5.c | 2 +- gcc/testsuite/gcc.dg/ucnid-6.c | 4 ++-- gcc/testsuite/gcc.dg/ucnid-7.c | 2 +- gcc/testsuite/gcc.dg/ucnid-8.c | 2 +- gcc/testsuite/gcc.dg/ucnid-9.c | 4 ++-- gcc/testsuite/gcc.dg/unused-5.c | 2 +- gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c | 2 +- gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c | 2 +- gcc/testsuite/gcc.dg/vect/pr49352.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-82.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-82_64.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-83.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-83_64.c | 2 +- gcc/testsuite/gcc.dg/visibility-11.c | 2 +- gcc/testsuite/gcc.dg/visibility-14.c | 2 +- gcc/testsuite/gcc.dg/visibility-15.c | 2 +- gcc/testsuite/gcc.dg/visibility-16.c | 2 +- gcc/testsuite/gcc.dg/visibility-17.c | 2 +- gcc/testsuite/gcc.dg/visibility-18.c | 2 +- gcc/testsuite/gcc.dg/visibility-19.c | 2 +- gcc/testsuite/gcc.dg/visibility-22.c | 2 +- gcc/testsuite/gcc.dg/visibility-23.c | 2 +- gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c | 2 +- gcc/testsuite/gcc.dg/vmx/extract-vsx.c | 2 +- gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c | 2 +- gcc/testsuite/gcc.dg/vmx/insert-vsx.c | 2 +- gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c | 2 +- gcc/testsuite/gcc.dg/vmx/ld-vsx.c | 2 +- gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c | 2 +- gcc/testsuite/gcc.dg/vmx/ldl-vsx.c | 2 +- gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c | 2 +- gcc/testsuite/gcc.dg/vmx/merge-vsx.c | 2 +- gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c | 2 +- gcc/testsuite/gcc.dg/vmx/splat-vsx.c | 2 +- gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c | 2 +- gcc/testsuite/gcc.dg/vmx/st-vsx.c | 2 +- gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c | 2 +- gcc/testsuite/gcc.dg/vmx/stl-vsx.c | 2 +- gcc/testsuite/gcc.dg/weak/weak-1.c | 4 ++-- gcc/testsuite/gcc.dg/weak/weak-12.c | 2 +- gcc/testsuite/gcc.dg/weak/weak-15.c | 4 ++-- gcc/testsuite/gcc.dg/weak/weak-16.c | 4 ++-- gcc/testsuite/gcc.dg/weak/weak-2.c | 4 ++-- gcc/testsuite/gcc.dg/weak/weak-3.c | 2 +- gcc/testsuite/gcc.dg/weak/weak-4.c | 4 ++-- gcc/testsuite/gcc.dg/weak/weak-5.c | 2 +- gcc/testsuite/gcc.misc-tests/gcov-13.c | 2 +- gcc/testsuite/gcc.target/arm/frame-pointer-1.c | 2 +- gcc/testsuite/gcc.target/arm/mla-1.c | 2 +- gcc/testsuite/gcc.target/arm/pr56184.C | 2 +- gcc/testsuite/gcc.target/arm/pr58784.c | 2 +- gcc/testsuite/gcc.target/arm/pr59896.c | 2 +- gcc/testsuite/gcc.target/arm/pr59985.C | 2 +- gcc/testsuite/gcc.target/arm/stack-red-zone.c | 2 +- gcc/testsuite/gcc.target/arm/thumb-find-work-register.c | 2 +- gcc/testsuite/gcc.target/i386/align-main-1.c | 2 +- gcc/testsuite/gcc.target/i386/align-main-2.c | 2 +- gcc/testsuite/gcc.target/i386/asm-3.c | 2 +- gcc/testsuite/gcc.target/i386/pad-4.c | 2 +- gcc/testsuite/gcc.target/i386/pic-1.c | 2 +- gcc/testsuite/gcc.target/i386/pr25993.c | 2 +- gcc/testsuite/gcc.target/i386/pr32000-2.c | 2 +- gcc/testsuite/gcc.target/i386/pr35160.c | 2 +- gcc/testsuite/gcc.target/i386/pr39543-2.c | 2 +- gcc/testsuite/gcc.target/i386/pr44130.c | 2 +- gcc/testsuite/gcc.target/i386/pr46470.c | 4 ++-- gcc/testsuite/gcc.target/i386/stack-usage-realign.c | 2 +- gcc/testsuite/gcc.target/i386/stackalign/return-3.c | 2 +- gcc/testsuite/gcc.target/i386/sw-1.c | 2 +- gcc/testsuite/gcc.target/ia64/builtin-fma-2.c | 2 +- gcc/testsuite/gcc.target/m68k/tls-gd-xgot.c | 2 +- gcc/testsuite/gcc.target/m68k/tls-gd.c | 2 +- gcc/testsuite/gcc.target/m68k/tls-ie-xgot.c | 2 +- gcc/testsuite/gcc.target/m68k/tls-ie.c | 2 +- gcc/testsuite/gcc.target/m68k/tls-ld-xgot-xtls.c | 2 +- gcc/testsuite/gcc.target/m68k/tls-ld-xgot.c | 2 +- gcc/testsuite/gcc.target/m68k/tls-ld-xtls.c | 2 +- gcc/testsuite/gcc.target/m68k/tls-ld.c | 2 +- gcc/testsuite/gcc.target/m68k/tls-le-xtls.c | 2 +- gcc/testsuite/gcc.target/m68k/tls-le.c | 2 +- gcc/testsuite/gcc.target/powerpc/20020118-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/20030218-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/20030505.c | 2 +- gcc/testsuite/gcc.target/powerpc/20081204-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/405-macchw-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-macchw-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-machhw-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-machhw-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/altivec-32.c | 2 +- gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/atomic-p7.c | 2 +- gcc/testsuite/gcc.target/powerpc/atomic-p8.c | 2 +- gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c | 2 +- gcc/testsuite/gcc.target/powerpc/bcd-1.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/bcd-2.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/bcd-3.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1a.c | 2 +- gcc/testsuite/gcc.target/powerpc/bool2-av.c | 2 +- gcc/testsuite/gcc.target/powerpc/bool2-p5.c | 2 +- gcc/testsuite/gcc.target/powerpc/bool2-p7.c | 2 +- gcc/testsuite/gcc.target/powerpc/bool2-p8.c | 2 +- gcc/testsuite/gcc.target/powerpc/bool3-av.c | 2 +- gcc/testsuite/gcc.target/powerpc/bool3-p7.c | 2 +- gcc/testsuite/gcc.target/powerpc/bool3-p8.c | 2 +- gcc/testsuite/gcc.target/powerpc/bswap64-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c | 2 +- gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c | 2 +- gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c | 2 +- gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/ctz-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/ctz-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/direct-move-double1.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/direct-move-double2.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/direct-move-float1.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/direct-move-float2.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/direct-move-long1.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/direct-move-long2.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/ehreturn.c | 2 +- gcc/testsuite/gcc.target/powerpc/extend-divide-1.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/extend-divide-2.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/fusion.c | 2 +- gcc/testsuite/gcc.target/powerpc/fusion2.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/fusion3.c | 2 +- gcc/testsuite/gcc.target/powerpc/fusion4.c | 2 +- gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c | 2 +- gcc/testsuite/gcc.target/powerpc/htm-ttest.c | 2 +- gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/lhs-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/lhs-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/lhs-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/loop_align.c | 2 +- gcc/testsuite/gcc.target/powerpc/mmfpgpr.c | 2 +- gcc/testsuite/gcc.target/powerpc/no-r11-1.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/no-r11-2.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/no-r11-3.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-fp.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/p9-vparity.c | 2 +- gcc/testsuite/gcc.target/powerpc/pack01.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/pack02.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/pack03.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/parity-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/popcount-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/popcount-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/popcount-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-pow.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-round.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-round2.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-round3.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-spe.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-target-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-target-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-target-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-target-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr42747.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr43154.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/pr47251.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr47755-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr47755.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr47862.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr48053-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr48192.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr48226.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr48258-1.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/pr48258-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr48857.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr52199.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr52457.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/pr52775.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr53199.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr53487.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr57150.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr57744.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr57949-1.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/pr57949-2.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/pr58673-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr58673-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr59054.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr60102.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr60137.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr60158.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr60203.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr60676.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr60735.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr64019.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr64205.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr64505.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr65849-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr65849-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr67789.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr67808.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr68163.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr69548.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr70963.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr71977-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr71977-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr72717.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr72853.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr77289.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr77416.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr78604.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr80510-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr80510-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr80718.c | 2 +- gcc/testsuite/gcc.target/powerpc/quad-atomic.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/recip-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/recip-6.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/recip-7.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/sd-pwr6.c | 2 +- gcc/testsuite/gcc.target/powerpc/sd-vsx.c | 2 +- gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c | 2 +- gcc/testsuite/gcc.target/powerpc/spe1.c | 2 +- gcc/testsuite/gcc.target/powerpc/tfmode_off.c | 4 ++-- gcc/testsuite/gcc.target/powerpc/upper-regs-df.c | 2 +- gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-cmp.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-extract-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-extract-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-extract-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-extract-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-extract-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-extract-6.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-extract-7.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-extract-8.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-extract-9.c | 2 +- gcc/testsuite/gcc.target/powerpc/vec-shift.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-extract-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-extract-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-extract-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-float0.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-himode.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-himode2.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-himode3.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-qimode.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-simode.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-simode2.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-simode3.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c | 2 +- gcc/testsuite/gcc.target/powerpc/warn-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/warn-2.c | 2 +- gcc/testsuite/gcc.target/rx/zero-width-bitfield.c | 2 +- gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-F.c | 2 +- gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-P.c | 2 +- gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-XF.c | 2 +- gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-XP.c | 2 +- gcc/testsuite/gcc.test-framework/dg-do-run-xrif-nocache-exp-XF.c | 2 +- gcc/testsuite/gcc.test-framework/dg-dot-run-sif-exp-P.c | 2 +- gcc/testsuite/gcc.test-framework/dg-dot-run-sif-exp-U.c | 2 +- gcc/testsuite/gcc.test-framework/dg-dot-run-xif-exp-P.c | 2 +- gcc/testsuite/gcc.test-framework/dg-dot-run-xif-exp-XP.c | 2 +- gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-F.c | 2 +- gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-P.c | 2 +- gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-XF.c | 2 +- gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-XP.c | 2 +- gcc/testsuite/gcc.test-framework/dg-nocache-sif-exp-P.c | 2 +- gcc/testsuite/gcc.test-framework/dg-nocache-sif-exp-U.c | 2 +- gcc/testsuite/gcc.test-framework/dg-nocache-xif-exp-P.c | 2 +- gcc/testsuite/gcc.test-framework/dg-nocache-xif-exp-XP.c | 2 +- gcc/testsuite/gcc.test-framework/gen_directive_tests | 8 ++++---- gcc/testsuite/gfortran.dg/char4_iunit_1.f03 | 2 +- gcc/testsuite/gfortran.dg/debug/pr35154-stabs.f | 2 +- gcc/testsuite/gfortran.dg/guality/pr41558.f90 | 2 +- gcc/testsuite/gfortran.dg/implicit_class_1.f90 | 2 +- gcc/testsuite/gfortran.dg/init_flag_10.f90 | 2 +- gcc/testsuite/gfortran.dg/init_flag_3.f90 | 2 +- gcc/testsuite/gfortran.dg/int_conv_2.f90 | 2 +- gcc/testsuite/gfortran.dg/isnan_1.f90 | 2 +- gcc/testsuite/gfortran.dg/isnan_2.f90 | 2 +- gcc/testsuite/gfortran.dg/large_real_kind_2.F90 | 2 +- gcc/testsuite/gfortran.dg/maxloc_2.f90 | 2 +- gcc/testsuite/gfortran.dg/maxlocval_2.f90 | 2 +- gcc/testsuite/gfortran.dg/maxlocval_4.f90 | 2 +- gcc/testsuite/gfortran.dg/minloc_1.f90 | 2 +- gcc/testsuite/gfortran.dg/minlocval_1.f90 | 2 +- gcc/testsuite/gfortran.dg/minlocval_4.f90 | 2 +- gcc/testsuite/gfortran.dg/module_nan.f90 | 2 +- gcc/testsuite/gfortran.dg/namelist_42.f90 | 2 +- gcc/testsuite/gfortran.dg/namelist_43.f90 | 2 +- gcc/testsuite/gfortran.dg/nan_1.f90 | 2 +- gcc/testsuite/gfortran.dg/nan_2.f90 | 2 +- gcc/testsuite/gfortran.dg/nan_3.f90 | 2 +- gcc/testsuite/gfortran.dg/nan_4.f90 | 2 +- gcc/testsuite/gfortran.dg/nan_5.f90 | 2 +- gcc/testsuite/gfortran.dg/nan_6.f90 | 2 +- gcc/testsuite/gfortran.dg/nan_7.f90 | 2 +- gcc/testsuite/gfortran.dg/nearest_1.f90 | 2 +- gcc/testsuite/gfortran.dg/nearest_3.f90 | 2 +- gcc/testsuite/gfortran.dg/pr20257.f90 | 2 +- gcc/testsuite/gfortran.dg/pr47614.f | 2 +- gcc/testsuite/gfortran.dg/read_infnan_1.f90 | 2 +- gcc/testsuite/gfortran.dg/real_const_3.f90 | 2 +- gcc/testsuite/gfortran.dg/realloc_on_assign_2.f03 | 2 +- gcc/testsuite/gfortran.dg/scratch_1.f90 | 2 +- gcc/testsuite/gfortran.dg/stat_1.f90 | 2 +- gcc/testsuite/gfortran.dg/stat_2.f90 | 2 +- gcc/testsuite/gfortran.dg/transfer_simplify_1.f90 | 2 +- gcc/testsuite/gfortran.dg/typebound_operator_9.f03 | 2 +- gcc/testsuite/gfortran.dg/vect/fast-math-pr38968.f90 | 2 +- gcc/testsuite/gnat.dg/debug7.adb | 2 +- gcc/testsuite/gnat.dg/debug9.adb | 2 +- gcc/testsuite/obj-c++.dg/dwarf-2.mm | 2 +- gcc/testsuite/obj-c++.dg/lto/trivial-1_0.mm | 2 +- gcc/testsuite/obj-c++.dg/tls/static-1a.mm | 2 +- gcc/testsuite/objc.dg/dwarf-1.m | 2 +- gcc/testsuite/objc.dg/dwarf-2.m | 2 +- gcc/testsuite/objc.dg/lto/trivial-1_0.m | 2 +- 653 files changed, 735 insertions(+), 731 deletions(-) mode change 100755 => 100644 gcc/testsuite/gcc.test-framework/gen_directive_tests (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index be06b90..ea83e35 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-17 Rainer Orth + + Remove dg-skip-if, dg-xfail-if, dg-xfail-run-if default args. + 2017-06-16 Carl Love * gcc.target/powerpc/builtins-3-runnable.c (test_result_sp, diff --git a/gcc/testsuite/c-c++-common/Wconversion-real.c b/gcc/testsuite/c-c++-common/Wconversion-real.c index 464aab0..4b961ff 100644 --- a/gcc/testsuite/c-c++-common/Wconversion-real.c +++ b/gcc/testsuite/c-c++-common/Wconversion-real.c @@ -1,7 +1,7 @@ /* Test for diagnostics for Wconversion for floating-point. */ /* { dg-do compile } */ -/* { dg-skip-if "doubles are floats" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "doubles are floats" { "avr-*-*" } } */ /* { dg-options "-std=c99 -Wconversion" { target c } } */ /* { dg-options "-Wconversion" { target c++ } } */ /* { dg-require-effective-target large_double } */ diff --git a/gcc/testsuite/c-c++-common/dfp/convert-bfp-11.c b/gcc/testsuite/c-c++-common/dfp/convert-bfp-11.c index d16919f..95c433d 100644 --- a/gcc/testsuite/c-c++-common/dfp/convert-bfp-11.c +++ b/gcc/testsuite/c-c++-common/dfp/convert-bfp-11.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { ! "powerpc*-*-linux*" } { "*" } { "" } } */ +/* { dg-skip-if "" { ! "powerpc*-*-linux*" } } */ /* Test decimal float conversions to and from IBM 128-bit long double. Checks are skipped at runtime if long double is not 128 bits. diff --git a/gcc/testsuite/c-c++-common/dfp/convert-bfp-6.c b/gcc/testsuite/c-c++-common/dfp/convert-bfp-6.c index 64198a9..e133f3b 100644 --- a/gcc/testsuite/c-c++-common/dfp/convert-bfp-6.c +++ b/gcc/testsuite/c-c++-common/dfp/convert-bfp-6.c @@ -1,4 +1,4 @@ -/* { dg-xfail-run-if "" { lax_strtofp } "*" "" } */ +/* { dg-xfail-run-if "" { lax_strtofp } } */ /* { dg-options "-w" } */ /* This test assumes IEEE float and double. */ diff --git a/gcc/testsuite/c-c++-common/dfp/convert-bfp-9.c b/gcc/testsuite/c-c++-common/dfp/convert-bfp-9.c index e609087..87d502a 100644 --- a/gcc/testsuite/c-c++-common/dfp/convert-bfp-9.c +++ b/gcc/testsuite/c-c++-common/dfp/convert-bfp-9.c @@ -1,4 +1,4 @@ -/* { dg-xfail-run-if "" { lax_strtofp } "*" "" } */ +/* { dg-xfail-run-if "" { lax_strtofp } } */ /* { dg-options "-w" } */ /* This test assumes IEEE float and double. */ diff --git a/gcc/testsuite/c-c++-common/pr41779.c b/gcc/testsuite/c-c++-common/pr41779.c index 25b0b68..c42a0f5 100644 --- a/gcc/testsuite/c-c++-common/pr41779.c +++ b/gcc/testsuite/c-c++-common/pr41779.c @@ -1,6 +1,6 @@ /* PR41779: Wconversion cannot see through real*integer promotions. */ /* { dg-do compile } */ -/* { dg-skip-if "doubles are floats" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "doubles are floats" { "avr-*-*" } } */ /* { dg-options "-std=c99 -Wconversion" { target c } } */ /* { dg-options "-Wconversion" { target c++ } } */ /* { dg-require-effective-target large_double } */ diff --git a/gcc/testsuite/c-c++-common/pr54486.c b/gcc/testsuite/c-c++-common/pr54486.c index b4bcf3b..8c311f8 100644 --- a/gcc/testsuite/c-c++-common/pr54486.c +++ b/gcc/testsuite/c-c++-common/pr54486.c @@ -1,7 +1,7 @@ /* PR middle-end/54486 */ /* { dg-do compile } */ /* { dg-options "-Wformat" } */ -/* { dg-skip-if "no POSIX printf" { *-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "no POSIX printf" { *-*-mingw* } } */ #ifdef __cplusplus extern "C" { diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C index 0316bcb..0cc7d3e 100644 --- a/gcc/testsuite/g++.dg/abi/rtti3.C +++ b/gcc/testsuite/g++.dg/abi/rtti3.C @@ -2,7 +2,7 @@ // necessarily the type info object // { dg-require-weak "" } -// { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } } +// { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } // { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } } // { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } } diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C index fa5fbd4..6e8f124 100644 --- a/gcc/testsuite/g++.dg/abi/thunk4.C +++ b/gcc/testsuite/g++.dg/abi/thunk4.C @@ -1,5 +1,5 @@ // { dg-require-weak "" } -// { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } } +// { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } // { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } diff --git a/gcc/testsuite/g++.dg/cpp0x/cast.C b/gcc/testsuite/g++.dg/cpp0x/cast.C index d11d724..75ab0e8 100644 --- a/gcc/testsuite/g++.dg/cpp0x/cast.C +++ b/gcc/testsuite/g++.dg/cpp0x/cast.C @@ -3,7 +3,7 @@ // Test cast from lvalue to rvalue // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one" { "epiphany-*-*" } } template struct sa; template <> struct sa {}; diff --git a/gcc/testsuite/g++.dg/cpp0x/iop.C b/gcc/testsuite/g++.dg/cpp0x/iop.C index 0a78be9..6e71ce0 100644 --- a/gcc/testsuite/g++.dg/cpp0x/iop.C +++ b/gcc/testsuite/g++.dg/cpp0x/iop.C @@ -7,7 +7,7 @@ // section "Revision 1 Summary and Rationale" for more details. // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one" { "epiphany-*-*" } } template struct sa; template <> struct sa {}; diff --git a/gcc/testsuite/g++.dg/cpp0x/named_refs.C b/gcc/testsuite/g++.dg/cpp0x/named_refs.C index 850179c..5139b1a 100644 --- a/gcc/testsuite/g++.dg/cpp0x/named_refs.C +++ b/gcc/testsuite/g++.dg/cpp0x/named_refs.C @@ -3,7 +3,7 @@ // Test: Named rvalue references are treated as lvalues. // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one" { "epiphany-*-*" } } template struct sa; template <> struct sa {}; diff --git a/gcc/testsuite/g++.dg/cpp0x/rv1p.C b/gcc/testsuite/g++.dg/cpp0x/rv1p.C index e87ec0e..a909727 100644 --- a/gcc/testsuite/g++.dg/cpp0x/rv1p.C +++ b/gcc/testsuite/g++.dg/cpp0x/rv1p.C @@ -3,7 +3,7 @@ // Test overload resolution among reference types // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } } // { dg-additional-options "-fno-ipa-icf" } template struct sa; diff --git a/gcc/testsuite/g++.dg/cpp0x/rv2p.C b/gcc/testsuite/g++.dg/cpp0x/rv2p.C index fb3019f..25a42ba 100644 --- a/gcc/testsuite/g++.dg/cpp0x/rv2p.C +++ b/gcc/testsuite/g++.dg/cpp0x/rv2p.C @@ -3,7 +3,7 @@ // Test overload resolution among reference types // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } } template struct sa; template <> struct sa {}; diff --git a/gcc/testsuite/g++.dg/cpp0x/rv3p.C b/gcc/testsuite/g++.dg/cpp0x/rv3p.C index 6d4625a..2d7d78d 100644 --- a/gcc/testsuite/g++.dg/cpp0x/rv3p.C +++ b/gcc/testsuite/g++.dg/cpp0x/rv3p.C @@ -3,7 +3,7 @@ // Test overload resolution among reference types // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } } template struct sa; template <> struct sa {}; diff --git a/gcc/testsuite/g++.dg/cpp0x/rv4p.C b/gcc/testsuite/g++.dg/cpp0x/rv4p.C index 8d720c7..0e4903b 100644 --- a/gcc/testsuite/g++.dg/cpp0x/rv4p.C +++ b/gcc/testsuite/g++.dg/cpp0x/rv4p.C @@ -3,7 +3,7 @@ // Test overload resolution among reference types // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } } template struct sa; template <> struct sa {}; diff --git a/gcc/testsuite/g++.dg/cpp0x/rv5p.C b/gcc/testsuite/g++.dg/cpp0x/rv5p.C index 7030277..63441a3 100644 --- a/gcc/testsuite/g++.dg/cpp0x/rv5p.C +++ b/gcc/testsuite/g++.dg/cpp0x/rv5p.C @@ -3,7 +3,7 @@ // Test overload resolution among reference types // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } } template struct sa; template <> struct sa {}; diff --git a/gcc/testsuite/g++.dg/cpp0x/rv6p.C b/gcc/testsuite/g++.dg/cpp0x/rv6p.C index 4be8343..26714f0 100644 --- a/gcc/testsuite/g++.dg/cpp0x/rv6p.C +++ b/gcc/testsuite/g++.dg/cpp0x/rv6p.C @@ -3,7 +3,7 @@ // Test overload resolution among reference types // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } } template struct sa; template <> struct sa {}; diff --git a/gcc/testsuite/g++.dg/cpp0x/rv7p.C b/gcc/testsuite/g++.dg/cpp0x/rv7p.C index 55fc5d7..60a3583 100644 --- a/gcc/testsuite/g++.dg/cpp0x/rv7p.C +++ b/gcc/testsuite/g++.dg/cpp0x/rv7p.C @@ -3,7 +3,7 @@ // Test overload resolution among reference types // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } } template struct sa; template <> struct sa {}; diff --git a/gcc/testsuite/g++.dg/cpp0x/rv8p.C b/gcc/testsuite/g++.dg/cpp0x/rv8p.C index 4424793..e12da4b 100644 --- a/gcc/testsuite/g++.dg/cpp0x/rv8p.C +++ b/gcc/testsuite/g++.dg/cpp0x/rv8p.C @@ -3,7 +3,7 @@ // Test overload resolution among reference types // { dg-do compile { target c++11 } } -// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct one/three/five/seven" { "epiphany-*-*" } } template struct sa; template <> struct sa {}; diff --git a/gcc/testsuite/g++.dg/debug/dwarf2/pr61433.C b/gcc/testsuite/g++.dg/debug/dwarf2/pr61433.C index 221727c..a217d96 100644 --- a/gcc/testsuite/g++.dg/debug/dwarf2/pr61433.C +++ b/gcc/testsuite/g++.dg/debug/dwarf2/pr61433.C @@ -1,6 +1,6 @@ // PR c++/61433 // { dg-do compile { target c++11 } } -// { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } +// { dg-xfail-if "" { powerpc-ibm-aix* } } // { dg-options "-O -fcompare-debug -fno-inline -fno-ipa-pure-const -fipa-sra" } template diff --git a/gcc/testsuite/g++.dg/debug/dwarf2/pubnames-2.C b/gcc/testsuite/g++.dg/debug/dwarf2/pubnames-2.C index bf94707..af0f6f1 100644 --- a/gcc/testsuite/g++.dg/debug/dwarf2/pubnames-2.C +++ b/gcc/testsuite/g++.dg/debug/dwarf2/pubnames-2.C @@ -1,5 +1,5 @@ // { dg-do compile { target c++11 } } -// { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } +// { dg-skip-if "" { powerpc-ibm-aix* } } // { dg-options "-gpubnames -gdwarf-4 -fno-debug-types-section -dA" } // { dg-final { scan-assembler-times "\.section\[\t \]\[^\n\]*debug_pubnames" 1 } } // { dg-final { scan-assembler "\"\\(anonymous namespace\\)\\\\0\"+\[ \t\]+\[#;/|@!]+\[ \t\]+external name" } } diff --git a/gcc/testsuite/g++.dg/debug/dwarf2/pubnames-3.C b/gcc/testsuite/g++.dg/debug/dwarf2/pubnames-3.C index 6ea8cbb..63b870b 100644 --- a/gcc/testsuite/g++.dg/debug/dwarf2/pubnames-3.C +++ b/gcc/testsuite/g++.dg/debug/dwarf2/pubnames-3.C @@ -1,5 +1,5 @@ // { dg-do compile { target c++11 } } -// { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } +// { dg-skip-if "" { powerpc-ibm-aix* } } // { dg-options "-gpubnames -gdwarf-4 -fdebug-types-section -dA" } // { dg-final { scan-assembler-times "\.section\[\t \]\[^\n\]*debug_pubnames" 1 } } // { dg-final { scan-assembler "\"\\(anonymous namespace\\)\\\\0\"+\[ \t\]+\[#;/|@!]+\[ \t\]+external name" } } diff --git a/gcc/testsuite/g++.dg/debug/pr46583.C b/gcc/testsuite/g++.dg/debug/pr46583.C index 06160b1..04b1fbf 100644 --- a/gcc/testsuite/g++.dg/debug/pr46583.C +++ b/gcc/testsuite/g++.dg/debug/pr46583.C @@ -1,7 +1,7 @@ // PR debug/46583 // { dg-do compile } // { dg-options "-O -fno-inline -fipa-cp -fipa-cp-clone -fcompare-debug" } -// { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } +// { dg-xfail-if "" { powerpc-ibm-aix* } } template < typename = unsigned long >struct A { diff --git a/gcc/testsuite/g++.dg/debug/pr47106.C b/gcc/testsuite/g++.dg/debug/pr47106.C index 9ef276a..d8d414d 100644 --- a/gcc/testsuite/g++.dg/debug/pr47106.C +++ b/gcc/testsuite/g++.dg/debug/pr47106.C @@ -1,7 +1,7 @@ // { dg-do compile } // { dg-options "-O -fpartial-inlining -flto -fconserve-stack -fcompare-debug" } // { dg-require-effective-target lto } -// { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } +// { dg-xfail-if "" { powerpc-ibm-aix* } } void end (int, int) __attribute__ ((__noreturn__)); diff --git a/gcc/testsuite/g++.dg/debug/pr56294.C b/gcc/testsuite/g++.dg/debug/pr56294.C index a9ee807..301fcb1 100644 --- a/gcc/testsuite/g++.dg/debug/pr56294.C +++ b/gcc/testsuite/g++.dg/debug/pr56294.C @@ -1,6 +1,6 @@ // { dg-do compile } // { dg-options "-fno-ipa-sra -fcompare-debug" } -// { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } +// { dg-xfail-if "" { powerpc-ibm-aix* } } struct comp_cost { int cost; unsigned complexity; }; struct cost_pair { struct iv_cand *cand; }; diff --git a/gcc/testsuite/g++.dg/debug/pr56819.C b/gcc/testsuite/g++.dg/debug/pr56819.C index bc61cb7..4aa86b0 100644 --- a/gcc/testsuite/g++.dg/debug/pr56819.C +++ b/gcc/testsuite/g++.dg/debug/pr56819.C @@ -1,7 +1,7 @@ // PR debug/56819 // { dg-do compile } // { dg-options "-fcompare-debug" } -// { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } +// { dg-xfail-if "" { powerpc-ibm-aix* } } template struct A diff --git a/gcc/testsuite/g++.dg/debug/pr71432.C b/gcc/testsuite/g++.dg/debug/pr71432.C index 14e5a38b..1682f12 100644 --- a/gcc/testsuite/g++.dg/debug/pr71432.C +++ b/gcc/testsuite/g++.dg/debug/pr71432.C @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ namespace std { diff --git a/gcc/testsuite/g++.dg/eh/spbp.C b/gcc/testsuite/g++.dg/eh/spbp.C index 181e65d..2440605 100644 --- a/gcc/testsuite/g++.dg/eh/spbp.C +++ b/gcc/testsuite/g++.dg/eh/spbp.C @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-options "-gdwarf-2" } */ -/* { dg-skip-if "No Dwarf" { { *-*-aix* hppa*-*-hpux* } && { ! hppa*64*-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "No Dwarf" { { *-*-aix* hppa*-*-hpux* } && { ! hppa*64*-*-* } } } */ /* This was a bug on x86-darwin, where the register numbering for SP and BP was swapped (it's easy to do because on that port it's diff --git a/gcc/testsuite/g++.dg/ext/alignof2.C b/gcc/testsuite/g++.dg/ext/alignof2.C index 912863e..2217590 100644 --- a/gcc/testsuite/g++.dg/ext/alignof2.C +++ b/gcc/testsuite/g++.dg/ext/alignof2.C @@ -3,7 +3,7 @@ // wrong for some fields. // { dg-do run } -// { dg-xfail-run-if "AIX ABI increases struct alignment for first member double" { powerpc-ibm-aix* } { "*" } { "" } } +// { dg-xfail-run-if "AIX ABI increases struct alignment for first member double" { powerpc-ibm-aix* } } extern "C" void abort(); diff --git a/gcc/testsuite/g++.dg/ext/cleanup-5.C b/gcc/testsuite/g++.dg/ext/cleanup-5.C index db4c2bb..167f01a 100644 --- a/gcc/testsuite/g++.dg/ext/cleanup-5.C +++ b/gcc/testsuite/g++.dg/ext/cleanup-5.C @@ -1,7 +1,7 @@ /* HP-UX libunwind.so doesn't provide _UA_END_OF_STACK */ /* { dg-do run } */ /* { dg-options "-fexceptions" } */ -/* { dg-skip-if "" { "ia64-*-hpux11.*" } { "*" } { "" } } */ +/* { dg-skip-if "" { "ia64-*-hpux11.*" } } */ /* Verify that cleanups work with exception handling. */ #include diff --git a/gcc/testsuite/g++.dg/ext/spe1.C b/gcc/testsuite/g++.dg/ext/spe1.C index 8b1e630..b98d4b2 100644 --- a/gcc/testsuite/g++.dg/ext/spe1.C +++ b/gcc/testsuite/g++.dg/ext/spe1.C @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ typedef int v2si __attribute__ ((vector_size (8))); diff --git a/gcc/testsuite/g++.dg/ext/strncpy-chk1.C b/gcc/testsuite/g++.dg/ext/strncpy-chk1.C index ff591a0..b94c3bd 100644 --- a/gcc/testsuite/g++.dg/ext/strncpy-chk1.C +++ b/gcc/testsuite/g++.dg/ext/strncpy-chk1.C @@ -1,7 +1,7 @@ // PR c++/40502 // { dg-do compile } // { dg-options "-O2" } -// { dg-skip-if "packed attribute missing for struct A" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for struct A" { "epiphany-*-*" } } struct A { char x[12], y[35]; }; struct B { char z[50]; }; diff --git a/gcc/testsuite/g++.dg/ext/visibility/class1.C b/gcc/testsuite/g++.dg/ext/visibility/class1.C index 792fc78..c9a1d26 100644 --- a/gcc/testsuite/g++.dg/ext/visibility/class1.C +++ b/gcc/testsuite/g++.dg/ext/visibility/class1.C @@ -3,7 +3,7 @@ // { dg-options "-fpic" } // { dg-do compile { target i?86-*-* x86_64-*-* } } -// { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } +// { dg-skip-if "" { *-*-darwin* } } // { dg-require-visibility "" } // { dg-require-effective-target fpic } // { dg-final { scan-assembler "InitEv@PLT" } } diff --git a/gcc/testsuite/g++.dg/lto/20100302_0.C b/gcc/testsuite/g++.dg/lto/20100302_0.C index 0551e6e..a9fb5c7 100644 --- a/gcc/testsuite/g++.dg/lto/20100302_0.C +++ b/gcc/testsuite/g++.dg/lto/20100302_0.C @@ -1,5 +1,5 @@ // Test for ABI forward-compatibility aliases with LTO. -// { dg-skip-if "" { { ! { i?86-*-* x86_64-*-* } } || { *-*-darwin* } } { "*" } { "" } } +// { dg-skip-if "" { { ! { i?86-*-* x86_64-*-* } } || { *-*-darwin* } } } // { dg-lto-options {"-flto -fabi-version=2"} } #include "20100302.h" diff --git a/gcc/testsuite/g++.dg/opt/pr60002.C b/gcc/testsuite/g++.dg/opt/pr60002.C index 8a17995..ceba0b7 100644 --- a/gcc/testsuite/g++.dg/opt/pr60002.C +++ b/gcc/testsuite/g++.dg/opt/pr60002.C @@ -1,7 +1,7 @@ // PR tree-optimization/60002 // { dg-do compile } // { dg-options "-O2 -fcompare-debug -fdeclone-ctor-dtor -fipa-cp-clone" } -// { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } +// { dg-xfail-if "" { powerpc-ibm-aix* } } struct A {}; diff --git a/gcc/testsuite/g++.dg/opt/vt1.C b/gcc/testsuite/g++.dg/opt/vt1.C index ba871fb..1b08718 100644 --- a/gcc/testsuite/g++.dg/opt/vt1.C +++ b/gcc/testsuite/g++.dg/opt/vt1.C @@ -1,8 +1,8 @@ // Test whether vtable for S is not put into read-only section. // { dg-do compile { target fpic } } // { dg-options "-O2 -fpic -fno-rtti" } -// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } { "*" } { "" } } -// { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } { "*" } { "" } } +// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } } +// { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } } // Origin: Jakub Jelinek struct S diff --git a/gcc/testsuite/g++.dg/other/opaque-1.C b/gcc/testsuite/g++.dg/other/opaque-1.C index 5cdaeaf..669776b 100644 --- a/gcc/testsuite/g++.dg/other/opaque-1.C +++ b/gcc/testsuite/g++.dg/other/opaque-1.C @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ #define __vector __attribute__((vector_size(8))) typedef float __vector __ev64_fs__; diff --git a/gcc/testsuite/g++.dg/other/opaque-2.C b/gcc/testsuite/g++.dg/other/opaque-2.C index 3bb4af2..414f87e 100644 --- a/gcc/testsuite/g++.dg/other/opaque-2.C +++ b/gcc/testsuite/g++.dg/other/opaque-2.C @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ #define __vector __attribute__((vector_size(8))) typedef float __vector __ev64_fs__; diff --git a/gcc/testsuite/g++.dg/other/opaque-3.C b/gcc/testsuite/g++.dg/other/opaque-3.C index 5ece652..f915f84 100644 --- a/gcc/testsuite/g++.dg/other/opaque-3.C +++ b/gcc/testsuite/g++.dg/other/opaque-3.C @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ __ev64_opaque__ o; #define v __attribute__((vector_size(8))) diff --git a/gcc/testsuite/g++.dg/other/pr42685.C b/gcc/testsuite/g++.dg/other/pr42685.C index 3c55955..dd070c4 100644 --- a/gcc/testsuite/g++.dg/other/pr42685.C +++ b/gcc/testsuite/g++.dg/other/pr42685.C @@ -1,6 +1,6 @@ // { dg-do compile } // { dg-options "-O -funroll-loops -fcompare-debug" } -// { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } +// { dg-xfail-if "" { powerpc-ibm-aix* } } void Remap(int n, int *src, int *dst, int *map) { diff --git a/gcc/testsuite/g++.dg/other/ucnid-1.C b/gcc/testsuite/g++.dg/other/ucnid-1.C index 95a31cb..954f34d 100644 --- a/gcc/testsuite/g++.dg/other/ucnid-1.C +++ b/gcc/testsuite/g++.dg/other/ucnid-1.C @@ -1,7 +1,7 @@ /* { dg-do run } */ /* { dg-options "" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ -/* { dg-skip-if "" { ! ucn } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ +/* { dg-skip-if "" { ! ucn } } */ #include int \u00C0(void) { return 1; } diff --git a/gcc/testsuite/g++.dg/other/unused1.C b/gcc/testsuite/g++.dg/other/unused1.C index b28d698..15e8a541 100644 --- a/gcc/testsuite/g++.dg/other/unused1.C +++ b/gcc/testsuite/g++.dg/other/unused1.C @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-g" } */ -/* { dg-skip-if "" { { hppa*-*-hpux* *-*-solaris2.[56]* powerpc-ibm-aix* } && { ! hppa*64*-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "" { { hppa*-*-hpux* *-*-solaris2.[56]* powerpc-ibm-aix* } && { ! hppa*64*-*-* } } } */ /* Make sure we didn't eliminate casted types because we thought they were unused. */ diff --git a/gcc/testsuite/g++.dg/pr65240-1.C b/gcc/testsuite/g++.dg/pr65240-1.C index 3282b8e..837da2d 100644 --- a/gcc/testsuite/g++.dg/pr65240-1.C +++ b/gcc/testsuite/g++.dg/pr65240-1.C @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3 -ffast-math -mcmodel=small -mno-fp-in-toc" } */ diff --git a/gcc/testsuite/g++.dg/pr65240-2.C b/gcc/testsuite/g++.dg/pr65240-2.C index 80cb82f..19712b2 100644 --- a/gcc/testsuite/g++.dg/pr65240-2.C +++ b/gcc/testsuite/g++.dg/pr65240-2.C @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3 -ffast-math -mcmodel=small -mfp-in-toc" } */ diff --git a/gcc/testsuite/g++.dg/pr65240-3.C b/gcc/testsuite/g++.dg/pr65240-3.C index 57f0b80..bafde4c 100644 --- a/gcc/testsuite/g++.dg/pr65240-3.C +++ b/gcc/testsuite/g++.dg/pr65240-3.C @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3 -ffast-math -mcmodel=medium" } */ diff --git a/gcc/testsuite/g++.dg/pr65240-4.C b/gcc/testsuite/g++.dg/pr65240-4.C index b6a1007..82c406f 100644 --- a/gcc/testsuite/g++.dg/pr65240-4.C +++ b/gcc/testsuite/g++.dg/pr65240-4.C @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O3 -ffast-math" } */ diff --git a/gcc/testsuite/g++.dg/pr65242.C b/gcc/testsuite/g++.dg/pr65242.C index c123056..be2ddaa 100644 --- a/gcc/testsuite/g++.dg/pr65242.C +++ b/gcc/testsuite/g++.dg/pr65242.C @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3" } */ diff --git a/gcc/testsuite/g++.dg/pr67211.C b/gcc/testsuite/g++.dg/pr67211.C index 4afc69f..cb3d342 100644 --- a/gcc/testsuite/g++.dg/pr67211.C +++ b/gcc/testsuite/g++.dg/pr67211.C @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -mtune=power8 -O3 -w" } */ diff --git a/gcc/testsuite/g++.dg/pr69667.C b/gcc/testsuite/g++.dg/pr69667.C index df44562..2b3e93d 100644 --- a/gcc/testsuite/g++.dg/pr69667.C +++ b/gcc/testsuite/g++.dg/pr69667.C @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power8 -w -std=c++14 -mlra" } */ diff --git a/gcc/testsuite/g++.dg/pr78112-2.C b/gcc/testsuite/g++.dg/pr78112-2.C index 7ffaee8..c174bd3 100644 --- a/gcc/testsuite/g++.dg/pr78112-2.C +++ b/gcc/testsuite/g++.dg/pr78112-2.C @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "No dwarf debug support" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "No dwarf debug support" { hppa*-*-hpux* } } */ /* { dg-options "-g -dA -gdwarf-4 -std=gnu++11" } */ /* { dg-options "-g -dA -std=gnu++11 -gdwarf-4" } */ /* { dg-final { scan-assembler-times DW_AT_object_pointer 18 } } */ diff --git a/gcc/testsuite/g++.dg/torture/pr31863.C b/gcc/testsuite/g++.dg/torture/pr31863.C index f10ad5f..646178a 100644 --- a/gcc/testsuite/g++.dg/torture/pr31863.C +++ b/gcc/testsuite/g++.dg/torture/pr31863.C @@ -1,6 +1,6 @@ /* { dg-do link } */ /* { dg-timeout-factor 2.0 } */ -/* { dg-skip-if "Program too big" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "Program too big" { "avr-*-*" } } */ namespace Loki { diff --git a/gcc/testsuite/g++.dg/torture/stackalign/eh-alloca-1.C b/gcc/testsuite/g++.dg/torture/stackalign/eh-alloca-1.C index 7c124fe..ea181ae 100644 --- a/gcc/testsuite/g++.dg/torture/stackalign/eh-alloca-1.C +++ b/gcc/testsuite/g++.dg/torture/stackalign/eh-alloca-1.C @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ #include "check.h" diff --git a/gcc/testsuite/g++.dg/torture/stackalign/eh-global-1.C b/gcc/testsuite/g++.dg/torture/stackalign/eh-global-1.C index 48a59eb..609c0c9 100644 --- a/gcc/testsuite/g++.dg/torture/stackalign/eh-global-1.C +++ b/gcc/testsuite/g++.dg/torture/stackalign/eh-global-1.C @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ #include "check.h" diff --git a/gcc/testsuite/g++.dg/torture/stackalign/eh-inline-1.C b/gcc/testsuite/g++.dg/torture/stackalign/eh-inline-1.C index b8c04d9..b56f7c8 100644 --- a/gcc/testsuite/g++.dg/torture/stackalign/eh-inline-1.C +++ b/gcc/testsuite/g++.dg/torture/stackalign/eh-inline-1.C @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ #include "check.h" diff --git a/gcc/testsuite/g++.dg/torture/stackalign/eh-inline-2.C b/gcc/testsuite/g++.dg/torture/stackalign/eh-inline-2.C index 53ff0cc..b535f1c 100644 --- a/gcc/testsuite/g++.dg/torture/stackalign/eh-inline-2.C +++ b/gcc/testsuite/g++.dg/torture/stackalign/eh-inline-2.C @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ #include "check.h" diff --git a/gcc/testsuite/g++.dg/torture/stackalign/eh-vararg-1.C b/gcc/testsuite/g++.dg/torture/stackalign/eh-vararg-1.C index 9c3c0f5..61da410 100644 --- a/gcc/testsuite/g++.dg/torture/stackalign/eh-vararg-1.C +++ b/gcc/testsuite/g++.dg/torture/stackalign/eh-vararg-1.C @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ #include #include "check.h" diff --git a/gcc/testsuite/g++.dg/torture/stackalign/eh-vararg-2.C b/gcc/testsuite/g++.dg/torture/stackalign/eh-vararg-2.C index aa9b2bd..8a5f029 100644 --- a/gcc/testsuite/g++.dg/torture/stackalign/eh-vararg-2.C +++ b/gcc/testsuite/g++.dg/torture/stackalign/eh-vararg-2.C @@ -1,6 +1,6 @@ /* { dg-options "-Wno-abi" {target arm_eabi} } */ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ #include #include "check.h" diff --git a/gcc/testsuite/g++.dg/torture/stackalign/throw-1.C b/gcc/testsuite/g++.dg/torture/stackalign/throw-1.C index 3eddc1d..bce29e3 100644 --- a/gcc/testsuite/g++.dg/torture/stackalign/throw-1.C +++ b/gcc/testsuite/g++.dg/torture/stackalign/throw-1.C @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ #include "check.h" diff --git a/gcc/testsuite/g++.dg/torture/stackalign/throw-2.C b/gcc/testsuite/g++.dg/torture/stackalign/throw-2.C index 63a8c6e..0e0d37c 100644 --- a/gcc/testsuite/g++.dg/torture/stackalign/throw-2.C +++ b/gcc/testsuite/g++.dg/torture/stackalign/throw-2.C @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ #include "check.h" diff --git a/gcc/testsuite/g++.dg/torture/stackalign/throw-4.C b/gcc/testsuite/g++.dg/torture/stackalign/throw-4.C index 52e6f7f..77414f0 100644 --- a/gcc/testsuite/g++.dg/torture/stackalign/throw-4.C +++ b/gcc/testsuite/g++.dg/torture/stackalign/throw-4.C @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ #include "check.h" diff --git a/gcc/testsuite/g++.dg/warn/weak1.C b/gcc/testsuite/g++.dg/warn/weak1.C index 456e6f3..7af7e4c 100644 --- a/gcc/testsuite/g++.dg/warn/weak1.C +++ b/gcc/testsuite/g++.dg/warn/weak1.C @@ -1,10 +1,10 @@ // { dg-do run } // { dg-require-weak "" } // The PA HP-UX dynamic loader doesn't support unsatisfied weak symbols. -// { dg-skip-if "No unsat" { hppa*-*-hpux* } { "*" } { "" } } -// { dg-skip-if "No weak unsat" { *-*-aix* } { "*" } { "" } } +// { dg-skip-if "No unsat" { hppa*-*-hpux* } } +// { dg-skip-if "No weak unsat" { *-*-aix* } } // The darwin loader does, but they do need to exist at link time. -// { dg-skip-if "No link unsat" { *-*-darwin* } { "*" } { "" } } +// { dg-skip-if "No link unsat" { *-*-darwin* } } // For kernel modules and static RTPs, the loader treats undefined weak // symbols in the same way as undefined strong symbols. The test // therefore fails to load, so skip it. diff --git a/gcc/testsuite/g++.old-deja/g++.brendan/crash43.C b/gcc/testsuite/g++.old-deja/g++.brendan/crash43.C index 8c73d70..91cf681 100644 --- a/gcc/testsuite/g++.old-deja/g++.brendan/crash43.C +++ b/gcc/testsuite/g++.old-deja/g++.brendan/crash43.C @@ -1,5 +1,5 @@ // { dg-do assemble } -// { dg-xfail-if "" { sparc64-*-elf } { "*" } { "" } } +// { dg-xfail-if "" { sparc64-*-elf } } // { dg-options "-g" } // GROUPS passed old-abort extern "C" { typedef int jmp_buf[12]; } diff --git a/gcc/testsuite/g++.old-deja/g++.brendan/synth1.C b/gcc/testsuite/g++.old-deja/g++.brendan/synth1.C index 3a27e63..cd7bd23 100644 --- a/gcc/testsuite/g++.old-deja/g++.brendan/synth1.C +++ b/gcc/testsuite/g++.old-deja/g++.brendan/synth1.C @@ -1,5 +1,5 @@ // { dg-do assemble } -// { dg-xfail-if "" { sparc64-*-elf } { "*" } { "" } } +// { dg-xfail-if "" { sparc64-*-elf } } // { dg-options "-pedantic-errors -g -Wall" } // GROUPS passed synthetics // Check to make sure that g++ doesn't get freaked out about the use diff --git a/gcc/testsuite/g++.old-deja/g++.jason/thunk2.C b/gcc/testsuite/g++.old-deja/g++.jason/thunk2.C index 88e06d8..427ef7f 100644 --- a/gcc/testsuite/g++.old-deja/g++.jason/thunk2.C +++ b/gcc/testsuite/g++.old-deja/g++.jason/thunk2.C @@ -1,6 +1,6 @@ // { dg-do run { target fpic } } // { dg-options "-fPIC" } -// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } { "*" } { "" } } +// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } } // Test that non-variadic function calls using thunks and PIC work right. struct A { diff --git a/gcc/testsuite/g++.old-deja/g++.jason/thunk3.C b/gcc/testsuite/g++.old-deja/g++.jason/thunk3.C index 5ea46f5..3941727 100644 --- a/gcc/testsuite/g++.old-deja/g++.jason/thunk3.C +++ b/gcc/testsuite/g++.old-deja/g++.jason/thunk3.C @@ -1,5 +1,5 @@ // { dg-do run } -// { dg-skip-if "fails with generic thunk support" { rs6000-*-* powerpc-*-eabi v850-*-* sh-*-* h8*-*-* xtensa*-*-* m32r*-*-* lm32-*-* nios2-*-* } { "*" } { "" } } +// { dg-skip-if "fails with generic thunk support" { rs6000-*-* powerpc-*-eabi v850-*-* sh-*-* h8*-*-* xtensa*-*-* m32r*-*-* lm32-*-* nios2-*-* } } // Test that variadic function calls using thunks work right. // Note that this will break on any target that uses the generic thunk // support, because it doesn't support variadic functions. diff --git a/gcc/testsuite/g++.old-deja/g++.law/bit-fields2.C b/gcc/testsuite/g++.old-deja/g++.law/bit-fields2.C index 270fc8a..abf733f 100644 --- a/gcc/testsuite/g++.old-deja/g++.law/bit-fields2.C +++ b/gcc/testsuite/g++.old-deja/g++.law/bit-fields2.C @@ -16,7 +16,7 @@ // defined to no larger than the size of an unsigned int, or where // PCC_BITFIELD_TYPE_MATTERS is defined. Add skips below for targets that // do not have that property. -// { dg-skip-if "" { mmix-knuth-mmixware } { "*" } { "" } } +// { dg-skip-if "" { mmix-knuth-mmixware } } #include diff --git a/gcc/testsuite/g++.old-deja/g++.mike/eh46.C b/gcc/testsuite/g++.old-deja/g++.mike/eh46.C index 9785e6a..ab3e020 100644 --- a/gcc/testsuite/g++.old-deja/g++.mike/eh46.C +++ b/gcc/testsuite/g++.old-deja/g++.mike/eh46.C @@ -1,5 +1,5 @@ // { dg-do assemble } -// { dg-xfail-if "" { arm-*-pe } { "*" } { "" } } +// { dg-xfail-if "" { arm-*-pe } } // { dg-options "-fexceptions" } int atoi(const char *); diff --git a/gcc/testsuite/g++.old-deja/g++.mike/ns15.C b/gcc/testsuite/g++.old-deja/g++.mike/ns15.C index 4e767b8..7768f69 100644 --- a/gcc/testsuite/g++.old-deja/g++.mike/ns15.C +++ b/gcc/testsuite/g++.old-deja/g++.mike/ns15.C @@ -1,5 +1,5 @@ // { dg-do assemble } -// { dg-xfail-if "" { xstormy16-*-* } { "*" } { "" } } +// { dg-xfail-if "" { xstormy16-*-* } } #include #include diff --git a/gcc/testsuite/g++.old-deja/g++.mike/p10416.C b/gcc/testsuite/g++.old-deja/g++.mike/p10416.C index 766a27b..f95056c 100644 --- a/gcc/testsuite/g++.old-deja/g++.mike/p10416.C +++ b/gcc/testsuite/g++.old-deja/g++.mike/p10416.C @@ -1,5 +1,5 @@ // { dg-do assemble } -// { dg-xfail-if "" { sparc64-*-elf arm-*-pe } { "*" } { "" } } +// { dg-xfail-if "" { sparc64-*-elf arm-*-pe } } // { dg-options "-fexceptions" } // prms-id: 10416 diff --git a/gcc/testsuite/g++.old-deja/g++.other/comdat5.C b/gcc/testsuite/g++.old-deja/g++.other/comdat5.C index ad707f5..3336496 100644 --- a/gcc/testsuite/g++.old-deja/g++.other/comdat5.C +++ b/gcc/testsuite/g++.old-deja/g++.other/comdat5.C @@ -2,6 +2,6 @@ // { dg-do link { target fpic } } // { dg-additional-sources " comdat5-aux.cc" } // { dg-options "-O2 -fPIC" } -// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } { "*" } { "" } } +// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } } #include "comdat4.C" diff --git a/gcc/testsuite/g++.old-deja/g++.other/local-alloc1.C b/gcc/testsuite/g++.old-deja/g++.other/local-alloc1.C index 7488f19..d595d98 100644 --- a/gcc/testsuite/g++.old-deja/g++.other/local-alloc1.C +++ b/gcc/testsuite/g++.old-deja/g++.other/local-alloc1.C @@ -1,6 +1,6 @@ // { dg-do assemble { target fpic } } // { dg-options "-O0 -fpic" } -// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } { "*" } { "" } } +// { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } } // Origin: Jakub Jelinek struct bar { diff --git a/gcc/testsuite/g++.old-deja/g++.pt/asm1.C b/gcc/testsuite/g++.old-deja/g++.pt/asm1.C index 068a90f..28728bb 100644 --- a/gcc/testsuite/g++.old-deja/g++.pt/asm1.C +++ b/gcc/testsuite/g++.old-deja/g++.pt/asm1.C @@ -1,6 +1,6 @@ // { dg-do assemble { target i?86-*-linux* i?86-*-gnu* x86_64-*-linux* } } // We'd use ebx with 32-bit pic code, so skip. -// { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } +// { dg-skip-if "" { ilp32 && { ! nonpic } } } // Origin: "Weidmann, Nicholas" template int foo(int v) diff --git a/gcc/testsuite/g++.old-deja/g++.pt/crash16.C b/gcc/testsuite/g++.old-deja/g++.pt/crash16.C index aa25c22..30bd0cc 100644 --- a/gcc/testsuite/g++.old-deja/g++.pt/crash16.C +++ b/gcc/testsuite/g++.old-deja/g++.pt/crash16.C @@ -1,5 +1,5 @@ // { dg-do assemble } -// { dg-xfail-if "" { xstormy16-*-* } { "*" } { "" } } +// { dg-xfail-if "" { xstormy16-*-* } } // { dg-options "" } extern "C" void qsort(void *base, __SIZE_TYPE__ nmemb, __SIZE_TYPE__ size, diff --git a/gcc/testsuite/g++.old-deja/g++.pt/static6.C b/gcc/testsuite/g++.old-deja/g++.pt/static6.C index 3ff41fe..b292853 100644 --- a/gcc/testsuite/g++.old-deja/g++.pt/static6.C +++ b/gcc/testsuite/g++.old-deja/g++.pt/static6.C @@ -1,5 +1,5 @@ // { dg-do link } -// { dg-xfail-if "" { *-*-aout *-*-coff *-*-hms } { "*" } { "" } } +// { dg-xfail-if "" { *-*-aout *-*-coff *-*-hms } } // Simplified from testcase by Erez Louidor Lior diff --git a/gcc/testsuite/gcc.c-torture/compile/20000804-1.c b/gcc/testsuite/gcc.c-torture/compile/20000804-1.c index 38e42be..5c6b731 100644 --- a/gcc/testsuite/gcc.c-torture/compile/20000804-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/20000804-1.c @@ -1,10 +1,10 @@ /* This does not work on h8300 due to the use of an asm statement to force a 'long long' (64-bits) to go in a register. */ /* { dg-do assemble } */ -/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && { ia32 && { ! nonpic } } } { "*" } { "" } } */ -/* { dg-skip-if "No 64-bit registers" { m32c-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && { ia32 && { ! nonpic } } } } */ +/* { dg-skip-if "No 64-bit registers" { m32c-*-* } } */ /* { dg-skip-if "Not enough 64-bit registers" { pdp11-*-* } { "-O0" } { "" } } */ -/* { dg-xfail-if "" { h8300-*-* } { "*" } { "" } } */ +/* { dg-xfail-if "" { h8300-*-* } } */ /* Copyright (C) 2000, 2003 Free Software Foundation */ __complex__ long long f () diff --git a/gcc/testsuite/gcc.c-torture/compile/20001226-1.c b/gcc/testsuite/gcc.c-torture/compile/20001226-1.c index 687b43a..be0bdcf 100644 --- a/gcc/testsuite/gcc.c-torture/compile/20001226-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/20001226-1.c @@ -1,8 +1,8 @@ /* { dg-do assemble } */ -/* { dg-skip-if "too much code for avr" { "avr-*-*" } { "*" } { "" } } */ -/* { dg-skip-if "too much code for pdp11" { "pdp11-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "too much code for avr" { "avr-*-*" } } */ +/* { dg-skip-if "too much code for pdp11" { "pdp11-*-*" } } */ /* { dg-xfail-if "PR36698" { spu-*-* } { "-O0" } { "" } } */ -/* { dg-skip-if "" { m32c-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { m32c-*-* } } */ /* { dg-timeout-factor 4.0 } */ /* This testcase exposed two branch shortening bugs on powerpc. */ diff --git a/gcc/testsuite/gcc.c-torture/compile/20060208-1.c b/gcc/testsuite/gcc.c-torture/compile/20060208-1.c index 18724fb..3881474 100644 --- a/gcc/testsuite/gcc.c-torture/compile/20060208-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/20060208-1.c @@ -1,5 +1,5 @@ /* PR middle-end/26092 */ -/* { dg-skip-if "can't take address of malloc" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "can't take address of malloc" { nvptx-*-* } } */ typedef __SIZE_TYPE__ size_t; extern void *malloc (size_t); diff --git a/gcc/testsuite/gcc.c-torture/compile/20080721-1.c b/gcc/testsuite/gcc.c-torture/compile/20080721-1.c index 6ee9ed9..6c928f5 100644 --- a/gcc/testsuite/gcc.c-torture/compile/20080721-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/20080721-1.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "can't read function data" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "can't read function data" { nvptx-*-* } } */ void foo(void); void bar(void); diff --git a/gcc/testsuite/gcc.c-torture/compile/920520-1.c b/gcc/testsuite/gcc.c-torture/compile/920520-1.c index 7dce411..037102e 100644 --- a/gcc/testsuite/gcc.c-torture/compile/920520-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/920520-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { pdp11-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { pdp11-*-* } } */ f(){asm("%0"::"r"(1.5F));}g(){asm("%0"::"r"(1.5));} diff --git a/gcc/testsuite/gcc.c-torture/compile/980506-1.c b/gcc/testsuite/gcc.c-torture/compile/980506-1.c index 0f46e17..3653372 100644 --- a/gcc/testsuite/gcc.c-torture/compile/980506-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/980506-1.c @@ -1,7 +1,7 @@ /* The arrays are too large for the xstormy16 - won't fit in 16 bits. */ /* { dg-do assemble } */ /* { dg-require-effective-target size32plus } */ -/* { dg-skip-if "Array too big" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "Array too big" { "avr-*-*" } } */ /* { dg-xfail-if "The array too big" { h8300-*-* } { "-mno-h" "-mn" } { "" } } */ unsigned char TIFFFax2DMode[20][256]; diff --git a/gcc/testsuite/gcc.c-torture/compile/limits-externdecl.c b/gcc/testsuite/gcc.c-torture/compile/limits-externdecl.c index f131eea..c233849 100644 --- a/gcc/testsuite/gcc.c-torture/compile/limits-externdecl.c +++ b/gcc/testsuite/gcc.c-torture/compile/limits-externdecl.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "ptxas runs out of memory" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "ptxas runs out of memory" { nvptx-*-* } } */ /* { dg-require-effective-target int32plus } */ /* Inspired by the test case for PR middle-end/52640. */ diff --git a/gcc/testsuite/gcc.c-torture/compile/limits-fndefn.c b/gcc/testsuite/gcc.c-torture/compile/limits-fndefn.c index 228c5d9..0bd8f6a 100644 --- a/gcc/testsuite/gcc.c-torture/compile/limits-fndefn.c +++ b/gcc/testsuite/gcc.c-torture/compile/limits-fndefn.c @@ -1,5 +1,5 @@ -/* { dg-skip-if "too complex for avr" { avr-*-* } { "*" } { "" } } */ -/* { dg-skip-if "ptxas times out" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "too complex for avr" { avr-*-* } } */ +/* { dg-skip-if "ptxas times out" { nvptx-*-* } } */ /* { dg-timeout-factor 4.0 } */ #define LIM1(x) x##0, x##1, x##2, x##3, x##4, x##5, x##6, x##7, x##8, x##9, #define LIM2(x) LIM1(x##0) LIM1(x##1) LIM1(x##2) LIM1(x##3) LIM1(x##4) \ diff --git a/gcc/testsuite/gcc.c-torture/compile/limits-stringlit.c b/gcc/testsuite/gcc.c-torture/compile/limits-stringlit.c index 56188d8..0828fc3 100644 --- a/gcc/testsuite/gcc.c-torture/compile/limits-stringlit.c +++ b/gcc/testsuite/gcc.c-torture/compile/limits-stringlit.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "Array too big" { avr-*-* m32c-*-* pdp11-*-* msp430-*-* } { "*" } { "" } } */ +/* { dg-skip-if "Array too big" { avr-*-* m32c-*-* pdp11-*-* msp430-*-* } } */ #define STR2 "012345678901234567890123456789012345678901234567890123456789\ 0123456789012345678901234567890123456789" diff --git a/gcc/testsuite/gcc.c-torture/compile/pr35318.c b/gcc/testsuite/gcc.c-torture/compile/pr35318.c index 6837d2d..97a1c87 100644 --- a/gcc/testsuite/gcc.c-torture/compile/pr35318.c +++ b/gcc/testsuite/gcc.c-torture/compile/pr35318.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { pdp11-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { pdp11-*-* } } */ /* PR target/35318 */ void diff --git a/gcc/testsuite/gcc.c-torture/compile/pr41181.c b/gcc/testsuite/gcc.c-torture/compile/pr41181.c index e1e4806..f866249 100644 --- a/gcc/testsuite/gcc.c-torture/compile/pr41181.c +++ b/gcc/testsuite/gcc.c-torture/compile/pr41181.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target ptr32plus } */ -/* { dg-skip-if "The array is too big" { "avr-*-*" "pdp11-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "The array is too big" { "avr-*-*" "pdp11-*-*" } } */ char paths[1024]; static void x264_slicetype_path(char (*best_paths)[250], int n, int length) { diff --git a/gcc/testsuite/gcc.c-torture/compile/pr46534.c b/gcc/testsuite/gcc.c-torture/compile/pr46534.c index 8300ca7..885aa6d 100644 --- a/gcc/testsuite/gcc.c-torture/compile/pr46534.c +++ b/gcc/testsuite/gcc.c-torture/compile/pr46534.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "too big" { avr-*-* nvptx-*-* pdp11-*-* } { "*" } { "" } } */ +/* { dg-skip-if "too big" { avr-*-* nvptx-*-* pdp11-*-* } } */ /* PR middle-end/46534 */ extern int printf (const char *, ...); diff --git a/gcc/testsuite/gcc.c-torture/execute/20020404-1.c b/gcc/testsuite/gcc.c-torture/execute/20020404-1.c index fe5ea14..34173e5 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20020404-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20020404-1.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target int32plus } */ -/* { dg-skip-if "pointers can be truncated" { m32c-*-* } "*" "" } */ +/* { dg-skip-if "pointers can be truncated" { m32c-*-* } } */ /* Extracted from GDB sources. */ typedef long long bfd_signed_vma; diff --git a/gcc/testsuite/gcc.c-torture/execute/20030222-1.c b/gcc/testsuite/gcc.c-torture/execute/20030222-1.c index a820cf2..dbac74a 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20030222-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20030222-1.c @@ -3,8 +3,8 @@ succeeded at all. We use volatile to make sure the long long is actually truncated to int, in case a single register is wide enough for a long long. */ -/* { dg-skip-if "asm would require extra shift-left-4-byte" { spu-*-* } "*" "" } */ -/* { dg-skip-if "asm requires register allocation" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "asm would require extra shift-left-4-byte" { spu-*-* } } */ +/* { dg-skip-if "asm requires register allocation" { nvptx-*-* } } */ #include void diff --git a/gcc/testsuite/gcc.c-torture/execute/20061220-1.c b/gcc/testsuite/gcc.c-torture/execute/20061220-1.c index 9a133e8..b33efc6 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20061220-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20061220-1.c @@ -1,5 +1,5 @@ /* PR middle-end/30262 */ -/* { dg-skip-if "asm statements do not work as expected" { rl78-*-* } "*" "" } */ +/* { dg-skip-if "asm statements do not work as expected" { rl78-*-* } } */ extern void abort (void); int diff --git a/gcc/testsuite/gcc.c-torture/execute/990413-2.c b/gcc/testsuite/gcc.c-torture/execute/990413-2.c index 3beb540..09a0573 100644 --- a/gcc/testsuite/gcc.c-torture/execute/990413-2.c +++ b/gcc/testsuite/gcc.c-torture/execute/990413-2.c @@ -1,5 +1,5 @@ /* This tests for a bug in regstack that was breaking glibc's math library. */ -/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.c-torture/execute/bf64-1.c b/gcc/testsuite/gcc.c-torture/execute/bf64-1.c index d69a7c4..c9241e2 100644 --- a/gcc/testsuite/gcc.c-torture/execute/bf64-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/bf64-1.c @@ -1,4 +1,4 @@ -/* { dg-xfail-if "ABI specifies bitfields cannot exceed 32 bits" { mcore-*-* } "*" "" } */ +/* { dg-xfail-if "ABI specifies bitfields cannot exceed 32 bits" { mcore-*-* } } */ struct tmp { long long int pad : 12; diff --git a/gcc/testsuite/gcc.c-torture/execute/complex-6.c b/gcc/testsuite/gcc.c-torture/execute/complex-6.c index 2e7a6cd..50fb18e 100644 --- a/gcc/testsuite/gcc.c-torture/execute/complex-6.c +++ b/gcc/testsuite/gcc.c-torture/execute/complex-6.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ /* This test tests complex conjugate and passing/returning of complex parameter. */ diff --git a/gcc/testsuite/gcc.c-torture/execute/fprintf-1.c b/gcc/testsuite/gcc.c-torture/execute/fprintf-1.c index bd3069f..15996ef 100644 --- a/gcc/testsuite/gcc.c-torture/execute/fprintf-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/fprintf-1.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ #include #include diff --git a/gcc/testsuite/gcc.c-torture/execute/fprintf-chk-1.c b/gcc/testsuite/gcc.c-torture/execute/fprintf-chk-1.c index caad0a4..6f9e62c 100644 --- a/gcc/testsuite/gcc.c-torture/execute/fprintf-chk-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/fprintf-chk-1.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ #include #include diff --git a/gcc/testsuite/gcc.c-torture/execute/gofast.c b/gcc/testsuite/gcc.c-torture/execute/gofast.c index a0b6e04..72774f1 100644 --- a/gcc/testsuite/gcc.c-torture/execute/gofast.c +++ b/gcc/testsuite/gcc.c-torture/execute/gofast.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ /* Program to test gcc's usage of the gofast library. */ diff --git a/gcc/testsuite/gcc.c-torture/execute/loop-2f.c b/gcc/testsuite/gcc.c-torture/execute/loop-2f.c index 539db4b..a857f27 100644 --- a/gcc/testsuite/gcc.c-torture/execute/loop-2f.c +++ b/gcc/testsuite/gcc.c-torture/execute/loop-2f.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target mmap } */ -/* { dg-skip-if "the executable is at the same position the test tries to remap" { m68k-*-linux* } { "*" } { "" } } */ +/* { dg-skip-if "the executable is at the same position the test tries to remap" { m68k-*-linux* } } */ #include diff --git a/gcc/testsuite/gcc.c-torture/execute/loop-2g.c b/gcc/testsuite/gcc.c-torture/execute/loop-2g.c index 0840945..71e2409 100644 --- a/gcc/testsuite/gcc.c-torture/execute/loop-2g.c +++ b/gcc/testsuite/gcc.c-torture/execute/loop-2g.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target mmap } */ -/* { dg-skip-if "the executable is at the same position the test tries to remap" { m68k-*-linux* } { "*" } { "" } } */ +/* { dg-skip-if "the executable is at the same position the test tries to remap" { m68k-*-linux* } } */ #include diff --git a/gcc/testsuite/gcc.c-torture/execute/pr34456.c b/gcc/testsuite/gcc.c-torture/execute/pr34456.c index 53e46ed..b4a845e 100644 --- a/gcc/testsuite/gcc.c-torture/execute/pr34456.c +++ b/gcc/testsuite/gcc.c-torture/execute/pr34456.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires qsort" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires qsort" { freestanding } } */ #include diff --git a/gcc/testsuite/gcc.c-torture/execute/pr35456.c b/gcc/testsuite/gcc.c-torture/execute/pr35456.c index 17c70bc..67f64db 100644 --- a/gcc/testsuite/gcc.c-torture/execute/pr35456.c +++ b/gcc/testsuite/gcc.c-torture/execute/pr35456.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "signed zero not supported" { "vax-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "signed zero not supported" { "vax-*-*" } } */ extern void abort (void); double diff --git a/gcc/testsuite/gcc.c-torture/execute/pr39228.c b/gcc/testsuite/gcc.c-torture/execute/pr39228.c index 2bc6006..ad0d376 100644 --- a/gcc/testsuite/gcc.c-torture/execute/pr39228.c +++ b/gcc/testsuite/gcc.c-torture/execute/pr39228.c @@ -1,5 +1,5 @@ /* { dg-add-options ieee } */ -/* { dg-skip-if "No Inf/NaN support" { spu-*-* } "*" "" } */ +/* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.c-torture/execute/pr47237.c b/gcc/testsuite/gcc.c-torture/execute/pr47237.c index 0802531..9812406 100644 --- a/gcc/testsuite/gcc.c-torture/execute/pr47237.c +++ b/gcc/testsuite/gcc.c-torture/execute/pr47237.c @@ -1,4 +1,4 @@ -/* { dg-xfail-if "can cause stack underflow" { nios2-*-* } "*" "" } */ +/* { dg-xfail-if "can cause stack underflow" { nios2-*-* } } */ /* { dg-require-effective-target untyped_assembly } */ #define INTEGER_ARG 5 diff --git a/gcc/testsuite/gcc.c-torture/execute/pr78622.c b/gcc/testsuite/gcc.c-torture/execute/pr78622.c index 384803d..c09bb43 100644 --- a/gcc/testsuite/gcc.c-torture/execute/pr78622.c +++ b/gcc/testsuite/gcc.c-torture/execute/pr78622.c @@ -1,6 +1,6 @@ /* PR middle-end/78622 - [7 Regression] -Wformat-overflow/-fprintf-return-value incorrect with overflow/wrapping - { dg-skip-if "Requires %hhd format" { hppa*-*-hpux* } { "*" } { "" } } + { dg-skip-if "Requires %hhd format" { hppa*-*-hpux* } } { dg-require-effective-target c99_runtime } { dg-additional-options "-Wformat-overflow=2" } */ diff --git a/gcc/testsuite/gcc.c-torture/execute/printf-1.c b/gcc/testsuite/gcc.c-torture/execute/printf-1.c index 13e331d..654e627 100644 --- a/gcc/testsuite/gcc.c-torture/execute/printf-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/printf-1.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ #include #include diff --git a/gcc/testsuite/gcc.c-torture/execute/printf-chk-1.c b/gcc/testsuite/gcc.c-torture/execute/printf-chk-1.c index fde85f9..aab4306 100644 --- a/gcc/testsuite/gcc.c-torture/execute/printf-chk-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/printf-chk-1.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ #include #include diff --git a/gcc/testsuite/gcc.c-torture/execute/strncmp-1.c b/gcc/testsuite/gcc.c-torture/execute/strncmp-1.c index c5d39fd..c244859 100644 --- a/gcc/testsuite/gcc.c-torture/execute/strncmp-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/strncmp-1.c @@ -1,4 +1,4 @@ -/* { dg-xfail-if "kernel strncmp does not perform unsigned comparisons" { vxworks_kernel } "*" "" } */ +/* { dg-xfail-if "kernel strncmp does not perform unsigned comparisons" { vxworks_kernel } } */ /* Copyright (C) 2002 Free Software Foundation. Test strncmp with various combinations of pointer alignments and lengths to diff --git a/gcc/testsuite/gcc.c-torture/execute/vfprintf-1.c b/gcc/testsuite/gcc.c-torture/execute/vfprintf-1.c index c9ce492..0ac41de 100644 --- a/gcc/testsuite/gcc.c-torture/execute/vfprintf-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/vfprintf-1.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ #ifndef test #include diff --git a/gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.c b/gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.c index a642209..401eaf4 100644 --- a/gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/vfprintf-chk-1.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ #ifndef test #include diff --git a/gcc/testsuite/gcc.c-torture/execute/vprintf-1.c b/gcc/testsuite/gcc.c-torture/execute/vprintf-1.c index 8b7038f..259397e 100644 --- a/gcc/testsuite/gcc.c-torture/execute/vprintf-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/vprintf-1.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ #ifndef test #include diff --git a/gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.c b/gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.c index f9bda6e..04ecc4d 100644 --- a/gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/vprintf-chk-1.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ #ifndef test #include diff --git a/gcc/testsuite/gcc.c-torture/execute/zerolen-2.c b/gcc/testsuite/gcc.c-torture/execute/zerolen-2.c index 4a55acd..7c93338 100644 --- a/gcc/testsuite/gcc.c-torture/execute/zerolen-2.c +++ b/gcc/testsuite/gcc.c-torture/execute/zerolen-2.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "assumes absence of larger-than-word padding" { epiphany-*-* } "*" "" } */ +/* { dg-skip-if "assumes absence of larger-than-word padding" { epiphany-*-* } } */ extern void abort(void); typedef int word __attribute__((mode(word))); diff --git a/gcc/testsuite/gcc.dg/20020219-1.c b/gcc/testsuite/gcc.dg/20020219-1.c index 839011f..055b5b9 100644 --- a/gcc/testsuite/gcc.dg/20020219-1.c +++ b/gcc/testsuite/gcc.dg/20020219-1.c @@ -13,9 +13,9 @@ /* { dg-do run } */ /* { dg-options "-O2" } */ /* { dg-options "-O2 -mdisable-indexing" { target hppa*-*-hpux* } } */ -/* { dg-skip-if "" { aarch64*-*-* && ilp32 } { "*" } { "" } } */ +/* { dg-skip-if "" { aarch64*-*-* && ilp32 } } */ /* { dg-skip-if "" { "ia64-*-hpux*" } "*" "-mlp64" } */ -/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */ +/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } } */ /* Disable the test entirely for 16-bit targets. */ #if __INT_MAX__ > 32767 diff --git a/gcc/testsuite/gcc.dg/20030702-1.c b/gcc/testsuite/gcc.dg/20030702-1.c index 0bc1b1c..e4e981b 100644 --- a/gcc/testsuite/gcc.dg/20030702-1.c +++ b/gcc/testsuite/gcc.dg/20030702-1.c @@ -2,7 +2,7 @@ correctly in combine. */ /* { dg-do compile { target fpic } } */ /* { dg-options "-O2 -fpic -fprofile-arcs" } */ -/* { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } { "*" } { "" } } */ +/* { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } } */ /* { dg-require-profiling "-fprofile-generate" } */ int fork (void); diff --git a/gcc/testsuite/gcc.dg/20050503-1.c b/gcc/testsuite/gcc.dg/20050503-1.c index f85129a..57dfefc 100644 --- a/gcc/testsuite/gcc.dg/20050503-1.c +++ b/gcc/testsuite/gcc.dg/20050503-1.c @@ -2,7 +2,7 @@ Test whether tail call information is propagated through builtin expanders. */ /* { dg-do compile } */ -/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && { ia32 && { ! nonpic } } } { "*" } { "" } } */ +/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && { ia32 && { ! nonpic } } } } */ /* { dg-options "-O2" } */ typedef __SIZE_TYPE__ size_t; diff --git a/gcc/testsuite/gcc.dg/Wconversion-complex-c99.c b/gcc/testsuite/gcc.dg/Wconversion-complex-c99.c index bc7439d..e8bc9db 100644 --- a/gcc/testsuite/gcc.dg/Wconversion-complex-c99.c +++ b/gcc/testsuite/gcc.dg/Wconversion-complex-c99.c @@ -5,7 +5,7 @@ Likewise, the magic value 16777217. */ /* { dg-do compile } */ -/* { dg-skip-if "doubles are floats,ints are 16bits" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "doubles are floats,ints are 16bits" { "avr-*-*" } } */ /* { dg-options " -std=c99 -pedantic -Wconversion " } */ /* { dg-require-effective-target int32plus } */ /* { dg-require-effective-target double64plus } */ diff --git a/gcc/testsuite/gcc.dg/Wconversion-complex-gnu.c b/gcc/testsuite/gcc.dg/Wconversion-complex-gnu.c index 80990cb..d458350 100644 --- a/gcc/testsuite/gcc.dg/Wconversion-complex-gnu.c +++ b/gcc/testsuite/gcc.dg/Wconversion-complex-gnu.c @@ -4,7 +4,7 @@ These tests cover integer complex values (which are GNU extensions). */ /* { dg-do compile } */ -/* { dg-skip-if "doubles are floats,ints are 16bits" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "doubles are floats,ints are 16bits" { "avr-*-*" } } */ /* { dg-options " -std=gnu99 -Wconversion " } */ /* { dg-require-effective-target int32plus } */ /* { dg-require-effective-target double64plus } */ diff --git a/gcc/testsuite/gcc.dg/Wconversion-real-integer.c b/gcc/testsuite/gcc.dg/Wconversion-real-integer.c index 8967025..92e6987 100644 --- a/gcc/testsuite/gcc.dg/Wconversion-real-integer.c +++ b/gcc/testsuite/gcc.dg/Wconversion-real-integer.c @@ -2,7 +2,7 @@ integers. */ /* { dg-do compile } */ -/* { dg-skip-if "doubles are floats,ints are 16bits" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "doubles are floats,ints are 16bits" { "avr-*-*" } } */ /* { dg-options "-std=c99 -Wconversion" } */ /* { dg-require-effective-target int32plus } */ /* { dg-require-effective-target double64plus } */ diff --git a/gcc/testsuite/gcc.dg/attr-alias-3.c b/gcc/testsuite/gcc.dg/attr-alias-3.c index 4c6f390..03c4da9 100644 --- a/gcc/testsuite/gcc.dg/attr-alias-3.c +++ b/gcc/testsuite/gcc.dg/attr-alias-3.c @@ -1,5 +1,5 @@ // { dg-do link } -// { dg-skip-if "" { "powerpc-ibm-aix*" } { "*" } { "" } } +// { dg-skip-if "" { "powerpc-ibm-aix*" } } // { dg-require-alias "" } // { dg-options "-O2 -fno-common" } diff --git a/gcc/testsuite/gcc.dg/attr-alias-5.c b/gcc/testsuite/gcc.dg/attr-alias-5.c index 56d9b30..91e63f8 100644 --- a/gcc/testsuite/gcc.dg/attr-alias-5.c +++ b/gcc/testsuite/gcc.dg/attr-alias-5.c @@ -4,7 +4,7 @@ /* { dg-options "-std=gnu99" } */ /* { dg-require-alias "" } */ /* { dg-require-ascii-locale "" } */ -/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ void f0 (void) __attribute__((alias("\xa1"))); /* { dg-error "undefined symbol '\\\\241'" } */ void f1 (void) __attribute__((alias("\u00e9"))); /* { dg-error "undefined symbol '\\\\U000000e9'" } */ diff --git a/gcc/testsuite/gcc.dg/attr-weakref-1.c b/gcc/testsuite/gcc.dg/attr-weakref-1.c index d327b40..9e14b60 100644 --- a/gcc/testsuite/gcc.dg/attr-weakref-1.c +++ b/gcc/testsuite/gcc.dg/attr-weakref-1.c @@ -5,7 +5,7 @@ // This test requires support for undefined weak symbols. This support // is not available on the following targets. The test is skipped rather than // xfailed to suppress the warning that would otherwise arise. -// { dg-skip-if "" { "hppa*-*-hpux*" "*-*-aix*" "nvptx-*-*" } "*" { "" } } +// { dg-skip-if "" { "hppa*-*-hpux*" "*-*-aix*" "nvptx-*-*" } } // For kernel modules and static RTPs, the loader treats undefined weak // symbols in the same way as undefined strong symbols. The test diff --git a/gcc/testsuite/gcc.dg/autopar/pr46799.c b/gcc/testsuite/gcc.dg/autopar/pr46799.c index 0516d26..50d67d1 100644 --- a/gcc/testsuite/gcc.dg/autopar/pr46799.c +++ b/gcc/testsuite/gcc.dg/autopar/pr46799.c @@ -1,7 +1,7 @@ /* PR debug/46799 */ /* { dg-do compile } */ /* { dg-options "-O -ftree-parallelize-loops=2 -fno-tree-dce -ftree-pre -fcompare-debug" } */ -/* { dg-xfail-if "compare-debug failure" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "compare-debug failure" { powerpc-ibm-aix* } } */ int foo (int i, int *a) diff --git a/gcc/testsuite/gcc.dg/builtin-apply2.c b/gcc/testsuite/gcc.dg/builtin-apply2.c index ad61d3b..3768caa 100644 --- a/gcc/testsuite/gcc.dg/builtin-apply2.c +++ b/gcc/testsuite/gcc.dg/builtin-apply2.c @@ -1,8 +1,8 @@ /* { dg-do run } */ /* { dg-require-effective-target untyped_assembly } */ -/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "avr-*-* nds32*-*-*" } { "*" } { "" } } */ -/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs." { "riscv*-*-*" } { "*" } { "" } } */ -/* { dg-skip-if "Variadic funcs use Base AAPCS. Normal funcs use VFP variant." { arm*-*-* && arm_hf_eabi } { "*" } { "" } } */ +/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { "avr-*-* nds32*-*-*" } } */ +/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs." { "riscv*-*-*" } } */ +/* { dg-skip-if "Variadic funcs use Base AAPCS. Normal funcs use VFP variant." { arm*-*-* && arm_hf_eabi } } */ /* PR target/12503 */ /* Origin: */ diff --git a/gcc/testsuite/gcc.dg/builtin-object-size-10.c b/gcc/testsuite/gcc.dg/builtin-object-size-10.c index 8d6fd97..2a212fa 100644 --- a/gcc/testsuite/gcc.dg/builtin-object-size-10.c +++ b/gcc/testsuite/gcc.dg/builtin-object-size-10.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fdump-tree-objsz1-details" } */ -// { dg-skip-if "packed attribute missing for drone_source_packet" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for drone_source_packet" { "epiphany-*-*" } } typedef struct { char sentinel[4]; diff --git a/gcc/testsuite/gcc.dg/builtin-object-size-11.c b/gcc/testsuite/gcc.dg/builtin-object-size-11.c index 309a684..7c4a921 100644 --- a/gcc/testsuite/gcc.dg/builtin-object-size-11.c +++ b/gcc/testsuite/gcc.dg/builtin-object-size-11.c @@ -1,7 +1,7 @@ /* PR48985 */ /* { dg-do run } */ /* { dg-options "-std=gnu89" } */ -/* { dg-skip-if "packed attribute missing for struct s" { "epiphany-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "packed attribute missing for struct s" { "epiphany-*-*" } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/builtin-return-1.c b/gcc/testsuite/gcc.dg/builtin-return-1.c index 56a6bae..edcec97 100644 --- a/gcc/testsuite/gcc.dg/builtin-return-1.c +++ b/gcc/testsuite/gcc.dg/builtin-return-1.c @@ -1,7 +1,7 @@ /* PR middle-end/11151 */ /* Originator: Andrew Church */ /* { dg-do run } */ -/* { dg-xfail-run-if "PR36571 untyped return is char register" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-xfail-run-if "PR36571 untyped return is char register" { "avr-*-*" } } */ /* { dg-require-effective-target untyped_assembly } */ /* This used to fail on SPARC because the (undefined) return value of 'bar' was overwriting that of 'foo'. */ diff --git a/gcc/testsuite/gcc.dg/builtin-stringop-chk-1.c b/gcc/testsuite/gcc.dg/builtin-stringop-chk-1.c index ebf6e85..e265578 100644 --- a/gcc/testsuite/gcc.dg/builtin-stringop-chk-1.c +++ b/gcc/testsuite/gcc.dg/builtin-stringop-chk-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -Wno-format -std=gnu99 -ftrack-macro-expansion=0" } */ /* { dg-additional-options "-mstructure-size-boundary=8" { target arm*-*-* } } */ -// { dg-skip-if "packed attribute missing for t" { "epiphany-*-*" } { "*" } { "" } } +// { dg-skip-if "packed attribute missing for t" { "epiphany-*-*" } } extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/c11-align-4.c b/gcc/testsuite/gcc.dg/c11-align-4.c index 6377db6..57f93ff 100644 --- a/gcc/testsuite/gcc.dg/c11-align-4.c +++ b/gcc/testsuite/gcc.dg/c11-align-4.c @@ -2,7 +2,7 @@ are at least some alignment constraints). */ /* { dg-do compile } */ /* { dg-options "-std=c11 -pedantic-errors" } */ -/* { dg-skip-if "no alignment constraints" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "no alignment constraints" { "avr-*-*" } } */ #include diff --git a/gcc/testsuite/gcc.dg/c11-true_min-1.c b/gcc/testsuite/gcc.dg/c11-true_min-1.c index fa83c17..f666c72 100644 --- a/gcc/testsuite/gcc.dg/c11-true_min-1.c +++ b/gcc/testsuite/gcc.dg/c11-true_min-1.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-options "-std=c11" } */ -/* { dg-xfail-run-if "PR58757 -mieee is required to compare denormals" { alpha*-*-* } { "*" } { "" } } */ +/* { dg-xfail-run-if "PR58757 -mieee is required to compare denormals" { alpha*-*-* } } */ /* Test that the smallest positive value is not 0. This needs to be true even when denormals are not supported, so we do not pass any flag diff --git a/gcc/testsuite/gcc.dg/cdce2.c b/gcc/testsuite/gcc.dg/cdce2.c index 55030f18..9e6f344 100644 --- a/gcc/testsuite/gcc.dg/cdce2.c +++ b/gcc/testsuite/gcc.dg/cdce2.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "doubles are floats" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "doubles are floats" { "avr-*-*" } } */ /* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details -lm" } */ /* { dg-final { scan-tree-dump "cdce2.c:15: note: function call is shrink-wrapped into error conditions\." "cdce" } } */ diff --git a/gcc/testsuite/gcc.dg/cleanup-12.c b/gcc/testsuite/gcc.dg/cleanup-12.c index 15c079f..efb9a58 100644 --- a/gcc/testsuite/gcc.dg/cleanup-12.c +++ b/gcc/testsuite/gcc.dg/cleanup-12.c @@ -2,8 +2,8 @@ /* HP-UX libunwind.so doesn't provide _UA_END_OF_STACK */ /* { dg-do run } */ /* { dg-options "-O2 -fexceptions" } */ -/* { dg-skip-if "" { "ia64-*-hpux11.*" } { "*" } { "" } } */ -/* { dg-skip-if "" { ! nonlocal_goto } { "*" } { "" } } */ +/* { dg-skip-if "" { "ia64-*-hpux11.*" } } */ +/* { dg-skip-if "" { ! nonlocal_goto } } */ /* Verify unwind info in presence of alloca. */ #include diff --git a/gcc/testsuite/gcc.dg/cleanup-13.c b/gcc/testsuite/gcc.dg/cleanup-13.c index 0ab1ca2..8a8db27 100644 --- a/gcc/testsuite/gcc.dg/cleanup-13.c +++ b/gcc/testsuite/gcc.dg/cleanup-13.c @@ -1,8 +1,8 @@ /* HP-UX libunwind.so doesn't provide _UA_END_OF_STACK */ /* { dg-do run } */ /* { dg-options "-fexceptions" } */ -/* { dg-skip-if "" { "ia64-*-hpux11.*" } { "*" } { "" } } */ -/* { dg-skip-if "" { ! nonlocal_goto } { "*" } { "" } } */ +/* { dg-skip-if "" { "ia64-*-hpux11.*" } } */ +/* { dg-skip-if "" { ! nonlocal_goto } } */ /* Verify DW_OP_* handling in the unwinder. */ #include diff --git a/gcc/testsuite/gcc.dg/cleanup-5.c b/gcc/testsuite/gcc.dg/cleanup-5.c index 816d4ce..4257f9e 100644 --- a/gcc/testsuite/gcc.dg/cleanup-5.c +++ b/gcc/testsuite/gcc.dg/cleanup-5.c @@ -1,8 +1,8 @@ /* HP-UX libunwind.so doesn't provide _UA_END_OF_STACK */ /* { dg-do run } */ /* { dg-options "-fexceptions" } */ -/* { dg-skip-if "" { "ia64-*-hpux11.*" } { "*" } { "" } } */ -/* { dg-skip-if "" { ! nonlocal_goto } { "*" } { "" } } */ +/* { dg-skip-if "" { "ia64-*-hpux11.*" } } */ +/* { dg-skip-if "" { ! nonlocal_goto } } */ /* Verify that cleanups work with exception handling. */ #include diff --git a/gcc/testsuite/gcc.dg/compat/struct-by-value-16_main.c b/gcc/testsuite/gcc.dg/compat/struct-by-value-16_main.c index ecd60d1..a6f5ca1 100644 --- a/gcc/testsuite/gcc.dg/compat/struct-by-value-16_main.c +++ b/gcc/testsuite/gcc.dg/compat/struct-by-value-16_main.c @@ -1,7 +1,7 @@ /* Test structures passed by value, including to a function with a variable-length argument lists. All struct members are of type _Complex float. */ -/* { dg-skip-if "Program too big" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "Program too big" { "avr-*-*" } } */ extern void struct_by_value_16_x (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.dg/compat/struct-by-value-17_main.c b/gcc/testsuite/gcc.dg/compat/struct-by-value-17_main.c index 8787877..42616ee 100644 --- a/gcc/testsuite/gcc.dg/compat/struct-by-value-17_main.c +++ b/gcc/testsuite/gcc.dg/compat/struct-by-value-17_main.c @@ -1,7 +1,7 @@ /* Test structures passed by value, including to a function with a variable-length argument lists. All struct members are of type _Complex double. */ -/* { dg-skip-if "Program too big" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "Program too big" { "avr-*-*" } } */ extern void struct_by_value_17_x (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.dg/compat/struct-by-value-18_main.c b/gcc/testsuite/gcc.dg/compat/struct-by-value-18_main.c index 0ecc660..9bb19b3 100644 --- a/gcc/testsuite/gcc.dg/compat/struct-by-value-18_main.c +++ b/gcc/testsuite/gcc.dg/compat/struct-by-value-18_main.c @@ -1,7 +1,7 @@ /* Test structures passed by value, including to a function with a variable-length argument lists. All struct members are of type _Complex long double. */ -/* { dg-skip-if "Program too big" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "Program too big" { "avr-*-*" } } */ extern void struct_by_value_18_x (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.dg/constructor-1.c b/gcc/testsuite/gcc.dg/constructor-1.c index 73e9fc3..f907ce8 100644 --- a/gcc/testsuite/gcc.dg/constructor-1.c +++ b/gcc/testsuite/gcc.dg/constructor-1.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "" { ! global_constructor } { "*" } { "" } } */ +/* { dg-skip-if "" { ! global_constructor } } */ /* The ipa-split pass pulls the body of the if(!x) block into a separate function to make foo a better inlining diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char1.c b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char1.c index 23f9596..f693420 100644 --- a/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char1.c +++ b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char1.c @@ -1,7 +1,7 @@ /* PR debug/7241 */ /* { dg-do compile } */ /* { dg-options "-O2 -gdwarf -dA" } */ -/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } { "*" } { "" } } */ +/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } } */ /* { dg-final { scan-assembler "0x\[68\]\[ \t\]+\[#@;!/|\]+\[ \t\]+DW_AT_encoding" } } */ /* { dg-final { scan-assembler-not "0x\[57\]\[ \t\]+\[#@;!/|\]+\[ \t\]+DW_AT_encoding" } } */ diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char2.c b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char2.c index 4a4bd43..11499c6 100644 --- a/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char2.c +++ b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char2.c @@ -1,7 +1,7 @@ /* PR debug/7241 */ /* { dg-do compile } */ /* { dg-options "-O2 -gdwarf -dA" } */ -/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } { "*" } { "" } } */ +/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } } */ /* { dg-final { scan-assembler "0x\[68\]\[ \t\]+\[#@;!/|\]+\[ \t\]+DW_AT_encoding" } } */ /* { dg-final { scan-assembler-not "0x\[57\]\[ \t\]+\[#@;!/|\]+\[ \t\]+DW_AT_encoding" } } */ diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char3.c b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char3.c index 4ff201f..4bcccda 100644 --- a/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char3.c +++ b/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-char3.c @@ -1,7 +1,7 @@ /* PR debug/7241 */ /* { dg-do compile } */ /* { dg-options "-O2 -gdwarf -dA" } */ -/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } { "*" } { "" } } */ +/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } } */ /* { dg-final { scan-assembler "0x\[68\]\[ \t\]+\[#@;!/|\]+\[ \t\]+DW_AT_encoding" } } */ /* { dg-final { scan-assembler-not "0x\[57\]\[ \t\]+\[#@;!/|\]+\[ \t\]+DW_AT_encoding" } } */ diff --git a/gcc/testsuite/gcc.dg/debug/pr35154.c b/gcc/testsuite/gcc.dg/debug/pr35154.c index 7f6a6ea..08eefaf 100644 --- a/gcc/testsuite/gcc.dg/debug/pr35154.c +++ b/gcc/testsuite/gcc.dg/debug/pr35154.c @@ -24,7 +24,7 @@ main() optb.f2 = 'D'; i_outer = 'e'; /* { dg-do compile } */ -/* { dg-skip-if "No stabs" { mmix-*-* alpha*-*-* hppa*64*-*-* ia64-*-* *-*-vxworks* } { "*" } { "" } } */ +/* { dg-skip-if "No stabs" { mmix-*-* alpha*-*-* hppa*64*-*-* ia64-*-* *-*-vxworks* } } */ /* { dg-skip-if "stabs only" { *-*-* } { "*" } { "-gstabs" } } */ return 0; } diff --git a/gcc/testsuite/gcc.dg/dfp/convert-dfp-round.c b/gcc/testsuite/gcc.dg/dfp/convert-dfp-round.c index e3781bf..ecae7dd 100644 --- a/gcc/testsuite/gcc.dg/dfp/convert-dfp-round.c +++ b/gcc/testsuite/gcc.dg/dfp/convert-dfp-round.c @@ -1,5 +1,5 @@ /* { dg-options "-O0" } */ -/* { dg-skip-if "test is for emulation" { hard_dfp } { "*" } { "" } } */ +/* { dg-skip-if "test is for emulation" { hard_dfp } } */ /* N1150 5.2: Conversions among decimal floating types and between decimal floating types and generic floating types. diff --git a/gcc/testsuite/gcc.dg/dfp/fe-binop.c b/gcc/testsuite/gcc.dg/dfp/fe-binop.c index eb0da1b2..f83577d 100644 --- a/gcc/testsuite/gcc.dg/dfp/fe-binop.c +++ b/gcc/testsuite/gcc.dg/dfp/fe-binop.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "test is for emulation" { hard_dfp } { "*" } { "" } } */ +/* { dg-skip-if "test is for emulation" { hard_dfp } } */ /* Touch tests that check for raising appropriate exceptions for binary arithmetic operations on decimal float values. */ diff --git a/gcc/testsuite/gcc.dg/dfp/fe-convert-1.c b/gcc/testsuite/gcc.dg/dfp/fe-convert-1.c index b652802..9185b01 100644 --- a/gcc/testsuite/gcc.dg/dfp/fe-convert-1.c +++ b/gcc/testsuite/gcc.dg/dfp/fe-convert-1.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "test is for emulation" { hard_dfp } { "*" } { "" } } */ +/* { dg-skip-if "test is for emulation" { hard_dfp } } */ /* Check that appropriate exceptions are raised for conversions involving decimal float values. */ diff --git a/gcc/testsuite/gcc.dg/format/dfp-printf-1.c b/gcc/testsuite/gcc.dg/format/dfp-printf-1.c index 4453ad1..e92f161 100644 --- a/gcc/testsuite/gcc.dg/format/dfp-printf-1.c +++ b/gcc/testsuite/gcc.dg/format/dfp-printf-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target dfp } */ /* { dg-options "-Wformat" } */ -/* { dg-skip-if "No scanf/printf dfp support" { *-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "No scanf/printf dfp support" { *-*-mingw* } } */ extern int printf (const char *restrict, ...); diff --git a/gcc/testsuite/gcc.dg/graphite/run-id-pr47653.c b/gcc/testsuite/gcc.dg/graphite/run-id-pr47653.c index 20fdf87..cd9d8eb 100644 --- a/gcc/testsuite/gcc.dg/graphite/run-id-pr47653.c +++ b/gcc/testsuite/gcc.dg/graphite/run-id-pr47653.c @@ -1,6 +1,6 @@ /* { dg-options "-O -fstack-check=generic -ftree-pre -fgraphite-identity" } */ /* nvptx doesn't expose a stack. */ -/* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { nvptx-*-* } } */ int main () { diff --git a/gcc/testsuite/gcc.dg/loop-8.c b/gcc/testsuite/gcc.dg/loop-8.c index 5fcab7b..842c0e7 100644 --- a/gcc/testsuite/gcc.dg/loop-8.c +++ b/gcc/testsuite/gcc.dg/loop-8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O1 -fdump-rtl-loop2_invariant" } */ -/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* powerpc*-*-* riscv*-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* powerpc*-*-* riscv*-*-*" } } */ void f (int *a, int *b) diff --git a/gcc/testsuite/gcc.dg/lower-subreg-1.c b/gcc/testsuite/gcc.dg/lower-subreg-1.c index 47057fe..6bae730 100644 --- a/gcc/testsuite/gcc.dg/lower-subreg-1.c +++ b/gcc/testsuite/gcc.dg/lower-subreg-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { ! { mips64 || { aarch64*-*-* arm*-*-* ia64-*-* sparc*-*-* spu-*-* tilegx-*-* } } } } } */ /* { dg-options "-O -fdump-rtl-subreg1" } */ /* { dg-additional-options "-mno-stv" { target ia32 } } */ -/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */ +/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } } */ /* { dg-require-effective-target ilp32 } */ long long test (long long a, long long b) { return a | b; } diff --git a/gcc/testsuite/gcc.dg/lto/20081126_0.c b/gcc/testsuite/gcc.dg/lto/20081126_0.c index 9243da9..f610d09 100644 --- a/gcc/testsuite/gcc.dg/lto/20081126_0.c +++ b/gcc/testsuite/gcc.dg/lto/20081126_0.c @@ -1,5 +1,5 @@ /* { dg-lto-do link } */ -/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } } */ /* { dg-lto-options {{-flto -r -nostdlib}} } */ int f(void) { diff --git a/gcc/testsuite/gcc.dg/lto/20081204-2_0.c b/gcc/testsuite/gcc.dg/lto/20081204-2_0.c index 5344605..c08da17 100644 --- a/gcc/testsuite/gcc.dg/lto/20081204-2_0.c +++ b/gcc/testsuite/gcc.dg/lto/20081204-2_0.c @@ -1,5 +1,5 @@ /* { dg-lto-do link } */ -/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } } */ /* { dg-lto-options {{-w -flto -fPIC -r -nostdlib}} } */ register int ri asm("edi"); diff --git a/gcc/testsuite/gcc.dg/lto/20090206-1_0.c b/gcc/testsuite/gcc.dg/lto/20090206-1_0.c index 83d2c86..3fbfb23 100644 --- a/gcc/testsuite/gcc.dg/lto/20090206-1_0.c +++ b/gcc/testsuite/gcc.dg/lto/20090206-1_0.c @@ -1,5 +1,5 @@ /* { dg-lto-do link } */ -/* { dg-skip-if "" { ! { i?86-*-linux* i?86-*-gnu* x86_64-*-linux* } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { i?86-*-linux* i?86-*-gnu* x86_64-*-linux* } } } */ /* { dg-lto-options {{-fPIC -r -nostdlib -flto -flto-partition=1to1 -msse2}} } */ /* { dg-require-effective-target sse2 } */ /* { dg-suppress-ld-options {-fPIC -msse2} } */ diff --git a/gcc/testsuite/gcc.dg/lto/20090206-2_0.c b/gcc/testsuite/gcc.dg/lto/20090206-2_0.c index 40b7132..b82e416 100644 --- a/gcc/testsuite/gcc.dg/lto/20090206-2_0.c +++ b/gcc/testsuite/gcc.dg/lto/20090206-2_0.c @@ -1,5 +1,5 @@ /* { dg-lto-do link } */ -/* { dg-skip-if "" { ! { i?86-*-linux* i?86-*-gnu* x86_64-*-linux* } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { i?86-*-linux* i?86-*-gnu* x86_64-*-linux* } } } */ /* { dg-require-effective-target fpic } */ /* { dg-lto-options {{-flto -flto-partition=1to1 -fPIC}} } */ /* { dg-suppress-ld-options {-fPIC} } */ diff --git a/gcc/testsuite/gcc.dg/lto/20090914-2_0.c b/gcc/testsuite/gcc.dg/lto/20090914-2_0.c index d83ed37..668e201 100644 --- a/gcc/testsuite/gcc.dg/lto/20090914-2_0.c +++ b/gcc/testsuite/gcc.dg/lto/20090914-2_0.c @@ -1,7 +1,7 @@ /* { dg-lto-do run } */ -/* { dg-skip-if "x86 only" { ! { x86_64-*-* i?86-*-* } } { "*" } { "" } } */ -/* { dg-skip-if "no .type" { *-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "no @function" { *-*-mingw* *-*-cygwin* } { "*" } { "" } } */ +/* { dg-skip-if "x86 only" { ! { x86_64-*-* i?86-*-* } } } */ +/* { dg-skip-if "no .type" { *-*-darwin* } } */ +/* { dg-skip-if "no @function" { *-*-mingw* *-*-cygwin* } } */ /* Doesn't work without this dummy function with -fwhopr. */ int foo(void) { } diff --git a/gcc/testsuite/gcc.dg/lto/20091013-1_1.c b/gcc/testsuite/gcc.dg/lto/20091013-1_1.c index b75d095..c958177 100644 --- a/gcc/testsuite/gcc.dg/lto/20091013-1_1.c +++ b/gcc/testsuite/gcc.dg/lto/20091013-1_1.c @@ -1,4 +1,4 @@ -/* { dg-xfail-if "cast to pointer of different size" { "avr-*-*" x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-xfail-if "cast to pointer of different size" { "avr-*-*" x86_64-*-mingw* } } */ typedef struct HDC__ { int unused; } *HDC; typedef struct HFONT__ { int unused; } *HFONT; diff --git a/gcc/testsuite/gcc.dg/lto/20091013-1_2.c b/gcc/testsuite/gcc.dg/lto/20091013-1_2.c index c856041..94a4f72 100644 --- a/gcc/testsuite/gcc.dg/lto/20091013-1_2.c +++ b/gcc/testsuite/gcc.dg/lto/20091013-1_2.c @@ -1,4 +1,4 @@ -/* { dg-xfail-if "cast to pointer of different size" { "avr-*-*" x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-xfail-if "cast to pointer of different size" { "avr-*-*" x86_64-*-mingw* } } */ typedef struct HDC__ { int unused; } *HDC; typedef struct HFONT__ { int unused; } *HFONT; diff --git a/gcc/testsuite/gcc.dg/lto/20100518_0.c b/gcc/testsuite/gcc.dg/lto/20100518_0.c index c0e9c8b..cf19a50 100644 --- a/gcc/testsuite/gcc.dg/lto/20100518_0.c +++ b/gcc/testsuite/gcc.dg/lto/20100518_0.c @@ -1,5 +1,5 @@ /* { dg-lto-do link } */ -/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } } */ /* Forgot to steam in/out the number of labels for asm goto. PR44184. */ extern int printf (__const char *__restrict __format, ...); diff --git a/gcc/testsuite/gcc.dg/lto/20120723_0.c b/gcc/testsuite/gcc.dg/lto/20120723_0.c index 77694d8..4724e3e 100644 --- a/gcc/testsuite/gcc.dg/lto/20120723_0.c +++ b/gcc/testsuite/gcc.dg/lto/20120723_0.c @@ -2,7 +2,7 @@ mixed up. ??? This testcase is invalid C and can only pass on specific platforms. */ /* { dg-lto-do run } */ -/* { dg-skip-if "" { { sparc*-*-* } && ilp32 } { "*" } { "" } } */ +/* { dg-skip-if "" { { sparc*-*-* } && ilp32 } } */ /* { dg-lto-options { {-O3 -fno-early-inlining -flto -Wno-lto-type-mismatch}} } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/lto/pr47259_0.c b/gcc/testsuite/gcc.dg/lto/pr47259_0.c index bda485c..3549c97 100644 --- a/gcc/testsuite/gcc.dg/lto/pr47259_0.c +++ b/gcc/testsuite/gcc.dg/lto/pr47259_0.c @@ -1,5 +1,5 @@ /* { dg-lto-do link } */ -/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } } */ /* { dg-lto-options { { -O2 -flto -w } } } */ register int r asm("esi"); diff --git a/gcc/testsuite/gcc.dg/pr25805.c b/gcc/testsuite/gcc.dg/pr25805.c index 94133dd..2c083f2 100644 --- a/gcc/testsuite/gcc.dg/pr25805.c +++ b/gcc/testsuite/gcc.dg/pr25805.c @@ -2,7 +2,7 @@ storage for d1.a. */ /* { dg-do run } */ /* { dg-options "" } */ -/* { dg-skip-if "packed attribute missing for d1" { "epiphany-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "packed attribute missing for d1" { "epiphany-*-*" } } */ extern void abort (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.dg/pr27531-1.c b/gcc/testsuite/gcc.dg/pr27531-1.c index 990c183..b1ea748 100644 --- a/gcc/testsuite/gcc.dg/pr27531-1.c +++ b/gcc/testsuite/gcc.dg/pr27531-1.c @@ -4,7 +4,7 @@ output to reference a label that had been eliminated. */ /* { dg-do link } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ typedef struct _IO_FILE FILE; char const *RCSname; diff --git a/gcc/testsuite/gcc.dg/pr28243.c b/gcc/testsuite/gcc.dg/pr28243.c index d096399..3fc8b7e 100644 --- a/gcc/testsuite/gcc.dg/pr28243.c +++ b/gcc/testsuite/gcc.dg/pr28243.c @@ -4,7 +4,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target fpic } */ /* { dg-options "-O2 -ftracer -fPIC" } */ -/* { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } { "*" } { "" } } */ +/* { dg-skip-if "requires unsupported run-time relocation" { spu-*-* } } */ struct displayfuncs { void (*init) (); diff --git a/gcc/testsuite/gcc.dg/pr35045.c b/gcc/testsuite/gcc.dg/pr35045.c index bcd01d7..626bde4 100644 --- a/gcc/testsuite/gcc.dg/pr35045.c +++ b/gcc/testsuite/gcc.dg/pr35045.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && { ia32 && { ! nonpic } } } { "*" } { "" } } */ +/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && { ia32 && { ! nonpic } } } } */ /* { dg-options "-O2 -fgcse-after-reload" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/pr40172-3.c b/gcc/testsuite/gcc.dg/pr40172-3.c index ea74fce..c44707c 100644 --- a/gcc/testsuite/gcc.dg/pr40172-3.c +++ b/gcc/testsuite/gcc.dg/pr40172-3.c @@ -1,6 +1,6 @@ /* PR middle-end/40172 */ /* { dg-do compile */ -/* { dg-xfail-if "" { "*-*-*" } { "*" } { "" } } */ +/* { dg-xfail-if "" { "*-*-*" } } */ /* { dg-options "-Wall -W -Werror -Wlogical-op" } */ extern int xxx; diff --git a/gcc/testsuite/gcc.dg/pr41241.c b/gcc/testsuite/gcc.dg/pr41241.c index 893353b..8ba92ab 100644 --- a/gcc/testsuite/gcc.dg/pr41241.c +++ b/gcc/testsuite/gcc.dg/pr41241.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fcompare-debug -g" } */ /* { dg-options "-O2 -fcompare-debug -g -march=i586 -mtune=i586 -fomit-frame-pointer" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ typedef struct { int t1; int t2; int t3; } *T; typedef struct { int s; } S; diff --git a/gcc/testsuite/gcc.dg/pr41345.c b/gcc/testsuite/gcc.dg/pr41345.c index b2c72c7..cb08091 100644 --- a/gcc/testsuite/gcc.dg/pr41345.c +++ b/gcc/testsuite/gcc.dg/pr41345.c @@ -1,7 +1,7 @@ /* PR bootstrap/41345 */ /* { dg-do compile } */ /* { dg-options "-O2 -g -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ void foo (int *x) diff --git a/gcc/testsuite/gcc.dg/pr42629.c b/gcc/testsuite/gcc.dg/pr42629.c index 40e9298..bb74221 100644 --- a/gcc/testsuite/gcc.dg/pr42629.c +++ b/gcc/testsuite/gcc.dg/pr42629.c @@ -4,7 +4,7 @@ /* { dg-options "-O1 -fsched-pressure -fschedule-insns -fcompare-debug" { target scheduling } } */ /* { dg-options "-O1 -fcompare-debug" { target { ! scheduling } } } */ /* { dg-require-effective-target int32plus } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ int lzo_adler32(int adler, char *buf) { diff --git a/gcc/testsuite/gcc.dg/pr42630.c b/gcc/testsuite/gcc.dg/pr42630.c index 5685637..08427ab 100644 --- a/gcc/testsuite/gcc.dg/pr42630.c +++ b/gcc/testsuite/gcc.dg/pr42630.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O1 -fvariable-expansion-in-unroller -funroll-loops -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ int sum(int *buf, int len) { diff --git a/gcc/testsuite/gcc.dg/pr42631.c b/gcc/testsuite/gcc.dg/pr42631.c index 18fb67d..9dd51a2 100644 --- a/gcc/testsuite/gcc.dg/pr42631.c +++ b/gcc/testsuite/gcc.dg/pr42631.c @@ -15,7 +15,7 @@ /* { dg-do compile } */ /* { dg-options "-g -O1 -funroll-loops -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ void foo() { diff --git a/gcc/testsuite/gcc.dg/pr42719.c b/gcc/testsuite/gcc.dg/pr42719.c index 06adf52..a44b835 100644 --- a/gcc/testsuite/gcc.dg/pr42719.c +++ b/gcc/testsuite/gcc.dg/pr42719.c @@ -1,7 +1,7 @@ /* PR tree-optimization/42719 */ /* { dg-do compile } */ /* { dg-options "-O2 -ftracer -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ int *v; diff --git a/gcc/testsuite/gcc.dg/pr42728.c b/gcc/testsuite/gcc.dg/pr42728.c index 8bd7b06..3ee919b 100644 --- a/gcc/testsuite/gcc.dg/pr42728.c +++ b/gcc/testsuite/gcc.dg/pr42728.c @@ -1,7 +1,7 @@ /* PR debug/42728 */ /* { dg-do compile } */ /* { dg-options "-O1 -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ void foo (char *a) diff --git a/gcc/testsuite/gcc.dg/pr42889.c b/gcc/testsuite/gcc.dg/pr42889.c index b518b20..a8e9e60 100644 --- a/gcc/testsuite/gcc.dg/pr42889.c +++ b/gcc/testsuite/gcc.dg/pr42889.c @@ -1,7 +1,7 @@ /* PR rtl-optimization/42889 */ /* { dg-do compile } */ /* { dg-options "-O -fgcse -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ extern int A[], B[]; diff --git a/gcc/testsuite/gcc.dg/pr42916.c b/gcc/testsuite/gcc.dg/pr42916.c index c2e69e3..bbe4436 100644 --- a/gcc/testsuite/gcc.dg/pr42916.c +++ b/gcc/testsuite/gcc.dg/pr42916.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O1 -funroll-loops -ftree-vectorize -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ int seed; diff --git a/gcc/testsuite/gcc.dg/pr43084.c b/gcc/testsuite/gcc.dg/pr43084.c index df55100..2afc484 100644 --- a/gcc/testsuite/gcc.dg/pr43084.c +++ b/gcc/testsuite/gcc.dg/pr43084.c @@ -1,7 +1,7 @@ /* PR debug/43084 */ /* { dg-do compile } */ /* { dg-options "-O1 -fipa-struct-reorg -fwhole-program -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ struct S { diff --git a/gcc/testsuite/gcc.dg/pr43670.c b/gcc/testsuite/gcc.dg/pr43670.c index 19504b7..45088fe 100644 --- a/gcc/testsuite/gcc.dg/pr43670.c +++ b/gcc/testsuite/gcc.dg/pr43670.c @@ -1,7 +1,7 @@ /* PR debug/43670 */ /* { dg-do compile } */ /* { dg-options "-O -ftree-vrp -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/pr44023.c b/gcc/testsuite/gcc.dg/pr44023.c index 344ca28..90f8553 100644 --- a/gcc/testsuite/gcc.dg/pr44023.c +++ b/gcc/testsuite/gcc.dg/pr44023.c @@ -3,7 +3,7 @@ /* { dg-options "-fcompare-debug -O2" } */ /* { dg-options "-fcompare-debug -O2 -mcpu=ev67" { target alpha*-*-* } } */ /* { dg-require-effective-target int32plus } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ void foo (unsigned f, long v, unsigned *w, unsigned a, unsigned b, unsigned e, unsigned c, unsigned d) diff --git a/gcc/testsuite/gcc.dg/pr44606.c b/gcc/testsuite/gcc.dg/pr44606.c index 1d0848e..13cc3ef 100644 --- a/gcc/testsuite/gcc.dg/pr44606.c +++ b/gcc/testsuite/gcc.dg/pr44606.c @@ -1,7 +1,7 @@ /* PR target/44606 */ /* { dg-do run } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "requires io" { freestanding } { "*" } { "" } } */ +/* { dg-skip-if "requires io" { freestanding } } */ #include diff --git a/gcc/testsuite/gcc.dg/pr44971.c b/gcc/testsuite/gcc.dg/pr44971.c index 4314458..2096959 100644 --- a/gcc/testsuite/gcc.dg/pr44971.c +++ b/gcc/testsuite/gcc.dg/pr44971.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fcompare-debug -w" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ typedef struct { diff --git a/gcc/testsuite/gcc.dg/pr45416.c b/gcc/testsuite/gcc.dg/pr45416.c index 5795034..a3f6a75 100644 --- a/gcc/testsuite/gcc.dg/pr45416.c +++ b/gcc/testsuite/gcc.dg/pr45416.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "Skip for Thumb1." { { arm*-*-* } && { arm_thumb1_ok } } { "*" } { "" } } */ +/* { dg-skip-if "Skip for Thumb1." { { arm*-*-* } && { arm_thumb1_ok } } } */ /* { dg-options "-O2" } */ int foo(long long a) diff --git a/gcc/testsuite/gcc.dg/pr45449.c b/gcc/testsuite/gcc.dg/pr45449.c index 1162497..61ddcbc 100644 --- a/gcc/testsuite/gcc.dg/pr45449.c +++ b/gcc/testsuite/gcc.dg/pr45449.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fno-tree-pre -fno-tree-pta -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ struct S { diff --git a/gcc/testsuite/gcc.dg/pr46771.c b/gcc/testsuite/gcc.dg/pr46771.c index e441302..3ba00a1 100644 --- a/gcc/testsuite/gcc.dg/pr46771.c +++ b/gcc/testsuite/gcc.dg/pr46771.c @@ -1,7 +1,7 @@ /* PR debug/46771 */ /* { dg-do compile } */ /* { dg-options "-O -ftree-vectorize -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ unsigned char v[1600]; diff --git a/gcc/testsuite/gcc.dg/pr47684.c b/gcc/testsuite/gcc.dg/pr47684.c index 7cda812..7c66d4d 100644 --- a/gcc/testsuite/gcc.dg/pr47684.c +++ b/gcc/testsuite/gcc.dg/pr47684.c @@ -1,7 +1,7 @@ /* PR debug/47684 */ /* { dg-do compile } */ /* { dg-options "-O3 -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ int in[8][4]; int out[4]; diff --git a/gcc/testsuite/gcc.dg/pr47881.c b/gcc/testsuite/gcc.dg/pr47881.c index bad9806..ef0bd88 100644 --- a/gcc/testsuite/gcc.dg/pr47881.c +++ b/gcc/testsuite/gcc.dg/pr47881.c @@ -1,7 +1,7 @@ /* PR debug/47881 */ /* { dg-do compile } */ /* { dg-options "-O -fcompare-debug -fno-dce -funroll-loops -fno-web" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ extern int data[]; diff --git a/gcc/testsuite/gcc.dg/pr47893.c b/gcc/testsuite/gcc.dg/pr47893.c index 868ae3e..7e1064d 100644 --- a/gcc/testsuite/gcc.dg/pr47893.c +++ b/gcc/testsuite/gcc.dg/pr47893.c @@ -2,7 +2,7 @@ /* { dg-do run } */ /* { dg-options "-O2" } */ /* { dg-additional-options "-mtune=atom -fno-omit-frame-pointer -fno-strict-aliasing" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */ -/* { dg-skip-if "Too much RAM needed" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "Too much RAM needed" { "avr-*-*" } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/pr48768.c b/gcc/testsuite/gcc.dg/pr48768.c index 0ab22ee..990c537 100644 --- a/gcc/testsuite/gcc.dg/pr48768.c +++ b/gcc/testsuite/gcc.dg/pr48768.c @@ -1,7 +1,7 @@ /* PR debug/48768 */ /* { dg-do compile } */ /* { dg-options "-O -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ int a, b; diff --git a/gcc/testsuite/gcc.dg/pr49551.c b/gcc/testsuite/gcc.dg/pr49551.c index 5477615..dda0667 100644 --- a/gcc/testsuite/gcc.dg/pr49551.c +++ b/gcc/testsuite/gcc.dg/pr49551.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O -fdata-sections" } */ -/* { dg-skip-if "-fdata-sections not supported" { hppa*-*-hpux* nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "-fdata-sections not supported" { hppa*-*-hpux* nvptx-*-* } } */ int x = 1; int x; diff --git a/gcc/testsuite/gcc.dg/pr50017.c b/gcc/testsuite/gcc.dg/pr50017.c index feeb4d4..e3f5f1f 100644 --- a/gcc/testsuite/gcc.dg/pr50017.c +++ b/gcc/testsuite/gcc.dg/pr50017.c @@ -1,7 +1,7 @@ /* PR debug/50017 */ /* { dg-do compile } */ /* { dg-options "-O3 -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ struct S { int r, i; }; diff --git a/gcc/testsuite/gcc.dg/pr56023.c b/gcc/testsuite/gcc.dg/pr56023.c index ae0117b..d53a22c 100644 --- a/gcc/testsuite/gcc.dg/pr56023.c +++ b/gcc/testsuite/gcc.dg/pr56023.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ void foo (char *c) diff --git a/gcc/testsuite/gcc.dg/pr56228.c b/gcc/testsuite/gcc.dg/pr56228.c index f1221b9..6e2b4b1 100644 --- a/gcc/testsuite/gcc.dg/pr56228.c +++ b/gcc/testsuite/gcc.dg/pr56228.c @@ -1,7 +1,7 @@ /* PR target/56228 */ /* { dg-do assemble } */ /* { dg-options "-O2" } */ -/* { dg-skip-if "accessing program memory with data memory address" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "accessing program memory with data memory address" { "avr-*-*" } } */ short a[14] = { 1, 2 }; short b[15] = { 3, 4 }; diff --git a/gcc/testsuite/gcc.dg/pr64434.c b/gcc/testsuite/gcc.dg/pr64434.c index 6996871..d70550d 100644 --- a/gcc/testsuite/gcc.dg/pr64434.c +++ b/gcc/testsuite/gcc.dg/pr64434.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O1 -fdump-rtl-expand-details" } */ -/* { dg-skip-if "PR64886" { hppa*-*-hpux* } { "*" } { "" } } */ +/* { dg-skip-if "PR64886" { hppa*-*-hpux* } } */ #define N 256 int a1[N], a2[N], a3[N], a4[N]; diff --git a/gcc/testsuite/gcc.dg/pr64935-1.c b/gcc/testsuite/gcc.dg/pr64935-1.c index 08f2531..c9c67eb 100644 --- a/gcc/testsuite/gcc.dg/pr64935-1.c +++ b/gcc/testsuite/gcc.dg/pr64935-1.c @@ -1,7 +1,7 @@ /* PR rtl-optimization/64935 */ /* { dg-do compile } */ /* { dg-options "-std=gnu89 -Wno-shift-count-overflow -O2 -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ int a[] = {}, b[] = {}, c[] = {}, d[] = {}, e[] = {}, f[] = {}, h[] = {}; int g[] = { 0 }; diff --git a/gcc/testsuite/gcc.dg/pr64935-2.c b/gcc/testsuite/gcc.dg/pr64935-2.c index 8d0a81a..bde658d 100644 --- a/gcc/testsuite/gcc.dg/pr64935-2.c +++ b/gcc/testsuite/gcc.dg/pr64935-2.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-options "-O -fschedule-insns --param=max-sched-ready-insns=0 -fcompare-debug" } */ /* { dg-require-effective-target scheduling } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ void foo (int *data, unsigned len, const int qlp_coeff[], diff --git a/gcc/testsuite/gcc.dg/pr65521.c b/gcc/testsuite/gcc.dg/pr65521.c index be73dfb..49d6a4c 100644 --- a/gcc/testsuite/gcc.dg/pr65521.c +++ b/gcc/testsuite/gcc.dg/pr65521.c @@ -1,7 +1,7 @@ /* PR ipa/65521 */ /* { dg-do compile } */ /* { dg-options "-O2 -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ struct S { int s; }; int f6 (void *, unsigned long); diff --git a/gcc/testsuite/gcc.dg/pr65779.c b/gcc/testsuite/gcc.dg/pr65779.c index 814cb2c..fa6515f 100644 --- a/gcc/testsuite/gcc.dg/pr65779.c +++ b/gcc/testsuite/gcc.dg/pr65779.c @@ -1,7 +1,7 @@ /* PR debug/65779 */ /* { dg-do assemble } */ /* { dg-options "-O2 -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ unsigned long foo (unsigned long x, unsigned char *y, unsigned int z) diff --git a/gcc/testsuite/gcc.dg/pr65980.c b/gcc/testsuite/gcc.dg/pr65980.c index dbd42c5..4babad6 100644 --- a/gcc/testsuite/gcc.dg/pr65980.c +++ b/gcc/testsuite/gcc.dg/pr65980.c @@ -1,7 +1,7 @@ /* PR rtl-optimization/65980 */ /* { dg-do compile } */ /* { dg-options "-O3 -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ typedef struct { int b; } A; void (*a) (int); diff --git a/gcc/testsuite/gcc.dg/pr66688.c b/gcc/testsuite/gcc.dg/pr66688.c index 48b83d7..c7f4ccb 100644 --- a/gcc/testsuite/gcc.dg/pr66688.c +++ b/gcc/testsuite/gcc.dg/pr66688.c @@ -1,7 +1,7 @@ /* PR tree-optimization/66688 */ /* { dg-do compile } */ /* { dg-options "-O2 -fno-reorder-blocks -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ struct fdt_header { unsigned magic; } *a; diff --git a/gcc/testsuite/gcc.dg/pr68671.c b/gcc/testsuite/gcc.dg/pr68671.c index 0950156..9b473ca 100644 --- a/gcc/testsuite/gcc.dg/pr68671.c +++ b/gcc/testsuite/gcc.dg/pr68671.c @@ -1,7 +1,7 @@ /* PR tree-optimization/68671 */ /* { dg-do run } */ /* { dg-options " -O2 -fno-tree-dce" } */ -/* { dg-xfail-if "ptxas crashes" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-xfail-if "ptxas crashes" { nvptx-*-* } } */ volatile int a = -1; volatile int b; diff --git a/gcc/testsuite/gcc.dg/pr70405.c b/gcc/testsuite/gcc.dg/pr70405.c index a2bc96a..25e0576 100644 --- a/gcc/testsuite/gcc.dg/pr70405.c +++ b/gcc/testsuite/gcc.dg/pr70405.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fcompare-debug" } */ /* { dg-additional-options "-mavx512f" { target i?86-*-* x86_64-*-* } } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ typedef short V __attribute__ ((vector_size (32))); diff --git a/gcc/testsuite/gcc.dg/pubtypes-1.c b/gcc/testsuite/gcc.dg/pubtypes-1.c index 3f09646..4d675b8 100644 --- a/gcc/testsuite/gcc.dg/pubtypes-1.c +++ b/gcc/testsuite/gcc.dg/pubtypes-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target *-*-darwin* } } */ /* { dg-options "-O0 -gdwarf-2 -dA -fno-eliminate-unused-debug-types" } */ -/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } { "*" } { "" } } */ +/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } } */ /* { dg-final { scan-assembler "__debug_pubtypes" } } */ /* { dg-final { scan-assembler "long+\[ \t\]+0x\[0-9a-f]+\[ \t\]+\[#;]+\[ \t\]+Pub Info Length" } } */ /* { dg-final { scan-assembler "used_struct\\\\0\"+\[ \t\]+\[#;]+\[ \t\]+external name" } } */ diff --git a/gcc/testsuite/gcc.dg/pubtypes-2.c b/gcc/testsuite/gcc.dg/pubtypes-2.c index b4ba871..3ac3a38 100644 --- a/gcc/testsuite/gcc.dg/pubtypes-2.c +++ b/gcc/testsuite/gcc.dg/pubtypes-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target *-*-darwin* } } */ /* { dg-options "-O0 -gdwarf-2 -dA" } */ -/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } { "*" } { "" } } */ +/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } } */ /* { dg-final { scan-assembler "__debug_pubtypes" } } */ /* { dg-final { scan-assembler "long+\[ \t\]+0x13b+\[ \t\]+\[#;]+\[ \t\]+Pub Info Length" } } */ /* { dg-final { scan-assembler "used_struct\\\\0\"+\[ \t\]+\[#;]+\[ \t\]+external name" } } */ diff --git a/gcc/testsuite/gcc.dg/pubtypes-3.c b/gcc/testsuite/gcc.dg/pubtypes-3.c index cd49535..6fa1940 100644 --- a/gcc/testsuite/gcc.dg/pubtypes-3.c +++ b/gcc/testsuite/gcc.dg/pubtypes-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target *-*-darwin* } } */ /* { dg-options "-O0 -gdwarf-2 -dA" } */ -/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } { "*" } { "" } } */ +/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } } */ /* { dg-final { scan-assembler "__debug_pubtypes" } } */ /* { dg-final { scan-assembler "long+\[ \t\]+0x13b+\[ \t\]+\[#;]+\[ \t\]+Pub Info Length" } } */ /* { dg-final { scan-assembler "used_struct\\\\0\"+\[ \t\]+\[#;]+\[ \t\]+external name" } } */ diff --git a/gcc/testsuite/gcc.dg/pubtypes-4.c b/gcc/testsuite/gcc.dg/pubtypes-4.c index 85e2b5b..b2f520d 100644 --- a/gcc/testsuite/gcc.dg/pubtypes-4.c +++ b/gcc/testsuite/gcc.dg/pubtypes-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target *-*-darwin* } } */ /* { dg-options "-O0 -gdwarf-2 -dA" } */ -/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } { "*" } { "" } } */ +/* { dg-skip-if "Unmatchable assembly" { mmix-*-* } } */ /* { dg-final { scan-assembler "__debug_pubtypes" } } */ /* { dg-final { scan-assembler "long+\[ \t\]+0x172+\[ \t\]+\[#;]+\[ \t\]+Pub Info Length" } } */ /* { dg-final { scan-assembler "used_struct\\\\0\"+\[ \t\]+\[#;]+\[ \t\]+external name" } } */ diff --git a/gcc/testsuite/gcc.dg/setjmp-1.c b/gcc/testsuite/gcc.dg/setjmp-1.c index c5dcef2..600fb7f 100644 --- a/gcc/testsuite/gcc.dg/setjmp-1.c +++ b/gcc/testsuite/gcc.dg/setjmp-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-options "-O -Wclobbered -Wextra -Wall" } */ -/* { dg-skip-if "" { ! nonlocal_goto } { "*" } { "" } } */ +/* { dg-skip-if "" { ! nonlocal_goto } } */ #include diff --git a/gcc/testsuite/gcc.dg/sibcall-6.c b/gcc/testsuite/gcc.dg/sibcall-6.c index 744bf46..8ee72ca 100644 --- a/gcc/testsuite/gcc.dg/sibcall-6.c +++ b/gcc/testsuite/gcc.dg/sibcall-6.c @@ -7,7 +7,7 @@ Contributed by Andreas Bauer */ /* { dg-do run { target epiphany-*-* i?86-*-* x86_64-*-* s390*-*-* } } */ -/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && { ia32 && { ! nonpic } } } { "*" } { "" } } */ +/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && { ia32 && { ! nonpic } } } } */ /* { dg-options "-O2 -foptimize-sibling-calls -fno-ipa-cp" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/sms-12.c b/gcc/testsuite/gcc.dg/sms-12.c index 581e1d7..aef32ee 100644 --- a/gcc/testsuite/gcc.dg/sms-12.c +++ b/gcc/testsuite/gcc.dg/sms-12.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "" { ! { aarch64*-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { aarch64*-*-* } } } */ /* { dg-options "-O2 -fmodulo-sched -funroll-loops -fdump-rtl-sms --param sms-min-sc=1 -fmodulo-sched-allow-regmoves -fPIC" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/special/weak-2.c b/gcc/testsuite/gcc.dg/special/weak-2.c index 91a92e6..b8133e2 100644 --- a/gcc/testsuite/gcc.dg/special/weak-2.c +++ b/gcc/testsuite/gcc.dg/special/weak-2.c @@ -4,7 +4,7 @@ /* NVPTX's implementation of weak is broken when a strong symbol is in a later object file than the weak definition. */ -/* { dg-skip-if "" { "nvptx-*-*" } "*" { "" } } */ +/* { dg-skip-if "" { "nvptx-*-*" } } */ #include diff --git a/gcc/testsuite/gcc.dg/stack-usage-1.c b/gcc/testsuite/gcc.dg/stack-usage-1.c index f10ba20..45d2c7b 100644 --- a/gcc/testsuite/gcc.dg/stack-usage-1.c +++ b/gcc/testsuite/gcc.dg/stack-usage-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-fstack-usage" } */ /* nvptx doesn't have a reg allocator, and hence no stack usage data. */ -/* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { nvptx-*-* } } */ /* This is aimed at testing basic support for -fstack-usage in the back-ends. See the SPARC back-end for example (grep flag_stack_usage_info in sparc.c). diff --git a/gcc/testsuite/gcc.dg/torture/asm-subreg-1.c b/gcc/testsuite/gcc.dg/torture/asm-subreg-1.c index d3a14b2..4090249 100644 --- a/gcc/testsuite/gcc.dg/torture/asm-subreg-1.c +++ b/gcc/testsuite/gcc.dg/torture/asm-subreg-1.c @@ -1,7 +1,7 @@ /* PR middle-end/20491 */ /* { dg-do compile } */ -/* { dg-skip-if "" { hppa*64*-*-* || sparc-*-vxworks* } "*" "" } */ +/* { dg-skip-if "" { hppa*64*-*-* || sparc-*-vxworks* } } */ /* Combine used to introduce invalid subregs for the asm input, and we'd crash later on, when removing all subregs. */ diff --git a/gcc/testsuite/gcc.dg/torture/builtin-math-7.c b/gcc/testsuite/gcc.dg/torture/builtin-math-7.c index 064e286..d4ff1c8 100644 --- a/gcc/testsuite/gcc.dg/torture/builtin-math-7.c +++ b/gcc/testsuite/gcc.dg/torture/builtin-math-7.c @@ -6,7 +6,7 @@ /* { dg-do run } */ /* C6X fails due to -freciprocal-math default. */ -/* { dg-skip-if "" { tic6x-*-* } "*" "" } */ +/* { dg-skip-if "" { tic6x-*-* } } */ /* { dg-add-options ieee } */ /* { dg-require-effective-target large_double } */ diff --git a/gcc/testsuite/gcc.dg/torture/c99-contract-1.c b/gcc/testsuite/gcc.dg/torture/c99-contract-1.c index 78b4cdc..392666f 100644 --- a/gcc/testsuite/gcc.dg/torture/c99-contract-1.c +++ b/gcc/testsuite/gcc.dg/torture/c99-contract-1.c @@ -2,7 +2,7 @@ expressions. */ /* { dg-do run } */ /* { dg-options "-std=c99 -pedantic-errors" } */ -/* { dg-skip-if "ptx only loosely follows IEEE" { "nvptx-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "ptx only loosely follows IEEE" { "nvptx-*-*" } } */ extern void abort (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.dg/torture/pr26565.c b/gcc/testsuite/gcc.dg/torture/pr26565.c index d45272d..12332d4 100644 --- a/gcc/testsuite/gcc.dg/torture/pr26565.c +++ b/gcc/testsuite/gcc.dg/torture/pr26565.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* m32c is already packed. */ -/* { dg-skip-if "" { "m32c-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "" { "m32c-*-*" } } */ void *memcpy(void *dest, const void *src, __SIZE_TYPE__ n); diff --git a/gcc/testsuite/gcc.dg/torture/pr37868.c b/gcc/testsuite/gcc.dg/torture/pr37868.c index 5204c5a..51c38f8 100644 --- a/gcc/testsuite/gcc.dg/torture/pr37868.c +++ b/gcc/testsuite/gcc.dg/torture/pr37868.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-options "-fno-strict-aliasing" } */ -/* { dg-skip-if "unaligned access" { arc*-*-* epiphany-*-* nds32*-*-* sparc*-*-* sh*-*-* tic6x-*-* } "*" "" } */ +/* { dg-skip-if "unaligned access" { arc*-*-* epiphany-*-* nds32*-*-* sparc*-*-* sh*-*-* tic6x-*-* } } */ extern void abort (void); #if (__SIZEOF_INT__ <= 2) diff --git a/gcc/testsuite/gcc.dg/torture/pr45764.c b/gcc/testsuite/gcc.dg/torture/pr45764.c index ac8c075..4847671 100644 --- a/gcc/testsuite/gcc.dg/torture/pr45764.c +++ b/gcc/testsuite/gcc.dg/torture/pr45764.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Too much RAM needed" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "Too much RAM needed" { "avr-*-*" } } */ int result[64][16]; diff --git a/gcc/testsuite/gcc.dg/torture/pr51106-2.c b/gcc/testsuite/gcc.dg/torture/pr51106-2.c index 4209553..aa76a71 100644 --- a/gcc/testsuite/gcc.dg/torture/pr51106-2.c +++ b/gcc/testsuite/gcc.dg/torture/pr51106-2.c @@ -1,7 +1,7 @@ /* PR target/51106 */ /* { dg-do "compile" } */ /* { dg-skip-if "RTL error" { "*-*-*" } { "-fno-fat-lto-objects" } { "" } } */ -/* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc-ibm-aix* } } */ int bar (int x) diff --git a/gcc/testsuite/gcc.dg/torture/pr53922.c b/gcc/testsuite/gcc.dg/torture/pr53922.c index fac054d..b3f2c1a 100644 --- a/gcc/testsuite/gcc.dg/torture/pr53922.c +++ b/gcc/testsuite/gcc.dg/torture/pr53922.c @@ -1,9 +1,9 @@ /* { dg-do run } */ /* { dg-require-weak "" } */ -/* { dg-skip-if "No undefined" { *-*-mingw* } { "*" } { "" } } */ -/* { dg-skip-if "No undefined weak" { *-*-aix* } { "*" } { "" } } */ -/* { dg-skip-if "No undefined weak" { hppa*-*-hpux* && { ! lp64 } } { "*" } { "" } } */ -/* { dg-skip-if "No undefined weak" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "No undefined" { *-*-mingw* } } */ +/* { dg-skip-if "No undefined weak" { *-*-aix* } } */ +/* { dg-skip-if "No undefined weak" { hppa*-*-hpux* && { ! lp64 } } } */ +/* { dg-skip-if "No undefined weak" { nvptx-*-* } } */ /* { dg-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } } */ /* { dg-additional-options "-Wl,-flat_namespace" { target *-*-darwin[89]* } } */ diff --git a/gcc/testsuite/gcc.dg/torture/pr59166.c b/gcc/testsuite/gcc.dg/torture/pr59166.c index 5bdeaa6..43df6be 100644 --- a/gcc/testsuite/gcc.dg/torture/pr59166.c +++ b/gcc/testsuite/gcc.dg/torture/pr59166.c @@ -1,6 +1,6 @@ /* PR rtl-optimization/59166 */ /* { dg-additional-options "-fcompare-debug" } */ -/* { dg-xfail-if "compare-debug failure" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "compare-debug failure" { powerpc-ibm-aix* } } */ int a, b, c, f, g; diff --git a/gcc/testsuite/gcc.dg/torture/pr60092.c b/gcc/testsuite/gcc.dg/torture/pr60092.c index d66e3f2..c23516c 100644 --- a/gcc/testsuite/gcc.dg/torture/pr60092.c +++ b/gcc/testsuite/gcc.dg/torture/pr60092.c @@ -1,7 +1,7 @@ /* { dg-do run } */ /* { dg-require-weak "" } */ /* { dg-skip-if "No undefined weak" { hppa*-*-hpux* && { ! lp64 } } } */ -/* { dg-skip-if "No undefined weak" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "No undefined weak" { nvptx-*-* } } */ /* { dg-additional-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } } */ /* { dg-additional-options "-Wl,-flat_namespace" { target *-*-darwin[89]* } } */ /* { dg-xfail-run-if "posix_memalign modifies first arg on error" { *-*-solaris2.11* } { "-O0" } } */ diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/alloca-1.c b/gcc/testsuite/gcc.dg/torture/stackalign/alloca-1.c index 6a35c9d..2f5d629 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/alloca-1.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/alloca-1.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ /* { dg-require-effective-target alloca } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c b/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c index 41b5c05..d033010 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c @@ -9,8 +9,8 @@ /* arm_hf_eabi: Variadic funcs use Base AAPCS. Normal funcs use VFP variant. avr: Variadic funcs don't pass arguments in registers, while normal funcs do. */ -/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { avr-*-* riscv*-*-* } } "*" "" } */ -/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { nds32*-*-* } "*" "" } */ +/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { avr-*-* riscv*-*-* } } } */ +/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { nds32*-*-* } } */ /* { dg-require-effective-target untyped_assembly } */ diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/global-1.c b/gcc/testsuite/gcc.dg/torture/stackalign/global-1.c index 91983f5..66bec64 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/global-1.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/global-1.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ -/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ +/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/inline-1.c b/gcc/testsuite/gcc.dg/torture/stackalign/inline-1.c index 9f3db03..912581e 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/inline-1.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/inline-1.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ -/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ +/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/inline-2.c b/gcc/testsuite/gcc.dg/torture/stackalign/inline-2.c index f838435..37ee84f 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/inline-2.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/inline-2.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ /* { dg-require-effective-target alloca } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/nested-1.c b/gcc/testsuite/gcc.dg/torture/stackalign/nested-1.c index ea53330..ae9047e 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/nested-1.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/nested-1.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ -/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ +/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/nested-2.c b/gcc/testsuite/gcc.dg/torture/stackalign/nested-2.c index ecfdcb0..d083d66 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/nested-2.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/nested-2.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ -/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ +/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/nested-3.c b/gcc/testsuite/gcc.dg/torture/stackalign/nested-3.c index 631cc92..4bebda6 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/nested-3.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/nested-3.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ /* { dg-require-effective-target alloca } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/nested-4.c b/gcc/testsuite/gcc.dg/torture/stackalign/nested-4.c index 0e94d2c..a46104b 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/nested-4.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/nested-4.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ -/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ +/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-1.c b/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-1.c index 0eef809..459b3df 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-1.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-1.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ -/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ +/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-2.c b/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-2.c index ee3dd74..2aaff40 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-2.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-2.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-3.c b/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-3.c index dc5abf2..ceb6266 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-3.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/pr16660-3.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/ret-struct-1.c b/gcc/testsuite/gcc.dg/torture/stackalign/ret-struct-1.c index bb1b4a1..ff0488d 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/ret-struct-1.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/ret-struct-1.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ -/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ +/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/struct-1.c b/gcc/testsuite/gcc.dg/torture/stackalign/struct-1.c index d0420ae..4e9796f 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/struct-1.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/struct-1.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ -/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ +/* { dg-skip-if "Stack alignment causes use of alloca" { nvptx-*-* } } */ #include "check.h" diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/vararg-1.c b/gcc/testsuite/gcc.dg/torture/stackalign/vararg-1.c index 22d4f77..819b73b 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/vararg-1.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/vararg-1.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ /* { dg-require-effective-target alloca } */ #include diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/vararg-2.c b/gcc/testsuite/gcc.dg/torture/stackalign/vararg-2.c index c678b51..f2d2a09 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/vararg-2.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/vararg-2.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } "*" "" } */ +/* { dg-skip-if "Stack alignment is too small" { hppa*-*-hpux* } } */ /* { dg-require-effective-target alloca } */ #include diff --git a/gcc/testsuite/gcc.dg/tree-prof/val-prof-7.c b/gcc/testsuite/gcc.dg/tree-prof/val-prof-7.c index 5a4e777..c9303e0 100644 --- a/gcc/testsuite/gcc.dg/tree-prof/val-prof-7.c +++ b/gcc/testsuite/gcc.dg/tree-prof/val-prof-7.c @@ -1,5 +1,5 @@ /* { dg-options "-O2 -fdump-ipa-profile -mtune=core2" } */ -/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } } */ char *buffer1; char *buffer2; diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt-2.c b/gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt-2.c index 8dac455..634f1dd 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -fdump-tree-ivopts" } */ -/* { dg-skip-if "PR68644" { hppa*-*-* powerpc*-*-* } { "*" } { "" } } */ +/* { dg-skip-if "PR68644" { hppa*-*-* powerpc*-*-* } } */ void f1 (int *p, unsigned int i) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr47286.c b/gcc/testsuite/gcc.dg/tree-ssa/pr47286.c index 6c42260..91a7da7 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr47286.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr47286.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } } */ /* { dg-options "-O2 -fdump-tree-optimized" } */ struct thread_info { int preempt_count; }; diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-store-ccp-3.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-store-ccp-3.c index 98ec5b8..621fc7c 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-store-ccp-3.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-store-ccp-3.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* Skipped on MIPS GNU/Linux target because __PIC__ can be defined for executables as well as shared libraries. */ -/* { dg-skip-if "" { *-*-darwin* hppa*64*-*-* mips*-*-linux* *-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* hppa*64*-*-* mips*-*-linux* *-*-mingw* } } */ /* { dg-options "-O2 -fno-common -fdump-tree-optimized" } */ const int conststaticvariable; diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-store-ccp-4.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-store-ccp-4.c index d4ee28c..3e16347 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-store-ccp-4.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-store-ccp-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target fpic } */ -/* { dg-skip-if "" { *-*-darwin* *-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* *-*-mingw* } } */ /* { dg-options "-O2 -fno-common -fpic -fdump-tree-optimized" } */ const int conststaticvariable; diff --git a/gcc/testsuite/gcc.dg/ucnid-10.c b/gcc/testsuite/gcc.dg/ucnid-10.c index 1438337..1a2d3e8a 100644 --- a/gcc/testsuite/gcc.dg/ucnid-10.c +++ b/gcc/testsuite/gcc.dg/ucnid-10.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-options "-std=gnu99" } */ /* { dg-require-ascii-locale "" } */ -/* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc-ibm-aix* } } */ #pragma pack(push) #pragma pack(pop, \u00f3) /* { dg-warning "pop, \\\\U000000f3.*push, \\\\U000000f3" } */ diff --git a/gcc/testsuite/gcc.dg/ucnid-11.c b/gcc/testsuite/gcc.dg/ucnid-11.c index 0ef6bfe..d7b729e 100644 --- a/gcc/testsuite/gcc.dg/ucnid-11.c +++ b/gcc/testsuite/gcc.dg/ucnid-11.c @@ -1,7 +1,7 @@ /* { dg-do run } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ -/* { dg-skip-if "" { ! ucn } { "*" } { "" } } */ -/* { dg-skip-if "-fdata-sections not supported" { { hppa*-*-hpux* } && { ! lp64 } } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ +/* { dg-skip-if "" { ! ucn } } */ +/* { dg-skip-if "-fdata-sections not supported" { { hppa*-*-hpux* } && { ! lp64 } } } */ /* { dg-options "-std=c99 -fdata-sections -g" } */ #include "ucnid-3.c" diff --git a/gcc/testsuite/gcc.dg/ucnid-12.c b/gcc/testsuite/gcc.dg/ucnid-12.c index ca50653..987ac1d 100644 --- a/gcc/testsuite/gcc.dg/ucnid-12.c +++ b/gcc/testsuite/gcc.dg/ucnid-12.c @@ -1,7 +1,7 @@ /* { dg-do run } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ -/* { dg-skip-if "" { ! ucn } { "*" } { "" } } */ -/* { dg-skip-if "-ffunction-sections not supported" { { hppa*-*-hpux* } && { ! lp64 } } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ +/* { dg-skip-if "" { ! ucn } } */ +/* { dg-skip-if "-ffunction-sections not supported" { { hppa*-*-hpux* } && { ! lp64 } } } */ /* { dg-options "-std=c99 -ffunction-sections -g" } */ #include "ucnid-4.c" diff --git a/gcc/testsuite/gcc.dg/ucnid-13.c b/gcc/testsuite/gcc.dg/ucnid-13.c index 871f103..2928cd2 100644 --- a/gcc/testsuite/gcc.dg/ucnid-13.c +++ b/gcc/testsuite/gcc.dg/ucnid-13.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-options "-std=gnu99 -Wpacked" } */ /* { dg-require-ascii-locale "" } */ -/* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc-ibm-aix* } } */ int a __attribute__((\u00c0)); /* { dg-warning "'\\\\U000000c0' attribute directive ignored" } */ diff --git a/gcc/testsuite/gcc.dg/ucnid-2.c b/gcc/testsuite/gcc.dg/ucnid-2.c index 577df38..35df3f0 100644 --- a/gcc/testsuite/gcc.dg/ucnid-2.c +++ b/gcc/testsuite/gcc.dg/ucnid-2.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ -/* { dg-skip-if "" { ! ucn } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ +/* { dg-skip-if "" { ! ucn } } */ /* { dg-options "-std=c99 -g" } */ void abort (void); diff --git a/gcc/testsuite/gcc.dg/ucnid-3.c b/gcc/testsuite/gcc.dg/ucnid-3.c index 0f8d46b..7465249 100644 --- a/gcc/testsuite/gcc.dg/ucnid-3.c +++ b/gcc/testsuite/gcc.dg/ucnid-3.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ -/* { dg-skip-if "" { ! ucn } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ +/* { dg-skip-if "" { ! ucn } } */ /* { dg-options "-std=c99 -g" } */ void abort (void); diff --git a/gcc/testsuite/gcc.dg/ucnid-4.c b/gcc/testsuite/gcc.dg/ucnid-4.c index 443dcb9..c8e61c3 100644 --- a/gcc/testsuite/gcc.dg/ucnid-4.c +++ b/gcc/testsuite/gcc.dg/ucnid-4.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ -/* { dg-skip-if "" { ! ucn } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ +/* { dg-skip-if "" { ! ucn } } */ /* { dg-options "-std=c99 -g" } */ void abort (void); diff --git a/gcc/testsuite/gcc.dg/ucnid-5.c b/gcc/testsuite/gcc.dg/ucnid-5.c index a83dc8d..16eedc3f 100644 --- a/gcc/testsuite/gcc.dg/ucnid-5.c +++ b/gcc/testsuite/gcc.dg/ucnid-5.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "No dollar in identfiers" { "avr-*-*" } { "*" } { "" } } */ +/* { dg-skip-if "No dollar in identfiers" { "avr-*-*" } } */ /* { dg-options "-std=c99 -fdollars-in-identifiers -g" } */ void abort (void); diff --git a/gcc/testsuite/gcc.dg/ucnid-6.c b/gcc/testsuite/gcc.dg/ucnid-6.c index 3f67b86..a6f4fd4 100644 --- a/gcc/testsuite/gcc.dg/ucnid-6.c +++ b/gcc/testsuite/gcc.dg/ucnid-6.c @@ -1,6 +1,6 @@ /* { dg-do run } */ -/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "*" } { "" } } */ -/* { dg-skip-if "" { ! ucn } { "*" } { "" } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } } */ +/* { dg-skip-if "" { ! ucn } } */ /* { dg-options "-std=c99 -save-temps -g" } */ void abort (void); diff --git a/gcc/testsuite/gcc.dg/ucnid-7.c b/gcc/testsuite/gcc.dg/ucnid-7.c index b90bf68..fe265af 100644 --- a/gcc/testsuite/gcc.dg/ucnid-7.c +++ b/gcc/testsuite/gcc.dg/ucnid-7.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-options "-std=c99" } */ /* { dg-require-ascii-locale "" } */ -/* { dg-skip-if "" { "powerpc-ibm-aix*" } { "*" } { "" } } */ +/* { dg-skip-if "" { "powerpc-ibm-aix*" } } */ void *p = &\u00e9; /* { dg-error "'\\\\U000000e9' undeclared" } */ void *q = &\u1e00; /* { dg-error "'\\\\U00001e00' undeclared" } */ diff --git a/gcc/testsuite/gcc.dg/ucnid-8.c b/gcc/testsuite/gcc.dg/ucnid-8.c index 450b4d9..369b86a 100644 --- a/gcc/testsuite/gcc.dg/ucnid-8.c +++ b/gcc/testsuite/gcc.dg/ucnid-8.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-options "-std=gnu99 -Wvla" } */ /* { dg-require-ascii-locale "" } */ -/* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc-ibm-aix* } } */ int a __attribute__((__mode__(\u00e9))); /* { dg-error "unknown machine mode '\\\\U000000e9'" } */ struct s1 { int \u00e9 : 0; }; /* { dg-error "zero width for bit-field '\\\\U000000e9'" } */ diff --git a/gcc/testsuite/gcc.dg/ucnid-9.c b/gcc/testsuite/gcc.dg/ucnid-9.c index 6af6d76..ac61c92 100644 --- a/gcc/testsuite/gcc.dg/ucnid-9.c +++ b/gcc/testsuite/gcc.dg/ucnid-9.c @@ -1,8 +1,8 @@ /* Test __func__ with extended identifiers and character set conversions. */ /* { dg-do run } */ -/* { dg-xfail-if "" { "powerpc-ibm-aix*" } { "*" } { "" } } */ -/* { dg-skip-if "" { ! ucn } { "*" } { "" } } */ +/* { dg-xfail-if "" { "powerpc-ibm-aix*" } } */ +/* { dg-skip-if "" { ! ucn } } */ /* { dg-options "-std=c99 -fexec-charset=ISO-8859-1 -g" } */ /* { dg-require-iconv "ISO-8859-1" } */ diff --git a/gcc/testsuite/gcc.dg/unused-5.c b/gcc/testsuite/gcc.dg/unused-5.c index 1b8e100..bdd5c8e 100644 --- a/gcc/testsuite/gcc.dg/unused-5.c +++ b/gcc/testsuite/gcc.dg/unused-5.c @@ -2,7 +2,7 @@ /* { dg-options "-Wunused" } */ /* { dg-final { scan-assembler "string_to_look_for" } } */ /* nvptx outputs strings as array of ints. */ -/* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { nvptx-*-* } } */ /* 'volatile' variables get output and don't produce a warning about being unused. */ diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c index f181bd8..c092848 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target vect_int } */ -/* { dg-skip-if "cost too high" { powerpc*le-*-* } { "*" } { "" } } */ +/* { dg-skip-if "cost too high" { powerpc*le-*-* } } */ #include #include "../../tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c index 5a4e4e9..726c0de 100644 --- a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c +++ b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target vect_int } */ -/* { dg-skip-if "AArch64 tiny code model does not support programs larger than 1MiB" {aarch64_tiny} {"*"} {""} } */ +/* { dg-skip-if "AArch64 tiny code model does not support programs larger than 1MiB" {aarch64_tiny} } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.dg/vect/pr49352.c b/gcc/testsuite/gcc.dg/vect/pr49352.c index 82233b5..b784b8a 100644 --- a/gcc/testsuite/gcc.dg/vect/pr49352.c +++ b/gcc/testsuite/gcc.dg/vect/pr49352.c @@ -1,7 +1,7 @@ /* PR tree-optimization/49352 */ /* { dg-do compile } */ /* { dg-additional-options "-O2 -fcompare-debug" } */ -/* { dg-xfail-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-xfail-if "" { powerpc-ibm-aix* } } */ int foo (int *x, int *y, int n) diff --git a/gcc/testsuite/gcc.dg/vect/vect-82.c b/gcc/testsuite/gcc.dg/vect/vect-82.c index 7f4578e..fcafb36 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-82.c +++ b/gcc/testsuite/gcc.dg/vect/vect-82.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "powerpc and integer vectorization only" { ! { powerpc*-*-* && vect_int } } { "*" } { "" } } */ +/* { dg-skip-if "powerpc and integer vectorization only" { ! { powerpc*-*-* && vect_int } } } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-82_64.c b/gcc/testsuite/gcc.dg/vect/vect-82_64.c index 8dc9d96..358a85a 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-82_64.c +++ b/gcc/testsuite/gcc.dg/vect/vect-82_64.c @@ -1,7 +1,7 @@ /* { dg-do run { target { { powerpc*-*-* && lp64 } && powerpc_altivec_ok } } } */ /* { dg-do compile { target { { powerpc*-*-* && ilp32 } && powerpc_altivec_ok } } } */ /* { dg-additional-options "-mpowerpc64 -maltivec" } */ -/* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc-ibm-aix* } } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-83.c b/gcc/testsuite/gcc.dg/vect/vect-83.c index 49beb31..a300a0a 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-83.c +++ b/gcc/testsuite/gcc.dg/vect/vect-83.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "powerpc and integer vectorization only" { ! { powerpc*-*-* && vect_int } } { "*" } { "" } } */ +/* { dg-skip-if "powerpc and integer vectorization only" { ! { powerpc*-*-* && vect_int } } } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/vect-83_64.c b/gcc/testsuite/gcc.dg/vect/vect-83_64.c index fe985cb..a5e897e 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-83_64.c +++ b/gcc/testsuite/gcc.dg/vect/vect-83_64.c @@ -1,7 +1,7 @@ /* { dg-do run { target { { powerpc*-*-* && lp64 } && powerpc_altivec_ok } } } */ /* { dg-do compile { target { { powerpc*-*-* && ilp32 } && powerpc_altivec_ok } } } */ /* { dg-additional-options "-mpowerpc64 -maltivec" } */ -/* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc-ibm-aix* } } */ #include #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/visibility-11.c b/gcc/testsuite/gcc.dg/visibility-11.c index d616fe9..1bcc424 100644 --- a/gcc/testsuite/gcc.dg/visibility-11.c +++ b/gcc/testsuite/gcc.dg/visibility-11.c @@ -3,7 +3,7 @@ hidden visibility from the first push, so the call didn't use the PLT. */ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ /* { dg-require-visibility "" } */ /* { dg-require-effective-target fpic } */ /* { dg-options "-Os -fpic -mstringop-strategy=libcall" } */ diff --git a/gcc/testsuite/gcc.dg/visibility-14.c b/gcc/testsuite/gcc.dg/visibility-14.c index e1d85f0..9ec7447 100644 --- a/gcc/testsuite/gcc.dg/visibility-14.c +++ b/gcc/testsuite/gcc.dg/visibility-14.c @@ -1,6 +1,6 @@ /* Test that called external functions are marked. */ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ /* { dg-require-visibility "" } */ /* { dg-final { scan-hidden "foo" { xfail *-*-aix* } } } */ diff --git a/gcc/testsuite/gcc.dg/visibility-15.c b/gcc/testsuite/gcc.dg/visibility-15.c index 4e69fa1..db55588 100644 --- a/gcc/testsuite/gcc.dg/visibility-15.c +++ b/gcc/testsuite/gcc.dg/visibility-15.c @@ -1,6 +1,6 @@ /* Test that accessed external functions are marked. */ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ /* { dg-require-visibility "" } */ /* { dg-final { scan-hidden "foo" { xfail *-*-aix* } } } */ diff --git a/gcc/testsuite/gcc.dg/visibility-16.c b/gcc/testsuite/gcc.dg/visibility-16.c index dcd5448..595bcb9 100644 --- a/gcc/testsuite/gcc.dg/visibility-16.c +++ b/gcc/testsuite/gcc.dg/visibility-16.c @@ -1,6 +1,6 @@ /* Test that accessed external variables are marked. */ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ /* { dg-require-visibility "" } */ /* { dg-final { scan-hidden "foo" { xfail *-*-aix* } } } */ diff --git a/gcc/testsuite/gcc.dg/visibility-17.c b/gcc/testsuite/gcc.dg/visibility-17.c index dc90d35..e8f68fe 100644 --- a/gcc/testsuite/gcc.dg/visibility-17.c +++ b/gcc/testsuite/gcc.dg/visibility-17.c @@ -1,6 +1,6 @@ /* Test that external variable whose address is taken are marked. */ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ /* { dg-require-visibility "" } */ /* { dg-final { scan-hidden "foo" { xfail *-*-aix* } } } */ diff --git a/gcc/testsuite/gcc.dg/visibility-18.c b/gcc/testsuite/gcc.dg/visibility-18.c index 653e3b1..4b089f1 100644 --- a/gcc/testsuite/gcc.dg/visibility-18.c +++ b/gcc/testsuite/gcc.dg/visibility-18.c @@ -1,6 +1,6 @@ /* Test that external variable whose address is taken are marked. */ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ /* { dg-require-visibility "" } */ /* { dg-final { scan-hidden "foo" { xfail *-*-aix* } } } */ diff --git a/gcc/testsuite/gcc.dg/visibility-19.c b/gcc/testsuite/gcc.dg/visibility-19.c index 2b0b9be..140294f 100644 --- a/gcc/testsuite/gcc.dg/visibility-19.c +++ b/gcc/testsuite/gcc.dg/visibility-19.c @@ -1,6 +1,6 @@ /* Test that accessed external functions are marked. */ /* { dg-do compile } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ /* { dg-require-visibility "" } */ /* { dg-final { scan-hidden "foo" { xfail *-*-aix* } } } */ diff --git a/gcc/testsuite/gcc.dg/visibility-22.c b/gcc/testsuite/gcc.dg/visibility-22.c index 52f59be..5e8cdad 100644 --- a/gcc/testsuite/gcc.dg/visibility-22.c +++ b/gcc/testsuite/gcc.dg/visibility-22.c @@ -5,7 +5,7 @@ /* This test requires support for undefined weak symbols. This support is not available on hppa*-*-hpux*. The test is skipped rather than xfailed to suppress the warning that would otherwise arise. */ -/* { dg-skip-if "" { "hppa*-*-hpux*" "*-*-aix*" "*-*-darwin*" } "*" { "" } } */ +/* { dg-skip-if "" { "hppa*-*-hpux*" "*-*-aix*" "*-*-darwin*" } } */ extern void foo () __attribute__((weak,visibility("hidden"))); int diff --git a/gcc/testsuite/gcc.dg/visibility-23.c b/gcc/testsuite/gcc.dg/visibility-23.c index 0fa9ef4..2abb605 100644 --- a/gcc/testsuite/gcc.dg/visibility-23.c +++ b/gcc/testsuite/gcc.dg/visibility-23.c @@ -3,7 +3,7 @@ /* { dg-require-visibility "" } */ /* { dg-final { scan-hidden "foo" } } */ /* { dg-options "-O2 -fPIC" { target fpic } } */ -/* { dg-skip-if "" { "hppa*-*-hpux*" "*-*-aix*" "*-*-darwin*" } "*" { "" } } */ +/* { dg-skip-if "" { "hppa*-*-hpux*" "*-*-aix*" "*-*-darwin*" } } */ extern void foo () __attribute__((weak,visibility("hidden"))); int diff --git a/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c b/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c index 6428ea5..8c965f6 100644 --- a/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c +++ b/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/extract-vsx.c b/gcc/testsuite/gcc.dg/vmx/extract-vsx.c index cd34a2ae..9003282 100644 --- a/gcc/testsuite/gcc.dg/vmx/extract-vsx.c +++ b/gcc/testsuite/gcc.dg/vmx/extract-vsx.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c b/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c index 672fc44..6cb59dd 100644 --- a/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c +++ b/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/insert-vsx.c b/gcc/testsuite/gcc.dg/vmx/insert-vsx.c index afb9c70..6885b8c 100644 --- a/gcc/testsuite/gcc.dg/vmx/insert-vsx.c +++ b/gcc/testsuite/gcc.dg/vmx/insert-vsx.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c b/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c index fc81beb..c870c55 100644 --- a/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c +++ b/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/ld-vsx.c b/gcc/testsuite/gcc.dg/vmx/ld-vsx.c index 9d2a529..ce21377 100644 --- a/gcc/testsuite/gcc.dg/vmx/ld-vsx.c +++ b/gcc/testsuite/gcc.dg/vmx/ld-vsx.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c b/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c index 1dd0ca3..222d1db 100644 --- a/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c +++ b/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c b/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c index 4bf3224..dc631f9 100644 --- a/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c +++ b/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c b/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c index 56e0b0e..b01208d 100644 --- a/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c +++ b/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/merge-vsx.c b/gcc/testsuite/gcc.dg/vmx/merge-vsx.c index 40693e9..088b9bd 100644 --- a/gcc/testsuite/gcc.dg/vmx/merge-vsx.c +++ b/gcc/testsuite/gcc.dg/vmx/merge-vsx.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c b/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c index cd389bd..620a31f 100644 --- a/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c +++ b/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/splat-vsx.c b/gcc/testsuite/gcc.dg/vmx/splat-vsx.c index 5a6e7df..54ca3c2 100644 --- a/gcc/testsuite/gcc.dg/vmx/splat-vsx.c +++ b/gcc/testsuite/gcc.dg/vmx/splat-vsx.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c b/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c index a2688fa..4881446 100644 --- a/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c +++ b/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/st-vsx.c b/gcc/testsuite/gcc.dg/vmx/st-vsx.c index ef67de0..d048c53 100644 --- a/gcc/testsuite/gcc.dg/vmx/st-vsx.c +++ b/gcc/testsuite/gcc.dg/vmx/st-vsx.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c b/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c index 26f2c27..65e2f25 100644 --- a/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c +++ b/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/vmx/stl-vsx.c b/gcc/testsuite/gcc.dg/vmx/stl-vsx.c index 9a1cce6..a5b973a 100644 --- a/gcc/testsuite/gcc.dg/vmx/stl-vsx.c +++ b/gcc/testsuite/gcc.dg/vmx/stl-vsx.c @@ -1,4 +1,4 @@ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-maltivec -mabi=altivec -std=gnu99 -mvsx" } */ diff --git a/gcc/testsuite/gcc.dg/weak/weak-1.c b/gcc/testsuite/gcc.dg/weak/weak-1.c index dc34079..6bbc669 100644 --- a/gcc/testsuite/gcc.dg/weak/weak-1.c +++ b/gcc/testsuite/gcc.dg/weak/weak-1.c @@ -1,9 +1,9 @@ /* { dg-do compile } */ /* { dg-require-weak "" } */ /* { dg-options "-fno-common" } */ -/* { dg-skip-if "" { *-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-mingw* } } */ /* NVPTX's definition of weak looks different to normal. */ -/* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { nvptx-*-* } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?a" } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?b" } } */ diff --git a/gcc/testsuite/gcc.dg/weak/weak-12.c b/gcc/testsuite/gcc.dg/weak/weak-12.c index 72f8991..d26fde6 100644 --- a/gcc/testsuite/gcc.dg/weak/weak-12.c +++ b/gcc/testsuite/gcc.dg/weak/weak-12.c @@ -3,7 +3,7 @@ /* { dg-require-weak "" } */ /* { dg-options "" } */ /* NVPTX's weak is applied to the definition, not declaration. */ -/* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { nvptx-*-* } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?foo" } } */ diff --git a/gcc/testsuite/gcc.dg/weak/weak-15.c b/gcc/testsuite/gcc.dg/weak/weak-15.c index d656d21..6364baf 100644 --- a/gcc/testsuite/gcc.dg/weak/weak-15.c +++ b/gcc/testsuite/gcc.dg/weak/weak-15.c @@ -1,9 +1,9 @@ /* { dg-do compile } */ /* { dg-require-weak "" } */ /* { dg-options "-fno-common" } */ -/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { x86_64-*-mingw* } } */ /* NVPTX's weak is applied to the definition, not declaration. */ -/* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { nvptx-*-* } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?a" } } */ /* { dg-final { scan-assembler-not "weak\[^ \t\]*\[ \t\]_?b" } } */ diff --git a/gcc/testsuite/gcc.dg/weak/weak-16.c b/gcc/testsuite/gcc.dg/weak/weak-16.c index b1a08ea..2c58d65 100644 --- a/gcc/testsuite/gcc.dg/weak/weak-16.c +++ b/gcc/testsuite/gcc.dg/weak/weak-16.c @@ -4,9 +4,9 @@ /* { dg-options "-fno-common -Os" } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?kallsyms_token_index" } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?kallsyms_token_table" } } */ -/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { x86_64-*-mingw* } } */ /* NVPTX's weak is applied to the definition, not declaration. */ -/* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { nvptx-*-* } } */ extern int kallsyms_token_index[] __attribute__((weak)); extern int kallsyms_token_table[] __attribute__((weak)); diff --git a/gcc/testsuite/gcc.dg/weak/weak-2.c b/gcc/testsuite/gcc.dg/weak/weak-2.c index cad6e7b..67171cf 100644 --- a/gcc/testsuite/gcc.dg/weak/weak-2.c +++ b/gcc/testsuite/gcc.dg/weak/weak-2.c @@ -1,9 +1,9 @@ /* { dg-do compile } */ /* { dg-require-weak "" } */ /* { dg-options "-fno-common" } */ -/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { x86_64-*-mingw* } } */ /* NVPTX's definition of weak looks different to normal. */ -/* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { nvptx-*-* } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?ffoo1a" } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?ffoo1b" } } */ diff --git a/gcc/testsuite/gcc.dg/weak/weak-3.c b/gcc/testsuite/gcc.dg/weak/weak-3.c index ca6e0b6..a719848 100644 --- a/gcc/testsuite/gcc.dg/weak/weak-3.c +++ b/gcc/testsuite/gcc.dg/weak/weak-3.c @@ -2,7 +2,7 @@ /* { dg-require-alias "" } */ /* { dg-require-weak "" } */ /* { dg-options "-fno-common -Waddress" } */ -/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { x86_64-*-mingw* } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?ffoo1a" } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?ffoo1b" } } */ diff --git a/gcc/testsuite/gcc.dg/weak/weak-4.c b/gcc/testsuite/gcc.dg/weak/weak-4.c index d2d0e68..d0f3283 100644 --- a/gcc/testsuite/gcc.dg/weak/weak-4.c +++ b/gcc/testsuite/gcc.dg/weak/weak-4.c @@ -1,9 +1,9 @@ /* { dg-do compile } */ /* { dg-require-weak "" } */ /* { dg-options "-fno-common" } */ -/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { x86_64-*-mingw* } } */ /* NVPTX's definition of weak looks different to normal. */ -/* { dg-skip-if "" { nvptx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { nvptx-*-* } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?vfoo1a" } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?vfoo1b" } } */ diff --git a/gcc/testsuite/gcc.dg/weak/weak-5.c b/gcc/testsuite/gcc.dg/weak/weak-5.c index 714c9dc..6f80bb0 100644 --- a/gcc/testsuite/gcc.dg/weak/weak-5.c +++ b/gcc/testsuite/gcc.dg/weak/weak-5.c @@ -2,7 +2,7 @@ /* { dg-require-weak "" } */ /* { dg-require-alias "" } */ /* { dg-options "-fno-common" } */ -/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { x86_64-*-mingw* } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?vfoo1a" } } */ /* { dg-final { scan-assembler "weak\[^ \t\]*\[ \t\]_?vfoo1b" } } */ diff --git a/gcc/testsuite/gcc.misc-tests/gcov-13.c b/gcc/testsuite/gcc.misc-tests/gcov-13.c index 2c80559..b42b904 100644 --- a/gcc/testsuite/gcc.misc-tests/gcov-13.c +++ b/gcc/testsuite/gcc.misc-tests/gcov-13.c @@ -4,7 +4,7 @@ /* { dg-options "-fprofile-arcs -ftest-coverage" } */ /* { dg-require-weak "" } */ /* { dg-additional-sources "gcovpart-13b.c" } */ -/* { dg-skip-if "weak ellision not supported" { { hppa*-*-hpux* } && { ! lp64 } } { "*" } { "" } } */ +/* { dg-skip-if "weak ellision not supported" { { hppa*-*-hpux* } && { ! lp64 } } } */ int __attribute__ ((weak)) weak () { diff --git a/gcc/testsuite/gcc.target/arm/frame-pointer-1.c b/gcc/testsuite/gcc.target/arm/frame-pointer-1.c index c288fef..bf9b83c 100644 --- a/gcc/testsuite/gcc.target/arm/frame-pointer-1.c +++ b/gcc/testsuite/gcc.target/arm/frame-pointer-1.c @@ -1,7 +1,7 @@ /* Check local register variables using a register conventionally used as the frame pointer aren't clobbered under high register pressure. */ /* { dg-do run } */ -/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */ +/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ /* { dg-options "-Os -mthumb -fomit-frame-pointer" } */ #include diff --git a/gcc/testsuite/gcc.target/arm/mla-1.c b/gcc/testsuite/gcc.target/arm/mla-1.c index 42101ef..aca009f 100644 --- a/gcc/testsuite/gcc.target/arm/mla-1.c +++ b/gcc/testsuite/gcc.target/arm/mla-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { arm_thumb1 } { "*" } { "" } } */ +/* { dg-skip-if "" { arm_thumb1 } } */ /* { dg-options "-O2" } */ diff --git a/gcc/testsuite/gcc.target/arm/pr56184.C b/gcc/testsuite/gcc.target/arm/pr56184.C index 5d23c40..fd278d3 100644 --- a/gcc/testsuite/gcc.target/arm/pr56184.C +++ b/gcc/testsuite/gcc.target/arm/pr56184.C @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */ +/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ /* { dg-options "-fno-short-enums -O2 -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=softfp -mtune=cortex-a9 -fno-section-anchors" } */ typedef unsigned int size_t; diff --git a/gcc/testsuite/gcc.target/arm/pr58784.c b/gcc/testsuite/gcc.target/arm/pr58784.c index 29a0f73..44528f3 100644 --- a/gcc/testsuite/gcc.target/arm/pr58784.c +++ b/gcc/testsuite/gcc.target/arm/pr58784.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "incompatible options" { arm_thumb1 } { "*" } { "" } } */ +/* { dg-skip-if "incompatible options" { arm_thumb1 } } */ /* { dg-options "-march=armv7-a -mfloat-abi=hard -mfpu=neon -marm -O2" } */ /* { dg-skip-if "need hardfp ABI" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pr59896.c b/gcc/testsuite/gcc.target/arm/pr59896.c index ea6dc24..f431192 100644 --- a/gcc/testsuite/gcc.target/arm/pr59896.c +++ b/gcc/testsuite/gcc.target/arm/pr59896.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */ +/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ /* { dg-options "-mthumb -O2" } */ typedef unsigned int size_t; diff --git a/gcc/testsuite/gcc.target/arm/pr59985.C b/gcc/testsuite/gcc.target/arm/pr59985.C index 97d5915..ecf72b1 100644 --- a/gcc/testsuite/gcc.target/arm/pr59985.C +++ b/gcc/testsuite/gcc.target/arm/pr59985.C @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "incompatible options" { arm_thumb1 } { "*" } { "" } } */ +/* { dg-skip-if "incompatible options" { arm_thumb1 } } */ /* { dg-options "-g -fcompare-debug -O2 -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=hard" } */ /* { dg-skip-if "need hardfp abi" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ diff --git a/gcc/testsuite/gcc.target/arm/stack-red-zone.c b/gcc/testsuite/gcc.target/arm/stack-red-zone.c index 8db2e2c..b29ed0b 100644 --- a/gcc/testsuite/gcc.target/arm/stack-red-zone.c +++ b/gcc/testsuite/gcc.target/arm/stack-red-zone.c @@ -1,5 +1,5 @@ /* No stack red zone. PR38644. */ -/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */ +/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ /* { dg-options "-mthumb -O2" } */ /* { dg-final { scan-assembler "ldrb\[^\n\]*\\n\[\t \]*add\[\t \]*sp" } } */ diff --git a/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c b/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c index e67a627..5c0bc27 100644 --- a/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c +++ b/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c @@ -1,6 +1,6 @@ /* Wrong method to get number of arg reg will cause argument corruption. */ /* { dg-do run } */ -/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */ +/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */ /* { dg-require-effective-target arm_eabi } */ /* { dg-options "-mthumb -O1" } */ diff --git a/gcc/testsuite/gcc.target/i386/align-main-1.c b/gcc/testsuite/gcc.target/i386/align-main-1.c index f62284f..d6ba10b 100644 --- a/gcc/testsuite/gcc.target/i386/align-main-1.c +++ b/gcc/testsuite/gcc.target/i386/align-main-1.c @@ -4,7 +4,7 @@ /* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */ /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */ /* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */ -/* { dg-skip-if "Options about stack-boundary aren't support" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "Options about stack-boundary aren't support" { x86_64-*-mingw* } } */ #include diff --git a/gcc/testsuite/gcc.target/i386/align-main-2.c b/gcc/testsuite/gcc.target/i386/align-main-2.c index b817589..addbbd1 100644 --- a/gcc/testsuite/gcc.target/i386/align-main-2.c +++ b/gcc/testsuite/gcc.target/i386/align-main-2.c @@ -4,7 +4,7 @@ /* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */ /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */ /* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */ -/* { dg-skip-if "Options about stack-boundary aren't support" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "Options about stack-boundary aren't support" { x86_64-*-mingw* } } */ #include #define ALIGNMENT 32 diff --git a/gcc/testsuite/gcc.target/i386/asm-3.c b/gcc/testsuite/gcc.target/i386/asm-3.c index ec37898..206f8c2 100644 --- a/gcc/testsuite/gcc.target/i386/asm-3.c +++ b/gcc/testsuite/gcc.target/i386/asm-3.c @@ -1,6 +1,6 @@ /* PR inline-asm/6806 */ /* { dg-do run } */ -/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } } */ /* { dg-options "-O2" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/pad-4.c b/gcc/testsuite/gcc.target/i386/pad-4.c index 58f55ef..b59c754 100644 --- a/gcc/testsuite/gcc.target/i386/pad-4.c +++ b/gcc/testsuite/gcc.target/i386/pad-4.c @@ -2,7 +2,7 @@ /* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target fpic } */ /* { dg-skip-if "" { *-*-* } { "-march=*" } { "-march=atom" } } */ -/* { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } { "*" } { "" } } */ +/* { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } } */ /* { dg-options "-O2 -fomit-frame-pointer -march=atom -fPIC" } */ /* { dg-final { scan-assembler-times "nop" 8 } } */ /* { dg-final { scan-assembler-not "rep" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pic-1.c b/gcc/testsuite/gcc.target/i386/pic-1.c index 9b7da4d..25b8aae 100644 --- a/gcc/testsuite/gcc.target/i386/pic-1.c +++ b/gcc/testsuite/gcc.target/i386/pic-1.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ia32 } */ /* { dg-require-effective-target fpic } */ -/* { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } { "*" } { "" } } */ +/* { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } } */ /* { dg-options "-fPIC" } */ /* Test verifies that %ebx is no longer fixed when generating PIC code on i686. */ diff --git a/gcc/testsuite/gcc.target/i386/pr25993.c b/gcc/testsuite/gcc.target/i386/pr25993.c index b079e25..1e7e933 100644 --- a/gcc/testsuite/gcc.target/i386/pr25993.c +++ b/gcc/testsuite/gcc.target/i386/pr25993.c @@ -1,5 +1,5 @@ /* { dg-do assemble } */ -/* { dg-skip-if "" { "*-*-darwin*" "*-*-mingw*" } { "*" } { "" } } */ +/* { dg-skip-if "" { "*-*-darwin*" "*-*-mingw*" } } */ /* { dg-options "-std=c99 -x assembler-with-cpp" } */ #ifndef __ASSEMBLER__ diff --git a/gcc/testsuite/gcc.target/i386/pr32000-2.c b/gcc/testsuite/gcc.target/i386/pr32000-2.c index 374b23f..7a3e9f1 100644 --- a/gcc/testsuite/gcc.target/i386/pr32000-2.c +++ b/gcc/testsuite/gcc.target/i386/pr32000-2.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "" { ! { ia32 && dfp } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { ia32 && dfp } } } */ /* { dg-options "-O -msse2 -std=gnu99 -mpreferred-stack-boundary=2" } */ /* { dg-require-effective-target sse2 } */ diff --git a/gcc/testsuite/gcc.target/i386/pr35160.c b/gcc/testsuite/gcc.target/i386/pr35160.c index 259c2a3..d06b8ba 100644 --- a/gcc/testsuite/gcc.target/i386/pr35160.c +++ b/gcc/testsuite/gcc.target/i386/pr35160.c @@ -1,6 +1,6 @@ /* PR inline-asm/35160 */ /* { dg-do run } */ -/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } } */ /* { dg-options "-O2" } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.target/i386/pr39543-2.c b/gcc/testsuite/gcc.target/i386/pr39543-2.c index 7f4e5a4..d0deb6b 100644 --- a/gcc/testsuite/gcc.target/i386/pr39543-2.c +++ b/gcc/testsuite/gcc.target/i386/pr39543-2.c @@ -1,7 +1,7 @@ /* PR inline-asm/39543 */ /* { dg-do compile } */ /* { dg-options "-O3" } */ -/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } } */ float __attribute__ ((aligned (16))) s0[128]; const float s1 = 0.707; diff --git a/gcc/testsuite/gcc.target/i386/pr44130.c b/gcc/testsuite/gcc.target/i386/pr44130.c index 3e50c7b..2ad7409 100644 --- a/gcc/testsuite/gcc.target/i386/pr44130.c +++ b/gcc/testsuite/gcc.target/i386/pr44130.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */ -/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { x86_64-*-mingw* } } */ /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-32,\[\\t \]*%\[re\]?sp" } } */ /* { dg-final { scan-assembler "vmovaps\[\\t \]*%ymm" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr46470.c b/gcc/testsuite/gcc.target/i386/pr46470.c index 8d6b5ca..9e8e731 100644 --- a/gcc/testsuite/gcc.target/i386/pr46470.c +++ b/gcc/testsuite/gcc.target/i386/pr46470.c @@ -1,13 +1,13 @@ /* { dg-do compile } */ /* The pic register save adds unavoidable stack pointer references. */ -/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */ +/* { dg-skip-if "" { ia32 && { ! nonpic } } } */ /* These options are selected to ensure 1 word needs to be allocated on the stack to maintain alignment for the call. This should be transformed to push+pop. We also want to force unwind info updates. */ /* { dg-options "-Os -fomit-frame-pointer -fasynchronous-unwind-tables -mno-red-zone" } */ /* { dg-options "-Os -fomit-frame-pointer -mpreferred-stack-boundary=3 -fasynchronous-unwind-tables" { target ia32 } } */ /* ms_abi has reserved stack-region. */ -/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "" { x86_64-*-mingw* } } */ void f(); void g() { f(); f(); } diff --git a/gcc/testsuite/gcc.target/i386/stack-usage-realign.c b/gcc/testsuite/gcc.target/i386/stack-usage-realign.c index c899606..084d9f3 100644 --- a/gcc/testsuite/gcc.target/i386/stack-usage-realign.c +++ b/gcc/testsuite/gcc.target/i386/stack-usage-realign.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target ia32 } */ -/* { dg-skip-if "no stack realignment" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "no stack realignment" { *-*-darwin* } } */ /* { dg-options "-fstack-usage -msse2 -mforce-drap" } */ typedef int __attribute__((vector_size(16))) vec; diff --git a/gcc/testsuite/gcc.target/i386/stackalign/return-3.c b/gcc/testsuite/gcc.target/i386/stackalign/return-3.c index e32547e..ec534d4 100644 --- a/gcc/testsuite/gcc.target/i386/stackalign/return-3.c +++ b/gcc/testsuite/gcc.target/i386/stackalign/return-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! { ia32 && dfp } } { "*" } { "" } } */ +/* { dg-skip-if "" { ! { ia32 && dfp } } } */ /* { dg-options "-msse -std=gnu99 -mpreferred-stack-boundary=2" } */ /* { dg-require-effective-target sse } */ diff --git a/gcc/testsuite/gcc.target/i386/sw-1.c b/gcc/testsuite/gcc.target/i386/sw-1.c index 1ad4621..aec095e 100644 --- a/gcc/testsuite/gcc.target/i386/sw-1.c +++ b/gcc/testsuite/gcc.target/i386/sw-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mtune=generic -fshrink-wrap -fdump-rtl-pro_and_epilogue" } */ -/* { dg-skip-if "No shrink-wrapping preformed" { x86_64-*-mingw* } { "*" } { "" } } */ +/* { dg-skip-if "No shrink-wrapping preformed" { x86_64-*-mingw* } } */ #include diff --git a/gcc/testsuite/gcc.target/ia64/builtin-fma-2.c b/gcc/testsuite/gcc.target/ia64/builtin-fma-2.c index 16d95b7..a0fae1a 100644 --- a/gcc/testsuite/gcc.target/ia64/builtin-fma-2.c +++ b/gcc/testsuite/gcc.target/ia64/builtin-fma-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "128-bit long double" { *-*-hpux* } { "*" } { "" } } */ +/* { dg-skip-if "128-bit long double" { *-*-hpux* } } */ /* { dg-options "-O" } */ /* Don't confuse the fma insn with the fma in the filename. */ /* { dg-final { scan-assembler-times "fma\[ \]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/m68k/tls-gd-xgot.c b/gcc/testsuite/gcc.target/m68k/tls-gd-xgot.c index 2a4900b..a1babd3 100644 --- a/gcc/testsuite/gcc.target/m68k/tls-gd-xgot.c +++ b/gcc/testsuite/gcc.target/m68k/tls-gd-xgot.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */ +/* { dg-skip-if "" { ! *-linux-* } } */ /* { dg-options "-O2 -fpic -mxgot" } */ /* { dg-final { scan-assembler "#foo@TLSGD,\%\[ad\]\[0-7\]" } } */ /* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */ diff --git a/gcc/testsuite/gcc.target/m68k/tls-gd.c b/gcc/testsuite/gcc.target/m68k/tls-gd.c index 2b69fbd..e49403b 100644 --- a/gcc/testsuite/gcc.target/m68k/tls-gd.c +++ b/gcc/testsuite/gcc.target/m68k/tls-gd.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */ +/* { dg-skip-if "" { ! *-linux-* } } */ /* { dg-options "-O2 -fpic" } */ /* { dg-final { scan-assembler "foo@TLSGD\\(\%a5\\)" } } */ /* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */ diff --git a/gcc/testsuite/gcc.target/m68k/tls-ie-xgot.c b/gcc/testsuite/gcc.target/m68k/tls-ie-xgot.c index d3fbfda..5bcade7 100644 --- a/gcc/testsuite/gcc.target/m68k/tls-ie-xgot.c +++ b/gcc/testsuite/gcc.target/m68k/tls-ie-xgot.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */ +/* { dg-skip-if "" { ! *-linux-* } } */ /* { dg-options "-O2 -mxgot" } */ /* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */ /* { dg-final { scan-assembler "#foo@TLSIE,\%\[ad\]\[0-7\]" } } */ diff --git a/gcc/testsuite/gcc.target/m68k/tls-ie.c b/gcc/testsuite/gcc.target/m68k/tls-ie.c index 2661f9f..f52259d 100644 --- a/gcc/testsuite/gcc.target/m68k/tls-ie.c +++ b/gcc/testsuite/gcc.target/m68k/tls-ie.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */ +/* { dg-skip-if "" { ! *-linux-* } } */ /* { dg-options "-O2" } */ /* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */ /* { dg-final { scan-assembler "foo@TLSIE\\(\%a5\\)" } } */ diff --git a/gcc/testsuite/gcc.target/m68k/tls-ld-xgot-xtls.c b/gcc/testsuite/gcc.target/m68k/tls-ld-xgot-xtls.c index 4817de0..74eb7e4 100644 --- a/gcc/testsuite/gcc.target/m68k/tls-ld-xgot-xtls.c +++ b/gcc/testsuite/gcc.target/m68k/tls-ld-xgot-xtls.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */ +/* { dg-skip-if "" { ! *-linux-* } } */ /* { dg-options "-O2 -fpic -mxgot -mxtls" } */ /* { dg-final { scan-assembler "#foo@TLSLDM,\%\[ad\]\[0-7\]" } } */ /* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */ diff --git a/gcc/testsuite/gcc.target/m68k/tls-ld-xgot.c b/gcc/testsuite/gcc.target/m68k/tls-ld-xgot.c index f95f719..590e905 100644 --- a/gcc/testsuite/gcc.target/m68k/tls-ld-xgot.c +++ b/gcc/testsuite/gcc.target/m68k/tls-ld-xgot.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */ +/* { dg-skip-if "" { ! *-linux-* } } */ /* { dg-options "-O2 -fpic -mxgot" } */ /* { dg-final { scan-assembler "#foo@TLSLDM,\%\[ad\]\[0-7\]" } } */ /* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */ diff --git a/gcc/testsuite/gcc.target/m68k/tls-ld-xtls.c b/gcc/testsuite/gcc.target/m68k/tls-ld-xtls.c index 1bc3eaf..804b156 100644 --- a/gcc/testsuite/gcc.target/m68k/tls-ld-xtls.c +++ b/gcc/testsuite/gcc.target/m68k/tls-ld-xtls.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */ +/* { dg-skip-if "" { ! *-linux-* } } */ /* { dg-options "-O2 -fpic -mxtls" } */ /* { dg-final { scan-assembler "foo@TLSLDM\\(\%a5\\)" } } */ /* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */ diff --git a/gcc/testsuite/gcc.target/m68k/tls-ld.c b/gcc/testsuite/gcc.target/m68k/tls-ld.c index 556a117..af470c9 100644 --- a/gcc/testsuite/gcc.target/m68k/tls-ld.c +++ b/gcc/testsuite/gcc.target/m68k/tls-ld.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */ +/* { dg-skip-if "" { ! *-linux-* } } */ /* { dg-options "-O2 -fpic" } */ /* { dg-final { scan-assembler "foo@TLSLDM\\(\%a5\\)" } } */ /* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */ diff --git a/gcc/testsuite/gcc.target/m68k/tls-le-xtls.c b/gcc/testsuite/gcc.target/m68k/tls-le-xtls.c index 9006115..9d77f0c 100644 --- a/gcc/testsuite/gcc.target/m68k/tls-le-xtls.c +++ b/gcc/testsuite/gcc.target/m68k/tls-le-xtls.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */ +/* { dg-skip-if "" { ! *-linux-* } } */ /* { dg-options "-O2 -mxtls" } */ /* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */ /* { dg-final { scan-assembler "#foo@TLSLE,\%\[ad\]\[0-7\]" } } */ diff --git a/gcc/testsuite/gcc.target/m68k/tls-le.c b/gcc/testsuite/gcc.target/m68k/tls-le.c index 1c0eab2..74234e9 100644 --- a/gcc/testsuite/gcc.target/m68k/tls-le.c +++ b/gcc/testsuite/gcc.target/m68k/tls-le.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */ +/* { dg-skip-if "" { ! *-linux-* } } */ /* { dg-options "-O2" } */ /* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */ /* { dg-final { scan-assembler "lea \\(foo@TLSLE,\%a0\\)" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/20020118-1.c b/gcc/testsuite/gcc.target/powerpc/20020118-1.c index b92dd2a..ea7f861 100644 --- a/gcc/testsuite/gcc.target/powerpc/20020118-1.c +++ b/gcc/testsuite/gcc.target/powerpc/20020118-1.c @@ -1,6 +1,6 @@ /* { dg-do run { target powerpc*-*-* } }*/ /* VxWorks only guarantees 64 bits of alignment (STACK_BOUNDARY == 64). */ -/* { dg-skip-if "" { "powerpc*-*-vxworks*" } { "*" } { "" } } */ +/* { dg-skip-if "" { "powerpc*-*-vxworks*" } } */ /* Force 128-bit stack alignment for eabi targets. */ /* { dg-options "-mno-eabi" { target powerpc*-*-eabi* } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/20030218-1.c b/gcc/testsuite/gcc.target/powerpc/20030218-1.c index 0c5077d..eea227b 100644 --- a/gcc/testsuite/gcc.target/powerpc/20030218-1.c +++ b/gcc/testsuite/gcc.target/powerpc/20030218-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ /* Test vectors that can interconvert without a cast. */ diff --git a/gcc/testsuite/gcc.target/powerpc/20030505.c b/gcc/testsuite/gcc.target/powerpc/20030505.c index 2bef590..1182d8d 100644 --- a/gcc/testsuite/gcc.target/powerpc/20030505.c +++ b/gcc/testsuite/gcc.target/powerpc/20030505.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-W -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ #define __vector __attribute__((vector_size(8))) diff --git a/gcc/testsuite/gcc.target/powerpc/20081204-1.c b/gcc/testsuite/gcc.target/powerpc/20081204-1.c index 8a973d0..31956a1 100644 --- a/gcc/testsuite/gcc.target/powerpc/20081204-1.c +++ b/gcc/testsuite/gcc.target/powerpc/20081204-1.c @@ -2,7 +2,7 @@ TARGET_HARD_FLOAT && !TARGET_FPRS. */ /* { dg-do compile } */ /* { dg-options "-mcpu=750 -mfloat-gprs=single" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ static int comp(const void *a,const void *b){ return (*(float *)a<*(float *)b)-(*(float *)a>*(float *)b); diff --git a/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c b/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c index 52675ba..3d66b1c 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c @@ -1,10 +1,10 @@ /* Test generation of dlmzb for strlen on 405. */ /* Origin: Joseph Myers */ /* { dg-do compile } */ -/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "dlmzb\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c b/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c index e65ba08..e3125e0 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "macchw " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c b/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c index 6263818..49bddc8 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "macchw\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c index 18d448c..8046d77 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "macchwu " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c index 7728c8b..1ccdbe2 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "macchwu\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c index 2211cd1..1e2814d 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "machhw " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c index 4c54f27..3bb6a4d 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "machhw\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c index 44d8ea6..fcb22c1 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "machhwu " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c index 0fc96d1..3a98d1b 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "machhwu\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c index 43ec019..ccc8839 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "maclhw " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c index d79df52..4f0d3a71 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "maclhw\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c index 0d65a5d..14bb3fc 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "maclhwu " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c index 5b148d6..772e6e0 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "maclhwu\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c b/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c index 510e0c8..6794b59 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mulchw " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c b/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c index 14b4df1..0edbf46 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mulchw\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c index a0ecdac..2e6e3b8 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mulchwu " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c index c4da992..1906beb 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mulchwu\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c index efdd8cd..178eadc 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mulhhw " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c index cfa0003..14d9a3b 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mulhhw\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c index c6f7a24..94f803a 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mulhhwu " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c index 9b647e7..cfdc1ba 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mulhhwu\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c index ea28b55..fcd5ef6 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mullhw " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c index 76bbb64..b45bbd2 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mullhw\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c b/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c index 152dfe9..b21f467 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mullhwu " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c b/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c index ff4b8ec..21b3ccd 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "mullhwu\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c b/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c index dd258ef..3df257a 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "nmacchw " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c b/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c index 2a470b9..f3a925a 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "nmacchw\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c index f699a3f..0540eed 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "nmachhw " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c index 07a30c1..64150e2 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "nmachhw\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c b/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c index 91eba84..1268bb8 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "nmaclhw " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c b/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c index 83717a4..3e777ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c @@ -3,7 +3,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-O2 -mcpu=405" } */ -/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } } */ /* { dg-final { scan-assembler "nmaclhw\\. " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c b/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c index 0373466..685f129 100644 --- a/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c +++ b/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c @@ -1,7 +1,7 @@ /* Test generation of dlmzb for strlen on 440. */ /* Origin: Joseph Myers */ /* { dg-do compile } */ -/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ /* { dg-require-effective-target ilp32 } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=440" } } */ /* { dg-options "-O2 -mcpu=440" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-32.c b/gcc/testsuite/gcc.target/powerpc/altivec-32.c index b13b6c9..68fb62f 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-32.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-32.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ /* { dg-options "-O2 -ftree-vectorize -mcpu=power6 -maltivec" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c b/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c index d0b671e..e6cf2f0 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*le-*-* } } */ /* { dg-options "-O -maltivec -mno-vsx" } */ typedef unsigned char V __attribute__((vector_size(16))); diff --git a/gcc/testsuite/gcc.target/powerpc/atomic-p7.c b/gcc/testsuite/gcc.target/powerpc/atomic-p7.c index 657dc16..3f5494f 100644 --- a/gcc/testsuite/gcc.target/powerpc/atomic-p7.c +++ b/gcc/testsuite/gcc.target/powerpc/atomic-p7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/atomic-p8.c b/gcc/testsuite/gcc.target/powerpc/atomic-p8.c index fe7c0e0..6a988e2 100644 --- a/gcc/testsuite/gcc.target/powerpc/atomic-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/atomic-p8.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c b/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c index 0163e73..13b1d14 100644 --- a/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bcd-1.c b/gcc/testsuite/gcc.target/powerpc/bcd-1.c index b4f3fb2..cb3b406 100644 --- a/gcc/testsuite/gcc.target/powerpc/bcd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bcd-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bcd-2.c b/gcc/testsuite/gcc.target/powerpc/bcd-2.c index 70a2f8f..c6e1886 100644 --- a/gcc/testsuite/gcc.target/powerpc/bcd-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bcd-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bcd-3.c b/gcc/testsuite/gcc.target/powerpc/bcd-3.c index 4d47e48..ca12fc9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bcd-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bcd-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1a.c b/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1a.c index 02de1f9..ae2f062 100644 --- a/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1a.c +++ b/gcc/testsuite/gcc.target/powerpc/bmi2-pext64-1a.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-options "-O3 -mcpu=power7" } */ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target powerpc_vsx_ok } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bool2-av.c b/gcc/testsuite/gcc.target/powerpc/bool2-av.c index d5994c7..50bd14a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bool2-av.c +++ b/gcc/testsuite/gcc.target/powerpc/bool2-av.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ /* { dg-options "-O2 -mcpu=power6 -maltivec" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bool2-p5.c b/gcc/testsuite/gcc.target/powerpc/bool2-p5.c index 1f01fdb..28edbae 100644 --- a/gcc/testsuite/gcc.target/powerpc/bool2-p5.c +++ b/gcc/testsuite/gcc.target/powerpc/bool2-p5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O2 -mcpu=power5 -mabi=altivec -mno-altivec -mno-vsx" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bool2-p7.c b/gcc/testsuite/gcc.target/powerpc/bool2-p7.c index 7bfe889..7f1d8c8 100644 --- a/gcc/testsuite/gcc.target/powerpc/bool2-p7.c +++ b/gcc/testsuite/gcc.target/powerpc/bool2-p7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bool2-p8.c b/gcc/testsuite/gcc.target/powerpc/bool2-p8.c index 4001e5b..ac1524c 100644 --- a/gcc/testsuite/gcc.target/powerpc/bool2-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/bool2-p8.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bool3-av.c b/gcc/testsuite/gcc.target/powerpc/bool3-av.c index 36ceacd..cc80d72 100644 --- a/gcc/testsuite/gcc.target/powerpc/bool3-av.c +++ b/gcc/testsuite/gcc.target/powerpc/bool3-av.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ /* { dg-options "-O2 -mcpu=power6 -mabi=altivec -maltivec -mno-vsx" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bool3-p7.c b/gcc/testsuite/gcc.target/powerpc/bool3-p7.c index 75f446e..9a0c006 100644 --- a/gcc/testsuite/gcc.target/powerpc/bool3-p7.c +++ b/gcc/testsuite/gcc.target/powerpc/bool3-p7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bool3-p8.c b/gcc/testsuite/gcc.target/powerpc/bool3-p8.c index e95901a..eba59e0 100644 --- a/gcc/testsuite/gcc.target/powerpc/bool3-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/bool3-p8.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bswap64-4.c b/gcc/testsuite/gcc.target/powerpc/bswap64-4.c index 826999c..1f5ac0e 100644 --- a/gcc/testsuite/gcc.target/powerpc/bswap64-4.c +++ b/gcc/testsuite/gcc.target/powerpc/bswap64-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ /* { dg-options "-O2 -mpowerpc64" } */ /* { dg-require-effective-target ilp32 } */ /* { dg-final { scan-assembler-times "lwbrx" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c index 7cc8fa7..5496b7c 100644 --- a/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=cell" } } */ /* { dg-options "-O2 -maltivec -mcpu=cell" } */ /* { dg-final { scan-assembler-times "lvlx" 19 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c index 25c4e47..dad61d7 100644 --- a/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=cell" } } */ /* { dg-options "-O2 -maltivec -mcpu=cell" } */ /* { dg-final { scan-assembler-times "lvlxl" 19 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c index 6f80861..62a32e0 100644 --- a/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=cell" } } */ /* { dg-options "-O2 -maltivec -mcpu=cell" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c index af1dc80..4f9e2d0 100644 --- a/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=cell" } } */ /* { dg-options "-O2 -maltivec -mcpu=cell" } */ /* { dg-final { scan-assembler-times "lvrxl" 19 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c index 25d8461..b2bdce6 100644 --- a/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=cell" } } */ /* { dg-options "-O2 -maltivec -mcpu=cell" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c index a6d9e5b..d33f066 100644 --- a/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=cell" } } */ /* { dg-options "-O2 -maltivec -mcpu=cell" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c index 16b1d13..7cf3cb8 100644 --- a/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=cell" } } */ /* { dg-options "-O2 -maltivec -mcpu=cell" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c b/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c index 828f441..a617ff8 100644 --- a/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c +++ b/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=cell" } } */ /* { dg-options "-O2 -maltivec -mcpu=cell" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c index a0e3041..684c0f6 100644 --- a/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ void use_cpu_is_builtins (unsigned int *p) diff --git a/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c index e4b460e..234041d 100644 --- a/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c index 0533f45..f3d58b0 100644 --- a/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8 -mno-crypto" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ctz-3.c b/gcc/testsuite/gcc.target/powerpc/ctz-3.c index 468a1f9..2c1316e 100644 --- a/gcc/testsuite/gcc.target/powerpc/ctz-3.c +++ b/gcc/testsuite/gcc.target/powerpc/ctz-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ctz-4.c b/gcc/testsuite/gcc.target/powerpc/ctz-4.c index 2d04a9b..618eced 100644 --- a/gcc/testsuite/gcc.target/powerpc/ctz-4.c +++ b/gcc/testsuite/gcc.target/powerpc/ctz-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c index d7c1553..a22d2da 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c index 96f5d78..e6c4e16 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target p8vector_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c index 18808ef..2551077 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c index 1fa123b..ba71d46 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target p8vector_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c index 25c8a5a..a722b4f 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c index 330cc37..657cefc 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target p8vector_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c index 9806942..bf534fc 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c b/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c index 1b6e3d1..030f245 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target p8vector_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ehreturn.c b/gcc/testsuite/gcc.target/powerpc/ehreturn.c index 558db42..ed58563 100644 --- a/gcc/testsuite/gcc.target/powerpc/ehreturn.c +++ b/gcc/testsuite/gcc.target/powerpc/ehreturn.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O2 -mminimal-toc -mno-multiple" } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ void foo () { diff --git a/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c b/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c index 365dead..8e08878 100644 --- a/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c +++ b/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c b/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c index 829cd40..d930247 100644 --- a/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c +++ b/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fusion.c b/gcc/testsuite/gcc.target/powerpc/fusion.c index ed35006..83dbddc 100644 --- a/gcc/testsuite/gcc.target/powerpc/fusion.c +++ b/gcc/testsuite/gcc.target/powerpc/fusion.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -mtune=power8 -O3" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fusion2.c b/gcc/testsuite/gcc.target/powerpc/fusion2.c index bb74f88..1230e87 100644 --- a/gcc/testsuite/gcc.target/powerpc/fusion2.c +++ b/gcc/testsuite/gcc.target/powerpc/fusion2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*le-*-* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -mtune=power8 -O3" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fusion3.c b/gcc/testsuite/gcc.target/powerpc/fusion3.c index 8eca640..bb35ccd 100644 --- a/gcc/testsuite/gcc.target/powerpc/fusion3.c +++ b/gcc/testsuite/gcc.target/powerpc/fusion3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -mtune=power9 -O3" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fusion4.c b/gcc/testsuite/gcc.target/powerpc/fusion4.c index 7ee064c..2f3ad12 100644 --- a/gcc/testsuite/gcc.target/powerpc/fusion4.c +++ b/gcc/testsuite/gcc.target/powerpc/fusion4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -mtune=power9 -O3 -msoft-float" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c index 0528b4f..ce0d643 100644 --- a/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c @@ -1,5 +1,5 @@ /* { dg-do assemble { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_htm_ok } */ /* { dg-options "-O2 -mhtm -save-temps" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c b/gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c index 691e517..035e119 100644 --- a/gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c +++ b/gcc/testsuite/gcc.target/powerpc/htm-tabort-no-r0.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_htm_ok } */ /* { dg-options "-O2 -mhtm -ffixed-r3 -ffixed-r4 -ffixed-r5 -ffixed-r6 -ffixed-r7 -ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/htm-ttest.c b/gcc/testsuite/gcc.target/powerpc/htm-ttest.c index 29cbd5b..357148c 100644 --- a/gcc/testsuite/gcc.target/powerpc/htm-ttest.c +++ b/gcc/testsuite/gcc.target/powerpc/htm-ttest.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_htm_ok } */ /* { dg-options "-O2 -mhtm" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c b/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c index 5e92814..3c58c1c 100644 --- a/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c @@ -2,7 +2,7 @@ transactional execution with the expected prototypes. */ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_htm_ok } */ /* { dg-options "-O2 -mhtm" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/lhs-1.c b/gcc/testsuite/gcc.target/powerpc/lhs-1.c index 2979711..9fefbbf 100644 --- a/gcc/testsuite/gcc.target/powerpc/lhs-1.c +++ b/gcc/testsuite/gcc.target/powerpc/lhs-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O2 -mcpu=power5" } */ /* { dg-final { scan-assembler-times "nop" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/lhs-2.c b/gcc/testsuite/gcc.target/powerpc/lhs-2.c index a688037..871dbab 100644 --- a/gcc/testsuite/gcc.target/powerpc/lhs-2.c +++ b/gcc/testsuite/gcc.target/powerpc/lhs-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ /* { dg-options "-O2 -mcpu=power6 -msched-groups" } */ /* { dg-final { scan-assembler "ori 1,1,0" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/lhs-3.c b/gcc/testsuite/gcc.target/powerpc/lhs-3.c index 9aab4b3..2132b44 100644 --- a/gcc/testsuite/gcc.target/powerpc/lhs-3.c +++ b/gcc/testsuite/gcc.target/powerpc/lhs-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ /* { dg-final { scan-assembler "ori 2,2,0" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/loop_align.c b/gcc/testsuite/gcc.target/powerpc/loop_align.c index 43ffd9b..670fdc0 100644 --- a/gcc/testsuite/gcc.target/powerpc/loop_align.c +++ b/gcc/testsuite/gcc.target/powerpc/loop_align.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7 -falign-functions=16" } */ /* { dg-final { scan-assembler ".p2align 5,,31" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c b/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c index cb4af8f..de9ff91 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c +++ b/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6x" } } */ /* { dg-options "-O2 -mcpu=power6x -mmfpgpr" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/no-r11-1.c b/gcc/testsuite/gcc.target/powerpc/no-r11-1.c index 94b7988..9b390e3 100644 --- a/gcc/testsuite/gcc.target/powerpc/no-r11-1.c +++ b/gcc/testsuite/gcc.target/powerpc/no-r11-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ +/* { dg-skip-if "" { powerpc_elfv2 } } */ /* { dg-options "-O2 -mno-pointers-to-nested-functions" } */ int diff --git a/gcc/testsuite/gcc.target/powerpc/no-r11-2.c b/gcc/testsuite/gcc.target/powerpc/no-r11-2.c index 214a9df..dc97559 100644 --- a/gcc/testsuite/gcc.target/powerpc/no-r11-2.c +++ b/gcc/testsuite/gcc.target/powerpc/no-r11-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ +/* { dg-skip-if "" { powerpc_elfv2 } } */ /* { dg-options "-O2 -mpointers-to-nested-functions" } */ int diff --git a/gcc/testsuite/gcc.target/powerpc/no-r11-3.c b/gcc/testsuite/gcc.target/powerpc/no-r11-3.c index a4985a3..d252234 100644 --- a/gcc/testsuite/gcc.target/powerpc/no-r11-3.c +++ b/gcc/testsuite/gcc.target/powerpc/no-r11-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ +/* { dg-skip-if "" { powerpc_elfv2 } } */ /* { dg-options "-O2 -mno-pointers-to-nested-functions" } */ extern void ext_call (int (func) (void)); diff --git a/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c b/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c index d9dc641..bbf7d91 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c +++ b/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc64le-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c index f230936..0773aef 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c index 13df148..7e1a251 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c index 57b7512..ff50a9a 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model=dynamic" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c index ae35a6b..4322c38 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model=dynamic" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c index d9040ab..5d9b0ba 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c index c087c92..2e4a73f 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c index d2c868c..c7f01c8 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c b/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c index 0524274..17b73bb 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c index 5ba772f..23663b9 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3 -mvsx-timode -mlra" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c index 39cbf38..5a5f25c 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target p8vector_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c b/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c index de3f1b4..58e1f44 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c index 231bd54..b53ccc5 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O3 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c index 457422c..f7599dc 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c index 741d92b..80ee3aa 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c index e0fe4c4..7917e14 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c index 0603c52..8ad8e0d 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c index a4aee27..ec4e554 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c index e4c2087..af5b590 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O2 -mlra -mvsx-timode" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pack01.c b/gcc/testsuite/gcc.target/powerpc/pack01.c index d0d9a7e..85b40f2 100644 --- a/gcc/testsuite/gcc.target/powerpc/pack01.c +++ b/gcc/testsuite/gcc.target/powerpc/pack01.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target p8vector_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pack02.c b/gcc/testsuite/gcc.target/powerpc/pack02.c index f85d3ff..ee63925 100644 --- a/gcc/testsuite/gcc.target/powerpc/pack02.c +++ b/gcc/testsuite/gcc.target/powerpc/pack02.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-require-effective-target longdouble128 } */ /* { dg-options "-O2 -mhard-float" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pack03.c b/gcc/testsuite/gcc.target/powerpc/pack03.c index dfaf2ef..f6e9943 100644 --- a/gcc/testsuite/gcc.target/powerpc/pack03.c +++ b/gcc/testsuite/gcc.target/powerpc/pack03.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target dfp_hw } */ /* { dg-options "-O2 -mhard-dfp" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/parity-1.c b/gcc/testsuite/gcc.target/powerpc/parity-1.c index 3605055..b0a08ee 100644 --- a/gcc/testsuite/gcc.target/powerpc/parity-1.c +++ b/gcc/testsuite/gcc.target/powerpc/parity-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ilp32 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O2 -mcpu=power5" } */ /* { dg-final { scan-assembler "popcntb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/popcount-1.c b/gcc/testsuite/gcc.target/powerpc/popcount-1.c index dfad50a..b8544c2 100644 --- a/gcc/testsuite/gcc.target/powerpc/popcount-1.c +++ b/gcc/testsuite/gcc.target/powerpc/popcount-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ilp32 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O2 -mcpu=power5" } */ /* { dg-final { scan-assembler "popcntb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/popcount-2.c b/gcc/testsuite/gcc.target/powerpc/popcount-2.c index e1c0f5a..8ecd8f9 100644 --- a/gcc/testsuite/gcc.target/powerpc/popcount-2.c +++ b/gcc/testsuite/gcc.target/powerpc/popcount-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ilp32 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ /* { dg-final { scan-assembler "popcntw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/popcount-3.c b/gcc/testsuite/gcc.target/powerpc/popcount-3.c index fec9c7e..00d9d15 100644 --- a/gcc/testsuite/gcc.target/powerpc/popcount-3.c +++ b/gcc/testsuite/gcc.target/powerpc/popcount-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ /* { dg-final { scan-assembler "popcntd" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c index 2ea79b3..98cfe25 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c index f553630..b08f33b 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math -ffp-contract=off" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c index 49b5574..5fbbe8d 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c index 01761d3..8372c36 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c index 86710b7..b287f14 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O2 -mcpu=power5 -std=c99" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c index 3d36237..0436a8d 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target ilp32 } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O2 -mcpu=power5 -std=c99 -msoft-float" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c b/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c index b85b9c1..57c4b73 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c index ea20f60..2efa952 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c index 11628c9..9e192d1 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c index 2cdbd6a..22d9af9 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5+" } } */ /* { dg-options "-O2 -mcpu=power5+ -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c index 572dec6..02ab12a 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ /* { dg-options "-O2 -mcpu=power6 -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c index 984d3f3..a7bc3e1 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target ilp32 } */ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c index 562e672..dd5fd75 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target ilp32 } */ /* { dg-skip-if "" { powerpc*-*-* } { "-mpowerpc64" } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=750" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c index c44eb08..b59cac3 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c index 5282a5a..a292ba1 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ /* { dg-options "-O3 -mcpu=power6 -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c index fa0b50e..4b0dda8 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target ilp32 } */ /* { dg-require-effective-target powerpc_fprs } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c index 0daf573..0854844 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target ilp32 } */ /* { dg-skip-if "" { powerpc*-*-* } { "-mpowerpc64" } } */ /* { dg-require-effective-target powerpc_fprs } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c index 62ead0a..372b233 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7 -ffast-math -mno-upper-regs-df" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-pow.c b/gcc/testsuite/gcc.target/powerpc/ppc-pow.c index df8930d..3636679 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-pow.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-pow.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* Check for VSX here, even though we don't use VSX to eliminate SPE, PAIRED and other ppc floating point varients. However, we need to also eliminate Darwin, since it doesn't like -mcpu=power6. */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round.c b/gcc/testsuite/gcc.target/powerpc/ppc-round.c index 4fc1679..0cfa0da 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-round.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7 -mno-upper-regs-df" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round2.c b/gcc/testsuite/gcc.target/powerpc/ppc-round2.c index 2b14fb4..938d545 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-round2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round3.c b/gcc/testsuite/gcc.target/powerpc/ppc-round3.c index 33954d7..9ab3870 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-round3.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power9" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-spe.c b/gcc/testsuite/gcc.target/powerpc/ppc-spe.c index 5880e04..753a59e 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-spe.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-spe.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ /* (Test with -O0 so we don't optimize any of them away). */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c index ac1dac9..eb379a0 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-options "-O2 --param case-values-threshold=2" } */ /* { dg-final { scan-assembler "mtctr" } } */ /* { dg-final { scan-assembler "bctr" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c index 4f2efcc..fad7dc4 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-options "-O2 --param case-values-threshold=20" } */ /* { dg-final { scan-assembler-not "mtctr" } } */ /* { dg-final { scan-assembler-not "bctr" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c index 07c85bb..2168830 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=altivec" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c b/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c index 8f8183b..59d4e2d 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=altivec" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-3.c b/gcc/testsuite/gcc.target/powerpc/ppc-target-3.c index d156acc..aecfaba 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-target-3.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=no-altivec" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c index 08e189d..5bdc56a 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */ /* { dg-options "-O2 -ffast-math -mcpu=power5 -mno-altivec -mabi=altivec -fno-unroll-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c index b70003d..921c468 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { *-*-darwin* } } */ /* { dg-options "-O2" } */ typedef __builtin_va_list va_list; diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c index 4e91b1b..d53db11 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { powerpc64-*-* && { lp64 && dfprt } } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */ /* Testcase to check for ABI compliance of parameter passing diff --git a/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c b/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c index f9d4dda..e15a399 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c @@ -1,5 +1,5 @@ // { dg-do compile } -/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ // { dg-options "-O2 -mpowerpc64" } // { dg-final { scan-assembler-not "stfd" } } diff --git a/gcc/testsuite/gcc.target/powerpc/pr42747.c b/gcc/testsuite/gcc.target/powerpc/pr42747.c index f8c1e08..da053ee 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr42747.c +++ b/gcc/testsuite/gcc.target/powerpc/pr42747.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr43154.c b/gcc/testsuite/gcc.target/powerpc/pr43154.c index d330c95..eb81669 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr43154.c +++ b/gcc/testsuite/gcc.target/powerpc/pr43154.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*le-*-* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr47251.c b/gcc/testsuite/gcc.target/powerpc/pr47251.c index 9dee8ba..0347fd4 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr47251.c +++ b/gcc/testsuite/gcc.target/powerpc/pr47251.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -msoft-float -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr47755-2.c b/gcc/testsuite/gcc.target/powerpc/pr47755-2.c index 3d6d4c9..a3e2a2e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr47755-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr47755-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr47755.c b/gcc/testsuite/gcc.target/powerpc/pr47755.c index d5feeca..7de395a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr47755.c +++ b/gcc/testsuite/gcc.target/powerpc/pr47755.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr47862.c b/gcc/testsuite/gcc.target/powerpc/pr47862.c index cc41fbc..4d17522 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr47862.c +++ b/gcc/testsuite/gcc.target/powerpc/pr47862.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr48053-3.c b/gcc/testsuite/gcc.target/powerpc/pr48053-3.c index fb5dae4..a453570 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr48053-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr48053-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr48192.c b/gcc/testsuite/gcc.target/powerpc/pr48192.c index 44f7839..a0ea3ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr48192.c +++ b/gcc/testsuite/gcc.target/powerpc/pr48192.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7 -std=gnu89" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr48226.c b/gcc/testsuite/gcc.target/powerpc/pr48226.c index dca811c..edd71c6 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr48226.c +++ b/gcc/testsuite/gcc.target/powerpc/pr48226.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr48258-1.c b/gcc/testsuite/gcc.target/powerpc/pr48258-1.c index 24a3c7e..79b91b0 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr48258-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr48258-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*le-*-* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math -fno-unroll-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr48258-2.c b/gcc/testsuite/gcc.target/powerpc/pr48258-2.c index 4d46188..ede94e8 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr48258-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr48258-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr48857.c b/gcc/testsuite/gcc.target/powerpc/pr48857.c index 81f157f..25f14b7 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr48857.c +++ b/gcc/testsuite/gcc.target/powerpc/pr48857.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7 -mabi=altivec" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr52199.c b/gcc/testsuite/gcc.target/powerpc/pr52199.c index febccc8..af0799e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr52199.c +++ b/gcc/testsuite/gcc.target/powerpc/pr52199.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7 -fmerge-all-constants" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr52457.c b/gcc/testsuite/gcc.target/powerpc/pr52457.c index 14181c2..8a3e53d 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr52457.c +++ b/gcc/testsuite/gcc.target/powerpc/pr52457.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O1 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr52775.c b/gcc/testsuite/gcc.target/powerpc/pr52775.c index 7f6b2af..48042ba 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr52775.c +++ b/gcc/testsuite/gcc.target/powerpc/pr52775.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power4" } } */ /* { dg-options "-O1 -mcpu=power4" } */ /* { dg-final { scan-assembler-times "fcfid" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr53199.c b/gcc/testsuite/gcc.target/powerpc/pr53199.c index eede1dc..5ed94c2 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr53199.c +++ b/gcc/testsuite/gcc.target/powerpc/pr53199.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ /* { dg-options "-O2 -mcpu=power6 -mavoid-indexed-addresses" } */ /* { dg-final { scan-assembler-times "lwbrx" 12 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr53487.c b/gcc/testsuite/gcc.target/powerpc/pr53487.c index cd60238..706a975 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr53487.c +++ b/gcc/testsuite/gcc.target/powerpc/pr53487.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7 -misel -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr57150.c b/gcc/testsuite/gcc.target/powerpc/pr57150.c index 004822d..7b09be0 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr57150.c +++ b/gcc/testsuite/gcc.target/powerpc/pr57150.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7 -fcaller-saves" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr57744.c b/gcc/testsuite/gcc.target/powerpc/pr57744.c index e53e8d3..0a5247e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr57744.c +++ b/gcc/testsuite/gcc.target/powerpc/pr57744.c @@ -1,5 +1,5 @@ /* { dg-do run { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr57949-1.c b/gcc/testsuite/gcc.target/powerpc/pr57949-1.c index 6c8311e..2049442 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr57949-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr57949-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc_elfv2 } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr57949-2.c b/gcc/testsuite/gcc.target/powerpc/pr57949-2.c index edbbf2a..99be772 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr57949-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr57949-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc_elfv2 } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7 -mcompat-align-parm" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr58673-1.c b/gcc/testsuite/gcc.target/powerpc/pr58673-1.c index 01d53fa..6d1ac36 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr58673-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr58673-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O1" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr58673-2.c b/gcc/testsuite/gcc.target/powerpc/pr58673-2.c index c919094..108fff5 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr58673-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr58673-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3 -funroll-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr59054.c b/gcc/testsuite/gcc.target/powerpc/pr59054.c index c33d937..e98354b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr59054.c +++ b/gcc/testsuite/gcc.target/powerpc/pr59054.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O0" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr60102.c b/gcc/testsuite/gcc.target/powerpc/pr60102.c index 59c0635..c0c4b80 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr60102.c +++ b/gcc/testsuite/gcc.target/powerpc/pr60102.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=8548 -mspe -mabi=spe -g -mfloat-gprs=double" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ double pr60102 (double x, int m) diff --git a/gcc/testsuite/gcc.target/powerpc/pr60137.c b/gcc/testsuite/gcc.target/powerpc/pr60137.c index 4c6cd91..41a4fb2 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr60137.c +++ b/gcc/testsuite/gcc.target/powerpc/pr60137.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3 -mno-vsx" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr60158.c b/gcc/testsuite/gcc.target/powerpc/pr60158.c index e832397..dc9fbdd 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr60158.c +++ b/gcc/testsuite/gcc.target/powerpc/pr60158.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ /* { dg-options "-mcpu=8548 -mno-spe -mfloat-gprs=double -Os -fdata-sections -fpic -mrelocatable" } */ #define NULL 0 diff --git a/gcc/testsuite/gcc.target/powerpc/pr60203.c b/gcc/testsuite/gcc.target/powerpc/pr60203.c index 3a1f56d..d2efa59 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr60203.c +++ b/gcc/testsuite/gcc.target/powerpc/pr60203.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr60676.c b/gcc/testsuite/gcc.target/powerpc/pr60676.c index 0ac9395..28fec8f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr60676.c +++ b/gcc/testsuite/gcc.target/powerpc/pr60676.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr60735.c b/gcc/testsuite/gcc.target/powerpc/pr60735.c index 9bac30b..70d6125 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr60735.c +++ b/gcc/testsuite/gcc.target/powerpc/pr60735.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=8548 -mspe -mabi=spe -O2" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ /* In PR60735, the type _Decimal64 generated an insn not found message. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr64019.c b/gcc/testsuite/gcc.target/powerpc/pr64019.c index a39b2191..d90c480 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr64019.c +++ b/gcc/testsuite/gcc.target/powerpc/pr64019.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -ffast-math -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr64205.c b/gcc/testsuite/gcc.target/powerpc/pr64205.c index f421ec2..7fa987e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr64205.c +++ b/gcc/testsuite/gcc.target/powerpc/pr64205.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ -/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=G5" } } */ /* { dg-options "-O2 -mcpu=G5 -maltivec" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr64505.c b/gcc/testsuite/gcc.target/powerpc/pr64505.c index 319cc08..8601f2d 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr64505.c +++ b/gcc/testsuite/gcc.target/powerpc/pr64505.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */ -/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ /* { dg-options "-O2 -mpowerpc64" } */ /* diff --git a/gcc/testsuite/gcc.target/powerpc/pr65849-1.c b/gcc/testsuite/gcc.target/powerpc/pr65849-1.c index 14b6e38..288fdee 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr65849-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr65849-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2 -mno-upper-regs-df" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr65849-2.c b/gcc/testsuite/gcc.target/powerpc/pr65849-2.c index 83f8b8e..0af6a4a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr65849-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr65849-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-sf" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr67789.c b/gcc/testsuite/gcc.target/powerpc/pr67789.c index 91fd1a1..371d7a3 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr67789.c +++ b/gcc/testsuite/gcc.target/powerpc/pr67789.c @@ -1,6 +1,6 @@ /* { dg-do assemble } */ /* { dg-options "-O2 -msecure-plt -fPIC" } */ -/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } } */ #define FE_TONEAREST 0 #define FE_UPWARD 1 diff --git a/gcc/testsuite/gcc.target/powerpc/pr67808.c b/gcc/testsuite/gcc.target/powerpc/pr67808.c index fdf40df..16b309c 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr67808.c +++ b/gcc/testsuite/gcc.target/powerpc/pr67808.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O1 -mvsx -mlra -mcpu=power7 -mlong-double-128" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr68163.c b/gcc/testsuite/gcc.target/powerpc/pr68163.c index 3953c8c..f984037 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr68163.c +++ b/gcc/testsuite/gcc.target/powerpc/pr68163.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr69548.c b/gcc/testsuite/gcc.target/powerpc/pr69548.c index 439f588..69492bf 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr69548.c +++ b/gcc/testsuite/gcc.target/powerpc/pr69548.c @@ -1,5 +1,5 @@ /* { dg-do assemble { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -Os -mbig" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr70963.c b/gcc/testsuite/gcc.target/powerpc/pr70963.c index 128ebd9..3e64e0e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr70963.c +++ b/gcc/testsuite/gcc.target/powerpc/pr70963.c @@ -1,6 +1,6 @@ /* { dg-do run { target powerpc64*-*-* } } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr71977-1.c b/gcc/testsuite/gcc.target/powerpc/pr71977-1.c index c4413b8..1cb2ec3 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71977-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71977-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr71977-2.c b/gcc/testsuite/gcc.target/powerpc/pr71977-2.c index 8ec1b61..2824deb 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71977-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71977-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr72717.c b/gcc/testsuite/gcc.target/powerpc/pr72717.c index 1446098..92180c1 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr72717.c +++ b/gcc/testsuite/gcc.target/powerpc/pr72717.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr72853.c b/gcc/testsuite/gcc.target/powerpc/pr72853.c index 8eae7d4..8a08608 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr72853.c +++ b/gcc/testsuite/gcc.target/powerpc/pr72853.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O3 -mupper-regs-df -mupper-regs-sf -funroll-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr77289.c b/gcc/testsuite/gcc.target/powerpc/pr77289.c index f8ebf1f..295aa27 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr77289.c +++ b/gcc/testsuite/gcc.target/powerpc/pr77289.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7 -funroll-loops -ffast-math -mlra -mupdate -fno-auto-inc-dec" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr77416.c b/gcc/testsuite/gcc.target/powerpc/pr77416.c index cb7bcc9..39a10de 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr77416.c +++ b/gcc/testsuite/gcc.target/powerpc/pr77416.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { { powerpc*-*-* } && ilp32 } } } */ -/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2" } */ /* { dg-final { scan-assembler-times "addze" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78604.c b/gcc/testsuite/gcc.target/powerpc/pr78604.c index 2331519..23d25c0 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78604.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78604.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fdump-tree-vect-details" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c index 8bff3ce..7024f3b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c index 2f7107b..18dc356 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr80718.c b/gcc/testsuite/gcc.target/powerpc/pr80718.c index 9ac5b1b..b001e2f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80718.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80718.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O3 -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/quad-atomic.c b/gcc/testsuite/gcc.target/powerpc/quad-atomic.c index dc0e3a8..e5824c2 100644 --- a/gcc/testsuite/gcc.target/powerpc/quad-atomic.c +++ b/gcc/testsuite/gcc.target/powerpc/quad-atomic.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target p8vector_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -Wno-shift-overflow" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/recip-5.c b/gcc/testsuite/gcc.target/powerpc/recip-5.c index d5dcaf0..664484f 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-5.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -ftree-vectorize -mrecip=all -ffast-math -mcpu=power7 -fno-unroll-loops" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/recip-6.c b/gcc/testsuite/gcc.target/powerpc/recip-6.c index fbee0c9..26aa2d4 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-6.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-6.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* powerpc*-ibm-aix* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target vsx_hw } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O3 -ftree-vectorize -ffast-math -mrecip=all -mrecip-precision" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/recip-7.c b/gcc/testsuite/gcc.target/powerpc/recip-7.c index 3d84bed..8841e9e 100644 --- a/gcc/testsuite/gcc.target/powerpc/recip-7.c +++ b/gcc/testsuite/gcc.target/powerpc/recip-7.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* powerpc*-ibm-aix* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } } */ /* { dg-require-effective-target ppc_recip_hw } */ /* { dg-options "-O3 -ftree-vectorize -ffast-math -mrecip -mpowerpc-gfxopt -mpowerpc-gpopt -mpopcntb" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c b/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c index 74b4141..d7d5a67 100644 --- a/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c +++ b/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target dfp } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/sd-vsx.c b/gcc/testsuite/gcc.target/powerpc/sd-vsx.c index 87ed77b..3494ef1 100644 --- a/gcc/testsuite/gcc.target/powerpc/sd-vsx.c +++ b/gcc/testsuite/gcc.target/powerpc/sd-vsx.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target dfp } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c b/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c index 09f8134..b492aee 100644 --- a/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c +++ b/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ /* { dg-final { scan-assembler "evstdd" } } */ void foo(void) diff --git a/gcc/testsuite/gcc.target/powerpc/spe1.c b/gcc/testsuite/gcc.target/powerpc/spe1.c index ddbb5a6..f2b093c 100644 --- a/gcc/testsuite/gcc.target/powerpc/spe1.c +++ b/gcc/testsuite/gcc.target/powerpc/spe1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */ -/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } } */ /* (Test with -O0 so we don't optimize any of them away). */ diff --git a/gcc/testsuite/gcc.target/powerpc/tfmode_off.c b/gcc/testsuite/gcc.target/powerpc/tfmode_off.c index f1c2d1e..cbb3d75 100644 --- a/gcc/testsuite/gcc.target/powerpc/tfmode_off.c +++ b/gcc/testsuite/gcc.target/powerpc/tfmode_off.c @@ -1,6 +1,6 @@ /* { dg-do assemble } */ -/* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */ -/* { dg-skip-if "no TFmode" { powerpc-*-eabi* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc-ibm-aix* } } */ +/* { dg-skip-if "no TFmode" { powerpc-*-eabi* } } */ /* { dg-require-effective-target longdouble128 } */ /* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c b/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c index e3a284c..17f01bf 100644 --- a/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c +++ b/gcc/testsuite/gcc.target/powerpc/upper-regs-df.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power7 -O2 -mupper-regs-df" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c b/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c index 401b5c1..8c24679 100644 --- a/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c +++ b/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmp.c b/gcc/testsuite/gcc.target/powerpc/vec-cmp.c index 4bcc15b..aee659d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-cmp.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmp.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc64*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc64*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c index ef34e2b..2f9624d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-di" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-2.c index efad62c..007aeaf 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O2 -mvsx" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-3.c index 62649ce..2df4848 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-4.c index 6380fef..3890cec 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-O2 -mcpu=power9" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-5.c index 95924f3..d85dab9 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-6.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-6.c index 27b8105..667b349 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-7.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-7.c index 11b71b4..6ee7c668 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-8.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-8.c index f10b3b0..9543090 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-8.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-9.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-9.c index e355bce..5932013 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-9.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-9.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-shift.c b/gcc/testsuite/gcc.target/powerpc/vec-shift.c index 80b59a2..eeac927 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-shift.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-shift.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c index 973a7ff..4423852 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c index 7b5ad7d..3a9a772 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c index ff5296c..41faeab 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c index 00cba7e..f639b90 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c index 977eb8e2..8f0607a 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c index 0a2102d..c260f0e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c index 6b49b41..8a85775 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c index bae3da4..c909a88 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7 -Wno-deprecated" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c index 70ad337..2ca4261 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-extract-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-extract-2.c index d4d27ea..27019e4 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-extract-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-extract-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c index 7fdcb0b..cc99504 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O3 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-extract-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-extract-4.c index 3b498f4..2e14581 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-extract-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-extract-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-extract-5.c b/gcc/testsuite/gcc.target/powerpc/vsx-extract-5.c index 1338c6b..7b0d809 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-extract-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-extract-5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-O2 -mcpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-float0.c b/gcc/testsuite/gcc.target/powerpc/vsx-float0.c index 2d6dd75..57613b5 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-float0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-float0.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode.c index 883864e..8f710e5 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c index 96de758..e6f26a8 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c index 2f4a858..3c0e66d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c index d8e0d7d..507854a 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-linux* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math -mveclibabi=mass" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c index eb82c56..a252457 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c index 02aa207..d321970 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c index 0e1da32..50142e8 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ /* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c b/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c index dfe6b0b..2df1719 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode.c index e4b2113..91d55bb 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c index 92553b9..56793a16 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c index fd15931..a35e6db0 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ /* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c index 60a9e3e..903a434 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c index b05c9cd..fb26ead 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -ffast-math" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c index 9afd5daf..54f41f2 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -ftree-vectorize -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c index fcad409..d747d6c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O2 -ftree-vectorize -mcpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c index 65843e9..6566503 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mvsx -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c index f8e644b..fe1590a 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mvsx -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c index 82320e2..0f67596 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c index e463112..a1ac364 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c index a74795d..b65b134 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c index b881585..5b60fda 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c index 216ffb2..0bdaf15 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c index 68451d0..587dbff 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c index cce8f76..36765bf 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c index dee52d1..5f52272 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/warn-1.c b/gcc/testsuite/gcc.target/powerpc/warn-1.c index f345106..b9f744b 100644 --- a/gcc/testsuite/gcc.target/powerpc/warn-1.c +++ b/gcc/testsuite/gcc.target/powerpc/warn-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O -mvsx -mno-altivec" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/warn-2.c b/gcc/testsuite/gcc.target/powerpc/warn-2.c index 02e8268..446ee5a 100644 --- a/gcc/testsuite/gcc.target/powerpc/warn-2.c +++ b/gcc/testsuite/gcc.target/powerpc/warn-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ /* { dg-options "-O -mcpu=power7 -mno-altivec" } */ diff --git a/gcc/testsuite/gcc.target/rx/zero-width-bitfield.c b/gcc/testsuite/gcc.target/rx/zero-width-bitfield.c index 8e477ff..5576f654 100644 --- a/gcc/testsuite/gcc.target/rx/zero-width-bitfield.c +++ b/gcc/testsuite/gcc.target/rx/zero-width-bitfield.c @@ -1,5 +1,5 @@ /* { dg-do run { xfail rx-*-* } } */ -/* { dg-skip-if "skipped until patch for generic zero=width bit-field handling is accepted" { rx-*-* } { "*" } { "" } } */ +/* { dg-skip-if "skipped until patch for generic zero=width bit-field handling is accepted" { rx-*-* } } */ /* { dg-options "-msim" } */ /* Note: The -msim above is actually there to override the default options which do not allow the GCC extension of zero-width bitfields. */ diff --git a/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-F.c b/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-F.c index 01459ea..591c0f6 100644 --- a/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-F.c +++ b/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-F.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-xfail-run-if "" { empty-*-* } { "*" } { "" } } */ +/* { dg-xfail-run-if "" { empty-*-* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-P.c b/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-P.c index d3472ab..73785d9 100644 --- a/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-P.c +++ b/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-P.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-xfail-run-if "" { empty-*-* } { "*" } { "" } } */ +/* { dg-xfail-run-if "" { empty-*-* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-XF.c b/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-XF.c index 0a0a1f8..78001d1 100644 --- a/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-XF.c +++ b/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-XF.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-xfail-run-if "" { *-*-* } { "*" } { "" } } */ +/* { dg-xfail-run-if "" { *-*-* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-XP.c b/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-XP.c index 6f41868..6d6132f 100644 --- a/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-XP.c +++ b/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-exp-XP.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-xfail-run-if "" { *-*-* } { "*" } { "" } } */ +/* { dg-xfail-run-if "" { *-*-* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-nocache-exp-XF.c b/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-nocache-exp-XF.c index dfa1792..b3d17ee 100644 --- a/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-nocache-exp-XF.c +++ b/gcc/testsuite/gcc.test-framework/dg-do-run-xrif-nocache-exp-XF.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-options "-DDEFINED" } */ -/* { dg-xfail-run-if "comment" { def_nocache } { "*" } { "" } } */ +/* { dg-xfail-run-if "comment" { def_nocache } } */ int main () diff --git a/gcc/testsuite/gcc.test-framework/dg-dot-run-sif-exp-P.c b/gcc/testsuite/gcc.test-framework/dg-dot-run-sif-exp-P.c index bf47361..23893d3 100644 --- a/gcc/testsuite/gcc.test-framework/dg-dot-run-sif-exp-P.c +++ b/gcc/testsuite/gcc.test-framework/dg-dot-run-sif-exp-P.c @@ -1,5 +1,5 @@ /* { dg-do run { target { *-*-* && yes } } } */ -/* { dg-skip-if "comment" { no && yes } { "*" } { "" } } */ +/* { dg-skip-if "comment" { no && yes } } */ int main () diff --git a/gcc/testsuite/gcc.test-framework/dg-dot-run-sif-exp-U.c b/gcc/testsuite/gcc.test-framework/dg-dot-run-sif-exp-U.c index 65008c8..a7c1aa1 100644 --- a/gcc/testsuite/gcc.test-framework/dg-dot-run-sif-exp-U.c +++ b/gcc/testsuite/gcc.test-framework/dg-dot-run-sif-exp-U.c @@ -1,5 +1,5 @@ /* { dg-do run { target { *-*-* || no } } } */ -/* { dg-skip-if "comment" { *-*-* && yes } { "*" } { "" } } */ +/* { dg-skip-if "comment" { *-*-* && yes } } */ int main () diff --git a/gcc/testsuite/gcc.test-framework/dg-dot-run-xif-exp-P.c b/gcc/testsuite/gcc.test-framework/dg-dot-run-xif-exp-P.c index eb2af26..1c2da09 100644 --- a/gcc/testsuite/gcc.test-framework/dg-dot-run-xif-exp-P.c +++ b/gcc/testsuite/gcc.test-framework/dg-dot-run-xif-exp-P.c @@ -1,5 +1,5 @@ /* { dg-do run { target { *-*-* && yes } } } */ -/* { dg-xfail-if "comment" { empty-*-* && yes } { "*" } { "" } } */ +/* { dg-xfail-if "comment" { empty-*-* && yes } } */ int main () diff --git a/gcc/testsuite/gcc.test-framework/dg-dot-run-xif-exp-XP.c b/gcc/testsuite/gcc.test-framework/dg-dot-run-xif-exp-XP.c index 59cb768..e508c69 100644 --- a/gcc/testsuite/gcc.test-framework/dg-dot-run-xif-exp-XP.c +++ b/gcc/testsuite/gcc.test-framework/dg-dot-run-xif-exp-XP.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { *-*-* empty-*-* } } } */ -/* { dg-xfail-if "comment" { *-*-* && yes } { "*" } { "" } } */ +/* { dg-xfail-if "comment" { *-*-* && yes } } */ int main () diff --git a/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-F.c b/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-F.c index 3011799..1eae016 100644 --- a/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-F.c +++ b/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-F.c @@ -1,5 +1,5 @@ /* { dg-do run { xfail *-empty-* } } */ -/* { dg-xfail-run-if "" { empty-*-* } { "*" } { "" } } */ +/* { dg-xfail-run-if "" { empty-*-* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-P.c b/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-P.c index 5bb9220..a2c5bdb 100644 --- a/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-P.c +++ b/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-P.c @@ -1,5 +1,5 @@ /* { dg-do run { xfail *-empty-* } } */ -/* { dg-xfail-run-if "" { empty-*-* } { "*" } { "" } } */ +/* { dg-xfail-run-if "" { empty-*-* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-XF.c b/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-XF.c index 854f1cb..514a7d9 100644 --- a/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-XF.c +++ b/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-XF.c @@ -1,5 +1,5 @@ /* { dg-do run { xfail *-*-* } } */ -/* { dg-xfail-run-if "" { empty-*-* } { "*" } { "" } } */ +/* { dg-xfail-run-if "" { empty-*-* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-XP.c b/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-XP.c index f1ac0c1..cfe31c8 100644 --- a/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-XP.c +++ b/gcc/testsuite/gcc.test-framework/dg-dot-run-xrif-exp-XP.c @@ -1,5 +1,5 @@ /* { dg-do run { xfail empty-*-* } } */ -/* { dg-xfail-run-if "" { *-*-* } { "*" } { "" } } */ +/* { dg-xfail-run-if "" { *-*-* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.test-framework/dg-nocache-sif-exp-P.c b/gcc/testsuite/gcc.test-framework/dg-nocache-sif-exp-P.c index 99392e3..c44532b 100644 --- a/gcc/testsuite/gcc.test-framework/dg-nocache-sif-exp-P.c +++ b/gcc/testsuite/gcc.test-framework/dg-nocache-sif-exp-P.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-DNOT_THE_RIGHT_DEFINE" } */ -/* { dg-skip-if "comment" { def_nocache } { "*" } { "" } } */ +/* { dg-skip-if "comment" { def_nocache } } */ int main () diff --git a/gcc/testsuite/gcc.test-framework/dg-nocache-sif-exp-U.c b/gcc/testsuite/gcc.test-framework/dg-nocache-sif-exp-U.c index ffaf49f..ab1a0ac 100644 --- a/gcc/testsuite/gcc.test-framework/dg-nocache-sif-exp-U.c +++ b/gcc/testsuite/gcc.test-framework/dg-nocache-sif-exp-U.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-DDEFINED" } */ -/* { dg-skip-if "comment" { def_nocache } { "*" } { "" } } */ +/* { dg-skip-if "comment" { def_nocache } } */ int main () diff --git a/gcc/testsuite/gcc.test-framework/dg-nocache-xif-exp-P.c b/gcc/testsuite/gcc.test-framework/dg-nocache-xif-exp-P.c index 21e8336..6481958 100644 --- a/gcc/testsuite/gcc.test-framework/dg-nocache-xif-exp-P.c +++ b/gcc/testsuite/gcc.test-framework/dg-nocache-xif-exp-P.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-DNOT_THE_RIGHT_DEFINE" } */ -/* { dg-xfail-if "comment" { def_nocache } { "*" } { "" } } */ +/* { dg-xfail-if "comment" { def_nocache } } */ int main () diff --git a/gcc/testsuite/gcc.test-framework/dg-nocache-xif-exp-XP.c b/gcc/testsuite/gcc.test-framework/dg-nocache-xif-exp-XP.c index 07a55ef..853a785 100644 --- a/gcc/testsuite/gcc.test-framework/dg-nocache-xif-exp-XP.c +++ b/gcc/testsuite/gcc.test-framework/dg-nocache-xif-exp-XP.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-DDEFINED" } */ -/* { dg-xfail-if "comment" { def_nocache } { "*" } { "" } } */ +/* { dg-xfail-if "comment" { def_nocache } } */ int main () diff --git a/gcc/testsuite/gcc.test-framework/gen_directive_tests b/gcc/testsuite/gcc.test-framework/gen_directive_tests old mode 100755 new mode 100644 index 59d97fe..274f530 --- a/gcc/testsuite/gcc.test-framework/gen_directive_tests +++ b/gcc/testsuite/gcc.test-framework/gen_directive_tests @@ -539,13 +539,13 @@ selector_deep() { dgdo_progs compile target "$GOOD_PROG" "dotn${NUM}-exp-U" "$BADXPR" deep_progs "$BADC_PROG" "xiff-100-exp-XF" \ - '/* { dg-xfail-if "match" { ' "{ $GOODXPR }" ' } { "*" } { "" } } */' + '/* { dg-xfail-if "match" { ' "{ $GOODXPR }" ' } } */' deep_progs "$GOOD_PROG" "xifp-100-exp-P" \ - '/* { dg-xfail-if "no match" { ' "{ $BADXPR }" ' } { "*" } { "" } } */' + '/* { dg-xfail-if "no match" { ' "{ $BADXPR }" ' } } */' deep_progs "$BADC_PROG" "xifn-100-exp-U" \ - '/* { dg-skip-if "match" { ' "{ $GOODXPR }" ' } { "*" } { "" } } */' + '/* { dg-skip-if "match" { ' "{ $GOODXPR }" ' } } */' deep_progs "$GOOD_PROG" "xifs-100-exp-P" \ - '/* { dg-skip-if "match" { ' "{ $BADXPR }" ' } { "*" } { "" } } */' + '/* { dg-skip-if "match" { ' "{ $BADXPR }" ' } } */' deep_progs "$GOOD_PROG" "satn-100-exp-P" \ '/* { dg-final { scan-assembler-not "unexpected garbage" { target ' \ "$GOODXPR" ' } } } */' diff --git a/gcc/testsuite/gfortran.dg/char4_iunit_1.f03 b/gcc/testsuite/gfortran.dg/char4_iunit_1.f03 index 7d388ad..0c7b70e 100644 --- a/gcc/testsuite/gfortran.dg/char4_iunit_1.f03 +++ b/gcc/testsuite/gfortran.dg/char4_iunit_1.f03 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! PR37077 Implement Internal Unit I/O for character KIND=4 ! Test case prepared by Jerry DeLisle program char4_iunit_1 diff --git a/gcc/testsuite/gfortran.dg/debug/pr35154-stabs.f b/gcc/testsuite/gfortran.dg/debug/pr35154-stabs.f index fd73199..99f3e2b 100644 --- a/gcc/testsuite/gfortran.dg/debug/pr35154-stabs.f +++ b/gcc/testsuite/gfortran.dg/debug/pr35154-stabs.f @@ -1,6 +1,6 @@ C Test program for common block debugging. G. Helffrich 11 July 2004. C { dg-do compile } -C { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* alpha*-*-* hppa*64*-*-* ia64-*-* *-*-vxworks* } { "*" } { "" } } +C { dg-skip-if "No stabs" { aarch64*-*-* mmix-*-* alpha*-*-* hppa*64*-*-* ia64-*-* *-*-vxworks* } } C { dg-skip-if "No stabs" {*-*-* } { "*" } { "-gstabs" } } common i,j common /label/l,m diff --git a/gcc/testsuite/gfortran.dg/guality/pr41558.f90 b/gcc/testsuite/gfortran.dg/guality/pr41558.f90 index 840b238..3428837 100644 --- a/gcc/testsuite/gfortran.dg/guality/pr41558.f90 +++ b/gcc/testsuite/gfortran.dg/guality/pr41558.f90 @@ -1,6 +1,6 @@ ! PR debug/41558 ! { dg-do run } -! { dg-skip-if "PR testsuite/51875" { { hppa*-*-hpux* } && { ! lp64 } } { "*" } { "" } } +! { dg-skip-if "PR testsuite/51875" { { hppa*-*-hpux* } && { ! lp64 } } } ! { dg-options "-g" } subroutine f (s) diff --git a/gcc/testsuite/gfortran.dg/implicit_class_1.f90 b/gcc/testsuite/gfortran.dg/implicit_class_1.f90 index 380942c..ae68970 100644 --- a/gcc/testsuite/gfortran.dg/implicit_class_1.f90 +++ b/gcc/testsuite/gfortran.dg/implicit_class_1.f90 @@ -1,5 +1,5 @@ ! { dg-do run } -! { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } +! { dg-skip-if "" { powerpc-ibm-aix* } } ! ! PR 56500: [OOP] "IMPLICIT CLASS(...)" wrongly rejected ! diff --git a/gcc/testsuite/gfortran.dg/init_flag_10.f90 b/gcc/testsuite/gfortran.dg/init_flag_10.f90 index 826a34b..dac9418 100644 --- a/gcc/testsuite/gfortran.dg/init_flag_10.f90 +++ b/gcc/testsuite/gfortran.dg/init_flag_10.f90 @@ -1,7 +1,7 @@ ! { dg-do run } ! { dg-options "-finit-real=NAN" } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! ! PR fortran/50619 ! diff --git a/gcc/testsuite/gfortran.dg/init_flag_3.f90 b/gcc/testsuite/gfortran.dg/init_flag_3.f90 index e442617..30e0081 100644 --- a/gcc/testsuite/gfortran.dg/init_flag_3.f90 +++ b/gcc/testsuite/gfortran.dg/init_flag_3.f90 @@ -1,7 +1,7 @@ ! { dg-do run } ! { dg-options "-finit-integer=-1 -finit-logical=false -finit-real=nan" } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } program init_flag_3 call real_test diff --git a/gcc/testsuite/gfortran.dg/int_conv_2.f90 b/gcc/testsuite/gfortran.dg/int_conv_2.f90 index ed7a5f4..c6fc00b 100644 --- a/gcc/testsuite/gfortran.dg/int_conv_2.f90 +++ b/gcc/testsuite/gfortran.dg/int_conv_2.f90 @@ -1,5 +1,5 @@ ! { dg-do compile } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! PR fortran/37930 program test implicit none diff --git a/gcc/testsuite/gfortran.dg/isnan_1.f90 b/gcc/testsuite/gfortran.dg/isnan_1.f90 index 89e4cd3..2a13d3a 100644 --- a/gcc/testsuite/gfortran.dg/isnan_1.f90 +++ b/gcc/testsuite/gfortran.dg/isnan_1.f90 @@ -2,7 +2,7 @@ ! ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! implicit none real :: x diff --git a/gcc/testsuite/gfortran.dg/isnan_2.f90 b/gcc/testsuite/gfortran.dg/isnan_2.f90 index 455ecef..c5360cb 100644 --- a/gcc/testsuite/gfortran.dg/isnan_2.f90 +++ b/gcc/testsuite/gfortran.dg/isnan_2.f90 @@ -3,7 +3,7 @@ ! { dg-do run } ! { dg-options "-fno-range-check" } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! implicit none character(len=1) :: s diff --git a/gcc/testsuite/gfortran.dg/large_real_kind_2.F90 b/gcc/testsuite/gfortran.dg/large_real_kind_2.F90 index 2e3891b..7ed4c30 100644 --- a/gcc/testsuite/gfortran.dg/large_real_kind_2.F90 +++ b/gcc/testsuite/gfortran.dg/large_real_kind_2.F90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-require-effective-target fortran_large_real } -! { dg-xfail-if "" { "*-*-freebsd*" } { "*" } { "" } } +! { dg-xfail-if "" { "*-*-freebsd*" } } ! Testing library calls on large real kinds (larger than kind=8) implicit none diff --git a/gcc/testsuite/gfortran.dg/maxloc_2.f90 b/gcc/testsuite/gfortran.dg/maxloc_2.f90 index deca9fc..1cf79ba 100644 --- a/gcc/testsuite/gfortran.dg/maxloc_2.f90 +++ b/gcc/testsuite/gfortran.dg/maxloc_2.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } real :: a(3), nan, minf, pinf real, allocatable :: c(:) integer :: ia(1) diff --git a/gcc/testsuite/gfortran.dg/maxlocval_2.f90 b/gcc/testsuite/gfortran.dg/maxlocval_2.f90 index 5f6b913..cd985ff 100644 --- a/gcc/testsuite/gfortran.dg/maxlocval_2.f90 +++ b/gcc/testsuite/gfortran.dg/maxlocval_2.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } real :: a(3), nan, minf, pinf real, allocatable :: c(:) logical :: l diff --git a/gcc/testsuite/gfortran.dg/maxlocval_4.f90 b/gcc/testsuite/gfortran.dg/maxlocval_4.f90 index 029abe3..b874332 100644 --- a/gcc/testsuite/gfortran.dg/maxlocval_4.f90 +++ b/gcc/testsuite/gfortran.dg/maxlocval_4.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } real :: a(3,3), b(3), nan, minf, pinf, h logical :: l, l2 logical :: l3(3,3), l4(3,3), l5(3,3) diff --git a/gcc/testsuite/gfortran.dg/minloc_1.f90 b/gcc/testsuite/gfortran.dg/minloc_1.f90 index 25691b0..b857294 100644 --- a/gcc/testsuite/gfortran.dg/minloc_1.f90 +++ b/gcc/testsuite/gfortran.dg/minloc_1.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } real :: a(3), nan, minf, pinf integer :: ia(1) real, allocatable :: c(:) diff --git a/gcc/testsuite/gfortran.dg/minlocval_1.f90 b/gcc/testsuite/gfortran.dg/minlocval_1.f90 index 261cab3..c877f1e 100644 --- a/gcc/testsuite/gfortran.dg/minlocval_1.f90 +++ b/gcc/testsuite/gfortran.dg/minlocval_1.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } real :: a(3), nan, minf, pinf real, allocatable :: c(:) logical :: l diff --git a/gcc/testsuite/gfortran.dg/minlocval_4.f90 b/gcc/testsuite/gfortran.dg/minlocval_4.f90 index c42b019..b371231 100644 --- a/gcc/testsuite/gfortran.dg/minlocval_4.f90 +++ b/gcc/testsuite/gfortran.dg/minlocval_4.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } real :: a(3,3), b(3), nan, minf, pinf, h logical :: l, l2 logical :: l3(3,3), l4(3,3), l5(3,3) diff --git a/gcc/testsuite/gfortran.dg/module_nan.f90 b/gcc/testsuite/gfortran.dg/module_nan.f90 index 5f41514..7e496c0 100644 --- a/gcc/testsuite/gfortran.dg/module_nan.f90 +++ b/gcc/testsuite/gfortran.dg/module_nan.f90 @@ -1,7 +1,7 @@ ! { dg-do run } ! { dg-options "-fno-range-check" } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! ! PR fortran/34318 ! diff --git a/gcc/testsuite/gfortran.dg/namelist_42.f90 b/gcc/testsuite/gfortran.dg/namelist_42.f90 index f15914f..9875d6a 100644 --- a/gcc/testsuite/gfortran.dg/namelist_42.f90 +++ b/gcc/testsuite/gfortran.dg/namelist_42.f90 @@ -1,6 +1,6 @@ ! { dg-do run { target fd_truncate } } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! ! PR fortran/34427 ! diff --git a/gcc/testsuite/gfortran.dg/namelist_43.f90 b/gcc/testsuite/gfortran.dg/namelist_43.f90 index d2f077e..a6e4eb6 100644 --- a/gcc/testsuite/gfortran.dg/namelist_43.f90 +++ b/gcc/testsuite/gfortran.dg/namelist_43.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! ! PR fortran/34427 ! diff --git a/gcc/testsuite/gfortran.dg/nan_1.f90 b/gcc/testsuite/gfortran.dg/nan_1.f90 index 4ff1b87..cfa8505 100644 --- a/gcc/testsuite/gfortran.dg/nan_1.f90 +++ b/gcc/testsuite/gfortran.dg/nan_1.f90 @@ -3,7 +3,7 @@ ! ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! module aux2 interface isnan diff --git a/gcc/testsuite/gfortran.dg/nan_2.f90 b/gcc/testsuite/gfortran.dg/nan_2.f90 index 709b147..9077883 100644 --- a/gcc/testsuite/gfortran.dg/nan_2.f90 +++ b/gcc/testsuite/gfortran.dg/nan_2.f90 @@ -1,7 +1,7 @@ ! { dg-do run } ! { dg-options "-fno-range-check -pedantic" } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! ! PR fortran/34333 ! diff --git a/gcc/testsuite/gfortran.dg/nan_3.f90 b/gcc/testsuite/gfortran.dg/nan_3.f90 index 0a46fdb..aecb42b 100644 --- a/gcc/testsuite/gfortran.dg/nan_3.f90 +++ b/gcc/testsuite/gfortran.dg/nan_3.f90 @@ -1,7 +1,7 @@ ! { dg-do run } ! { dg-options "-fno-range-check" } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! ! PR fortran/34319 ! diff --git a/gcc/testsuite/gfortran.dg/nan_4.f90 b/gcc/testsuite/gfortran.dg/nan_4.f90 index 30e2a49..46aba3e 100644 --- a/gcc/testsuite/gfortran.dg/nan_4.f90 +++ b/gcc/testsuite/gfortran.dg/nan_4.f90 @@ -1,7 +1,7 @@ ! { dg-do compile } ! { dg-options "-std=gnu" } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! ! PR fortran/34398. ! diff --git a/gcc/testsuite/gfortran.dg/nan_5.f90 b/gcc/testsuite/gfortran.dg/nan_5.f90 index be1169d..af77090 100644 --- a/gcc/testsuite/gfortran.dg/nan_5.f90 +++ b/gcc/testsuite/gfortran.dg/nan_5.f90 @@ -4,7 +4,7 @@ ! ! { dg-options "-fno-range-check" } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } implicit none real, parameter :: inf = 2 * huge(inf) diff --git a/gcc/testsuite/gfortran.dg/nan_6.f90 b/gcc/testsuite/gfortran.dg/nan_6.f90 index 8f0af29..f4adcd2 100644 --- a/gcc/testsuite/gfortran.dg/nan_6.f90 +++ b/gcc/testsuite/gfortran.dg/nan_6.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! ! List-directed part of PR fortran/43298 ! and follow up to PR fortran/34319. diff --git a/gcc/testsuite/gfortran.dg/nan_7.f90 b/gcc/testsuite/gfortran.dg/nan_7.f90 index 4c2f62e..4aecfd6 100644 --- a/gcc/testsuite/gfortran.dg/nan_7.f90 +++ b/gcc/testsuite/gfortran.dg/nan_7.f90 @@ -2,7 +2,7 @@ ! { dg-options "-fno-range-check" } ! { dg-require-effective-target fortran_real_16 } ! { dg-require-effective-target fortran_integer_16 } -! { dg-skip-if "" { "powerpc*le-*-*" } { "*" } { "" } } +! { dg-skip-if "" { "powerpc*le-*-*" } } ! PR47293 NAN not correctly read character(len=200) :: str real(16) :: r diff --git a/gcc/testsuite/gfortran.dg/nearest_1.f90 b/gcc/testsuite/gfortran.dg/nearest_1.f90 index ae9e75f..1518e86 100644 --- a/gcc/testsuite/gfortran.dg/nearest_1.f90 +++ b/gcc/testsuite/gfortran.dg/nearest_1.f90 @@ -1,7 +1,7 @@ ! { dg-do run } ! { dg-options "-O0 -ffloat-store" } ! { dg-add-options ieee } -! { dg-skip-if "Denormals not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "Denormals not supported" { spu-*-* } } ! PR fortran/27021 ! Original code submitted by Dominique d'Humieres ! Converted to Dejagnu for the testsuite by Steven G. Kargl diff --git a/gcc/testsuite/gfortran.dg/nearest_3.f90 b/gcc/testsuite/gfortran.dg/nearest_3.f90 index 7d68316..4aa0f4c 100644 --- a/gcc/testsuite/gfortran.dg/nearest_3.f90 +++ b/gcc/testsuite/gfortran.dg/nearest_3.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! ! PR fortran/34209 ! diff --git a/gcc/testsuite/gfortran.dg/pr20257.f90 b/gcc/testsuite/gfortran.dg/pr20257.f90 index aebfc03..03108b9 100644 --- a/gcc/testsuite/gfortran.dg/pr20257.f90 +++ b/gcc/testsuite/gfortran.dg/pr20257.f90 @@ -1,5 +1,5 @@ ! { dg-do run } -! { dg-skip-if "Too big for local store" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "Too big for local store" { spu-*-* } } integer,parameter :: n = 10000 real(8) array(10000) diff --git a/gcc/testsuite/gfortran.dg/pr47614.f b/gcc/testsuite/gfortran.dg/pr47614.f index 52f14c0..2317d72 100644 --- a/gcc/testsuite/gfortran.dg/pr47614.f +++ b/gcc/testsuite/gfortran.dg/pr47614.f @@ -1,5 +1,5 @@ ! { dg-do run { target { powerpc*-*-* } } } -! { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } +! { dg-skip-if "" { powerpc*-*-darwin* } } ! { dg-options "-O3 -funroll-loops -ffast-math -mcpu=power4" } diff --git a/gcc/testsuite/gfortran.dg/read_infnan_1.f90 b/gcc/testsuite/gfortran.dg/read_infnan_1.f90 index c5023e8..7fe2a0a 100644 --- a/gcc/testsuite/gfortran.dg/read_infnan_1.f90 +++ b/gcc/testsuite/gfortran.dg/read_infnan_1.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! PR43298 Fortran library does not read in NaN, NaN(), -Inf, or Inf diff --git a/gcc/testsuite/gfortran.dg/real_const_3.f90 b/gcc/testsuite/gfortran.dg/real_const_3.f90 index c70591d..b214bd0 100644 --- a/gcc/testsuite/gfortran.dg/real_const_3.f90 +++ b/gcc/testsuite/gfortran.dg/real_const_3.f90 @@ -1,7 +1,7 @@ !{ dg-do run } !{ dg-options "-fno-range-check" } !{ dg-add-options ieee } -!{ dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +!{ dg-skip-if "NaN not supported" { spu-*-* } } ! PR19310 and PR19904, allow disabling range check during compile. ! Contributed by Jerry DeLisle program main diff --git a/gcc/testsuite/gfortran.dg/realloc_on_assign_2.f03 b/gcc/testsuite/gfortran.dg/realloc_on_assign_2.f03 index 0564d0d..6d6680d9 100644 --- a/gcc/testsuite/gfortran.dg/realloc_on_assign_2.f03 +++ b/gcc/testsuite/gfortran.dg/realloc_on_assign_2.f03 @@ -1,5 +1,5 @@ ! { dg-do run } -! { dg-skip-if "Too big for local store" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "Too big for local store" { spu-*-* } } ! Tests the patch that implements F2003 automatic allocation and ! reallocation of allocatable arrays on assignment. The tests ! below were generated in the final stages of the development of diff --git a/gcc/testsuite/gfortran.dg/scratch_1.f90 b/gcc/testsuite/gfortran.dg/scratch_1.f90 index fd888cc..a1762fc 100644 --- a/gcc/testsuite/gfortran.dg/scratch_1.f90 +++ b/gcc/testsuite/gfortran.dg/scratch_1.f90 @@ -1,5 +1,5 @@ ! { dg-do run } -! { dg-skip-if "Too big for local store" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "Too big for local store" { spu-*-* } } ! Check that we can open more than 26 scratch files concurrently integer :: i do i = 1, 30 diff --git a/gcc/testsuite/gfortran.dg/stat_1.f90 b/gcc/testsuite/gfortran.dg/stat_1.f90 index ec582f9..49ef23a 100644 --- a/gcc/testsuite/gfortran.dg/stat_1.f90 +++ b/gcc/testsuite/gfortran.dg/stat_1.f90 @@ -1,5 +1,5 @@ ! { dg-do run } -! { dg-skip-if "" { *-*-mingw* spu-*-* } { "*" } { "" } } +! { dg-skip-if "" { *-*-mingw* spu-*-* } } ! { dg-options "-std=gnu" } character(len=*), parameter :: f = "testfile_stat_1" integer :: s1(13), r1, s2(13), r2, s3(13), r3, d(13), rd diff --git a/gcc/testsuite/gfortran.dg/stat_2.f90 b/gcc/testsuite/gfortran.dg/stat_2.f90 index a3eb6b2..ae029dc 100644 --- a/gcc/testsuite/gfortran.dg/stat_2.f90 +++ b/gcc/testsuite/gfortran.dg/stat_2.f90 @@ -1,5 +1,5 @@ ! { dg-do run } -! { dg-skip-if "" { *-*-mingw* spu-*-* } { "*" } { "" } } +! { dg-skip-if "" { *-*-mingw* spu-*-* } } ! { dg-options "-std=gnu" } character(len=*), parameter :: f = "testfile_stat_2" integer :: s1(13), r1, s2(13), r2, s3(13), r3, d(13), rd diff --git a/gcc/testsuite/gfortran.dg/transfer_simplify_1.f90 b/gcc/testsuite/gfortran.dg/transfer_simplify_1.f90 index 4f92121..8a3340a 100644 --- a/gcc/testsuite/gfortran.dg/transfer_simplify_1.f90 +++ b/gcc/testsuite/gfortran.dg/transfer_simplify_1.f90 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-options "-O2" } -! { dg-skip-if "NaN not supported" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "NaN not supported" { spu-*-* } } ! Tests that the PRs caused by the lack of gfc_simplify_transfer are ! now fixed. These were brought together in the meta-bug PR31237 ! (TRANSFER intrinsic). diff --git a/gcc/testsuite/gfortran.dg/typebound_operator_9.f03 b/gcc/testsuite/gfortran.dg/typebound_operator_9.f03 index 6e62526..e4c6b6e 100644 --- a/gcc/testsuite/gfortran.dg/typebound_operator_9.f03 +++ b/gcc/testsuite/gfortran.dg/typebound_operator_9.f03 @@ -1,6 +1,6 @@ ! { dg-do run } ! { dg-add-options ieee } -! { dg-skip-if "Too big for local store" { spu-*-* } { "*" } { "" } } +! { dg-skip-if "Too big for local store" { spu-*-* } } ! ! Solve a diffusion problem using an object-oriented approach ! diff --git a/gcc/testsuite/gfortran.dg/vect/fast-math-pr38968.f90 b/gcc/testsuite/gfortran.dg/vect/fast-math-pr38968.f90 index c34a077..f5bc41a 100644 --- a/gcc/testsuite/gfortran.dg/vect/fast-math-pr38968.f90 +++ b/gcc/testsuite/gfortran.dg/vect/fast-math-pr38968.f90 @@ -1,7 +1,7 @@ ! Skip this on platforms that don't have the vectorization instructions ! to handle complex types. This test is very slow on these platforms so ! skipping is better then running it unvectorized. -! { dg-skip-if "" { ia64-*-* sparc*-*-* } { "*" } { "" } } +! { dg-skip-if "" { ia64-*-* sparc*-*-* } } ! It can be slow on some x86 CPUs. ! { dg-timeout-factor 2 } program mymatmul diff --git a/gcc/testsuite/gnat.dg/debug7.adb b/gcc/testsuite/gnat.dg/debug7.adb index 3defc2c..41728ea 100644 --- a/gcc/testsuite/gnat.dg/debug7.adb +++ b/gcc/testsuite/gnat.dg/debug7.adb @@ -1,5 +1,5 @@ -- { dg-do compile } --- { dg-skip-if "No dwarf-2 support" { hppa*-*-hpux* } "*" "" } +-- { dg-skip-if "No dwarf-2 support" { hppa*-*-hpux* } } -- { dg-options "-cargs -gdwarf-2 -gstrict-dwarf -dA -margs" } -- { dg-final { scan-assembler "DW_TAG_imported_decl" } } diff --git a/gcc/testsuite/gnat.dg/debug9.adb b/gcc/testsuite/gnat.dg/debug9.adb index eaf3700..ec11af1 100644 --- a/gcc/testsuite/gnat.dg/debug9.adb +++ b/gcc/testsuite/gnat.dg/debug9.adb @@ -7,7 +7,7 @@ -- some hackish way to check that types are output in the proper context (i.e. -- at global or local scope). -- --- { dg-skip-if "No dwarf-4 support" { hppa*-*-hpux* } "*" "" } +-- { dg-skip-if "No dwarf-4 support" { hppa*-*-hpux* } } -- { dg-options "-cargs -gdwarf-4 -fdebug-types-section -dA -margs" } -- { dg-final { scan-assembler-times "\\(DIE \\(0x\[a-f0-9\]*\\) DW_TAG_type_unit\\)" 0 } } diff --git a/gcc/testsuite/obj-c++.dg/dwarf-2.mm b/gcc/testsuite/obj-c++.dg/dwarf-2.mm index 3720a88..9994df4 100644 --- a/gcc/testsuite/obj-c++.dg/dwarf-2.mm +++ b/gcc/testsuite/obj-c++.dg/dwarf-2.mm @@ -1,4 +1,4 @@ /* { dg-options "-gdwarf-2 -dA" } */ -/* { dg-skip-if "No Dwarf" { { hppa*-*-hpux* } && { ! hppa*64*-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "No Dwarf" { { hppa*-*-hpux* } && { ! hppa*64*-*-* } } } */ /* { dg-final { scan-assembler "0x11\[^0-9a-f\].*DW_AT_language" } } */ int x; diff --git a/gcc/testsuite/obj-c++.dg/lto/trivial-1_0.mm b/gcc/testsuite/obj-c++.dg/lto/trivial-1_0.mm index 744a017..55f62f0 100644 --- a/gcc/testsuite/obj-c++.dg/lto/trivial-1_0.mm +++ b/gcc/testsuite/obj-c++.dg/lto/trivial-1_0.mm @@ -1,5 +1,5 @@ /* { dg-lto-do run } */ -/* { dg-skip-if "Needs OBJC2 ABI" { "*-*-darwin*" && lp64 } { "*" } { "" } } */ +/* { dg-skip-if "Needs OBJC2 ABI" { "*-*-darwin*" && lp64 } } */ extern "C" { extern int printf (const char *,...) ; extern void abort (void) ; diff --git a/gcc/testsuite/obj-c++.dg/tls/static-1a.mm b/gcc/testsuite/obj-c++.dg/tls/static-1a.mm index 4097420..a19aba2 100644 --- a/gcc/testsuite/obj-c++.dg/tls/static-1a.mm +++ b/gcc/testsuite/obj-c++.dg/tls/static-1a.mm @@ -1,4 +1,4 @@ -// { dg-skip-if "Additional Source File" *-*-* "*" "" } +// { dg-skip-if "Additional Source File" *-*-* } // This is the additional source file for test static-1.mm struct A diff --git a/gcc/testsuite/objc.dg/dwarf-1.m b/gcc/testsuite/objc.dg/dwarf-1.m index 3bfabba..d411c3c 100644 --- a/gcc/testsuite/objc.dg/dwarf-1.m +++ b/gcc/testsuite/objc.dg/dwarf-1.m @@ -1,6 +1,6 @@ /* { dg-options "-gdwarf-2 -dA" } */ /* { dg-final { scan-assembler "\"id.0\".*DW_AT_name" } } */ -/* { dg-skip-if "No Dwarf" { { *-*-aix* hppa*-*-hpux* } && { ! hppa*64*-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "No Dwarf" { { *-*-aix* hppa*-*-hpux* } && { ! hppa*64*-*-* } } } */ @interface foo id x; @end diff --git a/gcc/testsuite/objc.dg/dwarf-2.m b/gcc/testsuite/objc.dg/dwarf-2.m index 967f515..c394c59 100644 --- a/gcc/testsuite/objc.dg/dwarf-2.m +++ b/gcc/testsuite/objc.dg/dwarf-2.m @@ -1,4 +1,4 @@ /* { dg-options "-gdwarf-2 -dA -gno-strict-dwarf" } */ /* { dg-final { scan-assembler "0x10\[^0-9a-f\].*DW_AT_language" } } */ -/* { dg-skip-if "No Dwarf" { { *-*-aix* hppa*-*-hpux* } && { ! hppa*64*-*-* } } { "*" } { "" } } */ +/* { dg-skip-if "No Dwarf" { { *-*-aix* hppa*-*-hpux* } && { ! hppa*64*-*-* } } } */ int x; diff --git a/gcc/testsuite/objc.dg/lto/trivial-1_0.m b/gcc/testsuite/objc.dg/lto/trivial-1_0.m index 076f230..ba1b1aa 100644 --- a/gcc/testsuite/objc.dg/lto/trivial-1_0.m +++ b/gcc/testsuite/objc.dg/lto/trivial-1_0.m @@ -1,5 +1,5 @@ /* { dg-lto-do run } */ -/* { dg-skip-if "" { "*-*-darwin*" && lp64 } { "*" } { "" } } */ +/* { dg-skip-if "" { "*-*-darwin*" && lp64 } } */ extern int printf (char *,...) ; typedef struct objc_class *Class; -- cgit v1.1 From 28ab5c5ea9510b1937d4bd0e9343372d67f83610 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sun, 18 Jun 2017 00:16:40 +0000 Subject: Daily bump. From-SVN: r249343 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index f777f12..7ae1e11 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170617 +20170618 -- cgit v1.1 From 5ebcc5477a59dbe51c7e1130a2b751a2a1d89574 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Sun, 18 Jun 2017 00:25:15 -0400 Subject: PR c++/70844 - -Wuseless-cast and inheriting constructor. * method.c (forward_parm): Suppress warn_useless_cast. From-SVN: r249344 --- gcc/cp/ChangeLog | 5 +++++ gcc/cp/method.c | 1 + gcc/testsuite/g++.dg/cpp0x/inh-ctor27.C | 13 +++++++++++++ 3 files changed, 19 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp0x/inh-ctor27.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index dba5e4d..d082574 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,8 @@ +2017-06-17 Jason Merrill + + PR c++/70844 - -Wuseless-cast and inheriting constructor. + * method.c (forward_parm): Suppress warn_useless_cast. + 2017-06-16 Jason Merrill PR c++/81045 - Wrong type-dependence with auto return type. diff --git a/gcc/cp/method.c b/gcc/cp/method.c index 9541fcb..fe4b2af 100644 --- a/gcc/cp/method.c +++ b/gcc/cp/method.c @@ -486,6 +486,7 @@ forward_parm (tree parm) type = PACK_EXPANSION_PATTERN (type); if (TREE_CODE (type) != REFERENCE_TYPE) type = cp_build_reference_type (type, /*rval=*/true); + warning_sentinel w (warn_useless_cast); exp = build_static_cast (type, exp, tf_warning_or_error); if (DECL_PACK_P (parm)) exp = make_pack_expansion (exp); diff --git a/gcc/testsuite/g++.dg/cpp0x/inh-ctor27.C b/gcc/testsuite/g++.dg/cpp0x/inh-ctor27.C new file mode 100644 index 0000000..ef2ada1 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/inh-ctor27.C @@ -0,0 +1,13 @@ +// PR c++/70844 +// { dg-options -Wuseless-cast } +// { dg-do compile { target c++11 } } + +struct base { + base (int const &); +}; + +struct derived : public base { + using base::base; +}; + +derived d(0); -- cgit v1.1 From 20ef9df1cffcae042e02d596724e69c24047c557 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Sun, 18 Jun 2017 00:55:02 -0400 Subject: PR c++/60063 - -Wunused-local-typedefs and templates. * decl2.c (is_late_template_attribute): Return false for "used". From-SVN: r249347 --- gcc/cp/ChangeLog | 3 +++ gcc/cp/decl2.c | 5 +++-- gcc/testsuite/g++.dg/warn/Wunused-local-typedefs-4.C | 13 +++++++++++++ 3 files changed, 19 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.dg/warn/Wunused-local-typedefs-4.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index d082574..465e7d9 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,8 @@ 2017-06-17 Jason Merrill + PR c++/60063 - -Wunused-local-typedefs and templates. + * decl2.c (is_late_template_attribute): Return false for "used". + PR c++/70844 - -Wuseless-cast and inheriting constructor. * method.c (forward_parm): Suppress warn_useless_cast. diff --git a/gcc/cp/decl2.c b/gcc/cp/decl2.c index 69cb40f..72239ec 100644 --- a/gcc/cp/decl2.c +++ b/gcc/cp/decl2.c @@ -1091,9 +1091,10 @@ is_late_template_attribute (tree attr, tree decl) if (is_attribute_p ("weak", name)) return true; - /* Attribute unused is applied directly, as it appertains to + /* Attributes used and unused are applied directly, as they appertain to decls. */ - if (is_attribute_p ("unused", name)) + if (is_attribute_p ("unused", name) + || is_attribute_p ("used", name)) return false; /* Attribute tls_model wants to modify the symtab. */ diff --git a/gcc/testsuite/g++.dg/warn/Wunused-local-typedefs-4.C b/gcc/testsuite/g++.dg/warn/Wunused-local-typedefs-4.C new file mode 100644 index 0000000..7efe112 --- /dev/null +++ b/gcc/testsuite/g++.dg/warn/Wunused-local-typedefs-4.C @@ -0,0 +1,13 @@ +// PR c++/60063 +// { dg-options -Wunused-local-typedefs } + +template struct S; + +void foo (int i) { + typedef __attribute__ ((used)) S X; +} + +template +void bar (T i) { + typedef __attribute__ ((used)) S Y; +} -- cgit v1.1 From 5dace4bf90ee311424ac625f9c1e2a9693df1ba9 Mon Sep 17 00:00:00 2001 From: Thomas Koenig Date: Sun, 18 Jun 2017 18:04:19 +0000 Subject: re PR fortran/52473 (CSHIFT slow - inline it?) 2017-06-18 Thomas Koenig PR fortran/52473 * m4/cshift0.m4: For arrays that are contiguous up to shift, implement blocked algorighm for cshift. * generated/cshift0_c10.c: Regenerated. * generated/cshift0_c16.c: Regenerated. * generated/cshift0_c4.c: Regenerated. * generated/cshift0_c8.c: Regenerated. * generated/cshift0_i1.c: Regenerated. * generated/cshift0_i16.c: Regenerated. * generated/cshift0_i2.c: Regenerated. * generated/cshift0_i4.c: Regenerated. * generated/cshift0_i8.c: Regenerated. * generated/cshift0_r10.c: Regenerated. * generated/cshift0_r16.c: Regenerated. * generated/cshift0_r4.c: Regenerated. * generated/cshift0_r8.c: Regenerated. 2017-06-18 Thomas Koenig PR fortran/52473 * gfortran.dg/cshift_1.f90: New test. From-SVN: r249350 --- gcc/testsuite/ChangeLog | 5 ++ gcc/testsuite/gfortran.dg/cshift_1.f90 | 108 +++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/cshift_1.f90 (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ea83e35..9200ee8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-18 Thomas Koenig + + PR fortran/52473 + * gfortran.dg/cshift_1.f90: New test. + 2017-06-17 Rainer Orth Remove dg-skip-if, dg-xfail-if, dg-xfail-run-if default args. diff --git a/gcc/testsuite/gfortran.dg/cshift_1.f90 b/gcc/testsuite/gfortran.dg/cshift_1.f90 new file mode 100644 index 0000000..e2024ea --- /dev/null +++ b/gcc/testsuite/gfortran.dg/cshift_1.f90 @@ -0,0 +1,108 @@ +! { dg-do run } +! Take cshift through its paces to make sure no boundary +! cases are wrong. + +module kinds + integer, parameter :: sp = selected_real_kind(6) ! Single precision +end module kinds + +module replacements + use kinds +contains + subroutine cshift_sp_3_v1 (array, shift, dim, res) + integer, parameter :: wp = sp + real(kind=wp), dimension(:,:,:), intent(in) :: array + integer, intent(in) :: shift, dim + real(kind=wp), dimension(:,:,:), intent(out) :: res + integer :: i,j,k + integer :: sh, rsh + integer :: n + integer :: n2, n3 + res = 0 + n3 = size(array,3) + n2 = size(array,2) + n1 = size(array,1) + if (dim == 1) then + n = n1 + sh = modulo(shift, n) + rsh = n - sh + do k=1, n3 + do j=1, n2 + do i=1, rsh + res(i,j,k) = array(i+sh,j,k) + end do + do i=rsh+1,n + res(i,j,k) = array(i-rsh,j,k) + end do + end do + end do + else if (dim == 2) then + n = n2 + sh = modulo(shift,n) + rsh = n - sh + do k=1, n3 + do j=1, rsh + do i=1, n1 + res(i,j,k) = array(i,j+sh, k) + end do + end do + do j=rsh+1, n + do i=1, n1 + res(i,j,k) = array(i,j-rsh, k) + end do + end do + end do + else if (dim == 3) then + n = n3 + sh = modulo(shift, n) + rsh = n - sh + do k=1, rsh + do j=1, n2 + do i=1, n1 + res(i,j,k) = array(i, j, k+sh) + end do + end do + end do + do k=rsh+1, n + do j=1, n2 + do i=1, n1 + res(i,j, k) = array(i, j, k-rsh) + end do + end do + end do + else + stop "Wrong argument to dim" + end if + end subroutine cshift_sp_3_v1 +end module replacements + +program testme + use kinds + use replacements + implicit none + integer, parameter :: wp = sp ! Working precision + INTEGER, PARAMETER :: n = 7 + real(kind=wp), dimension(:,:,:), allocatable :: a,b,c + integer i, j, k + real:: t1, t2 + integer, parameter :: nrep = 20 + + allocate (a(n,n,n), b(n,n,n),c(n,n,n)) + call random_number(a) + do k = 1,3 + do i=-3,3,2 + call cshift_sp_3_v1 (a, i, k, b) + c = cshift(a,i,k) + if (any (c /= b)) call abort + end do + end do + deallocate (b,c) + allocate (b(n-1,n-1,n-1),c(n-1,n-1,n-1)) + do k=1,3 + do i=-3,3,2 + call cshift_sp_3_v1 (a(1:n-1,1:n-1,1:n-1), i, k, b) + c = cshift(a(1:n-1,1:n-1,1:n-1), i, k) + if (any (c /= b)) call abort + end do + end do +end program testme -- cgit v1.1 From 18154846278637265878a0397995e8cda3c154a7 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Sun, 18 Jun 2017 21:56:45 +0200 Subject: * gcc.dg/lto/pr69866_0.c: This test needs alias. From-SVN: r249352 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/lto/pr69866_0.c | 1 + 2 files changed, 5 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9200ee8..63960eb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-18 Jan Hubicka + + * gcc.dg/lto/pr69866_0.c: This test needs alias. + 2017-06-18 Thomas Koenig PR fortran/52473 diff --git a/gcc/testsuite/gcc.dg/lto/pr69866_0.c b/gcc/testsuite/gcc.dg/lto/pr69866_0.c index f49ef8d..8c90030 100644 --- a/gcc/testsuite/gcc.dg/lto/pr69866_0.c +++ b/gcc/testsuite/gcc.dg/lto/pr69866_0.c @@ -1,4 +1,5 @@ /* { dg-lto-do link } */ +/* { dg-require-alias "" } */ int _umh(int i) { -- cgit v1.1 From 245ad722ca8f9605165f90f9dd3f8e6137e68b38 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Mon, 19 Jun 2017 00:16:29 +0000 Subject: Daily bump. From-SVN: r249356 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 7ae1e11..b9d7fd0 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170618 +20170619 -- cgit v1.1 From db9bbdeca441e21f50b12cbfc2ff34992242b4f3 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 19 Jun 2017 07:17:55 +0000 Subject: re PR ipa/81112 (internal compiler error: tree check: expected integer_cst, have range_expr in get_len, at tree.h:5321) 2017-06-19 Richard Biener PR ipa/81112 * ipa-prop.c (find_constructor_constant_at_offset): Handle RANGE_EXPR conservatively. * g++.dg/torture/pr81112.C: New testcase. From-SVN: r249357 --- gcc/ChangeLog | 6 +++ gcc/ipa-prop.c | 7 +++- gcc/testsuite/ChangeLog | 5 +++ gcc/testsuite/g++.dg/torture/pr81112.C | 67 ++++++++++++++++++++++++++++++++++ 4 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/torture/pr81112.C (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a741d75..60d3155 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-19 Richard Biener + + PR ipa/81112 + * ipa-prop.c (find_constructor_constant_at_offset): Handle + RANGE_EXPR conservatively. + 2017-06-16 Carl Love * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add diff --git a/gcc/ipa-prop.c b/gcc/ipa-prop.c index 292f3e2..51f6221 100644 --- a/gcc/ipa-prop.c +++ b/gcc/ipa-prop.c @@ -3013,7 +3013,10 @@ find_constructor_constant_at_offset (tree constructor, HOST_WIDE_INT req_offset) if (index) { - off = wi::to_offset (index); + if (TREE_CODE (index) == RANGE_EXPR) + off = wi::to_offset (TREE_OPERAND (index, 0)); + else + off = wi::to_offset (index); if (TYPE_DOMAIN (type) && TYPE_MIN_VALUE (TYPE_DOMAIN (type))) { tree low_bound = TYPE_MIN_VALUE (TYPE_DOMAIN (type)); @@ -3022,6 +3025,8 @@ find_constructor_constant_at_offset (tree constructor, HOST_WIDE_INT req_offset) TYPE_PRECISION (TREE_TYPE (index))); } off *= wi::to_offset (unit_size); + /* ??? Handle more than just the first index of a + RANGE_EXPR. */ } else off = wi::to_offset (unit_size) * ix; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 63960eb..3d77462 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-19 Richard Biener + + PR ipa/81112 + * g++.dg/torture/pr81112.C: New testcase. + 2017-06-18 Jan Hubicka * gcc.dg/lto/pr69866_0.c: This test needs alias. diff --git a/gcc/testsuite/g++.dg/torture/pr81112.C b/gcc/testsuite/g++.dg/torture/pr81112.C new file mode 100644 index 0000000..10e0ebe --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr81112.C @@ -0,0 +1,67 @@ +// { dg-do compile } + +class AssertionResult { + bool success_; +}; + +AssertionResult AssertionSuccess(); + +template +AssertionResult EXPECT_EQ(const T1& expected, const T1& actual) { + if (expected == actual) { + return AssertionSuccess(); + } + return AssertionSuccess(); +} + +struct uuid +{ + unsigned char data[16]; +}; + +bool operator== (uuid const& lhs, uuid const& rhs); + +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); +typedef int __v4si __attribute__ ((__vector_size__ (16))); +typedef char __v16qi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1))); + +int foo (__v16qi); + +extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + _mm_loadu_si128 (__m128i_u const *__P) +{ + return *__P; +} +extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + _mm_cmpeq_epi32 (__m128i __A, __m128i __B) +{ + return (__m128i) ((__v4si)__A == (__v4si)__B); +} +extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) + _mm_movemask_epi8 (__m128i __A) +{ + return foo ((__v16qi)__A); +} + + +__m128i load_unaligned_si128(const unsigned char* p) +{ + return _mm_loadu_si128(reinterpret_cast< const __m128i* >(p)); +} + +inline bool operator== (uuid const& lhs, uuid const& rhs) +{ + __m128i mm_left = load_unaligned_si128(lhs.data); + __m128i mm_right = load_unaligned_si128(rhs.data); + + __m128i mm_cmp = _mm_cmpeq_epi32(mm_left, mm_right); + + return _mm_movemask_epi8(mm_cmp) == 0xFFFF; +} + +void crash_gcc7() +{ + static const uuid u = uuid(); + EXPECT_EQ(u, u); +} -- cgit v1.1 From adb7eaa2bac31047b37cc8b9cb7b4121ca0a8fea Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 19 Jun 2017 07:26:50 +0000 Subject: tree-ssa-loop-niter.h (estimate_numbers_of_iterations): Take struct function as arg. 2017-06-19 Richard Biener * tree-ssa-loop-niter.h (estimate_numbers_of_iterations): Take struct function as arg. (estimate_numbers_of_iterations): Export overload with loop arg. (free_numbers_of_iterations_estimates_loop): Use an overload of free_numbers_of_iterations_estimates instead. * tree-cfg.c (remove_bb): Adjust. * tree-cfgcleanup.c (remove_forwarder_block_with_phi): Likewise. * tree-parloops.c (gen_parallel_loop): Likewise. * tree-ssa-loop-ivcanon.c (canonicalize_induction_variables): Likewise. (tree_unroll_loops_completely): Likewise. * tree-ssa-loop-niter.c (estimate_numbers_of_iterations_loop): Use an overload instead and export. (estimated_loop_iterations): Adjust. (max_loop_iterations): Likewise. (likely_max_loop_iterations): Likewise. (estimate_numbers_of_iterations): Take struct function as arg and adjust. (loop_exits_before_overflow): Adjust. (free_numbers_of_iterations_estimates_loop): Use an overload. * tree-vect-loop.c (vect_analyze_loop_form): Adjust. * tree-vectorizer.c (vect_free_loop_info_assumptions): Likewise. From-SVN: r249358 --- gcc/ChangeLog | 25 +++++++++++++++++++++++++ gcc/tree-cfg.c | 2 +- gcc/tree-cfgcleanup.c | 2 +- gcc/tree-parloops.c | 3 +-- gcc/tree-ssa-loop-ivcanon.c | 7 ++++--- gcc/tree-ssa-loop-niter.c | 26 +++++++++++--------------- gcc/tree-ssa-loop-niter.h | 6 +++--- gcc/tree-vect-loop.c | 2 +- gcc/tree-vectorizer.c | 4 ++-- 9 files changed, 49 insertions(+), 28 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 60d3155..49a8109 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,30 @@ 2017-06-19 Richard Biener + * tree-ssa-loop-niter.h (estimate_numbers_of_iterations): Take + struct function as arg. + (estimate_numbers_of_iterations): Export overload with loop arg. + (free_numbers_of_iterations_estimates_loop): Use an overload of + free_numbers_of_iterations_estimates instead. + * tree-cfg.c (remove_bb): Adjust. + * tree-cfgcleanup.c (remove_forwarder_block_with_phi): Likewise. + * tree-parloops.c (gen_parallel_loop): Likewise. + * tree-ssa-loop-ivcanon.c (canonicalize_induction_variables): + Likewise. + (tree_unroll_loops_completely): Likewise. + * tree-ssa-loop-niter.c (estimate_numbers_of_iterations_loop): + Use an overload instead and export. + (estimated_loop_iterations): Adjust. + (max_loop_iterations): Likewise. + (likely_max_loop_iterations): Likewise. + (estimate_numbers_of_iterations): Take struct function as arg + and adjust. + (loop_exits_before_overflow): Adjust. + (free_numbers_of_iterations_estimates_loop): Use an overload. + * tree-vect-loop.c (vect_analyze_loop_form): Adjust. + * tree-vectorizer.c (vect_free_loop_info_assumptions): Likewise. + +2017-06-19 Richard Biener + PR ipa/81112 * ipa-prop.c (find_constructor_constant_at_offset): Handle RANGE_EXPR conservatively. diff --git a/gcc/tree-cfg.c b/gcc/tree-cfg.c index 7df80f8..589508d 100644 --- a/gcc/tree-cfg.c +++ b/gcc/tree-cfg.c @@ -2177,7 +2177,7 @@ remove_bb (basic_block bb) with it. */ if (loop->latch == bb || loop->header == bb) - free_numbers_of_iterations_estimates_loop (loop); + free_numbers_of_iterations_estimates (loop); } /* Remove all the instructions in the block. */ diff --git a/gcc/tree-cfgcleanup.c b/gcc/tree-cfgcleanup.c index 94a172f..4cab592 100644 --- a/gcc/tree-cfgcleanup.c +++ b/gcc/tree-cfgcleanup.c @@ -959,7 +959,7 @@ remove_forwarder_block_with_phi (basic_block bb) { dest->loop_father->any_upper_bound = false; dest->loop_father->any_likely_upper_bound = false; - free_numbers_of_iterations_estimates_loop (dest->loop_father); + free_numbers_of_iterations_estimates (dest->loop_father); } } diff --git a/gcc/tree-parloops.c b/gcc/tree-parloops.c index 641f675..79d616b 100644 --- a/gcc/tree-parloops.c +++ b/gcc/tree-parloops.c @@ -2436,8 +2436,7 @@ gen_parallel_loop (struct loop *loop, /* Free loop bound estimations that could contain references to removed statements. */ - FOR_EACH_LOOP (loop, 0) - free_numbers_of_iterations_estimates_loop (loop); + free_numbers_of_iterations_estimates (cfun); } /* Returns true when LOOP contains vector phi nodes. */ diff --git a/gcc/tree-ssa-loop-ivcanon.c b/gcc/tree-ssa-loop-ivcanon.c index 82ad59c..b6ac765 100644 --- a/gcc/tree-ssa-loop-ivcanon.c +++ b/gcc/tree-ssa-loop-ivcanon.c @@ -1215,7 +1215,7 @@ canonicalize_induction_variables (void) bool irred_invalidated = false; bitmap loop_closed_ssa_invalidated = BITMAP_ALLOC (NULL); - estimate_numbers_of_iterations (); + estimate_numbers_of_iterations (cfun); FOR_EACH_LOOP (loop, LI_FROM_INNERMOST) { @@ -1361,6 +1361,8 @@ tree_unroll_loops_completely (bool may_increase_size, bool unroll_outer) int iteration = 0; bool irred_invalidated = false; + estimate_numbers_of_iterations (cfun); + do { changed = false; @@ -1370,7 +1372,7 @@ tree_unroll_loops_completely (bool may_increase_size, bool unroll_outer) loop_closed_ssa_invalidated = BITMAP_ALLOC (NULL); free_numbers_of_iterations_estimates (cfun); - estimate_numbers_of_iterations (); + estimate_numbers_of_iterations (cfun); changed = tree_unroll_loops_completely_1 (may_increase_size, unroll_outer, father_bbs, @@ -1588,7 +1590,6 @@ pass_complete_unrolli::execute (function *fun) { scev_initialize (); ret = tree_unroll_loops_completely (optimize >= 3, false); - free_numbers_of_iterations_estimates (fun); scev_finalize (); } loop_optimizer_finalize (); diff --git a/gcc/tree-ssa-loop-niter.c b/gcc/tree-ssa-loop-niter.c index b1f1407..848e812 100644 --- a/gcc/tree-ssa-loop-niter.c +++ b/gcc/tree-ssa-loop-niter.c @@ -3786,8 +3786,8 @@ maybe_lower_iteration_bound (struct loop *loop) /* Records estimates on numbers of iterations of LOOP. If USE_UNDEFINED_P is true also use estimates derived from undefined behavior. */ -static void -estimate_numbers_of_iterations_loop (struct loop *loop) +void +estimate_numbers_of_iterations (struct loop *loop) { vec exits; tree niter, type; @@ -3876,7 +3876,7 @@ estimated_loop_iterations (struct loop *loop, widest_int *nit) /* When SCEV information is available, try to update loop iterations estimate. Otherwise just return whatever we recorded earlier. */ if (scev_initialized_p ()) - estimate_numbers_of_iterations_loop (loop); + estimate_numbers_of_iterations (loop); return (get_estimated_loop_iterations (loop, nit)); } @@ -3912,7 +3912,7 @@ max_loop_iterations (struct loop *loop, widest_int *nit) /* When SCEV information is available, try to update loop iterations estimate. Otherwise just return whatever we recorded earlier. */ if (scev_initialized_p ()) - estimate_numbers_of_iterations_loop (loop); + estimate_numbers_of_iterations (loop); return get_max_loop_iterations (loop, nit); } @@ -3947,7 +3947,7 @@ likely_max_loop_iterations (struct loop *loop, widest_int *nit) /* When SCEV information is available, try to update loop iterations estimate. Otherwise just return whatever we recorded earlier. */ if (scev_initialized_p ()) - estimate_numbers_of_iterations_loop (loop); + estimate_numbers_of_iterations (loop); return get_likely_max_loop_iterations (loop, nit); } @@ -4051,7 +4051,7 @@ estimated_stmt_executions (struct loop *loop, widest_int *nit) /* Records estimates on numbers of iterations of loops. */ void -estimate_numbers_of_iterations (void) +estimate_numbers_of_iterations (function *fn) { struct loop *loop; @@ -4059,10 +4059,8 @@ estimate_numbers_of_iterations (void) loop iteration estimates. */ fold_defer_overflow_warnings (); - FOR_EACH_LOOP (loop, 0) - { - estimate_numbers_of_iterations_loop (loop); - } + FOR_EACH_LOOP_FN (fn, loop, 0) + estimate_numbers_of_iterations (loop); fold_undefer_and_ignore_overflow_warnings (); } @@ -4235,7 +4233,7 @@ loop_exits_before_overflow (tree base, tree step, valid_niter = fold_build2 (FLOOR_DIV_EXPR, unsigned_type, delta, step_abs); - estimate_numbers_of_iterations_loop (loop); + estimate_numbers_of_iterations (loop); if (max_loop_iterations (loop, &niter) && wi::fits_to_tree_p (niter, TREE_TYPE (valid_niter)) @@ -4502,7 +4500,7 @@ scev_probably_wraps_p (tree var, tree base, tree step, /* Frees the information on upper bounds on numbers of iterations of LOOP. */ void -free_numbers_of_iterations_estimates_loop (struct loop *loop) +free_numbers_of_iterations_estimates (struct loop *loop) { struct control_iv *civ; struct nb_iter_bound *bound; @@ -4534,9 +4532,7 @@ free_numbers_of_iterations_estimates (function *fn) struct loop *loop; FOR_EACH_LOOP_FN (fn, loop, 0) - { - free_numbers_of_iterations_estimates_loop (loop); - } + free_numbers_of_iterations_estimates (loop); } /* Substitute value VAL for ssa name NAME inside expressions held diff --git a/gcc/tree-ssa-loop-niter.h b/gcc/tree-ssa-loop-niter.h index b009857..8161cc7 100644 --- a/gcc/tree-ssa-loop-niter.h +++ b/gcc/tree-ssa-loop-niter.h @@ -45,13 +45,13 @@ extern HOST_WIDE_INT estimated_stmt_executions_int (struct loop *); extern bool max_stmt_executions (struct loop *, widest_int *); extern bool likely_max_stmt_executions (struct loop *, widest_int *); extern bool estimated_stmt_executions (struct loop *, widest_int *); -extern void estimate_numbers_of_iterations (void); +extern void estimate_numbers_of_iterations (function *); +extern void estimate_numbers_of_iterations (struct loop *); extern bool stmt_dominates_stmt_p (gimple *, gimple *); extern bool nowrap_type_p (tree); extern bool scev_probably_wraps_p (tree, tree, tree, gimple *, struct loop *, bool); -extern void free_loop_control_ivs (struct loop *); -extern void free_numbers_of_iterations_estimates_loop (struct loop *); +extern void free_numbers_of_iterations_estimates (struct loop *); extern void free_numbers_of_iterations_estimates (function *); extern void substitute_in_loop_info (struct loop *, tree, tree); diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c index b8b49c9..d601296 100644 --- a/gcc/tree-vect-loop.c +++ b/gcc/tree-vect-loop.c @@ -1570,7 +1570,7 @@ vect_analyze_loop_form (struct loop *loop) some assumptions. In order to do this, we need to clear existing information computed by scev and niter analyzer. */ scev_reset_htab (); - free_numbers_of_iterations_estimates_loop (loop); + free_numbers_of_iterations_estimates (loop); /* Also set flag for this loop so that following scev and niter analysis are done under the assumptions. */ loop_constraint_set (loop, LOOP_C_FINITE); diff --git a/gcc/tree-vectorizer.c b/gcc/tree-vectorizer.c index 1bef2e4..0d62c82 100644 --- a/gcc/tree-vectorizer.c +++ b/gcc/tree-vectorizer.c @@ -380,10 +380,10 @@ vect_free_loop_info_assumptions (struct loop *loop) { scev_reset_htab (); /* We need to explicitly reset upper bound information since they are - used even after free_numbers_of_iterations_estimates_loop. */ + used even after free_numbers_of_iterations_estimates. */ loop->any_upper_bound = false; loop->any_likely_upper_bound = false; - free_numbers_of_iterations_estimates_loop (loop); + free_numbers_of_iterations_estimates (loop); loop_constraint_clear (loop, LOOP_C_FINITE); } -- cgit v1.1 From fe1ae165924f6c4bc55e40c2d3843d39b9bfc297 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Mon, 19 Jun 2017 09:29:16 +0000 Subject: Remove reference to Solaris 2.[56] * g++.dg/other/unused1.C: Remove *-*-solaris2.[56]* from dg-skip-if list. From-SVN: r249359 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/other/unused1.C | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3d77462..8153a71 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-19 Rainer Orth + + * g++.dg/other/unused1.C: Remove *-*-solaris2.[56]* from + dg-skip-if list. + 2017-06-19 Richard Biener PR ipa/81112 diff --git a/gcc/testsuite/g++.dg/other/unused1.C b/gcc/testsuite/g++.dg/other/unused1.C index 15e8a541..77625d0 100644 --- a/gcc/testsuite/g++.dg/other/unused1.C +++ b/gcc/testsuite/g++.dg/other/unused1.C @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-g" } */ -/* { dg-skip-if "" { { hppa*-*-hpux* *-*-solaris2.[56]* powerpc-ibm-aix* } && { ! hppa*64*-*-* } } } */ +/* { dg-skip-if "" { { hppa*-*-hpux* powerpc-ibm-aix* } && { ! hppa*64*-*-* } } } */ /* Make sure we didn't eliminate casted types because we thought they were unused. */ -- cgit v1.1 From 4e9a497f07457d63c74962ee0d90c96bdd98f918 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Mon, 19 Jun 2017 11:47:31 +0200 Subject: profile-count.c (profile_count::dump): Dump quality. * profile-count.c (profile_count::dump): Dump quality. (profile_count::differs_from_p): Update for unsigned val. * profile-count.h (profile_count_quality): New enum. (profile_count): Turn m_val to 62bit unsigned, add quality tracking. From-SVN: r249360 --- gcc/ChangeLog | 7 +++++ gcc/profile-count.c | 15 +++++++++-- gcc/profile-count.h | 74 +++++++++++++++++++++++++++++++++++++++++------------ 3 files changed, 77 insertions(+), 19 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 49a8109..78ded85 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-06-19 Jan Hubicka + + * profile-count.c (profile_count::dump): Dump quality. + (profile_count::differs_from_p): Update for unsigned val. + * profile-count.h (profile_count_quality): New enum. + (profile_count): Turn m_val to 62bit unsigned, add quality tracking. + 2017-06-19 Richard Biener * tree-ssa-loop-niter.h (estimate_numbers_of_iterations): Take diff --git a/gcc/profile-count.c b/gcc/profile-count.c index 5ad7178..e64d1b5 100644 --- a/gcc/profile-count.c +++ b/gcc/profile-count.c @@ -37,7 +37,15 @@ profile_count::dump (FILE *f) const if (!initialized_p ()) fprintf (f, "uninitialized"); else - fprintf (f, "%" PRId64, m_val); + { + fprintf (f, "%" PRId64, m_val); + if (m_quality == count_adjusted) + fprintf (f, "(adjusted)"); + else if (m_quality == count_afdo) + fprintf (f, "(auto FDO)"); + else if (m_quality == count_guessed) + fprintf (f, "(guessed)"); + } } void @@ -51,7 +59,7 @@ profile_count::differs_from_p (profile_count other) const { if (!initialized_p () || !other.initialized_p ()) return false; - if (m_val - other.m_val < 100 && other.m_val - m_val < 100) + if (m_val - other.m_val < 100 || other.m_val - m_val < 100) return false; if (!other.m_val) return true; @@ -64,6 +72,7 @@ profile_count::stream_in (struct lto_input_block *ib) { profile_count ret; ret.m_val = streamer_read_gcov_count (ib); + ret.m_quality = (profile_count_quality) streamer_read_uhwi (ib); return ret; } @@ -71,10 +80,12 @@ void profile_count::stream_out (struct output_block *ob) { streamer_write_gcov_count (ob, m_val); + streamer_write_uhwi (ob, m_quality); } void profile_count::stream_out (struct lto_output_stream *ob) { streamer_write_gcov_count_stream (ob, m_val); + streamer_write_uhwi_stream (ob, m_quality); } diff --git a/gcc/profile-count.h b/gcc/profile-count.h index 78ffee9..cdd7906 100644 --- a/gcc/profile-count.h +++ b/gcc/profile-count.h @@ -21,6 +21,22 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_PROFILE_COUNT_H #define GCC_PROFILE_COUNT_H +/* Quality of the proflie count. Because gengtype does not support enums + inside of clases, this is in global namespace. */ +enum profile_count_quality { + /* Profile is based on static branch prediction heuristics. It may or may + not reflect the reality. */ + count_guessed = 0, + /* Profile was determined by autofdo. */ + count_afdo = 2, + /* Profile was originally based on feedback but it was adjusted + by code duplicating optimization. It may not precisely reflect the + particular code path. */ + count_adjusted = 1, + /* Profile was read from profile feedback or determined by accurate static + method. */ + count_read = 3 +}; /* The base value for branch probability notes and edge probabilities. */ #define REG_BR_PROB_BASE 10000 @@ -58,17 +74,21 @@ along with GCC; see the file COPYING3. If not see */ - class GTY(()) profile_count { - /* Use int64_t to hold basic block counters. Should be at least + /* Use 62bit to hold basic block counters. Should be at least 64bit. Although a counter cannot be negative, we use a signed type to hold various extra stages. */ - int64_t m_val; + static const int n_bits = 62; + static const uint64_t max_count = ((uint64_t) 1 << n_bits) - 2; + static const uint64_t uninitialized_count = ((uint64_t) 1 << n_bits) - 1; + + uint64_t m_val : n_bits; + enum profile_count_quality m_quality : 2; /* Assume numbers smaller than this to multiply. This is set to make - testsuite pass, in future we may implement precise multiples in higer + testsuite pass, in future we may implement precise multiplication in higer rangers. */ static const int64_t max_safe_multiplier = 131072; public: @@ -87,7 +107,8 @@ public: static profile_count uninitialized () { profile_count c; - c.m_val = -1; + c.m_val = uninitialized_count; + c.m_quality = count_guessed; return c; } @@ -97,8 +118,9 @@ public: static profile_count from_gcov_type (gcov_type v) { profile_count ret; - gcc_checking_assert (v>=0); + gcc_checking_assert (v >= 0 && (uint64_t) v <= max_count); ret.m_val = v; + ret.m_quality = count_read; return ret; } @@ -112,7 +134,7 @@ public: /* Return true if value has been initialized. */ bool initialized_p () const { - return m_val != -1; + return m_val != uninitialized_count; } /* Return true if value can be trusted. */ bool reliable_p () const @@ -123,7 +145,7 @@ public: /* Basic operations. */ bool operator== (const profile_count &other) const { - return m_val == other.m_val; + return m_val == other.m_val && m_quality == other.m_quality; } profile_count operator+ (const profile_count &other) const { @@ -136,6 +158,7 @@ public: profile_count ret; ret.m_val = m_val + other.m_val; + ret.m_quality = MIN (m_quality, other.m_quality); return ret; } profile_count &operator+= (const profile_count &other) @@ -150,7 +173,10 @@ public: if (!initialized_p () || !other.initialized_p ()) return *this = profile_count::uninitialized (); else - m_val += other.m_val; + { + m_val += other.m_val; + m_quality = MIN (m_quality, other.m_quality); + } return *this; } profile_count operator- (const profile_count &other) const @@ -160,7 +186,8 @@ public: if (!initialized_p () || !other.initialized_p ()) return profile_count::uninitialized (); profile_count ret; - ret.m_val = MAX (m_val - other.m_val, 0); + ret.m_val = m_val >= other.m_val ? m_val - other.m_val : 0; + ret.m_quality = MIN (m_quality, other.m_quality); return ret; } profile_count &operator-= (const profile_count &other) @@ -170,14 +197,17 @@ public: if (!initialized_p () || !other.initialized_p ()) return *this = profile_count::uninitialized (); else - m_val = MAX (m_val - other.m_val, 0); + { + m_val = m_val >= other.m_val ? m_val - other.m_val: 0; + m_quality = MIN (m_quality, other.m_quality); + } return *this; } /* Return false if profile_count is bogus. */ bool verify () const { - return m_val >= -1; + return m_val != uninitialized_count || m_quality == count_guessed; } /* Comparsions are three-state and conservative. False is returned if @@ -192,11 +222,13 @@ public: } bool operator< (const gcov_type other) const { - return initialized_p () && m_val < other; + gcc_checking_assert (other >= 0); + return initialized_p () && m_val < (uint64_t) other; } bool operator> (const gcov_type other) const { - return initialized_p () && m_val > other; + gcc_checking_assert (other >= 0); + return initialized_p () && m_val > (uint64_t) other; } bool operator<= (const profile_count &other) const @@ -209,11 +241,13 @@ public: } bool operator<= (const gcov_type other) const { - return initialized_p () && m_val <= other; + gcc_checking_assert (other >= 0); + return initialized_p () && m_val <= (uint64_t) other; } bool operator>= (const gcov_type other) const { - return initialized_p () && m_val >= other; + gcc_checking_assert (other >= 0); + return initialized_p () && m_val >= (uint64_t) other; } /* PROB is a probability in scale 0...REG_BR_PROB_BASE. Scale counter @@ -227,6 +261,7 @@ public: return profile_count::uninitialized (); profile_count ret; ret.m_val = RDIV (m_val * prob, REG_BR_PROB_BASE); + ret.m_quality = MIN (m_quality, count_adjusted); return ret; } /* Return *THIS * NUM / DEN. */ @@ -243,6 +278,7 @@ public: || den <= REG_BR_PROB_BASE) && den > 0) || 1); ret.m_val = RDIV (m_val * num, den); + ret.m_quality = MIN (m_quality, count_adjusted); return ret; } profile_count apply_scale (profile_count num, profile_count den) const @@ -251,14 +287,18 @@ public: return profile_count::zero (); if (!initialized_p () || !num.initialized_p () || !den.initialized_p ()) return profile_count::uninitialized (); - profile_count ret; gcc_checking_assert (den > 0); + if (num == den) + return *this; + + profile_count ret; /* Take care for overflows! */ if (num.m_val < max_safe_multiplier || m_val < max_safe_multiplier) ret.m_val = RDIV (m_val * num.m_val, den.m_val); else ret.m_val = RDIV (m_val * RDIV (num.m_val * max_safe_multiplier, den.m_val), max_safe_multiplier); + ret.m_quality = MIN (m_quality, count_adjusted); return ret; } -- cgit v1.1 From b2c2a7e46863bbc16daada88e37b78022f0f7d12 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Mon, 19 Jun 2017 09:50:13 +0000 Subject: Fix typo From-SVN: r249361 --- gcc/profile-count.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/profile-count.h b/gcc/profile-count.h index cdd7906..42509c4 100644 --- a/gcc/profile-count.h +++ b/gcc/profile-count.h @@ -28,11 +28,11 @@ enum profile_count_quality { not reflect the reality. */ count_guessed = 0, /* Profile was determined by autofdo. */ - count_afdo = 2, + count_afdo = 1, /* Profile was originally based on feedback but it was adjusted by code duplicating optimization. It may not precisely reflect the particular code path. */ - count_adjusted = 1, + count_adjusted = 2, /* Profile was read from profile feedback or determined by accurate static method. */ count_read = 3 -- cgit v1.1 From 431abe69f1c4ba0b4b05609f2f4f9206cc6e041a Mon Sep 17 00:00:00 2001 From: Paolo Carlini Date: Mon, 19 Jun 2017 10:15:57 +0000 Subject: re PR c++/66093 (g++ produces incorrect output on code with constexpr function initializing class with private fields) 2017-06-19 Paolo Carlini PR c++/66093 * g++.dg/cpp1y/constexpr-66093.C: New. From-SVN: r249364 --- gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/g++.dg/cpp1y/constexpr-66093.C | 35 ++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-66093.C (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8153a71..f879c10 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-19 Paolo Carlini + + PR c++/66093 + * g++.dg/cpp1y/constexpr-66093.C: New. + 2017-06-19 Rainer Orth * g++.dg/other/unused1.C: Remove *-*-solaris2.[56]* from diff --git a/gcc/testsuite/g++.dg/cpp1y/constexpr-66093.C b/gcc/testsuite/g++.dg/cpp1y/constexpr-66093.C new file mode 100644 index 0000000..ad31692 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/constexpr-66093.C @@ -0,0 +1,35 @@ +// { dg-do run { target c++14 } } + +#include + +constexpr int n = 10; + +struct A { + constexpr operator const int*() const { + return data; + } + + constexpr operator int*() { + return data; + } + +private: + int data[n]; +}; + +constexpr A f() { + A a{}; + for (int i = 1; i <= n; i++) { + a[i] = i; + } + return a; +} + +A a = f(); + +int main() +{ + for (int i = 0; i < n; i++) { + assert (a[i] == i); + } +} -- cgit v1.1 From 871cc215f7507cbe9ed4b1a5a9fd884deb65c18a Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Mon, 19 Jun 2017 15:12:51 +0200 Subject: Fix multi-versioning issues (PR ipa/80732). 2017-06-19 Martin Liska PR ipa/80732 * attribs.c (make_dispatcher_decl): Do not append '.ifunc' to dispatcher function name. * multiple_target.c (replace_function_decl): New function. (create_dispatcher_calls): Redirect both edges and references. 2017-06-19 Martin Liska PR ipa/80732 * gcc.target/i386/mvc5.c: Scan indirect_function. * gcc.target/i386/mvc7.c: Likewise. * gcc.target/i386/pr80732.c: New test. From-SVN: r249365 --- gcc/ChangeLog | 8 +++ gcc/attribs.c | 6 +- gcc/multiple_target.c | 115 +++++++++++++++++++++++--------- gcc/testsuite/ChangeLog | 7 ++ gcc/testsuite/gcc.target/i386/mvc5.c | 2 +- gcc/testsuite/gcc.target/i386/mvc7.c | 2 +- gcc/testsuite/gcc.target/i386/pr80732.c | 92 +++++++++++++++++++++++++ 7 files changed, 193 insertions(+), 39 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr80732.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 78ded85..084671a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-06-19 Martin Liska + + PR ipa/80732 + * attribs.c (make_dispatcher_decl): Do not append '.ifunc' + to dispatcher function name. + * multiple_target.c (replace_function_decl): New function. + (create_dispatcher_calls): Redirect both edges and references. + 2017-06-19 Jan Hubicka * profile-count.c (profile_count::dump): Dump quality. diff --git a/gcc/attribs.c b/gcc/attribs.c index 4ba0eab..5eb19e8 100644 --- a/gcc/attribs.c +++ b/gcc/attribs.c @@ -888,12 +888,8 @@ make_dispatcher_decl (const tree decl) tree func_decl; char *func_name; tree fn_type, func_type; - bool is_uniq = false; - if (TREE_PUBLIC (decl) == 0) - is_uniq = true; - - func_name = make_unique_name (decl, "ifunc", is_uniq); + func_name = xstrdup (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); fn_type = TREE_TYPE (decl); func_type = build_function_type (TREE_TYPE (fn_type), diff --git a/gcc/multiple_target.c b/gcc/multiple_target.c index 2ee6a959..bdb5b3b 100644 --- a/gcc/multiple_target.c +++ b/gcc/multiple_target.c @@ -34,6 +34,27 @@ along with GCC; see the file COPYING3. If not see #include "target.h" #include "attribs.h" #include "pretty-print.h" +#include "gimple-iterator.h" +#include "gimple-walk.h" + +/* Walker callback that replaces all FUNCTION_DECL of a function that's + going to be versioned. */ + +static tree +replace_function_decl (tree *op, int *walk_subtrees, void *data) +{ + struct walk_stmt_info *wi = (struct walk_stmt_info *) data; + cgraph_function_version_info *info = (cgraph_function_version_info *)wi->info; + + if (TREE_CODE (*op) == FUNCTION_DECL + && info->this_node->decl == *op) + { + *op = info->dispatcher_resolver; + *walk_subtrees = 0; + } + + return NULL; +} /* If the call in NODE has multiple target attribute with multiple fields, replace it with dispatcher call and create dispatcher (once). */ @@ -41,51 +62,48 @@ along with GCC; see the file COPYING3. If not see static void create_dispatcher_calls (struct cgraph_node *node) { - cgraph_edge *e; - cgraph_edge *e_next = NULL; + ipa_ref *ref; + + if (!DECL_FUNCTION_VERSIONED (node->decl)) + return; + + auto_vec edges_to_redirect; + auto_vec references_to_redirect; + + for (unsigned i = 0; node->iterate_referring (i, ref); i++) + references_to_redirect.safe_push (ref); /* We need to remember NEXT_CALLER as it could be modified in the loop. */ - for (e = node->callers; e ;e = (e == NULL) ? e_next : e->next_caller) - { - tree resolver_decl; - tree idecl; - tree decl; - gimple *call = e->call_stmt; - struct cgraph_node *inode; - - /* Checking if call of function is call of versioned function. - Versioned function are not inlined, so there is no need to - check for inline. */ - if (!call - || !(decl = gimple_call_fndecl (call)) - || !DECL_FUNCTION_VERSIONED (decl)) - continue; + for (cgraph_edge *e = node->callers; e ; e = e->next_caller) + edges_to_redirect.safe_push (e); + if (!edges_to_redirect.is_empty () || !references_to_redirect.is_empty ()) + { if (!targetm.has_ifunc_p ()) { - error_at (gimple_location (call), + error_at (DECL_SOURCE_LOCATION (node->decl), "the call requires ifunc, which is not" " supported by this target"); - break; + return; } else if (!targetm.get_function_versions_dispatcher) { - error_at (gimple_location (call), + error_at (DECL_SOURCE_LOCATION (node->decl), "target does not support function version dispatcher"); - break; + return; } - e_next = e->next_caller; - idecl = targetm.get_function_versions_dispatcher (decl); + tree idecl = targetm.get_function_versions_dispatcher (node->decl); if (!idecl) { - error_at (gimple_location (call), + error_at (DECL_SOURCE_LOCATION (node->decl), "default target_clones attribute was not set"); - break; + return; } - inode = cgraph_node::get (idecl); + + cgraph_node *inode = cgraph_node::get (idecl); gcc_assert (inode); - resolver_decl = targetm.generate_version_dispatcher_body (inode); + tree resolver_decl = targetm.generate_version_dispatcher_body (inode); /* Update aliases. */ inode->alias = true; @@ -93,12 +111,45 @@ create_dispatcher_calls (struct cgraph_node *node) if (!inode->analyzed) inode->resolve_alias (cgraph_node::get (resolver_decl)); - e->redirect_callee (inode); - e->redirect_call_stmt_to_callee (); - /* Since REDIRECT_CALLEE modifies NEXT_CALLER field we move to - previously set NEXT_CALLER. */ - e = NULL; + /* Redirect edges. */ + unsigned i; + cgraph_edge *e; + FOR_EACH_VEC_ELT (edges_to_redirect, i, e) + { + e->redirect_callee (inode); + e->redirect_call_stmt_to_callee (); + } + + /* Redirect references. */ + FOR_EACH_VEC_ELT (references_to_redirect, i, ref) + { + if (ref->use == IPA_REF_ADDR) + { + struct walk_stmt_info wi; + memset (&wi, 0, sizeof (wi)); + wi.info = (void *)node->function_version (); + + if (dyn_cast (ref->referring)) + { + hash_set visited_nodes; + walk_tree (&DECL_INITIAL (ref->referring->decl), + replace_function_decl, &wi, &visited_nodes); + } + else + { + gimple_stmt_iterator it = gsi_for_stmt (ref->stmt); + if (ref->referring->decl != resolver_decl) + walk_gimple_stmt (&it, NULL, replace_function_decl, &wi); + } + } + else + gcc_unreachable (); + } } + + symtab->change_decl_assembler_name (node->decl, + clone_function_name (node->decl, + "default")); } /* Return length of attribute names string, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f879c10..0b55fe0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2017-06-19 Martin Liska + + PR ipa/80732 + * gcc.target/i386/mvc5.c: Scan indirect_function. + * gcc.target/i386/mvc7.c: Likewise. + * gcc.target/i386/pr80732.c: New test. + 2017-06-19 Paolo Carlini PR c++/66093 diff --git a/gcc/testsuite/gcc.target/i386/mvc5.c b/gcc/testsuite/gcc.target/i386/mvc5.c index 8fea04c..677f79f 100644 --- a/gcc/testsuite/gcc.target/i386/mvc5.c +++ b/gcc/testsuite/gcc.target/i386/mvc5.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-ifunc "" } */ /* { dg-options "-fno-inline" } */ -/* { dg-final { scan-assembler-times "foo.ifunc" 6 } } */ +/* { dg-final { scan-assembler "foo,foo.resolver" } } */ __attribute__((target_clones("default","avx","avx2"))) int diff --git a/gcc/testsuite/gcc.target/i386/mvc7.c b/gcc/testsuite/gcc.target/i386/mvc7.c index 9a9d7a3..a3697ba 100644 --- a/gcc/testsuite/gcc.target/i386/mvc7.c +++ b/gcc/testsuite/gcc.target/i386/mvc7.c @@ -3,7 +3,7 @@ /* { dg-final { scan-assembler "foo.resolver" } } */ /* { dg-final { scan-assembler "avx" } } */ /* { dg-final { scan-assembler "slm" } } */ -/* { dg-final { scan-assembler-times "foo.ifunc" 4 } } */ +/* { dg-final { scan-assembler "foo,foo.resolver" } } */ __attribute__((target_clones("avx","default","arch=slm","arch=core-avx2"))) int foo (); diff --git a/gcc/testsuite/gcc.target/i386/pr80732.c b/gcc/testsuite/gcc.target/i386/pr80732.c new file mode 100644 index 0000000..2c59c5e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr80732.c @@ -0,0 +1,92 @@ +/* PR ipa/80732 */ +/* { dg-do run } */ +/* { dg-options "-ldl -fPIC -rdynamic -O3 -g -pie" } */ +/* { dg-require-ifunc "" } */ +/* { dg-require-effective-target fma4 } */ +/* { dg-require-effective-target fpic } */ +/* { dg-require-effective-target pie } */ + +#include + +__attribute__((target_clones("default","fma"),noinline,optimize("fast-math"))) +double f1(double a, double b, double c) +{ + return a * b + c; +} + +double k1(double a, double b, double c, void **p) +{ + *p = f1; + return f1(a, b, c); +} + +__attribute__((target("fma"),optimize("fast-math"))) +static double f2_fma(double a, double b, double c) +{ + return a * b + c; +} + +__attribute__((optimize("fast-math"))) +static double f2_default(double a, double b, double c) +{ + return a * b + c; +} + +static void *f2_resolve(void) +{ + __builtin_cpu_init (); + if (__builtin_cpu_supports("fma")) + return f2_fma; + else + return f2_default; +} + +double f2(double a, double b, double c) __attribute__((ifunc("f2_resolve"))); + +double k2(double a, double b, double c, void **p) +{ + *p = f2; + return f2(a, b, c); +} + +double (*initializer) (double, double, double) = { &f1 }; + +int main() +{ + char buffer[256]; + const char *expectation = "4.93038e-32, 4.93038e-32, 4.93038e-32"; + + volatile double a = 1.0000000000000002; + volatile double b = -0.9999999999999998; + volatile double c = 1.0; + + void *hdl = dlopen(0, RTLD_NOW); + + double (*pf1)(double, double, double) = dlsym(hdl, "f1"); + double (*pk1)(double, double, double, void**) = dlsym(hdl, "k1"); + double (*_pf1)(double, double, double); + + double v1_1 = pf1(a, b, c); + double v1_2 = pk1(a, b, c, (void**)&_pf1); + double v1_3 = _pf1(a, b, c); + __builtin_sprintf (buffer, "%g, %g, %g", v1_1, v1_2, v1_3); + if (__builtin_strcmp (buffer, expectation) != 0) + __builtin_abort (); + + double (*pf2)(double, double, double) = dlsym(hdl, "f2"); + double (*pk2)(double, double, double, void**) = dlsym(hdl, "k2"); + double (*_pf2)(double, double, double); + + double v2_1 = pf2(a, b, c); + double v2_2 = pk2(a, b, c, (void**)&_pf2); + double v2_3 = _pf2(a, b, c); + __builtin_sprintf(buffer, "%g, %g, %g", v2_1, v2_2, v2_3); + if (__builtin_strcmp (buffer, expectation) != 0) + __builtin_abort (); + + __builtin_sprintf(buffer, "%g, %g, %g", initializer (a, b, c), v2_2, v2_3); + if (__builtin_strcmp (buffer, expectation) != 0) + __builtin_abort (); + + return 0; +} -- cgit v1.1 From 0d053a49b6f6daf3036be9aed19b2fb9a549418d Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Mon, 19 Jun 2017 15:19:56 +0200 Subject: Introduce 4-stages profiledbootstrap to get a better profile. 2017-06-19 Martin Liska * doc/install.texi: Document that PGO runs in 4 stages. 2017-06-19 Martin Liska * Makefile.def: Define 4 stages PGO bootstrap. * Makefile.tpl: Define FLAGS. * Makefile.in: Regenerate. From-SVN: r249366 --- gcc/ChangeLog | 4 ++++ gcc/doc/install.texi | 5 +++-- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 084671a..6ddc171 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-06-19 Martin Liska + * doc/install.texi: Document that PGO runs in 4 stages. + +2017-06-19 Martin Liska + PR ipa/80732 * attribs.c (make_dispatcher_decl): Do not append '.ifunc' to dispatcher function name. diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 8e17bcc..7c9e2f2 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -2619,8 +2619,9 @@ bootstrap the compiler with profile feedback, use @code{make profiledbootstrap}. When @samp{make profiledbootstrap} is run, it will first build a @code{stage1} compiler. This compiler is used to build a @code{stageprofile} compiler instrumented to collect execution counts of instruction and branch -probabilities. Then runtime libraries are compiled with profile collected. -Finally a @code{stagefeedback} compiler is built using the information collected. +probabilities. Training run is done by building @code{stagetrain} +compiler. Finally a @code{stagefeedback} compiler is built +using the information collected. Unlike standard bootstrap, several additional restrictions apply. The compiler used to build @code{stage1} needs to support a 64-bit integral type. -- cgit v1.1 From a6e5212a77e34682cfb591ed80e7166eaa895365 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Mon, 19 Jun 2017 15:27:48 +0200 Subject: Initialize live_switch_vars for SWITCH_BODY == STATEMENT_LIST (PR sanitizer/80879). 2017-06-19 Martin Liska PR sanitizer/80879 * gimplify.c (gimplify_switch_expr): Initialize live_switch_vars for SWITCH_BODY == STATEMENT_LIST. 2017-06-19 Martin Liska PR sanitizer/80879 * gcc.dg/asan/use-after-scope-switch-4.c: New test. From-SVN: r249368 --- gcc/ChangeLog | 6 ++++ gcc/gimplify.c | 3 +- gcc/testsuite/ChangeLog | 5 ++++ .../gcc.dg/asan/use-after-scope-switch-4.c | 35 ++++++++++++++++++++++ 4 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/asan/use-after-scope-switch-4.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6ddc171..aab38b1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2017-06-19 Martin Liska + PR sanitizer/80879 + * gimplify.c (gimplify_switch_expr): + Initialize live_switch_vars for SWITCH_BODY == STATEMENT_LIST. + +2017-06-19 Martin Liska + * doc/install.texi: Document that PGO runs in 4 stages. 2017-06-19 Martin Liska diff --git a/gcc/gimplify.c b/gcc/gimplify.c index 9af95a2..cf82f95 100644 --- a/gcc/gimplify.c +++ b/gcc/gimplify.c @@ -2279,7 +2279,8 @@ gimplify_switch_expr (tree *expr_p, gimple_seq *pre_p) /* Do not create live_switch_vars if SWITCH_BODY is not a BIND_EXPR. */ saved_live_switch_vars = gimplify_ctxp->live_switch_vars; - if (TREE_CODE (SWITCH_BODY (switch_expr)) == BIND_EXPR) + tree_code body_type = TREE_CODE (SWITCH_BODY (switch_expr)); + if (body_type == BIND_EXPR || body_type == STATEMENT_LIST) gimplify_ctxp->live_switch_vars = new hash_set (4); else gimplify_ctxp->live_switch_vars = NULL; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0b55fe0..26e527c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2017-06-19 Martin Liska + PR sanitizer/80879 + * gcc.dg/asan/use-after-scope-switch-4.c: New test. + +2017-06-19 Martin Liska + PR ipa/80732 * gcc.target/i386/mvc5.c: Scan indirect_function. * gcc.target/i386/mvc7.c: Likewise. diff --git a/gcc/testsuite/gcc.dg/asan/use-after-scope-switch-4.c b/gcc/testsuite/gcc.dg/asan/use-after-scope-switch-4.c new file mode 100644 index 0000000..290a920 --- /dev/null +++ b/gcc/testsuite/gcc.dg/asan/use-after-scope-switch-4.c @@ -0,0 +1,35 @@ +// { dg-do run } +// { dg-additional-options "-fdump-tree-gimple" } + +int *ptr; + +struct a +{ + int c; +}; + +int main(int argc, char **argv) +{ + struct a e; + e.c = 2; + int x = 0; + + for (;;) + switch (e.c) + case 3: + { + int resxxx; + case 2: + ptr = &resxxx; + *ptr = 123; + + if (x) + return 0; + else + x = 1; + } + + return 1; +} + +/* { dg-final { scan-tree-dump-times "ASAN_MARK \\(UNPOISON, &resxxx, \[0-9\]\\);" 2 "gimple" } } */ -- cgit v1.1 From c14c0b1568f84e974152d2e2c1bc3da384a16f2d Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Mon, 19 Jun 2017 14:13:58 +0000 Subject: re PR c++/81119 (-Wshadow warns on "typedef struct foo foo;") PR c++/81119 * name-lookup.c (update_binding): Only warn about constructors hidden by functions. PR c++/81119 * g++.dg/warn/pr81119.C: New. From-SVN: r249369 --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/name-lookup.c | 23 ++++++++--------------- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/warn/pr81119.C | 20 ++++++++++++++++++++ 4 files changed, 39 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/g++.dg/warn/pr81119.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 465e7d9..fece2d0 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2017-06-19 Nathan Sidwell + + PR c++/81119 + * name-lookup.c (update_binding): Only warn about constructors + hidden by functions. + 2017-06-17 Jason Merrill PR c++/60063 - -Wunused-local-typedefs and templates. diff --git a/gcc/cp/name-lookup.c b/gcc/cp/name-lookup.c index 6ed164d..a337942 100644 --- a/gcc/cp/name-lookup.c +++ b/gcc/cp/name-lookup.c @@ -1784,6 +1784,14 @@ update_binding (cp_binding_level *level, cxx_binding *binding, tree *slot, else goto conflict; + if (to_type != old_type + && warn_shadow + && MAYBE_CLASS_TYPE_P (TREE_TYPE (to_type)) + && !(DECL_IN_SYSTEM_HEADER (decl) + && DECL_IN_SYSTEM_HEADER (to_type))) + warning (OPT_Wshadow, "%q#D hides constructor for %q#D", + decl, to_type); + to_val = ovl_insert (decl, old); } else if (!old) @@ -1849,21 +1857,6 @@ update_binding (cp_binding_level *level, cxx_binding *binding, tree *slot, add_decl_to_level (level, to_add); } - if (to_type != old_type) - { - gcc_checking_assert (!old_type - && TREE_CODE (to_type) == TYPE_DECL - && DECL_ARTIFICIAL (to_type)); - - tree type = TREE_TYPE (to_type); - if (to_type != decl - && MAYBE_CLASS_TYPE_P (type) && warn_shadow - && (!DECL_IN_SYSTEM_HEADER (decl) - || !DECL_IN_SYSTEM_HEADER (to_type))) - warning (OPT_Wshadow, "%q#D hides constructor for %q#T", - decl, type); - } - if (slot) { if (STAT_HACK_P (*slot)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 26e527c..c7729e8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-19 Nathan Sidwell + + PR c++/81119 + * g++.dg/warn/pr81119.C: New. + 2017-06-19 Martin Liska PR sanitizer/80879 diff --git a/gcc/testsuite/g++.dg/warn/pr81119.C b/gcc/testsuite/g++.dg/warn/pr81119.C new file mode 100644 index 0000000..2f82236 --- /dev/null +++ b/gcc/testsuite/g++.dg/warn/pr81119.C @@ -0,0 +1,20 @@ +// PR c++/81119 Wshadow regression +// { dg-additional-options "-Wshadow" } + +struct A; +typedef A A; // No warning, does not hide + +struct B; // { dg-message "previous" } +typedef int B; // { dg-error "conflicting" } + +struct C; +void C (); // { dg-warning "hides constructor" } +void C (int); // warning not repeated + +struct D; +int D; // no warning, not a function + +struct E; + +enum X + {E}; // no warning, not a function -- cgit v1.1 From 74e56995145901773528b4cfdec971e8967d21c0 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Mon, 19 Jun 2017 14:19:35 +0000 Subject: pt.c (coerce_template_parms): Fix indentation. * pt.c (coerce_template_parms): Fix indentation. (tsubst_decl): Remove repeated SET_DECL_RTL. Move VAR_P handling in to single block. From-SVN: r249370 --- gcc/cp/ChangeLog | 4 ++++ gcc/cp/pt.c | 14 ++++++-------- 2 files changed, 10 insertions(+), 8 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index fece2d0..5b90bbf 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,9 @@ 2017-06-19 Nathan Sidwell + * pt.c (coerce_template_parms): Fix indentation. + (tsubst_decl): Remove repeated SET_DECL_RTL. Move VAR_P handling + in to single block. + PR c++/81119 * name-lookup.c (update_binding): Only warn about constructors hidden by functions. diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 57be0ab..e5238ad 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -8101,10 +8101,10 @@ coerce_template_parms (tree parms, parm = TREE_VEC_ELT (parms, parm_idx); if (parm == error_mark_node) - { - TREE_VEC_ELT (new_inner_args, arg_idx) = error_mark_node; - continue; - } + { + TREE_VEC_ELT (new_inner_args, arg_idx) = error_mark_node; + continue; + } /* Calculate the next argument. */ if (arg_idx < nargs) @@ -12947,13 +12947,11 @@ tsubst_decl (tree t, tree args, tsubst_flags_t complain) /* The initializer must not be expanded until it is required; see [temp.inst]. */ DECL_INITIAL (r) = NULL_TREE; - if (VAR_P (r)) - SET_DECL_MODE (r, VOIDmode); - if (CODE_CONTAINS_STRUCT (TREE_CODE (t), TS_DECL_WRTL)) - SET_DECL_RTL (r, NULL); DECL_SIZE (r) = DECL_SIZE_UNIT (r) = 0; if (VAR_P (r)) { + SET_DECL_MODE (r, VOIDmode); + /* Possibly limit visibility based on template args. */ DECL_VISIBILITY (r) = VISIBILITY_DEFAULT; if (DECL_VISIBILITY_SPECIFIED (t)) -- cgit v1.1 From 9787269815559a63fbbda58b35137f832a612984 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 19 Jun 2017 16:35:18 +0200 Subject: re PR ipa/81112 (internal compiler error: tree check: expected integer_cst, have range_expr in get_len, at tree.h:5321) PR ipa/81112 * g++.dg/torture/pr81112.C: Add -Wno-psabi to dg-additional-options. From-SVN: r249371 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/torture/pr81112.C | 1 + 2 files changed, 6 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c7729e8..f382a38 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-19 Jakub Jelinek + + PR ipa/81112 + * g++.dg/torture/pr81112.C: Add -Wno-psabi to dg-additional-options. + 2017-06-19 Nathan Sidwell PR c++/81119 diff --git a/gcc/testsuite/g++.dg/torture/pr81112.C b/gcc/testsuite/g++.dg/torture/pr81112.C index 10e0ebe..e9ef2a8 100644 --- a/gcc/testsuite/g++.dg/torture/pr81112.C +++ b/gcc/testsuite/g++.dg/torture/pr81112.C @@ -1,4 +1,5 @@ // { dg-do compile } +// { dg-additional-options "-Wno-psabi" } class AssertionResult { bool success_; -- cgit v1.1 From 343ae898b17490d15c98f711ffcb04c88cca9235 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 19 Jun 2017 15:01:13 +0000 Subject: re PR bootstrap/80887 (gnat bootstrap fails at s-regpat.o: raised STORAGE_ERROR : stack overflow or erroneous memory access) 2017-06-19 Richard Biener PR tree-optimization/80887 c/ * gimple-parser.c (c_parser_gimple_postfix_expression): Handle negated _Literals to parse _Literal (int) -1. * tree-ssa-sccvn.c (mprts_hook_cnt): New global. (vn_lookup_simplify_result): Allow only mprts_hook_cnt succesful simplified lookups, then reset mprts_hook. (vn_nary_build_or_lookup_1): Set mprts_hook_cnt to 9 before simplifying. (try_to_simplify): Likewise. * gcc.dg/tree-ssa/pr80887.c: New testcase. From-SVN: r249373 --- gcc/ChangeLog | 10 ++++++++++ gcc/c/ChangeLog | 5 +++++ gcc/c/gimple-parser.c | 16 ++++++++++++++-- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/tree-ssa/pr80887.c | 32 ++++++++++++++++++++++++++++++++ gcc/tree-ssa-sccvn.c | 21 +++++++++++++++++++-- 6 files changed, 85 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr80887.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aab38b1..99a7242 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2017-06-19 Richard Biener + + PR tree-optimization/80887 + * tree-ssa-sccvn.c (mprts_hook_cnt): New global. + (vn_lookup_simplify_result): Allow only mprts_hook_cnt succesful + simplified lookups, then reset mprts_hook. + (vn_nary_build_or_lookup_1): Set mprts_hook_cnt to 9 before + simplifying. + (try_to_simplify): Likewise. + 2017-06-19 Martin Liska PR sanitizer/80879 diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 173fa92..58d59a6 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,8 @@ +2017-06-19 Richard Biener + + * gimple-parser.c (c_parser_gimple_postfix_expression): Handle + negated _Literals to parse _Literal (int) -1. + 2017-06-13 Martin Liska PR sanitize/78204 diff --git a/gcc/c/gimple-parser.c b/gcc/c/gimple-parser.c index 4a55904..22f58f4 100644 --- a/gcc/c/gimple-parser.c +++ b/gcc/c/gimple-parser.c @@ -850,7 +850,7 @@ c_parser_gimple_postfix_expression (c_parser *parser) } else if (strcmp (IDENTIFIER_POINTER (id), "_Literal") == 0) { - /* _Literal '(' type-name ')' number */ + /* _Literal '(' type-name ')' [ '-' ] constant */ c_parser_consume_token (parser); tree type = NULL_TREE; if (c_parser_require (parser, CPP_OPEN_PAREN, "expected %<(%>")) @@ -862,15 +862,27 @@ c_parser_gimple_postfix_expression (c_parser *parser) c_parser_skip_until_found (parser, CPP_CLOSE_PAREN, "expected %<)%>"); } + bool neg_p; + if ((neg_p = c_parser_next_token_is (parser, CPP_MINUS))) + c_parser_consume_token (parser); tree val = c_parser_gimple_postfix_expression (parser).value; if (! type || ! val || val == error_mark_node - || TREE_CODE (val) != INTEGER_CST) + || ! CONSTANT_CLASS_P (val)) { c_parser_error (parser, "invalid _Literal"); return expr; } + if (neg_p) + { + val = const_unop (NEGATE_EXPR, TREE_TYPE (val), val); + if (! val) + { + c_parser_error (parser, "invalid _Literal"); + return expr; + } + } expr.value = fold_convert (type, val); return expr; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f382a38..47e2a98 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-19 Richard Biener + + PR tree-optimization/80887 + * gcc.dg/tree-ssa/pr80887.c: New testcase. + 2017-06-19 Jakub Jelinek PR ipa/81112 diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr80887.c b/gcc/testsuite/gcc.dg/tree-ssa/pr80887.c new file mode 100644 index 0000000..df7a9d9 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr80887.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-fgimple -O" } */ + +int pos; +void __GIMPLE (startwith("fre")) +f() +{ + unsigned int t2; + unsigned int t1; + int a; + unsigned int u; + int _1; + int _2; + int _3; + unsigned int _4; + int _5; + unsigned int _6; + +bb_2: + _1 = pos; + _2 = _1 + 1; + pos = _2; + _3 = pos; + _4 = (unsigned int) _3; + u_9 = _4 + 4294967295u; + a_10 = pos; + _5 = a_10 + _Literal (int) -1; + t1_11 = (unsigned int) _5; + _6 = (unsigned int) a_10; + t2_12 = _6 + 4294967294u; + return; +} diff --git a/gcc/tree-ssa-sccvn.c b/gcc/tree-ssa-sccvn.c index 419da47..324cd73 100644 --- a/gcc/tree-ssa-sccvn.c +++ b/gcc/tree-ssa-sccvn.c @@ -1639,6 +1639,7 @@ vn_reference_lookup_or_insert_for_pieces (tree vuse, } static vn_nary_op_t vn_nary_op_insert_stmt (gimple *stmt, tree result); +static unsigned mprts_hook_cnt; /* Hook for maybe_push_res_to_seq, lookup the expression in the VN tables. */ @@ -1648,8 +1649,22 @@ vn_lookup_simplify_result (code_helper rcode, tree type, tree *ops) if (!rcode.is_tree_code ()) return NULL_TREE; vn_nary_op_t vnresult = NULL; - return vn_nary_op_lookup_pieces (TREE_CODE_LENGTH ((tree_code) rcode), - (tree_code) rcode, type, ops, &vnresult); + tree res = vn_nary_op_lookup_pieces (TREE_CODE_LENGTH ((tree_code) rcode), + (tree_code) rcode, type, ops, &vnresult); + /* We can end up endlessly recursing simplifications if the lookup above + presents us with a def-use chain that mirrors the original simplification. + See PR80887 for an example. Limit successful lookup artificially + to 10 times if we are called as mprts_hook. */ + if (res + && mprts_hook + && --mprts_hook_cnt == 0) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "Resetting mprts_hook after too many " + "invocations.\n"); + mprts_hook = NULL; + } + return res; } /* Return a value-number for RCODE OPS... either by looking up an existing @@ -1666,6 +1681,7 @@ vn_nary_build_or_lookup_1 (code_helper rcode, tree type, tree *ops, So first simplify and lookup this expression to see if it is already available. */ mprts_hook = vn_lookup_simplify_result; + mprts_hook_cnt = 9; bool res = false; switch (TREE_CODE_LENGTH ((tree_code) rcode)) { @@ -3896,6 +3912,7 @@ try_to_simplify (gassign *stmt) /* First try constant folding based on our current lattice. */ mprts_hook = vn_lookup_simplify_result; + mprts_hook_cnt = 9; tem = gimple_fold_stmt_to_constant_1 (stmt, vn_valueize, vn_valueize); mprts_hook = NULL; if (tem -- cgit v1.1 From 21e4389f5029128cf6dc6377ffe678711e91aee4 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 19 Jun 2017 15:08:02 +0000 Subject: re PR tree-optimization/81118 (ice in remove_redundant_iv_tests) 2017-06-19 Richard Biener PR middle-end/81118 * tree-cfgcleanup.c (cleanup_tree_cfg_noloop): Clear niter estimates if we changed anything. * gcc.dg/torture/pr81118.c: New testcase. From-SVN: r249374 --- gcc/ChangeLog | 6 ++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/torture/pr81118.c | 14 ++++++++++++++ gcc/tree-cfgcleanup.c | 7 ++++++- 4 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/torture/pr81118.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 99a7242..64fa389 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2017-06-19 Richard Biener + PR middle-end/81118 + * tree-cfgcleanup.c (cleanup_tree_cfg_noloop): Clear niter + estimates if we changed anything. + +2017-06-19 Richard Biener + PR tree-optimization/80887 * tree-ssa-sccvn.c (mprts_hook_cnt): New global. (vn_lookup_simplify_result): Allow only mprts_hook_cnt succesful diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 47e2a98..a27eac2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2017-06-19 Richard Biener + PR middle-end/81118 + * gcc.dg/torture/pr81118.c: New testcase. + +2017-06-19 Richard Biener + PR tree-optimization/80887 * gcc.dg/tree-ssa/pr80887.c: New testcase. diff --git a/gcc/testsuite/gcc.dg/torture/pr81118.c b/gcc/testsuite/gcc.dg/torture/pr81118.c new file mode 100644 index 0000000..42d83fd --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr81118.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-w" } */ + +int a[7], b; +int c() +{ + int d, e; + for (; d; d++) + if (a[d]) + if (b) + return; + else if (d >= e) + return 0; +} diff --git a/gcc/tree-cfgcleanup.c b/gcc/tree-cfgcleanup.c index 4cab592..8bb5e23 100644 --- a/gcc/tree-cfgcleanup.c +++ b/gcc/tree-cfgcleanup.c @@ -839,7 +839,12 @@ cleanup_tree_cfg_noloop (void) timevar_pop (TV_TREE_CLEANUP_CFG); if (changed && current_loops) - loops_state_set (LOOPS_NEED_FIXUP); + { + /* Removing edges and/or blocks may make recorded bounds refer + to stale GIMPLE stmts now, so clear them. */ + free_numbers_of_iterations_estimates (cfun); + loops_state_set (LOOPS_NEED_FIXUP); + } return changed; } -- cgit v1.1 From 4301ae2263d214d1c4b8e5d3d210e0aafff19e47 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 19 Jun 2017 17:27:40 +0200 Subject: re PR sanitizer/81111 (Cannot build libstdc++ with -fsanitize=undefined) PR sanitizer/81111 * ubsan.c (ubsan_encode_value): If current_function_decl is NULL, use create_tmp_var_raw instead of create_tmp_var, mark it addressable just by setting TREE_ADDRESSABLE on the result and use a TARGET_EXPR. * g++.dg/ubsan/pr81111.C: New test. From-SVN: r249375 --- gcc/ChangeLog | 7 ++++++ gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/g++.dg/ubsan/pr81111.C | 45 ++++++++++++++++++++++++++++++++++++ gcc/ubsan.c | 27 ++++++++++++++++++---- 4 files changed, 79 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ubsan/pr81111.C (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 64fa389..c165b7f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-06-19 Jakub Jelinek + + PR sanitizer/81111 + * ubsan.c (ubsan_encode_value): If current_function_decl is NULL, + use create_tmp_var_raw instead of create_tmp_var, mark it addressable + just by setting TREE_ADDRESSABLE on the result and use a TARGET_EXPR. + 2017-06-19 Richard Biener PR middle-end/81118 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a27eac2..b38e45e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-19 Jakub Jelinek + + PR sanitizer/81111 + * g++.dg/ubsan/pr81111.C: New test. + 2017-06-19 Richard Biener PR middle-end/81118 diff --git a/gcc/testsuite/g++.dg/ubsan/pr81111.C b/gcc/testsuite/g++.dg/ubsan/pr81111.C new file mode 100644 index 0000000..6d54a2f --- /dev/null +++ b/gcc/testsuite/g++.dg/ubsan/pr81111.C @@ -0,0 +1,45 @@ +// PR sanitizer/81111 +// { dg-do compile } +// { dg-options "-fsanitize=shift" } + +template +struct N +{ + static const V m = (((V)(-1) < 0) + ? (V)1 << (sizeof(V) * __CHAR_BIT__ - ((V)(-1) < 0)) + : (V) 0); +}; + +template +const V N::m; + +template +struct O +{ + static const V m = (V)1 << sizeof(V) * __CHAR_BIT__; +}; + +template +const V O::m; + +void +foo () +{ + N::m; + N::m; +#ifdef __SIZEOF_INT128__ + N<__int128>::m; + N::m; +#endif +} + +void +bar () +{ + O::m; + O::m; +#ifdef __SIZEOF_INT128__ + O<__int128>::m; + O::m; +#endif +} diff --git a/gcc/ubsan.c b/gcc/ubsan.c index 52ba5b5..855b2ea 100644 --- a/gcc/ubsan.c +++ b/gcc/ubsan.c @@ -143,9 +143,17 @@ ubsan_encode_value (tree t, bool in_expand_p) { /* The reason for this is that we don't want to pessimize code by making vars unnecessarily addressable. */ - tree var = create_tmp_var (type); - tree tem = build2 (MODIFY_EXPR, void_type_node, var, t); - mark_addressable (var); + tree var; + if (current_function_decl) + { + var = create_tmp_var (type); + mark_addressable (var); + } + else + { + var = create_tmp_var_raw (type); + TREE_ADDRESSABLE (var) = 1; + } if (in_expand_p) { rtx mem @@ -156,8 +164,17 @@ ubsan_encode_value (tree t, bool in_expand_p) expand_assignment (var, t, false); return build_fold_addr_expr (var); } - t = build_fold_addr_expr (var); - return build2 (COMPOUND_EXPR, TREE_TYPE (t), tem, t); + if (current_function_decl) + { + tree tem = build2 (MODIFY_EXPR, void_type_node, var, t); + t = build_fold_addr_expr (var); + return build2 (COMPOUND_EXPR, TREE_TYPE (t), tem, t); + } + else + { + var = build4 (TARGET_EXPR, type, var, t, NULL_TREE, NULL_TREE); + return build_fold_addr_expr (var); + } } else return build_fold_addr_expr (t); -- cgit v1.1 From 9f8fafe847daf2c1bc1721d6d97203686567549d Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 19 Jun 2017 17:28:42 +0200 Subject: re PR sanitizer/81125 (-fsanitize=undefined ICE) PR sanitizer/81125 * ubsan.h (enum ubsan_encode_value_phase): New. (ubsan_encode_value): Change second argument to enum ubsan_encode_value_phase with default value of UBSAN_ENCODE_VALUE_GENERIC. * ubsan.c (ubsan_encode_value): Change second argument to enum ubsan_encode_value_phase PHASE from bool IN_EXPAND_P, adjust uses, for UBSAN_ENCODE_VALUE_GENERIC use just create_tmp_var_raw instead of create_tmp_var and use a TARGET_EXPR. (ubsan_expand_bounds_ifn, ubsan_build_overflow_builtin, instrument_bool_enum_load, ubsan_instrument_float_cast): Adjust ubsan_encode_value callers. * g++.dg/ubsan/pr81125.C: New test. From-SVN: r249376 --- gcc/ChangeLog | 14 ++++++++++++++ gcc/testsuite/ChangeLog | 3 +++ gcc/testsuite/g++.dg/ubsan/pr81125.C | 20 ++++++++++++++++++++ gcc/ubsan.c | 32 +++++++++++++++++--------------- gcc/ubsan.h | 10 +++++++++- 5 files changed, 63 insertions(+), 16 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ubsan/pr81125.C (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c165b7f..396f112 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,19 @@ 2017-06-19 Jakub Jelinek + PR sanitizer/81125 + * ubsan.h (enum ubsan_encode_value_phase): New. + (ubsan_encode_value): Change second argument to + enum ubsan_encode_value_phase with default value of + UBSAN_ENCODE_VALUE_GENERIC. + * ubsan.c (ubsan_encode_value): Change second argument to + enum ubsan_encode_value_phase PHASE from bool IN_EXPAND_P, + adjust uses, for UBSAN_ENCODE_VALUE_GENERIC use just + create_tmp_var_raw instead of create_tmp_var and use a + TARGET_EXPR. + (ubsan_expand_bounds_ifn, ubsan_build_overflow_builtin, + instrument_bool_enum_load, ubsan_instrument_float_cast): Adjust + ubsan_encode_value callers. + PR sanitizer/81111 * ubsan.c (ubsan_encode_value): If current_function_decl is NULL, use create_tmp_var_raw instead of create_tmp_var, mark it addressable diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b38e45e..ecec608 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2017-06-19 Jakub Jelinek + PR sanitizer/81125 + * g++.dg/ubsan/pr81125.C: New test. + PR sanitizer/81111 * g++.dg/ubsan/pr81111.C: New test. diff --git a/gcc/testsuite/g++.dg/ubsan/pr81125.C b/gcc/testsuite/g++.dg/ubsan/pr81125.C new file mode 100644 index 0000000..c91ddc7 --- /dev/null +++ b/gcc/testsuite/g++.dg/ubsan/pr81125.C @@ -0,0 +1,20 @@ +// PR sanitizer/81125 +// { dg-do compile } +// { dg-options "-fsanitize=undefined" } + +#ifdef __SIZEOF_INT128__ +typedef __int128 T; +#else +typedef long long int T; +#endif + +struct A +{ + A (long); + T a; +}; + +A::A (long c) +{ + long b = a % c; +} diff --git a/gcc/ubsan.c b/gcc/ubsan.c index 855b2ea..44effdd 100644 --- a/gcc/ubsan.c +++ b/gcc/ubsan.c @@ -114,10 +114,10 @@ decl_for_type_insert (tree type, tree decl) /* Helper routine, which encodes a value in the pointer_sized_int_node. Arguments with precision <= POINTER_SIZE are passed directly, the rest is passed by reference. T is a value we are to encode. - IN_EXPAND_P is true if this function is called during expansion. */ + PHASE determines when this function is called. */ tree -ubsan_encode_value (tree t, bool in_expand_p) +ubsan_encode_value (tree t, enum ubsan_encode_value_phase phase) { tree type = TREE_TYPE (t); const unsigned int bitsize = GET_MODE_BITSIZE (TYPE_MODE (type)); @@ -144,7 +144,7 @@ ubsan_encode_value (tree t, bool in_expand_p) /* The reason for this is that we don't want to pessimize code by making vars unnecessarily addressable. */ tree var; - if (current_function_decl) + if (phase != UBSAN_ENCODE_VALUE_GENERIC) { var = create_tmp_var (type); mark_addressable (var); @@ -154,7 +154,7 @@ ubsan_encode_value (tree t, bool in_expand_p) var = create_tmp_var_raw (type); TREE_ADDRESSABLE (var) = 1; } - if (in_expand_p) + if (phase == UBSAN_ENCODE_VALUE_RTL) { rtx mem = assign_stack_temp_for_type (TYPE_MODE (type), @@ -164,7 +164,7 @@ ubsan_encode_value (tree t, bool in_expand_p) expand_assignment (var, t, false); return build_fold_addr_expr (var); } - if (current_function_decl) + if (phase != UBSAN_ENCODE_VALUE_GENERIC) { tree tem = build2 (MODIFY_EXPR, void_type_node, var, t); t = build_fold_addr_expr (var); @@ -725,9 +725,9 @@ ubsan_expand_bounds_ifn (gimple_stmt_iterator *gsi) ? BUILT_IN_UBSAN_HANDLE_OUT_OF_BOUNDS : BUILT_IN_UBSAN_HANDLE_OUT_OF_BOUNDS_ABORT; tree fn = builtin_decl_explicit (bcode); - tree val - = force_gimple_operand_gsi (gsi, ubsan_encode_value (orig_index), true, - NULL_TREE, true, GSI_SAME_STMT); + tree val = ubsan_encode_value (orig_index, UBSAN_ENCODE_VALUE_GIMPLE); + val = force_gimple_operand_gsi (gsi, val, true, NULL_TREE, true, + GSI_SAME_STMT); g = gimple_build_call (fn, 2, data, val); } gimple_set_location (g, loc); @@ -1283,9 +1283,11 @@ ubsan_build_overflow_builtin (tree_code code, location_t loc, tree lhstype, tree fn = builtin_decl_explicit (fn_code); return build_call_expr_loc (loc, fn, 2 + (code != NEGATE_EXPR), build_fold_addr_expr_loc (loc, data), - ubsan_encode_value (op0, true), - op1 ? ubsan_encode_value (op1, true) - : NULL_TREE); + ubsan_encode_value (op0, UBSAN_ENCODE_VALUE_RTL), + op1 + ? ubsan_encode_value (op1, + UBSAN_ENCODE_VALUE_RTL) + : NULL_TREE); } /* Perform the signed integer instrumentation. GSI is the iterator @@ -1476,9 +1478,9 @@ instrument_bool_enum_load (gimple_stmt_iterator *gsi) : BUILT_IN_UBSAN_HANDLE_LOAD_INVALID_VALUE_ABORT; tree fn = builtin_decl_explicit (bcode); - tree val = force_gimple_operand_gsi (&gsi2, ubsan_encode_value (urhs), - true, NULL_TREE, true, - GSI_SAME_STMT); + tree val = ubsan_encode_value (urhs, UBSAN_ENCODE_VALUE_GIMPLE); + val = force_gimple_operand_gsi (&gsi2, val, true, NULL_TREE, true, + GSI_SAME_STMT); g = gimple_build_call (fn, 2, data, val); } gimple_set_location (g, loc); @@ -1642,7 +1644,7 @@ ubsan_instrument_float_cast (location_t loc, tree type, tree expr) fn = builtin_decl_explicit (bcode); fn = build_call_expr_loc (loc, fn, 2, build_fold_addr_expr_loc (loc, data), - ubsan_encode_value (expr, false)); + ubsan_encode_value (expr)); } return fold_build3 (COND_EXPR, void_type_node, t, fn, integer_zero_node); diff --git a/gcc/ubsan.h b/gcc/ubsan.h index fddd359..6593423 100644 --- a/gcc/ubsan.h +++ b/gcc/ubsan.h @@ -42,6 +42,13 @@ enum ubsan_print_style { UBSAN_PRINT_ARRAY }; +/* This controls ubsan_encode_value behavior. */ +enum ubsan_encode_value_phase { + UBSAN_ENCODE_VALUE_GENERIC, + UBSAN_ENCODE_VALUE_GIMPLE, + UBSAN_ENCODE_VALUE_RTL +}; + extern bool ubsan_expand_bounds_ifn (gimple_stmt_iterator *); extern bool ubsan_expand_null_ifn (gimple_stmt_iterator *); extern bool ubsan_expand_objsize_ifn (gimple_stmt_iterator *); @@ -49,7 +56,8 @@ extern bool ubsan_expand_vptr_ifn (gimple_stmt_iterator *); extern bool ubsan_instrument_unreachable (gimple_stmt_iterator *); extern tree ubsan_create_data (const char *, int, const location_t *, ...); extern tree ubsan_type_descriptor (tree, enum ubsan_print_style = UBSAN_PRINT_NORMAL); -extern tree ubsan_encode_value (tree, bool = false); +extern tree ubsan_encode_value (tree, enum ubsan_encode_value_phase + = UBSAN_ENCODE_VALUE_GENERIC); extern bool is_ubsan_builtin_p (tree); extern tree ubsan_build_overflow_builtin (tree_code, location_t, tree, tree, tree, tree *); -- cgit v1.1 From c9f8853f9e74816ccb68a5a549f1f61295ce07ed Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 19 Jun 2017 19:56:44 +0200 Subject: tree-ssa-structalias.c (get_constraint_for_ptr_offset): Multiply in UWHI to avoid undefined overflow. * tree-ssa-structalias.c (get_constraint_for_ptr_offset): Multiply in UWHI to avoid undefined overflow. From-SVN: r249381 --- gcc/ChangeLog | 3 +++ gcc/tree-ssa-structalias.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 396f112..268abf3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,8 @@ 2017-06-19 Jakub Jelinek + * tree-ssa-structalias.c (get_constraint_for_ptr_offset): Multiply + in UWHI to avoid undefined overflow. + PR sanitizer/81125 * ubsan.h (enum ubsan_encode_value_phase): New. (ubsan_encode_value): Change second argument to diff --git a/gcc/tree-ssa-structalias.c b/gcc/tree-ssa-structalias.c index a4abd28..e563e9d 100644 --- a/gcc/tree-ssa-structalias.c +++ b/gcc/tree-ssa-structalias.c @@ -3087,7 +3087,7 @@ get_constraint_for_ptr_offset (tree ptr, tree offset, { /* Make sure the bit-offset also fits. */ HOST_WIDE_INT rhsunitoffset = soffset.to_shwi (); - rhsoffset = rhsunitoffset * BITS_PER_UNIT; + rhsoffset = rhsunitoffset * (unsigned HOST_WIDE_INT) BITS_PER_UNIT; if (rhsunitoffset != rhsoffset / BITS_PER_UNIT) rhsoffset = UNKNOWN_OFFSET; } -- cgit v1.1 From 4b691b139f04d13a00a959020ff976fdab60b9b1 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Mon, 19 Jun 2017 14:20:10 -0400 Subject: PR c++/81073 - constexpr and static var in statement-expression. * typeck2.c (store_init_value): Always call require_potential_constant_expression. * pt.c (convert_nontype_argument): Likewise. * constexpr.c (potential_constant_expression_1): Adjust message. Use decl_maybe_constant_var_p instead of decl_constant_var_p. * decl2.c (decl_maybe_constant_var_p): Consider initializer. From-SVN: r249382 --- gcc/cp/ChangeLog | 10 ++++++++++ gcc/cp/constexpr.c | 11 ++++++----- gcc/cp/decl2.c | 15 ++++++++++++--- gcc/cp/pt.c | 8 ++++---- gcc/cp/typeck2.c | 3 +-- gcc/testsuite/g++.dg/cpp0x/constexpr-diag1.C | 4 ++-- gcc/testsuite/g++.dg/cpp0x/constexpr-trivial2.C | 2 +- gcc/testsuite/g++.dg/ext/stmtexpr19.C | 17 +++++++++++++++++ 8 files changed, 53 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ext/stmtexpr19.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 5b90bbf..55ba486 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,13 @@ +2017-06-19 Jason Merrill + + PR c++/81073 - constexpr and static var in statement-expression. + * typeck2.c (store_init_value): Always call + require_potential_constant_expression. + * pt.c (convert_nontype_argument): Likewise. + * constexpr.c (potential_constant_expression_1): Adjust message. + Use decl_maybe_constant_var_p instead of decl_constant_var_p. + * decl2.c (decl_maybe_constant_var_p): Consider initializer. + 2017-06-19 Nathan Sidwell * pt.c (coerce_template_parms): Fix indentation. diff --git a/gcc/cp/constexpr.c b/gcc/cp/constexpr.c index ae24e40..569a247 100644 --- a/gcc/cp/constexpr.c +++ b/gcc/cp/constexpr.c @@ -5212,10 +5212,11 @@ potential_constant_expression_1 (tree t, bool want_rval, bool strict, if (want_rval && !var_in_maybe_constexpr_fn (t) && !type_dependent_expression_p (t) - && !decl_constant_var_p (t) + && !decl_maybe_constant_var_p (t) && (strict || !CP_TYPE_CONST_NON_VOLATILE_P (TREE_TYPE (t)) - || !DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (t)) + || (DECL_INITIAL (t) + && !DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (t))) && COMPLETE_TYPE_P (TREE_TYPE (t)) && !is_really_empty_class (TREE_TYPE (t))) { @@ -5540,21 +5541,21 @@ potential_constant_expression_1 (tree t, bool want_rval, bool strict, { if (flags & tf_error) error_at (DECL_SOURCE_LOCATION (tmp), "%qD declared " - "% in % function", tmp); + "% in % context", tmp); return false; } else if (CP_DECL_THREAD_LOCAL_P (tmp)) { if (flags & tf_error) error_at (DECL_SOURCE_LOCATION (tmp), "%qD declared " - "% in % function", tmp); + "% in % context", tmp); return false; } else if (!DECL_NONTRIVIALLY_INITIALIZED_P (tmp)) { if (flags & tf_error) error_at (DECL_SOURCE_LOCATION (tmp), "uninitialized " - "variable %qD in % function", tmp); + "variable %qD in % context", tmp); return false; } } diff --git a/gcc/cp/decl2.c b/gcc/cp/decl2.c index 72239ec..a475146 100644 --- a/gcc/cp/decl2.c +++ b/gcc/cp/decl2.c @@ -4145,10 +4145,19 @@ decl_maybe_constant_var_p (tree decl) /* A proxy isn't constant. */ return false; if (TREE_CODE (type) == REFERENCE_TYPE) - /* References can be constant. */ + /* References can be constant. */; + else if (CP_TYPE_CONST_NON_VOLATILE_P (type) + && INTEGRAL_OR_ENUMERATION_TYPE_P (type)) + /* And const integers. */; + else + return false; + + if (DECL_INITIAL (decl) + && !DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (decl)) + /* We know the initializer, and it isn't constant. */ + return false; + else return true; - return (CP_TYPE_CONST_NON_VOLATILE_P (type) - && INTEGRAL_OR_ENUMERATION_TYPE_P (type)); } /* Complain that DECL uses a type with no linkage. In C++98 mode this is diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index e5238ad..69ca929 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -6585,10 +6585,10 @@ convert_nontype_argument (tree type, tree expr, tsubst_flags_t complain) if (complain & tf_error) { int errs = errorcount, warns = warningcount + werrorcount; - if (processing_template_decl - && !require_potential_constant_expression (expr)) - return NULL_TREE; - expr = cxx_constant_value (expr); + if (!require_potential_constant_expression (expr)) + expr = error_mark_node; + else + expr = cxx_constant_value (expr); if (errorcount > errs || warningcount + werrorcount > warns) inform (loc, "in template argument for type %qT ", type); if (expr == error_mark_node) diff --git a/gcc/cp/typeck2.c b/gcc/cp/typeck2.c index 4623d6d..430ba30 100644 --- a/gcc/cp/typeck2.c +++ b/gcc/cp/typeck2.c @@ -821,8 +821,7 @@ store_init_value (tree decl, tree init, vec** cleanups, int flags) || (DECL_IN_AGGR_P (decl) && !DECL_VAR_DECLARED_INLINE_P (decl))) { /* Diagnose a non-constant initializer for constexpr. */ - if (processing_template_decl - && !require_potential_constant_expression (value)) + if (!require_potential_constant_expression (value)) value = error_mark_node; else value = cxx_constant_value (value, decl); diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-diag1.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-diag1.C index 450a0b5..ccb8d81 100644 --- a/gcc/testsuite/g++.dg/cpp0x/constexpr-diag1.C +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-diag1.C @@ -16,5 +16,5 @@ constexpr int i = ai.f(); constexpr int b = A().f(); // { dg-error "" } template -constexpr int f (T t) { return 42; } // { dg-error "parameter" } -constexpr int x = f(B()); // { dg-error "constexpr" } +constexpr int f (T t) { return 42; } +constexpr int x = f(B()); // { dg-error "non-literal" } diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-trivial2.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-trivial2.C index d241114..005f07b 100644 --- a/gcc/testsuite/g++.dg/cpp0x/constexpr-trivial2.C +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-trivial2.C @@ -10,5 +10,5 @@ struct T int main() { - constexpr T t = (T{} = T{}); + constexpr T t = (T{} = T{}); // { dg-error "" "" { target c++11_only } } } diff --git a/gcc/testsuite/g++.dg/ext/stmtexpr19.C b/gcc/testsuite/g++.dg/ext/stmtexpr19.C new file mode 100644 index 0000000..0c19a21 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/stmtexpr19.C @@ -0,0 +1,17 @@ +// PR c++/81073 +// { dg-options "" } +// { dg-do compile { target c++11 } } + +struct test { const int *addr; }; + +const test* setup() +{ + static constexpr test atest = + { + ({ static const int inner = 123; &inner; }) // { dg-error "static" } + }; + + return &atest; +} + +int main(){} -- cgit v1.1 From c72e002cc34657b86bf99ca68f3ba0fdbfc32df6 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Mon, 19 Jun 2017 18:59:00 +0000 Subject: badalloc1.C: Remove code path for -DSTACK_SIZE. * g++.old-deja/g++.eh/badalloc1.C: Remove code path for -DSTACK_SIZE. 2017-06-19 Christophe Lyon * g++.old-deja/g++.eh/badalloc1.C: Remove code path for -DSTACK_SIZE. From-SVN: r249384 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.old-deja/g++.eh/badalloc1.C | 8 -------- 2 files changed, 5 insertions(+), 8 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ecec608..80ebf57 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-19 Christophe Lyon + + * g++.old-deja/g++.eh/badalloc1.C: Remove code path for + -DSTACK_SIZE. + 2017-06-19 Jakub Jelinek PR sanitizer/81125 diff --git a/gcc/testsuite/g++.old-deja/g++.eh/badalloc1.C b/gcc/testsuite/g++.old-deja/g++.eh/badalloc1.C index f63d5c6..b660e84 100644 --- a/gcc/testsuite/g++.old-deja/g++.eh/badalloc1.C +++ b/gcc/testsuite/g++.old-deja/g++.eh/badalloc1.C @@ -3,7 +3,6 @@ // itself call malloc(), and will fail if there is no more // memory available. // { dg-do run { xfail { { xstormy16-*-* *-*-darwin[3-7]* } || vxworks_rtp } } } -// { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } // Copyright (C) 2000, 2002, 2003, 2010, 2012, 2014 Free Software Foundation, Inc. // Contributed by Nathan Sidwell 6 June 2000 @@ -16,12 +15,6 @@ extern "C" void *memcpy(void *, const void *, size_t); // libstdc++ requires a large initialization time allocation for the // emergency EH allocation pool. Add that to the arena size. -// Assume that STACK_SIZE defined implies a system that does not have a -// large data space either, and additionally that we're not linking against -// a shared libstdc++ (which requires quite a bit more initialization space). -#ifdef STACK_SIZE -const int arena_size = 256 + 8 * 128; -#else #if defined(__FreeBSD__) || defined(__sun__) || defined(__hpux__) // FreeBSD, Solaris and HP-UX require even more space at initialization time. // FreeBSD 5 now requires over 131072 bytes. @@ -32,7 +25,6 @@ const int arena_size = 262144 + 72 * 1024; // 32-bit-systems-based estimate. const int arena_size = 32768 * ((sizeof (void *) + 3)/4) + 72 * 1024; #endif -#endif struct object { -- cgit v1.1 From 5ec046c03624e39858314bd35eb0c06f8e63bd28 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Mon, 19 Jun 2017 19:11:31 +0000 Subject: re PR c++/81124 (internal compiler error: in operator*, at cp/cp-tree.h:726) PR c++/81124 PR c++/79766 * name-lookup.c (set_decl_namespace): Don't follow using directives and ignore using decls. Only check overly-explicit scope after discovering decl. * g++.dg/lookup/pr79766.C: New. * g++.dg/lookup/pr81124.C: New. * g++.dg/template/explicit6.C: Adjust. * g++.old-deja/g++.other/decl5.C: Adjust. From-SVN: r249385 --- gcc/cp/ChangeLog | 8 ++ gcc/cp/name-lookup.c | 115 ++++++++++++++------------- gcc/testsuite/ChangeLog | 9 +++ gcc/testsuite/g++.dg/lookup/pr79766.C | 29 +++++++ gcc/testsuite/g++.dg/lookup/pr81124.C | 11 +++ gcc/testsuite/g++.dg/template/explicit6.C | 2 +- gcc/testsuite/g++.old-deja/g++.other/decl5.C | 4 +- 7 files changed, 118 insertions(+), 60 deletions(-) create mode 100644 gcc/testsuite/g++.dg/lookup/pr79766.C create mode 100644 gcc/testsuite/g++.dg/lookup/pr81124.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 55ba486..b80d373 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,11 @@ +2017-06-19 Nathan Sidwell + + PR c++/81124 + PR c++/79766 + * name-lookup.c (set_decl_namespace): Don't follow using + directives and ignore using decls. Only check overly-explicit + scope after discovering decl. + 2017-06-19 Jason Merrill PR c++/81073 - constexpr and static var in statement-expression. diff --git a/gcc/cp/name-lookup.c b/gcc/cp/name-lookup.c index a337942..e91b89c 100644 --- a/gcc/cp/name-lookup.c +++ b/gcc/cp/name-lookup.c @@ -4266,8 +4266,6 @@ set_global_binding (tree name, tree val) void set_decl_namespace (tree decl, tree scope, bool friendp) { - tree old; - /* Get rid of namespace aliases. */ scope = ORIGINAL_NAMESPACE (scope); @@ -4277,41 +4275,49 @@ set_decl_namespace (tree decl, tree scope, bool friendp) decl, scope); DECL_CONTEXT (decl) = FROB_CONTEXT (scope); - /* Writing "int N::i" to declare a variable within "N" is invalid. */ - if (scope == current_namespace) - { - if (at_namespace_scope_p ()) - error ("explicit qualification in declaration of %qD", - decl); - return; - } + /* See whether this has been declared in the namespace or inline + children. */ + tree old = NULL_TREE; + { + name_lookup lookup (DECL_NAME (decl), LOOKUP_HIDDEN); + if (!lookup.search_qualified (scope, /*usings=*/false)) + /* No old declaration at all. */ + goto not_found; + old = lookup.value; + } - /* See whether this has been declared in the namespace. */ - old = lookup_qualified_name (scope, DECL_NAME (decl), /*type*/false, - /*complain*/true, /*hidden*/true); - if (old == error_mark_node) - /* No old declaration at all. */ - goto complain; /* If it's a TREE_LIST, the result of the lookup was ambiguous. */ if (TREE_CODE (old) == TREE_LIST) { + ambiguous: + DECL_CONTEXT (decl) = FROB_CONTEXT (scope); error ("reference to %qD is ambiguous", decl); print_candidates (old); return; } - if (!OVL_P (decl)) + + if (!DECL_DECLARES_FUNCTION_P (decl)) { - /* We might have found OLD in an inline namespace inside SCOPE. */ - if (TREE_CODE (decl) == TREE_CODE (old)) - DECL_CONTEXT (decl) = DECL_CONTEXT (old); /* Don't compare non-function decls with decls_match here, since it can't check for the correct constness at this - point. pushdecl will find those errors later. */ + point. pushdecl will find those errors later. */ + + /* We might have found it in an inline namespace child of SCOPE. */ + if (TREE_CODE (decl) == TREE_CODE (old)) + DECL_CONTEXT (decl) = DECL_CONTEXT (old); + + found: + /* Writing "N::i" to declare something directly in "N" is invalid. */ + if (CP_DECL_CONTEXT (decl) == current_namespace + && at_namespace_scope_p ()) + error ("explicit qualification in declaration of %qD", decl); return; } + /* Since decl is a function, old should contain a function decl. */ if (!OVL_P (old)) - goto complain; + goto not_found; + /* We handle these in check_explicit_instantiation_namespace. */ if (processing_explicit_instantiation) return; @@ -4325,53 +4331,48 @@ set_decl_namespace (tree decl, tree scope, bool friendp) friends in any namespace. */ if (friendp && DECL_USE_TEMPLATE (decl)) return; - if (OVL_P (old)) + + tree found; + found = NULL_TREE; + + for (lkp_iterator iter (old); iter; ++iter) { - tree found = NULL_TREE; + if (iter.using_p ()) + continue; - for (ovl_iterator iter (old); iter; ++iter) - { - tree ofn = *iter; - /* Adjust DECL_CONTEXT first so decls_match will return true - if DECL will match a declaration in an inline namespace. */ - DECL_CONTEXT (decl) = DECL_CONTEXT (ofn); - if (decls_match (decl, ofn)) - { - if (found && !decls_match (found, ofn)) - { - DECL_CONTEXT (decl) = FROB_CONTEXT (scope); - error ("reference to %qD is ambiguous", decl); - print_candidates (old); - return; - } - found = ofn; - } - } - if (found) + tree ofn = *iter; + + /* Adjust DECL_CONTEXT first so decls_match will return true + if DECL will match a declaration in an inline namespace. */ + DECL_CONTEXT (decl) = DECL_CONTEXT (ofn); + if (decls_match (decl, ofn)) { - if (!is_nested_namespace (scope, CP_DECL_CONTEXT (found), true)) - goto complain; - if (DECL_HIDDEN_FRIEND_P (found)) + if (found) { - pedwarn (DECL_SOURCE_LOCATION (decl), 0, - "%qD has not been declared within %qD", decl, scope); - inform (DECL_SOURCE_LOCATION (found), - "only here as a %"); + /* We found more than one matching declaration. */ + DECL_CONTEXT (decl) = FROB_CONTEXT (scope); + goto ambiguous; } - DECL_CONTEXT (decl) = DECL_CONTEXT (found); - return; + found = ofn; } } - else + + if (found) { - DECL_CONTEXT (decl) = DECL_CONTEXT (old); - if (decls_match (decl, old)) - return; + if (DECL_HIDDEN_FRIEND_P (found)) + { + pedwarn (DECL_SOURCE_LOCATION (decl), 0, + "%qD has not been declared within %qD", decl, scope); + inform (DECL_SOURCE_LOCATION (found), + "only here as a %"); + } + DECL_CONTEXT (decl) = DECL_CONTEXT (found); + goto found; } + not_found: /* It didn't work, go back to the explicit scope. */ DECL_CONTEXT (decl) = FROB_CONTEXT (scope); - complain: error ("%qD should have been declared inside %qD", decl, scope); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 80ebf57..3c17355 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2017-06-19 Nathan Sidwell + + PR c++/81124 + PR c++/79766 + * g++.dg/lookup/pr79766.C: New. + * g++.dg/lookup/pr81124.C: New. + * g++.dg/template/explicit6.C: Adjust. + * g++.old-deja/g++.other/decl5.C: Adjust. + 2017-06-19 Christophe Lyon * g++.old-deja/g++.eh/badalloc1.C: Remove code path for diff --git a/gcc/testsuite/g++.dg/lookup/pr79766.C b/gcc/testsuite/g++.dg/lookup/pr79766.C new file mode 100644 index 0000000..de9bbb5 --- /dev/null +++ b/gcc/testsuite/g++.dg/lookup/pr79766.C @@ -0,0 +1,29 @@ +// { dg-do compile { target c++11 } } +// PR 79766 qualified name to find inline namespace is ok + +namespace Y +{ + inline namespace X + { + void Q (); + } +} + +void Y::Q () // OK -> Y::X::Q +{ +} + +inline namespace Z +{ + void R (); +} + +void ::R () // OK -> Z::R +{ +} + +void S (); + +void ::S () // { dg-error "explicit qualification" } +{ +} diff --git a/gcc/testsuite/g++.dg/lookup/pr81124.C b/gcc/testsuite/g++.dg/lookup/pr81124.C new file mode 100644 index 0000000..d80d88a --- /dev/null +++ b/gcc/testsuite/g++.dg/lookup/pr81124.C @@ -0,0 +1,11 @@ +// { dg-do compile { target c++11 } } +// c++/81124 ICE with inline namespace + +namespace std { +inline namespace { +int to_string(); +void to_string(int); +} +void to_string(); +} +int std::to_string(); diff --git a/gcc/testsuite/g++.dg/template/explicit6.C b/gcc/testsuite/g++.dg/template/explicit6.C index a28fd9e..24fa50d 100644 --- a/gcc/testsuite/g++.dg/template/explicit6.C +++ b/gcc/testsuite/g++.dg/template/explicit6.C @@ -5,4 +5,4 @@ // Bug 19895: ICE on invalid struct A; -template A<>::A(); // { dg-error "(not a template)|(explicit qualification)" } +template A<>::A(); // { dg-error "(should have been)|(not a template)" } diff --git a/gcc/testsuite/g++.old-deja/g++.other/decl5.C b/gcc/testsuite/g++.old-deja/g++.other/decl5.C index 9167061..3ac9137 100644 --- a/gcc/testsuite/g++.old-deja/g++.other/decl5.C +++ b/gcc/testsuite/g++.old-deja/g++.other/decl5.C @@ -53,8 +53,8 @@ namespace N { namespace NMS { - void NMS::fn(); // { dg-error "explicit qual" } - int NMS::i; // { dg-error "explicit qual" } + void NMS::fn(); // { dg-error "should have been" } + int NMS::i; // { dg-error "should have been" } struct NMS::D { // { dg-error "does not name a class" } int i; }; -- cgit v1.1 From ecc5761533690734622d57cbe25914c44d7913e1 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Mon, 19 Jun 2017 16:55:21 -0400 Subject: PR c++/80829 - ICE with constexpr copy of base subobject. * constexpr.c (clear_no_implicit_zero): New. (cxx_eval_call_expression): Call it. From-SVN: r249386 --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/constexpr.c | 17 ++++++++++++++++- gcc/testsuite/g++.dg/cpp0x/constexpr-base5.C | 15 +++++++++++++++ 3 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-base5.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index b80d373..ff4280a 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2017-06-19 Jason Merrill + + PR c++/80829 - ICE with constexpr copy of base subobject. + * constexpr.c (clear_no_implicit_zero): New. + (cxx_eval_call_expression): Call it. + 2017-06-19 Nathan Sidwell PR c++/81124 diff --git a/gcc/cp/constexpr.c b/gcc/cp/constexpr.c index 569a247..5a57452 100644 --- a/gcc/cp/constexpr.c +++ b/gcc/cp/constexpr.c @@ -1394,6 +1394,21 @@ cxx_eval_internal_function (const constexpr_ctx *ctx, tree t, return t; } +/* Clean CONSTRUCTOR_NO_IMPLICIT_ZERO from CTOR and its sub-aggregates. */ + +static void +clear_no_implicit_zero (tree ctor) +{ + if (CONSTRUCTOR_NO_IMPLICIT_ZERO (ctor)) + { + CONSTRUCTOR_NO_IMPLICIT_ZERO (ctor) = false; + tree elt; unsigned HOST_WIDE_INT idx; + FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (ctor), idx, elt) + if (TREE_CODE (elt) == CONSTRUCTOR) + clear_no_implicit_zero (elt); + } +} + /* Subroutine of cxx_eval_constant_expression. Evaluate the call expression tree T in the context of OLD_CALL expression evaluation. */ @@ -1697,7 +1712,7 @@ cxx_eval_call_expression (const constexpr_ctx *ctx, tree t, /* The result of a constexpr function must be completely initialized. */ if (TREE_CODE (result) == CONSTRUCTOR) - CONSTRUCTOR_NO_IMPLICIT_ZERO (result) = false; + clear_no_implicit_zero (result); pop_cx_call_context (); return unshare_constructor (result); diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-base5.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-base5.C new file mode 100644 index 0000000..84700bc --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-base5.C @@ -0,0 +1,15 @@ +// PR c++/80829 +// { dg-do compile { target c++11 } } + +struct A { + constexpr A(int a) : _a(a) {} + int _a; +}; + +struct B : public A { + constexpr B(int a) : A(a) {} +}; + +int main() { + constexpr A a = B(10); +} -- cgit v1.1 From 66d052d5cb17463441615988fd2bbbeb292dfd04 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Mon, 19 Jun 2017 16:55:27 -0400 Subject: PR c++/80562 - ICE with constexpr if. * semantics.c (finish_if_stmt_cond): Call instantiate_non_dependent_expr. From-SVN: r249387 --- gcc/cp/ChangeLog | 4 ++++ gcc/cp/semantics.c | 5 ++++- gcc/testsuite/g++.dg/cpp1z/constexpr-if12.C | 14 ++++++++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/cpp1z/constexpr-if12.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index ff4280a..10d1ebd 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,9 @@ 2017-06-19 Jason Merrill + PR c++/80562 - ICE with constexpr if. + * semantics.c (finish_if_stmt_cond): Call + instantiate_non_dependent_expr. + PR c++/80829 - ICE with constexpr copy of base subobject. * constexpr.c (clear_no_implicit_zero): New. (cxx_eval_call_expression): Call it. diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c index 5b5ec54..5fe772a 100644 --- a/gcc/cp/semantics.c +++ b/gcc/cp/semantics.c @@ -733,7 +733,10 @@ finish_if_stmt_cond (tree cond, tree if_stmt) if (IF_STMT_CONSTEXPR_P (if_stmt) && require_potential_rvalue_constant_expression (cond) && !value_dependent_expression_p (cond)) - cond = cxx_constant_value (cond, NULL_TREE); + { + cond = instantiate_non_dependent_expr (cond); + cond = cxx_constant_value (cond, NULL_TREE); + } finish_cond (&IF_COND (if_stmt), cond); add_stmt (if_stmt); THEN_CLAUSE (if_stmt) = push_stmt_list (); diff --git a/gcc/testsuite/g++.dg/cpp1z/constexpr-if12.C b/gcc/testsuite/g++.dg/cpp1z/constexpr-if12.C new file mode 100644 index 0000000..1ed2c30 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1z/constexpr-if12.C @@ -0,0 +1,14 @@ +// PR c++/80562 +// { dg-options -std=c++1z } + +struct T { + constexpr auto foo() { return false; } +}; + +template +constexpr auto bf(T t) { + if constexpr(t.foo()) { + return false; + } + return true; +} -- cgit v1.1 From 62be3709cdf1837a66d789a88199a29f29edb1d0 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Tue, 20 Jun 2017 00:16:31 +0000 Subject: Daily bump. From-SVN: r249394 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index b9d7fd0..30a5315 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170619 +20170620 -- cgit v1.1 From 16122c22dc009696131c250603745b34340b803a Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Tue, 20 Jun 2017 06:26:27 +0000 Subject: re PR target/79799 (Improve vec_insert of float on Power9) [gcc] 2017-06-20 Michael Meissner PR target/79799 * config/rs6000/rs6000.c (rs6000_expand_vector_init): Add support for doing vector set of SFmode on ISA 3.0. * config/rs6000/vsx.md (vsx_set_v4sf_p9): Likewise. (vsx_set_v4sf_p9_zero): Special case setting 0.0f to a V4SF element. (vsx_insert_extract_v4sf_p9): Add an optimization for inserting a SFmode value into a V4SF variable that was extracted from another V4SF variable without converting the element to double precision and back to single precision vector format. (vsx_insert_extract_v4sf_p9_2): Likewise. [gcc/testsuite] 2017-06-20 Michael Meissner PR target/79799 * gcc.target/powerpc/pr79799-1.c: New test. * gcc.target/powerpc/pr79799-2.c: Likewise. * gcc.target/powerpc/pr79799-3.c: Likewise. * gcc.target/powerpc/pr79799-4.c: Likewise. * gcc.target/powerpc/pr79799-5.c: Likewise. From-SVN: r249395 --- gcc/ChangeLog | 14 +++ gcc/config/rs6000/rs6000.c | 2 + gcc/config/rs6000/vsx.md | 128 +++++++++++++++++++++++++++ gcc/testsuite/ChangeLog | 9 ++ gcc/testsuite/gcc.target/powerpc/pr79799-1.c | 43 +++++++++ gcc/testsuite/gcc.target/powerpc/pr79799-2.c | 31 +++++++ gcc/testsuite/gcc.target/powerpc/pr79799-3.c | 24 +++++ gcc/testsuite/gcc.target/powerpc/pr79799-4.c | 105 ++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr79799-5.c | 25 ++++++ 9 files changed, 381 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr79799-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr79799-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr79799-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr79799-4.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr79799-5.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 268abf3..5af9611 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2017-06-20 Michael Meissner + + PR target/79799 + * config/rs6000/rs6000.c (rs6000_expand_vector_init): Add support + for doing vector set of SFmode on ISA 3.0. + * config/rs6000/vsx.md (vsx_set_v4sf_p9): Likewise. + (vsx_set_v4sf_p9_zero): Special case setting 0.0f to a V4SF + element. + (vsx_insert_extract_v4sf_p9): Add an optimization for inserting a + SFmode value into a V4SF variable that was extracted from another + V4SF variable without converting the element to double precision + and back to single precision vector format. + (vsx_insert_extract_v4sf_p9_2): Likewise. + 2017-06-19 Jakub Jelinek * tree-ssa-structalias.c (get_constraint_for_ptr_offset): Multiply diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 14b1778..eee9d0c 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -7451,6 +7451,8 @@ rs6000_expand_vector_set (rtx target, rtx val, int elt) insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx); else if (mode == V16QImode) insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx); + else if (mode == V4SFmode) + insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx); } if (insn) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 7aa6d32..4d73f0a 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3173,6 +3173,134 @@ } [(set_attr "type" "vecperm")]) +(define_insn_and_split "vsx_set_v4sf_p9" + [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa") + (unspec:V4SF + [(match_operand:V4SF 1 "gpc_reg_operand" "0") + (match_operand:SF 2 "gpc_reg_operand" "ww") + (match_operand:QI 3 "const_0_to_3_operand" "n")] + UNSPEC_VSX_SET)) + (clobber (match_scratch:SI 4 "=&wJwK"))] + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER + && TARGET_UPPER_REGS_DI && TARGET_POWERPC64" + "#" + "&& reload_completed" + [(set (match_dup 5) + (unspec:V4SF [(match_dup 2)] + UNSPEC_VSX_CVDPSPN)) + (parallel [(set (match_dup 4) + (vec_select:SI (match_dup 6) + (parallel [(match_dup 7)]))) + (clobber (scratch:SI))]) + (set (match_dup 8) + (unspec:V4SI [(match_dup 8) + (match_dup 4) + (match_dup 3)] + UNSPEC_VSX_SET))] +{ + unsigned int tmp_regno = reg_or_subregno (operands[4]); + + operands[5] = gen_rtx_REG (V4SFmode, tmp_regno); + operands[6] = gen_rtx_REG (V4SImode, tmp_regno); + operands[7] = GEN_INT (VECTOR_ELT_ORDER_BIG ? 1 : 2); + operands[8] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0])); +} + [(set_attr "type" "vecperm") + (set_attr "length" "12")]) + +;; Special case setting 0.0f to a V4SF element +(define_insn_and_split "*vsx_set_v4sf_p9_zero" + [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa") + (unspec:V4SF + [(match_operand:V4SF 1 "gpc_reg_operand" "0") + (match_operand:SF 2 "zero_fp_constant" "j") + (match_operand:QI 3 "const_0_to_3_operand" "n")] + UNSPEC_VSX_SET)) + (clobber (match_scratch:SI 4 "=&wJwK"))] + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER + && TARGET_UPPER_REGS_DI && TARGET_POWERPC64" + "#" + "&& reload_completed" + [(set (match_dup 4) + (const_int 0)) + (set (match_dup 5) + (unspec:V4SI [(match_dup 5) + (match_dup 4) + (match_dup 3)] + UNSPEC_VSX_SET))] +{ + operands[5] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0])); +} + [(set_attr "type" "vecperm") + (set_attr "length" "8")]) + +;; Optimize x = vec_insert (vec_extract (v2, n), v1, m) if n is the element +;; that is in the default scalar position (1 for big endian, 2 for little +;; endian). We just need to do an xxinsertw since the element is in the +;; correct location. + +(define_insn "*vsx_insert_extract_v4sf_p9" + [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa") + (unspec:V4SF + [(match_operand:V4SF 1 "gpc_reg_operand" "0") + (vec_select:SF (match_operand:V4SF 2 "gpc_reg_operand" "wa") + (parallel + [(match_operand:QI 3 "const_0_to_3_operand" "n")])) + (match_operand:QI 4 "const_0_to_3_operand" "n")] + UNSPEC_VSX_SET))] + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER + && TARGET_UPPER_REGS_DI && TARGET_POWERPC64 + && (INTVAL (operands[3]) == (VECTOR_ELT_ORDER_BIG ? 1 : 2))" +{ + int ele = INTVAL (operands[4]); + + if (!VECTOR_ELT_ORDER_BIG) + ele = GET_MODE_NUNITS (V4SFmode) - 1 - ele; + + operands[4] = GEN_INT (GET_MODE_SIZE (SFmode) * ele); + return "xxinsertw %x0,%x2,%4"; +} + [(set_attr "type" "vecperm")]) + +;; Optimize x = vec_insert (vec_extract (v2, n), v1, m) if n is not the element +;; that is in the default scalar position (1 for big endian, 2 for little +;; endian). Convert the insert/extract to int and avoid doing the conversion. + +(define_insn_and_split "*vsx_insert_extract_v4sf_p9_2" + [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa") + (unspec:V4SF + [(match_operand:V4SF 1 "gpc_reg_operand" "0") + (vec_select:SF (match_operand:V4SF 2 "gpc_reg_operand" "wa") + (parallel + [(match_operand:QI 3 "const_0_to_3_operand" "n")])) + (match_operand:QI 4 "const_0_to_3_operand" "n")] + UNSPEC_VSX_SET)) + (clobber (match_scratch:SI 5 "=&wJwK"))] + "VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode) + && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER + && TARGET_UPPER_REGS_DI && TARGET_POWERPC64 + && (INTVAL (operands[3]) != (VECTOR_ELT_ORDER_BIG ? 1 : 2))" + "#" + "&& 1" + [(parallel [(set (match_dup 5) + (vec_select:SI (match_dup 6) + (parallel [(match_dup 3)]))) + (clobber (scratch:SI))]) + (set (match_dup 7) + (unspec:V4SI [(match_dup 8) + (match_dup 5) + (match_dup 4)] + UNSPEC_VSX_SET))] +{ + if (GET_CODE (operands[5]) == SCRATCH) + operands[5] = gen_reg_rtx (SImode); + + operands[6] = gen_lowpart (V4SImode, operands[2]); + operands[7] = gen_lowpart (V4SImode, operands[0]); + operands[8] = gen_lowpart (V4SImode, operands[1]); +} + [(set_attr "type" "vecperm")]) + ;; Expanders for builtins (define_expand "vsx_mergel_" [(use (match_operand:VSX_D 0 "vsx_register_operand" "")) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3c17355..0809b2c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2017-06-20 Michael Meissner + + PR target/79799 + * gcc.target/powerpc/pr79799-1.c: New test. + * gcc.target/powerpc/pr79799-2.c: Likewise. + * gcc.target/powerpc/pr79799-3.c: Likewise. + * gcc.target/powerpc/pr79799-4.c: Likewise. + * gcc.target/powerpc/pr79799-5.c: Likewise. + 2017-06-19 Nathan Sidwell PR c++/81124 diff --git a/gcc/testsuite/gcc.target/powerpc/pr79799-1.c b/gcc/testsuite/gcc.target/powerpc/pr79799-1.c new file mode 100644 index 0000000..87a9e49 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr79799-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +#include + +/* GCC 7.1 did not have a specialized method for inserting 32-bit floating + point on ISA 3.0 (power9) systems. */ + +vector float +insert_arg_0 (vector float vf, float f) +{ + return vec_insert (f, vf, 0); +} + +vector float +insert_arg_1 (vector float vf, float f) +{ + return vec_insert (f, vf, 1); +} + +vector float +insert_arg_2 (vector float vf, float f) +{ + return vec_insert (f, vf, 2); +} + +vector float +insert_arg_3 (vector float vf, float f) +{ + return vec_insert (f, vf, 3); +} + +/* { dg-final { scan-assembler {\mxscvdpspn\M} } } */ +/* { dg-final { scan-assembler {\mxxinsertw\M} } } */ +/* { dg-final { scan-assembler-not {\mlvewx\M} } } */ +/* { dg-final { scan-assembler-not {\mlvx\M} } } */ +/* { dg-final { scan-assembler-not {\mvperm\M} } } */ +/* { dg-final { scan-assembler-not {\mvpermr\M} } } */ +/* { dg-final { scan-assembler-not {\mstfs\M} } } */ +/* { dg-final { scan-assembler-not {\mstxssp\M} } } */ +/* { dg-final { scan-assembler-not {\mstxsspx\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr79799-2.c b/gcc/testsuite/gcc.target/powerpc/pr79799-2.c new file mode 100644 index 0000000..793e3b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr79799-2.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +#include + +/* Optimize x = vec_insert (vec_extract (v2, N), v1, M) for SFmode if N is the default + scalar position. */ + +#if __ORDER_LITTLE_ENDIAN__ +#define ELE 2 +#else +#define ELE 1 +#endif + +vector float +foo (vector float v1, vector float v2) +{ + return vec_insert (vec_extract (v2, ELE), v1, 0); +} + +/* { dg-final { scan-assembler {\mxxinsertw\M} } } */ +/* { dg-final { scan-assembler-not {\mxxextractuw\M} } } */ +/* { dg-final { scan-assembler-not {\mlvewx\M} } } */ +/* { dg-final { scan-assembler-not {\mlvx\M} } } */ +/* { dg-final { scan-assembler-not {\mvperm\M} } } */ +/* { dg-final { scan-assembler-not {\mvpermr\M} } } */ +/* { dg-final { scan-assembler-not {\mstfs\M} } } */ +/* { dg-final { scan-assembler-not {\mstxssp\M} } } */ +/* { dg-final { scan-assembler-not {\mstxsspx\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr79799-3.c b/gcc/testsuite/gcc.target/powerpc/pr79799-3.c new file mode 100644 index 0000000..7255042 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr79799-3.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +#include + +/* Optimize x = vec_insert (vec_extract (v2, N), v1, M) for SFmode. */ + +vector float +foo (vector float v1, vector float v2) +{ + return vec_insert (vec_extract (v2, 4), v1, 0); +} + +/* { dg-final { scan-assembler {\mxxinsertw\M} } } */ +/* { dg-final { scan-assembler {\mxxextractuw\M} } } */ +/* { dg-final { scan-assembler-not {\mlvewx\M} } } */ +/* { dg-final { scan-assembler-not {\mlvx\M} } } */ +/* { dg-final { scan-assembler-not {\mvperm\M} } } */ +/* { dg-final { scan-assembler-not {\mvpermr\M} } } */ +/* { dg-final { scan-assembler-not {\mstfs\M} } } */ +/* { dg-final { scan-assembler-not {\mstxssp\M} } } */ +/* { dg-final { scan-assembler-not {\mstxsspx\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr79799-4.c b/gcc/testsuite/gcc.target/powerpc/pr79799-4.c new file mode 100644 index 0000000..056a005 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr79799-4.c @@ -0,0 +1,105 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-require-effective-target vsx_hw } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target p9vector_hw } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +#include +#include + +__attribute__ ((__noinline__)) +vector float +insert_0 (vector float v, float f) +{ + return vec_insert (f, v, 0); +} + +__attribute__ ((__noinline__)) +vector float +insert_1 (vector float v, float f) +{ + return vec_insert (f, v, 1); +} + +__attribute__ ((__noinline__)) +vector float +insert_2 (vector float v, float f) +{ + return vec_insert (f, v, 2); +} + +__attribute__ ((__noinline__)) +vector float +insert_3 (vector float v, float f) +{ + return vec_insert (f, v, 3); +} + +__attribute__ ((__noinline__)) +void +test_insert (void) +{ + vector float v1 = { 1.0f, 2.0f, 3.0f, 4.0f }; + vector float v2 = { 5.0f, 6.0f, 7.0f, 8.0f }; + + v1 = insert_0 (v1, 5.0f); + v1 = insert_1 (v1, 6.0f); + v1 = insert_2 (v1, 7.0f); + v1 = insert_3 (v1, 8.0f); + + if (vec_any_ne (v1, v2)) + abort (); +} + +__attribute__ ((__noinline__)) +vector float +insert_extract_0_3 (vector float v1, vector float v2) +{ + return vec_insert (vec_extract (v2, 3), v1, 0); +} + +__attribute__ ((__noinline__)) +vector float +insert_extract_1_2 (vector float v1, vector float v2) +{ + return vec_insert (vec_extract (v2, 2), v1, 1); +} + +__attribute__ ((__noinline__)) +vector float +insert_extract_2_1 (vector float v1, vector float v2) +{ + return vec_insert (vec_extract (v2, 1), v1, 2); +} + +__attribute__ ((__noinline__)) +vector float +insert_extract_3_0 (vector float v1, vector float v2) +{ + return vec_insert (vec_extract (v2, 0), v1, 3); +} + +__attribute__ ((__noinline__)) +void +test_insert_extract (void) +{ + vector float v1 = { 1.0f, 2.0f, 3.0f, 4.0f }; + vector float v2 = { 5.0f, 6.0f, 7.0f, 8.0f }; + vector float v3 = { 8.0f, 7.0f, 6.0f, 5.0f }; + + v1 = insert_extract_0_3 (v1, v2); + v1 = insert_extract_1_2 (v1, v2); + v1 = insert_extract_2_1 (v1, v2); + v1 = insert_extract_3_0 (v1, v2); + + if (vec_any_ne (v1, v3)) + abort (); +} + +int +main (void) +{ + test_insert (); + test_insert_extract (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr79799-5.c b/gcc/testsuite/gcc.target/powerpc/pr79799-5.c new file mode 100644 index 0000000..fcd92ff --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr79799-5.c @@ -0,0 +1,25 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +#include + +/* Insure setting 0.0f to a V4SFmode element does not do a FP conversion. */ + +vector float +insert_arg_0 (vector float vf) +{ + return vec_insert (0.0f, vf, 0); +} + +/* { dg-final { scan-assembler {\mxxinsertw\M} } } */ +/* { dg-final { scan-assembler-not {\mlvewx\M} } } */ +/* { dg-final { scan-assembler-not {\mlvx\M} } } */ +/* { dg-final { scan-assembler-not {\mvperm\M} } } */ +/* { dg-final { scan-assembler-not {\mvpermr\M} } } */ +/* { dg-final { scan-assembler-not {\mstfs\M} } } */ +/* { dg-final { scan-assembler-not {\mstxssp\M} } } */ +/* { dg-final { scan-assembler-not {\mstxsspx\M} } } */ +/* { dg-final { scan-assembler-not {\mxscvdpspn\M} } } */ +/* { dg-final { scan-assembler-not {\mxxextractuw\M} } } */ -- cgit v1.1 From a1aa2599dd85d590f39dbe565cc213c8dab65cae Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 20 Jun 2017 09:04:27 +0200 Subject: re PR target/81121 (ICE: in extract_insn, at recog.c:2311) PR target/81121 * config/i386/i386.md (TARGET_USE_VECTOR_CONVERTS float si->{sf,df} splitter): Require TARGET_SSE2 in the condition. * gcc.target/i386/pr81121.c: New test. From-SVN: r249396 --- gcc/ChangeLog | 6 ++++++ gcc/config/i386/i386.md | 3 ++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/i386/pr81121.c | 10 ++++++++++ 4 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr81121.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5af9611..06e0cec 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-20 Jakub Jelinek + + PR target/81121 + * config/i386/i386.md (TARGET_USE_VECTOR_CONVERTS float si->{sf,df} + splitter): Require TARGET_SSE2 in the condition. + 2017-06-20 Michael Meissner PR target/79799 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index adc13a9..40a20d0 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -5290,7 +5290,8 @@ (define_split [(set (match_operand:MODEF 0 "sse_reg_operand") (float:MODEF (match_operand:SI 1 "nonimmediate_operand")))] - "TARGET_USE_VECTOR_CONVERTS + "TARGET_SSE2 + && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0809b2c..330a108 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-20 Jakub Jelinek + + PR target/81121 + * gcc.target/i386/pr81121.c: New test. + 2017-06-20 Michael Meissner PR target/79799 diff --git a/gcc/testsuite/gcc.target/i386/pr81121.c b/gcc/testsuite/gcc.target/i386/pr81121.c new file mode 100644 index 0000000..aca74e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr81121.c @@ -0,0 +1,10 @@ +/* PR target/81121 */ +/* { dg-do compile } */ +/* { dg-options "-O0 -march=amdfam10 -mno-sse2" } */ + +void +foo (short *x, short *y) +{ + float a = 0; + y[0] = x[0] * a; +} -- cgit v1.1 From cb6794f6312a07b2d044677e0adb0667e860197d Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 20 Jun 2017 09:10:14 +0200 Subject: re PR sanitizer/81125 (-fsanitize=undefined ICE) PR sanitizer/81125 * ubsan.h (ubsan_encode_value): Workaround buggy clang++ parser by removing enum keyword. (ubsan_type_descriptor): Likewise. Formatting fix. From-SVN: r249397 --- gcc/ChangeLog | 5 +++++ gcc/ubsan.h | 5 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 06e0cec..331e1a4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-20 Jakub Jelinek + PR sanitizer/81125 + * ubsan.h (ubsan_encode_value): Workaround buggy clang++ parser + by removing enum keyword. + (ubsan_type_descriptor): Likewise. Formatting fix. + PR target/81121 * config/i386/i386.md (TARGET_USE_VECTOR_CONVERTS float si->{sf,df} splitter): Require TARGET_SSE2 in the condition. diff --git a/gcc/ubsan.h b/gcc/ubsan.h index 6593423..8d990b6 100644 --- a/gcc/ubsan.h +++ b/gcc/ubsan.h @@ -55,8 +55,9 @@ extern bool ubsan_expand_objsize_ifn (gimple_stmt_iterator *); extern bool ubsan_expand_vptr_ifn (gimple_stmt_iterator *); extern bool ubsan_instrument_unreachable (gimple_stmt_iterator *); extern tree ubsan_create_data (const char *, int, const location_t *, ...); -extern tree ubsan_type_descriptor (tree, enum ubsan_print_style = UBSAN_PRINT_NORMAL); -extern tree ubsan_encode_value (tree, enum ubsan_encode_value_phase +extern tree ubsan_type_descriptor (tree, ubsan_print_style + = UBSAN_PRINT_NORMAL); +extern tree ubsan_encode_value (tree, ubsan_encode_value_phase = UBSAN_ENCODE_VALUE_GENERIC); extern bool is_ubsan_builtin_p (tree); extern tree ubsan_build_overflow_builtin (tree_code, location_t, tree, tree, -- cgit v1.1 From 0e36bb52a85446a759c7f7131048db1ca3236eb7 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 20 Jun 2017 09:22:31 +0200 Subject: tree-chkp.c (chkp_get_hard_register_var_fake_base_address): Rewritten to avoid overflow for > 32-bit pointers. * tree-chkp.c (chkp_get_hard_register_var_fake_base_address): Rewritten to avoid overflow for > 32-bit pointers. From-SVN: r249398 --- gcc/ChangeLog | 5 ++++- gcc/tree-chkp.c | 5 ++--- 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 331e1a4..d46daf3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,7 @@ -2017-06-20 Jakub Jelinek +2017-07-20 Jakub Jelinek + + * tree-chkp.c (chkp_get_hard_register_var_fake_base_address): + Rewritten to avoid overflow for > 32-bit pointers. PR sanitizer/81125 * ubsan.h (ubsan_encode_value): Workaround buggy clang++ parser diff --git a/gcc/tree-chkp.c b/gcc/tree-chkp.c index ecac901..e241f50 100644 --- a/gcc/tree-chkp.c +++ b/gcc/tree-chkp.c @@ -690,9 +690,8 @@ chkp_erase_completed_bounds (void) static tree chkp_get_hard_register_var_fake_base_address () { - tree base = fold_convert (ptr_type_node, integer_zero_node); - unsigned HOST_WIDE_INT offset = 1 << (TYPE_PRECISION (ptr_type_node) - 1); - return fold_build_pointer_plus_hwi (base, offset); + int prec = TYPE_PRECISION (ptr_type_node); + return wide_int_to_tree (ptr_type_node, wi::min_value (prec, SIGNED)); } /* If we check bounds for a hard register variable, we cannot -- cgit v1.1 From b5c7b957ae0548c3c00c2ac07a0d9fa2c597d72d Mon Sep 17 00:00:00 2001 From: Thomas Preud'homme Date: Tue, 20 Jun 2017 09:25:08 +0000 Subject: [ARM] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature macro 2017-06-20 Prakhar Bahuguna gcc/ * config/arm/arm-c.c (arm_cpu_builtins): New block to define __ARM_FEATURE_COPROC according to support. gcc/testsuite/ * gcc.target/arm/acle/cdp.c: Add feature macro bitmap test. * gcc.target/arm/acle/cdp2.c: Likewise. * gcc.target/arm/acle/ldc.c: Likewise. * gcc.target/arm/acle/ldc2.c: Likewise. * gcc.target/arm/acle/ldc2l.c: Likewise. * gcc.target/arm/acle/ldcl.c: Likewise. * gcc.target/arm/acle/mcr.c: Likewise. * gcc.target/arm/acle/mcr2.c: Likewise. * gcc.target/arm/acle/mcrr.c: Likewise. * gcc.target/arm/acle/mcrr2.c: Likewise. * gcc.target/arm/acle/mrc.c: Likewise. * gcc.target/arm/acle/mrc2.c: Likewise. * gcc.target/arm/acle/mrrc.c: Likewise. * gcc.target/arm/acle/mrrc2.c: Likewise. * gcc.target/arm/acle/stc.c: Likewise. * gcc.target/arm/acle/stc2.c: Likewise. * gcc.target/arm/acle/stc2l.c: Likewise. * gcc.target/arm/acle/stcl.c: Likewise. From-SVN: r249399 --- gcc/ChangeLog | 7 ++++++- gcc/config/arm/arm-c.c | 16 ++++++++++++++++ gcc/testsuite/ChangeLog | 21 +++++++++++++++++++++ gcc/testsuite/gcc.target/arm/acle/cdp.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/cdp2.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/ldc.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/ldc2.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/ldc2l.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/ldcl.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/mcr.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/mcr2.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/mcrr.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/mcrr2.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/mrc.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/mrc2.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/mrrc.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/mrrc2.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/stc.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/stc2.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/stc2l.c | 3 +++ gcc/testsuite/gcc.target/arm/acle/stcl.c | 3 +++ 21 files changed, 97 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d46daf3..10434ed 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,9 @@ -2017-07-20 Jakub Jelinek +2017-06-20 Prakhar Bahuguna + + * config/arm/arm-c.c (arm_cpu_builtins): New block to define + __ARM_FEATURE_COPROC according to support. + +2017-06-20 Jakub Jelinek * tree-chkp.c (chkp_get_hard_register_var_fake_base_address): Rewritten to avoid overflow for > 32-bit pointers. diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 3abe7d1..a3daa32 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -200,6 +200,22 @@ arm_cpu_builtins (struct cpp_reader* pfile) def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV); def_or_undef_macro (pfile, "__ARM_ASM_SYNTAX_UNIFIED__", inline_asm_unified); + + if (TARGET_32BIT && arm_arch4 && !(arm_arch8 && arm_arch_notm)) + { + int coproc_level = 0x1; + + if (arm_arch5) + coproc_level |= 0x2; + if (arm_arch5e) + coproc_level |= 0x4; + if (arm_arch6) + coproc_level |= 0x8; + + builtin_define_with_int_value ("__ARM_FEATURE_COPROC", coproc_level); + } + else + cpp_undef (pfile, "__ARM_FEATURE_COPROC"); } void diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 330a108..dccdaf4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,24 @@ +2017-06-20 Prakhar Bahuguna + + * gcc.target/arm/acle/cdp.c: Add feature macro bitmap test. + * gcc.target/arm/acle/cdp2.c: Likewise. + * gcc.target/arm/acle/ldc.c: Likewise. + * gcc.target/arm/acle/ldc2.c: Likewise. + * gcc.target/arm/acle/ldc2l.c: Likewise. + * gcc.target/arm/acle/ldcl.c: Likewise. + * gcc.target/arm/acle/mcr.c: Likewise. + * gcc.target/arm/acle/mcr2.c: Likewise. + * gcc.target/arm/acle/mcrr.c: Likewise. + * gcc.target/arm/acle/mcrr2.c: Likewise. + * gcc.target/arm/acle/mrc.c: Likewise. + * gcc.target/arm/acle/mrc2.c: Likewise. + * gcc.target/arm/acle/mrrc.c: Likewise. + * gcc.target/arm/acle/mrrc2.c: Likewise. + * gcc.target/arm/acle/stc.c: Likewise. + * gcc.target/arm/acle/stc2.c: Likewise. + * gcc.target/arm/acle/stc2l.c: Likewise. + * gcc.target/arm/acle/stcl.c: Likewise. + 2017-06-20 Jakub Jelinek PR target/81121 diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp.c b/gcc/testsuite/gcc.target/arm/acle/cdp.c index 28b218e..cebd8c4 100644 --- a/gcc/testsuite/gcc.target/arm/acle/cdp.c +++ b/gcc/testsuite/gcc.target/arm/acle/cdp.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_cdp (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp2.c b/gcc/testsuite/gcc.target/arm/acle/cdp2.c index 00bcd50..945d435 100644 --- a/gcc/testsuite/gcc.target/arm/acle/cdp2.c +++ b/gcc/testsuite/gcc.target/arm/acle/cdp2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_cdp2 (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc.c b/gcc/testsuite/gcc.target/arm/acle/ldc.c index f45f25d..cd57343 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldc.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldc.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2.c b/gcc/testsuite/gcc.target/arm/acle/ldc2.c index 433bf8a..d7691e3 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldc2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c index 88c8aa4..9ee63af 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/ldcl.c b/gcc/testsuite/gcc.target/arm/acle/ldcl.c index 72a97f1..a6bfd90 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldcl.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldcl.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/mcr.c b/gcc/testsuite/gcc.target/arm/acle/mcr.c index 93f977a..7095dcb 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcr.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcr.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_mcr (uint32_t a) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mcr2.c b/gcc/testsuite/gcc.target/arm/acle/mcr2.c index 5b60d10..2a4b0ce 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcr2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcr2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_mcr2 (uint32_t a) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr.c b/gcc/testsuite/gcc.target/arm/acle/mcrr.c index dcc223c..bcfbe1a 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcrr.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcrr.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc3_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x4) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_mcrr (uint64_t a) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c index 10f2014..afd07e6 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc4_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x8) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif void test_mcrr2 (uint64_t a) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mrc.c b/gcc/testsuite/gcc.target/arm/acle/mrc.c index 34ca6a1..809b6c9 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrc.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrc.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif uint32_t test_mrc (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrc2.c index 3b72a40..4c06ea3 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrc2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif uint32_t test_mrc2 (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc.c b/gcc/testsuite/gcc.target/arm/acle/mrrc.c index 28c3b8e..802de08 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrrc.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrrc.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc3_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x4) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif uint64_t test_mrrc (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c index 5b7aab0..adf3956 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc4_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x8) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif uint64_t test_mrrc2 (void) { diff --git a/gcc/testsuite/gcc.target/arm/acle/stc.c b/gcc/testsuite/gcc.target/arm/acle/stc.c index 7c6e04f..2714f65 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stc.c +++ b/gcc/testsuite/gcc.target/arm/acle/stc.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/stc2.c b/gcc/testsuite/gcc.target/arm/acle/stc2.c index 1578f7b..0a84652 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/stc2.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/stc2l.c b/gcc/testsuite/gcc.target/arm/acle/stc2l.c index 7adbd60..2453d04 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stc2l.c +++ b/gcc/testsuite/gcc.target/arm/acle/stc2l.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x2) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; diff --git a/gcc/testsuite/gcc.target/arm/acle/stcl.c b/gcc/testsuite/gcc.target/arm/acle/stcl.c index 2fd5edd..affdaa2 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stcl.c +++ b/gcc/testsuite/gcc.target/arm/acle/stcl.c @@ -5,6 +5,9 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" +#if (__ARM_FEATURE_COPROC & 0x1) == 0 + #error "__ARM_FEATURE_COPROC does not have correct feature bits set" +#endif extern void * p; -- cgit v1.1 From d47d743898d2af37ff24bbc6c5b78fb77020bcef Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Tue, 20 Jun 2017 09:53:29 +0000 Subject: pr65947-9.c: Adjust. 2017-06-20 Richard Biener * gcc.dg/vect/pr65947-9.c: Adjust. From-SVN: r249400 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/vect/pr65947-9.c | 17 ++++++++++------- 2 files changed, 14 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dccdaf4..9077fe1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-20 Richard Biener + + * gcc.dg/vect/pr65947-9.c: Adjust. + 2017-06-20 Prakhar Bahuguna * gcc.target/arm/acle/cdp.c: Add feature macro bitmap test. diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-9.c b/gcc/testsuite/gcc.dg/vect/pr65947-9.c index d5a76e9..a43560b 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-9.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-9.c @@ -9,10 +9,10 @@ extern void abort (void) __attribute__ ((noreturn)); /* Condition reduction with maximum possible loop size. Will fail to vectorize because the vectorisation requires a slot for default values. */ -char +signed char __attribute__((noinline,noclone)) condition_reduction (char *a, char min_v) { - char last = -72; + signed char last = -72; for (int i = 0; i < N; i++) if (a[i] < min_v) @@ -21,10 +21,10 @@ condition_reduction (char *a, char min_v) return last; } -char -main (void) +int +main () { - char a[N] = { + signed char a[N] = { 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, @@ -34,11 +34,14 @@ main (void) check_vect (); - char ret = condition_reduction (a, 16); - + signed char ret = condition_reduction (a, 16); if (ret != 10) abort (); + ret = condition_reduction (a, 1); + if (ret != -72) + abort (); + return 0; } -- cgit v1.1 From ad2f2a35d33ea79f95b70f8d96ee1445fabed402 Mon Sep 17 00:00:00 2001 From: Andreas Schwab Date: Tue, 20 Jun 2017 10:15:47 +0000 Subject: re PR target/80970 (internal compiler error in find_reloads, at reload.c:4077) PR target/80970 * config/m68k/m68k.md (bsetdreg, bchgdreg, bclrdreg): Use "=d" instead of "+d". From-SVN: r249401 --- gcc/ChangeLog | 6 ++++++ gcc/config/m68k/m68k.md | 6 +++--- gcc/testsuite/gcc.dg/torture/pr80970.c | 13 +++++++++++++ 3 files changed, 22 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/torture/pr80970.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 10434ed..7cb99a6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-20 Andreas Schwab + + PR target/80970 + * config/m68k/m68k.md (bsetdreg, bchgdreg, bclrdreg): Use "=d" + instead of "+d". + 2017-06-20 Prakhar Bahuguna * config/arm/arm-c.c (arm_cpu_builtins): New block to define diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 5bf6c92..7933f8e 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -5337,7 +5337,7 @@ [(set_attr "type" "bitrw")]) (define_insn "*bsetdreg" - [(set (match_operand:SI 0 "register_operand" "+d") + [(set (match_operand:SI 0 "register_operand" "=d") (ior:SI (ashift:SI (const_int 1) (and:SI (match_operand:SI 1 "register_operand" "d") (const_int 31))) @@ -5350,7 +5350,7 @@ [(set_attr "type" "bitrw")]) (define_insn "*bchgdreg" - [(set (match_operand:SI 0 "register_operand" "+d") + [(set (match_operand:SI 0 "register_operand" "=d") (xor:SI (ashift:SI (const_int 1) (and:SI (match_operand:SI 1 "register_operand" "d") (const_int 31))) @@ -5363,7 +5363,7 @@ [(set_attr "type" "bitrw")]) (define_insn "*bclrdreg" - [(set (match_operand:SI 0 "register_operand" "+d") + [(set (match_operand:SI 0 "register_operand" "=d") (and:SI (rotate:SI (const_int -2) (and:SI (match_operand:SI 1 "register_operand" "d") (const_int 31))) diff --git a/gcc/testsuite/gcc.dg/torture/pr80970.c b/gcc/testsuite/gcc.dg/torture/pr80970.c new file mode 100644 index 0000000..3b96b58 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr80970.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ + +int a, b, c, d, e; +void f () +{ + long g, h; + if (c) + e = d; + g = d & 31; + h = 1 << g; + a = e | h; + b = a; +} -- cgit v1.1 From c7a980b80b3a46ad24940269f6b85a75cdb94a60 Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Tue, 20 Jun 2017 10:40:38 +0000 Subject: Prevent fix-it hints from affecting more than one line Attempts to apply a removal or replacement fix-it hint to a source range that covers multiple lines currently lead to nonsensical results from the printing code in diagnostic-show-locus.c. We were already filtering them out in edit-context.c (leading to -fdiagnostics-generate-patch not generating any output for the whole TU). Reject attempts to add such fix-it hints within rich_location, fixing the diagnostic-show-locus.c issue. gcc/ChangeLog: * diagnostic-show-locus.c (selftest::test_fixit_deletion_affecting_newline): New function. (selftest::diagnostic_show_locus_c_tests): Call it. libcpp/ChangeLog: * include/line-map.h (class rich_location): Document that attempts to delete or replace a range *affecting* multiple lines will fail. * line-map.c (rich_location::maybe_add_fixit): Implement this restriction. From-SVN: r249403 --- gcc/ChangeLog | 6 ++++++ gcc/diagnostic-show-locus.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7cb99a6..4293a05 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-20 David Malcolm + + * diagnostic-show-locus.c + (selftest::test_fixit_deletion_affecting_newline): New function. + (selftest::diagnostic_show_locus_c_tests): Call it. + 2017-06-20 Andreas Schwab PR target/80970 diff --git a/gcc/diagnostic-show-locus.c b/gcc/diagnostic-show-locus.c index f410a32..8bf4d9e 100644 --- a/gcc/diagnostic-show-locus.c +++ b/gcc/diagnostic-show-locus.c @@ -2793,6 +2793,53 @@ test_fixit_replace_containing_newline (const line_table_case &case_) pp_formatted_text (dc.printer)); } +/* Fix-it hint, attempting to delete a newline. + This will fail, as we currently only support fix-it hints that + affect one line at a time. */ + +static void +test_fixit_deletion_affecting_newline (const line_table_case &case_) +{ + /* Create a tempfile and write some text to it. + ..........................0000000001111. + ..........................1234567890123. */ + const char *old_content = ("foo = bar (\n" + " );\n"); + + temp_source_file tmp (SELFTEST_LOCATION, ".c", old_content); + line_table_test ltt (case_); + const line_map_ordinary *ord_map = linemap_check_ordinary + (linemap_add (line_table, LC_ENTER, false, tmp.get_filename (), 0)); + linemap_line_start (line_table, 1, 100); + + /* Attempt to delete the " (\n...)". */ + location_t start + = linemap_position_for_line_and_column (line_table, ord_map, 1, 10); + location_t caret + = linemap_position_for_line_and_column (line_table, ord_map, 1, 11); + location_t finish + = linemap_position_for_line_and_column (line_table, ord_map, 2, 7); + location_t loc = make_location (caret, start, finish); + rich_location richloc (line_table, loc); + richloc. add_fixit_remove (); + + /* Fix-it hints that affect more than one line are not yet supported, so + the fix-it should not be displayed. */ + ASSERT_TRUE (richloc.seen_impossible_fixit_p ()); + + if (finish > LINE_MAP_MAX_LOCATION_WITH_COLS) + return; + + test_diagnostic_context dc; + diagnostic_show_locus (&dc, &richloc, DK_ERROR); + ASSERT_STREQ ("\n" + " foo = bar (\n" + " ~^\n" + " );\n" + " ~ \n", + pp_formatted_text (dc.printer)); +} + /* Run all of the selftests within this file. */ void @@ -2813,6 +2860,7 @@ diagnostic_show_locus_c_tests () for_each_line_table_case (test_fixit_insert_containing_newline); for_each_line_table_case (test_fixit_insert_containing_newline_2); for_each_line_table_case (test_fixit_replace_containing_newline); + for_each_line_table_case (test_fixit_deletion_affecting_newline); } } // namespace selftest -- cgit v1.1 From 531f0b3879b09b53d738b5bf84790c49bdd60977 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Tue, 20 Jun 2017 12:46:46 +0000 Subject: re PR sanitizer/81097 (UBSAN: false positive for not existing negation operator and a bogus message) 2017-06-20 Richard Biener PR middle-end/81097 * fold-const.c (split_tree): Fold to type before negating. * c-c++-common/ubsan/pr81097.c: New testcase. From-SVN: r249407 --- gcc/ChangeLog | 5 +++++ gcc/fold-const.c | 6 +++--- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/c-c++-common/ubsan/pr81097.c | 12 ++++++++++++ 4 files changed, 25 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/ubsan/pr81097.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4293a05..8210d27 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-20 Richard Biener + + PR middle-end/81097 + * fold-const.c (split_tree): Fold to type before negating. + 2017-06-20 David Malcolm * diagnostic-show-locus.c diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 8559b1d..379a30e 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -853,9 +853,9 @@ split_tree (location_t loc, tree in, tree type, enum tree_code code, && code == PLUS_EXPR) { /* -X - 1 is folded to ~X, undo that here. Do _not_ do this - when IN is constant. */ - *minus_litp = build_one_cst (TREE_TYPE (in)); - var = negate_expr (TREE_OPERAND (in, 0)); + when IN is constant. Convert to TYPE before negating. */ + *minus_litp = build_one_cst (type); + var = negate_expr (fold_convert_loc (loc, type, TREE_OPERAND (in, 0))); } else var = in; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9077fe1..28c97de 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2017-06-20 Richard Biener + PR middle-end/81097 + * c-c++-common/ubsan/pr81097.c: New testcase. + +2017-06-20 Richard Biener + * gcc.dg/vect/pr65947-9.c: Adjust. 2017-06-20 Prakhar Bahuguna diff --git a/gcc/testsuite/c-c++-common/ubsan/pr81097.c b/gcc/testsuite/c-c++-common/ubsan/pr81097.c new file mode 100644 index 0000000..cd323ea --- /dev/null +++ b/gcc/testsuite/c-c++-common/ubsan/pr81097.c @@ -0,0 +1,12 @@ +/* { dg-do run } */ +/* { dg-options "-fsanitize=undefined -fsanitize-undefined-trap-on-error" } */ + +unsigned int a = 3309568; +unsigned int b = -1204857327; +short c = -10871; +short x; +int main() +{ + x = ((short)(~a) | ~c) + ((short)(~b) | ~c); + return 0; +} -- cgit v1.1 From 71bbbd133f65c26f65709037401154362210560e Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Tue, 20 Jun 2017 12:53:11 +0000 Subject: PR c++/67074 - namespace aliases PR c++/67074 - namespace aliases * decl.c (duplicate_decls): Don't error here on mismatched namespace alias. * name-lookup.c (name_lookup::add_value): Matching namespaces are not ambiguous. (diagnose_name_conflict): Namespaces are never redeclarations. (update_binding): An alias can match a real namespace. PR c++/67074 * g++.dg/lookup/pr67074.C: New. * g++.dg/parse/namespace-alias-1.C: Adjust. From-SVN: r249408 --- gcc/cp/ChangeLog | 10 +++++++++ gcc/cp/decl.c | 14 +++---------- gcc/cp/name-lookup.c | 29 +++++++++++++++----------- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/g++.dg/lookup/pr67074.C | 18 ++++++++++++++++ gcc/testsuite/g++.dg/parse/namespace-alias-1.C | 2 +- 6 files changed, 55 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/g++.dg/lookup/pr67074.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 10d1ebd..3ed58b2 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,13 @@ +2017-06-20 Nathan Sidwell + + PR c++/67074 - namespace aliases + * decl.c (duplicate_decls): Don't error here on mismatched + namespace alias. + * name-lookup.c (name_lookup::add_value): Matching namespaces are + not ambiguous. + (diagnose_name_conflict): Namespaces are never redeclarations. + (update_binding): An alias can match a real namespace. + 2017-06-19 Jason Merrill PR c++/80562 - ICE with constexpr if. diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index 16cd2a5..bb7c56f 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -1751,17 +1751,9 @@ duplicate_decls (tree newdecl, tree olddecl, bool newdecl_is_friend) && (DECL_NAMESPACE_ALIAS (newdecl) == DECL_NAMESPACE_ALIAS (olddecl))) return olddecl; - /* [namespace.alias] - - A namespace-name or namespace-alias shall not be declared as - the name of any other entity in the same declarative region. - A namespace-name defined at global scope shall not be - declared as the name of any other entity in any global scope - of the program. */ - error ("conflicting declaration of namespace %q+D", newdecl); - inform (DECL_SOURCE_LOCATION (olddecl), - "previous declaration of namespace %qD here", olddecl); - return error_mark_node; + + /* Leave it to update_binding to merge or report error. */ + return NULL_TREE; } else { diff --git a/gcc/cp/name-lookup.c b/gcc/cp/name-lookup.c index e91b89c..54c9d7b 100644 --- a/gcc/cp/name-lookup.c +++ b/gcc/cp/name-lookup.c @@ -450,7 +450,13 @@ name_lookup::add_value (tree new_val) else if ((TREE_CODE (value) == TYPE_DECL && TREE_CODE (new_val) == TYPE_DECL && same_type_p (TREE_TYPE (value), TREE_TYPE (new_val)))) - ; + /* Typedefs to the same type. */; + else if (TREE_CODE (value) == NAMESPACE_DECL + && TREE_CODE (new_val) == NAMESPACE_DECL + && ORIGINAL_NAMESPACE (value) == ORIGINAL_NAMESPACE (new_val)) + /* Namespace (possibly aliased) to the same namespace. Locate + the namespace*/ + value = ORIGINAL_NAMESPACE (value); else { if (deduping) @@ -1630,10 +1636,10 @@ static void diagnose_name_conflict (tree decl, tree bval) { if (TREE_CODE (decl) == TREE_CODE (bval) - && (TREE_CODE (decl) != TYPE_DECL - || (DECL_ARTIFICIAL (decl) && DECL_ARTIFICIAL (bval)) - || (!DECL_ARTIFICIAL (decl) && !DECL_ARTIFICIAL (bval))) + && TREE_CODE (decl) != NAMESPACE_DECL && !DECL_DECLARES_FUNCTION_P (decl) + && (TREE_CODE (decl) != TYPE_DECL + || DECL_ARTIFICIAL (decl) == DECL_ARTIFICIAL (bval)) && CP_DECL_CONTEXT (decl) == CP_DECL_CONTEXT (bval)) error ("redeclaration of %q#D", decl); else @@ -1809,15 +1815,14 @@ update_binding (cp_binding_level *level, cxx_binding *binding, tree *slot, } else if (TREE_CODE (old) == NAMESPACE_DECL) { - if (DECL_NAMESPACE_ALIAS (old) && DECL_NAMESPACE_ALIAS (decl) - && ORIGINAL_NAMESPACE (old) == ORIGINAL_NAMESPACE (decl)) - /* In a declarative region, a namespace-alias-definition can be - used to redefine a namespace-alias declared in that declarative - region to refer only to the namespace to which it already - refers. [namespace.alias] */ - return old; - else + /* Two maybe-aliased namespaces. If they're to the same target + namespace, that's ok. */ + if (ORIGINAL_NAMESPACE (old) != ORIGINAL_NAMESPACE (decl)) goto conflict; + + /* The new one must be an alias at this point. */ + gcc_assert (DECL_NAMESPACE_ALIAS (decl)); + return old; } else if (TREE_CODE (old) == VAR_DECL) { diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 28c97de..ee1a4e2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-06-20 Nathan Sidwell + + PR c++/67074 + * g++.dg/lookup/pr67074.C: New. + * g++.dg/parse/namespace-alias-1.C: Adjust. + 2017-06-20 Richard Biener PR middle-end/81097 diff --git a/gcc/testsuite/g++.dg/lookup/pr67074.C b/gcc/testsuite/g++.dg/lookup/pr67074.C new file mode 100644 index 0000000..ce31ede --- /dev/null +++ b/gcc/testsuite/g++.dg/lookup/pr67074.C @@ -0,0 +1,18 @@ +// PR c++/67074 namespace aliases to the same place. + +namespace P { + namespace X { + static int i = 1; + } +} +namespace Q { + namespace X = P::X; +} + +using namespace P; +using namespace Q; + +void Frob () { X::i; } + +namespace N {} +namespace N = N; diff --git a/gcc/testsuite/g++.dg/parse/namespace-alias-1.C b/gcc/testsuite/g++.dg/parse/namespace-alias-1.C index 5986ab6..220d5f9 100644 --- a/gcc/testsuite/g++.dg/parse/namespace-alias-1.C +++ b/gcc/testsuite/g++.dg/parse/namespace-alias-1.C @@ -3,7 +3,7 @@ namespace N { namespace M = N; // { dg-message "previous declaration" } - namespace M {} // { dg-error "declaration of namespace" } + namespace M {} // { dg-error "conflicts with a previous declaration" } } namespace A -- cgit v1.1 From 67ea3f4e0fd389f4f2097c5fe3faa40f18c69d30 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Tue, 20 Jun 2017 13:01:32 +0000 Subject: Always check for target i?86 and x86_64 libstdc++-v3: * testsuite/20_util/variant/index_type.cc: Allow for all ilp32 and lp64 targets. gcc/testsuite: * c-c++-common/fold-masked-cmp-1.c: Allow for i?86-*-* target. * c-c++-common/fold-masked-cmp-2.c: Likewise. * c-c++-common/fold-masked-cmp-3.c: Likewise. * g++.dg/cpp0x/alignas4.C: Allow for i?86-*-* target, don't restrict to x86_64-*-*-gnu. Skip scan-assembler on *-*-darwin*. * g++.dg/vect/pr70944.cc: Allow for i?86-*-* target. * gcc.dg/loop-invariant.c: Likewise. * gcc.dg/lto/pr70955_0.c: Likewise. * gcc.dg/tree-ssa/pr69196-1.c: Likewise. * gcc.dg/tree-ssa/pr79803.c: Likewise. * gfortran.dg/pr68078.f90: Allow for i?86-*-linux*. * g++.dg/debug/dwarf2/const2b.C: Allow for x86_64-*-* target. * gcc.dg/attr-ms_struct-1.c: Allow for all i?86-*-*, x86_64-*-* targets. * gcc.dg/attr-ms_struct-2.c: Likewise. * gcc.dg/attr-ms_struct-packed1.c: Likewise. * gcc.dg/bf-ms-layout.c: Likewise. * gcc.dg/bf-ms-layout-2.c: Likewise. * gcc.dg/pic-macro-define.c: Remove target restrictions. Require fpic support. * gcc.target/i386/bitfield1.c: Allow for all i?86-*-*, x86_64-*-* targets. * gcc.target/i386/bitfield2.c: Likewise. * gcc.target/i386/darwin-fpmath.c: Allow for x86_64-*-darwin* targets. * gfortran.dg/fmt_pf.f90: Remove i?86-*-solaris2.9* from xfail. From-SVN: r249409 --- gcc/testsuite/ChangeLog | 31 ++++++++++++++++++++++++++ gcc/testsuite/c-c++-common/fold-masked-cmp-1.c | 2 +- gcc/testsuite/c-c++-common/fold-masked-cmp-2.c | 2 +- gcc/testsuite/c-c++-common/fold-masked-cmp-3.c | 2 +- gcc/testsuite/g++.dg/cpp0x/alignas4.C | 2 +- gcc/testsuite/g++.dg/debug/dwarf2/const2b.C | 2 +- gcc/testsuite/g++.dg/vect/pr70944.cc | 2 +- gcc/testsuite/gcc.dg/attr-ms_struct-1.c | 2 +- gcc/testsuite/gcc.dg/attr-ms_struct-2.c | 2 +- gcc/testsuite/gcc.dg/attr-ms_struct-packed1.c | 2 +- gcc/testsuite/gcc.dg/bf-ms-layout-2.c | 2 +- gcc/testsuite/gcc.dg/bf-ms-layout.c | 2 +- gcc/testsuite/gcc.dg/loop-invariant.c | 2 +- gcc/testsuite/gcc.dg/lto/pr70955_0.c | 4 ++-- gcc/testsuite/gcc.dg/pic-macro-define.c | 3 ++- gcc/testsuite/gcc.dg/tree-ssa/pr69196-1.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/pr79803.c | 2 +- gcc/testsuite/gcc.target/i386/bitfield1.c | 2 +- gcc/testsuite/gcc.target/i386/bitfield2.c | 2 +- gcc/testsuite/gcc.target/i386/darwin-fpmath.c | 2 +- gcc/testsuite/gfortran.dg/fmt_pf.f90 | 2 +- gcc/testsuite/gfortran.dg/pr68078.f90 | 2 +- 22 files changed, 54 insertions(+), 22 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ee1a4e2..e22ebf5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,34 @@ +2017-06-20 Rainer Orth + + * c-c++-common/fold-masked-cmp-1.c: Allow for i?86-*-* target. + * c-c++-common/fold-masked-cmp-2.c: Likewise. + * c-c++-common/fold-masked-cmp-3.c: Likewise. + * g++.dg/cpp0x/alignas4.C: Allow for i?86-*-* target, don't + restrict to x86_64-*-*-gnu. + Skip scan-assembler on *-*-darwin*. + * g++.dg/vect/pr70944.cc: Allow for i?86-*-* target. + * gcc.dg/loop-invariant.c: Likewise. + * gcc.dg/lto/pr70955_0.c: Likewise. + * gcc.dg/tree-ssa/pr69196-1.c: Likewise. + * gcc.dg/tree-ssa/pr79803.c: Likewise. + * gfortran.dg/pr68078.f90: Allow for i?86-*-linux*. + + * g++.dg/debug/dwarf2/const2b.C: Allow for x86_64-*-* target. + * gcc.dg/attr-ms_struct-1.c: Allow for all i?86-*-*, x86_64-*-* + targets. + * gcc.dg/attr-ms_struct-2.c: Likewise. + * gcc.dg/attr-ms_struct-packed1.c: Likewise. + * gcc.dg/bf-ms-layout.c: Likewise. + * gcc.dg/bf-ms-layout-2.c: Likewise. + * gcc.dg/pic-macro-define.c: Remove target restrictions. + Require fpic support. + * gcc.target/i386/bitfield1.c: Allow for all i?86-*-*, x86_64-*-* + targets. + * gcc.target/i386/bitfield2.c: Likewise. + * gcc.target/i386/darwin-fpmath.c: Allow for x86_64-*-darwin* + targets. + * gfortran.dg/fmt_pf.f90: Remove i?86-*-solaris2.9* from xfail. + 2017-06-20 Nathan Sidwell PR c++/67074 diff --git a/gcc/testsuite/c-c++-common/fold-masked-cmp-1.c b/gcc/testsuite/c-c++-common/fold-masked-cmp-1.c index a0e9083..c56adc4 100644 --- a/gcc/testsuite/c-c++-common/fold-masked-cmp-1.c +++ b/gcc/testsuite/c-c++-common/fold-masked-cmp-1.c @@ -1,6 +1,6 @@ /* Based on PR 67328 */ -/* { dg-do compile { target x86_64-*-* } } */ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ /* { dg-options "-O2" } */ enum output_type diff --git a/gcc/testsuite/c-c++-common/fold-masked-cmp-2.c b/gcc/testsuite/c-c++-common/fold-masked-cmp-2.c index 13d068a..a14bceb 100644 --- a/gcc/testsuite/c-c++-common/fold-masked-cmp-2.c +++ b/gcc/testsuite/c-c++-common/fold-masked-cmp-2.c @@ -1,6 +1,6 @@ /* Based on PR 67328 */ -/* { dg-do compile { target x86_64-*-* } } */ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ /* { dg-options "-O2" } */ enum output_type diff --git a/gcc/testsuite/c-c++-common/fold-masked-cmp-3.c b/gcc/testsuite/c-c++-common/fold-masked-cmp-3.c index 98900ec3..5531c35 100644 --- a/gcc/testsuite/c-c++-common/fold-masked-cmp-3.c +++ b/gcc/testsuite/c-c++-common/fold-masked-cmp-3.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target x86_64-*-* } } */ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ /* { dg-options "-fdump-tree-original" } */ void foo (int *p, int x) diff --git a/gcc/testsuite/g++.dg/cpp0x/alignas4.C b/gcc/testsuite/g++.dg/cpp0x/alignas4.C index 871aaef..baa56eb 100644 --- a/gcc/testsuite/g++.dg/cpp0x/alignas4.C +++ b/gcc/testsuite/g++.dg/cpp0x/alignas4.C @@ -1,6 +1,6 @@ // PR c++/59012 // { dg-do compile { target c++11 } } -// { dg-final { scan-assembler "align 8" { target x86_64-*-*-gnu } } } +// { dg-final { scan-assembler "align 8" { target { { i?86-*-* x86_64-*-* } && { ! *-*-darwin* } } } } } template struct A diff --git a/gcc/testsuite/g++.dg/debug/dwarf2/const2b.C b/gcc/testsuite/g++.dg/debug/dwarf2/const2b.C index 81360c2..3ad1c08 100644 --- a/gcc/testsuite/g++.dg/debug/dwarf2/const2b.C +++ b/gcc/testsuite/g++.dg/debug/dwarf2/const2b.C @@ -1,4 +1,4 @@ -/* { dg-do compile { target i386*-*-* } } */ +/* { dg-do compile { target i386*-*-* x86_64-*-* } } */ /* { dg-options "-O -gdwarf-2 -dA -msse" } */ /* { dg-require-effective-target sse } */ /* { dg-final { scan-assembler "DW_AT_const_value" } } */ diff --git a/gcc/testsuite/g++.dg/vect/pr70944.cc b/gcc/testsuite/g++.dg/vect/pr70944.cc index f8973aa..3c9e3ce 100644 --- a/gcc/testsuite/g++.dg/vect/pr70944.cc +++ b/gcc/testsuite/g++.dg/vect/pr70944.cc @@ -1,4 +1,4 @@ -/* { dg-do compile { target x86_64-*-* } } */ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ /* { dg-additional-options "-O3 -march=core-avx2" } */ unsigned *a; diff --git a/gcc/testsuite/gcc.dg/attr-ms_struct-1.c b/gcc/testsuite/gcc.dg/attr-ms_struct-1.c index 0b1d040..1e6cca5 100644 --- a/gcc/testsuite/gcc.dg/attr-ms_struct-1.c +++ b/gcc/testsuite/gcc.dg/attr-ms_struct-1.c @@ -1,5 +1,5 @@ /* Test for MS structure sizes. */ -/* { dg-do run { target *-*-mingw* *-*-cygwin* i?86-*-darwin* } } */ +/* { dg-do run { target i?86-*-* x86_64-*-* } } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-std=gnu99" } */ diff --git a/gcc/testsuite/gcc.dg/attr-ms_struct-2.c b/gcc/testsuite/gcc.dg/attr-ms_struct-2.c index f2534b5..4ebf06b 100644 --- a/gcc/testsuite/gcc.dg/attr-ms_struct-2.c +++ b/gcc/testsuite/gcc.dg/attr-ms_struct-2.c @@ -1,5 +1,5 @@ /* Test for MS structure sizes. */ -/* { dg-do run { target *-*-mingw* *-*-cygwin* i?86-*-darwin* } } */ +/* { dg-do run { target i?86-*-* x86_64-*-* } } */ /* { dg-require-effective-target ilp32 } */ /* { dg-options "-std=gnu99" } */ diff --git a/gcc/testsuite/gcc.dg/attr-ms_struct-packed1.c b/gcc/testsuite/gcc.dg/attr-ms_struct-packed1.c index 25388d2..cc26e6e 100644 --- a/gcc/testsuite/gcc.dg/attr-ms_struct-packed1.c +++ b/gcc/testsuite/gcc.dg/attr-ms_struct-packed1.c @@ -1,5 +1,5 @@ /* Test for MS structure with packed attribute. */ -/* { dg-do run { target *-*-mingw* *-*-cygwin* i?86-*-darwin* } } +/* { dg-do run { target i?86-*-* x86_64-*-* } } /* { dg-options "-std=gnu99" } */ extern void abort (); diff --git a/gcc/testsuite/gcc.dg/bf-ms-layout-2.c b/gcc/testsuite/gcc.dg/bf-ms-layout-2.c index 53a55e6..2d0215f 100644 --- a/gcc/testsuite/gcc.dg/bf-ms-layout-2.c +++ b/gcc/testsuite/gcc.dg/bf-ms-layout-2.c @@ -5,7 +5,7 @@ posted to GCC-patches http://gcc.gnu.org/ml/gcc-patches/2000-08/msg00577.html */ -/* { dg-do run { target *-*-mingw* *-*-cygwin* i?86-*-darwin* } } */ +/* { dg-do run { target i?86-*-* x86_64-*-* } } */ /* { dg-options "-D_TEST_MS_LAYOUT" } */ /* This test uses the attribute instead of the command line option. */ diff --git a/gcc/testsuite/gcc.dg/bf-ms-layout.c b/gcc/testsuite/gcc.dg/bf-ms-layout.c index 54909d8..92af912 100644 --- a/gcc/testsuite/gcc.dg/bf-ms-layout.c +++ b/gcc/testsuite/gcc.dg/bf-ms-layout.c @@ -5,7 +5,7 @@ posted to GCC-patches http://gcc.gnu.org/ml/gcc-patches/2000-08/msg00577.html */ -/* { dg-do run { target *-*-mingw* *-*-cygwin* i?86-*-darwin* } } */ +/* { dg-do run { target i?86-*-* x86_64-*-* } } */ /* { dg-options "-mms-bitfields -D_TEST_MS_LAYOUT" } */ #include diff --git a/gcc/testsuite/gcc.dg/loop-invariant.c b/gcc/testsuite/gcc.dg/loop-invariant.c index fe66bb9..702050b 100644 --- a/gcc/testsuite/gcc.dg/loop-invariant.c +++ b/gcc/testsuite/gcc.dg/loop-invariant.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target x86_64-*-* } } */ +/* { dg-do compile { target i?86-*-* x86_64-*-* } } */ /* { dg-options "-O2 -fdump-rtl-loop2_invariant" } */ /* NOTE: The target list above could be extended to other targets that have conditional moves, but don't have zero registers. */ diff --git a/gcc/testsuite/gcc.dg/lto/pr70955_0.c b/gcc/testsuite/gcc.dg/lto/pr70955_0.c index c3b75fc..52d000a 100644 --- a/gcc/testsuite/gcc.dg/lto/pr70955_0.c +++ b/gcc/testsuite/gcc.dg/lto/pr70955_0.c @@ -1,5 +1,5 @@ -/* __builtin_ms_va_list is only supported for x86_64 -m64. */ -/* { dg-skip-if "" { ! {x86_64-*-* && { ! ilp32 } } } } */ +/* __builtin_ms_va_list is only supported for x86 -m64. */ +/* { dg-skip-if "" { ! { { i?86-*-* x86_64-*-* } && { ! ilp32 } } } } */ #include diff --git a/gcc/testsuite/gcc.dg/pic-macro-define.c b/gcc/testsuite/gcc.dg/pic-macro-define.c index 7bda6fe..0923432 100644 --- a/gcc/testsuite/gcc.dg/pic-macro-define.c +++ b/gcc/testsuite/gcc.dg/pic-macro-define.c @@ -1,4 +1,5 @@ -/* { dg-do run { target "i?86-*-*-darwin" powerpc*-*-darwin* } } */ +/* { dg-do run } */ +/* { dg-require-effective-target fpic } */ /* { dg-options "-fPIC" } */ #if defined __PIC__ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr69196-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr69196-1.c index 5f92447..960491f 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr69196-1.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr69196-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target sparc*-*-* x86_64-*-* } } */ +/* { dg-do compile { target sparc*-*-* i?86-*-* x86_64-*-* } } */ /* { dg-options "-O2 -fdump-tree-thread1-details -fdisable-tree-ethread" } */ /* { dg-final { scan-tree-dump "FSM did not thread around loop and would copy too many statements" "thread1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr79803.c b/gcc/testsuite/gcc.dg/tree-ssa/pr79803.c index 51b245d..3b475fa 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr79803.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr79803.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { x86_64-*-* } } } */ +/* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */ /* { dg-options "-march=opteron-sse3 -Ofast --param l1-cache-line-size=3 -Wdisabled-optimization" } */ /* { dg-require-effective-target indirect_jumps } */ diff --git a/gcc/testsuite/gcc.target/i386/bitfield1.c b/gcc/testsuite/gcc.target/i386/bitfield1.c index e4e06cb..714792c 100644 --- a/gcc/testsuite/gcc.target/i386/bitfield1.c +++ b/gcc/testsuite/gcc.target/i386/bitfield1.c @@ -2,7 +2,7 @@ // { dg-do run } // { dg-require-effective-target ia32 } // { dg-options "-O2" } -// { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-cygwin* i?86-*-mingw*} } +// { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-* x86_64-*-* } } extern void abort (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/bitfield2.c b/gcc/testsuite/gcc.target/i386/bitfield2.c index db9d284..5784bf0 100644 --- a/gcc/testsuite/gcc.target/i386/bitfield2.c +++ b/gcc/testsuite/gcc.target/i386/bitfield2.c @@ -2,7 +2,7 @@ // { dg-do run } // { dg-require-effective-target ia32 } // { dg-options "-O2" } -// { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-cygwin* i?86-*-mingw* } } +// { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-* x86_64-*-* } } extern void abort (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.target/i386/darwin-fpmath.c b/gcc/testsuite/gcc.target/i386/darwin-fpmath.c index 7db6946..693bdee 100644 --- a/gcc/testsuite/gcc.target/i386/darwin-fpmath.c +++ b/gcc/testsuite/gcc.target/i386/darwin-fpmath.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target i?86-*-darwin* } } */ +/* { dg-do compile { target i?86-*-darwin* x86_64-*-darwin* } } */ /* { dg-final { scan-assembler "addsd" } } */ /* Do not add -msse or -msse2 or -mfpmath=sse to the options. GCC is supposed to use SSE math on Darwin by default, and libm won't work diff --git a/gcc/testsuite/gfortran.dg/fmt_pf.f90 b/gcc/testsuite/gfortran.dg/fmt_pf.f90 index 6cefa86..743fcbf 100644 --- a/gcc/testsuite/gfortran.dg/fmt_pf.f90 +++ b/gcc/testsuite/gfortran.dg/fmt_pf.f90 @@ -223,4 +223,4 @@ contains end subroutine end program -! { dg-output "All kinds rounded to nearest" { xfail { i?86-*-solaris2.9* hppa*-*-hpux* } } } +! { dg-output "All kinds rounded to nearest" { xfail { hppa*-*-hpux* } } } diff --git a/gcc/testsuite/gfortran.dg/pr68078.f90 b/gcc/testsuite/gfortran.dg/pr68078.f90 index 092ab29..ebe26d5 100644 --- a/gcc/testsuite/gfortran.dg/pr68078.f90 +++ b/gcc/testsuite/gfortran.dg/pr68078.f90 @@ -1,4 +1,4 @@ -! { dg-do run { target x86_64-*-linux* } } +! { dg-do run { target i?86-*-linux* x86_64-*-linux* } } ! { dg-additional-sources set_vm_limit.c } ! ! This test calls set_vm_limit to set an artificially low address space -- cgit v1.1 From 27b9e8dc8448519b68522a7ec3ec2e40f8941516 Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Tue, 20 Jun 2017 13:31:38 +0000 Subject: [Patch AArch64 obvious] Rearrange the processors in aarch64-cores.def gcc/ * config/aarch64/aarch64-cores.def: Rearrange to sort by architecture, then by implementer ID. * config/aarch64/aarch64-tune.md: Regenerate. From-SVN: r249410 --- gcc/ChangeLog | 6 ++++++ gcc/config/aarch64/aarch64-cores.def | 24 +++++++++++++----------- gcc/config/aarch64/aarch64-tune.md | 2 +- 3 files changed, 20 insertions(+), 12 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8210d27..22d5b21 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-20 James Greenhalgh + + * config/aarch64/aarch64-cores.def: Rearrange to sort by + architecture, then by implementer ID. + * config/aarch64/aarch64-tune.md: Regenerate. + 2017-06-20 Richard Biener PR middle-end/81097 diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 92b57cf..e333d5f 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -43,7 +43,7 @@ VARIANT is the variant of the CPU. In a GNU/Linux system it can found in /proc/cpuinfo. If this is -1, this means it can match any variant. */ -/* V8 Architecture Processors. */ +/* ARMv8-A Architecture Processors. */ /* ARM ('A') cores. */ AARCH64_CORE("cortex-a35", cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, 0x41, 0xd04, -1) @@ -52,13 +52,6 @@ AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AA AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, 0x41, 0xd08, -1) AARCH64_CORE("cortex-a73", cortexa73, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, 0xd09, -1) -/* Samsung ('S') cores. */ -AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001, -1) - -/* Qualcomm ('Q') cores. */ -AARCH64_CORE("falkor", falkor, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00, -1) -AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00, -1) - /* Cavium ('C') cores. */ AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a0, -1) /* Do not swap around "thunderxt88p1" and "thunderxt88", @@ -67,18 +60,27 @@ AARCH64_CORE("thunderxt88p1", thunderxt88p1, thunderx, 8A, AARCH64_FL_FOR_ARCH AARCH64_CORE("thunderxt88", thunderxt88, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a1, -1) AARCH64_CORE("thunderxt81", thunderxt81, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a2, -1) AARCH64_CORE("thunderxt83", thunderxt83, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a3, -1) -AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x43, 0x0af, -1) /* APM ('P') cores. */ AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, 0x50, 0x000, -1) -/* V8.1 Architecture Processors. */ +/* Qualcomm ('Q') cores. */ +AARCH64_CORE("falkor", falkor, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00, -1) +AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00, -1) + +/* Samsung ('S') cores. */ +AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001, -1) + +/* ARMv8.1-A Architecture Processors. */ /* Broadcom ('B') cores. */ AARCH64_CORE("thunderx2t99p1", thunderx2t99p1, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x42, 0x516, -1) AARCH64_CORE("vulcan", vulcan, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x42, 0x516, -1) -/* V8 big.LITTLE implementations. */ +/* Cavium ('C') cores. */ +AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x43, 0x0af, -1) + +/* ARMv8-A big.LITTLE implementations. */ AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1) AARCH64_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, 0x41, AARCH64_BIG_LITTLE (0xd08, 0xd03), -1) diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index c948846..4209f67 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,falkor,qdf24xx,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,thunderx2t99,xgene1,thunderx2t99p1,vulcan,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53" + "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) -- cgit v1.1 From 849ef9cac713286574a7627c85e0e0c4d191f884 Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Tue, 20 Jun 2017 13:36:46 +0000 Subject: [Patch AArch64 obvious] Fix expected string for fp16 extensions gcc/ * config/aarch64/aarch64-option-extensions.def (fp16): Fix expected feature string. From-SVN: r249411 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64-option-extensions.def | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 22d5b21..0b6694d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-20 James Greenhalgh + * config/aarch64/aarch64-option-extensions.def (fp16): Fix expected + feature string. + +2017-06-20 James Greenhalgh + * config/aarch64/aarch64-cores.def: Rearrange to sort by architecture, then by implementer ID. * config/aarch64/aarch64-tune.md: Regenerate. diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 36766d9..b54de03 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -58,6 +58,6 @@ AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, "atomics") /* Enabling "fp16" also enables "fp". Disabling "fp16" just disables "fp16". */ -AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, 0, "fp16") +AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, 0, "fphp asimdhp") #undef AARCH64_OPT_EXTENSION -- cgit v1.1 From 78295effade0997e7e5d9a7851711d05a9ba7cc8 Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Tue, 20 Jun 2017 14:49:13 +0000 Subject: [Patch AArch64] Add rcpc extension gcc/ * config/aarch64/aarch64-option-extensions.def (rcpc): New. * config/aarch64/aarch64.h (AARCH64_FL_RCPC): New. From-SVN: r249414 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64-option-extensions.def | 3 +++ gcc/config/aarch64/aarch64.h | 1 + 3 files changed, 9 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0b6694d..b28620a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-20 James Greenhalgh + * config/aarch64/aarch64-option-extensions.def (rcpc): New. + * config/aarch64/aarch64.h (AARCH64_FL_RCPC): New. + +2017-06-20 James Greenhalgh + * config/aarch64/aarch64-option-extensions.def (fp16): Fix expected feature string. diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index b54de03..c0752ce 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -60,4 +60,7 @@ AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, "atomics") Disabling "fp16" just disables "fp16". */ AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, 0, "fphp asimdhp") +/* Enabling or disabling "rcpc" only changes "rcpc". */ +AARCH64_OPT_EXTENSION("rcpc", AARCH64_FL_RCPC, 0, 0, "lrcpc") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index e4fb96f..3b3f27e 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -140,6 +140,7 @@ extern unsigned aarch64_architecture_version; #define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */ /* ARMv8.3-A architecture extensions. */ #define AARCH64_FL_V8_3 (1 << 10) /* Has ARMv8.3-A features. */ +#define AARCH64_FL_RCPC (1 << 11) /* Has support for RCpc model. */ /* Has FP and SIMD. */ #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) -- cgit v1.1 From 1e5d2102752fbb804c68773d2afeaccebbc9d771 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Tue, 20 Jun 2017 16:27:55 +0000 Subject: cp-tree.h (CPTI_NELTS_IDENTIFIER): Delete. * cp-tree.h (CPTI_NELTS_IDENTIFIER): Delete. (nelts_identifier): Delete. * decl.c (initialize_predefined_identifiers): Remove nelts. From-SVN: r249419 --- gcc/cp/ChangeLog | 4 ++++ gcc/cp/cp-tree.h | 2 -- gcc/cp/decl.c | 1 - 3 files changed, 4 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 3ed58b2..5786cba 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,5 +1,9 @@ 2017-06-20 Nathan Sidwell + * cp-tree.h (CPTI_NELTS_IDENTIFIER): Delete. + (nelts_identifier): Delete. + * decl.c (initialize_predefined_identifiers): Remove nelts. + PR c++/67074 - namespace aliases * decl.c (duplicate_decls): Don't error here on mismatched namespace alias. diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index e33bda6..6b27745 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -136,7 +136,6 @@ enum cp_tree_index CPTI_DELTA_IDENTIFIER, CPTI_IN_CHARGE_IDENTIFIER, CPTI_VTT_PARM_IDENTIFIER, - CPTI_NELTS_IDENTIFIER, CPTI_THIS_IDENTIFIER, CPTI_PFN_IDENTIFIER, CPTI_VPTR_IDENTIFIER, @@ -234,7 +233,6 @@ extern GTY(()) tree cp_global_trees[CPTI_MAX]; /* The name of the parameter that contains a pointer to the VTT to use for this subobject constructor or destructor. */ #define vtt_parm_identifier cp_global_trees[CPTI_VTT_PARM_IDENTIFIER] -#define nelts_identifier cp_global_trees[CPTI_NELTS_IDENTIFIER] #define this_identifier cp_global_trees[CPTI_THIS_IDENTIFIER] #define pfn_identifier cp_global_trees[CPTI_PFN_IDENTIFIER] #define vptr_identifier cp_global_trees[CPTI_VPTR_IDENTIFIER] diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index bb7c56f..7c34489 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -3982,7 +3982,6 @@ initialize_predefined_identifiers (void) { "__base_dtor ", &base_dtor_identifier, 1 }, { "__deleting_dtor ", &deleting_dtor_identifier, 1 }, { IN_CHARGE_NAME, &in_charge_identifier, 0 }, - { "nelts", &nelts_identifier, 0 }, { THIS_NAME, &this_identifier, 0 }, { VTABLE_DELTA_NAME, &delta_identifier, 0 }, { VTABLE_PFN_NAME, &pfn_identifier, 0 }, -- cgit v1.1 From d276da0cf5bff87311330b395d3918b569bbbcc3 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Tue, 20 Jun 2017 12:47:17 -0400 Subject: PR c++/80972 - C++17 ICE with attribute packed. * call.c (build_over_call): Allow a TARGET_EXPR from reference binding. From-SVN: r249420 --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/call.c | 2 ++ gcc/testsuite/g++.dg/ext/packed12.C | 6 ++++++ 3 files changed, 14 insertions(+) create mode 100644 gcc/testsuite/g++.dg/ext/packed12.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 5786cba..01230c0 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2017-06-20 Jason Merrill + + PR c++/80972 - C++17 ICE with attribute packed. + * call.c (build_over_call): Allow a TARGET_EXPR from reference + binding. + 2017-06-20 Nathan Sidwell * cp-tree.h (CPTI_NELTS_IDENTIFIER): Delete. diff --git a/gcc/cp/call.c b/gcc/cp/call.c index d1f27dd..b56da35 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -8025,6 +8025,8 @@ build_over_call (struct z_candidate *cand, int flags, tsubst_flags_t complain) subobject. */ if (CHECKING_P && cxx_dialect >= cxx1z) gcc_assert (TREE_CODE (arg) != TARGET_EXPR + /* It's from binding the ref parm to a packed field. */ + || convs[0]->need_temporary_p || seen_error () /* See unsafe_copy_elision_p. */ || DECL_BASE_CONSTRUCTOR_P (fn)); diff --git a/gcc/testsuite/g++.dg/ext/packed12.C b/gcc/testsuite/g++.dg/ext/packed12.C new file mode 100644 index 0000000..2ad14de --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/packed12.C @@ -0,0 +1,6 @@ +// PR c++/80972 + +struct A { int i; }; +struct B { A a; } __attribute__((packed)); + +A a = B().a; -- cgit v1.1 From b6837e0460c65804f78f3a43e430975d265cbae9 Mon Sep 17 00:00:00 2001 From: Julia Koval Date: Tue, 20 Jun 2017 20:20:51 +0200 Subject: Fix rounding pattern similar to PR73350. gcc/ * config/i386/i386.c: Fix rounding expand for new pattern. * config/i386/subst.md: Fix pattern (parallel -> unspec). gcc/testsuite/ * gcc.target/i386/pr73350-2.c: New test. From-SVN: r249423 --- gcc/ChangeLog | 5 +++++ gcc/config/i386/i386.c | 4 ++-- gcc/config/i386/subst.md | 9 ++++---- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/i386/pr73350-2.c | 35 +++++++++++++++++++++++++++++++ 5 files changed, 51 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr73350-2.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b28620a..b438766 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-20 Julia Koval + + * config/i386/i386.c: Fix rounding expand for new pattern. + * config/i386/subst.md: Fix pattern (parallel -> unspec). + 2017-06-20 James Greenhalgh * config/aarch64/aarch64-option-extensions.def (rcpc): New. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d5c2d46..9f7290a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -36597,8 +36597,8 @@ ix86_expand_sse_comi_round (const struct builtin_description *d, } else { - gcc_assert (GET_CODE (XVECEXP (pat, 0, 0)) == SET); - set_dst = SET_DEST (XVECEXP (pat, 0, 0)); + gcc_assert (GET_CODE (pat) == SET); + set_dst = SET_DEST (pat); } emit_insn (pat); diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index 57fb0d4..4685db3 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -177,10 +177,11 @@ [(set (match_operand:SUBST_A 0) (match_operand:SUBST_A 1))] "TARGET_AVX512F" - [(parallel[ - (set (match_dup 0) - (match_dup 1)) - (unspec [(match_operand:SI 2 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)])]) + [(set (match_dup 0) + (unspec:SUBST_A [(match_dup 1) + (match_operand:SI 2 "const48_operand")] + UNSPEC_EMBEDDED_ROUNDING)) +]) (define_subst_attr "round_expand_name" "round_expand" "" "_round") (define_subst_attr "round_expand_nimm_predicate" "round_expand" "nonimmediate_operand" "register_operand") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e22ebf5..b277662 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-20 Julia Koval + + * gcc.target/i386/pr73350-2.c: New test. + 2017-06-20 Rainer Orth * c-c++-common/fold-masked-cmp-1.c: Allow for i?86-*-* target. diff --git a/gcc/testsuite/gcc.target/i386/pr73350-2.c b/gcc/testsuite/gcc.target/i386/pr73350-2.c new file mode 100644 index 0000000..c1faab4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr73350-2.c @@ -0,0 +1,35 @@ +/* { dg-do run { target *-*-linux* *-*-gnu* } } */ +/* { dg-options "-O2 -mavx512er" } */ +/* { dg-require-effective-target avx512er } */ + +#include "avx512er-check.h" + +#include +#include +#include + +static int counter; + +void handler (int i) +{ + exit (0); +} + +static void +avx512er_test (void) +{ + struct sigaction s; + sigemptyset (&s.sa_mask); + s.sa_handler = handler; + s.sa_flags = 0; + sigaction (SIGFPE, &s, NULL); + + __m512 a = _mm512_set1_ps (-1.f); + + _mm_setcsr ( _MM_MASK_MASK & ~_MM_MASK_INVALID ); + __m512 r1 = _mm512_rsqrt28_round_ps (a, _MM_FROUND_NO_EXC); + __m512 r2 = _mm512_rsqrt28_round_ps (a, _MM_FROUND_CUR_DIRECTION); + + if (r1[0] + r2[0]) + abort (); +} -- cgit v1.1 From 1259ccfcdd8c7262175a17969b12d08352a28727 Mon Sep 17 00:00:00 2001 From: Carl Love Date: Tue, 20 Jun 2017 18:27:48 +0000 Subject: rs6000-c.c (altivec_overloaded_builtins): Add ALTIVEC_BUILTIN_VMULESW... gcc/ChangeLog: 2017-06-20 Carl Love * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW, ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW entries. * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin, builtin_function_type): Add ALTIVEC_BUILTIN_* case statements. * config/rs6000/altivec.md (MVULEUW, VMULESW, VMULOUW, VMULOSW): New enum "unspec" values. (vec_widen_umult_even_v4si, vec_widen_smult_even_v4si, vec_widen_umult_odd_v4si, vec_widen_smult_odd_v4si, altivec_vmuleuw, altivec_vmulesw, altivec_vmulouw, altivec_vmulosw): New patterns. * config/rs6000/rs6000-builtin.def (VMLEUW, VMULESW, VMULOUW, VMULOSW): Add definitions. From-SVN: r249424 --- gcc/ChangeLog | 16 +++++++ gcc/config/rs6000/altivec.md | 93 ++++++++++++++++++++++++++++++++++++ gcc/config/rs6000/rs6000-builtin.def | 8 ++++ gcc/config/rs6000/rs6000-c.c | 8 ++-- gcc/config/rs6000/rs6000.c | 6 +++ 5 files changed, 127 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b438766..8f1bb3d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2017-06-20 Carl Love + + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + ALTIVEC_BUILTIN_VMULESW, ALTIVEC_BUILTIN_VMULEUW, + ALTIVEC_BUILTIN_VMULOSW, ALTIVEC_BUILTIN_VMULOUW entries. + * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin, + builtin_function_type): Add ALTIVEC_BUILTIN_* case statements. + * config/rs6000/altivec.md (MVULEUW, VMULESW, VMULOUW, + VMULOSW): New enum "unspec" values. + (vec_widen_umult_even_v4si, vec_widen_smult_even_v4si, + vec_widen_umult_odd_v4si, vec_widen_smult_odd_v4si, + altivec_vmuleuw, altivec_vmulesw, altivec_vmulouw, + altivec_vmulosw): New patterns. + * config/rs6000/rs6000-builtin.def (VMLEUW, VMULESW, VMULOUW, + VMULOSW): Add definitions. + 2017-06-20 Julia Koval * config/i386/i386.c: Fix rounding expand for new pattern. diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 25b2768..0e3d965 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -36,10 +36,14 @@ UNSPEC_VMULESB UNSPEC_VMULEUH UNSPEC_VMULESH + UNSPEC_VMULEUW + UNSPEC_VMULESW UNSPEC_VMULOUB UNSPEC_VMULOSB UNSPEC_VMULOUH UNSPEC_VMULOSH + UNSPEC_VMULOUW + UNSPEC_VMULOSW UNSPEC_VPKPX UNSPEC_VPACK_SIGN_SIGN_SAT UNSPEC_VPACK_SIGN_UNS_SAT @@ -1412,6 +1416,32 @@ DONE; }) +(define_expand "vec_widen_umult_even_v4si" + [(use (match_operand:V2DI 0 "register_operand" "")) + (use (match_operand:V4SI 1 "register_operand" "")) + (use (match_operand:V4SI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmuleuw (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmulouw (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "vec_widen_smult_even_v4si" + [(use (match_operand:V2DI 0 "register_operand" "")) + (use (match_operand:V4SI 1 "register_operand" "")) + (use (match_operand:V4SI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmulesw (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmulosw (operands[0], operands[1], operands[2])); + DONE; +}) + (define_expand "vec_widen_umult_odd_v16qi" [(use (match_operand:V8HI 0 "register_operand" "")) (use (match_operand:V16QI 1 "register_operand" "")) @@ -1464,6 +1494,34 @@ DONE; }) +(define_expand "vec_widen_umult_odd_v4si" + [(use (match_operand:V2DI 0 "register_operand" "")) + (use (match_operand:V4SI 1 "register_operand" "")) + (use (match_operand:V4SI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmulouw (operands[0], operands[1], operands[2])); + else + emit_insn (gen_altivec_vmuleuw (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "vec_widen_smult_odd_v4si" + [(use (match_operand:V2DI 0 "register_operand" "")) + (use (match_operand:V4SI 1 "register_operand" "")) + (use (match_operand:V4SI 2 "register_operand" ""))] + "TARGET_ALTIVEC" +{ + if (VECTOR_ELT_ORDER_BIG) + emit_insn (gen_altivec_vmulosw (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_altivec_vmulesw (operands[0], operands[1], + operands[2])); + DONE; +}) + (define_insn "altivec_vmuleub" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") @@ -1536,6 +1594,41 @@ "vmulosh %0,%1,%2" [(set_attr "type" "veccomplex")]) +(define_insn "altivec_vmuleuw" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VMULEUW))] + "TARGET_ALTIVEC" + "vmuleuw %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmulouw" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VMULOUW))] + "TARGET_ALTIVEC" + "vmulouw %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmulesw" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VMULESW))] + "TARGET_ALTIVEC" + "vmulesw %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmulosw" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] + UNSPEC_VMULOSW))] + "TARGET_ALTIVEC" + "vmulosw %0,%1,%2" + [(set_attr "type" "veccomplex")]) ;; Vector pack/unpack (define_insn "altivec_vpkpx" diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 4682628..963b9a8 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1031,10 +1031,14 @@ BU_ALTIVEC_2 (VMULEUB, "vmuleub", CONST, vec_widen_umult_even_v16qi) BU_ALTIVEC_2 (VMULESB, "vmulesb", CONST, vec_widen_smult_even_v16qi) BU_ALTIVEC_2 (VMULEUH, "vmuleuh", CONST, vec_widen_umult_even_v8hi) BU_ALTIVEC_2 (VMULESH, "vmulesh", CONST, vec_widen_smult_even_v8hi) +BU_ALTIVEC_2 (VMULEUW, "vmuleuw", CONST, vec_widen_umult_even_v4si) +BU_ALTIVEC_2 (VMULESW, "vmulesw", CONST, vec_widen_smult_even_v4si) BU_ALTIVEC_2 (VMULOUB, "vmuloub", CONST, vec_widen_umult_odd_v16qi) BU_ALTIVEC_2 (VMULOSB, "vmulosb", CONST, vec_widen_smult_odd_v16qi) BU_ALTIVEC_2 (VMULOUH, "vmulouh", CONST, vec_widen_umult_odd_v8hi) BU_ALTIVEC_2 (VMULOSH, "vmulosh", CONST, vec_widen_smult_odd_v8hi) +BU_ALTIVEC_2 (VMULOUW, "vmulouw", CONST, vec_widen_umult_odd_v4si) +BU_ALTIVEC_2 (VMULOSW, "vmulosw", CONST, vec_widen_smult_odd_v4si) BU_ALTIVEC_2 (VNOR, "vnor", CONST, norv4si3) BU_ALTIVEC_2 (VOR, "vor", CONST, iorv4si3) BU_ALTIVEC_2 (VPKUHUM, "vpkuhum", CONST, altivec_vpkuhum) @@ -1346,12 +1350,16 @@ BU_ALTIVEC_OVERLOAD_2 (VMRGLH, "vmrglh") BU_ALTIVEC_OVERLOAD_2 (VMRGLW, "vmrglw") BU_ALTIVEC_OVERLOAD_2 (VMULESB, "vmulesb") BU_ALTIVEC_OVERLOAD_2 (VMULESH, "vmulesh") +BU_ALTIVEC_OVERLOAD_2 (VMULESW, "vmulesw") BU_ALTIVEC_OVERLOAD_2 (VMULEUB, "vmuleub") BU_ALTIVEC_OVERLOAD_2 (VMULEUH, "vmuleuh") +BU_ALTIVEC_OVERLOAD_2 (VMULEUW, "vmuleuw") BU_ALTIVEC_OVERLOAD_2 (VMULOSB, "vmulosb") BU_ALTIVEC_OVERLOAD_2 (VMULOSH, "vmulosh") +BU_ALTIVEC_OVERLOAD_2 (VMULOSW, "vmulosw") BU_ALTIVEC_OVERLOAD_2 (VMULOUB, "vmuloub") BU_ALTIVEC_OVERLOAD_2 (VMULOUH, "vmulouh") +BU_ALTIVEC_OVERLOAD_2 (VMULOUW, "vmulouw") BU_ALTIVEC_OVERLOAD_2 (VPKSHSS, "vpkshss") BU_ALTIVEC_OVERLOAD_2 (VPKSHUS, "vpkshus") BU_ALTIVEC_OVERLOAD_2 (VPKSWSS, "vpkswss") diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 19f6d9c..cfd74ab 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -2229,9 +2229,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH, RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH, + { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESW, RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH, + { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUW, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB, @@ -2248,9 +2248,9 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH, + { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSW, RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH, + { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUW, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH, diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index eee9d0c..de0c6df3 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16334,9 +16334,11 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) /* Even element flavors of vec_mul (signed). */ case ALTIVEC_BUILTIN_VMULESB: case ALTIVEC_BUILTIN_VMULESH: + case ALTIVEC_BUILTIN_VMULESW: /* Even element flavors of vec_mul (unsigned). */ case ALTIVEC_BUILTIN_VMULEUB: case ALTIVEC_BUILTIN_VMULEUH: + case ALTIVEC_BUILTIN_VMULEUW: { arg0 = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); @@ -16349,9 +16351,11 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) /* Odd element flavors of vec_mul (signed). */ case ALTIVEC_BUILTIN_VMULOSB: case ALTIVEC_BUILTIN_VMULOSH: + case ALTIVEC_BUILTIN_VMULOSW: /* Odd element flavors of vec_mul (unsigned). */ case ALTIVEC_BUILTIN_VMULOUB: case ALTIVEC_BUILTIN_VMULOUH: + case ALTIVEC_BUILTIN_VMULOUW: { arg0 = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); @@ -17967,8 +17971,10 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, /* unsigned 2 argument functions. */ case ALTIVEC_BUILTIN_VMULEUB: case ALTIVEC_BUILTIN_VMULEUH: + case ALTIVEC_BUILTIN_VMULEUW: case ALTIVEC_BUILTIN_VMULOUB: case ALTIVEC_BUILTIN_VMULOUH: + case ALTIVEC_BUILTIN_VMULOUW: case CRYPTO_BUILTIN_VCIPHER: case CRYPTO_BUILTIN_VCIPHERLAST: case CRYPTO_BUILTIN_VNCIPHER: -- cgit v1.1 From 8a259e30b1738597b9ddd9d31974d365038fa1d1 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Tue, 20 Jun 2017 21:04:07 +0200 Subject: pr80732.c: Include fma4-check.h. * gcc.target/i386/pr80732.c: Include fma4-check.h. (main): Renamed to ... (fma4_test): ... this. From-SVN: r249425 --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/i386/pr80732.c | 7 ++++--- 2 files changed, 10 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b277662..79c54ca 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-06-20 Uros Bizjak + + * gcc.target/i386/pr80732.c: Include fma4-check.h. + (main): Renamed to ... + (fma4_test): ... this. + 2017-06-20 Julia Koval * gcc.target/i386/pr73350-2.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/pr80732.c b/gcc/testsuite/gcc.target/i386/pr80732.c index 2c59c5e..e120729 100644 --- a/gcc/testsuite/gcc.target/i386/pr80732.c +++ b/gcc/testsuite/gcc.target/i386/pr80732.c @@ -6,6 +6,8 @@ /* { dg-require-effective-target fpic } */ /* { dg-require-effective-target pie } */ +#include "fma4-check.h" + #include __attribute__((target_clones("default","fma"),noinline,optimize("fast-math"))) @@ -51,7 +53,8 @@ double k2(double a, double b, double c, void **p) double (*initializer) (double, double, double) = { &f1 }; -int main() +static void +fma4_test (void) { char buffer[256]; const char *expectation = "4.93038e-32, 4.93038e-32, 4.93038e-32"; @@ -87,6 +90,4 @@ int main() __builtin_sprintf(buffer, "%g, %g, %g", initializer (a, b, c), v2_2, v2_3); if (__builtin_strcmp (buffer, expectation) != 0) __builtin_abort (); - - return 0; } -- cgit v1.1 From 0dc7d7cc944ddf8903d14199922fe31cec9693dd Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 20 Jun 2017 21:43:29 +0200 Subject: ira-costs.c (find_costs_and_classes): Initialize cost_classes later to make sure not to dereference a NULL... * ira-costs.c (find_costs_and_classes): Initialize cost_classes later to make sure not to dereference a NULL cost_classes_ptr pointer. From-SVN: r249426 --- gcc/ChangeLog | 5 +++++ gcc/ira-costs.c | 4 +++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f1bb3d..200dbe4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-20 Jakub Jelinek + + * ira-costs.c (find_costs_and_classes): Initialize cost_classes later + to make sure not to dereference a NULL cost_classes_ptr pointer. + 2017-06-20 Carl Love * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c index 9cf0119..2cd102a 100644 --- a/gcc/ira-costs.c +++ b/gcc/ira-costs.c @@ -1744,7 +1744,7 @@ find_costs_and_classes (FILE *dump_file) int best_cost, allocno_cost; enum reg_class best, alt_class; cost_classes_t cost_classes_ptr = regno_cost_classes[i]; - enum reg_class *cost_classes = cost_classes_ptr->classes; + enum reg_class *cost_classes; int *i_costs = temp_costs->cost; int i_mem_cost; int equiv_savings = regno_equiv_gains[i]; @@ -1755,6 +1755,7 @@ find_costs_and_classes (FILE *dump_file) continue; memcpy (temp_costs, COSTS (costs, i), struct_costs_size); i_mem_cost = temp_costs->mem_cost; + cost_classes = cost_classes_ptr->classes; } else { @@ -1762,6 +1763,7 @@ find_costs_and_classes (FILE *dump_file) continue; memset (temp_costs, 0, struct_costs_size); i_mem_cost = 0; + cost_classes = cost_classes_ptr->classes; /* Find cost of all allocnos with the same regno. */ for (a = ira_regno_allocno_map[i]; a != NULL; -- cgit v1.1 From 191578a57755cf7a53f1f24bbba7d9df79e63efe Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Tue, 20 Jun 2017 20:37:28 +0000 Subject: Fix -Werror=class-memaccess failures in jit testsuite (PR jit/81144) gcc/testsuite/ChangeLog: PR jit/81144 * jit.dg/test-operator-overloading.cc (make_test_quadratic): Replace memset call with zero-initialization. * jit.dg/test-quadratic.cc (make_test_quadratic): Likewise. From-SVN: r249427 --- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/jit.dg/test-operator-overloading.cc | 3 +-- gcc/testsuite/jit.dg/test-quadratic.cc | 3 +-- 3 files changed, 9 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 79c54ca..d5d658f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2017-06-20 David Malcolm + + PR jit/81144 + * jit.dg/test-operator-overloading.cc (make_test_quadratic): Replace + memset call with zero-initialization. + * jit.dg/test-quadratic.cc (make_test_quadratic): Likewise. + 2017-06-20 Uros Bizjak * gcc.target/i386/pr80732.c: Include fma4-check.h. diff --git a/gcc/testsuite/jit.dg/test-operator-overloading.cc b/gcc/testsuite/jit.dg/test-operator-overloading.cc index cbb1e98..f57b3fc 100644 --- a/gcc/testsuite/jit.dg/test-operator-overloading.cc +++ b/gcc/testsuite/jit.dg/test-operator-overloading.cc @@ -272,8 +272,7 @@ make_test_quadratic (quadratic_test &testcase) void create_code (gcc_jit_context *ctxt, void *user_data) { - struct quadratic_test testcase; - memset (&testcase, 0, sizeof (testcase)); + struct quadratic_test testcase = {}; testcase.ctxt = ctxt; make_types (testcase); make_sqrt (testcase); diff --git a/gcc/testsuite/jit.dg/test-quadratic.cc b/gcc/testsuite/jit.dg/test-quadratic.cc index f347669..61b5cdd 100644 --- a/gcc/testsuite/jit.dg/test-quadratic.cc +++ b/gcc/testsuite/jit.dg/test-quadratic.cc @@ -328,8 +328,7 @@ make_test_quadratic (quadratic_test &testcase) void create_code (gcc_jit_context *ctxt, void *user_data) { - struct quadratic_test testcase; - memset (&testcase, 0, sizeof (testcase)); + struct quadratic_test testcase = {}; testcase.ctxt = ctxt; make_types (testcase); make_sqrt (testcase); -- cgit v1.1 From b5e204dc76d982635b1b8b43ad30fbdc0c723a31 Mon Sep 17 00:00:00 2001 From: Andreas Tobler Date: Tue, 20 Jun 2017 23:28:15 +0200 Subject: config.gcc (armv6*-*-freebsd*): Change the target_cpu_cname to arm1176jzf-s. 2017-06-20 Andreas Tobler * config.gcc (armv6*-*-freebsd*): Change the target_cpu_cname to arm1176jzf-s. From-SVN: r249428 --- gcc/ChangeLog | 5 +++++ gcc/config.gcc | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 200dbe4..b45ec89 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-20 Andreas Tobler + + * config.gcc (armv6*-*-freebsd*): Change the target_cpu_cname to + arm1176jzf-s. + 2017-06-20 Jakub Jelinek * ira-costs.c (find_costs_and_classes): Initialize cost_classes later diff --git a/gcc/config.gcc b/gcc/config.gcc index 0518cb7..430779e 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1089,7 +1089,7 @@ arm*-*-freebsd*) # ARM FreeBSD EABI tm_file="${tm_file} arm/bpabi.h arm/freebsd.h arm/aout.h arm/arm.h" case $target in armv6*-*-freebsd*) - target_cpu_cname="arm1176jzfs" + target_cpu_cname="arm1176jzf-s" tm_defines="${tm_defines} TARGET_FREEBSD_ARMv6=1" if test $fbsd_major -ge 11; then tm_defines="${tm_defines} TARGET_FREEBSD_ARM_HARD_FLOAT=1" -- cgit v1.1 From 12d0fd3f853447360a61a82a6a8357a0df31c662 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Wed, 21 Jun 2017 00:16:31 +0000 Subject: Daily bump. From-SVN: r249432 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 30a5315..12ee994 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170620 +20170621 -- cgit v1.1 From a2074e9c4fe01e6b9130324c3d40cf2ce7072b2d Mon Sep 17 00:00:00 2001 From: Julian Brown Date: Wed, 21 Jun 2017 05:36:03 +0000 Subject: * config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi) (aarch64_crypto_pmullv2di): Change type attribute to crypto_pmull. * config/aarch64/thunderx2t99.md (thunderx2t99_pmull): New reservation. * config/arm/cortex-a57.md (cortex_a57_neon_type): Add crypto_pmull to attribute type list for neon_multiply. * config/arm/crypto.md (crypto_vmullp64): Change type to crypto_pmull. * config/arm/types.md (crypto_pmull): Add. * config/arm/xgene1.md (xgene1_neon_pmull): Add crypto_pmull to attribute type list. Co-Authored-By: Naveen H.S From-SVN: r249433 --- gcc/ChangeLog | 14 ++++++++++++++ gcc/config/aarch64/aarch64-simd.md | 4 ++-- gcc/config/aarch64/thunderx2t99.md | 7 +++++++ gcc/config/arm/cortex-a53.md | 2 +- gcc/config/arm/cortex-a57.md | 2 +- gcc/config/arm/crypto.md | 2 +- gcc/config/arm/exynos-m1.md | 2 +- gcc/config/arm/types.md | 2 ++ gcc/config/arm/xgene1.md | 3 ++- 9 files changed, 31 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b45ec89..70c0384 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2017-06-21 Julian Brown + Naveen H.S + + * config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi) + (aarch64_crypto_pmullv2di): Change type attribute to crypto_pmull. + * config/aarch64/thunderx2t99.md (thunderx2t99_pmull): New + reservation. + * config/arm/cortex-a57.md (cortex_a57_neon_type): Add crypto_pmull to + attribute type list for neon_multiply. + * config/arm/crypto.md (crypto_vmullp64): Change type to crypto_pmull. + * config/arm/types.md (crypto_pmull): Add. + * config/arm/xgene1.md (xgene1_neon_pmull): Add crypto_pmull to + attribute type list. + 2017-06-20 Andreas Tobler * config.gcc (armv6*-*-freebsd*): Change the target_cpu_cname to diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index c5a86ff..e811f3e 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5831,7 +5831,7 @@ UNSPEC_PMULL))] "TARGET_SIMD && TARGET_CRYPTO" "pmull\\t%0.1q, %1.1d, %2.1d" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) (define_insn "aarch64_crypto_pmullv2di" @@ -5841,5 +5841,5 @@ UNSPEC_PMULL2))] "TARGET_SIMD && TARGET_CRYPTO" "pmull2\\t%0.1q, %1.2d, %2.2d" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md index adb010c..7134884 100644 --- a/gcc/config/aarch64/thunderx2t99.md +++ b/gcc/config/aarch64/thunderx2t99.md @@ -461,3 +461,10 @@ (and (eq_attr "tune" "thunderx2t99") (eq_attr "type" "crc")) "thunderx2t99_i1") + +;; PMULL extension. + +(define_insn_reservation "thunderx2t99_pmull" 5 + (and (eq_attr "tune" "thunderx2t99") + (eq_attr "type" "crypto_pmull")) + "thunderx2t99_f1") diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index ff16e36..3c61337 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -389,7 +389,7 @@ neon_sat_mul_b_long, neon_sat_mul_h_long,\ neon_sat_mul_s_long, neon_sat_mul_h_scalar_q,\ neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\ - neon_sat_mul_s_scalar_long, neon_mla_b_q,\ + neon_sat_mul_s_scalar_long, crypto_pmull, neon_mla_b_q,\ neon_mla_h_q, neon_mla_s_q, neon_mla_b_long,\ neon_mla_h_long, neon_mla_s_long,\ neon_mla_h_scalar_q, neon_mla_s_scalar_q,\ diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index fd30758..ebf4a49 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -76,7 +76,7 @@ neon_mul_h_scalar_long, neon_mul_s_scalar_long,\ neon_sat_mul_b_long, neon_sat_mul_h_long,\ neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\ - neon_sat_mul_s_scalar_long") + neon_sat_mul_s_scalar_long, crypto_pmull") (const_string "neon_multiply") (eq_attr "type" "neon_mul_b_q, neon_mul_h_q, neon_mul_s_q,\ neon_mul_h_scalar_q, neon_mul_s_scalar_q,\ diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md index 46b0715..a5e558b 100644 --- a/gcc/config/arm/crypto.md +++ b/gcc/config/arm/crypto.md @@ -81,7 +81,7 @@ UNSPEC_VMULLP64))] "TARGET_CRYPTO" "vmull.p64\\t%q0, %P1, %P2" - [(set_attr "type" "neon_mul_d_long")] + [(set_attr "type" "crypto_pmull")] ) (define_insn "crypto_" diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md index 5d397cc..b54d4c8 100644 --- a/gcc/config/arm/exynos-m1.md +++ b/gcc/config/arm/exynos-m1.md @@ -78,7 +78,7 @@ neon_sat_mul_s_scalar, neon_sat_mul_s_scalar_q,\ neon_sat_mul_b_long, neon_sat_mul_h_long,\ neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\ - neon_sat_mul_s_scalar_long") + neon_sat_mul_s_scalar_long, crypto_pmull") (const_string "neon_multiply") (eq_attr "type" "neon_mla_b, neon_mla_h, neon_mla_s,\ diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index b0b375c..253f496 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -539,6 +539,7 @@ ; crypto_sha1_slow ; crypto_sha256_fast ; crypto_sha256_slow +; crypto_pmull ; ; The classification below is for coprocessor instructions ; @@ -1078,6 +1079,7 @@ crypto_sha1_slow,\ crypto_sha256_fast,\ crypto_sha256_slow,\ + crypto_pmull,\ coproc" (const_string "untyped")) diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index 62a0732..34a13f4 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -527,5 +527,6 @@ (define_insn_reservation "xgene1_neon_pmull" 5 (and (eq_attr "tune" "xgene1") (eq_attr "type" "neon_mul_d_long,\ - ")) + crypto_pmull,\ + ")) "xgene1_decode2op") -- cgit v1.1 From e2bb0ed087b7e0a4c14f90968e84e59f55e2de12 Mon Sep 17 00:00:00 2001 From: "Naveen H.S" Date: Wed, 21 Jun 2017 05:47:24 +0000 Subject: Update the ChangeLog to include config/arm/cortex-a53.md and config/arm/exynos-m1.md modifications From-SVN: r249434 --- gcc/ChangeLog | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 70c0384..58b7473 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -5,9 +5,13 @@ (aarch64_crypto_pmullv2di): Change type attribute to crypto_pmull. * config/aarch64/thunderx2t99.md (thunderx2t99_pmull): New reservation. + * config/arm/cortex-a53.md (cortex_a53_advsimd_type): Add crypto_pmull to + attribute type list for neon_multiply. * config/arm/cortex-a57.md (cortex_a57_neon_type): Add crypto_pmull to attribute type list for neon_multiply. * config/arm/crypto.md (crypto_vmullp64): Change type to crypto_pmull. + * config/arm/exynos-m1.md (exynos_m1_neon_type): Add crypto_pmull to + attribute type list for neon_multiply. * config/arm/types.md (crypto_pmull): Add. * config/arm/xgene1.md (xgene1_neon_pmull): Add crypto_pmull to attribute type list. -- cgit v1.1 From 6b92ab17be7b413d2f14e40c98c62fd95f6e994e Mon Sep 17 00:00:00 2001 From: Tom de Vries Date: Wed, 21 Jun 2017 09:10:16 +0000 Subject: Add dg-add-options feature stack_size 2017-06-21 Tom de Vries * doc/sourcebuild.texi (Add Options, Features for dg-add-options): Add stack_size feature. (Effective-Target Keywords, Other attributes): Suggest using dg-add-options stack_size feature to get stack limit in stack_size effective target documentation. * lib/target-supports.exp (add_options_for_stack_size): New proc. * gcc.c-torture/execute/920501-7.c: Use dg-add-options stack_size. * gcc.c-torture/compile/20080806-1.c: Same. * gcc.c-torture/compile/920723-1.c: Same. * gcc.c-torture/compile/930621-1.c: Same. * gcc.c-torture/compile/991214-2.c: Same. * gcc.c-torture/compile/bcopy.c: Same. * gcc.c-torture/compile/memtst.c: Same. * gcc.c-torture/compile/msp.c: Same. * gcc.c-torture/compile/stuct.c: Same. * gcc.c-torture/execute/20011008-3.c: Same. * gcc.c-torture/execute/20030209-1.c: Same. * gcc.c-torture/execute/20031012-1.c: Same. * gcc.c-torture/execute/20040805-1.c: Same. * gcc.c-torture/execute/920410-1.c: Same. * gcc.c-torture/execute/921113-1.c: Same. * gcc.c-torture/execute/921202-1.c: Same. * gcc.c-torture/execute/921208-2.c: Same. * gcc.c-torture/execute/930106-1.c: Same. * gcc.c-torture/execute/930406-1.c: Same. * gcc.c-torture/execute/950221-1.c: Same. * gcc.c-torture/execute/960521-1.c: Same. * gcc.c-torture/execute/980605-1.c: Same. * gcc.c-torture/execute/comp-goto-1.c: Same. * gcc.c-torture/execute/comp-goto-2.c: Same. * gcc.c-torture/execute/memcpy-1.c: Same. * gcc.c-torture/execute/multi-ix.c: Same. * gcc.c-torture/execute/nestfunc-4.c: Same. * gcc.c-torture/execute/pr20621-1.c: Same. * gcc.c-torture/execute/pr23135.c: Same. * gcc.c-torture/execute/pr28982b.c: Same. * gcc.dg/loop-3.c: Same. * gcc.dg/struct-ret-3.c: Same. * gcc.dg/torture/stackalign/comp-goto-1.c: Same. * gcc.dg/torture/stackalign/non-local-goto-4.c: Same. * gcc.dg/tree-prof/comp-goto-1.c: Same. * gcc.dg/tree-prof/pr44777.c: Same. From-SVN: r249440 --- gcc/ChangeLog | 8 +++++ gcc/doc/sourcebuild.texi | 15 +++++--- gcc/testsuite/ChangeLog | 40 ++++++++++++++++++++++ gcc/testsuite/gcc.c-torture/compile/20080806-1.c | 2 +- gcc/testsuite/gcc.c-torture/compile/920723-1.c | 2 +- gcc/testsuite/gcc.c-torture/compile/930621-1.c | 2 +- gcc/testsuite/gcc.c-torture/compile/991214-2.c | 2 +- gcc/testsuite/gcc.c-torture/compile/bcopy.c | 2 +- gcc/testsuite/gcc.c-torture/compile/memtst.c | 2 +- gcc/testsuite/gcc.c-torture/compile/msp.c | 2 +- gcc/testsuite/gcc.c-torture/compile/stuct.c | 2 +- gcc/testsuite/gcc.c-torture/execute/20011008-3.c | 2 +- gcc/testsuite/gcc.c-torture/execute/20030209-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/20031012-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/20040805-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/920410-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/920501-7.c | 2 +- gcc/testsuite/gcc.c-torture/execute/921113-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/921202-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/921208-2.c | 2 +- gcc/testsuite/gcc.c-torture/execute/930106-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/930406-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/950221-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/960521-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/980605-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/comp-goto-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/comp-goto-2.c | 2 +- gcc/testsuite/gcc.c-torture/execute/memcpy-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/multi-ix.c | 2 +- gcc/testsuite/gcc.c-torture/execute/nestfunc-4.c | 2 +- gcc/testsuite/gcc.c-torture/execute/pr20621-1.c | 2 +- gcc/testsuite/gcc.c-torture/execute/pr23135.c | 2 +- gcc/testsuite/gcc.c-torture/execute/pr28982b.c | 2 +- gcc/testsuite/gcc.dg/loop-3.c | 2 +- gcc/testsuite/gcc.dg/struct-ret-3.c | 2 +- .../gcc.dg/torture/stackalign/comp-goto-1.c | 2 +- .../gcc.dg/torture/stackalign/non-local-goto-4.c | 2 +- gcc/testsuite/gcc.dg/tree-prof/comp-goto-1.c | 2 +- gcc/testsuite/gcc.dg/tree-prof/pr44777.c | 2 +- gcc/testsuite/lib/target-supports.exp | 11 ++++++ 40 files changed, 105 insertions(+), 41 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 58b7473..199a01f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-06-21 Tom de Vries + + * doc/sourcebuild.texi (Add Options, Features for dg-add-options): Add + stack_size feature. + (Effective-Target Keywords, Other attributes): Suggest using + dg-add-options stack_size feature to get stack limit in stack_size + effective target documentation. + 2017-06-21 Julian Brown Naveen H.S diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index e5f0da6..7f5c2cf 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2097,11 +2097,10 @@ Target supports section anchors. Target defaults to short enums. @item stack_size -Target has limited stack size. The stack size limit can be obtained using -@code{[dg-effective-target-value stack_size]}. For example: -@smallexample -/* @{ dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" @{ target @{ stack_size @} @} @} */ -@end smallexample +@anchor{stack_size_et} +Target has limited stack size. The stack size limit can be obtained using the +STACK_SIZE macro defined by @ref{stack_size_ao,,@code{dg-add-options} feature +@code{stack_size}}. @item static Target supports @option{-static}. @@ -2282,6 +2281,12 @@ compliance mode. @code{mips16} function attributes. Only MIPS targets support this feature, and only then in certain modes. +@item stack_size +@anchor{stack_size_ao} +Add the flags needed to define macro STACK_SIZE and set it to the stack size +limit associated with the @ref{stack_size_et,,@code{stack_size} effective +target}. + @item tls Add the target-specific flags needed to use thread-local storage. @end table diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d5d658f..a7524ac 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,43 @@ +2017-06-21 Tom de Vries + + * lib/target-supports.exp (add_options_for_stack_size): New proc. + * gcc.c-torture/execute/920501-7.c: Use dg-add-options stack_size. + * gcc.c-torture/compile/20080806-1.c: Same. + * gcc.c-torture/compile/920723-1.c: Same. + * gcc.c-torture/compile/930621-1.c: Same. + * gcc.c-torture/compile/991214-2.c: Same. + * gcc.c-torture/compile/bcopy.c: Same. + * gcc.c-torture/compile/memtst.c: Same. + * gcc.c-torture/compile/msp.c: Same. + * gcc.c-torture/compile/stuct.c: Same. + * gcc.c-torture/execute/20011008-3.c: Same. + * gcc.c-torture/execute/20030209-1.c: Same. + * gcc.c-torture/execute/20031012-1.c: Same. + * gcc.c-torture/execute/20040805-1.c: Same. + * gcc.c-torture/execute/920410-1.c: Same. + * gcc.c-torture/execute/921113-1.c: Same. + * gcc.c-torture/execute/921202-1.c: Same. + * gcc.c-torture/execute/921208-2.c: Same. + * gcc.c-torture/execute/930106-1.c: Same. + * gcc.c-torture/execute/930406-1.c: Same. + * gcc.c-torture/execute/950221-1.c: Same. + * gcc.c-torture/execute/960521-1.c: Same. + * gcc.c-torture/execute/980605-1.c: Same. + * gcc.c-torture/execute/comp-goto-1.c: Same. + * gcc.c-torture/execute/comp-goto-2.c: Same. + * gcc.c-torture/execute/memcpy-1.c: Same. + * gcc.c-torture/execute/multi-ix.c: Same. + * gcc.c-torture/execute/nestfunc-4.c: Same. + * gcc.c-torture/execute/pr20621-1.c: Same. + * gcc.c-torture/execute/pr23135.c: Same. + * gcc.c-torture/execute/pr28982b.c: Same. + * gcc.dg/loop-3.c: Same. + * gcc.dg/struct-ret-3.c: Same. + * gcc.dg/torture/stackalign/comp-goto-1.c: Same. + * gcc.dg/torture/stackalign/non-local-goto-4.c: Same. + * gcc.dg/tree-prof/comp-goto-1.c: Same. + * gcc.dg/tree-prof/pr44777.c: Same. + 2017-06-20 David Malcolm PR jit/81144 diff --git a/gcc/testsuite/gcc.c-torture/compile/20080806-1.c b/gcc/testsuite/gcc.c-torture/compile/20080806-1.c index d0ee9cc..45f29d1 100644 --- a/gcc/testsuite/gcc.c-torture/compile/20080806-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/20080806-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ /* This used to ICE on s390x due to a reload bug. */ diff --git a/gcc/testsuite/gcc.c-torture/compile/920723-1.c b/gcc/testsuite/gcc.c-torture/compile/920723-1.c index c6351c37..cd8710b 100644 --- a/gcc/testsuite/gcc.c-torture/compile/920723-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/920723-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #if defined(STACK_SIZE) && STACK_SIZE < 65536 # define GITT_SIZE 75 diff --git a/gcc/testsuite/gcc.c-torture/compile/930621-1.c b/gcc/testsuite/gcc.c-torture/compile/930621-1.c index 13e997a..ce0f25b 100644 --- a/gcc/testsuite/gcc.c-torture/compile/930621-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/930621-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #if defined(STACK_SIZE) && (STACK_SIZE < 65536) # define BYTEMEM_SIZE 10000L diff --git a/gcc/testsuite/gcc.c-torture/compile/991214-2.c b/gcc/testsuite/gcc.c-torture/compile/991214-2.c index 32dad4f..79df357 100644 --- a/gcc/testsuite/gcc.c-torture/compile/991214-2.c +++ b/gcc/testsuite/gcc.c-torture/compile/991214-2.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #if defined(STACK_SIZE) && (STACK_SIZE < 65536) # define HISTO_SIZE 9 diff --git a/gcc/testsuite/gcc.c-torture/compile/bcopy.c b/gcc/testsuite/gcc.c-torture/compile/bcopy.c index cb7c05d..8108f29 100644 --- a/gcc/testsuite/gcc.c-torture/compile/bcopy.c +++ b/gcc/testsuite/gcc.c-torture/compile/bcopy.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ void bcopy1 (s, d, c) diff --git a/gcc/testsuite/gcc.c-torture/compile/memtst.c b/gcc/testsuite/gcc.c-torture/compile/memtst.c index e165a22..44cdaf8 100644 --- a/gcc/testsuite/gcc.c-torture/compile/memtst.c +++ b/gcc/testsuite/gcc.c-torture/compile/memtst.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #ifdef STACK_SIZE #define SIZE STACK_SIZE / 8 diff --git a/gcc/testsuite/gcc.c-torture/compile/msp.c b/gcc/testsuite/gcc.c-torture/compile/msp.c index 594cecb..263a873 100644 --- a/gcc/testsuite/gcc.c-torture/compile/msp.c +++ b/gcc/testsuite/gcc.c-torture/compile/msp.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #ifdef STACK_SIZE # define A_SIZE (STACK_SIZE/sizeof(int)) diff --git a/gcc/testsuite/gcc.c-torture/compile/stuct.c b/gcc/testsuite/gcc.c-torture/compile/stuct.c index 59acd57..b70957e 100644 --- a/gcc/testsuite/gcc.c-torture/compile/stuct.c +++ b/gcc/testsuite/gcc.c-torture/compile/stuct.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #ifdef STACK_SIZE #define SIZE STACK_SIZE / 8 diff --git a/gcc/testsuite/gcc.c-torture/execute/20011008-3.c b/gcc/testsuite/gcc.c-torture/execute/20011008-3.c index 2fd6871..0f56302 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20011008-3.c +++ b/gcc/testsuite/gcc.c-torture/execute/20011008-3.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ extern void exit (int); extern void abort (void); diff --git a/gcc/testsuite/gcc.c-torture/execute/20030209-1.c b/gcc/testsuite/gcc.c-torture/execute/20030209-1.c index 72c1e55..8f076ec 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20030209-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20030209-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #ifdef STACK_SIZE #if STACK_SIZE < 8*100*100 diff --git a/gcc/testsuite/gcc.c-torture/execute/20031012-1.c b/gcc/testsuite/gcc.c-torture/execute/20031012-1.c index db7f3fa..e02baf5 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20031012-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20031012-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ /* PR optimization/8750 Used to fail under Cygwin with diff --git a/gcc/testsuite/gcc.c-torture/execute/20040805-1.c b/gcc/testsuite/gcc.c-torture/execute/20040805-1.c index 4e978f5..d3208d6 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20040805-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20040805-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #if __INT_MAX__ < 32768 || (defined(STACK_SIZE) && STACK_SIZE < 0x12000) int main () { exit (0); } diff --git a/gcc/testsuite/gcc.c-torture/execute/920410-1.c b/gcc/testsuite/gcc.c-torture/execute/920410-1.c index 50bc417..44a72bd 100644 --- a/gcc/testsuite/gcc.c-torture/execute/920410-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/920410-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #define STACK_REQUIREMENT (40000 * 4 + 256) #if defined (STACK_SIZE) && STACK_SIZE < STACK_REQUIREMENT diff --git a/gcc/testsuite/gcc.c-torture/execute/920501-7.c b/gcc/testsuite/gcc.c-torture/execute/920501-7.c index 5cced09..1396eeb 100644 --- a/gcc/testsuite/gcc.c-torture/execute/920501-7.c +++ b/gcc/testsuite/gcc.c-torture/execute/920501-7.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target label_values } */ /* { dg-require-effective-target trampolines } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #ifdef STACK_SIZE #define DEPTH ((STACK_SIZE) / 512 + 1) diff --git a/gcc/testsuite/gcc.c-torture/execute/921113-1.c b/gcc/testsuite/gcc.c-torture/execute/921113-1.c index 24c4952..d3e44e3 100644 --- a/gcc/testsuite/gcc.c-torture/execute/921113-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/921113-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #define STACK_REQUIREMENT (128 * 128 * 4 + 1024) #if defined (STACK_SIZE) && STACK_SIZE < STACK_REQUIREMENT diff --git a/gcc/testsuite/gcc.c-torture/execute/921202-1.c b/gcc/testsuite/gcc.c-torture/execute/921202-1.c index 530fad0..8c6b8c7 100644 --- a/gcc/testsuite/gcc.c-torture/execute/921202-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/921202-1.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target untyped_assembly } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #ifndef STACK_SIZE #define VLEN 2055 diff --git a/gcc/testsuite/gcc.c-torture/execute/921208-2.c b/gcc/testsuite/gcc.c-torture/execute/921208-2.c index f18f2c8..da9ee52 100644 --- a/gcc/testsuite/gcc.c-torture/execute/921208-2.c +++ b/gcc/testsuite/gcc.c-torture/execute/921208-2.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target untyped_assembly } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #define STACK_REQUIREMENT (100000 * 4 + 1024) #if defined (STACK_SIZE) && STACK_SIZE < STACK_REQUIREMENT diff --git a/gcc/testsuite/gcc.c-torture/execute/930106-1.c b/gcc/testsuite/gcc.c-torture/execute/930106-1.c index 41add7d..cae2c54 100644 --- a/gcc/testsuite/gcc.c-torture/execute/930106-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/930106-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #if defined (STACK_SIZE) #define DUMMY_SIZE 9 diff --git a/gcc/testsuite/gcc.c-torture/execute/930406-1.c b/gcc/testsuite/gcc.c-torture/execute/930406-1.c index 0d6b0fb..f240d1b 100644 --- a/gcc/testsuite/gcc.c-torture/execute/930406-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/930406-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ f() { diff --git a/gcc/testsuite/gcc.c-torture/execute/950221-1.c b/gcc/testsuite/gcc.c-torture/execute/950221-1.c index aa71024..8ef83fd 100644 --- a/gcc/testsuite/gcc.c-torture/execute/950221-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/950221-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ struct parsefile { diff --git a/gcc/testsuite/gcc.c-torture/execute/960521-1.c b/gcc/testsuite/gcc.c-torture/execute/960521-1.c index fc69ff9..0174e7b 100644 --- a/gcc/testsuite/gcc.c-torture/execute/960521-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/960521-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #include diff --git a/gcc/testsuite/gcc.c-torture/execute/980605-1.c b/gcc/testsuite/gcc.c-torture/execute/980605-1.c index 9185f2b..7179ba6 100644 --- a/gcc/testsuite/gcc.c-torture/execute/980605-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/980605-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #include diff --git a/gcc/testsuite/gcc.c-torture/execute/comp-goto-1.c b/gcc/testsuite/gcc.c-torture/execute/comp-goto-1.c index 3bc00ef..2a84052 100644 --- a/gcc/testsuite/gcc.c-torture/execute/comp-goto-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/comp-goto-1.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target label_values } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #include diff --git a/gcc/testsuite/gcc.c-torture/execute/comp-goto-2.c b/gcc/testsuite/gcc.c-torture/execute/comp-goto-2.c index 21a1e6f..95d23a2f 100644 --- a/gcc/testsuite/gcc.c-torture/execute/comp-goto-2.c +++ b/gcc/testsuite/gcc.c-torture/execute/comp-goto-2.c @@ -1,6 +1,6 @@ /* { dg-require-effective-target label_values } */ /* { dg-require-effective-target trampolines } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ /* A slight variation of 920501-7.c. */ diff --git a/gcc/testsuite/gcc.c-torture/execute/memcpy-1.c b/gcc/testsuite/gcc.c-torture/execute/memcpy-1.c index e94ab8a..558c937 100644 --- a/gcc/testsuite/gcc.c-torture/execute/memcpy-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/memcpy-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #include diff --git a/gcc/testsuite/gcc.c-torture/execute/multi-ix.c b/gcc/testsuite/gcc.c-torture/execute/multi-ix.c index 8ab041b..39567f1 100644 --- a/gcc/testsuite/gcc.c-torture/execute/multi-ix.c +++ b/gcc/testsuite/gcc.c-torture/execute/multi-ix.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ /* Test for a reload bug: if you have a memory reference using the indexed addressing diff --git a/gcc/testsuite/gcc.c-torture/execute/nestfunc-4.c b/gcc/testsuite/gcc.c-torture/execute/nestfunc-4.c index ee5b376..c722570 100644 --- a/gcc/testsuite/gcc.c-torture/execute/nestfunc-4.c +++ b/gcc/testsuite/gcc.c-torture/execute/nestfunc-4.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ /* Origin: hp@bitrange.com Test that return values come out right from a 1000-level call chain to diff --git a/gcc/testsuite/gcc.c-torture/execute/pr20621-1.c b/gcc/testsuite/gcc.c-torture/execute/pr20621-1.c index 4a55c97..9d0119b 100644 --- a/gcc/testsuite/gcc.c-torture/execute/pr20621-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/pr20621-1.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ /* When generating o32 MIPS PIC, main's $gp save slot was out of range of a single load instruction. */ diff --git a/gcc/testsuite/gcc.c-torture/execute/pr23135.c b/gcc/testsuite/gcc.c-torture/execute/pr23135.c index 31b4f8f..8dd6358 100644 --- a/gcc/testsuite/gcc.c-torture/execute/pr23135.c +++ b/gcc/testsuite/gcc.c-torture/execute/pr23135.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ /* Based on execute/simd-1.c, modified by joern.rennecke@st.com to trigger a reload bug. Verified for gcc mainline from 20050722 13:00 UTC diff --git a/gcc/testsuite/gcc.c-torture/execute/pr28982b.c b/gcc/testsuite/gcc.c-torture/execute/pr28982b.c index 90d4a93..f28425e 100644 --- a/gcc/testsuite/gcc.c-torture/execute/pr28982b.c +++ b/gcc/testsuite/gcc.c-torture/execute/pr28982b.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ /* Like pr28982a.c, but with the spill slots outside the range of a single sp-based load on ARM. This test tests for cases where diff --git a/gcc/testsuite/gcc.dg/loop-3.c b/gcc/testsuite/gcc.dg/loop-3.c index 2c500d0..7472ea1 100644 --- a/gcc/testsuite/gcc.dg/loop-3.c +++ b/gcc/testsuite/gcc.dg/loop-3.c @@ -4,7 +4,7 @@ /* { dg-do compile } */ /* { dg-options "-O3" } */ /* { dg-options "-O3 -mtune=i386" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #if defined(STACK_SIZE) && (STACK_SIZE < 65536) # define BYTEMEM_SIZE 10000L diff --git a/gcc/testsuite/gcc.dg/struct-ret-3.c b/gcc/testsuite/gcc.dg/struct-ret-3.c index c6f87ac..4083bb4 100644 --- a/gcc/testsuite/gcc.dg/struct-ret-3.c +++ b/gcc/testsuite/gcc.dg/struct-ret-3.c @@ -2,7 +2,7 @@ /* Origin: Peeter Joot */ /* { dg-do run { target *-*-linux* *-*-gnu* } } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #include #include diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/comp-goto-1.c b/gcc/testsuite/gcc.dg/torture/stackalign/comp-goto-1.c index 726bb20..f4ff831 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/comp-goto-1.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/comp-goto-1.c @@ -1,7 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target label_values } */ /* { dg-require-effective-target trampolines } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #ifdef STACK_SIZE #define DEPTH ((STACK_SIZE) / 512 + 1) diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/non-local-goto-4.c b/gcc/testsuite/gcc.dg/torture/stackalign/non-local-goto-4.c index 90ca71c..922c6b3 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/non-local-goto-4.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/non-local-goto-4.c @@ -2,7 +2,7 @@ /* { dg-require-effective-target nonlocal_goto } */ /* { dg-require-effective-target label_values } */ /* { dg-require-effective-target trampolines } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ extern void abort (void); extern void exit (int); diff --git a/gcc/testsuite/gcc.dg/tree-prof/comp-goto-1.c b/gcc/testsuite/gcc.dg/tree-prof/comp-goto-1.c index dd6774f..bb1d120 100644 --- a/gcc/testsuite/gcc.dg/tree-prof/comp-goto-1.c +++ b/gcc/testsuite/gcc.dg/tree-prof/comp-goto-1.c @@ -1,7 +1,7 @@ /* { dg-require-effective-target freorder } */ /* { dg-require-effective-target label_values } */ /* { dg-options "-O2 -freorder-blocks-and-partition" } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ #include diff --git a/gcc/testsuite/gcc.dg/tree-prof/pr44777.c b/gcc/testsuite/gcc.dg/tree-prof/pr44777.c index 1249b5b..def1164 100644 --- a/gcc/testsuite/gcc.dg/tree-prof/pr44777.c +++ b/gcc/testsuite/gcc.dg/tree-prof/pr44777.c @@ -2,7 +2,7 @@ /* { dg-require-effective-target label_values } */ /* { dg-require-effective-target trampolines } */ /* { dg-options "-O0" } */ -/* { dg-additional-options "-DSTACK_SIZE=[dg-effective-target-value stack_size]" { target { stack_size } } } */ +/* { dg-add-options stack_size } */ /* A variant of gcc.c-torture/execute/comp-goto-2.c. */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 31701c2..502986e 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -7249,6 +7249,17 @@ proc add_options_for_double_vectors { flags } { return $flags } +# Add to FLAGS the flags needed to define the STACK_SIZE macro. + +proc add_options_for_stack_size { flags } { + if [is-effective-target stack_size] { + set stack_size [dg-effective-target-value stack_size] + return "$flags -DSTACK_SIZE=$stack_size" + } + + return $flags +} + # Return 1 if the target provides a full C99 runtime. proc check_effective_target_c99_runtime { } { -- cgit v1.1 From 9a85b75fc414653f4a691ea57b83722489cd3d61 Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Wed, 21 Jun 2017 09:58:57 +0000 Subject: [Patch AArch64] Add initial tuning support for Cortex-A55 and Cortex-A75 This patch adds support for the ARM Cortex-A75 and Cortex-A55 processors through the -mcpu/-mtune values cortex-a55 and cortex-a75, and an ARM DynamIQ big.LITTLE configuration of these two processors through the -mcpu/-mtune value cortex-a75.cortex-a55 The ARM Cortex-A75 is ARM's latest and highest performance applications processor. For the initial tuning provided in this patch, I have chosen to share the tuning structure with its predecessor, the Cortex-A73. The ARM Cortex-A55 delivers the best combination of power efficiency and performance in its class. For the initial tuning provided in this patch, I have chosen to share the tuning structure with its predecessor, the Cortex-A53. Both Cortex-A55 and Cortex-A75 support ARMv8-A with the ARM8.1-A and ARMv8.2-A extensions, along with the cryptography extension, and the RCPC extensions from ARMv8.3-A. This is reflected in the patch, -mcpu=cortex-a75 is treated as equivalent to passing -mtune=cortex-a75 -march=armv8.2-a+rcpc . 2017-06-21 James Greenhalgh * config/aarch64/aarch64-cores.def (cortex-a55): New. (cortex-a75): Likewise. (cortex-a75.cortex-a55): Likewise. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi (-mtune): Document new values for -mtune. From-SVN: r249441 --- gcc/ChangeLog | 8 ++++++++ gcc/config/aarch64/aarch64-cores.def | 10 ++++++++++ gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/doc/invoke.texi | 14 ++++++++------ 4 files changed, 27 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 199a01f..e08150c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-06-21 James Greenhalgh + + * config/aarch64/aarch64-cores.def (cortex-a55): New. + (cortex-a75): Likewise. + (cortex-a75.cortex-a55): Likewise. + * config/aarch64/aarch64-tune.md: Regenerate. + * doc/invoke.texi (-mtune): Document new values for -mtune. + 2017-06-21 Tom de Vries * doc/sourcebuild.texi (Add Options, Features for dg-add-options): Add diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index e333d5f..0baa20c 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -80,6 +80,12 @@ AARCH64_CORE("vulcan", vulcan, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AA /* Cavium ('C') cores. */ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x43, 0x0af, -1) +/* ARMv8.2-A Architecture Processors. */ + +/* ARM ('A') cores. */ +AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC, cortexa53, 0x41, 0xd05, -1) +AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC, cortexa73, 0x41, 0xd0a, -1) + /* ARMv8-A big.LITTLE implementations. */ AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1) @@ -87,4 +93,8 @@ AARCH64_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, AARCH AARCH64_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd04), -1) AARCH64_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd03), -1) +/* ARM DynamIQ big.LITTLE configurations. */ + +AARCH64_CORE("cortex-a75.cortex-a55", cortexa75cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd0a, 0xd05), -1) + #undef AARCH64_CORE diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index 4209f67..7fcd6cb 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53" + "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 86c8d62..7e7a16a5 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14077,17 +14077,19 @@ processors implementing the target architecture. @opindex mtune Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: -@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, -@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, -@samp{xgene1}, @samp{vulcan}, @samp{thunderx}, +@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, +@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, +@samp{exynos-m1}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35}, -@samp{cortex-a73.cortex-a53}, @samp{native}. +@samp{cortex-a73.cortex-a53}, @samp{cortex-a75.cortex-a55}, +@samp{native}. The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, -@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53} -specify that GCC should tune for a big.LITTLE system. +@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}, +@samp{cortex-a75.cortex-a55} specify that GCC should tune for a +big.LITTLE system. Additionally on native AArch64 GNU/Linux systems the value @samp{native} tunes performance to the host system. This option has no effect -- cgit v1.1 From f28e54bd06f3733ff147128107a8da6d3e6d428e Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Wed, 21 Jun 2017 10:40:21 +0000 Subject: Mark symbols as constant Aarch64_legitimate_constant_p currently returns false for symbols, eventhough they are always valid constants. This means LOSYM isn't CSEd correctly. If we return true CSE works better, resulting in smaller/faster code (0.3% smaller code on SPEC2006). Avoid this for TLS symbols since their sequence is complex. gcc/ * config/aarch64/aarch64.c (aarch64_legitimate_constant_p): Return true for non-tls symbols. From-SVN: r249442 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64.c | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e08150c..1aaaf61 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-21 Wilco Dijkstra + + * config/aarch64/aarch64.c (aarch64_legitimate_constant_p): + Return true for non-tls symbols. + 2017-06-21 James Greenhalgh * config/aarch64/aarch64-cores.def (cortex-a55): New. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 04417dc..ba6b45f 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -10129,6 +10129,11 @@ aarch64_legitimate_constant_p (machine_mode mode, rtx x) && aarch64_valid_symref (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) return true; + /* Treat symbols as constants. Avoid TLS symbols as they are complex, + so spilling them is better than rematerialization. */ + if (SYMBOL_REF_P (x) && !SYMBOL_REF_TLS_MODEL (x)) + return true; + return aarch64_constant_address_p (x); } -- cgit v1.1 From dca19fe10daf00bfef714e3f9f98c63ff70c7a64 Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Wed, 21 Jun 2017 10:46:02 +0000 Subject: Improve dup pattern Improve the dup pattern to prefer vector registers. When doing a dup after a load, the register allocator thinks the costs are identical and chooses an integer load. However a dup from an integer register includes an int->fp transfer which is not modelled. Adding a '?' to the integer variant means the cost is increased slightly so we prefer using a vector register. This improves the following example: #include void f(unsigned *a, uint32x4_t *b) { b[0] = vdupq_n_u32(a[1]); b[1] = vdupq_n_u32(a[2]); } to: ldr s0, [x0, 4] dup v0.4s, v0.s[0] str q0, [x1] ldr s0, [x0, 8] dup v0.4s, v0.s[0] str q0, [x1, 16] ret gcc/ * config/aarch64/aarch64-simd.md (aarch64_simd_dup): Swap alternatives, make integer dup more expensive. From-SVN: r249443 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64-simd.md | 8 ++++---- 2 files changed, 9 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1aaaf61..1fc622b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2017-06-21 Wilco Dijkstra + * config/aarch64/aarch64-simd.md (aarch64_simd_dup): + Swap alternatives, make integer dup more expensive. + +2017-06-21 Wilco Dijkstra + * config/aarch64/aarch64.c (aarch64_legitimate_constant_p): Return true for non-tls symbols. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index e811f3e..c949465 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -44,12 +44,12 @@ (define_insn "aarch64_simd_dup" [(set (match_operand:VDQ_I 0 "register_operand" "=w, w") (vec_duplicate:VDQ_I - (match_operand: 1 "register_operand" "r, w")))] + (match_operand: 1 "register_operand" "w,?r")))] "TARGET_SIMD" "@ - dup\\t%0., %1 - dup\\t%0., %1.[0]" - [(set_attr "type" "neon_from_gp, neon_dup")] + dup\\t%0., %1.[0] + dup\\t%0., %1" + [(set_attr "type" "neon_dup, neon_from_gp")] ) (define_insn "aarch64_simd_dup" -- cgit v1.1 From 9fe9816bcd72e5ae5fe374d7483e4b5b0c618b22 Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Wed, 21 Jun 2017 10:48:51 +0000 Subject: Emit SIMD moves as mov SIMD moves are currently emitted as ORR. Change this to use the MOV pseudo instruction just like integer moves (the ARM-ARM states MOV is the preferred disassembly), improving readability of -S output. gcc/ * config/aarch64/aarch64.md (movti_aarch64): Emit mov rather than orr. (movtf_aarch64): Likewise. * config/aarch64/aarch64-simd.md (aarch64_simd_mov): Emit mov rather than orr. From-SVN: r249444 --- gcc/ChangeLog | 8 ++++++++ gcc/config/aarch64/aarch64-simd.md | 4 ++-- gcc/config/aarch64/aarch64.md | 4 ++-- 3 files changed, 12 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1fc622b..c9ee703 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2017-06-21 Wilco Dijkstra + * config/aarch64/aarch64.md (movti_aarch64): + Emit mov rather than orr. + (movtf_aarch64): Likewise. + * config/aarch64/aarch64-simd.md (aarch64_simd_mov): + Emit mov rather than orr. + +2017-06-21 Wilco Dijkstra + * config/aarch64/aarch64-simd.md (aarch64_simd_dup): Swap alternatives, make integer dup more expensive. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index c949465..264a9c0 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -105,7 +105,7 @@ { case 0: return "ldr\\t%d0, %1"; case 1: return "str\\t%d1, %0"; - case 2: return "orr\t%0., %1., %1."; + case 2: return "mov\t%0., %1."; case 3: return "umov\t%0, %1.d[0]"; case 4: return "fmov\t%d0, %1"; case 5: return "mov\t%0, %1"; @@ -136,7 +136,7 @@ case 1: return "str\\t%q1, %0"; case 2: - return "orr\t%0., %1., %1."; + return "mov\t%0., %1."; case 3: case 4: case 5: diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 1a721bf..6bdbf65 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1017,7 +1017,7 @@ # # # - orr\\t%0.16b, %1.16b, %1.16b + mov\\t%0.16b, %1.16b ldp\\t%0, %H0, %1 stp\\t%1, %H1, %0 stp\\txzr, xzr, %0 @@ -1131,7 +1131,7 @@ "TARGET_FLOAT && (register_operand (operands[0], TFmode) || aarch64_reg_or_fp_zero (operands[1], TFmode))" "@ - orr\\t%0.16b, %1.16b, %1.16b + mov\\t%0.16b, %1.16b # # # -- cgit v1.1 From d54d1fc3bcd2d3dda563f9bd95b60299bc892041 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 21 Jun 2017 12:58:00 +0200 Subject: re PR c++/81130 (ICE OpenMP shared clause in gimplify_var_or_parm_decl, at gimplify.c:2584) PR c++/81130 * gimplify.c (omp_add_variable): Don't force GOVD_SEEN for types with ctors/dtors if GOVD_SHARED is set. * testsuite/libgomp.c++/pr81130.C: New test. From-SVN: r249445 --- gcc/ChangeLog | 6 ++++++ gcc/gimplify.c | 8 +++++--- 2 files changed, 11 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c9ee703..a40820b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-21 Jakub Jelinek + + PR c++/81130 + * gimplify.c (omp_add_variable): Don't force GOVD_SEEN for types + with ctors/dtors if GOVD_SHARED is set. + 2017-06-21 Wilco Dijkstra * config/aarch64/aarch64.md (movti_aarch64): diff --git a/gcc/gimplify.c b/gcc/gimplify.c index cf82f95..13760c0 100644 --- a/gcc/gimplify.c +++ b/gcc/gimplify.c @@ -6634,9 +6634,11 @@ omp_add_variable (struct gimplify_omp_ctx *ctx, tree decl, unsigned int flags) return; /* Never elide decls whose type has TREE_ADDRESSABLE set. This means - there are constructors involved somewhere. */ - if (TREE_ADDRESSABLE (TREE_TYPE (decl)) - || TYPE_NEEDS_CONSTRUCTING (TREE_TYPE (decl))) + there are constructors involved somewhere. Exception is a shared clause, + there is nothing privatized in that case. */ + if ((flags & GOVD_SHARED) == 0 + && (TREE_ADDRESSABLE (TREE_TYPE (decl)) + || TYPE_NEEDS_CONSTRUCTING (TREE_TYPE (decl)))) flags |= GOVD_SEEN; n = splay_tree_lookup (ctx->variables, (splay_tree_key)decl); -- cgit v1.1 From ed73f46f30cabeea4de64e7cce0682a7a610ffb6 Mon Sep 17 00:00:00 2001 From: Marc Glisse Date: Wed, 21 Jun 2017 13:16:27 +0200 Subject: NOP conversions in X+CST+CST 2017-06-21 Marc Glisse gcc/ * match.pd (nop_convert): New predicate. ((A +- CST1) +- CST2): Allow some NOP conversions. gcc/testsuite/ * gcc.dg/tree-ssa/addadd.c: Un-XFAIL. * gcc.dg/tree-ssa/addadd-2.c: New file. From-SVN: r249447 --- gcc/ChangeLog | 5 +++ gcc/match.pd | 58 +++++++++++++++++++++++++++----- gcc/testsuite/ChangeLog | 5 +++ gcc/testsuite/gcc.dg/tree-ssa/addadd-2.c | 15 +++++++++ gcc/testsuite/gcc.dg/tree-ssa/addadd.c | 6 ++-- 5 files changed, 77 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/addadd-2.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a40820b..65ff235 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-21 Marc Glisse + + * match.pd (nop_convert): New predicate. + ((A +- CST1) +- CST2): Allow some NOP conversions. + 2017-06-21 Jakub Jelinek PR c++/81130 diff --git a/gcc/match.pd b/gcc/match.pd index 244e9eb..7bd2676 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -74,6 +74,20 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (FLOOR) DEFINE_INT_AND_FLOAT_ROUND_FN (CEIL) DEFINE_INT_AND_FLOAT_ROUND_FN (ROUND) DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) + +/* As opposed to convert?, this still creates a single pattern, so + it is not a suitable replacement for convert? in all cases. */ +(match (nop_convert @0) + (convert @0) + (if (tree_nop_conversion_p (type, TREE_TYPE (@0))))) +(match (nop_convert @0) + (view_convert @0) + (if (VECTOR_TYPE_P (type) && VECTOR_TYPE_P (TREE_TYPE (@0)) + && TYPE_VECTOR_SUBPARTS (type) == TYPE_VECTOR_SUBPARTS (TREE_TYPE (@0)) + && tree_nop_conversion_p (TREE_TYPE (type), TREE_TYPE (TREE_TYPE (@0)))))) +/* This one has to be last, or it shadows the others. */ +(match (nop_convert @0) + @0) /* Simplifications of operations with one constant operand and simplifications to constants or single values. */ @@ -1296,18 +1310,44 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (minus @0 (minus @0 @1)) @1) - /* (A +- CST1) +- CST2 -> A + CST3 */ + /* (A +- CST1) +- CST2 -> A + CST3 + Use view_convert because it is safe for vectors and equivalent for + scalars. */ (for outer_op (plus minus) (for inner_op (plus minus) + neg_inner_op (minus plus) (simplify - (outer_op (inner_op @0 CONSTANT_CLASS_P@1) CONSTANT_CLASS_P@2) - /* If the constant operation overflows we cannot do the transform - as we would introduce undefined overflow, for example - with (a - 1) + INT_MIN. */ - (with { tree cst = const_binop (outer_op == inner_op - ? PLUS_EXPR : MINUS_EXPR, type, @1, @2); } - (if (cst && !TREE_OVERFLOW (cst)) - (inner_op @0 { cst; } )))))) + (outer_op (nop_convert (inner_op @0 CONSTANT_CLASS_P@1)) + CONSTANT_CLASS_P@2) + /* If one of the types wraps, use that one. */ + (if (!ANY_INTEGRAL_TYPE_P (type) || TYPE_OVERFLOW_WRAPS (type)) + (if (outer_op == PLUS_EXPR) + (plus (view_convert @0) (inner_op @2 (view_convert @1))) + (minus (view_convert @0) (neg_inner_op @2 (view_convert @1)))) + (if (!ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0)) + || TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0))) + (if (outer_op == PLUS_EXPR) + (view_convert (plus @0 (inner_op (view_convert @2) @1))) + (view_convert (minus @0 (neg_inner_op (view_convert @2) @1)))) + /* If the constant operation overflows we cannot do the transform + directly as we would introduce undefined overflow, for example + with (a - 1) + INT_MIN. */ + (if (types_match (type, @0)) + (with { tree cst = const_binop (outer_op == inner_op + ? PLUS_EXPR : MINUS_EXPR, + type, @1, @2); } + (if (cst && !TREE_OVERFLOW (cst)) + (inner_op @0 { cst; } ) + /* X+INT_MAX+1 is X-INT_MIN. */ + (if (INTEGRAL_TYPE_P (type) && cst + && wi::eq_p (cst, wi::min_value (type))) + (neg_inner_op @0 { wide_int_to_tree (type, cst); }) + /* Last resort, use some unsigned type. */ + (with { tree utype = unsigned_type_for (type); } + (view_convert (inner_op + (view_convert:utype @0) + (view_convert:utype + { drop_tree_overflow (cst); }))))))))))))) /* (CST1 - A) +- CST2 -> CST3 - A */ (for outer_op (plus minus) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a7524ac..ccfd274 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-21 Marc Glisse + + * gcc.dg/tree-ssa/addadd.c: Un-XFAIL. + * gcc.dg/tree-ssa/addadd-2.c: New file. + 2017-06-21 Tom de Vries * lib/target-supports.exp (add_options_for_stack_size): New proc. diff --git a/gcc/testsuite/gcc.dg/tree-ssa/addadd-2.c b/gcc/testsuite/gcc.dg/tree-ssa/addadd-2.c new file mode 100644 index 0000000..39aa032 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/addadd-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-optimized" } */ + +typedef int S __attribute__((vector_size(64))); +typedef unsigned U __attribute__((vector_size(64))); +void j(S*x){ + *x += __INT_MAX__; + *x += __INT_MAX__; +} +void k(S*x){ + U y = (U)(*x + __INT_MAX__); + *x = (S)(y + __INT_MAX__); +} + +/* { dg-final { scan-tree-dump-not "2147483647" "optimized" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/addadd.c b/gcc/testsuite/gcc.dg/tree-ssa/addadd.c index 669cfbc..16474db 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/addadd.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/addadd.c @@ -29,6 +29,6 @@ void j(S*x){ *x += __INT_MAX__; } -/* { dg-final { scan-tree-dump-times " \\+ 24;" 2 "optimized" { xfail *-*-* } } } */ -/* { dg-final { scan-tree-dump-times "\\(unsigned int\\)" 2 "optimized" { xfail *-*-* } } } */ -/* { dg-final { scan-tree-dump-not "2147483647" "optimized" { xfail *-*-* } } } */ +/* { dg-final { scan-tree-dump-times " \\+ 24;" 2 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\\(unsigned int\\)" 2 "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2147483647" "optimized" } } */ -- cgit v1.1 From a23ba8ccd0d3e16de01dfccf6304b9014e84f64f Mon Sep 17 00:00:00 2001 From: Marc Glisse Date: Wed, 21 Jun 2017 13:20:41 +0200 Subject: [i386] __builtin_ia32_stmxcsr could be pure 2017-06-21 Marc Glisse gcc/ * config/i386/i386.c (struct builtin_isa): New field pure_p. Reorder for compactness. (def_builtin, def_builtin2, ix86_add_new_builtins): Handle pure_p. (def_builtin_pure, def_builtin_pure2): New functions. (ix86_init_mmx_sse_builtins) [__builtin_ia32_stmxcsr]: Mark as pure. gcc/testsuite/ * gcc.target/i386/getround.c: New file. From-SVN: r249448 --- gcc/ChangeLog | 8 ++++++ gcc/config/i386/i386.c | 45 ++++++++++++++++++++++++++++---- gcc/testsuite/ChangeLog | 4 +++ gcc/testsuite/gcc.target/i386/getround.c | 14 ++++++++++ 4 files changed, 66 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/getround.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 65ff235..62f91e5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2017-06-21 Marc Glisse + * config/i386/i386.c (struct builtin_isa): New field pure_p. + Reorder for compactness. + (def_builtin, def_builtin2, ix86_add_new_builtins): Handle pure_p. + (def_builtin_pure, def_builtin_pure2): New functions. + (ix86_init_mmx_sse_builtins) [__builtin_ia32_stmxcsr]: Mark as pure. + +2017-06-21 Marc Glisse + * match.pd (nop_convert): New predicate. ((A +- CST1) +- CST2): Allow some NOP conversions. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 9f7290a..3caeeb0 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -31935,11 +31935,12 @@ static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX]; but are waiting to be built until a function is declared to use that ISA. */ struct builtin_isa { - const char *name; /* function name */ - enum ix86_builtin_func_type tcode; /* type to use in the declaration */ HOST_WIDE_INT isa; /* isa_flags this builtin is defined for */ HOST_WIDE_INT isa2; /* additional isa_flags this builtin is defined for */ - bool const_p; /* true if the declaration is constant */ + const char *name; /* function name */ + enum ix86_builtin_func_type tcode; /* type to use in the declaration */ + unsigned char const_p:1; /* true if the declaration is constant */ + unsigned char pure_p:1; /* true if the declaration has pure attribute */ bool leaf_p; /* true if the declaration has leaf attribute */ bool nothrow_p; /* true if the declaration has nothrow attribute */ bool set_and_not_built_p; @@ -32010,6 +32011,7 @@ def_builtin (HOST_WIDE_INT mask, const char *name, ix86_builtins_isa[(int) code].leaf_p = false; ix86_builtins_isa[(int) code].nothrow_p = false; ix86_builtins_isa[(int) code].const_p = false; + ix86_builtins_isa[(int) code].pure_p = false; ix86_builtins_isa[(int) code].set_and_not_built_p = true; } } @@ -32032,6 +32034,21 @@ def_builtin_const (HOST_WIDE_INT mask, const char *name, return decl; } +/* Like def_builtin, but also marks the function decl "pure". */ + +static inline tree +def_builtin_pure (HOST_WIDE_INT mask, const char *name, + enum ix86_builtin_func_type tcode, enum ix86_builtins code) +{ + tree decl = def_builtin (mask, name, tcode, code); + if (decl) + DECL_PURE_P (decl) = 1; + else + ix86_builtins_isa[(int) code].pure_p = true; + + return decl; +} + /* Like def_builtin, but for additional isa2 flags. */ static inline tree @@ -32066,6 +32083,7 @@ def_builtin2 (HOST_WIDE_INT mask, const char *name, ix86_builtins_isa[(int) code].leaf_p = false; ix86_builtins_isa[(int) code].nothrow_p = false; ix86_builtins_isa[(int) code].const_p = false; + ix86_builtins_isa[(int) code].pure_p = false; ix86_builtins_isa[(int) code].set_and_not_built_p = true; } @@ -32087,6 +32105,21 @@ def_builtin_const2 (HOST_WIDE_INT mask, const char *name, return decl; } +/* Like def_builtin, but also marks the function decl "pure". */ + +static inline tree +def_builtin_pure2 (HOST_WIDE_INT mask, const char *name, + enum ix86_builtin_func_type tcode, enum ix86_builtins code) +{ + tree decl = def_builtin2 (mask, name, tcode, code); + if (decl) + DECL_PURE_P (decl) = 1; + else + ix86_builtins_isa[(int) code].pure_p = true; + + return decl; +} + /* Add any new builtin functions for a given ISA that may not have been declared. This saves a bit of space compared to adding all of the declarations to the tree, even if we didn't use them. */ @@ -32125,6 +32158,8 @@ ix86_add_new_builtins (HOST_WIDE_INT isa, HOST_WIDE_INT isa2) ix86_builtins[i] = decl; if (ix86_builtins_isa[i].const_p) TREE_READONLY (decl) = 1; + if (ix86_builtins_isa[i].pure_p) + DECL_PURE_P (decl) = 1; if (ix86_builtins_isa[i].leaf_p) DECL_ATTRIBUTES (decl) = build_tree_list (get_identifier ("leaf"), NULL_TREE); @@ -32478,8 +32513,8 @@ ix86_init_mmx_sse_builtins (void) /* SSE */ def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", VOID_FTYPE_UNSIGNED, IX86_BUILTIN_LDMXCSR); - def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", - UNSIGNED_FTYPE_VOID, IX86_BUILTIN_STMXCSR); + def_builtin_pure (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", + UNSIGNED_FTYPE_VOID, IX86_BUILTIN_STMXCSR); /* SSE or 3DNow!A */ def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ccfd274..c9650f6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2017-06-21 Marc Glisse + * gcc.target/i386/getround.c: New file. + +2017-06-21 Marc Glisse + * gcc.dg/tree-ssa/addadd.c: Un-XFAIL. * gcc.dg/tree-ssa/addadd-2.c: New file. diff --git a/gcc/testsuite/gcc.target/i386/getround.c b/gcc/testsuite/gcc.target/i386/getround.c new file mode 100644 index 0000000..e9d43b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/getround.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O -msse" } */ + +#include + +unsigned save; + +void f(unsigned mode){ + unsigned tmp = _MM_GET_ROUNDING_MODE(); + _MM_SET_ROUNDING_MODE(mode); + save = tmp; +} + +/* { dg-final { scan-assembler-times "stmxcsr" 1 } } */ -- cgit v1.1 From ff9baa5f1c532a43d7d14a800f5a4a5c5757dca6 Mon Sep 17 00:00:00 2001 From: Pierre-Marie de Rodat Date: Wed, 21 Jun 2017 11:24:51 +0000 Subject: DWARF: make it possible to emit debug info for declarations only The DWARF back-end used to systematically ignore file-scope function and variable declarations. While this is justified in language like C/C++, where such declarations can appear in several translation units and thus bloat uselessly the debug info, this behavior is counter-productive in languages with a well-defined module system. Specifically, it prevents the description of imported entities, that belong to foreign languages, making them unavailable from debuggers. Take for instance: package C_Binding is function My_C_Function (I : Integer) return Integer; pragma Import (C, My_C_Function, "my_c_function"); end C_Binding; This makes available for Ada programs the C function "my_c_function" under the following name: C_Binding.My_C_Function. When GCC compiles it, though, it is represented as a FUNCTION_DECL node with DECL_EXTERNAL set and a null DECL_INITIAL, which used to be discarded unconditionally in the DWARF back-end. This patch moves such filter from the DWARF back-end to the relevant callers: passes.c:rest_of_decl_compilation and godump.c:go_early_global_decl. It also This patch also updates the Ada front-end to call debug hooks for functions such as in the above example, so that we do generate debugging information for them. gcc/ * dwarf2out.c (gen_decl_die): Remove the guard to skip file-scope FUNCTION_DECL declarations. (dwarf2out_early_global_decl): Remove the guard to skip FUNCTION_DECL declarations. (dwaf2out_decl): Likewise. * godump.c (go_early_global_decl): Skip call to the real debug hook for FUNCTION_DECL declarations. * passes.c (rest_of_decl_compilation): Skip call to the early_global_decl debug hook for FUNCTION_DECL declarations, unless -fdump-go-spec is passed. gcc/ada/ * gcc-interface/ada-tree.h (DECL_FUNCTION_IS_DEF): Update copyright notice. New macro. * gcc-interface/trans.c (Subprogram_Body_to_gnu): Tag the subprogram as a definition. (Compilation_Unit_to_gnu): Tag the elaboration procedure as a definition. * gcc-interface/decl.c (gnat_to_gnu_entity): Tag declarations of imported subprograms for the current compilation unit as definitions. Disable debug info for references to variables. * gcc-interface/gigi.h (create_subprog_decl): Update declaration. * gcc-interface/utils.c (gnat_pushdecl): Add external DECLs that are not built-in functions to their binding scope. (create_subprog_decl): Add a DEFINITION parameter. If it is true, tag the function as a definition. Update all callers. (gnat_write_global_declarations): Emit debug info for imported functions. Filter out external variables for which debug info is disabled. gcc/testsuite/ * gnat.dg/debug11_pkg.adb, gnat.dg/debug11_pkg.ads, gnat.dg/debug11_pkg2.ads: New testcase. From-SVN: r249449 --- gcc/ChangeLog | 13 +++++++++ gcc/ada/ChangeLog | 20 +++++++++++++ gcc/ada/gcc-interface/ada-tree.h | 7 ++++- gcc/ada/gcc-interface/decl.c | 19 ++++++++----- gcc/ada/gcc-interface/gigi.h | 5 +++- gcc/ada/gcc-interface/trans.c | 52 ++++++++++++++++++++-------------- gcc/ada/gcc-interface/utils.c | 35 +++++++++++++++++------ gcc/dwarf2out.c | 50 -------------------------------- gcc/godump.c | 3 +- gcc/passes.c | 11 +++---- gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/gnat.dg/debug11_pkg.adb | 26 +++++++++++++++++ gcc/testsuite/gnat.dg/debug11_pkg.ads | 11 +++++++ gcc/testsuite/gnat.dg/debug11_pkg2.ads | 9 ++++++ 14 files changed, 172 insertions(+), 94 deletions(-) create mode 100644 gcc/testsuite/gnat.dg/debug11_pkg.adb create mode 100644 gcc/testsuite/gnat.dg/debug11_pkg.ads create mode 100644 gcc/testsuite/gnat.dg/debug11_pkg2.ads (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 62f91e5..0926a49 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2017-06-21 Pierre-Marie de Rodat + + * dwarf2out.c (gen_decl_die): Remove the guard to skip file-scope + FUNCTION_DECL declarations. + (dwarf2out_early_global_decl): Remove the guard to skip FUNCTION_DECL + declarations. + (dwaf2out_decl): Likewise. + * godump.c (go_early_global_decl): Skip call to the real debug hook + for FUNCTION_DECL declarations. + * passes.c (rest_of_decl_compilation): Skip call to the + early_global_decl debug hook for FUNCTION_DECL declarations, unless + -fdump-go-spec is passed. + 2017-06-21 Marc Glisse * config/i386/i386.c (struct builtin_isa): New field pure_p. diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 5fb0cdf..fce09a0 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,23 @@ +2017-06-21 Pierre-Marie de Rodat + + * gcc-interface/ada-tree.h (DECL_FUNCTION_IS_DEF): Update copyright + notice. New macro. + * gcc-interface/trans.c (Subprogram_Body_to_gnu): Tag the subprogram + as a definition. + (Compilation_Unit_to_gnu): Tag the elaboration procedure as a + definition. + * gcc-interface/decl.c (gnat_to_gnu_entity): Tag declarations of + imported subprograms for the current compilation unit as + definitions. Disable debug info for references to variables. + * gcc-interface/gigi.h (create_subprog_decl): Update declaration. + * gcc-interface/utils.c (gnat_pushdecl): Add external DECLs that are + not built-in functions to their binding scope. + (create_subprog_decl): Add a DEFINITION parameter. If it is true, tag + the function as a definition. Update all callers. + (gnat_write_global_declarations): Emit debug info for imported + functions. Filter out external variables for which debug info + is disabled. + 2017-06-15 Nicolas Boulenguez PR ada/81105 diff --git a/gcc/ada/gcc-interface/ada-tree.h b/gcc/ada/gcc-interface/ada-tree.h index a3d38b1..511a0bd 100644 --- a/gcc/ada/gcc-interface/ada-tree.h +++ b/gcc/ada/gcc-interface/ada-tree.h @@ -6,7 +6,7 @@ * * * C Header File * * * - * Copyright (C) 1992-2016, Free Software Foundation, Inc. * + * Copyright (C) 1992-2017, Free Software Foundation, Inc. * * * * GNAT is free software; you can redistribute it and/or modify it under * * terms of the GNU General Public License as published by the Free Soft- * @@ -463,6 +463,11 @@ do { \ a discriminant of a discriminated type without default expression. */ #define DECL_INVARIANT_P(NODE) DECL_LANG_FLAG_4 (FIELD_DECL_CHECK (NODE)) +/* Nonzero in a FUNCTION_DECL if this is a definition, i.e. if it was created + by a call to gnat_to_gnu_entity with definition set to True. */ +#define DECL_FUNCTION_IS_DEF(NODE) \ + DECL_LANG_FLAG_4 (FUNCTION_DECL_CHECK (NODE)) + /* Nonzero in a VAR_DECL if it is a temporary created to hold the return value of a function call or 'reference to a function call. */ #define DECL_RETURN_VALUE_P(NODE) DECL_LANG_FLAG_5 (VAR_DECL_CHECK (NODE)) diff --git a/gcc/ada/gcc-interface/decl.c b/gcc/ada/gcc-interface/decl.c index eab244e..83b9d07 100644 --- a/gcc/ada/gcc-interface/decl.c +++ b/gcc/ada/gcc-interface/decl.c @@ -1392,7 +1392,8 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition) = create_var_decl (create_concat_name (gnat_entity, "ALIGN"), NULL_TREE, gnu_new_type, NULL_TREE, false, false, false, false, false, - true, debug_info_p, NULL, gnat_entity); + true, debug_info_p && definition, NULL, + gnat_entity); /* Initialize the aligned field if we have an initializer. */ if (gnu_expr) @@ -1441,7 +1442,8 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition) NULL_TREE, gnu_type, gnu_expr, const_flag, Is_Public (gnat_entity), imported_p || !definition, static_flag, - volatile_flag, true, debug_info_p, + volatile_flag, true, + debug_info_p && definition, NULL, gnat_entity); gnu_expr = build_unary_op (ADDR_EXPR, NULL_TREE, gnu_unc_var); TREE_CONSTANT (gnu_expr) = 1; @@ -1492,8 +1494,9 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition) = create_var_decl (gnu_entity_name, gnu_ext_name, gnu_type, gnu_expr, const_flag, Is_Public (gnat_entity), imported_p || !definition, static_flag, - volatile_flag, artificial_p, debug_info_p, - attr_list, gnat_entity, !renamed_obj); + volatile_flag, artificial_p, + debug_info_p && definition, attr_list, + gnat_entity, !renamed_obj); DECL_BY_REF_P (gnu_decl) = used_by_ref; DECL_POINTS_TO_READONLY_P (gnu_decl) = used_by_ref && inner_const_flag; DECL_CAN_NEVER_BE_NULL_P (gnu_decl) = Can_Never_Be_Null (gnat_entity); @@ -1545,8 +1548,8 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition) = create_var_decl (gnu_entity_name, gnu_ext_name, gnu_type, gnu_expr, true, Is_Public (gnat_entity), !definition, static_flag, volatile_flag, - artificial_p, debug_info_p, attr_list, - gnat_entity, false); + artificial_p, debug_info_p && definition, + attr_list, gnat_entity, false); SET_DECL_CONST_CORRESPONDING_VAR (gnu_decl, gnu_corr_var); } @@ -4083,7 +4086,9 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, bool definition) gnu_type, gnu_param_list, inline_status, public_flag, extern_flag, artificial_p, - debug_info_p, attr_list, gnat_entity); + debug_info_p, + definition && imported_p, attr_list, + gnat_entity); DECL_STUBBED_P (gnu_decl) = (Convention (gnat_entity) == Convention_Stubbed); diff --git a/gcc/ada/gcc-interface/gigi.h b/gcc/ada/gcc-interface/gigi.h index b1fb34a..0e25b61 100644 --- a/gcc/ada/gcc-interface/gigi.h +++ b/gcc/ada/gcc-interface/gigi.h @@ -720,6 +720,8 @@ extern tree create_label_decl (tree name, Node_Id gnat_node); DEBUG_INFO_P is true if we need to write debug information for it. + DEFINITION is true if the subprogram is to be considered as a definition. + ATTR_LIST is the list of attributes to be attached to the subprogram. GNAT_NODE is used for the position of the decl. */ @@ -728,7 +730,8 @@ extern tree create_subprog_decl (tree name, tree asm_name, tree type, enum inline_status_t inline_status, bool public_flag, bool extern_flag, bool artificial_p, bool debug_info_p, - struct attrib *attr_list, Node_Id gnat_node); + bool definition, struct attrib *attr_list, + Node_Id gnat_node); /* Given a subprogram declaration DECL, its assembler name and its type, finish constructing the subprogram declaration from ASM_NAME and TYPE. */ diff --git a/gcc/ada/gcc-interface/trans.c b/gcc/ada/gcc-interface/trans.c index 2542626..79d0995 100644 --- a/gcc/ada/gcc-interface/trans.c +++ b/gcc/ada/gcc-interface/trans.c @@ -398,7 +398,7 @@ gigi (Node_Id gnat_root, = create_subprog_decl (get_identifier ("__gnat_malloc"), NULL_TREE, ftype, NULL_TREE, is_disabled, true, true, true, false, - NULL, Empty); + false, NULL, Empty); DECL_IS_MALLOC (malloc_decl) = 1; ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE); @@ -406,7 +406,7 @@ gigi (Node_Id gnat_root, = create_subprog_decl (get_identifier ("__gnat_free"), NULL_TREE, ftype, NULL_TREE, is_disabled, true, true, true, false, - NULL, Empty); + false, NULL, Empty); ftype = build_function_type_list (ptr_type_node, ptr_type_node, sizetype, NULL_TREE); @@ -414,7 +414,7 @@ gigi (Node_Id gnat_root, = create_subprog_decl (get_identifier ("__gnat_realloc"), NULL_TREE, ftype, NULL_TREE, is_disabled, true, true, true, false, - NULL, Empty); + false, NULL, Empty); /* This is used for 64-bit multiplication with overflow checking. */ int64_type = gnat_type_for_size (64, 0); @@ -423,7 +423,7 @@ gigi (Node_Id gnat_root, build_function_type_list (int64_type, int64_type, int64_type, NULL_TREE), NULL_TREE, is_disabled, true, true, true, false, - NULL, Empty); + false, NULL, Empty); /* Name of the _Parent field in tagged record types. */ parent_name_id = get_identifier (Get_Name_String (Name_uParent)); @@ -446,21 +446,21 @@ gigi (Node_Id gnat_root, = create_subprog_decl (get_identifier ("system__soft_links__get_jmpbuf_address_soft"), NULL_TREE, build_function_type_list (jmpbuf_ptr_type, NULL_TREE), - NULL_TREE, is_disabled, true, true, true, false, NULL, Empty); + NULL_TREE, is_disabled, true, true, true, false, false, NULL, Empty); set_jmpbuf_decl = create_subprog_decl (get_identifier ("system__soft_links__set_jmpbuf_address_soft"), NULL_TREE, build_function_type_list (void_type_node, jmpbuf_ptr_type, NULL_TREE), - NULL_TREE, is_disabled, true, true, true, false, NULL, Empty); + NULL_TREE, is_disabled, true, true, true, false, false, NULL, Empty); get_excptr_decl = create_subprog_decl (get_identifier ("system__soft_links__get_gnat_exception"), NULL_TREE, build_function_type_list (build_pointer_type (except_type_node), NULL_TREE), - NULL_TREE, is_disabled, true, true, true, false, NULL, Empty); + NULL_TREE, is_disabled, true, true, true, false, false, NULL, Empty); not_handled_by_others_decl = get_identifier ("not_handled_by_others"); for (t = TYPE_FIELDS (except_type_node); t; t = DECL_CHAIN (t)) @@ -478,7 +478,7 @@ gigi (Node_Id gnat_root, (get_identifier ("__builtin_setjmp"), NULL_TREE, build_function_type_list (integer_type_node, jmpbuf_ptr_type, NULL_TREE), - NULL_TREE, is_disabled, true, true, true, false, NULL, Empty); + NULL_TREE, is_disabled, true, true, true, false, false, NULL, Empty); DECL_BUILT_IN_CLASS (setjmp_decl) = BUILT_IN_NORMAL; DECL_FUNCTION_CODE (setjmp_decl) = BUILT_IN_SETJMP; @@ -488,7 +488,7 @@ gigi (Node_Id gnat_root, = create_subprog_decl (get_identifier ("__builtin_update_setjmp_buf"), NULL_TREE, build_function_type_list (void_type_node, jmpbuf_ptr_type, NULL_TREE), - NULL_TREE, is_disabled, true, true, true, false, NULL, Empty); + NULL_TREE, is_disabled, true, true, true, false, false, NULL, Empty); DECL_BUILT_IN_CLASS (update_setjmp_buf_decl) = BUILT_IN_NORMAL; DECL_FUNCTION_CODE (update_setjmp_buf_decl) = BUILT_IN_UPDATE_SETJMP_BUF; @@ -500,14 +500,14 @@ gigi (Node_Id gnat_root, raise_nodefer_decl = create_subprog_decl (get_identifier ("__gnat_raise_nodefer_with_msg"), NULL_TREE, ftype, - NULL_TREE, is_disabled, true, true, true, false, NULL, Empty); + NULL_TREE, is_disabled, true, true, true, false, false, NULL, Empty); set_exception_parameter_decl = create_subprog_decl (get_identifier ("__gnat_set_exception_parameter"), NULL_TREE, build_function_type_list (void_type_node, ptr_type_node, ptr_type_node, NULL_TREE), - NULL_TREE, is_disabled, true, true, true, false, NULL, Empty); + NULL_TREE, is_disabled, true, true, true, false, false, NULL, Empty); /* Hooks to call when entering/leaving an exception handler. */ ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE); @@ -515,26 +515,30 @@ gigi (Node_Id gnat_root, begin_handler_decl = create_subprog_decl (get_identifier ("__gnat_begin_handler"), NULL_TREE, ftype, NULL_TREE, - is_disabled, true, true, true, false, NULL, Empty); + is_disabled, true, true, true, false, false, NULL, + Empty); /* __gnat_begin_handler is a dummy procedure. */ TREE_NOTHROW (begin_handler_decl) = 1; end_handler_decl = create_subprog_decl (get_identifier ("__gnat_end_handler"), NULL_TREE, ftype, NULL_TREE, - is_disabled, true, true, true, false, NULL, Empty); + is_disabled, true, true, true, false, false, NULL, + Empty); unhandled_except_decl = create_subprog_decl (get_identifier ("__gnat_unhandled_except_handler"), NULL_TREE, ftype, NULL_TREE, - is_disabled, true, true, true, false, NULL, Empty); + is_disabled, true, true, true, false, false, NULL, + Empty); /* Indicate that it never returns. */ ftype = build_qualified_type (ftype, TYPE_QUAL_VOLATILE); reraise_zcx_decl = create_subprog_decl (get_identifier ("__gnat_reraise_zcx"), NULL_TREE, ftype, NULL_TREE, - is_disabled, true, true, true, false, NULL, Empty); + is_disabled, true, true, true, false, false, NULL, + Empty); /* Dummy objects to materialize "others" and "all others" in the exception tables. These are exported by a-exexpr-gcc.adb, so see this unit for @@ -573,7 +577,8 @@ gigi (Node_Id gnat_root, tree decl = create_subprog_decl (get_identifier ("__gnat_last_chance_handler"), NULL_TREE, ftype, - NULL_TREE, is_disabled, true, true, true, false, NULL, Empty); + NULL_TREE, is_disabled, true, true, true, false, false, NULL, + Empty); for (i = 0; i < (int) ARRAY_SIZE (gnat_raise_decls); i++) gnat_raise_decls[i] = decl; } @@ -739,7 +744,7 @@ build_raise_check (int check, enum exception_info_kind kind) result = create_subprog_decl (get_identifier (Name_Buffer), NULL_TREE, ftype, NULL_TREE, is_disabled, true, true, true, false, - NULL, Empty); + false, NULL, Empty); return result; } @@ -3745,6 +3750,7 @@ Subprogram_Body_to_gnu (Node_Id gnat_node) = gnat_to_gnu_entity (gnat_subprog_id, NULL_TREE, Acts_As_Spec (gnat_node) && !present_gnu_tree (gnat_subprog_id)); + DECL_FUNCTION_IS_DEF (gnu_subprog_decl) = true; gnu_result_decl = DECL_RESULT (gnu_subprog_decl); gnu_subprog_type = TREE_TYPE (gnu_subprog_decl); gnu_cico_list = TYPE_CI_CO_LIST (gnu_subprog_type); @@ -5417,12 +5423,15 @@ Compilation_Unit_to_gnu (Node_Id gnat_node) const Entity_Id gnat_unit_entity = Defining_Entity (gnat_unit); Entity_Id gnat_entity; Node_Id gnat_pragma; - /* Make the decl for the elaboration procedure. */ + /* Make the decl for the elaboration procedure. Emit debug info for it, so + that users can break into their elaboration code in debuggers. Kludge: + don't consider it as a definition so that we have a line map for its body, + but no subprogram description in debug info. */ tree gnu_elab_proc_decl = create_subprog_decl (create_concat_name (gnat_unit_entity, body_p ? "elabb" : "elabs"), NULL_TREE, void_ftype, NULL_TREE, - is_disabled, true, false, true, true, NULL, gnat_unit); + is_disabled, true, false, true, true, false, NULL, gnat_unit); struct elab_info *info; vec_safe_push (gnu_elab_proc_stack, gnu_elab_proc_decl); @@ -6453,7 +6462,7 @@ gnat_to_gnu (Node_Id gnat_node) gnu_prefix = gnat_to_gnu (gnat_prefix); gnu_prefix = maybe_implicit_deref (gnu_prefix); } - + gnu_result = build_component_ref (gnu_prefix, gnu_field, (Nkind (Parent (gnat_node)) @@ -6484,7 +6493,8 @@ gnat_to_gnu (Node_Id gnat_node) (Entity (Prefix (gnat_node)), attr == Attr_Elab_Body ? "elabb" : "elabs"), NULL_TREE, void_ftype, NULL_TREE, is_disabled, - true, true, true, true, NULL, gnat_node); + true, true, true, true, false, NULL, + gnat_node); gnu_result = Attribute_to_gnu (gnat_node, &gnu_result_type, attr); } diff --git a/gcc/ada/gcc-interface/utils.c b/gcc/ada/gcc-interface/utils.c index b8c5d3d..9e65657 100644 --- a/gcc/ada/gcc-interface/utils.c +++ b/gcc/ada/gcc-interface/utils.c @@ -763,11 +763,13 @@ gnat_pushdecl (tree decl, Node_Id gnat_node) if (!(TREE_CODE (decl) == TYPE_DECL && TREE_CODE (TREE_TYPE (decl)) == UNCONSTRAINED_ARRAY_TYPE)) { - if (DECL_EXTERNAL (decl)) - { - if (TREE_CODE (decl) == FUNCTION_DECL && DECL_BUILT_IN (decl)) - vec_safe_push (builtin_decls, decl); - } + /* External declarations must go to the binding level they belong to. + This will make corresponding imported entities are available in the + debugger at the proper time. */ + if (DECL_EXTERNAL (decl) + && TREE_CODE (decl) == FUNCTION_DECL + && DECL_BUILT_IN (decl)) + vec_safe_push (builtin_decls, decl); else if (global_bindings_p ()) vec_safe_push (global_decls, decl); else @@ -3189,6 +3191,8 @@ create_label_decl (tree name, Node_Id gnat_node) DEBUG_INFO_P is true if we need to write debug information for it. + DEFINITION is true if the subprogram is to be considered as a definition. + ATTR_LIST is the list of attributes to be attached to the subprogram. GNAT_NODE is used for the position of the decl. */ @@ -3197,7 +3201,8 @@ tree create_subprog_decl (tree name, tree asm_name, tree type, tree param_decl_list, enum inline_status_t inline_status, bool public_flag, bool extern_flag, bool artificial_p, bool debug_info_p, - struct attrib *attr_list, Node_Id gnat_node) + bool definition, struct attrib *attr_list, + Node_Id gnat_node) { tree subprog_decl = build_decl (input_location, FUNCTION_DECL, name, type); DECL_ARGUMENTS (subprog_decl) = param_decl_list; @@ -3208,6 +3213,8 @@ create_subprog_decl (tree name, tree asm_name, tree type, tree param_decl_list, if (!debug_info_p) DECL_IGNORED_P (subprog_decl) = 1; + if (definition) + DECL_FUNCTION_IS_DEF (subprog_decl) = 1; switch (inline_status) { @@ -5523,10 +5530,22 @@ gnat_write_global_declarations (void) if (TREE_CODE (iter) == TYPE_DECL && !DECL_IGNORED_P (iter)) debug_hooks->type_decl (iter, false); + /* Output imported functions. */ + FOR_EACH_VEC_SAFE_ELT (global_decls, i, iter) + if (TREE_CODE (iter) == FUNCTION_DECL + && DECL_EXTERNAL (iter) + && DECL_INITIAL (iter) == NULL + && !DECL_IGNORED_P (iter) + && DECL_FUNCTION_IS_DEF (iter)) + debug_hooks->early_global_decl (iter); + /* Then output the global variables. We need to do that after the debug - information for global types is emitted so that they are finalized. */ + information for global types is emitted so that they are finalized. Skip + external global variables, unless we need to emit debug info for them: + this is useful for imported variables, for instance. */ FOR_EACH_VEC_SAFE_ELT (global_decls, i, iter) - if (TREE_CODE (iter) == VAR_DECL) + if (TREE_CODE (iter) == VAR_DECL + && (!DECL_EXTERNAL (iter) || !DECL_IGNORED_P (iter))) rest_of_decl_compilation (iter, true, 0); /* Output the imported modules/declarations. In GNAT, these are only diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index 92444e3..c277d27 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -25289,14 +25289,6 @@ gen_decl_die (tree decl, tree origin, struct vlr_context *ctx, break; case FUNCTION_DECL: - /* Don't output any DIEs to represent mere function declarations, - unless they are class members or explicit block externs. */ - if (DECL_INITIAL (decl_or_origin) == NULL_TREE - && DECL_FILE_SCOPE_P (decl_or_origin) - && (current_function_decl == NULL_TREE - || DECL_ARTIFICIAL (decl_or_origin))) - break; - #if 0 /* FIXME */ /* This doesn't work because the C frontend sets DECL_ABSTRACT_ORIGIN @@ -25501,11 +25493,6 @@ dwarf2out_early_global_decl (tree decl) tree save_fndecl = current_function_decl; if (TREE_CODE (decl) == FUNCTION_DECL) { - /* No cfun means the symbol has no body, so there's nothing - to emit. */ - if (!DECL_STRUCT_FUNCTION (decl)) - goto early_decl_exit; - /* For nested functions, make sure we have DIEs for the parents first so that all nested DIEs are generated at the proper scope in the first shot. */ @@ -25522,7 +25509,6 @@ dwarf2out_early_global_decl (tree decl) if (TREE_CODE (decl) == FUNCTION_DECL) current_function_decl = save_fndecl; } - early_decl_exit: symtab->global_info_ready = save; } @@ -25761,42 +25747,6 @@ dwarf2out_decl (tree decl) return; case FUNCTION_DECL: - /* What we would really like to do here is to filter out all mere - file-scope declarations of file-scope functions which are never - referenced later within this translation unit (and keep all of ones - that *are* referenced later on) but we aren't clairvoyant, so we have - no idea which functions will be referenced in the future (i.e. later - on within the current translation unit). So here we just ignore all - file-scope function declarations which are not also definitions. If - and when the debugger needs to know something about these functions, - it will have to hunt around and find the DWARF information associated - with the definition of the function. - - We can't just check DECL_EXTERNAL to find out which FUNCTION_DECL - nodes represent definitions and which ones represent mere - declarations. We have to check DECL_INITIAL instead. That's because - the C front-end supports some weird semantics for "extern inline" - function definitions. These can get inlined within the current - translation unit (and thus, we need to generate Dwarf info for their - abstract instances so that the Dwarf info for the concrete inlined - instances can have something to refer to) but the compiler never - generates any out-of-lines instances of such things (despite the fact - that they *are* definitions). - - The important point is that the C front-end marks these "extern - inline" functions as DECL_EXTERNAL, but we need to generate DWARF for - them anyway. Note that the C++ front-end also plays some similar games - for inline function definitions appearing within include files which - also contain `#pragma interface' pragmas. - - If we are called from dwarf2out_abstract_function output a DIE - anyway. We can end up here this way with early inlining and LTO - where the inlined function is output in a different LTRANS unit - or not at all. */ - if (DECL_INITIAL (decl) == NULL_TREE - && ! DECL_ABSTRACT_P (decl)) - return; - /* If we're a nested function, initially use a parent of NULL; if we're a plain function, this will be fixed up in decls_for_scope. If we're a method, it will be ignored, since we already have a DIE. */ diff --git a/gcc/godump.c b/gcc/godump.c index 4884dee..3e90531 100644 --- a/gcc/godump.c +++ b/gcc/godump.c @@ -504,7 +504,8 @@ static void go_early_global_decl (tree decl) { go_decl (decl); - real_debug_hooks->early_global_decl (decl); + if (TREE_CODE (decl) != FUNCTION_DECL || DECL_STRUCT_FUNCTION (decl) != NULL) + real_debug_hooks->early_global_decl (decl); } /* A global variable decl. */ diff --git a/gcc/passes.c b/gcc/passes.c index 64493ba..374f6f7 100644 --- a/gcc/passes.c +++ b/gcc/passes.c @@ -262,17 +262,18 @@ rest_of_decl_compilation (tree decl, finalize_compilation_unit (and by consequence, locally scoped symbols), or by rest_of_type_compilation below. - Also, pick up function prototypes, which will be mostly ignored - by the different early_global_decl() hooks, but will at least be - used by Go's hijack of the debug_hooks to implement - -fdump-go-spec. */ + For Go's hijack of the debug_hooks to implement -fdump-go-spec, pick up + function prototypes. Go's debug_hooks will not forward them to the + wrapped hooks. */ if (!in_lto_p && (TREE_CODE (decl) != FUNCTION_DECL /* This will pick up function prototypes with no bodies, which are not visible in finalize_compilation_unit() while iterating with FOR_EACH_*_FUNCTION through the symbol table. */ - || !DECL_SAVED_TREE (decl)) + || (flag_dump_go_spec != NULL + && !DECL_SAVED_TREE (decl) + && DECL_STRUCT_FUNCTION (decl) == NULL)) /* We need to check both decl_function_context and current_function_decl here to make sure local extern diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c9650f6..a31bba4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-21 Pierre-Marie de Rodat + + * gnat.dg/debug11_pkg.adb, gnat.dg/debug11_pkg.ads, + gnat.dg/debug11_pkg2.ads: New testcase. + 2017-06-21 Marc Glisse * gcc.target/i386/getround.c: New file. diff --git a/gcc/testsuite/gnat.dg/debug11_pkg.adb b/gcc/testsuite/gnat.dg/debug11_pkg.adb new file mode 100644 index 0000000..336f2fd --- /dev/null +++ b/gcc/testsuite/gnat.dg/debug11_pkg.adb @@ -0,0 +1,26 @@ +-- { dg-options "-cargs -g -dA -margs" } +-- { dg-final { scan-assembler "local_imported_func" } } +-- { dg-final { scan-assembler "local_imported_var" } } +-- { dg-final { scan-assembler "global_imported_func" } } +-- { dg-final { scan-assembler "global_imported_var" } } +-- { dg-final { scan-assembler-not "foreign_imported_func" } } +-- { dg-final { scan-assembler-not "foreign_imported_var" } } + +with Debug11_Pkg2; + +package body Debug11_Pkg is + + procedure Dummy is + Local_Imported_Var : Integer; + pragma Import (C, Local_Imported_Var, "imported_var"); + + function Local_Imported_Func return Integer; + pragma Import (C, Local_Imported_Func, "imported_func"); + begin + Local_Imported_Var := Local_Imported_Func; + Global_Imported_Var := Global_Imported_Func; + Debug11_Pkg2.Foreign_Imported_Var := + Debug11_Pkg2.Foreign_Imported_Func; + end Dummy; + +end Debug11_Pkg; diff --git a/gcc/testsuite/gnat.dg/debug11_pkg.ads b/gcc/testsuite/gnat.dg/debug11_pkg.ads new file mode 100644 index 0000000..dc45310 --- /dev/null +++ b/gcc/testsuite/gnat.dg/debug11_pkg.ads @@ -0,0 +1,11 @@ +package Debug11_Pkg is + + Global_Imported_Var : Integer; + pragma Import (C, Global_Imported_Var, "imported_var"); + + function Global_Imported_Func return Integer; + pragma Import (C, Global_Imported_Func, "imported_func"); + + procedure Dummy; + +end Debug11_Pkg; diff --git a/gcc/testsuite/gnat.dg/debug11_pkg2.ads b/gcc/testsuite/gnat.dg/debug11_pkg2.ads new file mode 100644 index 0000000..350f51c --- /dev/null +++ b/gcc/testsuite/gnat.dg/debug11_pkg2.ads @@ -0,0 +1,9 @@ +package Debug11_Pkg2 is + + Foreign_Imported_Var : Integer; + pragma Import (C, Foreign_Imported_Var, "imported_var"); + + function Foreign_Imported_Func return Integer; + pragma Import (C, Foreign_Imported_Func, "imported_func"); + +end Debug11_Pkg2; -- cgit v1.1 From e59a1c22fb249388e82b4fd004f33615abe36d2e Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Wed, 21 Jun 2017 14:51:46 +0200 Subject: Make early return predictor more precise. 2017-06-21 Martin Liska PR tree-optimization/79489 * gimplify.c (maybe_add_early_return_predict_stmt): New function. (gimplify_return_expr): Call the function. * predict.c (tree_estimate_probability_bb): Remove handling of early return. * predict.def: Update comment about early return predictor. * gimple-predict.h (is_gimple_predict): New function. * predict.def: Change default value of early return to 66. * tree-tailcall.c (find_tail_calls): Skip GIMPLE_PREDICT statements. * passes.def: Put pass_strip_predict_hints to the beginning of IPA passes. From-SVN: r249450 --- gcc/ChangeLog | 16 ++++++++++++++++ gcc/gimple-low.c | 2 ++ gcc/gimple-predict.h | 8 ++++++++ gcc/gimplify.c | 16 ++++++++++++++++ gcc/passes.def | 1 + gcc/predict.c | 41 ----------------------------------------- gcc/predict.def | 15 +++------------ gcc/tree-tailcall.c | 2 ++ 8 files changed, 48 insertions(+), 53 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0926a49..12d0ee8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2017-06-21 Martin Liska + + PR tree-optimization/79489 + * gimplify.c (maybe_add_early_return_predict_stmt): New + function. + (gimplify_return_expr): Call the function. + * predict.c (tree_estimate_probability_bb): Remove handling + of early return. + * predict.def: Update comment about early return predictor. + * gimple-predict.h (is_gimple_predict): New function. + * predict.def: Change default value of early return to 66. + * tree-tailcall.c (find_tail_calls): Skip GIMPLE_PREDICT + statements. + * passes.def: Put pass_strip_predict_hints to the beginning of + IPA passes. + 2017-06-21 Pierre-Marie de Rodat * dwarf2out.c (gen_decl_die): Remove the guard to skip file-scope diff --git a/gcc/gimple-low.c b/gcc/gimple-low.c index 619b9d7..4ea6c35 100644 --- a/gcc/gimple-low.c +++ b/gcc/gimple-low.c @@ -30,6 +30,8 @@ along with GCC; see the file COPYING3. If not see #include "calls.h" #include "gimple-iterator.h" #include "gimple-low.h" +#include "predict.h" +#include "gimple-predict.h" /* The differences between High GIMPLE and Low GIMPLE are the following: diff --git a/gcc/gimple-predict.h b/gcc/gimple-predict.h index ba58e12..0e6c2e1 100644 --- a/gcc/gimple-predict.h +++ b/gcc/gimple-predict.h @@ -80,4 +80,12 @@ gimple_build_predict (enum br_predictor predictor, enum prediction outcome) return p; } +/* Return true if GS is a GIMPLE_PREDICT statement. */ + +static inline bool +is_gimple_predict (const gimple *gs) +{ + return gimple_code (gs) == GIMPLE_PREDICT; +} + #endif /* GCC_GIMPLE_PREDICT_H */ diff --git a/gcc/gimplify.c b/gcc/gimplify.c index 13760c0..c645bce 100644 --- a/gcc/gimplify.c +++ b/gcc/gimplify.c @@ -1428,6 +1428,20 @@ gimplify_bind_expr (tree *expr_p, gimple_seq *pre_p) return GS_ALL_DONE; } +/* Maybe add early return predict statement to PRE_P sequence. */ + +static void +maybe_add_early_return_predict_stmt (gimple_seq *pre_p) +{ + /* If we are not in a conditional context, add PREDICT statement. */ + if (gimple_conditional_context ()) + { + gimple *predict = gimple_build_predict (PRED_TREE_EARLY_RETURN, + NOT_TAKEN); + gimplify_seq_add_stmt (pre_p, predict); + } +} + /* Gimplify a RETURN_EXPR. If the expression to be returned is not a GIMPLE value, it is assigned to a new temporary and the statement is re-written to return the temporary. @@ -1458,6 +1472,7 @@ gimplify_return_expr (tree stmt, gimple_seq *pre_p) || TREE_CODE (ret_expr) == RESULT_DECL || ret_expr == error_mark_node) { + maybe_add_early_return_predict_stmt (pre_p); greturn *ret = gimple_build_return (ret_expr); gimple_set_no_warning (ret, TREE_NO_WARNING (stmt)); gimplify_seq_add_stmt (pre_p, ret); @@ -1525,6 +1540,7 @@ gimplify_return_expr (tree stmt, gimple_seq *pre_p) gimplify_and_add (TREE_OPERAND (stmt, 0), pre_p); + maybe_add_early_return_predict_stmt (pre_p); ret = gimple_build_return (result); gimple_set_no_warning (ret, TREE_NO_WARNING (stmt)); gimplify_seq_add_stmt (pre_p, ret); diff --git a/gcc/passes.def b/gcc/passes.def index c14f6b9..316e19d 100644 --- a/gcc/passes.def +++ b/gcc/passes.def @@ -107,6 +107,7 @@ along with GCC; see the file COPYING3. If not see early optimizations again. It is thus good idea to do this late. */ NEXT_PASS (pass_split_functions); + NEXT_PASS (pass_strip_predict_hints); POP_INSERT_PASSES () NEXT_PASS (pass_release_ssa_names); NEXT_PASS (pass_rebuild_cgraph_edges); diff --git a/gcc/predict.c b/gcc/predict.c index 60d1a09..790be9f 100644 --- a/gcc/predict.c +++ b/gcc/predict.c @@ -2739,7 +2739,6 @@ tree_estimate_probability_bb (basic_block bb, bool local_only) { edge e; edge_iterator ei; - gimple *last; FOR_EACH_EDGE (e, ei, bb->succs) { @@ -2766,46 +2765,6 @@ tree_estimate_probability_bb (basic_block bb, bool local_only) } } - /* Predict early returns to be probable, as we've already taken - care for error returns and other cases are often used for - fast paths through function. - - Since we've already removed the return statements, we are - looking for CFG like: - - if (conditional) - { - .. - goto return_block - } - some other blocks - return_block: - return_stmt. */ - if (e->dest != bb->next_bb - && e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun) - && single_succ_p (e->dest) - && single_succ_edge (e->dest)->dest == EXIT_BLOCK_PTR_FOR_FN (cfun) - && (last = last_stmt (e->dest)) != NULL - && gimple_code (last) == GIMPLE_RETURN) - { - edge e1; - edge_iterator ei1; - - if (single_succ_p (bb)) - { - FOR_EACH_EDGE (e1, ei1, bb->preds) - if (!predicted_by_p (e1->src, PRED_NULL_RETURN) - && !predicted_by_p (e1->src, PRED_CONST_RETURN) - && !predicted_by_p (e1->src, PRED_NEGATIVE_RETURN)) - predict_edge_def (e1, PRED_TREE_EARLY_RETURN, NOT_TAKEN); - } - else - if (!predicted_by_p (e->src, PRED_NULL_RETURN) - && !predicted_by_p (e->src, PRED_CONST_RETURN) - && !predicted_by_p (e->src, PRED_NEGATIVE_RETURN)) - predict_edge_def (e, PRED_TREE_EARLY_RETURN, NOT_TAKEN); - } - /* Look for block we are guarding (ie we dominate it, but it doesn't postdominate us). */ if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun) && e->dest != bb diff --git a/gcc/predict.def b/gcc/predict.def index fcda6c4..f7b2bf7 100644 --- a/gcc/predict.def +++ b/gcc/predict.def @@ -128,18 +128,9 @@ DEF_PREDICTOR (PRED_POLYMORPHIC_CALL, "polymorphic call", HITRATE (59), 0) indefinitely. */ DEF_PREDICTOR (PRED_RECURSIVE_CALL, "recursive call", HITRATE (75), 0) -/* Branch causing function to terminate is probably not taken. - FIXME: early return currently predicts code: - int foo (int a) - { - if (a) - bar(); - else - bar2(); - } - even though there is no return statement involved. We probably want to track - this from FE or retire the predictor. */ -DEF_PREDICTOR (PRED_TREE_EARLY_RETURN, "early return (on trees)", HITRATE (54), 0) +/* Branch causing function to terminate is probably not taken. */ +DEF_PREDICTOR (PRED_TREE_EARLY_RETURN, "early return (on trees)", HITRATE (66), + 0) /* Branch containing goto is probably not taken. FIXME: Currently not used. */ diff --git a/gcc/tree-tailcall.c b/gcc/tree-tailcall.c index b705338..6aa9a56 100644 --- a/gcc/tree-tailcall.c +++ b/gcc/tree-tailcall.c @@ -421,6 +421,7 @@ find_tail_calls (basic_block bb, struct tailcall **ret) if (gimple_code (stmt) == GIMPLE_LABEL || gimple_code (stmt) == GIMPLE_RETURN || gimple_code (stmt) == GIMPLE_NOP + || gimple_code (stmt) == GIMPLE_PREDICT || gimple_clobber_p (stmt) || is_gimple_debug (stmt)) continue; @@ -555,6 +556,7 @@ find_tail_calls (basic_block bb, struct tailcall **ret) if (gimple_code (stmt) == GIMPLE_LABEL || gimple_code (stmt) == GIMPLE_NOP + || gimple_code (stmt) == GIMPLE_PREDICT || gimple_clobber_p (stmt) || is_gimple_debug (stmt)) continue; -- cgit v1.1 From 93c18375823fdd0e384f673f75e39136719135dd Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Wed, 21 Jun 2017 14:52:14 +0200 Subject: Rework cold and hot label attributes in predict.c. 2017-06-21 Martin Liska * gimplify.c (gimplify_label_expr): Insert GIMPLE_PREDICT statements on cold and hot labels. * predict.c (tree_estimate_probability_bb): Remove the prediction from this place. 2017-06-21 Martin Liska * gcc.dg/tree-ssa/attr-hotcold-2.c: Update scanned patterns. From-SVN: r249451 --- gcc/ChangeLog | 7 +++++++ gcc/gimplify.c | 10 +++++++++- gcc/predict.c | 23 ----------------------- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/tree-ssa/attr-hotcold-2.c | 4 ++-- 5 files changed, 22 insertions(+), 26 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 12d0ee8..2308d35 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2017-06-21 Martin Liska + * gimplify.c (gimplify_label_expr): Insert GIMPLE_PREDICT + statements on cold and hot labels. + * predict.c (tree_estimate_probability_bb): Remove the + prediction from this place. + +2017-06-21 Martin Liska + PR tree-optimization/79489 * gimplify.c (maybe_add_early_return_predict_stmt): New function. diff --git a/gcc/gimplify.c b/gcc/gimplify.c index c645bce..641a821 100644 --- a/gcc/gimplify.c +++ b/gcc/gimplify.c @@ -2357,10 +2357,18 @@ gimplify_label_expr (tree *expr_p, gimple_seq *pre_p) gcc_assert (decl_function_context (LABEL_EXPR_LABEL (*expr_p)) == current_function_decl); - glabel *label_stmt = gimple_build_label (LABEL_EXPR_LABEL (*expr_p)); + tree label = LABEL_EXPR_LABEL (*expr_p); + glabel *label_stmt = gimple_build_label (label); gimple_set_location (label_stmt, EXPR_LOCATION (*expr_p)); gimplify_seq_add_stmt (pre_p, label_stmt); + if (lookup_attribute ("cold", DECL_ATTRIBUTES (label))) + gimple_seq_add_stmt (pre_p, gimple_build_predict (PRED_COLD_LABEL, + NOT_TAKEN)); + else if (lookup_attribute ("hot", DECL_ATTRIBUTES (label))) + gimple_seq_add_stmt (pre_p, gimple_build_predict (PRED_HOT_LABEL, + TAKEN)); + return GS_ALL_DONE; } diff --git a/gcc/predict.c b/gcc/predict.c index 790be9f..44151bc 100644 --- a/gcc/predict.c +++ b/gcc/predict.c @@ -2742,29 +2742,6 @@ tree_estimate_probability_bb (basic_block bb, bool local_only) FOR_EACH_EDGE (e, ei, bb->succs) { - /* Predict edges to user labels with attributes. */ - if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun)) - { - gimple_stmt_iterator gi; - for (gi = gsi_start_bb (e->dest); !gsi_end_p (gi); gsi_next (&gi)) - { - glabel *label_stmt = dyn_cast (gsi_stmt (gi)); - tree decl; - - if (!label_stmt) - break; - decl = gimple_label_label (label_stmt); - if (DECL_ARTIFICIAL (decl)) - continue; - - /* Finally, we have a user-defined label. */ - if (lookup_attribute ("cold", DECL_ATTRIBUTES (decl))) - predict_edge_def (e, PRED_COLD_LABEL, NOT_TAKEN); - else if (lookup_attribute ("hot", DECL_ATTRIBUTES (decl))) - predict_edge_def (e, PRED_HOT_LABEL, TAKEN); - } - } - /* Look for block we are guarding (ie we dominate it, but it doesn't postdominate us). */ if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun) && e->dest != bb diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a31bba4..b45fc57 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-21 Martin Liska + + * gcc.dg/tree-ssa/attr-hotcold-2.c: Update scanned patterns. + 2017-06-21 Pierre-Marie de Rodat * gnat.dg/debug11_pkg.adb, gnat.dg/debug11_pkg.ads, diff --git a/gcc/testsuite/gcc.dg/tree-ssa/attr-hotcold-2.c b/gcc/testsuite/gcc.dg/tree-ssa/attr-hotcold-2.c index f7a5098..184dd10 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/attr-hotcold-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/attr-hotcold-2.c @@ -20,9 +20,9 @@ void f(int x, int y) /* { dg-final { scan-tree-dump-times "hot label heuristics" 1 "profile_estimate" } } */ /* { dg-final { scan-tree-dump-times "cold label heuristics" 1 "profile_estimate" } } */ -/* { dg-final { scan-tree-dump-times "block 4, loop depth 0, freq \[1-4\]\[^0-9\]" 3 "profile_estimate" } } */ +/* { dg-final { scan-tree-dump "A \\\[0\\\..*\\\]" "profile_estimate" } } */ /* Note: we're attempting to match some number > 6000, i.e. > 60%. The exact number ought to be tweekable without having to juggle the testcase around too much. */ -/* { dg-final { scan-tree-dump-times "block 5, loop depth 0, freq \[6-9\]\[0-9\]\[0-9\]\[0-9\]" 3 "profile_estimate" } } */ +/* { dg-final { scan-tree-dump "B \\\[\[6-9\]\[0-9\]\\\..*\\\]" "profile_estimate" } } */ -- cgit v1.1 From 5433db459e647106ea021ef2039dfa363b2b9e6e Mon Sep 17 00:00:00 2001 From: Tom de Vries Date: Wed, 21 Jun 2017 14:14:16 +0000 Subject: Fix warning in gcc.dg/tree-prof/comp-goto-1.c 2017-06-21 Tom de Vries * gcc.dg/tree-prof/comp-goto-1.c: Fix 'return type defaults to int' warning. From-SVN: r249452 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/tree-prof/comp-goto-1.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b45fc57..c527d1c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-21 Tom de Vries + + * gcc.dg/tree-prof/comp-goto-1.c: Fix 'return type defaults to int' + warning. + 2017-06-21 Martin Liska * gcc.dg/tree-ssa/attr-hotcold-2.c: Update scanned patterns. diff --git a/gcc/testsuite/gcc.dg/tree-prof/comp-goto-1.c b/gcc/testsuite/gcc.dg/tree-prof/comp-goto-1.c index bb1d120..fe768f9 100644 --- a/gcc/testsuite/gcc.dg/tree-prof/comp-goto-1.c +++ b/gcc/testsuite/gcc.dg/tree-prof/comp-goto-1.c @@ -165,5 +165,5 @@ main () exit (0); } #else -main(){ exit (0); } +int main(){ exit (0); } #endif -- cgit v1.1 From 27d33d3ef065fd94ec004bf87380e122e9dfebb8 Mon Sep 17 00:00:00 2001 From: Tom de Vries Date: Wed, 21 Jun 2017 14:14:31 +0000 Subject: Support dg-add-options in profopt.exp 2017-06-21 Tom de Vries * lib/profopt.exp (profopt-get-options): Support dg-add-options. From-SVN: r249453 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/lib/profopt.exp | 1 + 2 files changed, 5 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c527d1c..e05fb26 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2017-06-21 Tom de Vries + * lib/profopt.exp (profopt-get-options): Support dg-add-options. + +2017-06-21 Tom de Vries + * gcc.dg/tree-prof/comp-goto-1.c: Fix 'return type defaults to int' warning. diff --git a/gcc/testsuite/lib/profopt.exp b/gcc/testsuite/lib/profopt.exp index 6519c44..0ea8e7a 100644 --- a/gcc/testsuite/lib/profopt.exp +++ b/gcc/testsuite/lib/profopt.exp @@ -249,6 +249,7 @@ proc profopt-get-options { src } { set cmd [lindex $op 0] if { ![string compare "dg-options" $cmd] \ || ![string compare "dg-additional-options" $cmd] \ + || ![string compare "dg-add-options" $cmd] \ || ![string compare "dg-skip-if" $cmd] \ || ![string compare "dg-final-generate" $cmd] \ || ![string compare "dg-final-use" $cmd] \ -- cgit v1.1 From 5e9d501c7db51bb2fdbb3678db4f74ee6b73e3b8 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 21 Jun 2017 16:55:40 +0200 Subject: * g++.dg/cpp0x/constexpr-cast.C: Adjust dg-error for ILP32. From-SVN: r249455 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/g++.dg/cpp0x/constexpr-cast.C | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e05fb26..a23b04c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-21 Jakub Jelinek + + * g++.dg/cpp0x/constexpr-cast.C: Adjust dg-error for ILP32. + 2017-06-21 Tom de Vries * lib/profopt.exp (profopt-get-options): Support dg-add-options. diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-cast.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-cast.C index a50e27b..e23d0d4 100644 --- a/gcc/testsuite/g++.dg/cpp0x/constexpr-cast.C +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-cast.C @@ -7,7 +7,7 @@ int i; // The following is accepted due to bug 49171. constexpr void *q = reinterpret_cast(&i); // { dg-error "" "bug c++/49171" { xfail *-*-* } } -constexpr void *r0 = reinterpret_cast(1); // { dg-error "not a constant expression" } +constexpr void *r0 = reinterpret_cast(1); // { dg-error "not a constant expression|reinterpret_cast from integer to pointer" } constexpr void *r1 = reinterpret_cast(sizeof 'x'); // { dg-error ".reinterpret_cast\\(1\[ul\]\*\\). is not a constant expression" } template -- cgit v1.1 From 2c0113fd8ac55b9cf93c3a1c660264112edb0462 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Wed, 21 Jun 2017 15:26:21 +0000 Subject: [AArch64] Fix atomic_cmp_exchange_zero_reg_1.c with +lse * config/aarch64/atomics.md (aarch64_compare_and_swap_lse, SHORT): Relax operand 3 to aarch64_reg_or_zero and constraint to Z. (aarch64_compare_and_swap_lse, GPI): Likewise. (aarch64_atomic_cas, SHORT): Likewise for operand 2. (aarch64_atomic_cas, GPI): Likewise. From-SVN: r249457 --- gcc/ChangeLog | 8 ++++++++ gcc/config/aarch64/atomics.md | 8 ++++---- 2 files changed, 12 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2308d35..276a8d2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-06-21 Kyrylo Tkachov + + * config/aarch64/atomics.md (aarch64_compare_and_swap_lse, + SHORT): Relax operand 3 to aarch64_reg_or_zero and constraint to Z. + (aarch64_compare_and_swap_lse, GPI): Likewise. + (aarch64_atomic_cas, SHORT): Likewise for operand 2. + (aarch64_atomic_cas, GPI): Likewise. + 2017-06-21 Martin Liska * gimplify.c (gimplify_label_expr): Insert GIMPLE_PREDICT diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 27fc193..32b7169 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -94,7 +94,7 @@ (set (match_dup 1) (unspec_volatile:SHORT [(match_operand:SI 2 "aarch64_plus_operand" "rI") ;; expected - (match_operand:SHORT 3 "register_operand" "r") ;; desired + (match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ") ;; desired (match_operand:SI 4 "const_int_operand") ;; is_weak (match_operand:SI 5 "const_int_operand") ;; mod_s (match_operand:SI 6 "const_int_operand")] ;; mod_f @@ -119,7 +119,7 @@ (set (match_dup 1) (unspec_volatile:GPI [(match_operand:GPI 2 "aarch64_plus_operand" "rI") ;; expect - (match_operand:GPI 3 "register_operand" "r") ;; desired + (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ") ;; desired (match_operand:SI 4 "const_int_operand") ;; is_weak (match_operand:SI 5 "const_int_operand") ;; mod_s (match_operand:SI 6 "const_int_operand")] ;; mod_f @@ -616,7 +616,7 @@ (set (match_dup 1) (unspec_volatile:SHORT [(match_dup 0) - (match_operand:SHORT 2 "register_operand" "r") ;; value. + (match_operand:SHORT 2 "aarch64_reg_or_zero" "rZ") ;; value. (match_operand:SI 3 "const_int_operand" "")] ;; model. UNSPECV_ATOMIC_CAS))] "TARGET_LSE && reload_completed" @@ -640,7 +640,7 @@ (set (match_dup 1) (unspec_volatile:GPI [(match_dup 0) - (match_operand:GPI 2 "register_operand" "r") ;; value. + (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ") ;; value. (match_operand:SI 3 "const_int_operand" "")] ;; model. UNSPECV_ATOMIC_CAS))] "TARGET_LSE && reload_completed" -- cgit v1.1 From f1e247d0181d3b055b0d9435a7f65e88792e7812 Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Wed, 21 Jun 2017 15:35:14 +0000 Subject: aarch64-cores.def (thunderxt88p1): Use thunderxt88 tunings. 2017-06-21 Andrew Pinski * config/aarch64/aarch64-cores.def (thunderxt88p1): Use thunderxt88 tunings. (thunderxt88): Likewise. * config/aarch64/aarch64.c (thunderxt88_prefetch_tune): New variable. (thunderx_prefetch_tune): New variable. (thunderx2t99_prefetch_tune): Update for the correct values. (thunderxt88_tunings): New variable. (thunderx_tunings): Use thunderx_prefetch_tune instead of generic_prefetch_tune. (thunderx2t99_tunings): Use AUTOPREFETCHER_WEAK. From-SVN: r249458 --- gcc/ChangeLog | 13 +++++++++ gcc/config/aarch64/aarch64-cores.def | 4 +-- gcc/config/aarch64/aarch64.c | 53 ++++++++++++++++++++++++++++++++---- 3 files changed, 63 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 276a8d2..1b41a7f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2017-06-21 Andrew Pinski + + * config/aarch64/aarch64-cores.def (thunderxt88p1): Use thunderxt88 + tunings. + (thunderxt88): Likewise. + * config/aarch64/aarch64.c (thunderxt88_prefetch_tune): New variable. + (thunderx_prefetch_tune): New variable. + (thunderx2t99_prefetch_tune): Update for the correct values. + (thunderxt88_tunings): New variable. + (thunderx_tunings): Use thunderx_prefetch_tune instead of + generic_prefetch_tune. + (thunderx2t99_tunings): Use AUTOPREFETCHER_WEAK. + 2017-06-21 Kyrylo Tkachov * config/aarch64/atomics.md (aarch64_compare_and_swap_lse, diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 0baa20c..f8342ca 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -56,8 +56,8 @@ AARCH64_CORE("cortex-a73", cortexa73, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AA AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a0, -1) /* Do not swap around "thunderxt88p1" and "thunderxt88", this order is required to handle variant correctly. */ -AARCH64_CORE("thunderxt88p1", thunderxt88p1, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a1, 0) -AARCH64_CORE("thunderxt88", thunderxt88, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a1, -1) +AARCH64_CORE("thunderxt88p1", thunderxt88p1, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderxt88, 0x43, 0x0a1, 0) +AARCH64_CORE("thunderxt88", thunderxt88, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderxt88, 0x43, 0x0a1, -1) AARCH64_CORE("thunderxt81", thunderxt81, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a2, -1) AARCH64_CORE("thunderxt83", thunderxt83, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, 0x43, 0x0a3, -1) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ba6b45f..97937dd 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -554,12 +554,30 @@ static const cpu_prefetch_tune qdf24xx_prefetch_tune = 3 /* default_opt_level */ }; +static const cpu_prefetch_tune thunderxt88_prefetch_tune = +{ + 8, /* num_slots */ + 32, /* l1_cache_size */ + 128, /* l1_cache_line_size */ + 16*1024, /* l2_cache_size */ + 3 /* default_opt_level */ +}; + +static const cpu_prefetch_tune thunderx_prefetch_tune = +{ + 8, /* num_slots */ + 32, /* l1_cache_size */ + 128, /* l1_cache_line_size */ + -1, /* l2_cache_size */ + -1 /* default_opt_level */ +}; + static const cpu_prefetch_tune thunderx2t99_prefetch_tune = { - 0, /* num_slots */ - -1, /* l1_cache_size */ + 8, /* num_slots */ + 32, /* l1_cache_size */ 64, /* l1_cache_line_size */ - -1, /* l2_cache_size */ + 256, /* l2_cache_size */ -1 /* default_opt_level */ }; @@ -745,6 +763,31 @@ static const struct tune_params exynosm1_tunings = &exynosm1_prefetch_tune }; +static const struct tune_params thunderxt88_tunings = +{ + &thunderx_extra_costs, + &generic_addrcost_table, + &thunderx_regmove_cost, + &thunderx_vector_cost, + &generic_branch_cost, + &generic_approx_modes, + 6, /* memmov_cost */ + 2, /* issue_rate */ + AARCH64_FUSE_CMP_BRANCH, /* fusible_ops */ + 8, /* function_align. */ + 8, /* jump_align. */ + 8, /* loop_align. */ + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ + (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW), /* tune_flags. */ + &thunderxt88_prefetch_tune +}; + static const struct tune_params thunderx_tunings = { &thunderx_extra_costs, @@ -767,7 +810,7 @@ static const struct tune_params thunderx_tunings = 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW), /* tune_flags. */ - &generic_prefetch_tune + &thunderx_prefetch_tune }; static const struct tune_params xgene1_tunings = @@ -841,7 +884,7 @@ static const struct tune_params thunderx2t99_tunings = 2, /* min_div_recip_mul_sf. */ 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ - tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ + tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ &thunderx2t99_prefetch_tune }; -- cgit v1.1 From b10f10092ebcee637d04788f2ac8b72644dbba34 Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Wed, 21 Jun 2017 15:58:12 +0000 Subject: aarch64-cost-tables.h (thunderx_extra_costs): Increment Arith_shift and Arith_shift_reg by 1. 2017-06-21 Andrew Pinski * config/aarch64/aarch64-cost-tables.h (thunderx_extra_costs): Increment Arith_shift and Arith_shift_reg by 1. * config/aarch64/aarch64-tuning-flags.def (cheap_shift_extend): New tuning flag. * config/aarch64/aarch64.c (thunderx_tunings): Enable AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND. (aarch64_strip_extend): Add new argument and test for it. (aarch64_cheap_mult_shift_p): New function. (aarch64_rtx_mult_cost): Call aarch64_cheap_mult_shift_p and don't add a cost if it is true. Update calls to aarch64_strip_extend. (aarch64_rtx_costs): Update calls to aarch64_strip_extend. From-SVN: r249459 --- gcc/ChangeLog | 15 ++++++++ gcc/config/aarch64/aarch64-cost-tables.h | 4 +- gcc/config/aarch64/aarch64-tuning-flags.def | 6 +++ gcc/config/aarch64/aarch64.c | 60 ++++++++++++++++++++++++----- 4 files changed, 73 insertions(+), 12 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1b41a7f..ea97b0b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,20 @@ 2017-06-21 Andrew Pinski + * config/aarch64/aarch64-cost-tables.h (thunderx_extra_costs): + Increment Arith_shift and Arith_shift_reg by 1. + * config/aarch64/aarch64-tuning-flags.def (cheap_shift_extend): + New tuning flag. + * config/aarch64/aarch64.c (thunderx_tunings): Enable + AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND. + (aarch64_strip_extend): Add new argument and test for it. + (aarch64_cheap_mult_shift_p): New function. + (aarch64_rtx_mult_cost): Call aarch64_cheap_mult_shift_p and don't + add a cost if it is true. + Update calls to aarch64_strip_extend. + (aarch64_rtx_costs): Update calls to aarch64_strip_extend. + +2017-06-21 Andrew Pinski + * config/aarch64/aarch64-cores.def (thunderxt88p1): Use thunderxt88 tunings. (thunderxt88): Likewise. diff --git a/gcc/config/aarch64/aarch64-cost-tables.h b/gcc/config/aarch64/aarch64-cost-tables.h index 070c083..5d149bd 100644 --- a/gcc/config/aarch64/aarch64-cost-tables.h +++ b/gcc/config/aarch64/aarch64-cost-tables.h @@ -136,8 +136,8 @@ const struct cpu_cost_table thunderx_extra_costs = 0, /* Logical. */ 0, /* Shift. */ 0, /* Shift_reg. */ - COSTS_N_INSNS (1), /* Arith_shift. */ - COSTS_N_INSNS (1), /* Arith_shift_reg. */ + COSTS_N_INSNS (1)+1, /* Arith_shift. */ + COSTS_N_INSNS (1)+1, /* Arith_shift_reg. */ COSTS_N_INSNS (1), /* UNUSED: Log_shift. */ COSTS_N_INSNS (1), /* UNUSED: Log_shift_reg. */ 0, /* Extend. */ diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def index 9f980e3..f48642c 100644 --- a/gcc/config/aarch64/aarch64-tuning-flags.def +++ b/gcc/config/aarch64/aarch64-tuning-flags.def @@ -35,4 +35,10 @@ two load/stores are not at least 8 byte aligned don't create load/store pairs. */ AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW) +/* Some of the optional shift to some arthematic instructions are + considered cheap. Logical shift left <=4 with or without a + zero extend are considered cheap. Sign extend; non logical shift left + are not considered cheap. */ +AARCH64_EXTRA_TUNING_OPTION ("cheap_shift_extend", CHEAP_SHIFT_EXTEND) + #undef AARCH64_EXTRA_TUNING_OPTION diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 97937dd..3364a02 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -809,7 +809,8 @@ static const struct tune_params thunderx_tunings = 2, /* min_div_recip_mul_df. */ 0, /* max_case_values. */ tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */ - (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW), /* tune_flags. */ + (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW + | AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND), /* tune_flags. */ &thunderx_prefetch_tune }; @@ -6120,9 +6121,10 @@ aarch64_strip_shift (rtx x) /* Helper function for rtx cost calculation. Strip an extend expression from X. Returns the inner operand if successful, or the original expression on failure. We deal with a number of possible - canonicalization variations here. */ + canonicalization variations here. If STRIP_SHIFT is true, then + we can strip off a shift also. */ static rtx -aarch64_strip_extend (rtx x) +aarch64_strip_extend (rtx x, bool strip_shift) { rtx op = x; @@ -6146,7 +6148,8 @@ aarch64_strip_extend (rtx x) /* Now handle extended register, as this may also have an optional left shift by 1..4. */ - if (GET_CODE (op) == ASHIFT + if (strip_shift + && GET_CODE (op) == ASHIFT && CONST_INT_P (XEXP (op, 1)) && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) <= 4) op = XEXP (op, 0); @@ -6170,6 +6173,39 @@ aarch64_shift_p (enum rtx_code code) return code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT; } + +/* Return true iff X is a cheap shift without a sign extend. */ + +static bool +aarch64_cheap_mult_shift_p (rtx x) +{ + rtx op0, op1; + + op0 = XEXP (x, 0); + op1 = XEXP (x, 1); + + if (!(aarch64_tune_params.extra_tuning_flags + & AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND)) + return false; + + if (GET_CODE (op0) == SIGN_EXTEND) + return false; + + if (GET_CODE (x) == ASHIFT && CONST_INT_P (op1) + && UINTVAL (op1) <= 4) + return true; + + if (GET_CODE (x) != MULT || !CONST_INT_P (op1)) + return false; + + HOST_WIDE_INT l2 = exact_log2 (INTVAL (op1)); + + if (l2 > 0 && l2 <= 4) + return true; + + return false; +} + /* Helper function for rtx cost calculation. Calculate the cost of a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx. Return the calculated cost of the expression, recursing manually in to @@ -6207,7 +6243,11 @@ aarch64_rtx_mult_cost (rtx x, enum rtx_code code, int outer, bool speed) { if (compound_p) { - if (REG_P (op1)) + /* If the shift is considered cheap, + then don't add any cost. */ + if (aarch64_cheap_mult_shift_p (x)) + ; + else if (REG_P (op1)) /* ARITH + shift-by-register. */ cost += extra_cost->alu.arith_shift_reg; else if (is_extend) @@ -6225,7 +6265,7 @@ aarch64_rtx_mult_cost (rtx x, enum rtx_code code, int outer, bool speed) } /* Strip extends as we will have costed them in the case above. */ if (is_extend) - op0 = aarch64_strip_extend (op0); + op0 = aarch64_strip_extend (op0, true); cost += rtx_cost (op0, VOIDmode, code, 0, speed); @@ -7069,13 +7109,13 @@ cost_minus: if (speed) *cost += extra_cost->alu.extend_arith; - op1 = aarch64_strip_extend (op1); + op1 = aarch64_strip_extend (op1, true); *cost += rtx_cost (op1, VOIDmode, (enum rtx_code) GET_CODE (op1), 0, speed); return true; } - rtx new_op1 = aarch64_strip_extend (op1); + rtx new_op1 = aarch64_strip_extend (op1, false); /* Cost this as an FMA-alike operation. */ if ((GET_CODE (new_op1) == MULT @@ -7148,7 +7188,7 @@ cost_plus: if (speed) *cost += extra_cost->alu.extend_arith; - op0 = aarch64_strip_extend (op0); + op0 = aarch64_strip_extend (op0, true); *cost += rtx_cost (op0, VOIDmode, (enum rtx_code) GET_CODE (op0), 0, speed); return true; @@ -7156,7 +7196,7 @@ cost_plus: /* Strip any extend, leave shifts behind as we will cost them through mult_cost. */ - new_op0 = aarch64_strip_extend (op0); + new_op0 = aarch64_strip_extend (op0, false); if (GET_CODE (new_op0) == MULT || aarch64_shift_p (GET_CODE (new_op0))) -- cgit v1.1 From 113459fad35faf22bcc72cee950e8f2ae573eb6f Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Wed, 21 Jun 2017 16:11:36 +0000 Subject: C++: Add fix-it hints for -Wold-style-cast gcc/cp/ChangeLog: * parser.c (get_cast_suggestion): New function. (maybe_add_cast_fixit): New function. (cp_parser_cast_expression): Capture the location of the closing parenthesis. Call maybe_add_cast_fixit when emitting warnings about old-style casts. gcc/testsuite/ChangeLog: * g++.dg/other/old-style-cast-fixits.C: New test case. From-SVN: r249461 --- gcc/cp/ChangeLog | 8 ++ gcc/cp/parser.c | 94 ++++++++++++++++++++- gcc/testsuite/ChangeLog | 4 + gcc/testsuite/g++.dg/other/old-style-cast-fixits.C | 95 ++++++++++++++++++++++ 4 files changed, 198 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/g++.dg/other/old-style-cast-fixits.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 01230c0..7d50a0b 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,11 @@ +2017-06-21 David Malcolm + + * parser.c (get_cast_suggestion): New function. + (maybe_add_cast_fixit): New function. + (cp_parser_cast_expression): Capture the location of the closing + parenthesis. Call maybe_add_cast_fixit when emitting warnings + about old-style casts. + 2017-06-20 Jason Merrill PR c++/80972 - C++17 ICE with attribute packed. diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index 4adf9aa..37f9154 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -8636,6 +8636,85 @@ cp_parser_tokens_start_cast_expression (cp_parser *parser) } } +/* Try to find a legal C++-style cast to DST_TYPE for ORIG_EXPR, trying them + in the order: const_cast, static_cast, reinterpret_cast. + + Don't suggest dynamic_cast. + + Return the first legal cast kind found, or NULL otherwise. */ + +static const char * +get_cast_suggestion (tree dst_type, tree orig_expr) +{ + tree trial; + + /* Reuse the parser logic by attempting to build the various kinds of + cast, with "complain" disabled. + Identify the first such cast that is valid. */ + + /* Don't attempt to run such logic within template processing. */ + if (processing_template_decl) + return NULL; + + /* First try const_cast. */ + trial = build_const_cast (dst_type, orig_expr, tf_none); + if (trial != error_mark_node) + return "const_cast"; + + /* If that fails, try static_cast. */ + trial = build_static_cast (dst_type, orig_expr, tf_none); + if (trial != error_mark_node) + return "static_cast"; + + /* Finally, try reinterpret_cast. */ + trial = build_reinterpret_cast (dst_type, orig_expr, tf_none); + if (trial != error_mark_node) + return "reinterpret_cast"; + + /* No such cast possible. */ + return NULL; +} + +/* If -Wold-style-cast is enabled, add fix-its to RICHLOC, + suggesting how to convert a C-style cast of the form: + + (DST_TYPE)ORIG_EXPR + + to a C++-style cast. + + The primary range of RICHLOC is asssumed to be that of the original + expression. OPEN_PAREN_LOC and CLOSE_PAREN_LOC give the locations + of the parens in the C-style cast. */ + +static void +maybe_add_cast_fixit (rich_location *rich_loc, location_t open_paren_loc, + location_t close_paren_loc, tree orig_expr, + tree dst_type) +{ + /* This function is non-trivial, so bail out now if the warning isn't + going to be emitted. */ + if (!warn_old_style_cast) + return; + + /* Try to find a legal C++ cast, trying them in order: + const_cast, static_cast, reinterpret_cast. */ + const char *cast_suggestion = get_cast_suggestion (dst_type, orig_expr); + if (!cast_suggestion) + return; + + /* Replace the open paren with "CAST_SUGGESTION<". */ + pretty_printer pp; + pp_printf (&pp, "%s<", cast_suggestion); + rich_loc->add_fixit_replace (open_paren_loc, pp_formatted_text (&pp)); + + /* Replace the close paren with "> (". */ + rich_loc->add_fixit_replace (close_paren_loc, "> ("); + + /* Add a closing paren after the expr (the primary range of RICH_LOC). */ + rich_loc->add_fixit_insert_after (")"); +} + + /* Parse a cast-expression. cast-expression: @@ -8671,6 +8750,7 @@ cp_parser_cast_expression (cp_parser *parser, bool address_p, bool cast_p, /* Consume the `('. */ cp_token *open_paren = cp_lexer_consume_token (parser->lexer); location_t open_paren_loc = open_paren->location; + location_t close_paren_loc = UNKNOWN_LOCATION; /* A very tricky bit is that `(struct S) { 3 }' is a compound-literal (which we permit in C++ as an extension). @@ -8733,7 +8813,10 @@ cp_parser_cast_expression (cp_parser *parser, bool address_p, bool cast_p, /* Look for the type-id. */ type = cp_parser_type_id (parser); /* Look for the closing `)'. */ - cp_parser_require (parser, CPP_CLOSE_PAREN, RT_CLOSE_PAREN); + cp_token *close_paren + = cp_parser_require (parser, CPP_CLOSE_PAREN, RT_CLOSE_PAREN); + if (close_paren) + close_paren_loc = close_paren->location; parser->in_type_id_in_expr_p = saved_in_type_id_in_expr_p; } @@ -8763,8 +8846,13 @@ cp_parser_cast_expression (cp_parser *parser, bool address_p, bool cast_p, && !in_system_header_at (input_location) && !VOID_TYPE_P (type) && current_lang_name != lang_name_c) - warning (OPT_Wold_style_cast, - "use of old-style cast to %qT", type); + { + gcc_rich_location rich_loc (input_location); + maybe_add_cast_fixit (&rich_loc, open_paren_loc, close_paren_loc, + expr, type); + warning_at_rich_loc (&rich_loc, OPT_Wold_style_cast, + "use of old-style cast to %qT", type); + } /* Only type conversions to integral or enumeration types can be used in constant-expressions. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a23b04c..446e234 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-21 David Malcolm + + * g++.dg/other/old-style-cast-fixits.C: New test case. + 2017-06-21 Jakub Jelinek * g++.dg/cpp0x/constexpr-cast.C: Adjust dg-error for ILP32. diff --git a/gcc/testsuite/g++.dg/other/old-style-cast-fixits.C b/gcc/testsuite/g++.dg/other/old-style-cast-fixits.C new file mode 100644 index 0000000..a10b623 --- /dev/null +++ b/gcc/testsuite/g++.dg/other/old-style-cast-fixits.C @@ -0,0 +1,95 @@ +// { dg-options "-Wold-style-cast -fdiagnostics-show-caret" } + +struct foo {}; +struct bar { const foo *field; }; + +void test_1 (void *ptr) +{ + foo *f = (foo *)ptr; // { dg-warning "old-style cast" } + /* { dg-begin-multiline-output "" } + foo *f = (foo *)ptr; + ^~~ + ---------- + static_cast (ptr) + { dg-end-multiline-output "" } */ +} + +void test_2 (const foo *ptr) +{ + foo *f = (foo *)ptr; // { dg-warning "old-style cast" } + /* { dg-begin-multiline-output "" } + foo *f = (foo *)ptr; + ^~~ + ---------- + const_cast (ptr) + { dg-end-multiline-output "" } */ +} + +void test_3 (bar *ptr) +{ + foo *f = (foo *)ptr; // { dg-warning "old-style cast" } + /* { dg-begin-multiline-output "" } + foo *f = (foo *)ptr; + ^~~ + ---------- + reinterpret_cast (ptr) + { dg-end-multiline-output "" } */ +} + +void test_4 (bar *ptr) +{ + foo *f = (foo *)ptr->field; // { dg-warning "old-style cast" } + /* { dg-begin-multiline-output "" } + foo *f = (foo *)ptr->field; + ^~~~~ + ----------------- + const_cast (ptr->field) + { dg-end-multiline-output "" } */ +} + +void test_5 () +{ + bar b_inst; + foo *f = (foo *)&b_inst; // { dg-warning "old-style cast" } + /* { dg-begin-multiline-output "" } + foo *f = (foo *)&b_inst; + ^~~~~~ + -------------- + reinterpret_cast (&b_inst) + { dg-end-multiline-output "" } */ +} + +/* We don't offer suggestions for templates. */ + +template +void test_6 (void *ptr) +{ + foo *f = (foo *)ptr; // { dg-warning "old-style cast" } + /* { dg-begin-multiline-output "" } + foo *f = (foo *)ptr; + ^~~ + { dg-end-multiline-output "" } */ +} + +/* We don't offer suggestions where a single C++-style cast can't be + used. */ + +void test_7 (const void *ptr) +{ + foo *f = (foo *)ptr; // { dg-warning "old-style cast" } + /* { dg-begin-multiline-output "" } + foo *f = (foo *)ptr; + ^~~ + { dg-end-multiline-output "" } */ +} + +/* Likewise, no single C++-style cast is usable here. */ + +void test_8 (const bar &b_inst) +{ + foo *f = (foo *)&b_inst; // { dg-warning "old-style cast" } + /* { dg-begin-multiline-output "" } + foo *f = (foo *)&b_inst; + ^~~~~~ + { dg-end-multiline-output "" } */ +} -- cgit v1.1 From cb8d1b01b3a2198c67d04a3a077bc7c55aaaa31c Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 21 Jun 2017 20:30:32 +0200 Subject: re PR c++/81154 (OpenMP with shared variable in a template class crash) PR c++/81154 * semantics.c (handle_omp_array_sections_1, finish_omp_clauses): Complain about t not being a variable if t is OVERLOAD even when processing_template_decl. * g++.dg/gomp/pr81154.C: New test. From-SVN: r249467 --- gcc/cp/ChangeLog | 7 +++++ gcc/cp/semantics.c | 14 ++++----- gcc/testsuite/ChangeLog | 5 ++++ gcc/testsuite/g++.dg/gomp/pr81154.C | 57 +++++++++++++++++++++++++++++++++++++ 4 files changed, 76 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/g++.dg/gomp/pr81154.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 7d50a0b..c11cbe4 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,10 @@ +2017-06-21 Jakub Jelinek + + PR c++/81154 + * semantics.c (handle_omp_array_sections_1, finish_omp_clauses): + Complain about t not being a variable if t is OVERLOAD even + when processing_template_decl. + 2017-06-21 David Malcolm * parser.c (get_cast_suggestion): New function. diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c index 5fe772a..7ecc632 100644 --- a/gcc/cp/semantics.c +++ b/gcc/cp/semantics.c @@ -4589,7 +4589,7 @@ handle_omp_array_sections_1 (tree c, tree t, vec &types, } if (!VAR_P (t) && TREE_CODE (t) != PARM_DECL) { - if (processing_template_decl) + if (processing_template_decl && TREE_CODE (t) != OVERLOAD) return NULL_TREE; if (DECL_P (t)) error_at (OMP_CLAUSE_LOCATION (c), @@ -6109,7 +6109,7 @@ finish_omp_clauses (tree clauses, enum c_omp_region_type ort) if (!VAR_P (t) && TREE_CODE (t) != PARM_DECL && (!field_ok || TREE_CODE (t) != FIELD_DECL)) { - if (processing_template_decl) + if (processing_template_decl && TREE_CODE (t) != OVERLOAD) break; if (DECL_P (t)) error ("%qD is not a variable in clause %qs", t, @@ -6181,7 +6181,7 @@ finish_omp_clauses (tree clauses, enum c_omp_region_type ort) && ((ort & C_ORT_OMP_DECLARE_SIMD) != C_ORT_OMP || TREE_CODE (t) != FIELD_DECL)) { - if (processing_template_decl) + if (processing_template_decl && TREE_CODE (t) != OVERLOAD) break; if (DECL_P (t)) error ("%qD is not a variable in clause %", t); @@ -6224,7 +6224,7 @@ finish_omp_clauses (tree clauses, enum c_omp_region_type ort) && ((ort & C_ORT_OMP_DECLARE_SIMD) != C_ORT_OMP || TREE_CODE (t) != FIELD_DECL)) { - if (processing_template_decl) + if (processing_template_decl && TREE_CODE (t) != OVERLOAD) break; if (DECL_P (t)) error ("%qD is not a variable in clause %", t); @@ -6587,7 +6587,7 @@ finish_omp_clauses (tree clauses, enum c_omp_region_type ort) } if (!VAR_P (t) && TREE_CODE (t) != PARM_DECL) { - if (processing_template_decl) + if (processing_template_decl && TREE_CODE (t) != OVERLOAD) break; if (DECL_P (t)) error ("%qD is not a variable in % clause", t); @@ -6669,7 +6669,7 @@ finish_omp_clauses (tree clauses, enum c_omp_region_type ort) remove = true; else if (!VAR_P (t) && TREE_CODE (t) != PARM_DECL) { - if (processing_template_decl) + if (processing_template_decl && TREE_CODE (t) != OVERLOAD) break; if (DECL_P (t)) error ("%qD is not a variable in % clause", t); @@ -6800,7 +6800,7 @@ finish_omp_clauses (tree clauses, enum c_omp_region_type ort) } if (!VAR_P (t) && TREE_CODE (t) != PARM_DECL) { - if (processing_template_decl) + if (processing_template_decl && TREE_CODE (t) != OVERLOAD) break; if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_MAP && (OMP_CLAUSE_MAP_KIND (c) == GOMP_MAP_POINTER diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 446e234..0239d5a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-21 Jakub Jelinek + + PR c++/81154 + * g++.dg/gomp/pr81154.C: New test. + 2017-06-21 David Malcolm * g++.dg/other/old-style-cast-fixits.C: New test case. diff --git a/gcc/testsuite/g++.dg/gomp/pr81154.C b/gcc/testsuite/g++.dg/gomp/pr81154.C new file mode 100644 index 0000000..dc0aec3 --- /dev/null +++ b/gcc/testsuite/g++.dg/gomp/pr81154.C @@ -0,0 +1,57 @@ +// PR c++/81154 +// { dg-do compile } + +template +struct C +{ + int foo (T n) const + { +#pragma omp parallel shared (foo) // { dg-error "is not a variable in clause" } + ; +#pragma omp parallel private (foo) // { dg-error "is not a variable in clause" } + ; +#pragma omp parallel firstprivate (foo) // { dg-error "is not a variable in clause" } + ; +#pragma omp parallel for lastprivate (foo) // { dg-error "is not a variable in clause" } + for (T i = 0; i < n; i++) + ; +#pragma omp parallel for linear (foo) // { dg-error "is not a variable in clause" } + for (T i = 0; i < n; i++) + ; +#pragma omp parallel reduction (+:foo) // { dg-error "is not a variable in clause" } + ; + return 0; + } + int foo (int x, int y) { return x; } +}; + +struct D +{ + typedef int T; + int foo (T n) const + { +#pragma omp parallel shared (foo) // { dg-error "is not a variable in clause" } + ; +#pragma omp parallel private (foo) // { dg-error "is not a variable in clause" } + ; +#pragma omp parallel firstprivate (foo) // { dg-error "is not a variable in clause" } + ; +#pragma omp parallel for lastprivate (foo) // { dg-error "is not a variable in clause" } + for (T i = 0; i < n; i++) + ; +#pragma omp parallel for linear (foo) // { dg-error "is not a variable in clause" } + for (T i = 0; i < n; i++) + ; +#pragma omp parallel reduction (+:foo) // { dg-error "is not a variable in clause" } + ; + return 0; + } + int foo (int x, int y) { return x; } +}; + +int +main () +{ + C ().foo (1); + D ().foo (1); +} -- cgit v1.1 From ac135a731d319ec86562f7ff4a42453df3078836 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 21 Jun 2017 22:02:00 +0200 Subject: re PR target/81151 (-Wmaybe-uninitialized in insn-emit.c) PR target/81151 * config/i386/sse.md (round2): Renumber match_dup and operands indexes to avoid gap between operands and match_dups. From-SVN: r249469 --- gcc/ChangeLog | 6 ++++++ gcc/config/i386/sse.md | 14 +++++++------- 2 files changed, 13 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ea97b0b..d40f0c8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-21 Jakub Jelinek + + PR target/81151 + * config/i386/sse.md (round2): Renumber match_dup and + operands indexes to avoid gap between operands and match_dups. + 2017-06-21 Andrew Pinski * config/aarch64/aarch64-cost-tables.h (thunderx_extra_costs): diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 29a039d..f61ae2b 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15638,13 +15638,13 @@ (set_attr "mode" "")]) (define_expand "round2" - [(set (match_dup 4) + [(set (match_dup 3) (plus:VF (match_operand:VF 1 "register_operand") - (match_dup 3))) + (match_dup 2))) (set (match_operand:VF 0 "register_operand") (unspec:VF - [(match_dup 4) (match_dup 5)] + [(match_dup 3) (match_dup 4)] UNSPEC_ROUND))] "TARGET_ROUND && !flag_trapping_math" { @@ -15664,11 +15664,11 @@ vec_half = ix86_build_const_vector (mode, true, half); vec_half = force_reg (mode, vec_half); - operands[3] = gen_reg_rtx (mode); - emit_insn (gen_copysign3 (operands[3], vec_half, operands[1])); + operands[2] = gen_reg_rtx (mode); + emit_insn (gen_copysign3 (operands[2], vec_half, operands[1])); - operands[4] = gen_reg_rtx (mode); - operands[5] = GEN_INT (ROUND_TRUNC); + operands[3] = gen_reg_rtx (mode); + operands[4] = GEN_INT (ROUND_TRUNC); }) (define_expand "round2_sfix" -- cgit v1.1 From 4ded86690e9fd3c71e1ff47beea31079ad8a7b4f Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 21 Jun 2017 21:08:40 +0000 Subject: re PR target/80510 (Optimize Power7/power8 Altivec load/stores) 2017-06-21 Michael Meissner PR target/80510 * gcc.target/powerpc/pr80510-1.c: Restrict test to 64-bit until 32-bit support is added. Change ITYPE size to 64-bit integer. * gcc.target/powerpc/pr80510-2.c: Likewise. From-SVN: r249470 --- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/powerpc/pr80510-1.c | 8 +++++--- gcc/testsuite/gcc.target/powerpc/pr80510-2.c | 8 +++++--- 3 files changed, 17 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0239d5a..fa14c61 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2017-06-21 Michael Meissner + + PR target/80510 + * gcc.target/powerpc/pr80510-1.c: Restrict test to 64-bit until + 32-bit support is added. Change ITYPE size to 64-bit integer. + * gcc.target/powerpc/pr80510-2.c: Likewise. + 2017-06-21 Jakub Jelinek PR c++/81154 diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c index 7024f3b..d832e92 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ @@ -6,7 +6,9 @@ /* Make sure that STXSDX is generated for double scalars in Altivec registers on power7 instead of moving the value to a FPR register and doing a X-FORM - store. */ + store. + + 32-bit currently does not have support for STXSDX in the mov{df,dd} patterns. */ #ifndef TYPE #define TYPE double @@ -21,7 +23,7 @@ #endif #ifndef ITYPE -#define ITYPE long +#define ITYPE __INT64_TYPE__ #endif #ifdef DO_CALL diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c index 18dc356..83a186b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ @@ -6,7 +6,9 @@ /* Make sure that STXSSPX is generated for float scalars in Altivec registers on power7 instead of moving the value to a FPR register and doing a X-FORM - store. */ + store. + + 32-bit currently does not have support for STXSSPX in the mov{sf,sd} patterns. */ #ifndef TYPE #define TYPE float @@ -21,7 +23,7 @@ #endif #ifndef ITYPE -#define ITYPE long +#define ITYPE __INT64_TYPE__ #endif #ifdef DO_CALL -- cgit v1.1 From 8d4b68a7c4091c99c8d591e93efae5748a7ced13 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 21 Jun 2017 21:42:41 +0000 Subject: libgo, syscall: fix ptrace implementation on MIPS On MIPS, the correct structure for PtraceRegs is 'struct pt_regs' which is declared in linux/ptrace.h. Previously no PtraceRegs structure was created on MIPS because 'struct user_regs_struct' doesn't exist there. Fallback to using pt_regs when the PtraceRegs structure is generated in mksysinfo.sh, then adjust syscall_linux_mipsx.go to read the program counter from the correct field. In addition, implement PtraceGetRegs and PtraceSetRegs on all 3 ABI variants. syscall_linux_mips64x.go can now be removed since the ptrace code on all 3 ABIs is identical. Reviewed-on: https://go-review.googlesource.com/46150 From-SVN: r249472 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 0eeac9b..5ef0cc0 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -6449e2832eef94eacf89c88fa16bede637f729ba +b2bebba1f8a8185546c47f8460a3d5c2e31d0434 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 4c0478b33873f8201c103d0910d7f1d5dcfc2979 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 21 Jun 2017 21:47:35 +0000 Subject: internal/syscall/unix: implement randomTrap on mips64p32* Rename getrandom_linux_mipsn32.go to use the new architecture name for the n32 ABI and enable building it on mips64p32 and mips64p32le. Reviewed-on: https://go-review.googlesource.com/46151 From-SVN: r249474 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 5ef0cc0..74d94b9 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -b2bebba1f8a8185546c47f8460a3d5c2e31d0434 +c49c752b4d2934cff325dd540821c4b27cc61a05 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 95eebd21db8b4b389a7fa4075ffc64df086b61ed Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 21 Jun 2017 21:50:52 +0000 Subject: cmd/cgo: add mips64p32* to ptrSizeMap and intSizeMap Reviewed-on: https://go-review.googlesource.com/46152 From-SVN: r249475 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 74d94b9..d9c21fa 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -c49c752b4d2934cff325dd540821c4b27cc61a05 +5a97e51022e3b7798f985714ced3e02d6e730b54 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 1701a9d8f0ca4153bbf3cf75487c6a14606e5121 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 21 Jun 2017 21:55:34 +0000 Subject: libgo: use gc's arch names as the default GOARCHs on MIPS This means that the gc tools and gofrontend agree on the architecture names for the 3 MIPS ABIs which should allow a gofrontend compiler to build go. Reviewed-on: https://go-review.googlesource.com/46153 From-SVN: r249476 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index d9c21fa..0c0d6e5 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -5a97e51022e3b7798f985714ced3e02d6e730b54 +3f713ddb2a9a2a736f3a12d71c56cb7fd444afba The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From b95cd48b01b1340475dd7a408af6d665822a8cf5 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 21 Jun 2017 22:11:04 +0000 Subject: libgo: remove old MIPS architecture names This removes the old names for the 3 main MIPS ABIs: mipso32, mipsn32 and mipsn64. It also removes the mipso64 ABI which has no equivalent architecture name in go. This ABI has been dead for sometime and I doubt anyone will miss it. Reviewed-on: https://go-review.googlesource.com/46154 From-SVN: r249477 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 0c0d6e5..7eb0770 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -3f713ddb2a9a2a736f3a12d71c56cb7fd444afba +a4b455aa584e0d6e362a88597f11bba1427088e2 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 36f1a35f6931f67f7daec5aa7803a6475e8087ca Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 21 Jun 2017 22:29:58 +0000 Subject: compiler: fix missing case in Array_type::get_value_pointer Update the code in Array_type::get_value_pointer that handles "lvalue" context to look for both regular var expressions and temp var expressions, since both can appear in array/slice index expressions on the left hand side of assignments. Reviewed-on: https://go-review.googlesource.com/46170 From-SVN: r249486 --- gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/types.cc | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 7eb0770..f6f0c68 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -a4b455aa584e0d6e362a88597f11bba1427088e2 +0b93af68feb0a4135e83dd9e6c11df1563d862a9 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. diff --git a/gcc/go/gofrontend/types.cc b/gcc/go/gofrontend/types.cc index 912a23e..b9ad41e 100644 --- a/gcc/go/gofrontend/types.cc +++ b/gcc/go/gofrontend/types.cc @@ -7635,12 +7635,19 @@ Array_type::get_value_pointer(Gogo*, Expression* array, bool is_lvalue) const { Temporary_reference_expression* tref = array->temporary_reference_expression(); + Var_expression* ve = array->var_expression(); if (tref != NULL) { tref = tref->copy()->temporary_reference_expression(); tref->set_is_lvalue(); array = tref; } + else if (ve != NULL) + { + ve = new Var_expression(ve->named_object(), ve->location()); + ve->set_in_lvalue_pos(); + array = ve; + } } return Expression::make_slice_info(array, -- cgit v1.1 From fbe457feb7091d5a75374b8eec4695bf13c7819a Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Wed, 21 Jun 2017 22:39:36 +0000 Subject: debug/elf: handle Alpha relocs Patch by Uros Bizjak. Reviewed-on: https://go-review.googlesource.com/46391 From-SVN: r249487 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index f6f0c68..96cf627 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -0b93af68feb0a4135e83dd9e6c11df1563d862a9 +dac4bb4f4ed8e7f2939d45439048dec2f6db14cf The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From bc216de9f65527cd80fd02a645da036e8bfb7818 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Thu, 22 Jun 2017 00:16:21 +0000 Subject: Daily bump. From-SVN: r249492 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 12ee994..b5de4d3 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170621 +20170622 -- cgit v1.1 From 55ea0ea07dc837e596f81ce972361ec46d2cb1fe Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 04:13:36 +0000 Subject: compiler, runtime: better stack trace for `go f()` where f is nil The test for this is TestGoNil in the runtime package, which we don't run yet but will run with a subsequent gotools patch. Updates golang/go#8045 Reviewed-on: https://go-review.googlesource.com/46392 From-SVN: r249494 --- gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/gogo.h | 3 +++ gcc/go/gofrontend/statements.cc | 30 ++++++++++++++++++++++++++++-- 3 files changed, 32 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 96cf627..9a23eb9 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -dac4bb4f4ed8e7f2939d45439048dec2f6db14cf +075e67bdbcb730669c1af1aa2d53bb77cbb2a3c5 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. diff --git a/gcc/go/gofrontend/gogo.h b/gcc/go/gofrontend/gogo.h index c3e3f30..a04a1a3 100644 --- a/gcc/go/gofrontend/gogo.h +++ b/gcc/go/gofrontend/gogo.h @@ -3379,6 +3379,9 @@ static const int RUNTIME_ERROR_MAKE_CHAN_OUT_OF_BOUNDS = 9; // Division by zero. static const int RUNTIME_ERROR_DIVISION_BY_ZERO = 10; +// Go statement with nil function. +static const int RUNTIME_ERROR_GO_NIL = 11; + // This is used by some of the langhooks. extern Gogo* go_get_gogo(); diff --git a/gcc/go/gofrontend/statements.cc b/gcc/go/gofrontend/statements.cc index 7a448d7..e592176 100644 --- a/gcc/go/gofrontend/statements.cc +++ b/gcc/go/gofrontend/statements.cc @@ -2201,6 +2201,15 @@ Thunk_statement::simplify_statement(Gogo* gogo, Named_object* function, Location location = this->location(); + bool is_constant_function = this->is_constant_function(); + Temporary_statement* fn_temp = NULL; + if (!is_constant_function) + { + fn_temp = Statement::make_temporary(NULL, fn, location); + block->insert_statement_before(block->statements()->size() - 1, fn_temp); + fn = Expression::make_temporary_reference(fn_temp, location); + } + std::string thunk_name = Gogo::thunk_name(); // Build the thunk. @@ -2212,7 +2221,7 @@ Thunk_statement::simplify_statement(Gogo* gogo, Named_object* function, // argument to the thunk. Expression_list* vals = new Expression_list(); - if (!this->is_constant_function()) + if (!is_constant_function) vals->push_back(fn); if (interface_method != NULL) @@ -2238,6 +2247,23 @@ Thunk_statement::simplify_statement(Gogo* gogo, Named_object* function, // Allocate the initialized struct on the heap. constructor = Expression::make_heap_expression(constructor, location); + // Throw an error if the function is nil. This is so that for `go + // nil` we get a backtrace from the go statement, rather than a + // useless backtrace from the brand new goroutine. + Expression* param = constructor; + if (!is_constant_function) + { + fn = Expression::make_temporary_reference(fn_temp, location); + Expression* nil = Expression::make_nil(location); + Expression* isnil = Expression::make_binary(OPERATOR_EQEQ, fn, nil, + location); + Expression* crash = gogo->runtime_error(RUNTIME_ERROR_GO_NIL, location); + crash = Expression::make_conditional(isnil, crash, + Expression::make_nil(location), + location); + param = Expression::make_compound(crash, constructor, location); + } + // Look up the thunk. Named_object* named_thunk = gogo->lookup(thunk_name, NULL); go_assert(named_thunk != NULL && named_thunk->is_function()); @@ -2246,7 +2272,7 @@ Thunk_statement::simplify_statement(Gogo* gogo, Named_object* function, Expression* func = Expression::make_func_reference(named_thunk, NULL, location); Expression_list* params = new Expression_list(); - params->push_back(constructor); + params->push_back(param); Call_expression* call = Expression::make_call(func, params, false, location); // Build the simple go or defer statement. -- cgit v1.1 From c83c219a6359e2ab655e7b8a7fabe829fd7bc6b9 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 04:16:23 +0000 Subject: runtime: in traceback, print panic rather than runtime.gopanic The gc toolchain does the same thing, in gentraceback in runtime/traceback.go. The test for this is TestPanicTraceback in runtime/crash_test.go. We don't yet run that test, but we will in a future change. Reviewed-on: https://go-review.googlesource.com/46397 From-SVN: r249495 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 9a23eb9..17df499 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -075e67bdbcb730669c1af1aa2d53bb77cbb2a3c5 +f70ef19badafb85b1caa72b51b0082deb48d433a The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 8dc877ebc405937c7026f8fa7632b23e1f6ebccb Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Thu, 22 Jun 2017 06:54:04 +0000 Subject: Support --sysroot with Solaris ld * configure.ac (gcc_cv_ld_static_dynamic): Also check stderr for $gcc_cv_ld --help output. (gcc_cv_ld_demangle): Likewise. (gcc_cv_ld_eh_frame_hdr): Likewise. (gcc_cv_ld_pie): Likewise. (gcc_cv_ld_as_needed): Likewise. Prefer native forms unless $gnu_ld. (gcc_cv_ld_buildid): Likewise. (gcc_cv_ld_sysroot): Likewise. (ld_bndplt_support): Likewise. (ld_pushpopstate_support): Likewise. * configure: Regenerate. * config/sol2.h [!USE_GLD] (SYSROOT_SPEC): Define. From-SVN: r249496 --- gcc/ChangeLog | 15 +++++++++++++++ gcc/config/sol2.h | 5 +++++ gcc/configure | 44 ++++++++++++++++++++++---------------------- gcc/configure.ac | 44 ++++++++++++++++++++++---------------------- 4 files changed, 64 insertions(+), 44 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d40f0c8..c056ae4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2017-06-22 Rainer Orth + + * configure.ac (gcc_cv_ld_static_dynamic): Also check stderr for + $gcc_cv_ld --help output. + (gcc_cv_ld_demangle): Likewise. + (gcc_cv_ld_eh_frame_hdr): Likewise. + (gcc_cv_ld_pie): Likewise. + (gcc_cv_ld_as_needed): Likewise. Prefer native forms unless $gnu_ld. + (gcc_cv_ld_buildid): Likewise. + (gcc_cv_ld_sysroot): Likewise. + (ld_bndplt_support): Likewise. + (ld_pushpopstate_support): Likewise. + * configure: Regenerate. + * config/sol2.h [!USE_GLD] (SYSROOT_SPEC): Define. + 2017-06-21 Jakub Jelinek PR target/81151 diff --git a/gcc/config/sol2.h b/gcc/config/sol2.h index 1ae7f9f..b8398d0 100644 --- a/gcc/config/sol2.h +++ b/gcc/config/sol2.h @@ -331,6 +331,11 @@ along with GCC; see the file COPYING3. If not see #endif #ifndef USE_GLD +/* Prefer native form with Solaris ld. */ +#define SYSROOT_SPEC "-z sysroot=%R" +#endif + +#ifndef USE_GLD /* With Sun ld, use mapfile to enforce direct binding to libgcc_s unwinder. */ #define LINK_LIBGCC_MAPFILE_SPEC \ "%{shared|shared-libgcc:-M %slibgcc-unwind.map}" diff --git a/gcc/configure b/gcc/configure index cc542ac..317517c 100755 --- a/gcc/configure +++ b/gcc/configure @@ -24372,8 +24372,8 @@ if test $in_tree_ld = yes ; then fi elif test x$gcc_cv_ld != x; then # Check if linker supports -Bstatic/-Bdynamic option - if $gcc_cv_ld --help 2>/dev/null | grep -- -Bstatic > /dev/null \ - && $gcc_cv_ld --help 2>/dev/null | grep -- -Bdynamic > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep -- -Bstatic > /dev/null \ + && $gcc_cv_ld --help 2>&1 | grep -- -Bdynamic > /dev/null; then gcc_cv_ld_static_dynamic=yes else case "$target" in @@ -24426,7 +24426,7 @@ $as_echo_n "checking linker --demangle support... " >&6; } fi elif test x$gcc_cv_ld != x -a x"$gnu_ld" = xyes; then # Check if the GNU linker supports --demangle option - if $gcc_cv_ld --help 2>/dev/null | grep no-demangle > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep no-demangle > /dev/null; then gcc_cv_ld_demangle=yes fi fi @@ -28058,7 +28058,7 @@ if test $in_tree_ld = yes ; then elif test x$gcc_cv_ld != x; then if echo "$ld_ver" | grep GNU > /dev/null; then # Check if linker supports --eh-frame-hdr option - if $gcc_cv_ld --help 2>/dev/null | grep eh-frame-hdr > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep eh-frame-hdr > /dev/null; then gcc_cv_ld_eh_frame_hdr=yes fi else @@ -28136,7 +28136,7 @@ if test $in_tree_ld = yes ; then fi elif test x$gcc_cv_ld != x; then # Check if linker supports -pie option - if $gcc_cv_ld --help 2>/dev/null | grep -- -pie > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep -- -pie > /dev/null; then gcc_cv_ld_pie=yes case "$target" in *-*-solaris2*) @@ -28493,19 +28493,19 @@ if test $in_tree_ld = yes ; then gcc_cv_ld_as_needed=yes fi elif test x$gcc_cv_ld != x; then - # Check if linker supports --as-needed and --no-as-needed options - if $gcc_cv_ld --help 2>/dev/null | grep as-needed > /dev/null; then - gcc_cv_ld_as_needed=yes - else - case "$target" in - # Solaris 2 ld always supports -z ignore/-z record. - *-*-solaris2*) - gcc_cv_ld_as_needed=yes - gcc_cv_ld_as_needed_option="-z ignore" - gcc_cv_ld_no_as_needed_option="-z record" - ;; - esac - fi + # Check if linker supports --as-needed and --no-as-needed options + if $gcc_cv_ld --help 2>&1 | grep as-needed > /dev/null; then + gcc_cv_ld_as_needed=yes + fi + case "$target:$gnu_ld" in + *-*-solaris2*:no) + # Solaris 2 ld always supports -z ignore/-z record. Prefer the native + # forms. + gcc_cv_ld_as_needed=yes + gcc_cv_ld_as_needed_option="-z ignore" + gcc_cv_ld_no_as_needed_option="-z record" + ;; + esac fi # --as-needed/-z ignore can only be used if libgcc_s.so.1 uses # dl_iterate_phdr, i.e. since Solaris 11. @@ -28808,7 +28808,7 @@ else gcc_cv_ld_buildid=yes fi elif test x$gcc_cv_ld != x; then - if $gcc_cv_ld --help 2>/dev/null | grep build-id > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep build-id > /dev/null; then gcc_cv_ld_buildid=yes fi fi @@ -28881,7 +28881,7 @@ else gcc_cv_ld_sysroot=yes fi elif test x$gcc_cv_ld != x; then - if $gcc_cv_ld --help 2>/dev/null | grep sysroot > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep sysroot > /dev/null; then gcc_cv_ld_sysroot=yes fi fi @@ -29857,7 +29857,7 @@ if test x"$ld_is_gold" = xno; then fi elif test x$gcc_cv_ld != x; then # Check if linker supports -a bndplt option - if $gcc_cv_ld --help 2>/dev/null | grep -- '-z bndplt' > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep -- '-z bndplt' > /dev/null; then ld_bndplt_support=yes fi fi @@ -29881,7 +29881,7 @@ if test x"$ld_is_gold" = xno; then fi elif test x$gcc_cv_ld != x; then # Check if linker supports --push-state/--pop-state options - if $gcc_cv_ld --help 2>/dev/null | grep -- '--push-state' > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep -- '--push-state' > /dev/null; then ld_pushpopstate_support=yes fi fi diff --git a/gcc/configure.ac b/gcc/configure.ac index b54f797..e1b03a9 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -3569,8 +3569,8 @@ if test $in_tree_ld = yes ; then fi elif test x$gcc_cv_ld != x; then # Check if linker supports -Bstatic/-Bdynamic option - if $gcc_cv_ld --help 2>/dev/null | grep -- -Bstatic > /dev/null \ - && $gcc_cv_ld --help 2>/dev/null | grep -- -Bdynamic > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep -- -Bstatic > /dev/null \ + && $gcc_cv_ld --help 2>&1 | grep -- -Bdynamic > /dev/null; then gcc_cv_ld_static_dynamic=yes else case "$target" in @@ -3614,7 +3614,7 @@ if test x"$demangler_in_ld" = xyes; then fi elif test x$gcc_cv_ld != x -a x"$gnu_ld" = xyes; then # Check if the GNU linker supports --demangle option - if $gcc_cv_ld --help 2>/dev/null | grep no-demangle > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep no-demangle > /dev/null; then gcc_cv_ld_demangle=yes fi fi @@ -4985,7 +4985,7 @@ if test $in_tree_ld = yes ; then elif test x$gcc_cv_ld != x; then if echo "$ld_ver" | grep GNU > /dev/null; then # Check if linker supports --eh-frame-hdr option - if $gcc_cv_ld --help 2>/dev/null | grep eh-frame-hdr > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep eh-frame-hdr > /dev/null; then gcc_cv_ld_eh_frame_hdr=yes fi else @@ -5056,7 +5056,7 @@ if test $in_tree_ld = yes ; then fi elif test x$gcc_cv_ld != x; then # Check if linker supports -pie option - if $gcc_cv_ld --help 2>/dev/null | grep -- -pie > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep -- -pie > /dev/null; then gcc_cv_ld_pie=yes case "$target" in *-*-solaris2*) @@ -5382,19 +5382,19 @@ if test $in_tree_ld = yes ; then gcc_cv_ld_as_needed=yes fi elif test x$gcc_cv_ld != x; then - # Check if linker supports --as-needed and --no-as-needed options - if $gcc_cv_ld --help 2>/dev/null | grep as-needed > /dev/null; then - gcc_cv_ld_as_needed=yes - else - case "$target" in - # Solaris 2 ld always supports -z ignore/-z record. - *-*-solaris2*) - gcc_cv_ld_as_needed=yes - gcc_cv_ld_as_needed_option="-z ignore" - gcc_cv_ld_no_as_needed_option="-z record" - ;; - esac - fi + # Check if linker supports --as-needed and --no-as-needed options + if $gcc_cv_ld --help 2>&1 | grep as-needed > /dev/null; then + gcc_cv_ld_as_needed=yes + fi + case "$target:$gnu_ld" in + *-*-solaris2*:no) + # Solaris 2 ld always supports -z ignore/-z record. Prefer the native + # forms. + gcc_cv_ld_as_needed=yes + gcc_cv_ld_as_needed_option="-z ignore" + gcc_cv_ld_no_as_needed_option="-z record" + ;; + esac fi # --as-needed/-z ignore can only be used if libgcc_s.so.1 uses # dl_iterate_phdr, i.e. since Solaris 11. @@ -5634,7 +5634,7 @@ AC_CACHE_CHECK(linker --build-id support, gcc_cv_ld_buildid=yes fi elif test x$gcc_cv_ld != x; then - if $gcc_cv_ld --help 2>/dev/null | grep build-id > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep build-id > /dev/null; then gcc_cv_ld_buildid=yes fi fi]) @@ -5689,7 +5689,7 @@ AC_CACHE_CHECK(linker --sysroot support, gcc_cv_ld_sysroot=yes fi elif test x$gcc_cv_ld != x; then - if $gcc_cv_ld --help 2>/dev/null | grep sysroot > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep sysroot > /dev/null; then gcc_cv_ld_sysroot=yes fi fi]) @@ -6363,7 +6363,7 @@ if test x"$ld_is_gold" = xno; then fi elif test x$gcc_cv_ld != x; then # Check if linker supports -a bndplt option - if $gcc_cv_ld --help 2>/dev/null | grep -- '-z bndplt' > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep -- '-z bndplt' > /dev/null; then ld_bndplt_support=yes fi fi @@ -6384,7 +6384,7 @@ if test x"$ld_is_gold" = xno; then fi elif test x$gcc_cv_ld != x; then # Check if linker supports --push-state/--pop-state options - if $gcc_cv_ld --help 2>/dev/null | grep -- '--push-state' > /dev/null; then + if $gcc_cv_ld --help 2>&1 | grep -- '--push-state' > /dev/null; then ld_pushpopstate_support=yes fi fi -- cgit v1.1 From 85d5b033ae83c37ae0b4dbd4210d463dcacc4842 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 22 Jun 2017 08:14:21 +0000 Subject: pr65947-14.c: New testcase. 2017-06-22 Richard Biener * gcc.dg/vect/pr65947-14.c: New testcase. From-SVN: r249500 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/vect/pr65947-14.c | 44 ++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/vect/pr65947-14.c (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fa14c61..907e176 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-22 Richard Biener + + * gcc.dg/vect/pr65947-14.c: New testcase. + 2017-06-21 Michael Meissner PR target/80510 diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-14.c b/gcc/testsuite/gcc.dg/vect/pr65947-14.c new file mode 100644 index 0000000..2b15707 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr65947-14.c @@ -0,0 +1,44 @@ +/* { dg-require-effective-target vect_condition } */ + +#include "tree-vect.h" + +extern void abort (void) __attribute__ ((noreturn)); + +#define N 27 + +/* Condition reduction with matches only in even lanes at runtime. */ + +int +condition_reduction (int *a, int min_v) +{ + int last = N + 96; + + for (int i = 0; i < N; i++) + if (a[i] > min_v) + last = i; + + return last; +} + +int +main (void) +{ + int a[N] = { + 47, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 21, 22, 23, 24, 25, 26, 27 + }; + + check_vect (); + + int ret = condition_reduction (a, 46); + + /* loop should have found a value of 0, not default N + 96. */ + if (ret != 0) + abort (); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } */ +/* { dg-final { scan-tree-dump-times "condition expression based on integer induction." 4 "vect" } } */ -- cgit v1.1 From a78f698034a2ab7fabd0d6ca3d35e688670b6d2f Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 22 Jun 2017 08:33:28 +0000 Subject: pr65947-14.c: Fix missing brace. 2017-06-22 Richard Biener * gcc.dg/vect/pr65947-14.c: Fix missing brace. From-SVN: r249501 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/vect/pr65947-14.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 907e176..050e37d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2017-06-22 Richard Biener + * gcc.dg/vect/pr65947-14.c: Fix missing brace. + +2017-06-22 Richard Biener + * gcc.dg/vect/pr65947-14.c: New testcase. 2017-06-21 Michael Meissner diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-14.c b/gcc/testsuite/gcc.dg/vect/pr65947-14.c index 2b15707..0d47a7d 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-14.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-14.c @@ -40,5 +40,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } } */ /* { dg-final { scan-tree-dump-times "condition expression based on integer induction." 4 "vect" } } */ -- cgit v1.1 From 71f82be94fad1597696b14c325eed203b75dde70 Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Thu, 22 Jun 2017 08:39:04 +0000 Subject: [Patch match.pd] Fold (A / (1 << B)) to (A >> B) For the testcase in the patch: unsigned long f2 (unsigned long a, int b) { unsigned long x = 1UL << b; return a / x; } We currently generate an unsigned division and a left shift, where we could instead generate a right shift. gcc/ 2017-06-21 James Greenhalgh * match.pd (A / (1 << B) -> A >> B): New. * generic-match-head.c: Include optabs-tree.h. * gimple-match-head.c: Likewise. * optabs-tree.h (target_supports_op_p): New. * optabs-tree.c (target_supports_op_p): New. gcc/testsuite/ 2017-06-21 James Greenhalgh * gcc.dg/tree-ssa/forwprop-37.c: New. From-SVN: r249502 --- gcc/ChangeLog | 8 ++++++++ gcc/generic-match-head.c | 1 + gcc/gimple-match-head.c | 1 + gcc/match.pd | 12 ++++++++++++ gcc/optabs-tree.c | 15 +++++++++++++++ gcc/optabs-tree.h | 2 ++ gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/tree-ssa/forwprop-37.c | 25 +++++++++++++++++++++++++ 8 files changed, 68 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/forwprop-37.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c056ae4..9b150a4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-06-22 James Greenhalgh + + * match.pd (A / (1 << B) -> A >> B): New. + * generic-match-head.c: Include optabs-tree.h. + * gimple-match-head.c: Likewise. + * optabs-tree.h (target_supports_op_p): New. + * optabs-tree.c (target_supports_op_p): New. + 2017-06-22 Rainer Orth * configure.ac (gcc_cv_ld_static_dynamic): Also check stderr for diff --git a/gcc/generic-match-head.c b/gcc/generic-match-head.c index 0c0d182..4504401 100644 --- a/gcc/generic-match-head.c +++ b/gcc/generic-match-head.c @@ -33,6 +33,7 @@ along with GCC; see the file COPYING3. If not see #include "builtins.h" #include "case-cfn-macros.h" #include "gimplify.h" +#include "optabs-tree.h" /* Routine to determine if the types T1 and T2 are effectively diff --git a/gcc/gimple-match-head.c b/gcc/gimple-match-head.c index e7e9839..5f6aa273 100644 --- a/gcc/gimple-match-head.c +++ b/gcc/gimple-match-head.c @@ -39,6 +39,7 @@ along with GCC; see the file COPYING3. If not see #include "internal-fn.h" #include "case-cfn-macros.h" #include "gimplify.h" +#include "optabs-tree.h" /* Forward declarations of the private auto-generated matchers. diff --git a/gcc/match.pd b/gcc/match.pd index 7bd2676..a4cae11 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -161,6 +161,18 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (op @0 integer_onep) (non_lvalue @0))) +/* (A / (1 << B)) -> (A >> B). + Only for unsigned A. For signed A, this would not preserve rounding + toward zero. + For example: (-1 / ( 1 << B)) != -1 >> B. */ +(simplify + (trunc_div @0 (lshift integer_onep@1 @2)) + (if ((TYPE_UNSIGNED (type) || tree_expr_nonnegative_p (@0)) + && (!VECTOR_TYPE_P (type) + || target_supports_op_p (type, RSHIFT_EXPR, optab_vector) + || target_supports_op_p (type, RSHIFT_EXPR, optab_scalar))) + (rshift @0 @2))) + /* Preserve explicit divisions by 0: the C++ front-end wants to detect undefined behavior in constexpr evaluation, and assuming that the division traps enables better optimizations than these anyway. */ diff --git a/gcc/optabs-tree.c b/gcc/optabs-tree.c index 4bb54ba..c183b14 100644 --- a/gcc/optabs-tree.c +++ b/gcc/optabs-tree.c @@ -376,3 +376,18 @@ init_tree_optimization_optabs (tree optnode) ggc_free (tmp_optabs); } } + +/* Return TRUE if the target has support for vector right shift of an + operand of type TYPE. If OT_TYPE is OPTAB_DEFAULT, check for existence + of a shift by either a scalar or a vector. Otherwise, check only + for a shift that matches OT_TYPE. */ + +bool +target_supports_op_p (tree type, enum tree_code code, + enum optab_subtype ot_subtype) +{ + optab ot = optab_for_tree_code (code, type, ot_subtype); + return (ot != unknown_optab + && optab_handler (ot, TYPE_MODE (type)) != CODE_FOR_nothing); +} + diff --git a/gcc/optabs-tree.h b/gcc/optabs-tree.h index d0b27e0..52e842b 100644 --- a/gcc/optabs-tree.h +++ b/gcc/optabs-tree.h @@ -41,5 +41,7 @@ bool supportable_convert_operation (enum tree_code, tree, tree, tree *, bool expand_vec_cmp_expr_p (tree, tree, enum tree_code); bool expand_vec_cond_expr_p (tree, tree, enum tree_code); void init_tree_optimization_optabs (tree); +bool target_supports_op_p (tree, enum tree_code, + enum optab_subtype = optab_default); #endif diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 050e37d..497c4b8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-22 James Greenhalgh + + * gcc.dg/tree-ssa/forwprop-37.c: New. + 2017-06-22 Richard Biener * gcc.dg/vect/pr65947-14.c: Fix missing brace. diff --git a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-37.c b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-37.c new file mode 100644 index 0000000..dec826c --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-37.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fdump-tree-forwprop1-raw" } */ + +unsigned int +f1 (unsigned int a, unsigned int b) +{ + unsigned int x = 1U << b; + return a / x; +} + +unsigned long +f2 (unsigned long a, int b) +{ + unsigned long x = 1UL << b; + return a / x; +} + +unsigned long long +f3 (unsigned long long a, int b) +{ + unsigned long long x = 1ULL << b; + return a / x; +} + +/* { dg-final { scan-tree-dump-not "trunc_div_expr" "forwprop1" } } */ -- cgit v1.1 From c24c235efacf23441fdae032eb66540143f11c1d Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Thu, 22 Jun 2017 12:54:40 +0200 Subject: Fix ipa-split-5.c test-case. 2017-06-22 Martin Liska * gcc.dg/tree-ssa/ipa-split-5.c: Make function bigger in order to not inline it. From-SVN: r249503 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.dg/tree-ssa/ipa-split-5.c | 17 +++++++++++++++++ 2 files changed, 22 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 497c4b8..af774e4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-22 Martin Liska + + * gcc.dg/tree-ssa/ipa-split-5.c: Make function bigger in order + to not inline it. + 2017-06-22 James Greenhalgh * gcc.dg/tree-ssa/forwprop-37.c: New. diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ipa-split-5.c b/gcc/testsuite/gcc.dg/tree-ssa/ipa-split-5.c index 1278e6e..2d713d6 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ipa-split-5.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ipa-split-5.c @@ -20,6 +20,23 @@ struct a split_me (int a) retval = make_me_big (a); retval = make_me_big (a); retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); + retval = make_me_big (a); return retval; } } -- cgit v1.1 From 0759db190d979bb4adaeaedd19ab0c823c168691 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 22 Jun 2017 12:07:07 +0000 Subject: tree-vect-loop.c (vect_model_reduction_cost): Handle COND_REDUCTION and INTEGER_INDUC_COND_REDUCTION without REDUC_MAX_EXPR... 2016-06-22 Richard Biener * tree-vect-loop.c (vect_model_reduction_cost): Handle COND_REDUCTION and INTEGER_INDUC_COND_REDUCTION without REDUC_MAX_EXPR support. (vectorizable_reduction): Likewise. (vect_create_epilog_for_reduction): Likewise. * gcc.dg/vect/pr65947-1.c: Remove xfail. * gcc.dg/vect/pr65947-2.c: Likewise. * gcc.dg/vect/pr65947-3.c: Likewise. * gcc.dg/vect/pr65947-4.c: Likewise. * gcc.dg/vect/pr65947-5.c: Likewise. * gcc.dg/vect/pr65947-6.c: Likewise. * gcc.dg/vect/pr65947-8.c: Likewise. * gcc.dg/vect/pr65947-9.c: Likewise. * gcc.dg/vect/pr65947-10.c: Likewise. * gcc.dg/vect/pr65947-12.c: Likewise. * gcc.dg/vect/pr65947-13.c: Likewise. * gcc.dg/vect/pr65947-14.c: Likewise. * gcc.dg/vect/vect-cond-2.c: Likewise. * gcc.dg/vect/vect-pr69848.c: Likewise. From-SVN: r249553 --- gcc/ChangeLog | 8 ++ gcc/testsuite/ChangeLog | 17 ++++ gcc/testsuite/gcc.dg/vect/pr65947-1.c | 4 +- gcc/testsuite/gcc.dg/vect/pr65947-10.c | 2 +- gcc/testsuite/gcc.dg/vect/pr65947-12.c | 2 +- gcc/testsuite/gcc.dg/vect/pr65947-13.c | 2 +- gcc/testsuite/gcc.dg/vect/pr65947-14.c | 2 +- gcc/testsuite/gcc.dg/vect/pr65947-2.c | 2 +- gcc/testsuite/gcc.dg/vect/pr65947-3.c | 2 +- gcc/testsuite/gcc.dg/vect/pr65947-4.c | 4 +- gcc/testsuite/gcc.dg/vect/pr65947-5.c | 4 +- gcc/testsuite/gcc.dg/vect/pr65947-6.c | 2 +- gcc/testsuite/gcc.dg/vect/pr65947-8.c | 2 +- gcc/testsuite/gcc.dg/vect/pr65947-9.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-cond-2.c | 4 +- gcc/testsuite/gcc.dg/vect/vect-pr69848.c | 2 +- gcc/tree-vect-loop.c | 130 +++++++++++++++++++++++++------ 17 files changed, 147 insertions(+), 44 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9b150a4..4b78674 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2016-06-22 Richard Biener + + * tree-vect-loop.c (vect_model_reduction_cost): Handle + COND_REDUCTION and INTEGER_INDUC_COND_REDUCTION without + REDUC_MAX_EXPR support. + (vectorizable_reduction): Likewise. + (vect_create_epilog_for_reduction): Likewise. + 2017-06-22 James Greenhalgh * match.pd (A / (1 << B) -> A >> B): New. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index af774e4..641e412 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,20 @@ +2016-06-22 Richard Biener + + * gcc.dg/vect/pr65947-1.c: Remove xfail. + * gcc.dg/vect/pr65947-2.c: Likewise. + * gcc.dg/vect/pr65947-3.c: Likewise. + * gcc.dg/vect/pr65947-4.c: Likewise. + * gcc.dg/vect/pr65947-5.c: Likewise. + * gcc.dg/vect/pr65947-6.c: Likewise. + * gcc.dg/vect/pr65947-8.c: Likewise. + * gcc.dg/vect/pr65947-9.c: Likewise. + * gcc.dg/vect/pr65947-10.c: Likewise. + * gcc.dg/vect/pr65947-12.c: Likewise. + * gcc.dg/vect/pr65947-13.c: Likewise. + * gcc.dg/vect/pr65947-14.c: Likewise. + * gcc.dg/vect/vect-cond-2.c: Likewise. + * gcc.dg/vect/vect-pr69848.c: Likewise. + 2017-06-22 Martin Liska * gcc.dg/tree-ssa/ipa-split-5.c: Make function bigger in order diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-1.c b/gcc/testsuite/gcc.dg/vect/pr65947-1.c index 93ca4db..9072f11 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-1.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-1.c @@ -40,5 +40,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } } */ -/* { dg-final { scan-tree-dump-times "condition expression based on integer induction." 4 "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "condition expression based on integer induction." 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-10.c b/gcc/testsuite/gcc.dg/vect/pr65947-10.c index 9bdfd6d..a8a674f 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-10.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-10.c @@ -40,6 +40,6 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */ /* { dg-final { scan-tree-dump-not "condition expression based on integer induction." "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-12.c b/gcc/testsuite/gcc.dg/vect/pr65947-12.c index 2f37aaf..8e2c46f 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-12.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-12.c @@ -41,5 +41,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */ /* { dg-final { scan-tree-dump-not "condition expression based on integer induction." "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-13.c b/gcc/testsuite/gcc.dg/vect/pr65947-13.c index e1b626e..061777a 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-13.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-13.c @@ -41,5 +41,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */ /* { dg-final { scan-tree-dump-not "condition expression based on integer induction." "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-14.c b/gcc/testsuite/gcc.dg/vect/pr65947-14.c index 0d47a7d..a28e80b 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-14.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-14.c @@ -40,5 +40,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */ /* { dg-final { scan-tree-dump-times "condition expression based on integer induction." 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-2.c b/gcc/testsuite/gcc.dg/vect/pr65947-2.c index 6a36db1..d72fffa 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-2.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-2.c @@ -41,5 +41,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */ /* { dg-final { scan-tree-dump-not "condition expression based on integer induction." "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-3.c b/gcc/testsuite/gcc.dg/vect/pr65947-3.c index 1323ed0..98945ba 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-3.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-3.c @@ -51,5 +51,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */ /* { dg-final { scan-tree-dump-not "condition expression based on integer induction." "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-4.c b/gcc/testsuite/gcc.dg/vect/pr65947-4.c index d754b8d..695889d 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-4.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-4.c @@ -40,6 +40,6 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } } */ -/* { dg-final { scan-tree-dump-times "condition expression based on integer induction." 4 "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "condition expression based on integer induction." 4 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-5.c b/gcc/testsuite/gcc.dg/vect/pr65947-5.c index b2af501..04d9b38 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-5.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-5.c @@ -41,6 +41,6 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 1 "vect" { xfail { ! vect_max_reduc } } } } */ -/* { dg-final { scan-tree-dump "loop size is greater than data size" "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 1 "vect" } } */ +/* { dg-final { scan-tree-dump "loop size is greater than data size" "vect" } } */ /* { dg-final { scan-tree-dump-not "condition expression based on integer induction." "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-6.c b/gcc/testsuite/gcc.dg/vect/pr65947-6.c index 12dc852..caa4a14 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-6.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-6.c @@ -40,5 +40,5 @@ main (void) return 0; } -/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 2 "vect" } } */ /* { dg-final { scan-tree-dump-not "condition expression based on integer induction." "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-8.c b/gcc/testsuite/gcc.dg/vect/pr65947-8.c index 2931185..f0f1ac2 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-8.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-8.c @@ -42,4 +42,4 @@ main (void) } /* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" } } */ -/* { dg-final { scan-tree-dump "multiple types in double reduction or condition reduction" "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump "multiple types in double reduction or condition reduction" "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-9.c b/gcc/testsuite/gcc.dg/vect/pr65947-9.c index a43560b..d769af9 100644 --- a/gcc/testsuite/gcc.dg/vect/pr65947-9.c +++ b/gcc/testsuite/gcc.dg/vect/pr65947-9.c @@ -46,4 +46,4 @@ main () } /* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" } } */ -/* { dg-final { scan-tree-dump "loop size is greater than data size" "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump "loop size is greater than data size" "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-cond-2.c b/gcc/testsuite/gcc.dg/vect/vect-cond-2.c index 646eac1..094cfe7 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-cond-2.c +++ b/gcc/testsuite/gcc.dg/vect/vect-cond-2.c @@ -39,6 +39,4 @@ int main (void) return 0; } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { ! vect_max_reduc } } } } */ - - +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-pr69848.c b/gcc/testsuite/gcc.dg/vect/vect-pr69848.c index 779a657..c08f1e2 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-pr69848.c +++ b/gcc/testsuite/gcc.dg/vect/vect-pr69848.c @@ -34,4 +34,4 @@ int main (void) return 0; } -/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" { xfail { ! vect_max_reduc } } } } */ +/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" } } */ diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c index d601296..a7c3d3d 100644 --- a/gcc/tree-vect-loop.c +++ b/gcc/tree-vect-loop.c @@ -3772,6 +3772,18 @@ vect_model_reduction_cost (stmt_vec_info stmt_info, enum tree_code reduc_code, vect_epilogue); } } + else if (STMT_VINFO_VEC_REDUCTION_TYPE (stmt_info) == COND_REDUCTION) + { + unsigned nunits = TYPE_VECTOR_SUBPARTS (vectype); + /* Extraction of scalar elements. */ + epilogue_cost += add_stmt_cost (target_cost_data, 2 * nunits, + vec_to_scalar, stmt_info, 0, + vect_epilogue); + /* Scalar max reductions via COND_EXPR / MAX_EXPR. */ + epilogue_cost += add_stmt_cost (target_cost_data, 2 * nunits - 3, + scalar_stmt, stmt_info, 0, + vect_epilogue); + } else { int vec_size_in_bits = tree_to_uhwi (TYPE_SIZE (vectype)); @@ -3780,10 +3792,14 @@ vect_model_reduction_cost (stmt_vec_info stmt_info, enum tree_code reduc_code, int element_bitsize = tree_to_uhwi (bitsize); int nelements = vec_size_in_bits / element_bitsize; + if (code == COND_EXPR) + code = MAX_EXPR; + optab = optab_for_tree_code (code, vectype, optab_default); /* We have a whole vector shift available. */ - if (VECTOR_MODE_P (mode) + if (optab != unknown_optab + && VECTOR_MODE_P (mode) && optab_handler (optab, mode) != CODE_FOR_nothing && have_whole_vector_shift (mode)) { @@ -4424,7 +4440,8 @@ vect_create_epilog_for_reduction (vec vect_defs, gimple *stmt, else new_phi_result = PHI_RESULT (new_phis[0]); - if (STMT_VINFO_VEC_REDUCTION_TYPE (stmt_info) == COND_REDUCTION) + if (STMT_VINFO_VEC_REDUCTION_TYPE (stmt_info) == COND_REDUCTION + && reduc_code != ERROR_MARK) { /* For condition reductions, we have a vector (NEW_PHI_RESULT) containing various data values where the condition matched and another vector @@ -4536,6 +4553,70 @@ vect_create_epilog_for_reduction (vec vect_defs, gimple *stmt, gsi_insert_before (&exit_gsi, epilog_stmt, GSI_SAME_STMT); scalar_results.safe_push (new_temp); } + else if (STMT_VINFO_VEC_REDUCTION_TYPE (stmt_info) == COND_REDUCTION + && reduc_code == ERROR_MARK) + { + /* Condition redution without supported REDUC_MAX_EXPR. Generate + idx = 0; + idx_val = induction_index[0]; + val = data_reduc[0]; + for (idx = 0, val = init, i = 0; i < nelts; ++i) + if (induction_index[i] > idx_val) + val = data_reduc[i], idx_val = induction_index[i]; + return val; */ + + tree data_eltype = TREE_TYPE (TREE_TYPE (new_phi_result)); + tree idx_eltype = TREE_TYPE (TREE_TYPE (induction_index)); + unsigned HOST_WIDE_INT el_size = tree_to_uhwi (TYPE_SIZE (idx_eltype)); + unsigned HOST_WIDE_INT v_size + = el_size * TYPE_VECTOR_SUBPARTS (TREE_TYPE (induction_index)); + tree idx_val = NULL_TREE, val = NULL_TREE; + for (unsigned HOST_WIDE_INT off = 0; off < v_size; off += el_size) + { + tree old_idx_val = idx_val; + tree old_val = val; + idx_val = make_ssa_name (idx_eltype); + epilog_stmt = gimple_build_assign (idx_val, BIT_FIELD_REF, + build3 (BIT_FIELD_REF, idx_eltype, + induction_index, + bitsize_int (el_size), + bitsize_int (off))); + gsi_insert_before (&exit_gsi, epilog_stmt, GSI_SAME_STMT); + val = make_ssa_name (data_eltype); + epilog_stmt = gimple_build_assign (val, BIT_FIELD_REF, + build3 (BIT_FIELD_REF, + data_eltype, + new_phi_result, + bitsize_int (el_size), + bitsize_int (off))); + gsi_insert_before (&exit_gsi, epilog_stmt, GSI_SAME_STMT); + if (off != 0) + { + tree new_idx_val = idx_val; + tree new_val = val; + if (off != v_size - el_size) + { + new_idx_val = make_ssa_name (idx_eltype); + epilog_stmt = gimple_build_assign (new_idx_val, + MAX_EXPR, idx_val, + old_idx_val); + gsi_insert_before (&exit_gsi, epilog_stmt, GSI_SAME_STMT); + } + new_val = make_ssa_name (data_eltype); + epilog_stmt = gimple_build_assign (new_val, + COND_EXPR, + build2 (GT_EXPR, + boolean_type_node, + idx_val, + old_idx_val), + val, old_val); + gsi_insert_before (&exit_gsi, epilog_stmt, GSI_SAME_STMT); + idx_val = new_idx_val; + val = new_val; + } + } + scalar_results.safe_push (val); + } /* 2.3 Create the reduction code, using one of the three schemes described above. In SLP we simply need to extract all the elements from the @@ -4598,6 +4679,10 @@ vect_create_epilog_for_reduction (vec vect_defs, gimple *stmt, int vec_size_in_bits = tree_to_uhwi (TYPE_SIZE (vectype)); tree vec_temp; + /* COND reductions all do the final reduction with MAX_EXPR. */ + if (code == COND_EXPR) + code = MAX_EXPR; + /* Regardless of whether we have a whole vector shift, if we're emulating the operation via tree-vect-generic, we don't want to use it. Only the first round of the reduction is likely @@ -4763,6 +4848,22 @@ vect_create_epilog_for_reduction (vec vect_defs, gimple *stmt, /* Not SLP - we have one scalar to keep in SCALAR_RESULTS. */ scalar_results.safe_push (new_temp); } + + if (STMT_VINFO_VEC_REDUCTION_TYPE (stmt_info) + == INTEGER_INDUC_COND_REDUCTION) + { + /* Earlier we set the initial value to be zero. Check the result + and if it is zero then replace with the original initial + value. */ + tree zero = build_zero_cst (scalar_type); + tree zcompare = build2 (EQ_EXPR, boolean_type_node, new_temp, zero); + + tree tmp = make_ssa_name (new_scalar_dest); + epilog_stmt = gimple_build_assign (tmp, COND_EXPR, zcompare, + initial_def, new_temp); + gsi_insert_before (&exit_gsi, epilog_stmt, GSI_SAME_STMT); + scalar_results[0] = tmp; + } } vect_finalize_reduction: @@ -5639,21 +5740,6 @@ vectorizable_reduction (gimple *stmt, gimple_stmt_iterator *gsi, epilog_reduc_code = ERROR_MARK; } - - /* When epilog_reduc_code is ERROR_MARK then a reduction will be - generated in the epilog using multiple expressions. This does not - work for condition reductions. */ - if (epilog_reduc_code == ERROR_MARK - && (STMT_VINFO_VEC_REDUCTION_TYPE (stmt_info) - == INTEGER_INDUC_COND_REDUCTION - || STMT_VINFO_VEC_REDUCTION_TYPE (stmt_info) - == CONST_COND_REDUCTION)) - { - if (dump_enabled_p ()) - dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, - "no reduc code for scalar code.\n"); - return false; - } } else { @@ -5674,17 +5760,11 @@ vectorizable_reduction (gimple *stmt, gimple_stmt_iterator *gsi, cr_index_vector_type = build_vector_type (cr_index_scalar_type, TYPE_VECTOR_SUBPARTS (vectype_out)); - epilog_reduc_code = REDUC_MAX_EXPR; optab = optab_for_tree_code (REDUC_MAX_EXPR, cr_index_vector_type, optab_default); if (optab_handler (optab, TYPE_MODE (cr_index_vector_type)) - == CODE_FOR_nothing) - { - if (dump_enabled_p ()) - dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, - "reduc max op not supported by target.\n"); - return false; - } + != CODE_FOR_nothing) + epilog_reduc_code = REDUC_MAX_EXPR; } if ((double_reduc -- cgit v1.1 From 7d8c7b26c811748fc606085bf169dcd8a426eaf4 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 14:23:54 +0000 Subject: runtime: build testprogcgo with -pthread Building this test with gccgo requires an explicit -pthread option to be passed to the C compiler, so that it links against -lpthread. This test is not built today, but it will be soon with a future patch. Reviewed-on: https://go-review.googlesource.com/46451 From-SVN: r249555 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 17df499..d983939 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -f70ef19badafb85b1caa72b51b0082deb48d433a +bbc4f30a027ee09475d08aa4aeed1f2f7067e2e9 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 2a208bc2570b07b64deb1d549332e5d981c867bc Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 14:27:09 +0000 Subject: runtime: don't build test files that use SetCgoTraceback for gccgo The gofrontend doesn't support the runtime.SetCgoTraceback function, which is specifically for handling mixed Go and C tracebacks. Use a build tag to avoid compiling the runtime/testdata/testprogcgo files that refer to SetCgoTraceback. These files are not currently compiled anyhow, but they will be with a future gotools patch. Reviewed-on: https://go-review.googlesource.com/46452 From-SVN: r249556 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index d983939..42c8f85 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -bbc4f30a027ee09475d08aa4aeed1f2f7067e2e9 +e017833e4ce4a3bc3ba02eac4351b15c86157ec0 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From ed99905e1d89e84b74a07a55a46270d1f9f27991 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 14:28:57 +0000 Subject: runtime: adjust tests for gofrontend - don't run tests that depend on SetCgoTraceback - don't expect a '(' after the function name in a traceback - change the expected name of nested functions in a traceback These tests are not currently run, but they will be soon. Reviewed-on: https://go-review.googlesource.com/46453 From-SVN: r249557 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 42c8f85..cb902243 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -e017833e4ce4a3bc3ba02eac4351b15c86157ec0 +a81079a81b63714221674f07d13bedc768092f27 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From b92e4dff0a767a4e39dac6a012e381816ee5937a Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 14:31:16 +0000 Subject: runtime: rename _defer struct _panic field to panicStack The gc version of the _defer struct has a _panic field that has a completely different meaning. We are going to want that bring that new meaning into the gofrontend to improve panic reports with nested panic calls. Simplify that by first renaming the existing _panic field. Reviewed-on: https://go-review.googlesource.com/46454 From-SVN: r249558 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index cb902243..8ce4017 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -a81079a81b63714221674f07d13bedc768092f27 +a459f1fdfe0bd365bf2def730e1529052c6487fd The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From c8a47c4877889b42afc5e3804c0fc575770564f2 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 14:33:13 +0000 Subject: runtime: avoid write barriers when calling deferred function Calling a deferred function currently requires changing from a uintptr to the function code to a Go function value. That is done by setting the value of a func local variable using unsafe.Pointer. The local variable will always be on the stack. Adjust the code that sets the local variable to avoid generating a write barrier. A write barrier is never needed here. Also, for deferreturn, we must avoid write barriers entirely when called from a cgo function; that requires more than just this, but this is a start. The test for this is runtime tests that use the go tool; these are not currently run, but they will be in the future. Reviewed-on: https://go-review.googlesource.com/46455 From-SVN: r249559 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 8ce4017..a8dba360 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -a459f1fdfe0bd365bf2def730e1529052c6487fd +73b14da15ec731837ce2a45db658142bfbf5fe22 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From a055692a25c10bcd8fd90825cc39709f455335b2 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Thu, 22 Jun 2017 14:37:17 +0000 Subject: Support $SYSROOT for = in -I etc. * incpath.c (add_sysroot_to_chain): Allow for $SYSROOT prefix. * doc/cppdiropts.texi (-I @var{dir}): Document it. From-SVN: r249560 --- gcc/ChangeLog | 5 +++++ gcc/doc/cppdiropts.texi | 5 +++-- gcc/incpath.c | 13 ++++++++++--- 3 files changed, 18 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4b78674..a2340c0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-22 Rainer Orth + + * incpath.c (add_sysroot_to_chain): Allow for $SYSROOT prefix. + * doc/cppdiropts.texi (-I @var{dir}): Document it. + 2016-06-22 Richard Biener * tree-vect-loop.c (vect_model_reduction_cost): Handle diff --git a/gcc/doc/cppdiropts.texi b/gcc/doc/cppdiropts.texi index 1f72649..eee2b5c 100644 --- a/gcc/doc/cppdiropts.texi +++ b/gcc/doc/cppdiropts.texi @@ -22,8 +22,9 @@ for header files during preprocessing. @ifset cppmanual @xref{Search Path}. @end ifset -If @var{dir} begins with @samp{=}, then the @samp{=} is replaced -by the sysroot prefix; see @option{--sysroot} and @option{-isysroot}. +If @var{dir} begins with @samp{=} or @code{$SYSROOT}, then the @samp{=} +or @code{$SYSROOT} is replaced by the sysroot prefix; see +@option{--sysroot} and @option{-isysroot}. Directories specified with @option{-iquote} apply only to the quote form of the directive, @code{@w{#include "@var{file}"}}. diff --git a/gcc/incpath.c b/gcc/incpath.c index 98fe5ec..47942e2 100644 --- a/gcc/incpath.c +++ b/gcc/incpath.c @@ -314,7 +314,7 @@ remove_duplicates (cpp_reader *pfile, struct cpp_dir *head, } /* Add SYSROOT to any user-supplied paths in CHAIN starting with - "=". */ + "=" or "$SYSROOT". */ static void add_sysroot_to_chain (const char *sysroot, int chain) @@ -322,8 +322,15 @@ add_sysroot_to_chain (const char *sysroot, int chain) struct cpp_dir *p; for (p = heads[chain]; p != NULL; p = p->next) - if (p->name[0] == '=' && p->user_supplied_p) - p->name = concat (sysroot, p->name + 1, NULL); + { + if (p->user_supplied_p) + { + if (p->name[0] == '=') + p->name = concat (sysroot, p->name + 1, NULL); + if (strncmp (p->name, "$SYSROOT", strlen ("$SYSROOT")) == 0) + p->name = concat (sysroot, p->name + strlen ("$SYSROOT"), NULL); + } + } } /* Merge the four include chains together in the order quote, bracket, -- cgit v1.1 From 3b0ddadf74ec9c7aa404765ec50bb55d255dbec7 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 14:44:30 +0000 Subject: runtime: change some stack fields to uintptr Because of how gccgo implements cgo calls, the code in dropm may not have any write barriers. As a step toward implementing that, change the gcstack, gcnextsegment, and gcnextsp fields of the g struct to uintptr, so that assignments to them do not require write barriers. The gcinitialsp field remains unsafe.Pointer, as on 32-bit systems that do not support split stack it points to a heap allocated space used for the goroutine stack. The test for this is runtime tests like TestCgoCallbackGC, which are not run today but will be run with a future gotools patch. Reviewed-on: https://go-review.googlesource.com/46396 From-SVN: r249561 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index a8dba360..942752b 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -73b14da15ec731837ce2a45db658142bfbf5fe22 +b5c9fe259ec43f8079581c3bea0f1d12d85213a7 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From c016fd32fe7da1a8c97f96f7e9767e4e300b3d28 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 14:46:12 +0000 Subject: runtime: don't assume that _ = *s will panic if s is nil With the gc toolchain apparently var s *string _ = *s is enough to panic with a nil pointer dereference. The gccgo compiler will simply discard the dereference, which I think is a reasonable and acceptable optimization. Change the tests to use an exported variable instead. The tests are not currently run, but they will be with a later patch to gotools. Reviewed-on: https://go-review.googlesource.com/46450 From-SVN: r249562 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 942752b..296cd0f 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -b5c9fe259ec43f8079581c3bea0f1d12d85213a7 +8804c912363320e0c229c5a471fb6f4b9e5965e6 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From eaee472d05fea91e1dde0bb9347d179ebf1aafa3 Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Thu, 22 Jun 2017 16:50:23 +0200 Subject: profile-count.h (apply_probability, [...]): Fix checks for zero. * profile-count.h (apply_probability, apply_scale, probability_in): Fix checks for zero. From-SVN: r249563 --- gcc/ChangeLog | 5 +++++ gcc/profile-count.h | 19 ++++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a2340c0..0a3426e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-22 Jan Hubicka + + * profile-count.h (apply_probability, + apply_scale, probability_in): Fix checks for zero. + 2017-06-22 Rainer Orth * incpath.c (add_sysroot_to_chain): Allow for $SYSROOT prefix. diff --git a/gcc/profile-count.h b/gcc/profile-count.h index 42509c4..0f77e4e 100644 --- a/gcc/profile-count.h +++ b/gcc/profile-count.h @@ -255,7 +255,7 @@ public: profile_count apply_probability (int prob) const { gcc_checking_assert (prob >= 0 && prob <= REG_BR_PROB_BASE); - if (*this == profile_count::zero ()) + if (m_val == 0) return *this; if (!initialized_p ()) return profile_count::uninitialized (); @@ -267,24 +267,25 @@ public: /* Return *THIS * NUM / DEN. */ profile_count apply_scale (int64_t num, int64_t den) const { - if (*this == profile_count::zero ()) + if (m_val == 0) return *this; if (!initialized_p ()) return profile_count::uninitialized (); profile_count ret; + gcc_checking_assert (num >= 0 && den > 0); /* FIXME: shrink wrapping violates this sanity check. */ - gcc_checking_assert ((num >= 0 - && (num <= REG_BR_PROB_BASE - || den <= REG_BR_PROB_BASE) - && den > 0) || 1); + gcc_checking_assert ((num <= REG_BR_PROB_BASE + || den <= REG_BR_PROB_BASE) || 1); ret.m_val = RDIV (m_val * num, den); ret.m_quality = MIN (m_quality, count_adjusted); return ret; } profile_count apply_scale (profile_count num, profile_count den) const { - if (*this == profile_count::zero () || num == profile_count::zero ()) - return profile_count::zero (); + if (m_val == 0) + return *this; + if (num.m_val == 0) + return num; if (!initialized_p () || !num.initialized_p () || !den.initialized_p ()) return profile_count::uninitialized (); gcc_checking_assert (den > 0); @@ -306,7 +307,7 @@ public: OVERALL. */ int probability_in (profile_count overall) { - if (*this == profile_count::zero ()) + if (!m_val) return 0; if (!initialized_p () || !overall.initialized_p ()) return REG_BR_PROB_BASE / 2; -- cgit v1.1 From b8f70831bfbd1e9bdd989010ea114967bee0f34b Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 15:42:50 +0000 Subject: compiler: fix stale comment in lexer Remove stale comment in code that accepts "go:nowritebarrier" pragma. Update comment for "go:nowritebarrierrec". Reviewed-on: https://go-review.googlesource.com/46416 From-SVN: r249564 --- gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/lex.cc | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 296cd0f..dbff708 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -8804c912363320e0c229c5a471fb6f4b9e5965e6 +54d83c2d67c35ad4f622936d2fbf81c17354fff9 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. diff --git a/gcc/go/gofrontend/lex.cc b/gcc/go/gofrontend/lex.cc index e834c13..beb3652 100644 --- a/gcc/go/gofrontend/lex.cc +++ b/gcc/go/gofrontend/lex.cc @@ -1909,7 +1909,6 @@ Lex::skip_cpp_comment() // Applies to the next function. If the function needs to use // any write barriers, it should emit an error instead. // FIXME: Should only work when compiling the runtime package. - // FIXME: Not implemented. this->pragmas_ |= GOPRAGMA_NOWRITEBARRIER; } else if (verb == "go:nowritebarrierrec") @@ -1918,7 +1917,7 @@ Lex::skip_cpp_comment() // function that it calls, needs to use any write barriers, it // should emit an error instead. // FIXME: Should only work when compiling the runtime package. - // FIXME: Not implemented. + // FIXME: currently treated the same as go:nowritebarrier this->pragmas_ |= GOPRAGMA_NOWRITEBARRIERREC; } else if (verb == "go:cgo_unsafe_args") -- cgit v1.1 From 47f68dc2318a708b375768a09ae42833109e0bce Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 15:46:47 +0000 Subject: runtime: make NumGoroutine wait for system goroutines to register In libgo system goroutines register themselves after they start. That means that there is a small race between the goroutine being seen by the scheduler and the scheduler knowing that the goroutine is a system goroutine. That in turn means that runtime.NumGoroutines can overestimate the number of goroutines at times. This patch fixes the overestimate by counting the number of system goroutines waiting to start, and pausing NumGoroutines until those goroutines have all registered. This is kind of a lot of mechanism for this not very important problem, but I couldn't think of a better approach. The test for this is TestNumGoroutine in runtime/proc_test.go. The test is not currently run, but it will be soon. Reviewed-on: https://go-review.googlesource.com/46457 From-SVN: r249565 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index dbff708..ccc7919 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -54d83c2d67c35ad4f622936d2fbf81c17354fff9 +681c8a7b0a9d52c0b81e7a4b1c55fe65ed889573 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 13f752b27354d0b8f7ff0148973c6b478e6fdd9e Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Thu, 22 Jun 2017 11:18:05 -0600 Subject: aarch64.c (aarch64_emit_probe_stack_range): Handle frame sizes that do not satisfy aarch64_uimm12_shift. * config/aarch64/aarch64.c (aarch64_emit_probe_stack_range): Handle frame sizes that do not satisfy aarch64_uimm12_shift. * gcc.c-torture/compile/stack-check-1.c: New test. From-SVN: r249566 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64.c | 18 +++++++++++++----- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.c-torture/compile/stack-check-1.c | 2 ++ 4 files changed, 24 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/compile/stack-check-1.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a3426e..03a824f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-22 Jeff Law + + * config/aarch64/aarch64.c (aarch64_emit_probe_stack_range): Handle + frame sizes that do not satisfy aarch64_uimm12_shift. + 2017-06-22 Jan Hubicka * profile-count.h (apply_probability, diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 3364a02..95592f9 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -2766,11 +2766,19 @@ aarch64_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size) plus_constant (Pmode, stack_pointer_rtx, -first)); /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */ - emit_set_insn (reg2, - plus_constant (Pmode, stack_pointer_rtx, - -(first + rounded_size))); - - + HOST_WIDE_INT adjustment = - (first + rounded_size); + if (! aarch64_uimm12_shift (adjustment)) + { + aarch64_internal_mov_immediate (reg2, GEN_INT (adjustment), + true, Pmode); + emit_set_insn (reg2, gen_rtx_PLUS (Pmode, stack_pointer_rtx, reg2)); + } + else + { + emit_set_insn (reg2, + plus_constant (Pmode, stack_pointer_rtx, adjustment)); + } + /* Step 3: the loop do diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 641e412..e162386 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-22 Jeff Law + + * gcc.c-torture/compile/stack-check-1.c: New test. + 2016-06-22 Richard Biener * gcc.dg/vect/pr65947-1.c: Remove xfail. diff --git a/gcc/testsuite/gcc.c-torture/compile/stack-check-1.c b/gcc/testsuite/gcc.c-torture/compile/stack-check-1.c new file mode 100644 index 0000000..4058eb5 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/stack-check-1.c @@ -0,0 +1,2 @@ +/* { dg-additional-options "-fstack-check" } */ +#include "20031023-1.c" -- cgit v1.1 From 84c0088f38ce49f390401d11a581cd1a57a008d5 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Thu, 22 Jun 2017 18:40:56 +0000 Subject: Reorder IDENTIFIER flags Reorder IDENTIFIER flags gcc/cp/ * cp-tree.h (enum cp_identifier_kind): New. (IDENTIFIER_KIND_BIT_0, IDENTIFIER_KIND_BIT_1, IDENTIFIER_KIND_BIT_2): New. (IDENTIFIER_MARKED): Move to TREE_LANG_FLAG_4. (IDENTIFIER_VIRTUAL_P, IDENTIFIER_REPO_CHOSEN): Add IDENTIFIER_CHECK. (C_IS_RESERVED_WORD): Replace with ... (IDENTIFIER_KEYWORD_P): ... this. (IDENTIFIER_CTOR_OR_DTOR_P): Replace with ... (IDENTIFIER_CDTOR_P): ... this. (IDENTIFIER_CTOR_P, IDENTIFIER_DTOR_P): New. (IDENTIFIER_OPNAME_P): Replace with ... (IDENTIFIER_ANY_OP_P): ... this. (IDENTIFIER_ASSIGN_OP_P): New. (IDENTIFIER_TYPENAME_P): Replace with ... (IDENTIFIER_CONV_OP_P): ... this. (NEW_DELETE_OPNAME_P): Replace with ... (IDENTIFIER_NEWDEL_OP_P): ... this. (DECL_CONV_FN_P, DECL_OVERLOADED_OPERATOR_P): Adjust. (get_identifier_kind_name, set_identifier_kind): Declare. * lex.c (get_identifier_kind_name, set_identifier_kind): New. (init_operators): Adjust to avoid keywords, use set_identifier_kind. Copy TYPE_EXPR slot. (init_reswords): Call set_identifier_kind. (unqualified_name_lookup_error): Adjust. * operators.def (TYPE_EXPR): Remove. * decl.c (struct predefined_identifier): Move into ... (initialize_predefined_identifiers): ... here. Call set_identifier_kind. (grokfndecl, check_var_type, grokdeclarator): Adjust. (grok_op_properties): Use IDENTIFIER_ANY_ASSIGN_OP to halve search space. Adjust. * call.c (name_as_c_string): Adjust. (build_new_method_call_1): Likewise. * cp-cilkplus.c (is_conversion_operator_function_decl_p): Likewise. * cxx-pretty-print.c (pp_cxx_unqualified_id): Adjust. * dump.c (cp_dump_tree): Adjust. * error.c (dump_decl_name): Adjust. * mangle.c (write_unqualified_id, write_member_name) write_expression): Adjust. (mangle_conv_op_name_for_type): Use set_identifier_kind. * name-lookup.c (do_class_using_decl): Adjust. (lookup_name_fuzzy, lookup_name_real_1): Likewise. * parser.c (cp_lexer_get_preprocessor_token) cp_parser_direct_declarator): Likewise. * pt.c (push_template_decl_real, tsubst_decl, tsubst_baselink) tsubst_copy, tsubst_copy_and_build): Adjust. * ptree.c (cxx_print_identifier): Print identifier kind. * search.c (lookup_field_r, lookup_member) lookup_fnfields_idx_nolazy): Adjust. * semantics.c (finish_id_expression): Adjust.. * typeck.c (cp_build_addr_expr_1): Adjust. From-SVN: r249571 --- gcc/cp/ChangeLog | 56 +++++++++++++ gcc/cp/call.c | 12 ++- gcc/cp/cp-cilkplus.c | 2 +- gcc/cp/cp-tree.h | 125 +++++++++++++++++++---------- gcc/cp/cxx-pretty-print.c | 2 +- gcc/cp/decl.c | 195 +++++++++++++++++++++------------------------- gcc/cp/dump.c | 4 +- gcc/cp/error.c | 2 +- gcc/cp/lex.c | 86 +++++++++++++------- gcc/cp/mangle.c | 27 +++---- gcc/cp/name-lookup.c | 6 +- gcc/cp/operators.def | 15 ++-- gcc/cp/parser.c | 5 +- gcc/cp/pt.c | 14 ++-- gcc/cp/ptree.c | 3 +- gcc/cp/search.c | 6 +- gcc/cp/semantics.c | 2 +- gcc/cp/typeck.c | 2 +- 18 files changed, 340 insertions(+), 224 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index c11cbe4..6acbe8b 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,59 @@ +2017-06-22 Nathan Sidwell + + Reorder IDENTIFIER flags + gcc/cp/ + * cp-tree.h (enum cp_identifier_kind): New. + (IDENTIFIER_KIND_BIT_0, IDENTIFIER_KIND_BIT_1, + IDENTIFIER_KIND_BIT_2): New. + (IDENTIFIER_MARKED): Move to TREE_LANG_FLAG_4. + (IDENTIFIER_VIRTUAL_P, IDENTIFIER_REPO_CHOSEN): Add IDENTIFIER_CHECK. + (C_IS_RESERVED_WORD): Replace with ... + (IDENTIFIER_KEYWORD_P): ... this. + (IDENTIFIER_CTOR_OR_DTOR_P): Replace with ... + (IDENTIFIER_CDTOR_P): ... this. + (IDENTIFIER_CTOR_P, IDENTIFIER_DTOR_P): New. + (IDENTIFIER_OPNAME_P): Replace with ... + (IDENTIFIER_ANY_OP_P): ... this. + (IDENTIFIER_ASSIGN_OP_P): New. + (IDENTIFIER_TYPENAME_P): Replace with ... + (IDENTIFIER_CONV_OP_P): ... this. + (NEW_DELETE_OPNAME_P): Replace with ... + (IDENTIFIER_NEWDEL_OP_P): ... this. + (DECL_CONV_FN_P, DECL_OVERLOADED_OPERATOR_P): Adjust. + (get_identifier_kind_name, set_identifier_kind): Declare. + * lex.c (get_identifier_kind_name, set_identifier_kind): New. + (init_operators): Adjust to avoid keywords, use + set_identifier_kind. Copy TYPE_EXPR slot. + (init_reswords): Call set_identifier_kind. + (unqualified_name_lookup_error): Adjust. + * operators.def (TYPE_EXPR): Remove. + * decl.c (struct predefined_identifier): Move into ... + (initialize_predefined_identifiers): ... here. Call + set_identifier_kind. + (grokfndecl, check_var_type, grokdeclarator): Adjust. + (grok_op_properties): Use IDENTIFIER_ANY_ASSIGN_OP to halve search + space. Adjust. + * call.c (name_as_c_string): Adjust. + (build_new_method_call_1): Likewise. + * cp-cilkplus.c (is_conversion_operator_function_decl_p): Likewise. + * cxx-pretty-print.c (pp_cxx_unqualified_id): Adjust. + * dump.c (cp_dump_tree): Adjust. + * error.c (dump_decl_name): Adjust. + * mangle.c (write_unqualified_id, write_member_name, + write_expression): Adjust. + (mangle_conv_op_name_for_type): Use set_identifier_kind. + * name-lookup.c (do_class_using_decl): Adjust. + (lookup_name_fuzzy, lookup_name_real_1): Likewise. + * parser.c (cp_lexer_get_preprocessor_token, + cp_parser_direct_declarator): Likewise. + * pt.c (push_template_decl_real, tsubst_decl, tsubst_baselink, + tsubst_copy, tsubst_copy_and_build): Adjust. + * ptree.c (cxx_print_identifier): Print identifier kind. + * search.c (lookup_field_r, lookup_member, + lookup_fnfields_idx_nolazy): Adjust. + * semantics.c (finish_id_expression): Adjust.. + * typeck.c (cp_build_addr_expr_1): Adjust. + 2017-06-21 Jakub Jelinek PR c++/81154 diff --git a/gcc/cp/call.c b/gcc/cp/call.c index b56da35..2fc29da 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -8884,21 +8884,19 @@ name_as_c_string (tree name, tree type, bool *free_p) /* Assume that we will not allocate memory. */ *free_p = false; /* Constructors and destructors are special. */ - if (IDENTIFIER_CTOR_OR_DTOR_P (name)) + if (IDENTIFIER_CDTOR_P (name)) { pretty_name = CONST_CAST (char *, identifier_to_locale (IDENTIFIER_POINTER (constructor_name (type)))); /* For a destructor, add the '~'. */ - if (name == complete_dtor_identifier - || name == base_dtor_identifier - || name == deleting_dtor_identifier) + if (IDENTIFIER_DTOR_P (name)) { pretty_name = concat ("~", pretty_name, NULL); /* Remember that we need to free the memory allocated. */ *free_p = true; } } - else if (IDENTIFIER_TYPENAME_P (name)) + else if (IDENTIFIER_CONV_OP_P (name)) { pretty_name = concat ("operator ", type_as_string_translate (TREE_TYPE (name), @@ -9015,7 +9013,7 @@ build_new_method_call_1 (tree instance, tree fns, vec **args, pointer if this is a call to a base-class constructor or destructor. */ skip_first_for_error = false; - if (IDENTIFIER_CTOR_OR_DTOR_P (name)) + if (IDENTIFIER_CDTOR_P (name)) { /* Callers should explicitly indicate whether they want to construct the complete object or just the part without virtual bases. */ @@ -9143,7 +9141,7 @@ build_new_method_call_1 (tree instance, tree fns, vec **args, { tree arglist = build_tree_list_vec (user_args); tree errname = name; - if (IDENTIFIER_CTOR_OR_DTOR_P (errname)) + if (IDENTIFIER_CDTOR_P (errname)) { tree fn = DECL_ORIGIN (OVL_FIRST (fns)); errname = DECL_NAME (fn); diff --git a/gcc/cp/cp-cilkplus.c b/gcc/cp/cp-cilkplus.c index 7c66448..5ccf5d3 100644 --- a/gcc/cp/cp-cilkplus.c +++ b/gcc/cp/cp-cilkplus.c @@ -36,7 +36,7 @@ is_conversion_operator_function_decl_p (tree t) if (TREE_CODE (t) != FUNCTION_DECL) return false; - return DECL_NAME (t) && IDENTIFIER_TYPENAME_P (DECL_NAME (t)); + return DECL_CONV_FN_P (t); } /* Recursively traverse EXP to search for a CILK_SPAWN_STMT subtree. diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 6b27745..40c113b 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -298,7 +298,7 @@ extern GTY(()) tree cp_global_trees[CPTI_MAX]; #include "name-lookup.h" /* Usage of TREE_LANG_FLAG_?: - 0: IDENTIFIER_MARKED (IDENTIFIER_NODEs) + 0: IDENTIFIER_KIND_BIT_0 (in IDENTIFIER_NODE) NEW_EXPR_USE_GLOBAL (in NEW_EXPR). COND_EXPR_IS_VEC_DELETE (in COND_EXPR). DELETE_EXPR_USE_GLOBAL (in DELETE_EXPR). @@ -339,7 +339,7 @@ extern GTY(()) tree cp_global_trees[CPTI_MAX]; IF_STMT_CONSTEXPR_P (IF_STMT) TEMPLATE_TYPE_PARM_FOR_CLASS (TEMPLATE_TYPE_PARM) DECL_NAMESPACE_INLINE_P (in NAMESPACE_DECL) - 1: IDENTIFIER_VIRTUAL_P (in IDENTIFIER_NODE) + 1: IDENTIFIER_KIND_BIT_1 (in IDENTIFIER_NODE) TI_PENDING_TEMPLATE_FLAG. TEMPLATE_PARMS_FOR_INLINE. DELETE_EXPR_USE_VEC (in DELETE_EXPR). @@ -357,7 +357,7 @@ extern GTY(()) tree cp_global_trees[CPTI_MAX]; TINFO_USED_TEMPLATE_ID (in TEMPLATE_INFO) PACK_EXPANSION_SIZEOF_P (in *_PACK_EXPANSION) OVL_USING_P (in OVERLOAD) - 2: IDENTIFIER_OPNAME_P (in IDENTIFIER_NODE) + 2: IDENTIFIER_KIND_BIT_2 (in IDENTIFIER_NODE) ICS_THIS_FLAG (in _CONV) DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (in VAR_DECL) STATEMENT_LIST_TRY_BLOCK (in STATEMENT_LIST) @@ -372,21 +372,20 @@ extern GTY(()) tree cp_global_trees[CPTI_MAX]; 3: (TREE_REFERENCE_EXPR) (in NON_LVALUE_EXPR) (commented-out). ICS_BAD_FLAG (in _CONV) FN_TRY_BLOCK_P (in TRY_BLOCK) - IDENTIFIER_CTOR_OR_DTOR_P (in IDENTIFIER_NODE) BIND_EXPR_BODY_BLOCK (in BIND_EXPR) DECL_NON_TRIVIALLY_INITIALIZED_P (in VAR_DECL) CALL_EXPR_ORDERED_ARGS (in CALL_EXPR, AGGR_INIT_EXPR) DECLTYPE_FOR_REF_CAPTURE (in DECLTYPE_TYPE) CONSTUCTOR_C99_COMPOUND_LITERAL (in CONSTRUCTOR) OVL_NESTED_P (in OVERLOAD) - 4: TREE_HAS_CONSTRUCTOR (in INDIRECT_REF, SAVE_EXPR, CONSTRUCTOR, + 4: IDENTIFIER_MARKED (IDENTIFIER_NODEs) + TREE_HAS_CONSTRUCTOR (in INDIRECT_REF, SAVE_EXPR, CONSTRUCTOR, CALL_EXPR, or FIELD_DECL). - IDENTIFIER_TYPENAME_P (in IDENTIFIER_NODE) DECL_TINFO_P (in VAR_DECL) FUNCTION_REF_QUALIFIED (in FUNCTION_TYPE, METHOD_TYPE) OVL_LOOKUP_P (in OVERLOAD) LOOKUP_FOUND_P (in RECORD_TYPE, UNION_TYPE, NAMESPACE_DECL) - 5: C_IS_RESERVED_WORD (in IDENTIFIER_NODE) + 5: IDENTIFIER_VIRTUAL_P (in IDENTIFIER_NODE) DECL_VTABLE_OR_VTT_P (in VAR_DECL) FUNCTION_RVALUE_QUALIFIED (in FUNCTION_TYPE, METHOD_TYPE) CALL_EXPR_REVERSE_ARGS (in CALL_EXPR, AGGR_INIT_EXPR) @@ -566,11 +565,6 @@ struct default_hash_traits static void remove (value_type) { gcc_unreachable (); } }; -/* In an IDENTIFIER_NODE, nonzero if this identifier is actually a - keyword. C_RID_CODE (node) is then the RID_* value of the keyword. */ - -#define C_IS_RESERVED_WORD(ID) TREE_LANG_FLAG_5 (ID) - #define LANG_IDENTIFIER_CAST(NODE) \ ((struct lang_identifier*)IDENTIFIER_NODE_CHECK (NODE)) @@ -987,29 +981,89 @@ enum GTY(()) abstract_class_use { #define SET_IDENTIFIER_LABEL_VALUE(NODE, VALUE) \ IDENTIFIER_LABEL_VALUE (NODE) = (VALUE) -/* Nonzero if this identifier is used as a virtual function name somewhere - (optimizes searches). */ -#define IDENTIFIER_VIRTUAL_P(NODE) TREE_LANG_FLAG_1 (NODE) +/* Kinds of identifiers. Values are carefully chosen. */ +enum cp_identifier_kind { + cik_normal = 0, /* Not a special identifier. */ + cik_keyword = 1, /* A keyword. */ + cik_ctor = 2, /* Constructor (in-chg, complete or base). */ + cik_dtor = 3, /* Destructor (in-chg, deleting, complete or + base). */ + cik_simple_op = 4, /* Non-assignment operator name. */ + cik_newdel_op = 5, /* New or delete operator name. */ + cik_assign_op = 6, /* An assignment operator name. */ + cik_conv_op = 7, /* Conversion operator name. */ + cik_max +}; -/* Nonzero if this identifier is the prefix for a mangled C++ operator - name. */ -#define IDENTIFIER_OPNAME_P(NODE) TREE_LANG_FLAG_2 (NODE) +/* Kind bits. */ +#define IDENTIFIER_KIND_BIT_0(NODE) \ + TREE_LANG_FLAG_0 (IDENTIFIER_NODE_CHECK (NODE)) +#define IDENTIFIER_KIND_BIT_1(NODE) \ + TREE_LANG_FLAG_1 (IDENTIFIER_NODE_CHECK (NODE)) +#define IDENTIFIER_KIND_BIT_2(NODE) \ + TREE_LANG_FLAG_2 (IDENTIFIER_NODE_CHECK (NODE)) -/* Nonzero if this identifier is the name of a type-conversion - operator. */ -#define IDENTIFIER_TYPENAME_P(NODE) \ - TREE_LANG_FLAG_4 (NODE) +/* Used by various search routines. */ +#define IDENTIFIER_MARKED(NODE) \ + TREE_LANG_FLAG_4 (IDENTIFIER_NODE_CHECK (NODE)) -/* Nonzero if this identifier is the name of a constructor or - destructor. */ -#define IDENTIFIER_CTOR_OR_DTOR_P(NODE) \ - TREE_LANG_FLAG_3 (NODE) +/* Nonzero if this identifier is used as a virtual function name somewhere + (optimizes searches). */ +#define IDENTIFIER_VIRTUAL_P(NODE) \ + TREE_LANG_FLAG_5 (IDENTIFIER_NODE_CHECK (NODE)) /* True iff NAME is the DECL_ASSEMBLER_NAME for an entity with vague linkage which the prelinker has assigned to this translation unit. */ #define IDENTIFIER_REPO_CHOSEN(NAME) \ - (TREE_LANG_FLAG_6 (NAME)) + (TREE_LANG_FLAG_6 (IDENTIFIER_NODE_CHECK (NAME))) + +/* True if this identifier is a reserved word. C_RID_CODE (node) is + then the RID_* value of the keyword. Value 1. */ +#define IDENTIFIER_KEYWORD_P(NODE) \ + ((!IDENTIFIER_KIND_BIT_2 (NODE)) \ + & (!IDENTIFIER_KIND_BIT_1 (NODE)) \ + & IDENTIFIER_KIND_BIT_0 (NODE)) + +/* True if this identifier is the name of a constructor or + destructor. Value 2 or 3. */ +#define IDENTIFIER_CDTOR_P(NODE) \ + ((!IDENTIFIER_KIND_BIT_2 (NODE)) \ + & IDENTIFIER_KIND_BIT_1 (NODE)) + +/* True if this identifier is the name of a constructor. Value 2. */ +#define IDENTIFIER_CTOR_P(NODE) \ + (IDENTIFIER_CDTOR_P(NODE) \ + & (!IDENTIFIER_KIND_BIT_0 (NODE))) + +/* True if this identifier is the name of a destructor. Value 3. */ +#define IDENTIFIER_DTOR_P(NODE) \ + (IDENTIFIER_CDTOR_P(NODE) \ + & IDENTIFIER_KIND_BIT_0 (NODE)) + +/* True if this identifier is for any operator name (including + conversions). Value 4, 5, 6 or 7. */ +#define IDENTIFIER_ANY_OP_P(NODE) \ + (IDENTIFIER_KIND_BIT_2 (NODE)) + +/* True if this identifier is for new or delete operator. Value 5. */ +#define IDENTIFIER_NEWDEL_OP_P(NODE) \ + (IDENTIFIER_KIND_BIT_2 (NODE) \ + & (!IDENTIFIER_KIND_BIT_1 (NODE)) \ + & IDENTIFIER_KIND_BIT_0 (NODE)) + +/* True if this identifier is for any assignment. Values 6. */ +#define IDENTIFIER_ASSIGN_OP_P(NODE) \ + (IDENTIFIER_KIND_BIT_2 (NODE) \ + & IDENTIFIER_KIND_BIT_1 (NODE) \ + & (!IDENTIFIER_KIND_BIT_0 (NODE))) + +/* True if this identifier is the name of a type-conversion + operator. Value 7. */ +#define IDENTIFIER_CONV_OP_P(NODE) \ + (IDENTIFIER_KIND_BIT_2 (NODE) \ + & IDENTIFIER_KIND_BIT_1 (NODE) \ + & IDENTIFIER_KIND_BIT_0 (NODE)) /* In a RECORD_TYPE or UNION_TYPE, nonzero if any component is read-only. */ #define C_TYPE_FIELDS_READONLY(TYPE) \ @@ -1718,14 +1772,6 @@ struct GTY(()) language_function { #define current_function_auto_return_pattern \ (cp_function_chain->x_auto_return_pattern) -/* True if NAME is the IDENTIFIER_NODE for an overloaded "operator - new" or "operator delete". */ -#define NEW_DELETE_OPNAME_P(NAME) \ - ((NAME) == cp_operator_id (NEW_EXPR) \ - || (NAME) == cp_operator_id (VEC_NEW_EXPR) \ - || (NAME) == cp_operator_id (DELETE_EXPR) \ - || (NAME) == cp_operator_id (VEC_DELETE_EXPR)) - #define cp_operator_id(CODE) \ (operator_name_info[(int) (CODE)].identifier) #define cp_assignment_operator_id(CODE) \ @@ -2313,9 +2359,6 @@ struct GTY(()) lang_type { /* Nonzero if this BINFO is a primary base class. */ #define BINFO_PRIMARY_P(NODE) BINFO_FLAG_5(NODE) - -/* Used by various search routines. */ -#define IDENTIFIER_MARKED(NODE) TREE_LANG_FLAG_0 (NODE) /* A vec of the vcall indices associated with the class NODE. The PURPOSE of each element is a FUNCTION_DECL for a virtual @@ -2766,7 +2809,7 @@ struct GTY(()) lang_decl { /* Nonzero if NODE is a user-defined conversion operator. */ #define DECL_CONV_FN_P(NODE) \ - (DECL_NAME (NODE) && IDENTIFIER_TYPENAME_P (DECL_NAME (NODE))) + (DECL_NAME (NODE) && IDENTIFIER_CONV_OP_P (DECL_NAME (NODE))) /* If FN is a conversion operator, the type to which it converts. Otherwise, NULL_TREE. */ @@ -2800,7 +2843,7 @@ struct GTY(()) lang_decl { value of ERROR_MARK is zero, this macro can be used as a predicate to test whether or not NODE is an overloaded operator. */ #define DECL_OVERLOADED_OPERATOR_P(NODE) \ - (IDENTIFIER_OPNAME_P (DECL_NAME (NODE)) \ + (IDENTIFIER_ANY_OP_P (DECL_NAME (NODE)) \ ? LANG_DECL_FN_CHECK (NODE)->operator_code : ERROR_MARK) /* Nonzero if NODE is an assignment operator (including += and such). */ @@ -6305,6 +6348,8 @@ extern tree copy_decl (tree CXX_MEM_STAT_INFO); extern tree copy_type (tree CXX_MEM_STAT_INFO); extern tree cxx_make_type (enum tree_code); extern tree make_class_type (enum tree_code); +extern const char *get_identifier_kind_name (tree); +extern void set_identifier_kind (tree, cp_identifier_kind); extern bool cxx_init (void); extern void cxx_finish (void); extern bool in_main_input_context (void); diff --git a/gcc/cp/cxx-pretty-print.c b/gcc/cp/cxx-pretty-print.c index b74a56f..5398e3d 100644 --- a/gcc/cp/cxx-pretty-print.c +++ b/gcc/cp/cxx-pretty-print.c @@ -159,7 +159,7 @@ pp_cxx_unqualified_id (cxx_pretty_printer *pp, tree t) case IDENTIFIER_NODE: if (t == NULL) pp->translate_string (""); - else if (IDENTIFIER_TYPENAME_P (t)) + else if (IDENTIFIER_CONV_OP_P (t)) pp_cxx_conversion_function_id (pp, t); else { diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index 7c34489..b0a34de 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -3948,62 +3948,56 @@ record_unknown_type (tree type, const char* name) SET_TYPE_MODE (type, TYPE_MODE (void_type_node)); } -/* A string for which we should create an IDENTIFIER_NODE at - startup. */ - -struct predefined_identifier -{ - /* The name of the identifier. */ - const char *const name; - /* The place where the IDENTIFIER_NODE should be stored. */ - tree *const node; - /* Nonzero if this is the name of a constructor or destructor. */ - const int ctor_or_dtor_p; -}; - /* Create all the predefined identifiers. */ static void initialize_predefined_identifiers (void) { - const predefined_identifier *pid; + struct predefined_identifier + { + const char *name; /* Name. */ + tree *node; /* Node to store it in. */ + cp_identifier_kind kind; /* Kind of identifier. */ + }; /* A table of identifiers to create at startup. */ static const predefined_identifier predefined_identifiers[] = { - { "C++", &lang_name_cplusplus, 0 }, - { "C", &lang_name_c, 0 }, + {"C++", &lang_name_cplusplus, cik_normal}, + {"C", &lang_name_c, cik_normal}, /* Some of these names have a trailing space so that it is impossible for them to conflict with names written by users. */ - { "__ct ", &ctor_identifier, 1 }, - { "__base_ctor ", &base_ctor_identifier, 1 }, - { "__comp_ctor ", &complete_ctor_identifier, 1 }, - { "__dt ", &dtor_identifier, 1 }, - { "__comp_dtor ", &complete_dtor_identifier, 1 }, - { "__base_dtor ", &base_dtor_identifier, 1 }, - { "__deleting_dtor ", &deleting_dtor_identifier, 1 }, - { IN_CHARGE_NAME, &in_charge_identifier, 0 }, - { THIS_NAME, &this_identifier, 0 }, - { VTABLE_DELTA_NAME, &delta_identifier, 0 }, - { VTABLE_PFN_NAME, &pfn_identifier, 0 }, - { "_vptr", &vptr_identifier, 0 }, - { "__vtt_parm", &vtt_parm_identifier, 0 }, - { "::", &global_identifier, 0 }, - { "std", &std_identifier, 0 }, + {"__ct ", &ctor_identifier, cik_ctor}, + {"__base_ctor ", &base_ctor_identifier, cik_ctor}, + {"__comp_ctor ", &complete_ctor_identifier, cik_ctor}, + {"__dt ", &dtor_identifier, cik_dtor}, + {"__comp_dtor ", &complete_dtor_identifier, cik_dtor}, + {"__base_dtor ", &base_dtor_identifier, cik_dtor}, + {"__deleting_dtor ", &deleting_dtor_identifier, cik_dtor}, + {IN_CHARGE_NAME, &in_charge_identifier, cik_normal}, + {THIS_NAME, &this_identifier, cik_normal}, + {VTABLE_DELTA_NAME, &delta_identifier, cik_normal}, + {VTABLE_PFN_NAME, &pfn_identifier, cik_normal}, + {"_vptr", &vptr_identifier, cik_normal}, + {"__vtt_parm", &vtt_parm_identifier, cik_normal}, + {"::", &global_identifier, cik_normal}, + {"std", &std_identifier, cik_normal}, /* The demangler expects anonymous namespaces to be called something starting with '_GLOBAL__N_'. It no longer needs to be unique to the TU. */ - { "_GLOBAL__N_1", &anon_identifier, 0 }, - { "auto", &auto_identifier, 0 }, - { "decltype(auto)", &decltype_auto_identifier, 0 }, - { "initializer_list", &init_list_identifier, 0 }, - { NULL, NULL, 0 } + {"_GLOBAL__N_1", &anon_identifier, cik_normal}, + {"auto", &auto_identifier, cik_normal}, + {"decltype(auto)", &decltype_auto_identifier, cik_normal}, + {"initializer_list", &init_list_identifier, cik_normal}, + {NULL, NULL, cik_normal} }; - for (pid = predefined_identifiers; pid->name; ++pid) + for (const predefined_identifier *pid = predefined_identifiers; + pid->name; ++pid) { *pid->node = get_identifier (pid->name); - if (pid->ctor_or_dtor_p) - IDENTIFIER_CTOR_OR_DTOR_P (*pid->node) = 1; + /* Some of these identifiers already have a special kind. */ + if (pid->kind != cik_normal) + set_identifier_kind (*pid->node, pid->kind); } } @@ -8721,7 +8715,7 @@ grokfndecl (tree ctype, error_at (location, "deduction guide %qD must not have a function body", decl); } - else if (IDENTIFIER_OPNAME_P (DECL_NAME (decl)) + else if (IDENTIFIER_ANY_OP_P (DECL_NAME (decl)) && !grok_op_properties (decl, /*complain=*/true)) return NULL_TREE; else if (UDLIT_OPER_P (DECL_NAME (decl))) @@ -9773,7 +9767,7 @@ check_var_type (tree identifier, tree type) error ("unnamed variable or field declared void"); else if (identifier_p (identifier)) { - gcc_assert (!IDENTIFIER_OPNAME_P (identifier)); + gcc_assert (!IDENTIFIER_ANY_OP_P (identifier)); error ("variable or field %qE declared void", identifier); } else @@ -10114,12 +10108,7 @@ grokdeclarator (const cp_declarator *declarator, dname = fns; if (!identifier_p (dname)) - { - if (variable_template_p (dname)) - dname = DECL_NAME (dname); - else - dname = OVL_NAME (dname); - } + dname = OVL_NAME (dname); } /* Fall through. */ @@ -10127,13 +10116,13 @@ grokdeclarator (const cp_declarator *declarator, if (identifier_p (decl)) dname = decl; - if (C_IS_RESERVED_WORD (dname)) + if (IDENTIFIER_KEYWORD_P (dname)) { error ("declarator-id missing; using reserved word %qD", dname); name = identifier_to_locale (IDENTIFIER_POINTER (dname)); } - else if (!IDENTIFIER_TYPENAME_P (dname)) + else if (!IDENTIFIER_CONV_OP_P (dname)) name = identifier_to_locale (IDENTIFIER_POINTER (dname)); else { @@ -10192,26 +10181,27 @@ grokdeclarator (const cp_declarator *declarator, return error_mark_node; } - if (dname - && identifier_p (dname) - && UDLIT_OPER_P (dname) - && innermost_code != cdk_function) - { - error ("declaration of %qD as non-function", dname); - return error_mark_node; - } - - if (dname && IDENTIFIER_OPNAME_P (dname)) + if (dname && identifier_p (dname)) { - if (typedef_p) + if (UDLIT_OPER_P (dname) + && innermost_code != cdk_function) { - error ("declaration of %qD as %", dname); + error ("declaration of %qD as non-function", dname); return error_mark_node; } - else if (decl_context == PARM || decl_context == CATCHPARM) + + if (IDENTIFIER_ANY_OP_P (dname)) { - error ("declaration of %qD as parameter", dname); - return error_mark_node; + if (typedef_p) + { + error ("declaration of %qD as %", dname); + return error_mark_node; + } + else if (decl_context == PARM || decl_context == CATCHPARM) + { + error ("declaration of %qD as parameter", dname); + return error_mark_node; + } } } @@ -11708,22 +11698,20 @@ grokdeclarator (const cp_declarator *declarator, return error_mark_node; } - /* Only functions may be declared using an operator-function-id. */ - if (unqualified_id - && IDENTIFIER_OPNAME_P (unqualified_id) - && TREE_CODE (type) != FUNCTION_TYPE - && TREE_CODE (type) != METHOD_TYPE) + if (!FUNC_OR_METHOD_TYPE_P (type)) { - error ("declaration of %qD as non-function", unqualified_id); - return error_mark_node; - } + /* Only functions may be declared using an operator-function-id. */ + if (dname && IDENTIFIER_ANY_OP_P (dname)) + { + error ("declaration of %qD as non-function", dname); + return error_mark_node; + } - if (reqs - && TREE_CODE (type) != FUNCTION_TYPE - && TREE_CODE (type) != METHOD_TYPE) - error_at (location_of (reqs), - "requires-clause on declaration of non-function type %qT", - type); + if (reqs) + error_at (location_of (reqs), + "requires-clause on declaration of non-function type %qT", + type); + } /* We don't check parameter types here because we can emit a better error message later. */ @@ -11768,7 +11756,8 @@ grokdeclarator (const cp_declarator *declarator, } if (ctype && TREE_CODE (type) == FUNCTION_TYPE && staticp < 2 - && !NEW_DELETE_OPNAME_P (unqualified_id)) + && !(identifier_p (unqualified_id) + && IDENTIFIER_NEWDEL_OP_P (unqualified_id))) { cp_cv_quals real_quals = memfn_quals; if (cxx_dialect < cxx14 && constexpr_p @@ -11879,15 +11868,13 @@ grokdeclarator (const cp_declarator *declarator, return error_mark_node; } - if (NEW_DELETE_OPNAME_P (unqualified_id)) + if (virtualp + && identifier_p (unqualified_id) + && IDENTIFIER_NEWDEL_OP_P (unqualified_id)) { - if (virtualp) - { - error ("%qD cannot be declared %, since it " - "is always static", - unqualified_id); - virtualp = 0; - } + error ("%qD cannot be declared %, since it " + "is always static", unqualified_id); + virtualp = 0; } } @@ -12149,6 +12136,7 @@ grokdeclarator (const cp_declarator *declarator, original_name = dname; else original_name = unqualified_id; + // FIXME:gcc_assert (original_name == dname); if (storage_class == sc_auto) error ("storage class % invalid for function %qs", name); @@ -12943,27 +12931,24 @@ grok_op_properties (tree decl, bool complain) if (class_type && !CLASS_TYPE_P (class_type)) class_type = NULL_TREE; - if (DECL_CONV_FN_P (decl)) + if (IDENTIFIER_CONV_OP_P (name)) operator_code = TYPE_EXPR; else - do - { -#define DEF_OPERATOR(NAME, CODE, MANGLING, ARITY, ASSN_P) \ - if (cp_operator_id (CODE) == name) \ - { \ - operator_code = (CODE); \ - break; \ - } \ - else if (cp_assignment_operator_id (CODE) == name) \ - { \ - operator_code = (CODE); \ - DECL_ASSIGNMENT_OPERATOR_P (decl) = 1; \ - break; \ - } - + { + /* It'd be nice to hang something else of the identifier to + find CODE more directly. */ + const operator_name_info_t *oni + = (IDENTIFIER_ASSIGN_OP_P (name) + ? assignment_operator_name_info : operator_name_info); + DECL_ASSIGNMENT_OPERATOR_P (decl) = IDENTIFIER_ASSIGN_OP_P (name); + if (false) + ; +#define DEF_OPERATOR(NAME, CODE, MANGLING, ARITY, KIND) \ + else if (oni[int (CODE)].identifier == name) \ + operator_code = (CODE); #include "operators.def" #undef DEF_OPERATOR - + else gcc_unreachable (); } while (0); @@ -13082,7 +13067,7 @@ grok_op_properties (tree decl, bool complain) return true; /* Warn about conversion operators that will never be used. */ - if (IDENTIFIER_TYPENAME_P (name) + if (IDENTIFIER_CONV_OP_P (name) && ! DECL_TEMPLATE_INFO (decl) && warn_conversion /* Warn only declaring the function; there is no need to diff --git a/gcc/cp/dump.c b/gcc/cp/dump.c index 080fa1a..6fafa5b 100644 --- a/gcc/cp/dump.c +++ b/gcc/cp/dump.c @@ -226,12 +226,12 @@ cp_dump_tree (void* dump_info, tree t) switch (code) { case IDENTIFIER_NODE: - if (IDENTIFIER_OPNAME_P (t)) + if (IDENTIFIER_ANY_OP_P (t)) { dump_string_field (di, "note", "operator"); return true; } - else if (IDENTIFIER_TYPENAME_P (t)) + else if (IDENTIFIER_CONV_OP_P (t)) { dump_child ("tynm", TREE_TYPE (t)); return true; diff --git a/gcc/cp/error.c b/gcc/cp/error.c index e53afa7..86fa804 100644 --- a/gcc/cp/error.c +++ b/gcc/cp/error.c @@ -1051,7 +1051,7 @@ dump_decl_name (cxx_pretty_printer *pp, tree t, int flags) { /* These special cases are duplicated here so that other functions can feed identifiers to error and get them demangled properly. */ - if (IDENTIFIER_TYPENAME_P (t)) + if (IDENTIFIER_CONV_OP_P (t)) { pp_cxx_ws_string (pp, "operator"); /* Not exactly IDENTIFIER_TYPE_VALUE. */ diff --git a/gcc/cp/lex.c b/gcc/cp/lex.c index cf7c0d1..2fa2673 100644 --- a/gcc/cp/lex.c +++ b/gcc/cp/lex.c @@ -89,6 +89,37 @@ operator_name_info_t assignment_operator_name_info[(int) MAX_TREE_CODES]; #include "operators.def" #undef DEF_OPERATOR +/* Get the name of the kind of identifier T. */ + +const char * +get_identifier_kind_name (tree id) +{ + /* Keep in sync with cp_id_kind enumeration. */ + static const char *const names[cik_max] = { + "normal", "keyword", "constructor", "destructor", + "assign-op", "op-assign-op", "simple-op", "conv-op", }; + + unsigned kind = 0; + kind |= IDENTIFIER_KIND_BIT_2 (id) << 2; + kind |= IDENTIFIER_KIND_BIT_1 (id) << 1; + kind |= IDENTIFIER_KIND_BIT_0 (id) << 0; + + return names[kind]; +} + +/* Set the identifier kind, which we expect to currently be zero. */ + +void +set_identifier_kind (tree id, cp_identifier_kind kind) +{ + gcc_checking_assert (!IDENTIFIER_KIND_BIT_2 (id) + & !IDENTIFIER_KIND_BIT_1 (id) + & !IDENTIFIER_KIND_BIT_0 (id)); + IDENTIFIER_KIND_BIT_2 (id) |= (kind >> 2) & 1; + IDENTIFIER_KIND_BIT_1 (id) |= (kind >> 1) & 1; + IDENTIFIER_KIND_BIT_0 (id) |= (kind >> 0) & 1; +} + static void init_operators (void) { @@ -96,22 +127,26 @@ init_operators (void) char buffer[256]; struct operator_name_info_t *oni; -#define DEF_OPERATOR(NAME, CODE, MANGLING, ARITY, ASSN_P) \ - sprintf (buffer, ISALPHA (NAME[0]) ? "operator %s" : "operator%s", NAME); \ - identifier = get_identifier (buffer); \ - IDENTIFIER_OPNAME_P (identifier) = 1; \ - \ - oni = (ASSN_P \ - ? &assignment_operator_name_info[(int) CODE] \ - : &operator_name_info[(int) CODE]); \ - oni->identifier = identifier; \ - oni->name = NAME; \ - oni->mangled_name = MANGLING; \ +#define DEF_OPERATOR(NAME, CODE, MANGLING, ARITY, KIND) \ + sprintf (buffer, "operator%s%s", !NAME[0] \ + || NAME[0] == '_' || ISALPHA (NAME[0]) ? " " : "", NAME); \ + identifier = get_identifier (buffer); \ + \ + if (KIND != cik_simple_op || !IDENTIFIER_ANY_OP_P (identifier)) \ + set_identifier_kind (identifier, KIND); \ + \ + oni = (KIND == cik_assign_op \ + ? &assignment_operator_name_info[(int) CODE] \ + : &operator_name_info[(int) CODE]); \ + oni->identifier = identifier; \ + oni->name = NAME; \ + oni->mangled_name = MANGLING; \ oni->arity = ARITY; #include "operators.def" #undef DEF_OPERATOR + operator_name_info[(int) TYPE_EXPR] = operator_name_info[(int) CAST_EXPR]; operator_name_info[(int) ERROR_MARK].identifier = get_identifier (""); @@ -123,6 +158,7 @@ init_operators (void) operator_name_info [(int) INIT_EXPR].name = operator_name_info [(int) MODIFY_EXPR].name; + operator_name_info [(int) EXACT_DIV_EXPR].name = "(ceiling /)"; operator_name_info [(int) CEIL_DIV_EXPR].name = "(ceiling /)"; operator_name_info [(int) FLOOR_DIV_EXPR].name = "(floor /)"; @@ -130,26 +166,20 @@ init_operators (void) operator_name_info [(int) CEIL_MOD_EXPR].name = "(ceiling %)"; operator_name_info [(int) FLOOR_MOD_EXPR].name = "(floor %)"; operator_name_info [(int) ROUND_MOD_EXPR].name = "(round %)"; + operator_name_info [(int) ABS_EXPR].name = "abs"; operator_name_info [(int) TRUTH_AND_EXPR].name = "strict &&"; operator_name_info [(int) TRUTH_OR_EXPR].name = "strict ||"; operator_name_info [(int) RANGE_EXPR].name = "..."; operator_name_info [(int) UNARY_PLUS_EXPR].name = "+"; - assignment_operator_name_info [(int) EXACT_DIV_EXPR].name - = "(exact /=)"; - assignment_operator_name_info [(int) CEIL_DIV_EXPR].name - = "(ceiling /=)"; - assignment_operator_name_info [(int) FLOOR_DIV_EXPR].name - = "(floor /=)"; - assignment_operator_name_info [(int) ROUND_DIV_EXPR].name - = "(round /=)"; - assignment_operator_name_info [(int) CEIL_MOD_EXPR].name - = "(ceiling %=)"; - assignment_operator_name_info [(int) FLOOR_MOD_EXPR].name - = "(floor %=)"; - assignment_operator_name_info [(int) ROUND_MOD_EXPR].name - = "(round %=)"; + assignment_operator_name_info [(int) EXACT_DIV_EXPR].name = "(exact /=)"; + assignment_operator_name_info [(int) CEIL_DIV_EXPR].name = "(ceiling /=)"; + assignment_operator_name_info [(int) FLOOR_DIV_EXPR].name = "(floor /=)"; + assignment_operator_name_info [(int) ROUND_DIV_EXPR].name = "(round /=)"; + assignment_operator_name_info [(int) CEIL_MOD_EXPR].name = "(ceiling %=)"; + assignment_operator_name_info [(int) FLOOR_MOD_EXPR].name = "(floor %=)"; + assignment_operator_name_info [(int) ROUND_MOD_EXPR].name = "(round %=)"; } /* Initialize the reserved words. */ @@ -184,7 +214,7 @@ init_reswords (void) C_SET_RID_CODE (id, c_common_reswords[i].rid); ridpointers [(int) c_common_reswords[i].rid] = id; if (! (c_common_reswords[i].disable & mask)) - C_IS_RESERVED_WORD (id) = 1; + set_identifier_kind (id, cik_keyword); } for (i = 0; i < NUM_INT_N_ENTS; i++) @@ -193,7 +223,7 @@ init_reswords (void) sprintf (name, "__int%d", int_n_data[i].bitsize); id = get_identifier (name); C_SET_RID_CODE (id, RID_FIRST_INT_N + i); - C_IS_RESERVED_WORD (id) = 1; + set_identifier_kind (id, cik_keyword); } } @@ -431,7 +461,7 @@ unqualified_name_lookup_error (tree name, location_t loc) if (loc == UNKNOWN_LOCATION) loc = EXPR_LOC_OR_LOC (name, input_location); - if (IDENTIFIER_OPNAME_P (name)) + if (IDENTIFIER_ANY_OP_P (name)) { if (name != cp_operator_id (ERROR_MARK)) error_at (loc, "%qD not defined", name); diff --git a/gcc/cp/mangle.c b/gcc/cp/mangle.c index c83aef5..e235913 100644 --- a/gcc/cp/mangle.c +++ b/gcc/cp/mangle.c @@ -1261,9 +1261,9 @@ write_template_prefix (const tree node) static void write_unqualified_id (tree identifier) { - if (IDENTIFIER_TYPENAME_P (identifier)) + if (IDENTIFIER_CONV_OP_P (identifier)) write_conversion_operator_name (TREE_TYPE (identifier)); - else if (IDENTIFIER_OPNAME_P (identifier)) + else if (IDENTIFIER_ANY_OP_P (identifier)) { int i; const char *mangled_name = NULL; @@ -2825,14 +2825,16 @@ write_template_args (tree args) static void write_member_name (tree member) { - if (abi_version_at_least (11) && IDENTIFIER_OPNAME_P (member)) + if (identifier_p (member)) { - write_string ("on"); - if (abi_warn_or_compat_version_crosses (11)) - G.need_abi_warning = 1; + if (abi_version_at_least (11) && IDENTIFIER_ANY_OP_P (member)) + { + write_string ("on"); + if (abi_warn_or_compat_version_crosses (11)) + G.need_abi_warning = 1; + } + write_unqualified_id (member); } - if (identifier_p (member)) - write_unqualified_id (member); else if (DECL_P (member)) write_unqualified_name (member); else if (TREE_CODE (member) == TEMPLATE_ID_EXPR) @@ -3050,7 +3052,7 @@ write_expression (tree expr) /* An operator name appearing as a dependent name needs to be specially marked to disambiguate between a use of the operator name and a use of the operator in an expression. */ - if (IDENTIFIER_OPNAME_P (expr)) + if (IDENTIFIER_ANY_OP_P (expr)) write_string ("on"); write_unqualified_id (expr); } @@ -3058,7 +3060,7 @@ write_expression (tree expr) { tree fn = TREE_OPERAND (expr, 0); fn = OVL_NAME (fn); - if (IDENTIFIER_OPNAME_P (fn)) + if (IDENTIFIER_ANY_OP_P (fn)) write_string ("on"); write_unqualified_id (fn); write_template_args (TREE_OPERAND (expr, 1)); @@ -4241,9 +4243,8 @@ mangle_conv_op_name_for_type (const tree type) when performing conversions. */ TREE_TYPE (identifier) = type; - /* Set bits on the identifier so we know later it's a conversion. */ - IDENTIFIER_OPNAME_P (identifier) = 1; - IDENTIFIER_TYPENAME_P (identifier) = 1; + /* Set the identifier kind so we know later it's a conversion. */ + set_identifier_kind (identifier, cik_conv_op); } return identifier; diff --git a/gcc/cp/name-lookup.c b/gcc/cp/name-lookup.c index 54c9d7b..0df546a 100644 --- a/gcc/cp/name-lookup.c +++ b/gcc/cp/name-lookup.c @@ -4161,7 +4161,7 @@ do_class_using_decl (tree scope, tree name) scope_dependent_p = dependent_scope_p (scope); name_dependent_p = (scope_dependent_p - || (IDENTIFIER_TYPENAME_P (name) + || (IDENTIFIER_CONV_OP_P (name) && dependent_type_p (TREE_TYPE (name)))); bases_dependent_p = any_dependent_bases_p (); @@ -5066,7 +5066,7 @@ lookup_name_fuzzy (tree name, enum lookup_name_fuzzy_kind kind) /* Only consider reserved words that survived the filtering in init_reswords (e.g. for -std). */ - if (!C_IS_RESERVED_WORD (resword_identifier)) + if (!IDENTIFIER_KEYWORD_P (resword_identifier)) continue; bm.consider (IDENTIFIER_POINTER (resword_identifier)); @@ -5228,7 +5228,7 @@ lookup_name_real_1 (tree name, int prefer_type, int nonclass, bool block_p, /* Conversion operators are handled specially because ordinary unqualified name lookup will not find template conversion operators. */ - if (IDENTIFIER_TYPENAME_P (name)) + if (IDENTIFIER_CONV_OP_P (name)) { cp_binding_level *level; diff --git a/gcc/cp/operators.def b/gcc/cp/operators.def index d26f2a1..7dfdd22 100644 --- a/gcc/cp/operators.def +++ b/gcc/cp/operators.def @@ -67,20 +67,20 @@ along with GCC; see the file COPYING3. If not see an ASSIGNMENT_P argument; it is always zero. */ #define DEF_SIMPLE_OPERATOR(NAME, CODE, MANGLING, ARITY) \ - DEF_OPERATOR(NAME, CODE, MANGLING, ARITY, 0) + DEF_OPERATOR(NAME, CODE, MANGLING, ARITY, cik_simple_op) /* Use DEF_ASSN_OPERATOR to define an assignment operator. Its arguments are as for DEF_OPERATOR, but there is no need to provide an ASSIGNMENT_P argument; it is always one. */ #define DEF_ASSN_OPERATOR(NAME, CODE, MANGLING, ARITY) \ - DEF_OPERATOR(NAME, CODE, MANGLING, ARITY, 1) + DEF_OPERATOR(NAME, CODE, MANGLING, ARITY, cik_assign_op) /* Memory allocation operators. */ -DEF_SIMPLE_OPERATOR ("new", NEW_EXPR, "nw", -1) -DEF_SIMPLE_OPERATOR ("new []", VEC_NEW_EXPR, "na", -1) -DEF_SIMPLE_OPERATOR ("delete", DELETE_EXPR, "dl", -1) -DEF_SIMPLE_OPERATOR ("delete []", VEC_DELETE_EXPR, "da", -1) +DEF_OPERATOR ("new", NEW_EXPR, "nw", -1, cik_newdel_op) +DEF_OPERATOR ("new []", VEC_NEW_EXPR, "na", -1, cik_newdel_op) +DEF_OPERATOR ("delete", DELETE_EXPR, "dl", -1, cik_newdel_op) +DEF_OPERATOR ("delete []", VEC_DELETE_EXPR, "da", -1, cik_newdel_op) /* Unary operators. */ DEF_SIMPLE_OPERATOR ("+", UNARY_PLUS_EXPR, "ps", 1) @@ -97,8 +97,7 @@ DEF_SIMPLE_OPERATOR ("alignof", ALIGNOF_EXPR, "az", 1) DEF_SIMPLE_OPERATOR ("__imag__", IMAGPART_EXPR, "v18__imag__", 1) DEF_SIMPLE_OPERATOR ("__real__", REALPART_EXPR, "v18__real__", 1) -/* The cast operator. */ -DEF_SIMPLE_OPERATOR ("", TYPE_EXPR, "cv", 1) +/* The cast operators. */ DEF_SIMPLE_OPERATOR ("", CAST_EXPR, "cv", 1) DEF_SIMPLE_OPERATOR ("dynamic_cast", DYNAMIC_CAST_EXPR, "dc", 1) DEF_SIMPLE_OPERATOR ("reinterpret_cast", REINTERPRET_CAST_EXPR, "rc", 1) diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index 37f9154..ddb1cf3 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -806,7 +806,7 @@ cp_lexer_get_preprocessor_token (cp_lexer *lexer, cp_token *token) /* Check to see if this token is a keyword. */ if (token->type == CPP_NAME) { - if (C_IS_RESERVED_WORD (token->u.value)) + if (IDENTIFIER_KEYWORD_P (token->u.value)) { /* Mark this token as a keyword. */ token->type = CPP_KEYWORD; @@ -20089,7 +20089,8 @@ cp_parser_direct_declarator (cp_parser* parser, { if (TREE_CODE (unqualified_name) == BIT_NOT_EXPR) sfk = sfk_destructor; - else if (IDENTIFIER_TYPENAME_P (unqualified_name)) + else if (identifier_p (unqualified_name) + && IDENTIFIER_CONV_OP_P (unqualified_name)) sfk = sfk_conversion; else if (/* There's no way to declare a constructor for an unnamed type, even if the type diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 69ca929..fba7fb1 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -5333,11 +5333,11 @@ push_template_decl_real (tree decl, bool is_friend) error ("destructor %qD declared as member template", decl); return error_mark_node; } - if (NEW_DELETE_OPNAME_P (DECL_NAME (decl)) + if (IDENTIFIER_NEWDEL_OP_P (DECL_NAME (decl)) && (!prototype_p (TREE_TYPE (decl)) || TYPE_ARG_TYPES (TREE_TYPE (decl)) == void_list_node || !TREE_CHAIN (TYPE_ARG_TYPES (TREE_TYPE (decl))) - || (TREE_CHAIN (TYPE_ARG_TYPES ((TREE_TYPE (decl)))) + || (TREE_CHAIN (TYPE_ARG_TYPES (TREE_TYPE (decl))) == void_list_node))) { /* [basic.stc.dynamic.allocation] @@ -12416,7 +12416,7 @@ tsubst_decl (tree t, tree args, tsubst_flags_t complain) /* If we aren't complaining now, return on error before we register the specialization so that we'll complain eventually. */ if ((complain & tf_error) == 0 - && IDENTIFIER_OPNAME_P (DECL_NAME (r)) + && IDENTIFIER_ANY_OP_P (DECL_NAME (r)) && !grok_op_properties (r, /*complain=*/false)) RETURN (error_mark_node); @@ -12487,7 +12487,7 @@ tsubst_decl (tree t, tree args, tsubst_flags_t complain) clone_function_decl (r, /*update_methods=*/false); } else if ((complain & tf_error) != 0 - && IDENTIFIER_OPNAME_P (DECL_NAME (r)) + && IDENTIFIER_ANY_OP_P (DECL_NAME (r)) && !grok_op_properties (r, /*complain=*/true)) RETURN (error_mark_node); @@ -14247,7 +14247,7 @@ tsubst_baselink (tree baselink, tree object_type, } tree name = OVL_NAME (fns); - if (IDENTIFIER_TYPENAME_P (name)) + if (IDENTIFIER_CONV_OP_P (name)) name = mangle_conv_op_name_for_type (optype); baselink = lookup_fnfields (qualifying_scope, name, /*protect=*/1); @@ -15035,7 +15035,7 @@ tsubst_copy (tree t, tree args, tsubst_flags_t complain, tree in_decl) t = DECL_NAME (t); /* Fall through. */ case IDENTIFIER_NODE: - if (IDENTIFIER_TYPENAME_P (t)) + if (IDENTIFIER_CONV_OP_P (t)) { tree new_type = tsubst (TREE_TYPE (t), args, complain, in_decl); return mangle_conv_op_name_for_type (new_type); @@ -16668,7 +16668,7 @@ tsubst_copy_and_build (tree t, bool non_integral_constant_expression_p; const char *error_msg; - if (IDENTIFIER_TYPENAME_P (t)) + if (IDENTIFIER_CONV_OP_P (t)) { tree new_type = tsubst (TREE_TYPE (t), args, complain, in_decl); t = mangle_conv_op_name_for_type (new_type); diff --git a/gcc/cp/ptree.c b/gcc/cp/ptree.c index 5775e07..7b69dbe 100644 --- a/gcc/cp/ptree.c +++ b/gcc/cp/ptree.c @@ -178,7 +178,8 @@ cxx_print_identifier (FILE *file, tree node, int indent) fprintf (file, " "); else indent_to (file, indent + 4); - fprintf (file, "local bindings <%p>", (void *) IDENTIFIER_BINDING (node)); + fprintf (file, "%s local bindings <%p>", get_identifier_kind_name (node), + (void *) IDENTIFIER_BINDING (node)); print_node (file, "label", IDENTIFIER_LABEL_VALUE (node), indent + 4); print_node (file, "template", IDENTIFIER_TEMPLATE (node), indent + 4); } diff --git a/gcc/cp/search.c b/gcc/cp/search.c index d8ad40a..00f895c 100644 --- a/gcc/cp/search.c +++ b/gcc/cp/search.c @@ -1187,7 +1187,7 @@ lookup_field_r (tree binfo, void *data) done: /* Don't look for constructors or destructors in base classes. */ - if (IDENTIFIER_CTOR_OR_DTOR_P (lfi->name)) + if (IDENTIFIER_CDTOR_P (lfi->name)) return dfs_skip_bases; return NULL_TREE; } @@ -1352,7 +1352,7 @@ lookup_member (tree xbasetype, tree name, int protect, bool want_type, if (rval && is_overloaded_fn (rval)) rval = build_baselink (rval_binfo, basetype_path, rval, - (IDENTIFIER_TYPENAME_P (name) + (IDENTIFIER_CONV_OP_P (name) ? TREE_TYPE (name): NULL_TREE)); return rval; } @@ -1595,7 +1595,7 @@ lookup_fnfields_idx_nolazy (tree type, tree name) fn = CLASSTYPE_DESTRUCTORS (type); return fn ? CLASSTYPE_DESTRUCTOR_SLOT : -1; } - if (IDENTIFIER_TYPENAME_P (name)) + if (IDENTIFIER_CONV_OP_P (name)) return lookup_conversion_operator (type, TREE_TYPE (name)); /* Skip the conversion operators. */ diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c index 7ecc632..9589b47 100644 --- a/gcc/cp/semantics.c +++ b/gcc/cp/semantics.c @@ -3496,7 +3496,7 @@ finish_id_expression (tree id_expression, && (!TYPE_P (scope) || (!dependent_type_p (scope) && !(identifier_p (id_expression) - && IDENTIFIER_TYPENAME_P (id_expression) + && IDENTIFIER_CONV_OP_P (id_expression) && dependent_type_p (TREE_TYPE (id_expression)))))) { /* If the qualifying type is non-dependent (and the name diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c index 0f22e64..1c15f29 100644 --- a/gcc/cp/typeck.c +++ b/gcc/cp/typeck.c @@ -5652,7 +5652,7 @@ cp_build_addr_expr_1 (tree arg, bool strict_lvalue, tsubst_flags_t complain) arg = mark_lvalue_use (arg); argtype = lvalue_type (arg); - gcc_assert (!identifier_p (arg) || !IDENTIFIER_OPNAME_P (arg)); + gcc_assert (!(identifier_p (arg) && IDENTIFIER_ANY_OP_P (arg))); if (TREE_CODE (arg) == COMPONENT_REF && type_unknown_p (arg) && !really_overloaded_fn (arg)) -- cgit v1.1 From 4333d74bab07cb91b535d2072cc0fad48cf24f49 Mon Sep 17 00:00:00 2001 From: Carl Love Date: Thu, 22 Jun 2017 18:45:35 +0000 Subject: builtins-3.c (vmulosh, [...]): Fix scan-assembler-times should check for word not half word instructions. gcc/testsuite/ChangeLog: 2017-06-22 Carl Love * gcc.target/powerpc/builtins-3.c (vmulosh, vmulouh, vmulesh, vmuleuh): Fix scan-assembler-times should check for word not half word instructions. From-SVN: r249572 --- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/powerpc/builtins-3.c | 16 ++++++++-------- 2 files changed, 14 insertions(+), 8 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e162386..cc8cef2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-06-22 Carl Love + + * gcc.target/powerpc/builtins-3.c (vmulosh, vmulouh, vmulesh, + vmuleuh): Fix scan-assembler-times should check for word not half word + instructions. + 2017-06-22 Jeff Law * gcc.c-torture/compile/stack-check-1.c: New test. diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c index b252488..00fa6ec 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c @@ -207,10 +207,10 @@ test_vul_sldw_vul_vul (vector unsigned long long x, test_vsll_slo_vsll_vuc 1 vslo test_vull_slo_vsll_vsc 1 vslo test_vull_slo_vsll_vuc 1 vslo - test_vsll_mulo_vsi_vsi 1 vmulosh - test_vull_mulo_vui_vui 1 vmulouh - test_vsll_mule_vsi_vsi 1 vmulesh - test_vull_mule_vui_vui 1 vmuleuh + test_vsll_mulo_vsi_vsi 1 vmulosw + test_vull_mulo_vui_vui 1 vmulouw + test_vsll_mule_vsi_vsi 1 vmulesw + test_vull_mule_vui_vui 1 vmuleuw test_vsc_mulo_vsc_vsc 1 xxsldwi test_vuc_mulo_vuc_vuc 1 xxsldwi test_vssi_mulo_vssi_vssi 1 xxsldwi @@ -236,8 +236,8 @@ test_vul_sldw_vul_vul (vector unsigned long long x, /* { dg-final { scan-assembler-times "xvnegsp" 1 } } */ /* { dg-final { scan-assembler-times "xvnegdp" 1 } } */ /* { dg-final { scan-assembler-times "vslo" 4 } } */ -/* { dg-final { scan-assembler-times "vmulosh" 1 } } */ -/* { dg-final { scan-assembler-times "vmulouh" 1 } } */ -/* { dg-final { scan-assembler-times "vmulesh" 1 } } */ -/* { dg-final { scan-assembler-times "vmuleuh" 1 } } */ +/* { dg-final { scan-assembler-times "vmulosw" 1 } } */ +/* { dg-final { scan-assembler-times "vmulouw" 1 } } */ +/* { dg-final { scan-assembler-times "vmulesw" 1 } } */ +/* { dg-final { scan-assembler-times "vmuleuw" 1 } } */ /* { dg-final { scan-assembler-times "xxsldwi" 8 } } */ -- cgit v1.1 From 60edf8bbba843187e6b4700f41707bb9dd9cec14 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Thu, 22 Jun 2017 19:46:10 +0000 Subject: driver-i386.c (host_detect_local_cpu): Add Kaby Lake models to skylake case. gcc/ 2017-06-22 Matt Turner * config/i386/driver-i386.c (host_detect_local_cpu): Add Kaby Lake models to skylake case. Assume skylake for unknown models with clflushopt. gcc/testsuite/ 2017-06-22 Matt Turner * gcc.target/i386/builtin_target.c: Add Kaby Lake models to skylake check. libgcc/ 2017-06-22 Matt Turner * config/i386/cpuinfo.c (get_intel_cpu): Add Kaby Lake models to skylake case. From-SVN: r249574 --- gcc/ChangeLog | 6 ++++++ gcc/config/i386/driver-i386.c | 6 ++++++ gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/i386/builtin_target.c | 3 +++ 4 files changed, 20 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 03a824f..087126d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-22 Matt Turner + + * config/i386/driver-i386.c (host_detect_local_cpu): Add Kaby + Lake models to skylake case. Assume skylake for unknown + models with clflushopt. + 2017-06-22 Jeff Law * config/aarch64/aarch64.c (aarch64_emit_probe_stack_range): Handle diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 6c81251..570c490 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -781,6 +781,9 @@ const char *host_detect_local_cpu (int argc, const char **argv) case 0x4e: case 0x5e: /* Skylake. */ + case 0x8e: + case 0x9e: + /* Kaby Lake. */ cpu = "skylake"; break; case 0x57: @@ -794,6 +797,9 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* Assume Knights Landing. */ if (has_avx512f) cpu = "knl"; + /* Assume Skylake. */ + else if (has_clflushopt) + cpu = "skylake"; /* Assume Broadwell. */ else if (has_adx) cpu = "broadwell"; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index cc8cef2..b41c8d9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-22 Matt Turner + + * gcc.target/i386/builtin_target.c: Add Kaby Lake models to + skylake check. + 2017-06-22 Carl Love * gcc.target/powerpc/builtins-3.c (vmulosh, vmulouh, vmulesh, diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc/testsuite/gcc.target/i386/builtin_target.c index 374f029..9c190eb 100644 --- a/gcc/testsuite/gcc.target/i386/builtin_target.c +++ b/gcc/testsuite/gcc.target/i386/builtin_target.c @@ -88,6 +88,9 @@ check_intel_cpu_model (unsigned int family, unsigned int model, case 0x4e: case 0x5e: /* Skylake. */ + case 0x8e: + case 0x9e: + /* Kaby Lake. */ assert (__builtin_cpu_is ("corei7")); assert (__builtin_cpu_is ("skylake")); break; -- cgit v1.1 From 61fbdfbe1b1efc68dd02f03b0d915dc2ded0e076 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 19:52:11 +0000 Subject: runtime: fix type cast in assignment to gcnextsp in C code Patch from Rainer Orth. Reviewed-on: https://go-review.googlesource.com/46459 From-SVN: r249575 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index ccc7919..e3fcdb8 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -681c8a7b0a9d52c0b81e7a4b1c55fe65ed889573 +27204e41643f4549c5ed97d48e17912f64c0aa71 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From f384e12acc5b5b06d5fcc9a40ea6cffb8c0aa4c8 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 22:08:50 +0000 Subject: runtime: export getm function Use go:linkname to export the getm function. This makes it visible to runtime/testdata/testprogcgo/dropm_stub.go, which uses it as part of the TestEnsureDropM test in runtime/crash_cgo_test.go. That test is not run today, but it will be soon. Reviewed-on: https://go-review.googlesource.com/46462 From-SVN: r249576 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index e3fcdb8..fb6b7be 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -27204e41643f4549c5ed97d48e17912f64c0aa71 +55b2b2dee55bd495a770347daaf858634057ecb0 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From b34391e08e273b5dbdce966518c6d7be0596bd16 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 22:11:01 +0000 Subject: runtime: mark dropm and callees nowritebarrierrec The CgocallbackDone function calls dropm after it calls entersyscall, which means that dropm must not have any write barriers. Mark it accordingly. Reviewed-on: https://go-review.googlesource.com/46464 From-SVN: r249577 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index fb6b7be..3f42df6 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -55b2b2dee55bd495a770347daaf858634057ecb0 +c5aa42107d116c9121de447d214297c88dd9f5fa The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From c8a0d1c344a6da9bbe6c0bad34dd3d12fe11d0df Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Thu, 22 Jun 2017 22:12:50 +0000 Subject: runtime: uncomment check for gchelper on g0 stack Now that systemstack changes to the g0 stack, this check passes. Reviewed-on: https://go-review.googlesource.com/46460 From-SVN: r249578 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 3f42df6..b6037a6 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -c5aa42107d116c9121de447d214297c88dd9f5fa +385efb8947af70b8425c833a1ab68ba5f357dfae The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 3e20731323ec2491cab16ca5f69dd29f133125ef Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Fri, 23 Jun 2017 00:16:22 +0000 Subject: Daily bump. From-SVN: r249583 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index b5de4d3..fc6b5b6 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170622 +20170623 -- cgit v1.1 From 70fdc808941016567f8e55caea593324b15df230 Mon Sep 17 00:00:00 2001 From: Jonathan Wakely Date: Fri, 23 Jun 2017 09:16:05 +0100 Subject: PR c++/81187 fix -Wnoexcept-type entry in manual PR c++/81187 * doc/invoke.texi (-Wnoexcept-type): Fix name of option, from -Wnoexcept. From-SVN: r249584 --- gcc/ChangeLog | 6 ++++++ gcc/doc/invoke.texi | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 087126d..e3245df 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-23 Jonathan Wakely + + PR c++/81187 + * doc/invoke.texi (-Wnoexcept-type): Fix name of option, from + -Wnoexcept. + 2017-06-22 Matt Turner * config/i386/driver-i386.c (host_detect_local_cpu): Add Kaby diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 7e7a16a5..7c81f0d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -2908,7 +2908,7 @@ to a function that does not have a non-throwing exception specification (i.e. @code{throw()} or @code{noexcept}) but is known by the compiler to never throw an exception. -@item -Wnoexcept @r{(C++ and Objective-C++ only)} +@item -Wnoexcept-type @r{(C++ and Objective-C++ only)} @opindex Wnoexcept-type @opindex Wno-noexcept-type Warn if the C++1z feature making @code{noexcept} part of a function -- cgit v1.1 From 2db9b7cd422b63fe0a87218128cc0939b439859e Mon Sep 17 00:00:00 2001 From: Marc Glisse Date: Fri, 23 Jun 2017 11:05:47 +0200 Subject: Refactor fileptr_type_node handling 2017-06-23 Marc Glisse gcc/ * tree.h (builtin_structptr_type): New type. (builtin_structptr_types): Declare new array. * tree.c (builtin_structptr_types): New array. (free_lang_data, build_common_tree_nodes): Use it. gcc/c-family/ * c-common.c (c_common_nodes_and_builtins): Use builtin_structptr_types. gcc/cp/ * decl.c (duplicate_decls): Use builtin_structptr_types. gcc/lto/ * lto-lang.c (lto_init): Use builtin_structptr_types. From-SVN: r249585 --- gcc/ChangeLog | 7 +++++ gcc/c-family/ChangeLog | 4 +++ gcc/c-family/c-common.c | 12 +++++--- gcc/cp/ChangeLog | 4 +++ gcc/cp/decl.c | 76 +++++++++++++++++++++---------------------------- gcc/lto/ChangeLog | 4 +++ gcc/lto/lto-lang.c | 18 +++++++----- gcc/tree.c | 22 +++++++++++--- gcc/tree.h | 9 ++++++ 9 files changed, 97 insertions(+), 59 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e3245df..4f750a6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-06-23 Marc Glisse + + * tree.h (builtin_structptr_type): New type. + (builtin_structptr_types): Declare new array. + * tree.c (builtin_structptr_types): New array. + (free_lang_data, build_common_tree_nodes): Use it. + 2017-06-23 Jonathan Wakely PR c++/81187 diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index e8d1d57..a61bb56 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,7 @@ +2017-06-23 Marc Glisse + + * c-common.c (c_common_nodes_and_builtins): Use builtin_structptr_types. + 2017-06-15 Martin Sebor PR c++/80560 diff --git a/gcc/c-family/c-common.c b/gcc/c-family/c-common.c index 4395e51..f6a9d05 100644 --- a/gcc/c-family/c-common.c +++ b/gcc/c-family/c-common.c @@ -4181,10 +4181,14 @@ c_common_nodes_and_builtins (void) if (c_dialect_cxx ()) { /* For C++, make fileptr_type_node a distinct void * type until - FILE type is defined. */ - fileptr_type_node = build_variant_type_copy (ptr_type_node); - /* Likewise for const struct tm*. */ - const_tm_ptr_type_node = build_variant_type_copy (const_ptr_type_node); + FILE type is defined. Likewise for const struct tm*. */ + for (unsigned i = 0; + i < sizeof (builtin_structptr_types) + / sizeof (builtin_structptr_type); + ++i) + builtin_structptr_types[i].node = + build_variant_type_copy (builtin_structptr_types[i].base); + } record_builtin_type (RID_VOID, NULL, void_type_node); diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 6acbe8b..92f478a 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,7 @@ +2017-06-23 Marc Glisse + + * decl.c (duplicate_decls): Use builtin_structptr_types. + 2017-06-22 Nathan Sidwell Reorder IDENTIFIER flags diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index b0a34de..0361357 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -1470,53 +1470,41 @@ duplicate_decls (tree newdecl, tree olddecl, bool newdecl_is_friend) t2 = TYPE_ARG_TYPES (TREE_TYPE (olddecl)); t1 || t2; t1 = TREE_CHAIN (t1), t2 = TREE_CHAIN (t2)) - if (!t1 || !t2) - break; - /* Deal with fileptr_type_node. FILE type is not known - at the time we create the builtins. */ - else if (TREE_VALUE (t2) == fileptr_type_node) - { - tree t = TREE_VALUE (t1); - - if (TYPE_PTR_P (t) - && TYPE_IDENTIFIER (TREE_TYPE (t)) - == get_identifier ("FILE") - && compparms (TREE_CHAIN (t1), TREE_CHAIN (t2))) + { + if (!t1 || !t2) + break; + /* FILE, tm types are not known at the time + we create the builtins. */ + for (unsigned i = 0; + i < sizeof (builtin_structptr_types) + / sizeof (builtin_structptr_type); + ++i) + if (TREE_VALUE (t2) == builtin_structptr_types[i].node) { - tree oldargs = TYPE_ARG_TYPES (TREE_TYPE (olddecl)); - - TYPE_ARG_TYPES (TREE_TYPE (olddecl)) - = TYPE_ARG_TYPES (TREE_TYPE (newdecl)); - types_match = decls_match (newdecl, olddecl); - if (types_match) - return duplicate_decls (newdecl, olddecl, - newdecl_is_friend); - TYPE_ARG_TYPES (TREE_TYPE (olddecl)) = oldargs; - } - } - /* Likewise for const struct tm*. */ - else if (TREE_VALUE (t2) == const_tm_ptr_type_node) - { - tree t = TREE_VALUE (t1); + tree t = TREE_VALUE (t1); - if (TYPE_PTR_P (t) - && TYPE_IDENTIFIER (TREE_TYPE (t)) - == get_identifier ("tm") - && compparms (TREE_CHAIN (t1), TREE_CHAIN (t2))) - { - tree oldargs = TYPE_ARG_TYPES (TREE_TYPE (olddecl)); - - TYPE_ARG_TYPES (TREE_TYPE (olddecl)) - = TYPE_ARG_TYPES (TREE_TYPE (newdecl)); - types_match = decls_match (newdecl, olddecl); - if (types_match) - return duplicate_decls (newdecl, olddecl, - newdecl_is_friend); - TYPE_ARG_TYPES (TREE_TYPE (olddecl)) = oldargs; + if (TYPE_PTR_P (t) + && TYPE_IDENTIFIER (TREE_TYPE (t)) + == get_identifier (builtin_structptr_types[i].str) + && compparms (TREE_CHAIN (t1), TREE_CHAIN (t2))) + { + tree oldargs = TYPE_ARG_TYPES (TREE_TYPE (olddecl)); + + TYPE_ARG_TYPES (TREE_TYPE (olddecl)) + = TYPE_ARG_TYPES (TREE_TYPE (newdecl)); + types_match = decls_match (newdecl, olddecl); + if (types_match) + return duplicate_decls (newdecl, olddecl, + newdecl_is_friend); + TYPE_ARG_TYPES (TREE_TYPE (olddecl)) = oldargs; + } + goto next_arg; } - } - else if (! same_type_p (TREE_VALUE (t1), TREE_VALUE (t2))) - break; + + if (! same_type_p (TREE_VALUE (t1), TREE_VALUE (t2))) + break; +next_arg:; + } warning_at (DECL_SOURCE_LOCATION (newdecl), OPT_Wbuiltin_declaration_mismatch, diff --git a/gcc/lto/ChangeLog b/gcc/lto/ChangeLog index 58601c5..41f0343 100644 --- a/gcc/lto/ChangeLog +++ b/gcc/lto/ChangeLog @@ -1,3 +1,7 @@ +2017-06-23 Marc Glisse + + * lto-lang.c (lto_init): Use builtin_structptr_types. + 2017-06-15 Jan Hubicka Thomas Preud'homme diff --git a/gcc/lto/lto-lang.c b/gcc/lto/lto-lang.c index 52ab2a8..5893517 100644 --- a/gcc/lto/lto-lang.c +++ b/gcc/lto/lto-lang.c @@ -1220,13 +1220,17 @@ lto_init (void) /* In the C++ front-end, fileptr_type_node is defined as a variant copy of ptr_type_node, rather than ptr_node itself. The distinction should only be relevant to the front-end, so we - always use the C definition here in lto1. */ - gcc_assert (fileptr_type_node == ptr_type_node); - gcc_assert (TYPE_MAIN_VARIANT (fileptr_type_node) == ptr_type_node); - /* Likewise for const struct tm*. */ - gcc_assert (const_tm_ptr_type_node == const_ptr_type_node); - gcc_assert (TYPE_MAIN_VARIANT (const_tm_ptr_type_node) - == const_ptr_type_node); + always use the C definition here in lto1. + Likewise for const struct tm*. */ + for (unsigned i = 0; + i < sizeof (builtin_structptr_types) / sizeof (builtin_structptr_type); + ++i) + { + gcc_assert (builtin_structptr_types[i].node + == builtin_structptr_types[i].base); + gcc_assert (TYPE_MAIN_VARIANT (builtin_structptr_types[i].node) + == builtin_structptr_types[i].base); + } lto_build_c_type_nodes (); gcc_assert (va_list_type_node); diff --git a/gcc/tree.c b/gcc/tree.c index 2602803..13c6c90 100644 --- a/gcc/tree.c +++ b/gcc/tree.c @@ -5983,8 +5983,10 @@ free_lang_data (void) free_lang_data_in_cgraph (); /* Create gimple variants for common types. */ - fileptr_type_node = ptr_type_node; - const_tm_ptr_type_node = const_ptr_type_node; + for (unsigned i = 0; + i < sizeof (builtin_structptr_types) / sizeof (builtin_structptr_type); + ++i) + builtin_structptr_types[i].node = builtin_structptr_types[i].base; /* Reset some langhooks. Do not reset types_compatible_p, it may still be used indirectly via the get_alias_set langhook. */ @@ -10449,8 +10451,10 @@ build_common_tree_nodes (bool signed_char) ptr_type_node = build_pointer_type (void_type_node); const_ptr_type_node = build_pointer_type (build_type_variant (void_type_node, 1, 0)); - fileptr_type_node = ptr_type_node; - const_tm_ptr_type_node = const_ptr_type_node; + for (unsigned i = 0; + i < sizeof (builtin_structptr_types) / sizeof (builtin_structptr_type); + ++i) + builtin_structptr_types[i].node = builtin_structptr_types[i].base; pointer_sized_int_node = build_nonstandard_integer_type (POINTER_SIZE, 1); @@ -14544,6 +14548,16 @@ get_nonnull_args (const_tree fntype) return argmap; } +/* List of pointer types used to declare builtins before we have seen their + real declaration. + + Keep the size up to date in tree.h ! */ +const builtin_structptr_type builtin_structptr_types[2] = +{ + { fileptr_type_node, ptr_type_node, "FILE" }, + { const_tm_ptr_type_node, const_ptr_type_node, "tm" } +}; + #if CHECKING_P namespace selftest { diff --git a/gcc/tree.h b/gcc/tree.h index bfe83f7..7a4f5d6 100644 --- a/gcc/tree.h +++ b/gcc/tree.h @@ -5523,4 +5523,13 @@ desired_pro_or_demotion_p (const_tree to_type, const_tree from_type) return to_type_precision <= TYPE_PRECISION (from_type); } +/* Pointer type used to declare builtins before we have seen its real + declaration. */ +struct builtin_structptr_type +{ + tree& node; + tree& base; + const char *str; +}; +extern const builtin_structptr_type builtin_structptr_types[2]; #endif /* GCC_TREE_H */ -- cgit v1.1 From 08f424143c105ec8e610e01a4ee09d96d1eaa823 Mon Sep 17 00:00:00 2001 From: Bernd Edlinger Date: Fri, 23 Jun 2017 12:44:07 +0000 Subject: ira.c (update_equiv_regs): Revert to using may_trap_or_fault_p again. 2017-06-23 Bernd Edlinger rtl-optimizatoin/79286 * ira.c (update_equiv_regs): Revert to using may_trap_or_fault_p again. * rtlanal.c (rtx_addr_can_trap_p_1): SYMBOL_REF_FUNCTION_P can never trap. PIC register plus a const unspec without offset can never trap. From-SVN: r249588 --- gcc/ChangeLog | 7 +++++++ gcc/ira.c | 3 ++- gcc/rtlanal.c | 9 ++++++--- 3 files changed, 15 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4f750a6..b3a9add 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-06-23 Bernd Edlinger + + rtl-optimizatoin/79286 + * ira.c (update_equiv_regs): Revert to using may_trap_or_fault_p again. + * rtlanal.c (rtx_addr_can_trap_p_1): SYMBOL_REF_FUNCTION_P can never + trap. PIC register plus a const unspec without offset can never trap. + 2017-06-23 Marc Glisse * tree.h (builtin_structptr_type): New type. diff --git a/gcc/ira.c b/gcc/ira.c index 36a779b..08a1cc5 100644 --- a/gcc/ira.c +++ b/gcc/ira.c @@ -3551,7 +3551,8 @@ update_equiv_regs (void) if (DF_REG_DEF_COUNT (regno) == 1 && note && !rtx_varies_p (XEXP (note, 0), 0) - && def_dominates_uses (regno)) + && (!may_trap_or_fault_p (XEXP (note, 0)) + || def_dominates_uses (regno))) { rtx note_value = XEXP (note, 0); remove_note (insn, note); diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index d9f57c3..bf4183e 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -485,7 +485,7 @@ rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size, case SYMBOL_REF: if (SYMBOL_REF_WEAK (x)) return 1; - if (!CONSTANT_POOL_ADDRESS_P (x)) + if (!CONSTANT_POOL_ADDRESS_P (x) && !SYMBOL_REF_FUNCTION_P (x)) { tree decl; HOST_WIDE_INT decl_size; @@ -644,8 +644,11 @@ rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size, case PLUS: /* An address is assumed not to trap if: - - it is the pic register plus a constant. */ - if (XEXP (x, 0) == pic_offset_table_rtx && CONSTANT_P (XEXP (x, 1))) + - it is the pic register plus a const unspec without offset. */ + if (XEXP (x, 0) == pic_offset_table_rtx + && GET_CODE (XEXP (x, 1)) == CONST + && GET_CODE (XEXP (XEXP (x, 1), 0)) == UNSPEC + && offset == 0) return 0; /* - or it is an address that can't trap plus a constant integer. */ -- cgit v1.1 From fb68f296283941d15505fcf610099281562fa9e0 Mon Sep 17 00:00:00 2001 From: James Cowgill Date: Fri, 23 Jun 2017 13:19:30 +0000 Subject: go-test.exp (go-set-goarch): Update MIPS architecture names. * go.test/go-test.exp (go-set-goarch): Update MIPS architecture names. From-SVN: r249589 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/go.test/go-test.exp | 16 +++++++--------- 2 files changed, 12 insertions(+), 9 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b41c8d9..24532f7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-23 James Cowgill + + * go.test/go-test.exp (go-set-goarch): Update MIPS architecture + names. + 2017-06-22 Matt Turner * gcc.target/i386/builtin_target.c: Add Kaby Lake models to diff --git a/gcc/testsuite/go.test/go-test.exp b/gcc/testsuite/go.test/go-test.exp index 5f6ef29..4b10e4e 100644 --- a/gcc/testsuite/go.test/go-test.exp +++ b/gcc/testsuite/go.test/go-test.exp @@ -213,29 +213,27 @@ proc go-set-goarch { } { #error FOO #endif }] { - set goarch "mipso32" + set goarch "mips" } elseif [check_no_compiler_messages mipsn32 assembly { #if _MIPS_SIM != _ABIN32 #error FOO #endif }] { - set goarch "mipsn32" + set goarch "mips64p32" } elseif [check_no_compiler_messages mipsn64 assembly { #if _MIPS_SIM != _ABI64 #error FOO #endif }] { - set goarch "mipsn64" - } elseif [check_no_compiler_messages mipso64 assembly { - #if _MIPS_SIM != _ABIO64 - #error FOO - #endif - }] { - set goarch "mipso64" + set goarch "mips64" } else { perror "$target_triplet: unrecognized MIPS ABI" return "" } + + if [istarget "mips*el-*-*"] { + append goarch "le" + } } "powerpc*-*-*" { if [check_effective_target_ilp32] { -- cgit v1.1 From 54357b3b84538e0f26b6501fd91bb98170995ff5 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Fri, 23 Jun 2017 13:45:36 +0000 Subject: runtime: improve handling of panic during deferred function When a panic occurs while processing a deferred function that recovered an earlier panic, we shouldn't report the recovered panic in the panic stack trace. Stop doing so by keeping track of the panic that triggered a defer, marking it as aborted if we see the defer again, and discarding aborted panics when a panic is recovered. This is what the gc runtime does. The test for this is TestRecursivePanic in runtime/crash_test.go. We don't run that test yet, but we will soon. Reviewed-on: https://go-review.googlesource.com/46461 From-SVN: r249590 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index b6037a6..d82e012 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -385efb8947af70b8425c833a1ab68ba5f357dfae +c4adba240f9d5af8ab0534316d6b05bd988c432c The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 52607f7ea8d62d0d6abdbc1288da70e75944865c Mon Sep 17 00:00:00 2001 From: Will Schmidt Date: Fri, 23 Jun 2017 14:40:26 +0000 Subject: rs6000.c: Add include of ssa-propagate.h for update_call_from_tree(). [gcc] 2017-06-23 Will Schmidt * config/rs6000/rs6000.c: Add include of ssa-propagate.h for update_call_from_tree(). (rs6000_gimple_fold_builtin): Add handling for early expansion of vector shifts (sl,sr,sra,rl). (builtin_function_type): Add vector shift right instructions to the unsigned argument list. [gcc/testsuite] 2017-06-23 Will Schmidt * gcc.target/powerpc/fold-vec-shift-char.c: New. * gcc.target/powerpc/fold-vec-shift-int.c: New. * gcc.target/powerpc/fold-vec-shift-longlong.c: New. * gcc.target/powerpc/fold-vec-shift-short.c: New. * gcc.target/powerpc/fold-vec-shift-left.c: New. * gcc.target/powerpc/fold-vec-shift-left-fwrapv.c: New. * gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c: New. * gcc.target/powerpc/fold-vec-shift-left-longlong.c: New. From-SVN: r249591 --- gcc/ChangeLog | 8 +++ gcc/config/rs6000/rs6000.c | 79 ++++++++++++++++++++++ gcc/testsuite/ChangeLog | 11 +++ .../gcc.target/powerpc/fold-vec-shift-char.c | 66 ++++++++++++++++++ .../gcc.target/powerpc/fold-vec-shift-int.c | 61 +++++++++++++++++ .../powerpc/fold-vec-shift-left-fwrapv.c | 48 +++++++++++++ .../powerpc/fold-vec-shift-left-longlong-fwrapv.c | 22 ++++++ .../powerpc/fold-vec-shift-left-longlong.c | 22 ++++++ .../gcc.target/powerpc/fold-vec-shift-left.c | 48 +++++++++++++ .../gcc.target/powerpc/fold-vec-shift-longlong.c | 63 +++++++++++++++++ .../gcc.target/powerpc/fold-vec-shift-short.c | 61 +++++++++++++++++ 11 files changed, 489 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-shift-char.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-fwrapv.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c create mode 100644 gcc/testsuite/gcc.target/powerpc/fold-vec-shift-short.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b3a9add..327d809 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-06-23 Will Schmidt + + * config/rs6000/rs6000.c: Add include of ssa-propagate.h for + update_call_from_tree(). (rs6000_gimple_fold_builtin): Add + handling for early expansion of vector shifts (sl,sr,sra,rl). + (builtin_function_type): Add vector shift right instructions + to the unsigned argument list. + 2017-06-23 Bernd Edlinger rtl-optimizatoin/79286 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index de0c6df3..7a38dea 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -77,6 +77,7 @@ #endif #include "case-cfn-macros.h" #include "ppc-auxv.h" +#include "tree-ssa-propagate.h" /* This file should be included last. */ #include "target-def.h" @@ -16571,6 +16572,76 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) gsi_replace (gsi, g, true); return true; } + /* Flavors of vec_rotate_left. */ + case ALTIVEC_BUILTIN_VRLB: + case ALTIVEC_BUILTIN_VRLH: + case ALTIVEC_BUILTIN_VRLW: + case P8V_BUILTIN_VRLD: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* Flavors of vector shift right algebraic. + vec_sra{b,h,w} -> vsra{b,h,w}. */ + case ALTIVEC_BUILTIN_VSRAB: + case ALTIVEC_BUILTIN_VSRAH: + case ALTIVEC_BUILTIN_VSRAW: + case P8V_BUILTIN_VSRAD: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* Flavors of vector shift left. + builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */ + case ALTIVEC_BUILTIN_VSLB: + case ALTIVEC_BUILTIN_VSLH: + case ALTIVEC_BUILTIN_VSLW: + case P8V_BUILTIN_VSLD: + { + arg0 = gimple_call_arg (stmt, 0); + if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0))) + && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0)))) + return false; + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* Flavors of vector shift right. */ + case ALTIVEC_BUILTIN_VSRB: + case ALTIVEC_BUILTIN_VSRH: + case ALTIVEC_BUILTIN_VSRW: + case P8V_BUILTIN_VSRD: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple_seq stmts = NULL; + /* Convert arg0 to unsigned. */ + tree arg0_unsigned + = gimple_build (&stmts, VIEW_CONVERT_EXPR, + unsigned_type_for (TREE_TYPE (arg0)), arg0); + tree res + = gimple_build (&stmts, RSHIFT_EXPR, + TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1); + /* Convert result back to the lhs type. */ + res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + update_call_from_tree (gsi, res); + return true; + } default: break; } @@ -18072,6 +18143,14 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, h.uns_p[2] = 1; break; + /* unsigned second arguments (vector shift right). */ + case ALTIVEC_BUILTIN_VSRB: + case ALTIVEC_BUILTIN_VSRH: + case ALTIVEC_BUILTIN_VSRW: + case P8V_BUILTIN_VSRD: + h.uns_p[2] = 1; + break; + default: break; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 24532f7..4e2defd 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,14 @@ +2017-06-23 Will Schmidt + + * gcc.target/powerpc/fold-vec-shift-char.c: New. + * gcc.target/powerpc/fold-vec-shift-int.c: New. + * gcc.target/powerpc/fold-vec-shift-longlong.c: New. + * gcc.target/powerpc/fold-vec-shift-short.c: New. + * gcc.target/powerpc/fold-vec-shift-left.c: New. + * gcc.target/powerpc/fold-vec-shift-left-fwrapv.c: New. + * gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c: New. + * gcc.target/powerpc/fold-vec-shift-left-longlong.c: New. + 2017-06-23 James Cowgill * go.test/go-test.exp (go-set-goarch): Update MIPS architecture diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-char.c new file mode 100644 index 0000000..ebe91e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-char.c @@ -0,0 +1,66 @@ +/* Verify that overloaded built-ins for vec_sl with char + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +//# vec_sl - shift left +//# vec_sr - shift right +//# vec_sra - shift right algebraic +//# vec_rl - rotate left + +vector signed char +testsl_signed (vector signed char x, vector unsigned char y) +{ + return vec_sl (x, y); +} + +vector unsigned char +testsl_unsigned (vector unsigned char x, vector unsigned char y) +{ + return vec_sl (x, y); +} + +vector signed char +testsr_signed (vector signed char x, vector unsigned char y) +{ + return vec_sr (x, y); +} + +vector unsigned char +testsr_unsigned (vector unsigned char x, vector unsigned char y) +{ + return vec_sr (x, y); +} + +vector signed char +testsra_signed (vector signed char x, vector unsigned char y) +{ + return vec_sra (x, y); +} + +vector unsigned char +testsra_unsigned (vector unsigned char x, vector unsigned char y) +{ + return vec_sra (x, y); +} + +vector signed char +testrl_signed (vector signed char x, vector unsigned char y) +{ + return vec_rl (x, y); +} + +vector unsigned char +testrl_unsigned (vector unsigned char x, vector unsigned char y) +{ + return vec_rl (x, y); +} + +/* { dg-final { scan-assembler-times "vslb" 2 } } */ +/* { dg-final { scan-assembler-times "vsrb" 2 } } */ +/* { dg-final { scan-assembler-times "vsrab" 2 } } */ +/* { dg-final { scan-assembler-times "vrlb" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c new file mode 100644 index 0000000..e9c5fe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-int.c @@ -0,0 +1,61 @@ +/* Verify that overloaded built-ins for vec_sl with int + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector signed int +testsl_signed (vector signed int x, vector unsigned int y) +{ + return vec_sl (x, y); +} + +vector unsigned int +testsl_unsigned (vector unsigned int x, vector unsigned int y) +{ + return vec_sl (x, y); +} + +vector signed int +testsr_signed (vector signed int x, vector unsigned int y) +{ + return vec_sr (x, y); +} + +vector unsigned int +testsr_unsigned (vector unsigned int x, vector unsigned int y) +{ + return vec_sr (x, y); +} + +vector signed int +testsra_signed (vector signed int x, vector unsigned int y) +{ + return vec_sra (x, y); +} + +vector unsigned int +testsra_unsigned (vector unsigned int x, vector unsigned int y) +{ + return vec_sra (x, y); +} + +vector signed int +testrl_signed (vector signed int x, vector unsigned int y) +{ + return vec_rl (x, y); +} + +vector unsigned int +testrl_unsigned (vector unsigned int x, vector unsigned int y) +{ + return vec_rl (x, y); +} + +/* { dg-final { scan-assembler-times "vslw" 2 } } */ +/* { dg-final { scan-assembler-times "vsrw" 2 } } */ +/* { dg-final { scan-assembler-times "vsraw" 2 } } */ +/* { dg-final { scan-assembler-times "vrlw" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-fwrapv.c new file mode 100644 index 0000000..3426480 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-fwrapv.c @@ -0,0 +1,48 @@ +/* Verify that overloaded built-ins for vec_sl produce the right results. */ +/* This test covers the shift left tests with the -fwrapv option. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -fwrapv" } */ + +#include + +vector signed char +testsl_signed_char (vector signed char x, vector unsigned char y) +{ + return vec_sl (x, y); +} + +vector unsigned char +testsl_unsigned_char (vector unsigned char x, vector unsigned char y) +{ + return vec_sl (x, y); +} + +vector signed short +testsl_signed_short (vector signed short x, vector unsigned short y) +{ + return vec_sl (x, y); +} + +vector unsigned short +testsl_unsigned_short (vector unsigned short x, vector unsigned short y) +{ + return vec_sl (x, y); +} + +vector signed int +testsl_signed_int (vector signed int x, vector unsigned int y) +{ + return vec_sl (x, y); +} + +vector unsigned int +testsl_unsigned_int (vector unsigned int x, vector unsigned int y) +{ + return vec_sl (x, y); +} + +/* { dg-final { scan-assembler-times "vslb" 2 } } */ +/* { dg-final { scan-assembler-times "vslh" 2 } } */ +/* { dg-final { scan-assembler-times "vslw" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c new file mode 100644 index 0000000..b776683 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c @@ -0,0 +1,22 @@ +/* Verify that overloaded built-ins for vec_sl produce the right results. */ +/* This test covers the shift left tests with the -fwrapv option. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -mpower8-vector -fwrapv" } */ + +#include + +vector signed long long +testsl_signed_longlong (vector signed long long x, vector unsigned long long y) +{ + return vec_sl (x, y); +} + +vector unsigned long long +testsl_unsigned_longlong (vector unsigned long long x, vector unsigned long long y) +{ + return vec_sl (x, y); +} + +/* { dg-final { scan-assembler-times "vsld" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c new file mode 100644 index 0000000..f040486 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c @@ -0,0 +1,22 @@ +/* cross section of shift tests specific for shift-left. + * This is a counterpart to the fold-vec-shift-left-frwapv test. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mpower8-vector -O2" } */ + +#include + +vector signed long long +testsl_signed_longlong (vector signed long long x, vector unsigned long long y) +{ + return vec_sl (x, y); +} + +vector unsigned long long +testsl_unsigned_longlong (vector unsigned long long x, vector unsigned long long y) +{ + return vec_sl (x, y); +} + +/* { dg-final { scan-assembler-times "vsld" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left.c new file mode 100644 index 0000000..36f92b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left.c @@ -0,0 +1,48 @@ +/* cross section of shift tests specific for shift-left. + * This is a counterpart to the fold-vec-shift-left-frwapv test. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector signed char +testsl_signed_char (vector signed char x, vector unsigned char y) +{ + return vec_sl (x, y); +} + +vector unsigned char +testsl_unsigned_char (vector unsigned char x, vector unsigned char y) +{ + return vec_sl (x, y); +} + +vector signed short +testsl_signed_short (vector signed short x, vector unsigned short y) +{ + return vec_sl (x, y); +} + +vector unsigned short +testsl_unsigned_short (vector unsigned short x, vector unsigned short y) +{ + return vec_sl (x, y); +} + +vector signed int +testsl_signed_int (vector signed int x, vector unsigned int y) +{ + return vec_sl (x, y); +} + +vector unsigned int +testsl_unsigned_int (vector unsigned int x, vector unsigned int y) +{ + return vec_sl (x, y); +} + +/* { dg-final { scan-assembler-times "vslb" 2 } } */ +/* { dg-final { scan-assembler-times "vslh" 2 } } */ +/* { dg-final { scan-assembler-times "vslw" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c new file mode 100644 index 0000000..97b82cf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c @@ -0,0 +1,63 @@ +/* Verify that overloaded built-ins for vec_sl with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include + +vector signed long long +testsl_signed (vector signed long long x, vector unsigned long long y) +{ + return vec_sl (x, y); +} + +vector unsigned long long +testsl_unsigned (vector unsigned long long x, vector unsigned long long y) +{ + return vec_sl (x, y); +} + +vector signed long long +testsr_signed (vector signed long long x, vector unsigned long long y) +{ + return vec_sr (x, y); +} + +vector unsigned long long +testsr_unsigned (vector unsigned long long x, vector unsigned long long y) +{ + return vec_sr (x, y); +} + +vector signed long long +testsra_signed (vector signed long long x, vector unsigned long long y) +{ + return vec_sra (x, y); +} + +/* watch for PR 79544 here (vsrd / vsrad issue) */ +vector unsigned long long +testsra_unsigned (vector unsigned long long x, vector unsigned long long y) +{ + return vec_sra (x, y); +} + +vector signed long long +testrl_signed (vector signed long long x, vector unsigned long long y) +{ + return vec_rl (x, y); +} + +vector unsigned long long +testrl_unsigned (vector unsigned long long x, vector unsigned long long y) +{ + return vec_rl (x, y); +} + +/* { dg-final { scan-assembler-times "vsld" 2 } } */ +/* { dg-final { scan-assembler-times "vsrd" 2 } } */ +/* { dg-final { scan-assembler-times "vsrad" 2 } } */ +/* { dg-final { scan-assembler-times "vrld" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-short.c new file mode 100644 index 0000000..4ca7c18 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-short.c @@ -0,0 +1,61 @@ +/* Verify that overloaded built-ins for vec_sl with short + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +vector signed short +testsl_signed (vector signed short x, vector unsigned short y) +{ + return vec_sl (x, y); +} + +vector unsigned short +testsl_unsigned (vector unsigned short x, vector unsigned short y) +{ + return vec_sl (x, y); +} + +vector signed short +testsr_signed (vector signed short x, vector unsigned short y) +{ + return vec_sr (x, y); +} + +vector unsigned short +testsr_unsigned (vector unsigned short x, vector unsigned short y) +{ + return vec_sr (x, y); +} + +vector signed short +testsra_signed (vector signed short x, vector unsigned short y) +{ + return vec_sra (x, y); +} + +vector unsigned short +testsra_unsigned (vector unsigned short x, vector unsigned short y) +{ + return vec_sra (x, y); +} + +vector signed short +testrl_signed (vector signed short x, vector unsigned short y) +{ + return vec_rl (x, y); +} + +vector unsigned short +testrl_unsigned (vector unsigned short x, vector unsigned short y) +{ + return vec_rl (x, y); +} + +/* { dg-final { scan-assembler-times "vslh" 2 } } */ +/* { dg-final { scan-assembler-times "vsrh" 2 } } */ +/* { dg-final { scan-assembler-times "vsrah" 2 } } */ +/* { dg-final { scan-assembler-times "vrlh" 2 } } */ -- cgit v1.1 From 8447a92f07bd4e4b0dd1b2fef60591734c3d188a Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Fri, 23 Jun 2017 08:57:52 -0600 Subject: * gcc.c-torture/compile/stack-check-1.c: Require "untyped_assembly". From-SVN: r249592 --- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.c-torture/compile/stack-check-1.c | 1 + 2 files changed, 5 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4e2defd..8c55862 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-22 Jeff Law + + * gcc.c-torture/compile/stack-check-1.c: Require "untyped_assembly". + 2017-06-23 Will Schmidt * gcc.target/powerpc/fold-vec-shift-char.c: New. diff --git a/gcc/testsuite/gcc.c-torture/compile/stack-check-1.c b/gcc/testsuite/gcc.c-torture/compile/stack-check-1.c index 4058eb5..5c99688 100644 --- a/gcc/testsuite/gcc.c-torture/compile/stack-check-1.c +++ b/gcc/testsuite/gcc.c-torture/compile/stack-check-1.c @@ -1,2 +1,3 @@ +/* { dg-require-effective-target untyped_assembly } */ /* { dg-additional-options "-fstack-check" } */ #include "20031023-1.c" -- cgit v1.1 From ef2361cbd8462374b28e9e8becf8710a9b30d125 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Fri, 23 Jun 2017 09:57:58 -0600 Subject: contrib.texi: Add entry for Steven Pemberton's work on enquire. * doc/contrib.texi: Add entry for Steven Pemberton's work on enquire. From-SVN: r249593 --- gcc/ChangeLog | 5 +++++ gcc/doc/contrib.texi | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 327d809..130fa37 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-23 Jeff Law + + * doc/contrib.texi: Add entry for Steven Pemberton's work on + enquire. + 2017-06-23 Will Schmidt * config/rs6000/rs6000.c: Add include of ssa-propagate.h for diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi index 4f5ffc1..60b7102 100644 --- a/gcc/doc/contrib.texi +++ b/gcc/doc/contrib.texi @@ -761,6 +761,11 @@ clean-ups and porting work, and maintaining the IRIX, Solaris 2, and Tru64 UNIX ports. @item +Steven Pemberton for his contribution of @file{enquire} which allowed GCC to +determine various properties of the floating point unit and generate +@file{float.h} in older versions of GCC. + +@item Hartmut Penner for work on the s390 port. @item -- cgit v1.1 From 5f0b897b2ee47bf3845d924dd5bc3beb949bc78b Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Fri, 23 Jun 2017 16:03:49 +0000 Subject: compiler: add go:notinheap magic comment Implement go:notinheap as the gc compiler does. A type marked as go:notinheap may not live in the heap, and does not require a write barrier. Struct and array types that incorporate notinheap types are themselves notinheap. Allocating a value of a notinheap type on the heap is an error. This is not just an optimization. There is code where a write barrier may not occur that was getting a write barrier with gccgo but not gc, because the types in question were notinheap. The case I found was setting the mcache field in exitsyscallfast. Reviewed-on: https://go-review.googlesource.com/46490 From-SVN: r249594 --- gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/expressions.cc | 14 +++++++++++ gcc/go/gofrontend/expressions.h | 3 +++ gcc/go/gofrontend/lex.cc | 5 ++++ gcc/go/gofrontend/lex.h | 3 ++- gcc/go/gofrontend/parse.cc | 52 +++++++++++++++++++++++++++++----------- gcc/go/gofrontend/parse.h | 12 +++++----- gcc/go/gofrontend/types.cc | 49 +++++++++++++++++++++++++++++++++++++ gcc/go/gofrontend/types.h | 39 +++++++++++++++++++++++++++++- gcc/go/gofrontend/wb.cc | 22 +++++++++++++++++ 10 files changed, 178 insertions(+), 23 deletions(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index d82e012..02be610 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -c4adba240f9d5af8ab0534316d6b05bd988c432c +29c61dc3c5151df5de9362b7882ccf04679df976 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. diff --git a/gcc/go/gofrontend/expressions.cc b/gcc/go/gofrontend/expressions.cc index 5eec731..12505b2 100644 --- a/gcc/go/gofrontend/expressions.cc +++ b/gcc/go/gofrontend/expressions.cc @@ -7499,6 +7499,10 @@ Builtin_call_expression::lower_make(Statement_inserter* inserter) } Type* type = first_arg->type(); + if (!type->in_heap()) + go_error_at(first_arg->location(), + "can't make slice of go:notinheap type"); + bool is_slice = false; bool is_map = false; bool is_chan = false; @@ -8742,6 +8746,9 @@ Builtin_call_expression::do_check_types(Gogo*) } Type* element_type = slice_type->array_type()->element_type(); + if (!element_type->in_heap()) + go_error_at(args->front()->location(), + "can't append to slice of go:notinheap type"); if (this->is_varargs()) { if (!args->back()->type()->is_slice_type() @@ -12436,6 +12443,13 @@ Allocation_expression::do_type() return Type::make_pointer_type(this->type_); } +void +Allocation_expression::do_check_types(Gogo*) +{ + if (!this->type_->in_heap()) + go_error_at(this->location(), "can't heap allocate go:notinheap type"); +} + // Make a copy of an allocation expression. Expression* diff --git a/gcc/go/gofrontend/expressions.h b/gcc/go/gofrontend/expressions.h index 43fb854..a144ff4 100644 --- a/gcc/go/gofrontend/expressions.h +++ b/gcc/go/gofrontend/expressions.h @@ -3220,6 +3220,9 @@ class Allocation_expression : public Expression do_determine_type(const Type_context*) { } + void + do_check_types(Gogo*); + Expression* do_copy(); diff --git a/gcc/go/gofrontend/lex.cc b/gcc/go/gofrontend/lex.cc index beb3652..e9f11c2 100644 --- a/gcc/go/gofrontend/lex.cc +++ b/gcc/go/gofrontend/lex.cc @@ -1897,6 +1897,11 @@ Lex::skip_cpp_comment() // Applies to the next function. Do not inline the function. this->pragmas_ |= GOPRAGMA_NOINLINE; } + else if (verb == "go:notinheap") + { + // Applies to the next type. The type does not live in the heap. + this->pragmas_ |= GOPRAGMA_NOTINHEAP; + } else if (verb == "go:systemstack") { // Applies to the next function. It must run on the system stack. diff --git a/gcc/go/gofrontend/lex.h b/gcc/go/gofrontend/lex.h index 0a7a842..a8b7091 100644 --- a/gcc/go/gofrontend/lex.h +++ b/gcc/go/gofrontend/lex.h @@ -64,7 +64,8 @@ enum GoPragma GOPRAGMA_NOWRITEBARRIER = 1 << 6, // No write barriers. GOPRAGMA_NOWRITEBARRIERREC = 1 << 7, // No write barriers here or callees. GOPRAGMA_CGOUNSAFEARGS = 1 << 8, // Pointer to arg is pointer to all. - GOPRAGMA_UINTPTRESCAPES = 1 << 9 // uintptr(p) escapes. + GOPRAGMA_UINTPTRESCAPES = 1 << 9, // uintptr(p) escapes. + GOPRAGMA_NOTINHEAP = 1 << 10 // type is not in heap. }; // A token returned from the lexer. diff --git a/gcc/go/gofrontend/parse.cc b/gcc/go/gofrontend/parse.cc index 84840fb..28b1772 100644 --- a/gcc/go/gofrontend/parse.cc +++ b/gcc/go/gofrontend/parse.cc @@ -1310,14 +1310,16 @@ Parse::declaration() const Token* token = this->peek_token(); unsigned int pragmas = this->lex_->get_and_clear_pragmas(); - if (pragmas != 0 && !token->is_keyword(KEYWORD_FUNC)) + if (pragmas != 0 + && !token->is_keyword(KEYWORD_FUNC) + && !token->is_keyword(KEYWORD_TYPE)) go_warning_at(token->location(), 0, "ignoring magic comment before non-function"); if (token->is_keyword(KEYWORD_CONST)) this->const_decl(); else if (token->is_keyword(KEYWORD_TYPE)) - this->type_decl(); + this->type_decl(pragmas); else if (token->is_keyword(KEYWORD_VAR)) this->var_decl(); else if (token->is_keyword(KEYWORD_FUNC)) @@ -1342,7 +1344,8 @@ Parse::declaration_may_start_here() // Decl

= P | "(" [ List

] ")" . void -Parse::decl(void (Parse::*pfn)(void*), void* varg) +Parse::decl(void (Parse::*pfn)(void*, unsigned int), void* varg, + unsigned int pragmas) { if (this->peek_token()->is_eof()) { @@ -1352,9 +1355,12 @@ Parse::decl(void (Parse::*pfn)(void*), void* varg) } if (!this->peek_token()->is_op(OPERATOR_LPAREN)) - (this->*pfn)(varg); + (this->*pfn)(varg, pragmas); else { + if (pragmas != 0) + go_warning_at(this->location(), 0, + "ignoring magic //go:... comment before group"); if (!this->advance_token()->is_op(OPERATOR_RPAREN)) { this->list(pfn, varg, true); @@ -1378,9 +1384,10 @@ Parse::decl(void (Parse::*pfn)(void*), void* varg) // might follow. This is either a '}' or a ')'. void -Parse::list(void (Parse::*pfn)(void*), void* varg, bool follow_is_paren) +Parse::list(void (Parse::*pfn)(void*, unsigned int), void* varg, + bool follow_is_paren) { - (this->*pfn)(varg); + (this->*pfn)(varg, 0); Operator follow = follow_is_paren ? OPERATOR_RPAREN : OPERATOR_RCURLY; while (this->peek_token()->is_op(OPERATOR_SEMICOLON) || this->peek_token()->is_op(OPERATOR_COMMA)) @@ -1389,7 +1396,7 @@ Parse::list(void (Parse::*pfn)(void*), void* varg, bool follow_is_paren) go_error_at(this->location(), "unexpected comma"); if (this->advance_token()->is_op(follow)) break; - (this->*pfn)(varg); + (this->*pfn)(varg, 0); } } @@ -1508,17 +1515,17 @@ Parse::const_spec(Type** last_type, Expression_list** last_expr_list) // TypeDecl = "type" Decl . void -Parse::type_decl() +Parse::type_decl(unsigned int pragmas) { go_assert(this->peek_token()->is_keyword(KEYWORD_TYPE)); this->advance_token(); - this->decl(&Parse::type_spec, NULL); + this->decl(&Parse::type_spec, NULL, pragmas); } // TypeSpec = identifier ["="] Type . void -Parse::type_spec(void*) +Parse::type_spec(void*, unsigned int pragmas) { const Token* token = this->peek_token(); if (!token->is_identifier()) @@ -1592,6 +1599,15 @@ Parse::type_spec(void*) this->gogo_->define_type(named_type, nt); go_assert(named_type->package() == NULL); + + if ((pragmas & GOPRAGMA_NOTINHEAP) != 0) + { + nt->set_not_in_heap(); + pragmas &= ~GOPRAGMA_NOTINHEAP; + } + if (pragmas != 0) + go_warning_at(location, 0, + "ignoring magic //go:... comment before type"); } else { @@ -1608,15 +1624,19 @@ Parse::var_decl() { go_assert(this->peek_token()->is_keyword(KEYWORD_VAR)); this->advance_token(); - this->decl(&Parse::var_spec, NULL); + this->decl(&Parse::var_spec, NULL, 0); } // VarSpec = IdentifierList // ( CompleteType [ "=" ExpressionList ] | "=" ExpressionList ) . void -Parse::var_spec(void*) +Parse::var_spec(void*, unsigned int pragmas) { + if (pragmas != 0) + go_warning_at(this->location(), 0, + "ignoring magic //go:... comment before var"); + // Get the variable names. Typed_identifier_list til; this->identifier_list(&til); @@ -5698,14 +5718,18 @@ Parse::import_decl() { go_assert(this->peek_token()->is_keyword(KEYWORD_IMPORT)); this->advance_token(); - this->decl(&Parse::import_spec, NULL); + this->decl(&Parse::import_spec, NULL, 0); } // ImportSpec = [ "." | PackageName ] PackageFileName . void -Parse::import_spec(void*) +Parse::import_spec(void*, unsigned int pragmas) { + if (pragmas != 0) + go_warning_at(this->location(), 0, + "ignoring magic //go:... comment before import"); + const Token* token = this->peek_token(); Location location = token->location(); diff --git a/gcc/go/gofrontend/parse.h b/gcc/go/gofrontend/parse.h index e13dcc9..e416072 100644 --- a/gcc/go/gofrontend/parse.h +++ b/gcc/go/gofrontend/parse.h @@ -182,14 +182,14 @@ class Parse void method_spec(Typed_identifier_list*); void declaration(); bool declaration_may_start_here(); - void decl(void (Parse::*)(void*), void*); - void list(void (Parse::*)(void*), void*, bool); + void decl(void (Parse::*)(void*, unsigned int), void*, unsigned int pragmas); + void list(void (Parse::*)(void*, unsigned int), void*, bool); void const_decl(); void const_spec(Type**, Expression_list**); - void type_decl(); - void type_spec(void*); + void type_decl(unsigned int pragmas); + void type_spec(void*, unsigned int pragmas); void var_decl(); - void var_spec(void*); + void var_spec(void*, unsigned int pragmas); void init_vars(const Typed_identifier_list*, Type*, Expression_list*, bool is_coloneq, Location); bool init_vars_from_call(const Typed_identifier_list*, Type*, Expression*, @@ -278,7 +278,7 @@ class Parse void goto_stat(); void package_clause(); void import_decl(); - void import_spec(void*); + void import_spec(void*, unsigned int pragmas); void reset_iota(); int iota_value(); diff --git a/gcc/go/gofrontend/types.cc b/gcc/go/gofrontend/types.cc index b9ad41e..b2756fd 100644 --- a/gcc/go/gofrontend/types.cc +++ b/gcc/go/gofrontend/types.cc @@ -746,6 +746,20 @@ Type::are_convertible(const Type* lhs, const Type* rhs, std::string* reason) if (Type::are_assignable(lhs, rhs, reason)) return true; + // A pointer to a regular type may not be converted to a pointer to + // a type that may not live in the heap, except when converting to + // unsafe.Pointer. + if (lhs->points_to() != NULL + && rhs->points_to() != NULL + && !rhs->points_to()->in_heap() + && lhs->points_to()->in_heap() + && !lhs->is_unsafe_pointer_type()) + { + if (reason != NULL) + reason->assign(_("conversion from notinheap type to normal type")); + return false; + } + // The types are convertible if they have identical underlying // types, ignoring struct field tags. if ((lhs->named_type() != NULL || rhs->named_type() != NULL) @@ -5955,6 +5969,24 @@ Struct_type::do_needs_key_update() return false; } +// Return whether this struct type is permitted to be in the heap. + +bool +Struct_type::do_in_heap() +{ + const Struct_field_list* fields = this->fields_; + if (fields == NULL) + return true; + for (Struct_field_list::const_iterator pf = fields->begin(); + pf != fields->end(); + ++pf) + { + if (!pf->type()->in_heap()) + return false; + } + return true; +} + // Build identity and hash functions for this struct. // Hash code. @@ -8026,6 +8058,10 @@ Map_type::do_verify() // The runtime support uses "map[void]void". if (!this->key_type_->is_comparable() && !this->key_type_->is_void_type()) go_error_at(this->location_, "invalid map key type"); + if (!this->key_type_->in_heap()) + go_error_at(this->location_, "go:notinheap map key not allowed"); + if (!this->val_type_->in_heap()) + go_error_at(this->location_, "go:notinheap map value not allowed"); return true; } @@ -8540,6 +8576,19 @@ Type::make_map_type(Type* key_type, Type* val_type, Location location) // Class Channel_type. +// Verify. + +bool +Channel_type::do_verify() +{ + // We have no location for this error, but this is not something the + // ordinary user will see. + if (!this->element_type_->in_heap()) + go_error_at(Linemap::unknown_location(), + "chan of go:notinheap type not allowed"); + return true; +} + // Hash code. unsigned int diff --git a/gcc/go/gofrontend/types.h b/gcc/go/gofrontend/types.h index 3f6240b..aeb04d6 100644 --- a/gcc/go/gofrontend/types.h +++ b/gcc/go/gofrontend/types.h @@ -636,6 +636,11 @@ class Type needs_key_update() { return this->do_needs_key_update(); } + // Whether the type is permitted in the heap. + bool + in_heap() + { return this->do_in_heap(); } + // Return a hash code for this type for the method hash table. // Types which are equivalent according to are_identical will have // the same hash code. @@ -1051,6 +1056,10 @@ class Type do_needs_key_update() { return false; } + virtual bool + do_in_heap() + { return true; } + virtual unsigned int do_hash_for_method(Gogo*) const; @@ -1343,6 +1352,8 @@ class Type // The GC symbol for this type. This starts out as NULL and // is filled in as needed. Bvariable* gc_symbol_var_; + // Whether this type can appear in the heap. + bool in_heap_; }; // Type hash table operations. @@ -2417,6 +2428,9 @@ class Struct_type : public Type bool do_needs_key_update(); + bool + do_in_heap(); + unsigned int do_hash_for_method(Gogo*) const; @@ -2590,6 +2604,10 @@ class Array_type : public Type do_needs_key_update() { return this->element_type_->needs_key_update(); } + bool + do_in_heap() + { return this->length_ == NULL || this->element_type_->in_heap(); } + unsigned int do_hash_for_method(Gogo*) const; @@ -2811,6 +2829,9 @@ class Channel_type : public Type { return Type::traverse(this->element_type_, traverse); } bool + do_verify(); + + bool do_has_pointer() const { return true; } @@ -3047,7 +3068,7 @@ class Named_type : public Type type_(type), local_methods_(NULL), all_methods_(NULL), interface_method_tables_(NULL), pointer_interface_method_tables_(NULL), location_(location), named_btype_(NULL), dependencies_(), - is_alias_(false), is_visible_(true), is_error_(false), + is_alias_(false), is_visible_(true), is_error_(false), in_heap_(true), is_placeholder_(false), is_converted_(false), is_circular_(false), is_verified_(false), seen_(false), seen_in_compare_is_identity_(false), seen_in_get_backend_(false), seen_alias_(false) @@ -3079,6 +3100,11 @@ class Named_type : public Type set_is_alias() { this->is_alias_ = true; } + // Mark this type as not permitted in the heap. + void + set_not_in_heap() + { this->in_heap_ = false; } + // Return the function in which this type is defined. This will // return NULL for a type defined in global scope. const Named_object* @@ -3277,6 +3303,10 @@ class Named_type : public Type bool do_needs_key_update(); + bool + do_in_heap() + { return this->in_heap_ && this->type_->in_heap(); } + unsigned int do_hash_for_method(Gogo*) const; @@ -3344,6 +3374,9 @@ class Named_type : public Type bool is_visible_; // Whether this type is erroneous. bool is_error_; + // Whether this type is permitted in the heap. This is true by + // default, false if there is a magic //go:notinheap comment. + bool in_heap_; // Whether the current value of named_btype_ is a placeholder for // which the final size of the type is not known. bool is_placeholder_; @@ -3436,6 +3469,10 @@ class Forward_declaration_type : public Type do_needs_key_update() { return this->real_type()->needs_key_update(); } + bool + do_in_heap() + { return this->real_type()->in_heap(); } + unsigned int do_hash_for_method(Gogo* gogo) const { return this->real_type()->hash_for_method(gogo); } diff --git a/gcc/go/gofrontend/wb.cc b/gcc/go/gofrontend/wb.cc index 5a49961..cbefc11 100644 --- a/gcc/go/gofrontend/wb.cc +++ b/gcc/go/gofrontend/wb.cc @@ -156,6 +156,13 @@ Write_barriers::variable(Named_object* no) if (!var->has_pre_init() && init->is_static_initializer()) return TRAVERSE_CONTINUE; + // Nothing to do for a type that can not be in the heap, or a + // pointer to a type that can not be in the heap. + if (!var->type()->in_heap()) + return TRAVERSE_CONTINUE; + if (var->type()->points_to() != NULL && !var->type()->points_to()->in_heap()) + return TRAVERSE_CONTINUE; + // Otherwise change the initializer into a pre_init assignment // statement with a write barrier. @@ -215,6 +222,14 @@ Write_barriers::statement(Block* block, size_t* pindex, Statement* s) if (!var->type()->has_pointer()) break; + // Nothing to do for a type that can not be in the heap, or a + // pointer to a type that can not be in the heap. + if (!var->type()->in_heap()) + break; + if (var->type()->points_to() != NULL + && !var->type()->points_to()->in_heap()) + break; + // Otherwise initialize the variable with a write barrier. Function* function = this->function_; @@ -345,6 +360,13 @@ Gogo::assign_needs_write_barrier(Expression* lhs) } } + // Nothing to do for a type that can not be in the heap, or a + // pointer to a type that can not be in the heap. + if (!lhs->type()->in_heap()) + return false; + if (lhs->type()->points_to() != NULL && !lhs->type()->points_to()->in_heap()) + return false; + // Write barrier needed in other cases. return true; } -- cgit v1.1 From bb96aa6726d1fac7e2500ef37d1193eed00b03f1 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Fri, 23 Jun 2017 16:05:44 +0000 Subject: runtime: don't crash if no p in kickoff The kickoff function for g0 can be invoked without a p, for example from mcall(exitsyscall0) in exitsyscall after exitsyscall has cleared the p field. The assignment gp.param = nil will invoke a write barrier. If gp.param is not already nil, this will require a p. Avoid the problem for a specific case that is known to be OK: when the value in gp.param is a *g. Reviewed-on: https://go-review.googlesource.com/46512 From-SVN: r249595 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 02be610..473eeca 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -29c61dc3c5151df5de9362b7882ccf04679df976 +f107cc8bced1939b0083231fc1ea24669ca4832c The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 3c76bd9257081e6cbbaecf5bcb57cec64b0a6d31 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Fri, 23 Jun 2017 17:10:18 +0000 Subject: os: align siginfo argument to waitid Backport https://golang.org/cl/46511 from gc trunk, as it may fix a bug reported for gccgo running on MIPS (https://groups.google.com/d/msg/golang-dev/sDg-t1_DPw0/-AJmLxgPBQAJ). Reviewed-on: https://go-review.googlesource.com/46571 From-SVN: r249599 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index 473eeca..eb58bbd 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -f107cc8bced1939b0083231fc1ea24669ca4832c +c49ba1ca392b3c23a4b3934e0a95a908b1dc2f1d The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From 08c273bb9ca995bc8c8f58a3cbdb2be6a47765bd Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Fri, 23 Jun 2017 19:37:27 +0200 Subject: Fix expand_builtin_atomic_fetch_op for pre-op (PR80902) __atomic_add_fetch adds a value to some memory, and returns the result. If there is no direct support for this, expand_builtin_atomic_fetch_op is asked to implement this as __atomic_fetch_add (which returns the original value of the mem), followed by the addition. Now, the __atomic_add_fetch could have been a tail call, but we shouldn't perform the __atomic_fetch_add as a tail call: following code would not be executed, and in fact thrown away because there is a barrier after tail calls. This fixes it. PR middle-end/80902 * builtins.c (expand_builtin_atomic_fetch_op): If emitting code after a call, force the call to not be a tail call. From-SVN: r249603 --- gcc/ChangeLog | 6 ++++++ gcc/builtins.c | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 130fa37..ff2c723 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-06-23 Segher Boessenkool + + PR middle-end/80902 + * builtins.c (expand_builtin_atomic_fetch_op): If emitting code after + a call, force the call to not be a tail call. + 2017-06-23 Jeff Law * doc/contrib.texi: Add entry for Steven Pemberton's work on diff --git a/gcc/builtins.c b/gcc/builtins.c index ce657bf..7e829ef 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -6079,6 +6079,12 @@ expand_builtin_atomic_fetch_op (machine_mode mode, tree exp, rtx target, gcc_assert (TREE_OPERAND (addr, 0) == fndecl); TREE_OPERAND (addr, 0) = builtin_decl_explicit (ext_call); + /* If we will emit code after the call, the call can not be a tail call. + If it is emitted as a tail call, a barrier is emitted after it, and + then all trailing code is removed. */ + if (!ignore) + CALL_EXPR_TAILCALL (exp) = 0; + /* Expand the call here so we can emit trailing code. */ ret = expand_call (exp, target, ignore); -- cgit v1.1 From aa9ace3e6fd3e0e879f4f24adf8befbc3ed1e1b5 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 23 Jun 2017 19:46:21 +0200 Subject: trans.c (gnat_to_gnu): Initialize sync to false to avoid UB. * gcc-interface/trans.c (gnat_to_gnu): Initialize sync to false to avoid UB. From-SVN: r249604 --- gcc/ada/ChangeLog | 5 +++++ gcc/ada/gcc-interface/trans.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index fce09a0..dc8f279 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,8 @@ +2017-06-23 Jakub Jelinek + + * gcc-interface/trans.c (gnat_to_gnu): Initialize sync to false to + avoid UB. + 2017-06-21 Pierre-Marie de Rodat * gcc-interface/ada-tree.h (DECL_FUNCTION_IS_DEF): Update copyright diff --git a/gcc/ada/gcc-interface/trans.c b/gcc/ada/gcc-interface/trans.c index 79d0995..7844bd7 100644 --- a/gcc/ada/gcc-interface/trans.c +++ b/gcc/ada/gcc-interface/trans.c @@ -5883,7 +5883,7 @@ gnat_to_gnu (Node_Id gnat_node) tree gnu_result_type = void_type_node; tree gnu_expr, gnu_lhs, gnu_rhs; Node_Id gnat_temp; - bool sync; + bool sync = false; /* Save node number for error message and set location information. */ error_gnat_node = gnat_node; -- cgit v1.1 From 9761349c768b0ea3fc12d2b36bb04ceb2d3aff8b Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Fri, 23 Jun 2017 18:08:31 +0000 Subject: re PR ipa/81185 (Target clones support generates awkward names) 2017-06-23 Michael Meissner PR ipa/81185 * multiple_target.c (create_dispatcher_calls): Only create the dispatcher call if the function is the default clone of a versioned function. From-SVN: r249605 --- gcc/ChangeLog | 7 +++++++ gcc/multiple_target.c | 3 ++- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ff2c723..3e43b44 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-06-23 Michael Meissner + + PR ipa/81185 + * multiple_target.c (create_dispatcher_calls): Only create the + dispatcher call if the function is the default clone of a + versioned function. + 2017-06-23 Segher Boessenkool PR middle-end/80902 diff --git a/gcc/multiple_target.c b/gcc/multiple_target.c index bdb5b3b..38d6892 100644 --- a/gcc/multiple_target.c +++ b/gcc/multiple_target.c @@ -64,7 +64,8 @@ create_dispatcher_calls (struct cgraph_node *node) { ipa_ref *ref; - if (!DECL_FUNCTION_VERSIONED (node->decl)) + if (!DECL_FUNCTION_VERSIONED (node->decl) + || !is_function_default_version (node->decl)) return; auto_vec edges_to_redirect; -- cgit v1.1 From 37416b699f362c378a0351c3b2b2e32754a1cc76 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Fri, 23 Jun 2017 18:25:10 +0000 Subject: re PR target/80510 (Optimize Power7/power8 Altivec load/stores) [gcc] 2017-06-23 Michael Meissner PR target/80510 * config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in 32-bit, since indexed is not valid for DImode. (mov_hardfloat32): Reorder ISA 2.07 load/stores before ISA 3.0 d-form load/stores to be the same as mov_hardfloat64. (define_peephole2 for Altivec d-form load): Add 32-bit support. (define_peephole2 for Altivec d-form store): Likewise. [gcc/testsuite] 2017-06-23 Michael Meissner PR target/80510 * gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit. * gcc.target/powerpc/pr80510-2.c: Likewise. From-SVN: r249607 --- gcc/ChangeLog | 8 ++++++++ gcc/config/rs6000/rs6000.md | 28 +++++++++++++++------------- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/powerpc/pr80510-1.c | 6 ++---- gcc/testsuite/gcc.target/powerpc/pr80510-2.c | 6 ++---- 5 files changed, 33 insertions(+), 21 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3e43b44..5019018 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2017-06-23 Michael Meissner + PR target/80510 + * config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in + 32-bit, since indexed is not valid for DImode. + (mov_hardfloat32): Reorder ISA 2.07 load/stores before ISA + 3.0 d-form load/stores to be the same as mov_hardfloat64. + (define_peephole2 for Altivec d-form load): Add 32-bit support. + (define_peephole2 for Altivec d-form store): Likewise. + PR ipa/81185 * multiple_target.c (create_dispatcher_calls): Only create the dispatcher call if the function is the default clone of a diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8e1b460..f78dbf9 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -690,7 +690,9 @@ ;; Iterator to optimize the following cases: ;; D-form load to FPR register & move to Altivec register ;; Move Altivec register to FPR register and store -(define_mode_iterator ALTIVEC_DFORM [DI DF SF]) +(define_mode_iterator ALTIVEC_DFORM [DF + SF + (DI "TARGET_POWERPC64")]) ;; Start with fixed-point load and store insns. Here we put only the more @@ -7391,8 +7393,8 @@ ;; except for 0.0 which can be created on VSX with an xor instruction. (define_insn "*mov_hardfloat32" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,Z,,wY,,,!r,Y,r,!r") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,,wY,,,,,r,Y,r"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,wY,,Z,,,!r,Y,r,!r") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,,Z,,,,,r,Y,r"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7400,10 +7402,10 @@ stfd%U0%X0 %1,%0 lfd%U1%X1 %0,%1 fmr %0,%1 - lxsd%U1x %x0,%y1 - stxsd%U0x %x1,%y0 lxsd %0,%1 stxsd %1,%0 + lxsd%U1x %x0,%y1 + stxsd%U0x %x1,%y0 xxlor %x0,%x1,%x1 xxlxor %x0,%x0,%x0 # @@ -13967,13 +13969,13 @@ ;; LXSDX 32,3,9 (define_peephole2 - [(match_scratch:DI 0 "b") + [(match_scratch:P 0 "b") (set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand") (match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand")) (set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand") (match_dup 1))] - "TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_ - && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])" + "TARGET_VSX && TARGET_UPPER_REGS_ && !TARGET_P9_DFORM_SCALAR + && peep2_reg_dead_p (2, operands[1])" [(set (match_dup 0) (match_dup 4)) (set (match_dup 3) @@ -13988,7 +13990,7 @@ add_op0 = XEXP (addr, 0); add_op1 = XEXP (addr, 1); gcc_assert (REG_P (add_op0)); - new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg); + new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg); operands[4] = add_op1; operands[5] = change_address (mem, mode, new_addr); @@ -14004,13 +14006,13 @@ ;; STXSDX 32,3,9 (define_peephole2 - [(match_scratch:DI 0 "b") + [(match_scratch:P 0 "b") (set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand") (match_operand:ALTIVEC_DFORM 2 "altivec_register_operand")) (set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand") (match_dup 1))] - "TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_ - && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])" + "TARGET_VSX && TARGET_UPPER_REGS_ && !TARGET_P9_DFORM_SCALAR + && peep2_reg_dead_p (2, operands[1])" [(set (match_dup 0) (match_dup 4)) (set (match_dup 5) @@ -14025,7 +14027,7 @@ add_op0 = XEXP (addr, 0); add_op1 = XEXP (addr, 1); gcc_assert (REG_P (add_op0)); - new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg); + new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg); operands[4] = add_op1; operands[5] = change_address (mem, mode, new_addr); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8c55862..a269478 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2017-06-23 Michael Meissner + + PR target/80510 + * gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit. + * gcc.target/powerpc/pr80510-2.c: Likewise. + 2017-06-22 Jeff Law * gcc.c-torture/compile/stack-check-1.c: Require "untyped_assembly". diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c index d832e92..deb51ac 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ @@ -6,9 +6,7 @@ /* Make sure that STXSDX is generated for double scalars in Altivec registers on power7 instead of moving the value to a FPR register and doing a X-FORM - store. - - 32-bit currently does not have support for STXSDX in the mov{df,dd} patterns. */ + store. */ #ifndef TYPE #define TYPE double diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c index 83a186b..b4d2491 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ @@ -6,9 +6,7 @@ /* Make sure that STXSSPX is generated for float scalars in Altivec registers on power7 instead of moving the value to a FPR register and doing a X-FORM - store. - - 32-bit currently does not have support for STXSSPX in the mov{sf,sd} patterns. */ + store. */ #ifndef TYPE #define TYPE float -- cgit v1.1 From 8845cb377abb4e2ede6cc5c1a6bc635d71063fd2 Mon Sep 17 00:00:00 2001 From: Aaron Sawdey Date: Fri, 23 Jun 2017 19:59:42 +0000 Subject: rs6000-string.c: (expand_block_clear... 2017-06-23 Aaron Sawdey * config/rs6000/rs6000-string.c: (expand_block_clear, do_load_for_compare, select_block_compare_mode, compute_current_alignment, expand_block_compare, expand_strncmp_align_check, expand_strn_compare, expand_block_move, rs6000_output_load_multiple) Move functions related to string/block move/compare to a separate file. * config/rs6000/rs6000.c: Move above functions to rs6000-string.c. * config/rs6000/rs6000-protos.h (rs6000_emit_dot_insn): Add prototype for this function which is now used in two files. * config/rs6000/t-rs6000: Add rule to compile rs6000-string.o. * config.gcc: Add rs6000-string.o to extra_objs for targets powerpc*-*-* and rs6000*-*-*. From-SVN: r249608 --- gcc/ChangeLog | 16 + gcc/config.gcc | 2 + gcc/config/rs6000/rs6000-protos.h | 1 + gcc/config/rs6000/rs6000-string.c | 1465 +++++++++++++++++++++++++++++++++++++ gcc/config/rs6000/rs6000.c | 1433 +----------------------------------- gcc/config/rs6000/t-rs6000 | 4 + 6 files changed, 1489 insertions(+), 1432 deletions(-) create mode 100644 gcc/config/rs6000/rs6000-string.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5019018..5cb2af4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2017-06-23 Aaron Sawdey + + * config/rs6000/rs6000-string.c: (expand_block_clear, + do_load_for_compare, select_block_compare_mode, + compute_current_alignment, expand_block_compare, + expand_strncmp_align_check, expand_strn_compare, + expand_block_move, rs6000_output_load_multiple) + Move functions related to string/block move/compare + to a separate file. + * config/rs6000/rs6000.c: Move above functions to rs6000-string.c. + * config/rs6000/rs6000-protos.h (rs6000_emit_dot_insn): Add prototype + for this function which is now used in two files. + * config/rs6000/t-rs6000: Add rule to compile rs6000-string.o. + * config.gcc: Add rs6000-string.o to extra_objs for + targets powerpc*-*-* and rs6000*-*-*. + 2017-06-23 Michael Meissner PR target/80510 diff --git a/gcc/config.gcc b/gcc/config.gcc index 430779e..d5609c0 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -454,6 +454,7 @@ powerpc*-*-*spe*) ;; powerpc*-*-*) cpu_type=rs6000 + extra_objs="rs6000-string.o" extra_headers="ppc-asm.h altivec.h htmintrin.h htmxlintrin.h" extra_headers="${extra_headers} bmi2intrin.h bmiintrin.h x86intrin.h" extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h" @@ -471,6 +472,7 @@ riscv*) ;; rs6000*-*-*) extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt" + extra_objs="rs6000-string.o" ;; sparc*-*-*) cpu_type=sparc diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 8165d04..e313204 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -134,6 +134,7 @@ extern void rs6000_emit_sCOND (machine_mode, rtx[]); extern void rs6000_emit_cbranch (machine_mode, rtx[]); extern char * output_cbranch (rtx, const char *, int, rtx_insn *); extern const char * output_probe_stack_range (rtx, rtx); +extern void rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg); extern bool rs6000_emit_set_const (rtx, rtx); extern int rs6000_emit_cmove (rtx, rtx, rtx, rtx); extern int rs6000_emit_vector_cond_expr (rtx, rtx, rtx, rtx, rtx, rtx); diff --git a/gcc/config/rs6000/rs6000-string.c b/gcc/config/rs6000/rs6000-string.c new file mode 100644 index 0000000..c2fd056 --- /dev/null +++ b/gcc/config/rs6000/rs6000-string.c @@ -0,0 +1,1465 @@ +/* Subroutines used to expand string and block move, clear, + compare and other operations for PowerPC. + Copyright (C) 1991-2017 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "backend.h" +#include "rtl.h" +#include "tree.h" +#include "memmodel.h" +#include "tm_p.h" +#include "ira.h" +#include "print-tree.h" +#include "varasm.h" +#include "explow.h" +#include "expr.h" +#include "output.h" + +/* Expand a block clear operation, and return 1 if successful. Return 0 + if we should let the compiler generate normal code. + + operands[0] is the destination + operands[1] is the length + operands[3] is the alignment */ + +int +expand_block_clear (rtx operands[]) +{ + rtx orig_dest = operands[0]; + rtx bytes_rtx = operands[1]; + rtx align_rtx = operands[3]; + bool constp = (GET_CODE (bytes_rtx) == CONST_INT); + HOST_WIDE_INT align; + HOST_WIDE_INT bytes; + int offset; + int clear_bytes; + int clear_step; + + /* If this is not a fixed size move, just call memcpy */ + if (! constp) + return 0; + + /* This must be a fixed size alignment */ + gcc_assert (GET_CODE (align_rtx) == CONST_INT); + align = INTVAL (align_rtx) * BITS_PER_UNIT; + + /* Anything to clear? */ + bytes = INTVAL (bytes_rtx); + if (bytes <= 0) + return 1; + + /* Use the builtin memset after a point, to avoid huge code bloat. + When optimize_size, avoid any significant code bloat; calling + memset is about 4 instructions, so allow for one instruction to + load zero and three to do clearing. */ + if (TARGET_ALTIVEC && align >= 128) + clear_step = 16; + else if (TARGET_POWERPC64 && (align >= 64 || !STRICT_ALIGNMENT)) + clear_step = 8; + else + clear_step = 4; + + if (optimize_size && bytes > 3 * clear_step) + return 0; + if (! optimize_size && bytes > 8 * clear_step) + return 0; + + for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes) + { + machine_mode mode = BLKmode; + rtx dest; + + if (bytes >= 16 && TARGET_ALTIVEC && align >= 128) + { + clear_bytes = 16; + mode = V4SImode; + } + else if (bytes >= 8 && TARGET_POWERPC64 + && (align >= 64 || !STRICT_ALIGNMENT)) + { + clear_bytes = 8; + mode = DImode; + if (offset == 0 && align < 64) + { + rtx addr; + + /* If the address form is reg+offset with offset not a + multiple of four, reload into reg indirect form here + rather than waiting for reload. This way we get one + reload, not one per store. */ + addr = XEXP (orig_dest, 0); + if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM) + && GET_CODE (XEXP (addr, 1)) == CONST_INT + && (INTVAL (XEXP (addr, 1)) & 3) != 0) + { + addr = copy_addr_to_reg (addr); + orig_dest = replace_equiv_address (orig_dest, addr); + } + } + } + else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) + { /* move 4 bytes */ + clear_bytes = 4; + mode = SImode; + } + else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) + { /* move 2 bytes */ + clear_bytes = 2; + mode = HImode; + } + else /* move 1 byte at a time */ + { + clear_bytes = 1; + mode = QImode; + } + + dest = adjust_address (orig_dest, mode, offset); + + emit_move_insn (dest, CONST0_RTX (mode)); + } + + return 1; +} + +/* Figure out the correct instructions to generate to load data for + block compare. MODE is used for the read from memory, and + data is zero extended if REG is wider than MODE. If LE code + is being generated, bswap loads are used. + + REG is the destination register to move the data into. + MEM is the memory block being read. + MODE is the mode of memory to use for the read. */ +static void +do_load_for_compare (rtx reg, rtx mem, machine_mode mode) +{ + switch (GET_MODE (reg)) + { + case DImode: + switch (mode) + { + case QImode: + emit_insn (gen_zero_extendqidi2 (reg, mem)); + break; + case HImode: + { + rtx src = mem; + if (!BYTES_BIG_ENDIAN) + { + src = gen_reg_rtx (HImode); + emit_insn (gen_bswaphi2 (src, mem)); + } + emit_insn (gen_zero_extendhidi2 (reg, src)); + break; + } + case SImode: + { + rtx src = mem; + if (!BYTES_BIG_ENDIAN) + { + src = gen_reg_rtx (SImode); + emit_insn (gen_bswapsi2 (src, mem)); + } + emit_insn (gen_zero_extendsidi2 (reg, src)); + } + break; + case DImode: + if (!BYTES_BIG_ENDIAN) + emit_insn (gen_bswapdi2 (reg, mem)); + else + emit_insn (gen_movdi (reg, mem)); + break; + default: + gcc_unreachable (); + } + break; + + case SImode: + switch (mode) + { + case QImode: + emit_insn (gen_zero_extendqisi2 (reg, mem)); + break; + case HImode: + { + rtx src = mem; + if (!BYTES_BIG_ENDIAN) + { + src = gen_reg_rtx (HImode); + emit_insn (gen_bswaphi2 (src, mem)); + } + emit_insn (gen_zero_extendhisi2 (reg, src)); + break; + } + case SImode: + if (!BYTES_BIG_ENDIAN) + emit_insn (gen_bswapsi2 (reg, mem)); + else + emit_insn (gen_movsi (reg, mem)); + break; + case DImode: + /* DImode is larger than the destination reg so is not expected. */ + gcc_unreachable (); + break; + default: + gcc_unreachable (); + } + break; + default: + gcc_unreachable (); + break; + } +} + +/* Select the mode to be used for reading the next chunk of bytes + in the compare. + + OFFSET is the current read offset from the beginning of the block. + BYTES is the number of bytes remaining to be read. + ALIGN is the minimum alignment of the memory blocks being compared in bytes. + WORD_MODE_OK indicates using WORD_MODE is allowed, else SImode is + the largest allowable mode. */ +static machine_mode +select_block_compare_mode (unsigned HOST_WIDE_INT offset, + unsigned HOST_WIDE_INT bytes, + unsigned HOST_WIDE_INT align, bool word_mode_ok) +{ + /* First see if we can do a whole load unit + as that will be more efficient than a larger load + shift. */ + + /* If big, use biggest chunk. + If exactly chunk size, use that size. + If remainder can be done in one piece with shifting, do that. + Do largest chunk possible without violating alignment rules. */ + + /* The most we can read without potential page crossing. */ + unsigned HOST_WIDE_INT maxread = ROUND_UP (bytes, align); + + if (word_mode_ok && bytes >= UNITS_PER_WORD) + return word_mode; + else if (bytes == GET_MODE_SIZE (SImode)) + return SImode; + else if (bytes == GET_MODE_SIZE (HImode)) + return HImode; + else if (bytes == GET_MODE_SIZE (QImode)) + return QImode; + else if (bytes < GET_MODE_SIZE (SImode) + && offset >= GET_MODE_SIZE (SImode) - bytes) + /* This matches the case were we have SImode and 3 bytes + and offset >= 1 and permits us to move back one and overlap + with the previous read, thus avoiding having to shift + unwanted bytes off of the input. */ + return SImode; + else if (word_mode_ok && bytes < UNITS_PER_WORD + && offset >= UNITS_PER_WORD-bytes) + /* Similarly, if we can use DImode it will get matched here and + can do an overlapping read that ends at the end of the block. */ + return word_mode; + else if (word_mode_ok && maxread >= UNITS_PER_WORD) + /* It is safe to do all remaining in one load of largest size, + possibly with a shift to get rid of unwanted bytes. */ + return word_mode; + else if (maxread >= GET_MODE_SIZE (SImode)) + /* It is safe to do all remaining in one SImode load, + possibly with a shift to get rid of unwanted bytes. */ + return SImode; + else if (bytes > GET_MODE_SIZE (SImode)) + return SImode; + else if (bytes > GET_MODE_SIZE (HImode)) + return HImode; + + /* final fallback is do one byte */ + return QImode; +} + +/* Compute the alignment of pointer+OFFSET where the original alignment + of pointer was BASE_ALIGN. */ +static unsigned HOST_WIDE_INT +compute_current_alignment (unsigned HOST_WIDE_INT base_align, + unsigned HOST_WIDE_INT offset) +{ + if (offset == 0) + return base_align; + return MIN (base_align, offset & -offset); +} + +/* Expand a block compare operation, and return true if successful. + Return false if we should let the compiler generate normal code, + probably a memcmp call. + + OPERANDS[0] is the target (result). + OPERANDS[1] is the first source. + OPERANDS[2] is the second source. + OPERANDS[3] is the length. + OPERANDS[4] is the alignment. */ +bool +expand_block_compare (rtx operands[]) +{ + rtx target = operands[0]; + rtx orig_src1 = operands[1]; + rtx orig_src2 = operands[2]; + rtx bytes_rtx = operands[3]; + rtx align_rtx = operands[4]; + HOST_WIDE_INT cmp_bytes = 0; + rtx src1 = orig_src1; + rtx src2 = orig_src2; + + /* This case is complicated to handle because the subtract + with carry instructions do not generate the 64-bit + carry and so we must emit code to calculate it ourselves. + We choose not to implement this yet. */ + if (TARGET_32BIT && TARGET_POWERPC64) + return false; + + /* If this is not a fixed size compare, just call memcmp. */ + if (!CONST_INT_P (bytes_rtx)) + return false; + + /* This must be a fixed size alignment. */ + if (!CONST_INT_P (align_rtx)) + return false; + + unsigned int base_align = UINTVAL (align_rtx) / BITS_PER_UNIT; + + /* SLOW_UNALIGNED_ACCESS -- don't do unaligned stuff. */ + if (SLOW_UNALIGNED_ACCESS (word_mode, MEM_ALIGN (orig_src1)) + || SLOW_UNALIGNED_ACCESS (word_mode, MEM_ALIGN (orig_src2))) + return false; + + gcc_assert (GET_MODE (target) == SImode); + + /* Anything to move? */ + unsigned HOST_WIDE_INT bytes = UINTVAL (bytes_rtx); + if (bytes == 0) + return true; + + /* The code generated for p7 and older is not faster than glibc + memcmp if alignment is small and length is not short, so bail + out to avoid those conditions. */ + if (!TARGET_EFFICIENT_OVERLAPPING_UNALIGNED + && ((base_align == 1 && bytes > 16) + || (base_align == 2 && bytes > 32))) + return false; + + rtx tmp_reg_src1 = gen_reg_rtx (word_mode); + rtx tmp_reg_src2 = gen_reg_rtx (word_mode); + /* P7/P8 code uses cond for subfc. but P9 uses + it for cmpld which needs CCUNSmode. */ + rtx cond; + if (TARGET_P9_MISC) + cond = gen_reg_rtx (CCUNSmode); + else + cond = gen_reg_rtx (CCmode); + + /* If we have an LE target without ldbrx and word_mode is DImode, + then we must avoid using word_mode. */ + int word_mode_ok = !(!BYTES_BIG_ENDIAN && !TARGET_LDBRX + && word_mode == DImode); + + /* Strategy phase. How many ops will this take and should we expand it? */ + + unsigned HOST_WIDE_INT offset = 0; + machine_mode load_mode = + select_block_compare_mode (offset, bytes, base_align, word_mode_ok); + unsigned int load_mode_size = GET_MODE_SIZE (load_mode); + + /* We don't want to generate too much code. */ + unsigned HOST_WIDE_INT max_bytes = + load_mode_size * (unsigned HOST_WIDE_INT) rs6000_block_compare_inline_limit; + if (!IN_RANGE (bytes, 1, max_bytes)) + return false; + + bool generate_6432_conversion = false; + rtx convert_label = NULL; + rtx final_label = NULL; + + /* Example of generated code for 18 bytes aligned 1 byte. + Compiled with -fno-reorder-blocks for clarity. + ldbrx 10,31,8 + ldbrx 9,7,8 + subfc. 9,9,10 + bne 0,.L6487 + addi 9,12,8 + addi 5,11,8 + ldbrx 10,0,9 + ldbrx 9,0,5 + subfc. 9,9,10 + bne 0,.L6487 + addi 9,12,16 + lhbrx 10,0,9 + addi 9,11,16 + lhbrx 9,0,9 + subf 9,9,10 + b .L6488 + .p2align 4,,15 + .L6487: #convert_label + popcntd 9,9 + subfe 10,10,10 + or 9,9,10 + .L6488: #final_label + extsw 10,9 + + We start off with DImode for two blocks that jump to the DI->SI conversion + if the difference is found there, then a final block of HImode that skips + the DI->SI conversion. */ + + while (bytes > 0) + { + unsigned int align = compute_current_alignment (base_align, offset); + if (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED) + load_mode = select_block_compare_mode (offset, bytes, align, + word_mode_ok); + else + load_mode = select_block_compare_mode (0, bytes, align, word_mode_ok); + load_mode_size = GET_MODE_SIZE (load_mode); + if (bytes >= load_mode_size) + cmp_bytes = load_mode_size; + else if (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED) + { + /* Move this load back so it doesn't go past the end. + P8/P9 can do this efficiently. */ + unsigned int extra_bytes = load_mode_size - bytes; + cmp_bytes = bytes; + if (extra_bytes < offset) + { + offset -= extra_bytes; + cmp_bytes = load_mode_size; + bytes = cmp_bytes; + } + } + else + /* P7 and earlier can't do the overlapping load trick fast, + so this forces a non-overlapping load and a shift to get + rid of the extra bytes. */ + cmp_bytes = bytes; + + src1 = adjust_address (orig_src1, load_mode, offset); + src2 = adjust_address (orig_src2, load_mode, offset); + + if (!REG_P (XEXP (src1, 0))) + { + rtx src1_reg = copy_addr_to_reg (XEXP (src1, 0)); + src1 = replace_equiv_address (src1, src1_reg); + } + set_mem_size (src1, cmp_bytes); + + if (!REG_P (XEXP (src2, 0))) + { + rtx src2_reg = copy_addr_to_reg (XEXP (src2, 0)); + src2 = replace_equiv_address (src2, src2_reg); + } + set_mem_size (src2, cmp_bytes); + + do_load_for_compare (tmp_reg_src1, src1, load_mode); + do_load_for_compare (tmp_reg_src2, src2, load_mode); + + if (cmp_bytes < load_mode_size) + { + /* Shift unneeded bytes off. */ + rtx sh = GEN_INT (BITS_PER_UNIT * (load_mode_size - cmp_bytes)); + if (word_mode == DImode) + { + emit_insn (gen_lshrdi3 (tmp_reg_src1, tmp_reg_src1, sh)); + emit_insn (gen_lshrdi3 (tmp_reg_src2, tmp_reg_src2, sh)); + } + else + { + emit_insn (gen_lshrsi3 (tmp_reg_src1, tmp_reg_src1, sh)); + emit_insn (gen_lshrsi3 (tmp_reg_src2, tmp_reg_src2, sh)); + } + } + + int remain = bytes - cmp_bytes; + if (GET_MODE_SIZE (GET_MODE (target)) > GET_MODE_SIZE (load_mode)) + { + /* Target is larger than load size so we don't need to + reduce result size. */ + + /* We previously did a block that need 64->32 conversion but + the current block does not, so a label is needed to jump + to the end. */ + if (generate_6432_conversion && !final_label) + final_label = gen_label_rtx (); + + if (remain > 0) + { + /* This is not the last block, branch to the end if the result + of this subtract is not zero. */ + if (!final_label) + final_label = gen_label_rtx (); + rtx fin_ref = gen_rtx_LABEL_REF (VOIDmode, final_label); + rtx tmp = gen_rtx_MINUS (word_mode, tmp_reg_src1, tmp_reg_src2); + rtx cr = gen_reg_rtx (CCmode); + rs6000_emit_dot_insn (tmp_reg_src2, tmp, 2, cr); + emit_insn (gen_movsi (target, + gen_lowpart (SImode, tmp_reg_src2))); + rtx ne_rtx = gen_rtx_NE (VOIDmode, cr, const0_rtx); + rtx ifelse = gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx, + fin_ref, pc_rtx); + rtx j = emit_jump_insn (gen_rtx_SET (pc_rtx, ifelse)); + JUMP_LABEL (j) = final_label; + LABEL_NUSES (final_label) += 1; + } + else + { + if (word_mode == DImode) + { + emit_insn (gen_subdi3 (tmp_reg_src2, tmp_reg_src1, + tmp_reg_src2)); + emit_insn (gen_movsi (target, + gen_lowpart (SImode, tmp_reg_src2))); + } + else + emit_insn (gen_subsi3 (target, tmp_reg_src1, tmp_reg_src2)); + + if (final_label) + { + rtx fin_ref = gen_rtx_LABEL_REF (VOIDmode, final_label); + rtx j = emit_jump_insn (gen_rtx_SET (pc_rtx, fin_ref)); + JUMP_LABEL(j) = final_label; + LABEL_NUSES (final_label) += 1; + emit_barrier (); + } + } + } + else + { + /* Do we need a 64->32 conversion block? We need the 64->32 + conversion even if target size == load_mode size because + the subtract generates one extra bit. */ + generate_6432_conversion = true; + + if (remain > 0) + { + if (!convert_label) + convert_label = gen_label_rtx (); + + /* Compare to zero and branch to convert_label if not zero. */ + rtx cvt_ref = gen_rtx_LABEL_REF (VOIDmode, convert_label); + if (TARGET_P9_MISC) + { + /* Generate a compare, and convert with a setb later. */ + rtx cmp = gen_rtx_COMPARE (CCUNSmode, tmp_reg_src1, + tmp_reg_src2); + emit_insn (gen_rtx_SET (cond, cmp)); + } + else + /* Generate a subfc. and use the longer + sequence for conversion. */ + if (TARGET_64BIT) + emit_insn (gen_subfdi3_carry_dot2 (tmp_reg_src2, tmp_reg_src2, + tmp_reg_src1, cond)); + else + emit_insn (gen_subfsi3_carry_dot2 (tmp_reg_src2, tmp_reg_src2, + tmp_reg_src1, cond)); + rtx ne_rtx = gen_rtx_NE (VOIDmode, cond, const0_rtx); + rtx ifelse = gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx, + cvt_ref, pc_rtx); + rtx j = emit_jump_insn (gen_rtx_SET (pc_rtx, ifelse)); + JUMP_LABEL(j) = convert_label; + LABEL_NUSES (convert_label) += 1; + } + else + { + /* Just do the subtract/compare. Since this is the last block + the convert code will be generated immediately following. */ + if (TARGET_P9_MISC) + { + rtx cmp = gen_rtx_COMPARE (CCUNSmode, tmp_reg_src1, + tmp_reg_src2); + emit_insn (gen_rtx_SET (cond, cmp)); + } + else + if (TARGET_64BIT) + emit_insn (gen_subfdi3_carry (tmp_reg_src2, tmp_reg_src2, + tmp_reg_src1)); + else + emit_insn (gen_subfsi3_carry (tmp_reg_src2, tmp_reg_src2, + tmp_reg_src1)); + } + } + + offset += cmp_bytes; + bytes -= cmp_bytes; + } + + if (generate_6432_conversion) + { + if (convert_label) + emit_label (convert_label); + + /* We need to produce DI result from sub, then convert to target SI + while maintaining <0 / ==0 / >0 properties. This sequence works: + subfc L,A,B + subfe H,H,H + popcntd L,L + rldimi L,H,6,0 + + This is an alternate one Segher cooked up if somebody + wants to expand this for something that doesn't have popcntd: + subfc L,a,b + subfe H,x,x + addic t,L,-1 + subfe v,t,L + or z,v,H + + And finally, p9 can just do this: + cmpld A,B + setb r */ + + if (TARGET_P9_MISC) + { + emit_insn (gen_setb_unsigned (target, cond)); + } + else + { + if (TARGET_64BIT) + { + rtx tmp_reg_ca = gen_reg_rtx (DImode); + emit_insn (gen_subfdi3_carry_in_xx (tmp_reg_ca)); + emit_insn (gen_popcntddi2 (tmp_reg_src2, tmp_reg_src2)); + emit_insn (gen_iordi3 (tmp_reg_src2, tmp_reg_src2, tmp_reg_ca)); + emit_insn (gen_movsi (target, gen_lowpart (SImode, tmp_reg_src2))); + } + else + { + rtx tmp_reg_ca = gen_reg_rtx (SImode); + emit_insn (gen_subfsi3_carry_in_xx (tmp_reg_ca)); + emit_insn (gen_popcntdsi2 (tmp_reg_src2, tmp_reg_src2)); + emit_insn (gen_iorsi3 (target, tmp_reg_src2, tmp_reg_ca)); + } + } + } + + if (final_label) + emit_label (final_label); + + gcc_assert (bytes == 0); + return true; +} + +/* Generate alignment check and branch code to set up for + strncmp when we don't have DI alignment. + STRNCMP_LABEL is the label to branch if there is a page crossing. + SRC is the string pointer to be examined. + BYTES is the max number of bytes to compare. */ +static void +expand_strncmp_align_check (rtx strncmp_label, rtx src, HOST_WIDE_INT bytes) +{ + rtx lab_ref = gen_rtx_LABEL_REF (VOIDmode, strncmp_label); + rtx src_check = copy_addr_to_reg (XEXP (src, 0)); + if (GET_MODE (src_check) == SImode) + emit_insn (gen_andsi3 (src_check, src_check, GEN_INT (0xfff))); + else + emit_insn (gen_anddi3 (src_check, src_check, GEN_INT (0xfff))); + rtx cond = gen_reg_rtx (CCmode); + emit_move_insn (cond, gen_rtx_COMPARE (CCmode, src_check, + GEN_INT (4096 - bytes))); + + rtx cmp_rtx = gen_rtx_LT (VOIDmode, cond, const0_rtx); + + rtx ifelse = gen_rtx_IF_THEN_ELSE (VOIDmode, cmp_rtx, + pc_rtx, lab_ref); + rtx j = emit_jump_insn (gen_rtx_SET (pc_rtx, ifelse)); + JUMP_LABEL (j) = strncmp_label; + LABEL_NUSES (strncmp_label) += 1; +} + +/* Expand a string compare operation with length, and return + true if successful. Return false if we should let the + compiler generate normal code, probably a strncmp call. + + OPERANDS[0] is the target (result). + OPERANDS[1] is the first source. + OPERANDS[2] is the second source. + If NO_LENGTH is zero, then: + OPERANDS[3] is the length. + OPERANDS[4] is the alignment in bytes. + If NO_LENGTH is nonzero, then: + OPERANDS[3] is the alignment in bytes. */ +bool +expand_strn_compare (rtx operands[], int no_length) +{ + rtx target = operands[0]; + rtx orig_src1 = operands[1]; + rtx orig_src2 = operands[2]; + rtx bytes_rtx, align_rtx; + if (no_length) + { + bytes_rtx = NULL; + align_rtx = operands[3]; + } + else + { + bytes_rtx = operands[3]; + align_rtx = operands[4]; + } + unsigned HOST_WIDE_INT cmp_bytes = 0; + rtx src1 = orig_src1; + rtx src2 = orig_src2; + + /* If we have a length, it must be constant. This simplifies things + a bit as we don't have to generate code to check if we've exceeded + the length. Later this could be expanded to handle this case. */ + if (!no_length && !CONST_INT_P (bytes_rtx)) + return false; + + /* This must be a fixed size alignment. */ + if (!CONST_INT_P (align_rtx)) + return false; + + unsigned int base_align = UINTVAL (align_rtx); + int align1 = MEM_ALIGN (orig_src1) / BITS_PER_UNIT; + int align2 = MEM_ALIGN (orig_src2) / BITS_PER_UNIT; + + /* SLOW_UNALIGNED_ACCESS -- don't do unaligned stuff. */ + if (SLOW_UNALIGNED_ACCESS (word_mode, align1) + || SLOW_UNALIGNED_ACCESS (word_mode, align2)) + return false; + + gcc_assert (GET_MODE (target) == SImode); + + /* If we have an LE target without ldbrx and word_mode is DImode, + then we must avoid using word_mode. */ + int word_mode_ok = !(!BYTES_BIG_ENDIAN && !TARGET_LDBRX + && word_mode == DImode); + + unsigned int word_mode_size = GET_MODE_SIZE (word_mode); + + unsigned HOST_WIDE_INT offset = 0; + unsigned HOST_WIDE_INT bytes; /* N from the strncmp args if available. */ + unsigned HOST_WIDE_INT compare_length; /* How much to compare inline. */ + if (no_length) + /* Use this as a standin to determine the mode to use. */ + bytes = rs6000_string_compare_inline_limit * word_mode_size; + else + bytes = UINTVAL (bytes_rtx); + + machine_mode load_mode = + select_block_compare_mode (offset, bytes, base_align, word_mode_ok); + unsigned int load_mode_size = GET_MODE_SIZE (load_mode); + compare_length = rs6000_string_compare_inline_limit * load_mode_size; + + /* If we have equality at the end of the last compare and we have not + found the end of the string, we need to call strcmp/strncmp to + compare the remainder. */ + bool equality_compare_rest = false; + + if (no_length) + { + bytes = compare_length; + equality_compare_rest = true; + } + else + { + if (bytes <= compare_length) + compare_length = bytes; + else + equality_compare_rest = true; + } + + rtx result_reg = gen_reg_rtx (word_mode); + rtx final_move_label = gen_label_rtx (); + rtx final_label = gen_label_rtx (); + rtx begin_compare_label = NULL; + + if (base_align < 8) + { + /* Generate code that checks distance to 4k boundary for this case. */ + begin_compare_label = gen_label_rtx (); + rtx strncmp_label = gen_label_rtx (); + rtx jmp; + + /* Strncmp for power8 in glibc does this: + rldicl r8,r3,0,52 + cmpldi cr7,r8,4096-16 + bgt cr7,L(pagecross) */ + + /* Make sure that the length we use for the alignment test and + the subsequent code generation are in agreement so we do not + go past the length we tested for a 4k boundary crossing. */ + unsigned HOST_WIDE_INT align_test = compare_length; + if (align_test < 8) + { + align_test = HOST_WIDE_INT_1U << ceil_log2 (align_test); + base_align = align_test; + } + else + { + align_test = ROUND_UP (align_test, 8); + base_align = 8; + } + + if (align1 < 8) + expand_strncmp_align_check (strncmp_label, src1, align_test); + if (align2 < 8) + expand_strncmp_align_check (strncmp_label, src2, align_test); + + /* Now generate the following sequence: + - branch to begin_compare + - strncmp_label + - call to strncmp + - branch to final_label + - begin_compare_label */ + + rtx cmp_ref = gen_rtx_LABEL_REF (VOIDmode, begin_compare_label); + jmp = emit_jump_insn (gen_rtx_SET (pc_rtx, cmp_ref)); + JUMP_LABEL (jmp) = begin_compare_label; + LABEL_NUSES (begin_compare_label) += 1; + emit_barrier (); + + emit_label (strncmp_label); + + if (!REG_P (XEXP (src1, 0))) + { + rtx src1_reg = copy_addr_to_reg (XEXP (src1, 0)); + src1 = replace_equiv_address (src1, src1_reg); + } + + if (!REG_P (XEXP (src2, 0))) + { + rtx src2_reg = copy_addr_to_reg (XEXP (src2, 0)); + src2 = replace_equiv_address (src2, src2_reg); + } + + if (no_length) + { + tree fun = builtin_decl_explicit (BUILT_IN_STRCMP); + emit_library_call_value (XEXP (DECL_RTL (fun), 0), + target, LCT_NORMAL, GET_MODE (target), 2, + force_reg (Pmode, XEXP (src1, 0)), Pmode, + force_reg (Pmode, XEXP (src2, 0)), Pmode); + } + else + { + /* -m32 -mpowerpc64 results in word_mode being DImode even + though otherwise it is 32-bit. The length arg to strncmp + is a size_t which will be the same size as pointers. */ + rtx len_rtx; + if (TARGET_64BIT) + len_rtx = gen_reg_rtx (DImode); + else + len_rtx = gen_reg_rtx (SImode); + + emit_move_insn (len_rtx, bytes_rtx); + + tree fun = builtin_decl_explicit (BUILT_IN_STRNCMP); + emit_library_call_value (XEXP (DECL_RTL (fun), 0), + target, LCT_NORMAL, GET_MODE (target), 3, + force_reg (Pmode, XEXP (src1, 0)), Pmode, + force_reg (Pmode, XEXP (src2, 0)), Pmode, + len_rtx, GET_MODE (len_rtx)); + } + + rtx fin_ref = gen_rtx_LABEL_REF (VOIDmode, final_label); + jmp = emit_jump_insn (gen_rtx_SET (pc_rtx, fin_ref)); + JUMP_LABEL (jmp) = final_label; + LABEL_NUSES (final_label) += 1; + emit_barrier (); + emit_label (begin_compare_label); + } + + rtx cleanup_label = NULL; + rtx tmp_reg_src1 = gen_reg_rtx (word_mode); + rtx tmp_reg_src2 = gen_reg_rtx (word_mode); + + /* Generate sequence of ld/ldbrx, cmpb to compare out + to the length specified. */ + unsigned HOST_WIDE_INT bytes_to_compare = compare_length; + while (bytes_to_compare > 0) + { + /* Compare sequence: + check each 8B with: ld/ld cmpd bne + If equal, use rldicr/cmpb to check for zero byte. + cleanup code at end: + cmpb get byte that differs + cmpb look for zero byte + orc combine + cntlzd get bit of first zero/diff byte + subfic convert for rldcl use + rldcl rldcl extract diff/zero byte + subf subtract for final result + + The last compare can branch around the cleanup code if the + result is zero because the strings are exactly equal. */ + unsigned int align = compute_current_alignment (base_align, offset); + if (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED) + load_mode = select_block_compare_mode (offset, bytes_to_compare, align, + word_mode_ok); + else + load_mode = select_block_compare_mode (0, bytes_to_compare, align, + word_mode_ok); + load_mode_size = GET_MODE_SIZE (load_mode); + if (bytes_to_compare >= load_mode_size) + cmp_bytes = load_mode_size; + else if (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED) + { + /* Move this load back so it doesn't go past the end. + P8/P9 can do this efficiently. */ + unsigned int extra_bytes = load_mode_size - bytes_to_compare; + cmp_bytes = bytes_to_compare; + if (extra_bytes < offset) + { + offset -= extra_bytes; + cmp_bytes = load_mode_size; + bytes_to_compare = cmp_bytes; + } + } + else + /* P7 and earlier can't do the overlapping load trick fast, + so this forces a non-overlapping load and a shift to get + rid of the extra bytes. */ + cmp_bytes = bytes_to_compare; + + src1 = adjust_address (orig_src1, load_mode, offset); + src2 = adjust_address (orig_src2, load_mode, offset); + + if (!REG_P (XEXP (src1, 0))) + { + rtx src1_reg = copy_addr_to_reg (XEXP (src1, 0)); + src1 = replace_equiv_address (src1, src1_reg); + } + set_mem_size (src1, cmp_bytes); + + if (!REG_P (XEXP (src2, 0))) + { + rtx src2_reg = copy_addr_to_reg (XEXP (src2, 0)); + src2 = replace_equiv_address (src2, src2_reg); + } + set_mem_size (src2, cmp_bytes); + + do_load_for_compare (tmp_reg_src1, src1, load_mode); + do_load_for_compare (tmp_reg_src2, src2, load_mode); + + /* We must always left-align the data we read, and + clear any bytes to the right that are beyond the string. + Otherwise the cmpb sequence won't produce the correct + results. The beginning of the compare will be done + with word_mode so will not have any extra shifts or + clear rights. */ + + if (load_mode_size < word_mode_size) + { + /* Rotate left first. */ + rtx sh = GEN_INT (BITS_PER_UNIT * (word_mode_size - load_mode_size)); + if (word_mode == DImode) + { + emit_insn (gen_rotldi3 (tmp_reg_src1, tmp_reg_src1, sh)); + emit_insn (gen_rotldi3 (tmp_reg_src2, tmp_reg_src2, sh)); + } + else + { + emit_insn (gen_rotlsi3 (tmp_reg_src1, tmp_reg_src1, sh)); + emit_insn (gen_rotlsi3 (tmp_reg_src2, tmp_reg_src2, sh)); + } + } + + if (cmp_bytes < word_mode_size) + { + /* Now clear right. This plus the rotate can be + turned into a rldicr instruction. */ + HOST_WIDE_INT mb = BITS_PER_UNIT * (word_mode_size - cmp_bytes); + rtx mask = GEN_INT (HOST_WIDE_INT_M1U << mb); + if (word_mode == DImode) + { + emit_insn (gen_anddi3_mask (tmp_reg_src1, tmp_reg_src1, mask)); + emit_insn (gen_anddi3_mask (tmp_reg_src2, tmp_reg_src2, mask)); + } + else + { + emit_insn (gen_andsi3_mask (tmp_reg_src1, tmp_reg_src1, mask)); + emit_insn (gen_andsi3_mask (tmp_reg_src2, tmp_reg_src2, mask)); + } + } + + /* Cases to handle. A and B are chunks of the two strings. + 1: Not end of comparison: + A != B: branch to cleanup code to compute result. + A == B: check for 0 byte, next block if not found. + 2: End of the inline comparison: + A != B: branch to cleanup code to compute result. + A == B: check for 0 byte, call strcmp/strncmp + 3: compared requested N bytes: + A == B: branch to result 0. + A != B: cleanup code to compute result. */ + + unsigned HOST_WIDE_INT remain = bytes_to_compare - cmp_bytes; + + rtx dst_label; + if (remain > 0 || equality_compare_rest) + { + /* Branch to cleanup code, otherwise fall through to do + more compares. */ + if (!cleanup_label) + cleanup_label = gen_label_rtx (); + dst_label = cleanup_label; + } + else + /* Branch to end and produce result of 0. */ + dst_label = final_move_label; + + rtx lab_ref = gen_rtx_LABEL_REF (VOIDmode, dst_label); + rtx cond = gen_reg_rtx (CCmode); + + /* Always produce the 0 result, it is needed if + cmpb finds a 0 byte in this chunk. */ + rtx tmp = gen_rtx_MINUS (word_mode, tmp_reg_src1, tmp_reg_src2); + rs6000_emit_dot_insn (result_reg, tmp, 1, cond); + + rtx cmp_rtx; + if (remain == 0 && !equality_compare_rest) + cmp_rtx = gen_rtx_EQ (VOIDmode, cond, const0_rtx); + else + cmp_rtx = gen_rtx_NE (VOIDmode, cond, const0_rtx); + + rtx ifelse = gen_rtx_IF_THEN_ELSE (VOIDmode, cmp_rtx, + lab_ref, pc_rtx); + rtx j = emit_jump_insn (gen_rtx_SET (pc_rtx, ifelse)); + JUMP_LABEL (j) = dst_label; + LABEL_NUSES (dst_label) += 1; + + if (remain > 0 || equality_compare_rest) + { + /* Generate a cmpb to test for a 0 byte and branch + to final result if found. */ + rtx cmpb_zero = gen_reg_rtx (word_mode); + rtx lab_ref_fin = gen_rtx_LABEL_REF (VOIDmode, final_move_label); + rtx condz = gen_reg_rtx (CCmode); + rtx zero_reg = gen_reg_rtx (word_mode); + if (word_mode == SImode) + { + emit_insn (gen_movsi (zero_reg, GEN_INT (0))); + emit_insn (gen_cmpbsi3 (cmpb_zero, tmp_reg_src1, zero_reg)); + if (cmp_bytes < word_mode_size) + { + /* Don't want to look at zero bytes past end. */ + HOST_WIDE_INT mb = + BITS_PER_UNIT * (word_mode_size - cmp_bytes); + rtx mask = GEN_INT (HOST_WIDE_INT_M1U << mb); + emit_insn (gen_andsi3_mask (cmpb_zero, cmpb_zero, mask)); + } + } + else + { + emit_insn (gen_movdi (zero_reg, GEN_INT (0))); + emit_insn (gen_cmpbdi3 (cmpb_zero, tmp_reg_src1, zero_reg)); + if (cmp_bytes < word_mode_size) + { + /* Don't want to look at zero bytes past end. */ + HOST_WIDE_INT mb = + BITS_PER_UNIT * (word_mode_size - cmp_bytes); + rtx mask = GEN_INT (HOST_WIDE_INT_M1U << mb); + emit_insn (gen_anddi3_mask (cmpb_zero, cmpb_zero, mask)); + } + } + + emit_move_insn (condz, gen_rtx_COMPARE (CCmode, cmpb_zero, zero_reg)); + rtx cmpnz_rtx = gen_rtx_NE (VOIDmode, condz, const0_rtx); + rtx ifelse = gen_rtx_IF_THEN_ELSE (VOIDmode, cmpnz_rtx, + lab_ref_fin, pc_rtx); + rtx j2 = emit_jump_insn (gen_rtx_SET (pc_rtx, ifelse)); + JUMP_LABEL (j2) = final_move_label; + LABEL_NUSES (final_move_label) += 1; + + } + + offset += cmp_bytes; + bytes_to_compare -= cmp_bytes; + } + + if (equality_compare_rest) + { + /* Update pointers past what has been compared already. */ + src1 = adjust_address (orig_src1, load_mode, offset); + src2 = adjust_address (orig_src2, load_mode, offset); + + if (!REG_P (XEXP (src1, 0))) + { + rtx src1_reg = copy_addr_to_reg (XEXP (src1, 0)); + src1 = replace_equiv_address (src1, src1_reg); + } + set_mem_size (src1, cmp_bytes); + + if (!REG_P (XEXP (src2, 0))) + { + rtx src2_reg = copy_addr_to_reg (XEXP (src2, 0)); + src2 = replace_equiv_address (src2, src2_reg); + } + set_mem_size (src2, cmp_bytes); + + /* Construct call to strcmp/strncmp to compare the rest of the string. */ + if (no_length) + { + tree fun = builtin_decl_explicit (BUILT_IN_STRCMP); + emit_library_call_value (XEXP (DECL_RTL (fun), 0), + target, LCT_NORMAL, GET_MODE (target), 2, + force_reg (Pmode, XEXP (src1, 0)), Pmode, + force_reg (Pmode, XEXP (src2, 0)), Pmode); + } + else + { + rtx len_rtx; + if (TARGET_64BIT) + len_rtx = gen_reg_rtx (DImode); + else + len_rtx = gen_reg_rtx (SImode); + + emit_move_insn (len_rtx, GEN_INT (bytes - compare_length)); + tree fun = builtin_decl_explicit (BUILT_IN_STRNCMP); + emit_library_call_value (XEXP (DECL_RTL (fun), 0), + target, LCT_NORMAL, GET_MODE (target), 3, + force_reg (Pmode, XEXP (src1, 0)), Pmode, + force_reg (Pmode, XEXP (src2, 0)), Pmode, + len_rtx, GET_MODE (len_rtx)); + } + + rtx fin_ref = gen_rtx_LABEL_REF (VOIDmode, final_label); + rtx jmp = emit_jump_insn (gen_rtx_SET (pc_rtx, fin_ref)); + JUMP_LABEL (jmp) = final_label; + LABEL_NUSES (final_label) += 1; + emit_barrier (); + } + + if (cleanup_label) + emit_label (cleanup_label); + + /* Generate the final sequence that identifies the differing + byte and generates the final result, taking into account + zero bytes: + + cmpb cmpb_result1, src1, src2 + cmpb cmpb_result2, src1, zero + orc cmpb_result1, cmp_result1, cmpb_result2 + cntlzd get bit of first zero/diff byte + addi convert for rldcl use + rldcl rldcl extract diff/zero byte + subf subtract for final result + */ + + rtx cmpb_diff = gen_reg_rtx (word_mode); + rtx cmpb_zero = gen_reg_rtx (word_mode); + rtx rot_amt = gen_reg_rtx (word_mode); + rtx zero_reg = gen_reg_rtx (word_mode); + + rtx rot1_1 = gen_reg_rtx (word_mode); + rtx rot1_2 = gen_reg_rtx (word_mode); + rtx rot2_1 = gen_reg_rtx (word_mode); + rtx rot2_2 = gen_reg_rtx (word_mode); + + if (word_mode == SImode) + { + emit_insn (gen_cmpbsi3 (cmpb_diff, tmp_reg_src1, tmp_reg_src2)); + emit_insn (gen_movsi (zero_reg, GEN_INT (0))); + emit_insn (gen_cmpbsi3 (cmpb_zero, tmp_reg_src1, zero_reg)); + emit_insn (gen_one_cmplsi2 (cmpb_diff,cmpb_diff)); + emit_insn (gen_iorsi3 (cmpb_diff, cmpb_diff, cmpb_zero)); + emit_insn (gen_clzsi2 (rot_amt, cmpb_diff)); + emit_insn (gen_addsi3 (rot_amt, rot_amt, GEN_INT (8))); + emit_insn (gen_rotlsi3 (rot1_1, tmp_reg_src1, + gen_lowpart (SImode, rot_amt))); + emit_insn (gen_andsi3_mask (rot1_2, rot1_1, GEN_INT (0xff))); + emit_insn (gen_rotlsi3 (rot2_1, tmp_reg_src2, + gen_lowpart (SImode, rot_amt))); + emit_insn (gen_andsi3_mask (rot2_2, rot2_1, GEN_INT (0xff))); + emit_insn (gen_subsi3 (result_reg, rot1_2, rot2_2)); + } + else + { + emit_insn (gen_cmpbdi3 (cmpb_diff, tmp_reg_src1, tmp_reg_src2)); + emit_insn (gen_movdi (zero_reg, GEN_INT (0))); + emit_insn (gen_cmpbdi3 (cmpb_zero, tmp_reg_src1, zero_reg)); + emit_insn (gen_one_cmpldi2 (cmpb_diff,cmpb_diff)); + emit_insn (gen_iordi3 (cmpb_diff, cmpb_diff, cmpb_zero)); + emit_insn (gen_clzdi2 (rot_amt, cmpb_diff)); + emit_insn (gen_adddi3 (rot_amt, rot_amt, GEN_INT (8))); + emit_insn (gen_rotldi3 (rot1_1, tmp_reg_src1, + gen_lowpart (SImode, rot_amt))); + emit_insn (gen_anddi3_mask (rot1_2, rot1_1, GEN_INT (0xff))); + emit_insn (gen_rotldi3 (rot2_1, tmp_reg_src2, + gen_lowpart (SImode, rot_amt))); + emit_insn (gen_anddi3_mask (rot2_2, rot2_1, GEN_INT (0xff))); + emit_insn (gen_subdi3 (result_reg, rot1_2, rot2_2)); + } + + emit_label (final_move_label); + emit_insn (gen_movsi (target, + gen_lowpart (SImode, result_reg))); + emit_label (final_label); + return true; +} + +/* Expand a block move operation, and return 1 if successful. Return 0 + if we should let the compiler generate normal code. + + operands[0] is the destination + operands[1] is the source + operands[2] is the length + operands[3] is the alignment */ + +#define MAX_MOVE_REG 4 + +int +expand_block_move (rtx operands[]) +{ + rtx orig_dest = operands[0]; + rtx orig_src = operands[1]; + rtx bytes_rtx = operands[2]; + rtx align_rtx = operands[3]; + int constp = (GET_CODE (bytes_rtx) == CONST_INT); + int align; + int bytes; + int offset; + int move_bytes; + rtx stores[MAX_MOVE_REG]; + int num_reg = 0; + + /* If this is not a fixed size move, just call memcpy */ + if (! constp) + return 0; + + /* This must be a fixed size alignment */ + gcc_assert (GET_CODE (align_rtx) == CONST_INT); + align = INTVAL (align_rtx) * BITS_PER_UNIT; + + /* Anything to move? */ + bytes = INTVAL (bytes_rtx); + if (bytes <= 0) + return 1; + + if (bytes > rs6000_block_move_inline_limit) + return 0; + + for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) + { + union { + rtx (*movmemsi) (rtx, rtx, rtx, rtx); + rtx (*mov) (rtx, rtx); + } gen_func; + machine_mode mode = BLKmode; + rtx src, dest; + + /* Altivec first, since it will be faster than a string move + when it applies, and usually not significantly larger. */ + if (TARGET_ALTIVEC && bytes >= 16 && align >= 128) + { + move_bytes = 16; + mode = V4SImode; + gen_func.mov = gen_movv4si; + } + else if (TARGET_STRING + && bytes > 24 /* move up to 32 bytes at a time */ + && ! fixed_regs[5] + && ! fixed_regs[6] + && ! fixed_regs[7] + && ! fixed_regs[8] + && ! fixed_regs[9] + && ! fixed_regs[10] + && ! fixed_regs[11] + && ! fixed_regs[12]) + { + move_bytes = (bytes > 32) ? 32 : bytes; + gen_func.movmemsi = gen_movmemsi_8reg; + } + else if (TARGET_STRING + && bytes > 16 /* move up to 24 bytes at a time */ + && ! fixed_regs[5] + && ! fixed_regs[6] + && ! fixed_regs[7] + && ! fixed_regs[8] + && ! fixed_regs[9] + && ! fixed_regs[10]) + { + move_bytes = (bytes > 24) ? 24 : bytes; + gen_func.movmemsi = gen_movmemsi_6reg; + } + else if (TARGET_STRING + && bytes > 8 /* move up to 16 bytes at a time */ + && ! fixed_regs[5] + && ! fixed_regs[6] + && ! fixed_regs[7] + && ! fixed_regs[8]) + { + move_bytes = (bytes > 16) ? 16 : bytes; + gen_func.movmemsi = gen_movmemsi_4reg; + } + else if (bytes >= 8 && TARGET_POWERPC64 + && (align >= 64 || !STRICT_ALIGNMENT)) + { + move_bytes = 8; + mode = DImode; + gen_func.mov = gen_movdi; + if (offset == 0 && align < 64) + { + rtx addr; + + /* If the address form is reg+offset with offset not a + multiple of four, reload into reg indirect form here + rather than waiting for reload. This way we get one + reload, not one per load and/or store. */ + addr = XEXP (orig_dest, 0); + if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM) + && GET_CODE (XEXP (addr, 1)) == CONST_INT + && (INTVAL (XEXP (addr, 1)) & 3) != 0) + { + addr = copy_addr_to_reg (addr); + orig_dest = replace_equiv_address (orig_dest, addr); + } + addr = XEXP (orig_src, 0); + if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM) + && GET_CODE (XEXP (addr, 1)) == CONST_INT + && (INTVAL (XEXP (addr, 1)) & 3) != 0) + { + addr = copy_addr_to_reg (addr); + orig_src = replace_equiv_address (orig_src, addr); + } + } + } + else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) + { /* move up to 8 bytes at a time */ + move_bytes = (bytes > 8) ? 8 : bytes; + gen_func.movmemsi = gen_movmemsi_2reg; + } + else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) + { /* move 4 bytes */ + move_bytes = 4; + mode = SImode; + gen_func.mov = gen_movsi; + } + else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) + { /* move 2 bytes */ + move_bytes = 2; + mode = HImode; + gen_func.mov = gen_movhi; + } + else if (TARGET_STRING && bytes > 1) + { /* move up to 4 bytes at a time */ + move_bytes = (bytes > 4) ? 4 : bytes; + gen_func.movmemsi = gen_movmemsi_1reg; + } + else /* move 1 byte at a time */ + { + move_bytes = 1; + mode = QImode; + gen_func.mov = gen_movqi; + } + + src = adjust_address (orig_src, mode, offset); + dest = adjust_address (orig_dest, mode, offset); + + if (mode != BLKmode) + { + rtx tmp_reg = gen_reg_rtx (mode); + + emit_insn ((*gen_func.mov) (tmp_reg, src)); + stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); + } + + if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) + { + int i; + for (i = 0; i < num_reg; i++) + emit_insn (stores[i]); + num_reg = 0; + } + + if (mode == BLKmode) + { + /* Move the address into scratch registers. The movmemsi + patterns require zero offset. */ + if (!REG_P (XEXP (src, 0))) + { + rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); + src = replace_equiv_address (src, src_reg); + } + set_mem_size (src, move_bytes); + + if (!REG_P (XEXP (dest, 0))) + { + rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); + dest = replace_equiv_address (dest, dest_reg); + } + set_mem_size (dest, move_bytes); + + emit_insn ((*gen_func.movmemsi) (dest, src, + GEN_INT (move_bytes & 31), + align_rtx)); + } + } + + return 1; +} + + +/* Return a string to perform a load_multiple operation. + operands[0] is the vector. + operands[1] is the source address. + operands[2] is the first destination register. */ + +const char * +rs6000_output_load_multiple (rtx operands[3]) +{ + /* We have to handle the case where the pseudo used to contain the address + is assigned to one of the output registers. */ + int i, j; + int words = XVECLEN (operands[0], 0); + rtx xop[10]; + + if (XVECLEN (operands[0], 0) == 1) + return "lwz %2,0(%1)"; + + for (i = 0; i < words; i++) + if (refers_to_regno_p (REGNO (operands[2]) + i, operands[1])) + { + if (i == words-1) + { + xop[0] = GEN_INT (4 * (words-1)); + xop[1] = operands[1]; + xop[2] = operands[2]; + output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop); + return ""; + } + else if (i == 0) + { + xop[0] = GEN_INT (4 * (words-1)); + xop[1] = operands[1]; + xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); + output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop); + return ""; + } + else + { + for (j = 0; j < words; j++) + if (j != i) + { + xop[0] = GEN_INT (j * 4); + xop[1] = operands[1]; + xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); + output_asm_insn ("lwz %2,%0(%1)", xop); + } + xop[0] = GEN_INT (i * 4); + xop[1] = operands[1]; + output_asm_insn ("lwz %1,%0(%1)", xop); + return ""; + } + } + + return "lswi %2,%1,%N0"; +} + diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 7a38dea..79dccba 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -18664,113 +18664,6 @@ rs6000_init_libfuncs (void) } } - -/* Expand a block clear operation, and return 1 if successful. Return 0 - if we should let the compiler generate normal code. - - operands[0] is the destination - operands[1] is the length - operands[3] is the alignment */ - -int -expand_block_clear (rtx operands[]) -{ - rtx orig_dest = operands[0]; - rtx bytes_rtx = operands[1]; - rtx align_rtx = operands[3]; - bool constp = (GET_CODE (bytes_rtx) == CONST_INT); - HOST_WIDE_INT align; - HOST_WIDE_INT bytes; - int offset; - int clear_bytes; - int clear_step; - - /* If this is not a fixed size move, just call memcpy */ - if (! constp) - return 0; - - /* This must be a fixed size alignment */ - gcc_assert (GET_CODE (align_rtx) == CONST_INT); - align = INTVAL (align_rtx) * BITS_PER_UNIT; - - /* Anything to clear? */ - bytes = INTVAL (bytes_rtx); - if (bytes <= 0) - return 1; - - /* Use the builtin memset after a point, to avoid huge code bloat. - When optimize_size, avoid any significant code bloat; calling - memset is about 4 instructions, so allow for one instruction to - load zero and three to do clearing. */ - if (TARGET_ALTIVEC && align >= 128) - clear_step = 16; - else if (TARGET_POWERPC64 && (align >= 64 || !STRICT_ALIGNMENT)) - clear_step = 8; - else - clear_step = 4; - - if (optimize_size && bytes > 3 * clear_step) - return 0; - if (! optimize_size && bytes > 8 * clear_step) - return 0; - - for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes) - { - machine_mode mode = BLKmode; - rtx dest; - - if (bytes >= 16 && TARGET_ALTIVEC && align >= 128) - { - clear_bytes = 16; - mode = V4SImode; - } - else if (bytes >= 8 && TARGET_POWERPC64 - && (align >= 64 || !STRICT_ALIGNMENT)) - { - clear_bytes = 8; - mode = DImode; - if (offset == 0 && align < 64) - { - rtx addr; - - /* If the address form is reg+offset with offset not a - multiple of four, reload into reg indirect form here - rather than waiting for reload. This way we get one - reload, not one per store. */ - addr = XEXP (orig_dest, 0); - if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM) - && GET_CODE (XEXP (addr, 1)) == CONST_INT - && (INTVAL (XEXP (addr, 1)) & 3) != 0) - { - addr = copy_addr_to_reg (addr); - orig_dest = replace_equiv_address (orig_dest, addr); - } - } - } - else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) - { /* move 4 bytes */ - clear_bytes = 4; - mode = SImode; - } - else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) - { /* move 2 bytes */ - clear_bytes = 2; - mode = HImode; - } - else /* move 1 byte at a time */ - { - clear_bytes = 1; - mode = QImode; - } - - dest = adjust_address (orig_dest, mode, offset); - - emit_move_insn (dest, CONST0_RTX (mode)); - } - - return 1; -} - /* Emit a potentially record-form instruction, setting DST from SRC. If DOT is 0, that is all; otherwise, set CCREG to the result of the signed comparison of DST with zero. If DOT is 1, the generated RTL @@ -18778,7 +18671,7 @@ expand_block_clear (rtx operands[]) is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and a separate COMPARE. */ -static void +void rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg) { if (dot == 0) @@ -18807,1330 +18700,6 @@ rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg) } } -/* Figure out the correct instructions to generate to load data for - block compare. MODE is used for the read from memory, and - data is zero extended if REG is wider than MODE. If LE code - is being generated, bswap loads are used. - - REG is the destination register to move the data into. - MEM is the memory block being read. - MODE is the mode of memory to use for the read. */ -static void -do_load_for_compare (rtx reg, rtx mem, machine_mode mode) -{ - switch (GET_MODE (reg)) - { - case DImode: - switch (mode) - { - case QImode: - emit_insn (gen_zero_extendqidi2 (reg, mem)); - break; - case HImode: - { - rtx src = mem; - if (!BYTES_BIG_ENDIAN) - { - src = gen_reg_rtx (HImode); - emit_insn (gen_bswaphi2 (src, mem)); - } - emit_insn (gen_zero_extendhidi2 (reg, src)); - break; - } - case SImode: - { - rtx src = mem; - if (!BYTES_BIG_ENDIAN) - { - src = gen_reg_rtx (SImode); - emit_insn (gen_bswapsi2 (src, mem)); - } - emit_insn (gen_zero_extendsidi2 (reg, src)); - } - break; - case DImode: - if (!BYTES_BIG_ENDIAN) - emit_insn (gen_bswapdi2 (reg, mem)); - else - emit_insn (gen_movdi (reg, mem)); - break; - default: - gcc_unreachable (); - } - break; - - case SImode: - switch (mode) - { - case QImode: - emit_insn (gen_zero_extendqisi2 (reg, mem)); - break; - case HImode: - { - rtx src = mem; - if (!BYTES_BIG_ENDIAN) - { - src = gen_reg_rtx (HImode); - emit_insn (gen_bswaphi2 (src, mem)); - } - emit_insn (gen_zero_extendhisi2 (reg, src)); - break; - } - case SImode: - if (!BYTES_BIG_ENDIAN) - emit_insn (gen_bswapsi2 (reg, mem)); - else - emit_insn (gen_movsi (reg, mem)); - break; - case DImode: - /* DImode is larger than the destination reg so is not expected. */ - gcc_unreachable (); - break; - default: - gcc_unreachable (); - } - break; - default: - gcc_unreachable (); - break; - } -} - -/* Select the mode to be used for reading the next chunk of bytes - in the compare. - - OFFSET is the current read offset from the beginning of the block. - BYTES is the number of bytes remaining to be read. - ALIGN is the minimum alignment of the memory blocks being compared in bytes. - WORD_MODE_OK indicates using WORD_MODE is allowed, else SImode is - the largest allowable mode. */ -static machine_mode -select_block_compare_mode (unsigned HOST_WIDE_INT offset, - unsigned HOST_WIDE_INT bytes, - unsigned HOST_WIDE_INT align, bool word_mode_ok) -{ - /* First see if we can do a whole load unit - as that will be more efficient than a larger load + shift. */ - - /* If big, use biggest chunk. - If exactly chunk size, use that size. - If remainder can be done in one piece with shifting, do that. - Do largest chunk possible without violating alignment rules. */ - - /* The most we can read without potential page crossing. */ - unsigned HOST_WIDE_INT maxread = ROUND_UP (bytes, align); - - if (word_mode_ok && bytes >= UNITS_PER_WORD) - return word_mode; - else if (bytes == GET_MODE_SIZE (SImode)) - return SImode; - else if (bytes == GET_MODE_SIZE (HImode)) - return HImode; - else if (bytes == GET_MODE_SIZE (QImode)) - return QImode; - else if (bytes < GET_MODE_SIZE (SImode) - && offset >= GET_MODE_SIZE (SImode) - bytes) - /* This matches the case were we have SImode and 3 bytes - and offset >= 1 and permits us to move back one and overlap - with the previous read, thus avoiding having to shift - unwanted bytes off of the input. */ - return SImode; - else if (word_mode_ok && bytes < UNITS_PER_WORD - && offset >= UNITS_PER_WORD-bytes) - /* Similarly, if we can use DImode it will get matched here and - can do an overlapping read that ends at the end of the block. */ - return word_mode; - else if (word_mode_ok && maxread >= UNITS_PER_WORD) - /* It is safe to do all remaining in one load of largest size, - possibly with a shift to get rid of unwanted bytes. */ - return word_mode; - else if (maxread >= GET_MODE_SIZE (SImode)) - /* It is safe to do all remaining in one SImode load, - possibly with a shift to get rid of unwanted bytes. */ - return SImode; - else if (bytes > GET_MODE_SIZE (SImode)) - return SImode; - else if (bytes > GET_MODE_SIZE (HImode)) - return HImode; - - /* final fallback is do one byte */ - return QImode; -} - -/* Compute the alignment of pointer+OFFSET where the original alignment - of pointer was BASE_ALIGN. */ -static unsigned HOST_WIDE_INT -compute_current_alignment (unsigned HOST_WIDE_INT base_align, - unsigned HOST_WIDE_INT offset) -{ - if (offset == 0) - return base_align; - return min (base_align, offset & -offset); -} - -/* Expand a block compare operation, and return true if successful. - Return false if we should let the compiler generate normal code, - probably a memcmp call. - - OPERANDS[0] is the target (result). - OPERANDS[1] is the first source. - OPERANDS[2] is the second source. - OPERANDS[3] is the length. - OPERANDS[4] is the alignment. */ -bool -expand_block_compare (rtx operands[]) -{ - rtx target = operands[0]; - rtx orig_src1 = operands[1]; - rtx orig_src2 = operands[2]; - rtx bytes_rtx = operands[3]; - rtx align_rtx = operands[4]; - HOST_WIDE_INT cmp_bytes = 0; - rtx src1 = orig_src1; - rtx src2 = orig_src2; - - /* This case is complicated to handle because the subtract - with carry instructions do not generate the 64-bit - carry and so we must emit code to calculate it ourselves. - We choose not to implement this yet. */ - if (TARGET_32BIT && TARGET_POWERPC64) - return false; - - /* If this is not a fixed size compare, just call memcmp. */ - if (!CONST_INT_P (bytes_rtx)) - return false; - - /* This must be a fixed size alignment. */ - if (!CONST_INT_P (align_rtx)) - return false; - - unsigned int base_align = UINTVAL (align_rtx) / BITS_PER_UNIT; - - /* SLOW_UNALIGNED_ACCESS -- don't do unaligned stuff. */ - if (SLOW_UNALIGNED_ACCESS (word_mode, MEM_ALIGN (orig_src1)) - || SLOW_UNALIGNED_ACCESS (word_mode, MEM_ALIGN (orig_src2))) - return false; - - gcc_assert (GET_MODE (target) == SImode); - - /* Anything to move? */ - unsigned HOST_WIDE_INT bytes = UINTVAL (bytes_rtx); - if (bytes == 0) - return true; - - /* The code generated for p7 and older is not faster than glibc - memcmp if alignment is small and length is not short, so bail - out to avoid those conditions. */ - if (!TARGET_EFFICIENT_OVERLAPPING_UNALIGNED - && ((base_align == 1 && bytes > 16) - || (base_align == 2 && bytes > 32))) - return false; - - rtx tmp_reg_src1 = gen_reg_rtx (word_mode); - rtx tmp_reg_src2 = gen_reg_rtx (word_mode); - /* P7/P8 code uses cond for subfc. but P9 uses - it for cmpld which needs CCUNSmode. */ - rtx cond; - if (TARGET_P9_MISC) - cond = gen_reg_rtx (CCUNSmode); - else - cond = gen_reg_rtx (CCmode); - - /* If we have an LE target without ldbrx and word_mode is DImode, - then we must avoid using word_mode. */ - int word_mode_ok = !(!BYTES_BIG_ENDIAN && !TARGET_LDBRX - && word_mode == DImode); - - /* Strategy phase. How many ops will this take and should we expand it? */ - - unsigned HOST_WIDE_INT offset = 0; - machine_mode load_mode = - select_block_compare_mode (offset, bytes, base_align, word_mode_ok); - unsigned int load_mode_size = GET_MODE_SIZE (load_mode); - - /* We don't want to generate too much code. */ - unsigned HOST_WIDE_INT max_bytes = - load_mode_size * (unsigned HOST_WIDE_INT) rs6000_block_compare_inline_limit; - if (!IN_RANGE (bytes, 1, max_bytes)) - return false; - - bool generate_6432_conversion = false; - rtx convert_label = NULL; - rtx final_label = NULL; - - /* Example of generated code for 18 bytes aligned 1 byte. - Compiled with -fno-reorder-blocks for clarity. - ldbrx 10,31,8 - ldbrx 9,7,8 - subfc. 9,9,10 - bne 0,.L6487 - addi 9,12,8 - addi 5,11,8 - ldbrx 10,0,9 - ldbrx 9,0,5 - subfc. 9,9,10 - bne 0,.L6487 - addi 9,12,16 - lhbrx 10,0,9 - addi 9,11,16 - lhbrx 9,0,9 - subf 9,9,10 - b .L6488 - .p2align 4,,15 - .L6487: #convert_label - popcntd 9,9 - subfe 10,10,10 - or 9,9,10 - .L6488: #final_label - extsw 10,9 - - We start off with DImode for two blocks that jump to the DI->SI conversion - if the difference is found there, then a final block of HImode that skips - the DI->SI conversion. */ - - while (bytes > 0) - { - unsigned int align = compute_current_alignment (base_align, offset); - if (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED) - load_mode = select_block_compare_mode (offset, bytes, align, - word_mode_ok); - else - load_mode = select_block_compare_mode (0, bytes, align, word_mode_ok); - load_mode_size = GET_MODE_SIZE (load_mode); - if (bytes >= load_mode_size) - cmp_bytes = load_mode_size; - else if (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED) - { - /* Move this load back so it doesn't go past the end. - P8/P9 can do this efficiently. */ - unsigned int extra_bytes = load_mode_size - bytes; - cmp_bytes = bytes; - if (extra_bytes < offset) - { - offset -= extra_bytes; - cmp_bytes = load_mode_size; - bytes = cmp_bytes; - } - } - else - /* P7 and earlier can't do the overlapping load trick fast, - so this forces a non-overlapping load and a shift to get - rid of the extra bytes. */ - cmp_bytes = bytes; - - src1 = adjust_address (orig_src1, load_mode, offset); - src2 = adjust_address (orig_src2, load_mode, offset); - - if (!REG_P (XEXP (src1, 0))) - { - rtx src1_reg = copy_addr_to_reg (XEXP (src1, 0)); - src1 = replace_equiv_address (src1, src1_reg); - } - set_mem_size (src1, cmp_bytes); - - if (!REG_P (XEXP (src2, 0))) - { - rtx src2_reg = copy_addr_to_reg (XEXP (src2, 0)); - src2 = replace_equiv_address (src2, src2_reg); - } - set_mem_size (src2, cmp_bytes); - - do_load_for_compare (tmp_reg_src1, src1, load_mode); - do_load_for_compare (tmp_reg_src2, src2, load_mode); - - if (cmp_bytes < load_mode_size) - { - /* Shift unneeded bytes off. */ - rtx sh = GEN_INT (BITS_PER_UNIT * (load_mode_size - cmp_bytes)); - if (word_mode == DImode) - { - emit_insn (gen_lshrdi3 (tmp_reg_src1, tmp_reg_src1, sh)); - emit_insn (gen_lshrdi3 (tmp_reg_src2, tmp_reg_src2, sh)); - } - else - { - emit_insn (gen_lshrsi3 (tmp_reg_src1, tmp_reg_src1, sh)); - emit_insn (gen_lshrsi3 (tmp_reg_src2, tmp_reg_src2, sh)); - } - } - - int remain = bytes - cmp_bytes; - if (GET_MODE_SIZE (GET_MODE (target)) > GET_MODE_SIZE (load_mode)) - { - /* Target is larger than load size so we don't need to - reduce result size. */ - - /* We previously did a block that need 64->32 conversion but - the current block does not, so a label is needed to jump - to the end. */ - if (generate_6432_conversion && !final_label) - final_label = gen_label_rtx (); - - if (remain > 0) - { - /* This is not the last block, branch to the end if the result - of this subtract is not zero. */ - if (!final_label) - final_label = gen_label_rtx (); - rtx fin_ref = gen_rtx_LABEL_REF (VOIDmode, final_label); - rtx tmp = gen_rtx_MINUS (word_mode, tmp_reg_src1, tmp_reg_src2); - rtx cr = gen_reg_rtx (CCmode); - rs6000_emit_dot_insn (tmp_reg_src2, tmp, 2, cr); - emit_insn (gen_movsi (target, - gen_lowpart (SImode, tmp_reg_src2))); - rtx ne_rtx = gen_rtx_NE (VOIDmode, cr, const0_rtx); - rtx ifelse = gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx, - fin_ref, pc_rtx); - rtx j = emit_jump_insn (gen_rtx_SET (pc_rtx, ifelse)); - JUMP_LABEL (j) = final_label; - LABEL_NUSES (final_label) += 1; - } - else - { - if (word_mode == DImode) - { - emit_insn (gen_subdi3 (tmp_reg_src2, tmp_reg_src1, - tmp_reg_src2)); - emit_insn (gen_movsi (target, - gen_lowpart (SImode, tmp_reg_src2))); - } - else - emit_insn (gen_subsi3 (target, tmp_reg_src1, tmp_reg_src2)); - - if (final_label) - { - rtx fin_ref = gen_rtx_LABEL_REF (VOIDmode, final_label); - rtx j = emit_jump_insn (gen_rtx_SET (pc_rtx, fin_ref)); - JUMP_LABEL(j) = final_label; - LABEL_NUSES (final_label) += 1; - emit_barrier (); - } - } - } - else - { - /* Do we need a 64->32 conversion block? We need the 64->32 - conversion even if target size == load_mode size because - the subtract generates one extra bit. */ - generate_6432_conversion = true; - - if (remain > 0) - { - if (!convert_label) - convert_label = gen_label_rtx (); - - /* Compare to zero and branch to convert_label if not zero. */ - rtx cvt_ref = gen_rtx_LABEL_REF (VOIDmode, convert_label); - if (TARGET_P9_MISC) - { - /* Generate a compare, and convert with a setb later. */ - rtx cmp = gen_rtx_COMPARE (CCUNSmode, tmp_reg_src1, - tmp_reg_src2); - emit_insn (gen_rtx_SET (cond, cmp)); - } - else - /* Generate a subfc. and use the longer - sequence for conversion. */ - if (TARGET_64BIT) - emit_insn (gen_subfdi3_carry_dot2 (tmp_reg_src2, tmp_reg_src2, - tmp_reg_src1, cond)); - else - emit_insn (gen_subfsi3_carry_dot2 (tmp_reg_src2, tmp_reg_src2, - tmp_reg_src1, cond)); - rtx ne_rtx = gen_rtx_NE (VOIDmode, cond, const0_rtx); - rtx ifelse = gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx, - cvt_ref, pc_rtx); - rtx j = emit_jump_insn (gen_rtx_SET (pc_rtx, ifelse)); - JUMP_LABEL(j) = convert_label; - LABEL_NUSES (convert_label) += 1; - } - else - { - /* Just do the subtract/compare. Since this is the last block - the convert code will be generated immediately following. */ - if (TARGET_P9_MISC) - { - rtx cmp = gen_rtx_COMPARE (CCUNSmode, tmp_reg_src1, - tmp_reg_src2); - emit_insn (gen_rtx_SET (cond, cmp)); - } - else - if (TARGET_64BIT) - emit_insn (gen_subfdi3_carry (tmp_reg_src2, tmp_reg_src2, - tmp_reg_src1)); - else - emit_insn (gen_subfsi3_carry (tmp_reg_src2, tmp_reg_src2, - tmp_reg_src1)); - } - } - - offset += cmp_bytes; - bytes -= cmp_bytes; - } - - if (generate_6432_conversion) - { - if (convert_label) - emit_label (convert_label); - - /* We need to produce DI result from sub, then convert to target SI - while maintaining <0 / ==0 / >0 properties. This sequence works: - subfc L,A,B - subfe H,H,H - popcntd L,L - rldimi L,H,6,0 - - This is an alternate one Segher cooked up if somebody - wants to expand this for something that doesn't have popcntd: - subfc L,a,b - subfe H,x,x - addic t,L,-1 - subfe v,t,L - or z,v,H - - And finally, p9 can just do this: - cmpld A,B - setb r */ - - if (TARGET_P9_MISC) - { - emit_insn (gen_setb_unsigned (target, cond)); - } - else - { - if (TARGET_64BIT) - { - rtx tmp_reg_ca = gen_reg_rtx (DImode); - emit_insn (gen_subfdi3_carry_in_xx (tmp_reg_ca)); - emit_insn (gen_popcntddi2 (tmp_reg_src2, tmp_reg_src2)); - emit_insn (gen_iordi3 (tmp_reg_src2, tmp_reg_src2, tmp_reg_ca)); - emit_insn (gen_movsi (target, gen_lowpart (SImode, tmp_reg_src2))); - } - else - { - rtx tmp_reg_ca = gen_reg_rtx (SImode); - emit_insn (gen_subfsi3_carry_in_xx (tmp_reg_ca)); - emit_insn (gen_popcntdsi2 (tmp_reg_src2, tmp_reg_src2)); - emit_insn (gen_iorsi3 (target, tmp_reg_src2, tmp_reg_ca)); - } - } - } - - if (final_label) - emit_label (final_label); - - gcc_assert (bytes == 0); - return true; -} - -/* Generate alignment check and branch code to set up for - strncmp when we don't have DI alignment. - STRNCMP_LABEL is the label to branch if there is a page crossing. - SRC is the string pointer to be examined. - BYTES is the max number of bytes to compare. */ -static void -expand_strncmp_align_check (rtx strncmp_label, rtx src, HOST_WIDE_INT bytes) -{ - rtx lab_ref = gen_rtx_LABEL_REF (VOIDmode, strncmp_label); - rtx src_check = copy_addr_to_reg (XEXP (src, 0)); - if (GET_MODE (src_check) == SImode) - emit_insn (gen_andsi3 (src_check, src_check, GEN_INT (0xfff))); - else - emit_insn (gen_anddi3 (src_check, src_check, GEN_INT (0xfff))); - rtx cond = gen_reg_rtx (CCmode); - emit_move_insn (cond, gen_rtx_COMPARE (CCmode, src_check, - GEN_INT (4096 - bytes))); - - rtx cmp_rtx = gen_rtx_LT (VOIDmode, cond, const0_rtx); - - rtx ifelse = gen_rtx_IF_THEN_ELSE (VOIDmode, cmp_rtx, - pc_rtx, lab_ref); - rtx j = emit_jump_insn (gen_rtx_SET (pc_rtx, ifelse)); - JUMP_LABEL (j) = strncmp_label; - LABEL_NUSES (strncmp_label) += 1; -} - -/* Expand a string compare operation with length, and return - true if successful. Return false if we should let the - compiler generate normal code, probably a strncmp call. - - OPERANDS[0] is the target (result). - OPERANDS[1] is the first source. - OPERANDS[2] is the second source. - If NO_LENGTH is zero, then: - OPERANDS[3] is the length. - OPERANDS[4] is the alignment in bytes. - If NO_LENGTH is nonzero, then: - OPERANDS[3] is the alignment in bytes. */ -bool -expand_strn_compare (rtx operands[], int no_length) -{ - rtx target = operands[0]; - rtx orig_src1 = operands[1]; - rtx orig_src2 = operands[2]; - rtx bytes_rtx, align_rtx; - if (no_length) - { - bytes_rtx = NULL; - align_rtx = operands[3]; - } - else - { - bytes_rtx = operands[3]; - align_rtx = operands[4]; - } - unsigned HOST_WIDE_INT cmp_bytes = 0; - rtx src1 = orig_src1; - rtx src2 = orig_src2; - - /* If we have a length, it must be constant. This simplifies things - a bit as we don't have to generate code to check if we've exceeded - the length. Later this could be expanded to handle this case. */ - if (!no_length && !CONST_INT_P (bytes_rtx)) - return false; - - /* This must be a fixed size alignment. */ - if (!CONST_INT_P (align_rtx)) - return false; - - unsigned int base_align = UINTVAL (align_rtx); - int align1 = MEM_ALIGN (orig_src1) / BITS_PER_UNIT; - int align2 = MEM_ALIGN (orig_src2) / BITS_PER_UNIT; - - /* SLOW_UNALIGNED_ACCESS -- don't do unaligned stuff. */ - if (SLOW_UNALIGNED_ACCESS (word_mode, align1) - || SLOW_UNALIGNED_ACCESS (word_mode, align2)) - return false; - - gcc_assert (GET_MODE (target) == SImode); - - /* If we have an LE target without ldbrx and word_mode is DImode, - then we must avoid using word_mode. */ - int word_mode_ok = !(!BYTES_BIG_ENDIAN && !TARGET_LDBRX - && word_mode == DImode); - - unsigned int word_mode_size = GET_MODE_SIZE (word_mode); - - unsigned HOST_WIDE_INT offset = 0; - unsigned HOST_WIDE_INT bytes; /* N from the strncmp args if available. */ - unsigned HOST_WIDE_INT compare_length; /* How much to compare inline. */ - if (no_length) - /* Use this as a standin to determine the mode to use. */ - bytes = rs6000_string_compare_inline_limit * word_mode_size; - else - bytes = UINTVAL (bytes_rtx); - - machine_mode load_mode = - select_block_compare_mode (offset, bytes, base_align, word_mode_ok); - unsigned int load_mode_size = GET_MODE_SIZE (load_mode); - compare_length = rs6000_string_compare_inline_limit * load_mode_size; - - /* If we have equality at the end of the last compare and we have not - found the end of the string, we need to call strcmp/strncmp to - compare the remainder. */ - bool equality_compare_rest = false; - - if (no_length) - { - bytes = compare_length; - equality_compare_rest = true; - } - else - { - if (bytes <= compare_length) - compare_length = bytes; - else - equality_compare_rest = true; - } - - rtx result_reg = gen_reg_rtx (word_mode); - rtx final_move_label = gen_label_rtx (); - rtx final_label = gen_label_rtx (); - rtx begin_compare_label = NULL; - - if (base_align < 8) - { - /* Generate code that checks distance to 4k boundary for this case. */ - begin_compare_label = gen_label_rtx (); - rtx strncmp_label = gen_label_rtx (); - rtx jmp; - - /* Strncmp for power8 in glibc does this: - rldicl r8,r3,0,52 - cmpldi cr7,r8,4096-16 - bgt cr7,L(pagecross) */ - - /* Make sure that the length we use for the alignment test and - the subsequent code generation are in agreement so we do not - go past the length we tested for a 4k boundary crossing. */ - unsigned HOST_WIDE_INT align_test = compare_length; - if (align_test < 8) - { - align_test = HOST_WIDE_INT_1U << ceil_log2 (align_test); - base_align = align_test; - } - else - { - align_test = ROUND_UP (align_test, 8); - base_align = 8; - } - - if (align1 < 8) - expand_strncmp_align_check (strncmp_label, src1, align_test); - if (align2 < 8) - expand_strncmp_align_check (strncmp_label, src2, align_test); - - /* Now generate the following sequence: - - branch to begin_compare - - strncmp_label - - call to strncmp - - branch to final_label - - begin_compare_label */ - - rtx cmp_ref = gen_rtx_LABEL_REF (VOIDmode, begin_compare_label); - jmp = emit_jump_insn (gen_rtx_SET (pc_rtx, cmp_ref)); - JUMP_LABEL (jmp) = begin_compare_label; - LABEL_NUSES (begin_compare_label) += 1; - emit_barrier (); - - emit_label (strncmp_label); - - if (!REG_P (XEXP (src1, 0))) - { - rtx src1_reg = copy_addr_to_reg (XEXP (src1, 0)); - src1 = replace_equiv_address (src1, src1_reg); - } - - if (!REG_P (XEXP (src2, 0))) - { - rtx src2_reg = copy_addr_to_reg (XEXP (src2, 0)); - src2 = replace_equiv_address (src2, src2_reg); - } - - if (no_length) - { - tree fun = builtin_decl_explicit (BUILT_IN_STRCMP); - emit_library_call_value (XEXP (DECL_RTL (fun), 0), - target, LCT_NORMAL, GET_MODE (target), 2, - force_reg (Pmode, XEXP (src1, 0)), Pmode, - force_reg (Pmode, XEXP (src2, 0)), Pmode); - } - else - { - /* -m32 -mpowerpc64 results in word_mode being DImode even - though otherwise it is 32-bit. The length arg to strncmp - is a size_t which will be the same size as pointers. */ - rtx len_rtx; - if (TARGET_64BIT) - len_rtx = gen_reg_rtx (DImode); - else - len_rtx = gen_reg_rtx (SImode); - - emit_move_insn (len_rtx, bytes_rtx); - - tree fun = builtin_decl_explicit (BUILT_IN_STRNCMP); - emit_library_call_value (XEXP (DECL_RTL (fun), 0), - target, LCT_NORMAL, GET_MODE (target), 3, - force_reg (Pmode, XEXP (src1, 0)), Pmode, - force_reg (Pmode, XEXP (src2, 0)), Pmode, - len_rtx, GET_MODE (len_rtx)); - } - - rtx fin_ref = gen_rtx_LABEL_REF (VOIDmode, final_label); - jmp = emit_jump_insn (gen_rtx_SET (pc_rtx, fin_ref)); - JUMP_LABEL (jmp) = final_label; - LABEL_NUSES (final_label) += 1; - emit_barrier (); - emit_label (begin_compare_label); - } - - rtx cleanup_label = NULL; - rtx tmp_reg_src1 = gen_reg_rtx (word_mode); - rtx tmp_reg_src2 = gen_reg_rtx (word_mode); - - /* Generate sequence of ld/ldbrx, cmpb to compare out - to the length specified. */ - unsigned HOST_WIDE_INT bytes_to_compare = compare_length; - while (bytes_to_compare > 0) - { - /* Compare sequence: - check each 8B with: ld/ld cmpd bne - If equal, use rldicr/cmpb to check for zero byte. - cleanup code at end: - cmpb get byte that differs - cmpb look for zero byte - orc combine - cntlzd get bit of first zero/diff byte - subfic convert for rldcl use - rldcl rldcl extract diff/zero byte - subf subtract for final result - - The last compare can branch around the cleanup code if the - result is zero because the strings are exactly equal. */ - unsigned int align = compute_current_alignment (base_align, offset); - if (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED) - load_mode = select_block_compare_mode (offset, bytes_to_compare, align, - word_mode_ok); - else - load_mode = select_block_compare_mode (0, bytes_to_compare, align, - word_mode_ok); - load_mode_size = GET_MODE_SIZE (load_mode); - if (bytes_to_compare >= load_mode_size) - cmp_bytes = load_mode_size; - else if (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED) - { - /* Move this load back so it doesn't go past the end. - P8/P9 can do this efficiently. */ - unsigned int extra_bytes = load_mode_size - bytes_to_compare; - cmp_bytes = bytes_to_compare; - if (extra_bytes < offset) - { - offset -= extra_bytes; - cmp_bytes = load_mode_size; - bytes_to_compare = cmp_bytes; - } - } - else - /* P7 and earlier can't do the overlapping load trick fast, - so this forces a non-overlapping load and a shift to get - rid of the extra bytes. */ - cmp_bytes = bytes_to_compare; - - src1 = adjust_address (orig_src1, load_mode, offset); - src2 = adjust_address (orig_src2, load_mode, offset); - - if (!REG_P (XEXP (src1, 0))) - { - rtx src1_reg = copy_addr_to_reg (XEXP (src1, 0)); - src1 = replace_equiv_address (src1, src1_reg); - } - set_mem_size (src1, cmp_bytes); - - if (!REG_P (XEXP (src2, 0))) - { - rtx src2_reg = copy_addr_to_reg (XEXP (src2, 0)); - src2 = replace_equiv_address (src2, src2_reg); - } - set_mem_size (src2, cmp_bytes); - - do_load_for_compare (tmp_reg_src1, src1, load_mode); - do_load_for_compare (tmp_reg_src2, src2, load_mode); - - /* We must always left-align the data we read, and - clear any bytes to the right that are beyond the string. - Otherwise the cmpb sequence won't produce the correct - results. The beginning of the compare will be done - with word_mode so will not have any extra shifts or - clear rights. */ - - if (load_mode_size < word_mode_size) - { - /* Rotate left first. */ - rtx sh = GEN_INT (BITS_PER_UNIT * (word_mode_size - load_mode_size)); - if (word_mode == DImode) - { - emit_insn (gen_rotldi3 (tmp_reg_src1, tmp_reg_src1, sh)); - emit_insn (gen_rotldi3 (tmp_reg_src2, tmp_reg_src2, sh)); - } - else - { - emit_insn (gen_rotlsi3 (tmp_reg_src1, tmp_reg_src1, sh)); - emit_insn (gen_rotlsi3 (tmp_reg_src2, tmp_reg_src2, sh)); - } - } - - if (cmp_bytes < word_mode_size) - { - /* Now clear right. This plus the rotate can be - turned into a rldicr instruction. */ - HOST_WIDE_INT mb = BITS_PER_UNIT * (word_mode_size - cmp_bytes); - rtx mask = GEN_INT (HOST_WIDE_INT_M1U << mb); - if (word_mode == DImode) - { - emit_insn (gen_anddi3_mask (tmp_reg_src1, tmp_reg_src1, mask)); - emit_insn (gen_anddi3_mask (tmp_reg_src2, tmp_reg_src2, mask)); - } - else - { - emit_insn (gen_andsi3_mask (tmp_reg_src1, tmp_reg_src1, mask)); - emit_insn (gen_andsi3_mask (tmp_reg_src2, tmp_reg_src2, mask)); - } - } - - /* Cases to handle. A and B are chunks of the two strings. - 1: Not end of comparison: - A != B: branch to cleanup code to compute result. - A == B: check for 0 byte, next block if not found. - 2: End of the inline comparison: - A != B: branch to cleanup code to compute result. - A == B: check for 0 byte, call strcmp/strncmp - 3: compared requested N bytes: - A == B: branch to result 0. - A != B: cleanup code to compute result. */ - - unsigned HOST_WIDE_INT remain = bytes_to_compare - cmp_bytes; - - rtx dst_label; - if (remain > 0 || equality_compare_rest) - { - /* Branch to cleanup code, otherwise fall through to do - more compares. */ - if (!cleanup_label) - cleanup_label = gen_label_rtx (); - dst_label = cleanup_label; - } - else - /* Branch to end and produce result of 0. */ - dst_label = final_move_label; - - rtx lab_ref = gen_rtx_LABEL_REF (VOIDmode, dst_label); - rtx cond = gen_reg_rtx (CCmode); - - /* Always produce the 0 result, it is needed if - cmpb finds a 0 byte in this chunk. */ - rtx tmp = gen_rtx_MINUS (word_mode, tmp_reg_src1, tmp_reg_src2); - rs6000_emit_dot_insn (result_reg, tmp, 1, cond); - - rtx cmp_rtx; - if (remain == 0 && !equality_compare_rest) - cmp_rtx = gen_rtx_EQ (VOIDmode, cond, const0_rtx); - else - cmp_rtx = gen_rtx_NE (VOIDmode, cond, const0_rtx); - - rtx ifelse = gen_rtx_IF_THEN_ELSE (VOIDmode, cmp_rtx, - lab_ref, pc_rtx); - rtx j = emit_jump_insn (gen_rtx_SET (pc_rtx, ifelse)); - JUMP_LABEL (j) = dst_label; - LABEL_NUSES (dst_label) += 1; - - if (remain > 0 || equality_compare_rest) - { - /* Generate a cmpb to test for a 0 byte and branch - to final result if found. */ - rtx cmpb_zero = gen_reg_rtx (word_mode); - rtx lab_ref_fin = gen_rtx_LABEL_REF (VOIDmode, final_move_label); - rtx condz = gen_reg_rtx (CCmode); - rtx zero_reg = gen_reg_rtx (word_mode); - if (word_mode == SImode) - { - emit_insn (gen_movsi (zero_reg, GEN_INT (0))); - emit_insn (gen_cmpbsi3 (cmpb_zero, tmp_reg_src1, zero_reg)); - if (cmp_bytes < word_mode_size) - { - /* Don't want to look at zero bytes past end. */ - HOST_WIDE_INT mb = - BITS_PER_UNIT * (word_mode_size - cmp_bytes); - rtx mask = GEN_INT (HOST_WIDE_INT_M1U << mb); - emit_insn (gen_andsi3_mask (cmpb_zero, cmpb_zero, mask)); - } - } - else - { - emit_insn (gen_movdi (zero_reg, GEN_INT (0))); - emit_insn (gen_cmpbdi3 (cmpb_zero, tmp_reg_src1, zero_reg)); - if (cmp_bytes < word_mode_size) - { - /* Don't want to look at zero bytes past end. */ - HOST_WIDE_INT mb = - BITS_PER_UNIT * (word_mode_size - cmp_bytes); - rtx mask = GEN_INT (HOST_WIDE_INT_M1U << mb); - emit_insn (gen_anddi3_mask (cmpb_zero, cmpb_zero, mask)); - } - } - - emit_move_insn (condz, gen_rtx_COMPARE (CCmode, cmpb_zero, zero_reg)); - rtx cmpnz_rtx = gen_rtx_NE (VOIDmode, condz, const0_rtx); - rtx ifelse = gen_rtx_IF_THEN_ELSE (VOIDmode, cmpnz_rtx, - lab_ref_fin, pc_rtx); - rtx j2 = emit_jump_insn (gen_rtx_SET (pc_rtx, ifelse)); - JUMP_LABEL (j2) = final_move_label; - LABEL_NUSES (final_move_label) += 1; - - } - - offset += cmp_bytes; - bytes_to_compare -= cmp_bytes; - } - - if (equality_compare_rest) - { - /* Update pointers past what has been compared already. */ - src1 = adjust_address (orig_src1, load_mode, offset); - src2 = adjust_address (orig_src2, load_mode, offset); - - if (!REG_P (XEXP (src1, 0))) - { - rtx src1_reg = copy_addr_to_reg (XEXP (src1, 0)); - src1 = replace_equiv_address (src1, src1_reg); - } - set_mem_size (src1, cmp_bytes); - - if (!REG_P (XEXP (src2, 0))) - { - rtx src2_reg = copy_addr_to_reg (XEXP (src2, 0)); - src2 = replace_equiv_address (src2, src2_reg); - } - set_mem_size (src2, cmp_bytes); - - /* Construct call to strcmp/strncmp to compare the rest of the string. */ - if (no_length) - { - tree fun = builtin_decl_explicit (BUILT_IN_STRCMP); - emit_library_call_value (XEXP (DECL_RTL (fun), 0), - target, LCT_NORMAL, GET_MODE (target), 2, - force_reg (Pmode, XEXP (src1, 0)), Pmode, - force_reg (Pmode, XEXP (src2, 0)), Pmode); - } - else - { - rtx len_rtx; - if (TARGET_64BIT) - len_rtx = gen_reg_rtx (DImode); - else - len_rtx = gen_reg_rtx (SImode); - - emit_move_insn (len_rtx, GEN_INT (bytes - compare_length)); - tree fun = builtin_decl_explicit (BUILT_IN_STRNCMP); - emit_library_call_value (XEXP (DECL_RTL (fun), 0), - target, LCT_NORMAL, GET_MODE (target), 3, - force_reg (Pmode, XEXP (src1, 0)), Pmode, - force_reg (Pmode, XEXP (src2, 0)), Pmode, - len_rtx, GET_MODE (len_rtx)); - } - - rtx fin_ref = gen_rtx_LABEL_REF (VOIDmode, final_label); - rtx jmp = emit_jump_insn (gen_rtx_SET (pc_rtx, fin_ref)); - JUMP_LABEL (jmp) = final_label; - LABEL_NUSES (final_label) += 1; - emit_barrier (); - } - - if (cleanup_label) - emit_label (cleanup_label); - - /* Generate the final sequence that identifies the differing - byte and generates the final result, taking into account - zero bytes: - - cmpb cmpb_result1, src1, src2 - cmpb cmpb_result2, src1, zero - orc cmpb_result1, cmp_result1, cmpb_result2 - cntlzd get bit of first zero/diff byte - addi convert for rldcl use - rldcl rldcl extract diff/zero byte - subf subtract for final result - */ - - rtx cmpb_diff = gen_reg_rtx (word_mode); - rtx cmpb_zero = gen_reg_rtx (word_mode); - rtx rot_amt = gen_reg_rtx (word_mode); - rtx zero_reg = gen_reg_rtx (word_mode); - - rtx rot1_1 = gen_reg_rtx (word_mode); - rtx rot1_2 = gen_reg_rtx (word_mode); - rtx rot2_1 = gen_reg_rtx (word_mode); - rtx rot2_2 = gen_reg_rtx (word_mode); - - if (word_mode == SImode) - { - emit_insn (gen_cmpbsi3 (cmpb_diff, tmp_reg_src1, tmp_reg_src2)); - emit_insn (gen_movsi (zero_reg, GEN_INT (0))); - emit_insn (gen_cmpbsi3 (cmpb_zero, tmp_reg_src1, zero_reg)); - emit_insn (gen_one_cmplsi2 (cmpb_diff,cmpb_diff)); - emit_insn (gen_iorsi3 (cmpb_diff, cmpb_diff, cmpb_zero)); - emit_insn (gen_clzsi2 (rot_amt, cmpb_diff)); - emit_insn (gen_addsi3 (rot_amt, rot_amt, GEN_INT (8))); - emit_insn (gen_rotlsi3 (rot1_1, tmp_reg_src1, - gen_lowpart (SImode, rot_amt))); - emit_insn (gen_andsi3_mask (rot1_2, rot1_1, GEN_INT (0xff))); - emit_insn (gen_rotlsi3 (rot2_1, tmp_reg_src2, - gen_lowpart (SImode, rot_amt))); - emit_insn (gen_andsi3_mask (rot2_2, rot2_1, GEN_INT (0xff))); - emit_insn (gen_subsi3 (result_reg, rot1_2, rot2_2)); - } - else - { - emit_insn (gen_cmpbdi3 (cmpb_diff, tmp_reg_src1, tmp_reg_src2)); - emit_insn (gen_movdi (zero_reg, GEN_INT (0))); - emit_insn (gen_cmpbdi3 (cmpb_zero, tmp_reg_src1, zero_reg)); - emit_insn (gen_one_cmpldi2 (cmpb_diff,cmpb_diff)); - emit_insn (gen_iordi3 (cmpb_diff, cmpb_diff, cmpb_zero)); - emit_insn (gen_clzdi2 (rot_amt, cmpb_diff)); - emit_insn (gen_adddi3 (rot_amt, rot_amt, GEN_INT (8))); - emit_insn (gen_rotldi3 (rot1_1, tmp_reg_src1, - gen_lowpart (SImode, rot_amt))); - emit_insn (gen_anddi3_mask (rot1_2, rot1_1, GEN_INT (0xff))); - emit_insn (gen_rotldi3 (rot2_1, tmp_reg_src2, - gen_lowpart (SImode, rot_amt))); - emit_insn (gen_anddi3_mask (rot2_2, rot2_1, GEN_INT (0xff))); - emit_insn (gen_subdi3 (result_reg, rot1_2, rot2_2)); - } - - emit_label (final_move_label); - emit_insn (gen_movsi (target, - gen_lowpart (SImode, result_reg))); - emit_label (final_label); - return true; -} - -/* Expand a block move operation, and return 1 if successful. Return 0 - if we should let the compiler generate normal code. - - operands[0] is the destination - operands[1] is the source - operands[2] is the length - operands[3] is the alignment */ - -#define MAX_MOVE_REG 4 - -int -expand_block_move (rtx operands[]) -{ - rtx orig_dest = operands[0]; - rtx orig_src = operands[1]; - rtx bytes_rtx = operands[2]; - rtx align_rtx = operands[3]; - int constp = (GET_CODE (bytes_rtx) == CONST_INT); - int align; - int bytes; - int offset; - int move_bytes; - rtx stores[MAX_MOVE_REG]; - int num_reg = 0; - - /* If this is not a fixed size move, just call memcpy */ - if (! constp) - return 0; - - /* This must be a fixed size alignment */ - gcc_assert (GET_CODE (align_rtx) == CONST_INT); - align = INTVAL (align_rtx) * BITS_PER_UNIT; - - /* Anything to move? */ - bytes = INTVAL (bytes_rtx); - if (bytes <= 0) - return 1; - - if (bytes > rs6000_block_move_inline_limit) - return 0; - - for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) - { - union { - rtx (*movmemsi) (rtx, rtx, rtx, rtx); - rtx (*mov) (rtx, rtx); - } gen_func; - machine_mode mode = BLKmode; - rtx src, dest; - - /* Altivec first, since it will be faster than a string move - when it applies, and usually not significantly larger. */ - if (TARGET_ALTIVEC && bytes >= 16 && align >= 128) - { - move_bytes = 16; - mode = V4SImode; - gen_func.mov = gen_movv4si; - } - else if (TARGET_STRING - && bytes > 24 /* move up to 32 bytes at a time */ - && ! fixed_regs[5] - && ! fixed_regs[6] - && ! fixed_regs[7] - && ! fixed_regs[8] - && ! fixed_regs[9] - && ! fixed_regs[10] - && ! fixed_regs[11] - && ! fixed_regs[12]) - { - move_bytes = (bytes > 32) ? 32 : bytes; - gen_func.movmemsi = gen_movmemsi_8reg; - } - else if (TARGET_STRING - && bytes > 16 /* move up to 24 bytes at a time */ - && ! fixed_regs[5] - && ! fixed_regs[6] - && ! fixed_regs[7] - && ! fixed_regs[8] - && ! fixed_regs[9] - && ! fixed_regs[10]) - { - move_bytes = (bytes > 24) ? 24 : bytes; - gen_func.movmemsi = gen_movmemsi_6reg; - } - else if (TARGET_STRING - && bytes > 8 /* move up to 16 bytes at a time */ - && ! fixed_regs[5] - && ! fixed_regs[6] - && ! fixed_regs[7] - && ! fixed_regs[8]) - { - move_bytes = (bytes > 16) ? 16 : bytes; - gen_func.movmemsi = gen_movmemsi_4reg; - } - else if (bytes >= 8 && TARGET_POWERPC64 - && (align >= 64 || !STRICT_ALIGNMENT)) - { - move_bytes = 8; - mode = DImode; - gen_func.mov = gen_movdi; - if (offset == 0 && align < 64) - { - rtx addr; - - /* If the address form is reg+offset with offset not a - multiple of four, reload into reg indirect form here - rather than waiting for reload. This way we get one - reload, not one per load and/or store. */ - addr = XEXP (orig_dest, 0); - if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM) - && GET_CODE (XEXP (addr, 1)) == CONST_INT - && (INTVAL (XEXP (addr, 1)) & 3) != 0) - { - addr = copy_addr_to_reg (addr); - orig_dest = replace_equiv_address (orig_dest, addr); - } - addr = XEXP (orig_src, 0); - if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM) - && GET_CODE (XEXP (addr, 1)) == CONST_INT - && (INTVAL (XEXP (addr, 1)) & 3) != 0) - { - addr = copy_addr_to_reg (addr); - orig_src = replace_equiv_address (orig_src, addr); - } - } - } - else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64) - { /* move up to 8 bytes at a time */ - move_bytes = (bytes > 8) ? 8 : bytes; - gen_func.movmemsi = gen_movmemsi_2reg; - } - else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT)) - { /* move 4 bytes */ - move_bytes = 4; - mode = SImode; - gen_func.mov = gen_movsi; - } - else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT)) - { /* move 2 bytes */ - move_bytes = 2; - mode = HImode; - gen_func.mov = gen_movhi; - } - else if (TARGET_STRING && bytes > 1) - { /* move up to 4 bytes at a time */ - move_bytes = (bytes > 4) ? 4 : bytes; - gen_func.movmemsi = gen_movmemsi_1reg; - } - else /* move 1 byte at a time */ - { - move_bytes = 1; - mode = QImode; - gen_func.mov = gen_movqi; - } - - src = adjust_address (orig_src, mode, offset); - dest = adjust_address (orig_dest, mode, offset); - - if (mode != BLKmode) - { - rtx tmp_reg = gen_reg_rtx (mode); - - emit_insn ((*gen_func.mov) (tmp_reg, src)); - stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg); - } - - if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes) - { - int i; - for (i = 0; i < num_reg; i++) - emit_insn (stores[i]); - num_reg = 0; - } - - if (mode == BLKmode) - { - /* Move the address into scratch registers. The movmemsi - patterns require zero offset. */ - if (!REG_P (XEXP (src, 0))) - { - rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); - src = replace_equiv_address (src, src_reg); - } - set_mem_size (src, move_bytes); - - if (!REG_P (XEXP (dest, 0))) - { - rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); - dest = replace_equiv_address (dest, dest_reg); - } - set_mem_size (dest, move_bytes); - - emit_insn ((*gen_func.movmemsi) (dest, src, - GEN_INT (move_bytes & 31), - align_rtx)); - } - } - - return 1; -} - - -/* Return a string to perform a load_multiple operation. - operands[0] is the vector. - operands[1] is the source address. - operands[2] is the first destination register. */ - -const char * -rs6000_output_load_multiple (rtx operands[3]) -{ - /* We have to handle the case where the pseudo used to contain the address - is assigned to one of the output registers. */ - int i, j; - int words = XVECLEN (operands[0], 0); - rtx xop[10]; - - if (XVECLEN (operands[0], 0) == 1) - return "lwz %2,0(%1)"; - - for (i = 0; i < words; i++) - if (refers_to_regno_p (REGNO (operands[2]) + i, operands[1])) - { - if (i == words-1) - { - xop[0] = GEN_INT (4 * (words-1)); - xop[1] = operands[1]; - xop[2] = operands[2]; - output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop); - return ""; - } - else if (i == 0) - { - xop[0] = GEN_INT (4 * (words-1)); - xop[1] = operands[1]; - xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); - output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop); - return ""; - } - else - { - for (j = 0; j < words; j++) - if (j != i) - { - xop[0] = GEN_INT (j * 4); - xop[1] = operands[1]; - xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j); - output_asm_insn ("lwz %2,%0(%1)", xop); - } - xop[0] = GEN_INT (i * 4); - xop[1] = operands[1]; - output_asm_insn ("lwz %1,%0(%1)", xop); - return ""; - } - } - - return "lswi %2,%1,%N0"; -} - /* A validation routine: say whether CODE, a condition code, and MODE match. The other alternatives either don't make sense or should diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index a1dca3c..a47091a 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -26,6 +26,10 @@ rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c $(COMPILE) $< $(POSTCOMPILE) +rs6000-string.o: $(srcdir)/config/rs6000/rs6000-string.c + $(COMPILE) $< + $(POSTCOMPILE) + $(srcdir)/config/rs6000/rs6000-tables.opt: $(srcdir)/config/rs6000/genopt.sh \ $(srcdir)/config/rs6000/rs6000-cpus.def $(SHELL) $(srcdir)/config/rs6000/genopt.sh $(srcdir)/config/rs6000 > \ -- cgit v1.1 From 0f0d0eaae5e0b07dd5a08be93ba0009b1146cf76 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Fri, 23 Jun 2017 20:11:27 +0000 Subject: cmd/go: don't require GOROOT to exist for gccgo Reviewed-on: https://go-review.googlesource.com/46590 From-SVN: r249609 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index eb58bbd..e2d91ad 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -c49ba1ca392b3c23a4b3934e0a95a908b1dc2f1d +fc0cfdff94ca1099421900f43837ca5a70189cd6 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From f1857c636967baea1e29af2e3ed72de7e5be3895 Mon Sep 17 00:00:00 2001 From: Ian Lance Taylor Date: Fri, 23 Jun 2017 20:19:40 +0000 Subject: runtime: complete defer handling in CgocallBackDone When C code calls a Go function, it actually calls a function generated by cgo. That function is written in Go, and, among other things, it calls the real Go function like this: CgocallBack() defer CgocallBackDone() RealGoFunction() The deferred CgocallBackDone function enters syscall mode as we return to C. Typically the C function will then eventually return to Go. However, in the case where the C function is running on a thread created in C, it will not return to Go. For that case we will have allocated an m struct, with an associated g struct, for the duration of the Go code, and when the Go is complete we will return the m and g to a free list. That all works, but we are running in a deferred function, which means that we have been invoked by deferreturn, and deferreturn expects to do a bit of cleanup to record that the defer has been completed. Doing that cleanup while using an m and g that have already been returned to the free list is clearly a bad idea. It was kind of working because deferreturn was holding the g pointer in a local variable, but there were races with some other thread picking up and using the newly freed g. It was also kind of working because of a special check in freedefer; that check is no longer necessary. This patch changes the special case of releasing the m and g to do the defer cleanup in CgocallBackDone itself. This patch also checks for the special case of a panic through CgocallBackDone. In that special case, we don't want to release the m and g. Since we are returning to C code that was not called by Go code, we know that the panic is not going to be caught and we are going to exit the program. So for that special case we keep the m and g structs so that the rest of the panic code can use them. Reviewed-on: https://go-review.googlesource.com/46530 From-SVN: r249611 --- gcc/go/gofrontend/MERGE | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/go/gofrontend/MERGE b/gcc/go/gofrontend/MERGE index e2d91ad..416a587 100644 --- a/gcc/go/gofrontend/MERGE +++ b/gcc/go/gofrontend/MERGE @@ -1,4 +1,4 @@ -fc0cfdff94ca1099421900f43837ca5a70189cd6 +0a20181d00d43a423c55f4e772b759fba0619478 The first line of this file holds the git revision number of the last merge done from the gofrontend repository. -- cgit v1.1 From d3f062be9c9b3432e849793f57c692c23cffefcd Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Fri, 23 Jun 2017 21:01:32 +0000 Subject: Testcase for FSF GCC bug 79794. gcc/testsuite/ PR middle-end/79794 * gcc.target/aarch64/pr79794.c: New. From-SVN: r249612 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/aarch64/pr79794.c | 25 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr79794.c (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a269478..c9d75b7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-23 Jim Wilson + + PR middle-end/79794 + * gcc.target/aarch64/pr79794.c: New. + 2017-06-23 Michael Meissner PR target/80510 diff --git a/gcc/testsuite/gcc.target/aarch64/pr79794.c b/gcc/testsuite/gcc.target/aarch64/pr79794.c new file mode 100644 index 0000000..363d2db --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr79794.c @@ -0,0 +1,25 @@ +/* PR middle-end/79794 */ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-final { scan-assembler-not "umov" } } */ + +struct node_struct +{ + float _Complex gap; + unsigned long long state; +}; + +struct reg_struct +{ + int size; + struct node_struct *node; +}; + +void +func(int target, struct reg_struct *reg) +{ + int i; + + for(i=0; isize; i++) + reg->node[i].state ^= ((unsigned long long) 1 << target); +} -- cgit v1.1 From ee444c5f45985c29dcf5b4341f05a0bd15cc1897 Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Fri, 23 Jun 2017 21:40:55 +0000 Subject: Fix missing Aarch64 falkor/qdf24xx options. gcc/ * doc/invoke.texi (AArch64 Options, -mtune): Re-add falkor and qdf24xx. From-SVN: r249613 --- gcc/ChangeLog | 5 +++++ gcc/doc/invoke.texi | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5cb2af4..0e94ee6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-23 Jim Wilson + + * doc/invoke.texi (AArch64 Options, -mtune): Re-add falkor and + qdf24xx. + 2017-06-23 Aaron Sawdey * config/rs6000/rs6000-string.c: (expand_block_clear, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 7c81f0d..e4ca1b4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14079,7 +14079,8 @@ Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, -@samp{exynos-m1}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, +@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, +@samp{xgene1}, @samp{vulcan}, @samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35}, -- cgit v1.1 From e2e80f2f3c05ebc80ed0489babe527468a99e5a1 Mon Sep 17 00:00:00 2001 From: Jason Merrill Date: Fri, 23 Jun 2017 19:29:51 -0400 Subject: PR c++/79056 - C++17 ICE with invalid template syntax. * parser.c (cp_parser_simple_type_specifier): Don't assume that type is a TYPE_DECL. (cp_parser_check_for_invalid_template_id): Handle TYPE_DECL. * pt.c (template_placeholder_p): New. * cp-tree.h: Declare it. From-SVN: r249614 --- gcc/cp/ChangeLog | 9 +++++++++ gcc/cp/cp-tree.h | 1 + gcc/cp/parser.c | 6 ++++-- gcc/cp/pt.c | 8 ++++++++ gcc/testsuite/g++.dg/parse/template28.C | 10 ++++++++++ 5 files changed, 32 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.dg/parse/template28.C (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 92f478a..2d590a5 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,12 @@ +2017-06-23 Jason Merrill + + PR c++/79056 - C++17 ICE with invalid template syntax. + * parser.c (cp_parser_simple_type_specifier): Don't assume that type + is a TYPE_DECL. + (cp_parser_check_for_invalid_template_id): Handle TYPE_DECL. + * pt.c (template_placeholder_p): New. + * cp-tree.h: Declare it. + 2017-06-23 Marc Glisse * decl.c (duplicate_decls): Use builtin_structptr_types. diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 40c113b..33dde15 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -6413,6 +6413,7 @@ extern void check_template_variable (tree); extern tree make_auto (void); extern tree make_decltype_auto (void); extern tree make_template_placeholder (tree); +extern bool template_placeholder_p (tree); extern tree do_auto_deduction (tree, tree, tree); extern tree do_auto_deduction (tree, tree, tree, tsubst_flags_t, diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index ddb1cf3..97cd923 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -2983,7 +2983,9 @@ cp_parser_check_for_invalid_template_id (cp_parser* parser, if (cp_lexer_next_token_is (parser->lexer, CPP_LESS)) { - if (TYPE_P (type)) + if (TREE_CODE (type) == TYPE_DECL) + type = TREE_TYPE (type); + if (TYPE_P (type) && !template_placeholder_p (type)) error_at (location, "%qT is not a template", type); else if (identifier_p (type)) { @@ -17060,7 +17062,7 @@ cp_parser_simple_type_specifier (cp_parser* parser, /* There is no valid C++ program where a non-template type is followed by a "<". That usually indicates that the user thought that the type was a template. */ - cp_parser_check_for_invalid_template_id (parser, TREE_TYPE (type), + cp_parser_check_for_invalid_template_id (parser, type, none_type, token->location); } diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index fba7fb1..392fba0 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -24799,6 +24799,14 @@ make_template_placeholder (tree tmpl) return t; } +/* True iff T is a C++17 class template deduction placeholder. */ + +bool +template_placeholder_p (tree t) +{ + return is_auto (t) && CLASS_PLACEHOLDER_TEMPLATE (t); +} + /* Make a "constrained auto" type-specifier. This is an auto type with constraints that must be associated after deduction. The constraint is formed from the given diff --git a/gcc/testsuite/g++.dg/parse/template28.C b/gcc/testsuite/g++.dg/parse/template28.C new file mode 100644 index 0000000..6868bc8 --- /dev/null +++ b/gcc/testsuite/g++.dg/parse/template28.C @@ -0,0 +1,10 @@ +// PR c++/79056 + +template struct A {}; + +template void foo(A=A()) {} // { dg-error "" } + +void bar() +{ + foo(A()); // { dg-error "" } +} -- cgit v1.1 From ef5b7d19b688bb92178f41f504133f0ee51bffc6 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sat, 24 Jun 2017 00:16:20 +0000 Subject: Daily bump. From-SVN: r249619 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index fc6b5b6..e775f2e 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170623 +20170624 -- cgit v1.1 From e56e3fda6092548f3cd5336d131b412be986b1e6 Mon Sep 17 00:00:00 2001 From: Thomas Koenig Date: Sat, 24 Jun 2017 07:07:56 +0000 Subject: re PR fortran/52473 (CSHIFT slow - inline it?) 2017-06-24 Thomas Koenig PR fortran/52473 * Makefile.am: Add i_cshift1a_c. Add rules to generate files from cshift1a.m4. * Makefile.in: Regenerated. * m4/cshift1a.m4: New file. * m4/cshift.m4 (cshift1): Split up inner loop by removing condition. Use memcpy where possible. Call helper functions based on dtype. * libgfortran.h: Add prototypes for cshift1_16_c10, cshift1_16_c16, cshift1_16_c4, cshift1_16_c8, cshift1_16_i1, cshift1_16_i16, cshift1_16_i2, cshift1_16_i4, cshift1_16_i8, cshift1_16_r10, cshift1_16_r16, cshift1_16_r4, cshift1_16_r8, cshift1_4_c10, cshift1_4_c16, cshift1_4_c4, cshift1_4_c8, cshift1_4_i1, cshift1_4_i16, cshift1_4_i2, cshift1_4_i4, cshift1_4_i8, cshift1_4_r10, cshift1_4_r16, cshift1_4_r4, cshift1_4_r8, cshift1_8_c10, cshift1_8_c16, cshift1_8_c4, cshift1_8_c8, cshift1_8_i1, cshift1_8_i16, cshift1_8_i2, cshift1_8_i4, cshift1_8_i8, cshift1_8_r10, cshift1_8_r16, cshift1_8_r4 and cshift1_8_r8. * generated/cshift1_16_c10.c: New file, generated from cshift1a.m4. * generated/cshift1_16_c16.c: New file, generated from cshift1a.m4. * generated/cshift1_16_c4.c: New file, generated from cshift1a.m4. * generated/cshift1_16_c8.c: New file, generated from cshift1a.m4. * generated/cshift1_16_i1.c: New file, generated from cshift1a.m4. * generated/cshift1_16_i16.c: New file, generated from cshift1a.m4. * generated/cshift1_16_i2.c: New file, generated from cshift1a.m4. * generated/cshift1_16_i4.c: New file, generated from cshift1a.m4. * generated/cshift1_16_i8.c: New file, generated from cshift1a.m4. * generated/cshift1_16_r10.c: New file, generated from cshift1a.m4. * generated/cshift1_16_r16.c: New file, generated from cshift1a.m4. * generated/cshift1_16_r4.c: New file, generated from cshift1a.m4. * generated/cshift1_16_r8.c: New file, generated from cshift1a.m4. * generated/cshift1_4_c10.c: New file, generated from cshift1a.m4. * generated/cshift1_4_c16.c: New file, generated from cshift1a.m4. * generated/cshift1_4_c4.c: New file, generated from cshift1a.m4. * generated/cshift1_4_c8.c: New file, generated from cshift1a.m4. * generated/cshift1_4_i1.c: New file, generated from cshift1a.m4. * generated/cshift1_4_i16.c: New file, generated from cshift1a.m4. * generated/cshift1_4_i2.c: New file, generated from cshift1a.m4. * generated/cshift1_4_i4.c: New file, generated from cshift1a.m4. * generated/cshift1_4_i8.c: New file, generated from cshift1a.m4. * generated/cshift1_4_r10.c: New file, generated from cshift1a.m4. * generated/cshift1_4_r16.c: New file, generated from cshift1a.m4. * generated/cshift1_4_r4.c: New file, generated from cshift1a.m4. * generated/cshift1_4_r8.c: New file, generated from cshift1a.m4. * generated/cshift1_8_c10.c: New file, generated from cshift1a.m4. * generated/cshift1_8_c16.c: New file, generated from cshift1a.m4. * generated/cshift1_8_c4.c: New file, generated from cshift1a.m4. * generated/cshift1_8_c8.c: New file, generated from cshift1a.m4. * generated/cshift1_8_i1.c: New file, generated from cshift1a.m4. * generated/cshift1_8_i16.c: New file, generated from cshift1a.m4. * generated/cshift1_8_i2.c: New file, generated from cshift1a.m4. * generated/cshift1_8_i4.c: New file, generated from cshift1a.m4. * generated/cshift1_8_i8.c: New file, generated from cshift1a.m4. * generated/cshift1_8_r10.c: New file, generated from cshift1a.m4. * generated/cshift1_8_r16.c: New file, generated from cshift1a.m4. * generated/cshift1_8_r4.c: New file, generated from cshift1a.m4. * generated/cshift1_8_r8.c: New file, generated from cshift1a.m4. 2017-06-24 Thomas Koenig PR fortran/52473 * gfortran.dg/cshift_2.f90: New test. From-SVN: r249620 --- gcc/testsuite/ChangeLog | 5 ++ gcc/testsuite/gfortran.dg/cshift_2.f90 | 152 +++++++++++++++++++++++++++++++++ 2 files changed, 157 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/cshift_2.f90 (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c9d75b7..eefa2c4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-24 Thomas Koenig + + PR fortran/52473 + * gfortran.dg/cshift_2.f90: New test. + 2017-06-23 Jim Wilson PR middle-end/79794 diff --git a/gcc/testsuite/gfortran.dg/cshift_2.f90 b/gcc/testsuite/gfortran.dg/cshift_2.f90 new file mode 100644 index 0000000..66a6e2b --- /dev/null +++ b/gcc/testsuite/gfortran.dg/cshift_2.f90 @@ -0,0 +1,152 @@ +! { dg-do run } +! Test CSHIFT with array argument for shift +module rnd + implicit none +contains + subroutine fill(a,n) + integer, intent(out), dimension(:,:) :: a + integer, intent(in) :: n + real, dimension(size(a,1),size(a,2)) :: r + call random_number(r) + a = int(2*n*r-n) + end subroutine fill +end module rnd + +module csh + implicit none +contains + subroutine emul_cshift(a,sh_in,dim, c) + integer, dimension(:,:,:), intent(in) :: a + integer, dimension(:,:,:), intent(out) :: c + integer, dimension(:,:), intent(in) :: sh_in + integer, intent(in) :: dim + integer :: sh, rsh + integer :: s1, s2, s3, n, i + integer :: n1, n2, n3 + n1 = size(a,1) + n2 = size(a,2) + n3 = size(a,3) + if (dim == 1) then + n = n1 + do s2=1,n2 + do s3=1,n3 + sh = modulo(sh_in(s2,s3), n) + rsh = n - sh + do i=1,rsh + c(i,s2,s3) = a(i+sh,s2,s3) + end do + do i=rsh+1,n + c(i,s2,s3) = a(i-rsh,s2,s3) + end do + end do + end do + else if (dim == 2) then + n = n2 + do s3=1,n3 + do s1=1,n1 + sh = modulo(sh_in(s1,s3),n) + rsh = n - sh + do i=1,rsh + c(s1,i,s3) = a(s1,i+sh,s3) + end do + do i=rsh+1,n + c(s1,i,s3) = a(s1,i-rsh,s3) + end do + end do + end do + + else if (dim == 3) then + n = n3 + do s2=1,n2 + do s1=1,n1 + sh = modulo(sh_in(s1,s2),n) + rsh = n - sh + do i=1,rsh + c(s1,s2,i) = a(s1,s2,i+sh) + end do + do i=rsh+1,n + c(s1,s2,i) = a(s1,s2,i-rsh) + end do + end do + end do + else + stop "Illegal dim" + end if + end subroutine emul_cshift +end module csh +program main + use csh + use rnd + implicit none + integer, parameter :: n1=30,n2=40,n3=50 + integer, dimension(n1,n2,n3) :: a, b,c + integer :: s1, s2, s3 + integer :: dim + integer, dimension(:,:), allocatable :: sh1, sh2, sh3 + integer, dimension(:), allocatable :: sh_shift + integer :: sh, rsh + integer :: i,j,k,v + type t + integer :: i1, i2, i3 + end type t + type(t), dimension(n1,n2,n3) :: ta, tb + + v = 1 + do k=1,n3 + do j=1,n2 + do i=1,n1 + a(i,j,k) = v + v = v + 1 + end do + end do + end do + + ta%i1 = a + ta%i2 = a+a + ta%i3 = a+a+a + allocate(sh1(n2,n3)) + allocate(sh2(n1,n3)) + allocate(sh3(n1,n2)) + + call fill(sh1,10) + call fill(sh2,10) + call fill(sh3,10) + + b = cshift(a,sh1,1) + call emul_cshift(a,sh1,1,c) + if (any(b /= c)) then + print *,b + print *,c + call abort + end if + tb = cshift(ta,sh1,1) + if (any(tb%i1 /= c)) call abort + + b = cshift(a,sh2,2) + call emul_cshift(a,sh2,2,c) + if (any(b /= c)) call abort + tb = cshift(ta,sh2,2) + if (any (tb%i2 /= c*2)) call abort + + b = cshift(a,sh3,3) + call emul_cshift(a,sh3,3,c) + if (any(b /= c)) call abort + tb = cshift(ta,sh3,3) + if (any(tb%i3 /= c*3)) call abort + + b = -42 + c = -42 + b(1:n1:2,:,:) = cshift(a(1:n1/2,:,:),sh1,1) + call emul_cshift(a(1:n1/2,:,:), sh1, 1, c(1:n1:2,:,:)) + if (any(b /= c)) call abort + + tb%i1 = -42 + tb%i2 = -2*42 + tb%i3 = -3*42 + tb(1:n1:2,:,:) = cshift(ta(1:n1/2,:,:),sh1,1) + if (any(tb%i1 /= b)) call abort + if (any(tb%i2 /= 2*b)) call abort + if (any(tb%i3 /= 3*b)) call abort + +9000 format (99(3(I3,1X),2X)) +end program main -- cgit v1.1 From 22235619ba63b4a17f2b208958f467233c84bdb7 Mon Sep 17 00:00:00 2001 From: Paolo Carlini Date: Sat, 24 Jun 2017 19:31:24 +0000 Subject: re PR c++/62315 (do not print typename in diagnostic if the original code does not have it) /cp 2017-06-24 Paolo Carlini PR c++/62315 * parser.c (cp_parser_diagnose_invalid_type_name): Don't print 'typename' in error messages about missing 'typename'. /testsuite 2017-06-24 Paolo Carlini PR c++/62315 * g++.dg/parse/typedef2.C: Specify a dg-error string. From-SVN: r249626 --- gcc/cp/ChangeLog | 6 ++++++ gcc/cp/parser.c | 18 +++++++++++++++--- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/parse/typedef2.C | 3 +-- 4 files changed, 27 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 2d590a5..a06de8b 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2017-06-24 Paolo Carlini + + PR c++/62315 + * parser.c (cp_parser_diagnose_invalid_type_name): Don't print + 'typename' in error messages about missing 'typename'. + 2017-06-23 Jason Merrill PR c++/79056 - C++17 ICE with invalid template syntax. diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index 97cd923..634047e 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -3272,9 +3272,21 @@ cp_parser_diagnose_invalid_type_name (cp_parser *parser, tree id, } else if (TYPE_P (parser->scope) && dependent_scope_p (parser->scope)) - error_at (location, "need % before %<%T::%E%> because " - "%qT is a dependent scope", - parser->scope, id, parser->scope); + { + if (TREE_CODE (parser->scope) == TYPENAME_TYPE) + error_at (location, + "need % before %<%T::%D::%E%> because " + "%<%T::%D%> is a dependent scope", + TYPE_CONTEXT (parser->scope), + TYPENAME_TYPE_FULLNAME (parser->scope), + id, + TYPE_CONTEXT (parser->scope), + TYPENAME_TYPE_FULLNAME (parser->scope)); + else + error_at (location, "need % before %<%T::%E%> because " + "%qT is a dependent scope", + parser->scope, id, parser->scope); + } else if (TYPE_P (parser->scope)) { if (!COMPLETE_TYPE_P (parser->scope)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index eefa2c4..ad5ccb7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-06-24 Paolo Carlini + + PR c++/62315 + * g++.dg/parse/typedef2.C: Specify a dg-error string. + 2017-06-24 Thomas Koenig PR fortran/52473 diff --git a/gcc/testsuite/g++.dg/parse/typedef2.C b/gcc/testsuite/g++.dg/parse/typedef2.C index 3ae347d..1cc1ea0 100644 --- a/gcc/testsuite/g++.dg/parse/typedef2.C +++ b/gcc/testsuite/g++.dg/parse/typedef2.C @@ -1,3 +1,2 @@ template struct B { typedef typename T::X X; }; -template struct A { typedef B::X::Y Z; }; // { dg-error "" } - +template struct A { typedef B::X::Y Z; }; // { dg-error "before 'B::X::Y' because 'B::X'" } -- cgit v1.1 From ab3a378a6b3f356e17959ae03aaed54d3ea2d08c Mon Sep 17 00:00:00 2001 From: Jerry DeLisle Date: Sat, 24 Jun 2017 21:22:08 +0000 Subject: re PR fortran/81160 (arith.c:2009: bad statement order ?) 2017-06-24 Jerry DeLisle PR fortran/81160 * arith.c (wprecision_int_real): Set return value before mpz_clear and then return after it. From-SVN: r249627 --- gcc/fortran/ChangeLog | 6 ++++++ gcc/fortran/arith.c | 5 +++-- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 8e9e9a6..88fd0b3 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,9 @@ +2017-06-24 Jerry DeLisle + + PR fortran/81160 + * arith.c (wprecision_int_real): Set return value before + mpz_clear and then return after it. + 2017-06-15 Janus Weil PR fortran/80983 diff --git a/gcc/fortran/arith.c b/gcc/fortran/arith.c index 8fa305c..c3be14d 100644 --- a/gcc/fortran/arith.c +++ b/gcc/fortran/arith.c @@ -2001,13 +2001,14 @@ wprecision_real_real (mpfr_t r, int from_kind, int to_kind) static bool wprecision_int_real (mpz_t n, mpfr_t r) { + bool ret; mpz_t i; mpz_init (i); mpfr_get_z (i, r, GFC_RND_MODE); mpz_sub (i, i, n); - return mpz_cmp_si (i, 0) != 0; + ret = mpz_cmp_si (i, 0) != 0; mpz_clear (i); - + return ret; } /* Convert integers to integers. */ -- cgit v1.1 From 97adb48b8efd00c393a3a73e7ec904239d3ea04b Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sun, 25 Jun 2017 00:16:23 +0000 Subject: Daily bump. From-SVN: r249632 --- gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index e775f2e..31abf71 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20170624 +20170625 -- cgit v1.1