From c8742849e22d004b6ab94b3f573639f763e42e3a Mon Sep 17 00:00:00 2001 From: Martin Jambor Date: Wed, 21 Feb 2024 15:43:13 +0100 Subject: ipa: Convert lattices from pure array to vector (PR 113476) In PR 113476 we have discovered that ipcp_param_lattices is no longer a POD and should be destructed. In a follow-up discussion it transpired that their initialization done by memsetting their backing memory to zero is also invalid because now any write there before construction can be considered dead. Plus that having them in an array is a little bit old-school and does not get the extra checking offered by vector along with automatic construction and destruction when necessary. So this patch converts the array to a vector. That however means that ipcp_param_lattices cannot be just a forward declared type but must be known to all code that deals with ipa_node_params and thus to all code that includes ipa-prop.h. Therefore I have moved ipcp_param_lattices and the type it depends on to a new header ipa-cp.h which now ipa-prop.h depends on. Because we have the (IMHO not a very wise) rule that headers don't include what they need themselves, I had to add inclusions of ipa-cp.h and sreal.h (on which it depends) to very many files, which made the patch rather ugly. gcc/lto/ChangeLog: 2024-02-16 Martin Jambor PR ipa/113476 * lto-common.cc: Include sreal.h and ipa-cp.h. * lto-partition.cc: Include ipa-cp.h, move inclusion of sreal higher. * lto.cc: Include sreal.h and ipa-cp.h. gcc/ChangeLog: 2024-02-16 Martin Jambor PR ipa/113476 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust initializers in the contructor. (ipa_node_params::~ipa_node_params): Release lattices as a vector. * ipa-cp.h: New file. * ipa-cp.cc: Include sreal.h and ipa-cp.h. (ipcp_value_source): Move to ipa-cp.h. (ipcp_value_base): Likewise. (ipcp_value): Likewise. (ipcp_lattice): Likewise. (ipcp_agg_lattice): Likewise. (ipcp_bits_lattice): Likewise. (ipcp_vr_lattice): Likewise. (ipcp_param_lattices): Likewise. (ipa_get_parm_lattices): Remove assert latticess is non-NULL. (ipa_value_from_jfunc): Adjust a check for empty lattices. (ipa_context_from_jfunc): Likewise. (ipa_agg_value_from_jfunc): Likewise. (merge_agg_lats_step): Do not memset new aggregate lattices to zero. (ipcp_propagate_stage): Allocate lattices in a vector as opposed to just in contiguous memory. (ipcp_store_vr_results): Adjust a check for empty lattices. * auto-profile.cc: Include sreal.h and ipa-cp.h. * cgraph.cc: Likewise. * cgraphclones.cc: Likewise. * cgraphunit.cc: Likewise. * config/aarch64/aarch64.cc: Likewise. * config/i386/i386-builtins.cc: Likewise. * config/i386/i386-expand.cc: Likewise. * config/i386/i386-features.cc: Likewise. * config/i386/i386-options.cc: Likewise. * config/i386/i386.cc: Likewise. * config/rs6000/rs6000.cc: Likewise. * config/s390/s390.cc: Likewise. * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the files to be included in gtype-desc.cc. * gimple-range-fold.cc: Include sreal.h and ipa-cp.h. * ipa-devirt.cc: Likewise. * ipa-fnsummary.cc: Likewise. * ipa-icf.cc: Likewise. * ipa-inline-analysis.cc: Likewise. * ipa-inline-transform.cc: Likewise. * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher. * ipa-modref.cc: Include sreal.h and ipa-cp.h. * ipa-param-manipulation.cc: Likewise. * ipa-predicate.cc: Likewise. * ipa-profile.cc: Likewise. * ipa-prop.cc: Likewise. (ipa_node_params_t::duplicate): Assert new lattices remain empty instead of setting them to NULL. * ipa-pure-const.cc: Include sreal.h and ipa-cp.h. * ipa-split.cc: Likewise. * ipa-sra.cc: Likewise. * ipa-strub.cc: Likewise. * ipa-utils.cc: Likewise. * ipa.cc: Likewise. * toplev.cc: Likewise. * tree-ssa-ccp.cc: Likewise. * tree-ssa-sccvn.cc: Likewise. * tree-vrp.cc: Likewise. --- gcc/auto-profile.cc | 2 + gcc/cgraph.cc | 2 + gcc/cgraphclones.cc | 2 + gcc/cgraphunit.cc | 2 + gcc/config/aarch64/aarch64.cc | 2 + gcc/config/i386/i386-builtins.cc | 2 + gcc/config/i386/i386-expand.cc | 2 + gcc/config/i386/i386-features.cc | 2 + gcc/config/i386/i386-options.cc | 2 + gcc/config/i386/i386.cc | 2 + gcc/config/rs6000/rs6000.cc | 2 + gcc/config/s390/s390.cc | 2 + gcc/gengtype.cc | 6 +- gcc/gimple-range-fold.cc | 2 + gcc/ipa-cp.cc | 283 +------------------------------------ gcc/ipa-cp.h | 292 +++++++++++++++++++++++++++++++++++++++ gcc/ipa-devirt.cc | 2 + gcc/ipa-fnsummary.cc | 2 + gcc/ipa-icf.cc | 2 + gcc/ipa-inline-analysis.cc | 2 + gcc/ipa-inline-transform.cc | 2 + gcc/ipa-inline.cc | 3 +- gcc/ipa-modref.cc | 2 + gcc/ipa-param-manipulation.cc | 2 + gcc/ipa-predicate.cc | 2 + gcc/ipa-profile.cc | 2 + gcc/ipa-prop.cc | 4 +- gcc/ipa-prop.h | 6 +- gcc/ipa-pure-const.cc | 2 + gcc/ipa-split.cc | 2 + gcc/ipa-sra.cc | 2 + gcc/ipa-strub.cc | 2 + gcc/ipa-utils.cc | 2 + gcc/ipa.cc | 2 + gcc/lto/lto-common.cc | 2 + gcc/lto/lto-partition.cc | 3 +- gcc/lto/lto.cc | 2 + gcc/toplev.cc | 2 + gcc/tree-ssa-ccp.cc | 2 + gcc/tree-ssa-sccvn.cc | 2 + gcc/tree-vrp.cc | 2 + 41 files changed, 380 insertions(+), 285 deletions(-) create mode 100644 gcc/ipa-cp.h (limited to 'gcc') diff --git a/gcc/auto-profile.cc b/gcc/auto-profile.cc index 63d0c3d..e5407d3 100644 --- a/gcc/auto-profile.cc +++ b/gcc/auto-profile.cc @@ -42,6 +42,8 @@ along with GCC; see the file COPYING3. If not see #include "gimple-iterator.h" #include "value-prof.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "ipa-inline.h" diff --git a/gcc/cgraph.cc b/gcc/cgraph.cc index 0ac8f73..473d841 100644 --- a/gcc/cgraph.cc +++ b/gcc/cgraph.cc @@ -51,6 +51,8 @@ along with GCC; see the file COPYING3. If not see #include "ipa-utils.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "cfgloop.h" diff --git a/gcc/cgraphclones.cc b/gcc/cgraphclones.cc index 6d7bc40..4fff687 100644 --- a/gcc/cgraphclones.cc +++ b/gcc/cgraphclones.cc @@ -84,6 +84,8 @@ along with GCC; see the file COPYING3. If not see #include "alloc-pool.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "symtab-thunks.h" diff --git a/gcc/cgraphunit.cc b/gcc/cgraphunit.cc index 5c40525..d200166 100644 --- a/gcc/cgraphunit.cc +++ b/gcc/cgraphunit.cc @@ -191,6 +191,8 @@ along with GCC; see the file COPYING3. If not see #include "debug.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "gimple-pretty-print.h" #include "plugin.h" diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 28d1555..16318bf 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -91,6 +91,8 @@ #include "tree-pass.h" #include "cfgbuild.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "hash-map.h" diff --git a/gcc/config/i386/i386-builtins.cc b/gcc/config/i386/i386-builtins.cc index d5b83e9..8b79d33 100644 --- a/gcc/config/i386/i386-builtins.cc +++ b/gcc/config/i386/i386-builtins.cc @@ -82,6 +82,8 @@ along with GCC; see the file COPYING3. If not see #include "intl.h" #include "ifcvt.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "wide-int-bitmask.h" diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 50f9fe2..a4d3369 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -82,6 +82,8 @@ along with GCC; see the file COPYING3. If not see #include "intl.h" #include "ifcvt.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "wide-int-bitmask.h" diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc index f1b1cf2..d3b9ae8 100644 --- a/gcc/config/i386/i386-features.cc +++ b/gcc/config/i386/i386-features.cc @@ -82,6 +82,8 @@ along with GCC; see the file COPYING3. If not see #include "intl.h" #include "ifcvt.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "wide-int-bitmask.h" diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 8f5ce81..93a0114 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -82,6 +82,8 @@ along with GCC; see the file COPYING3. If not see #include "intl.h" #include "ifcvt.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "wide-int-bitmask.h" diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 46f2386..4fdab34 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -86,6 +86,8 @@ along with GCC; see the file COPYING3. If not see #include "intl.h" #include "ifcvt.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "wide-int-bitmask.h" diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 5d975da..a2a679d 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -72,6 +72,8 @@ #include "context.h" #include "tree-pass.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "except.h" diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc index f182c26..c857b20 100644 --- a/gcc/config/s390/s390.cc +++ b/gcc/config/s390/s390.cc @@ -83,6 +83,8 @@ along with GCC; see the file COPYING3. If not see #include "tm-constrs.h" #include "tree-vrp.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "sched-int.h" diff --git a/gcc/gengtype.cc b/gcc/gengtype.cc index 87f8090..c0ecbe8 100644 --- a/gcc/gengtype.cc +++ b/gcc/gengtype.cc @@ -1715,9 +1715,9 @@ open_base_files (void) "tree-dfa.h", "tree-ssa.h", "reload.h", "cpplib.h", "tree-chrec.h", "except.h", "output.h", "cfgloop.h", "target.h", "lto-streamer.h", "target-globals.h", "ipa-ref.h", "cgraph.h", "symbol-summary.h", - "ipa-prop.h", "ipa-fnsummary.h", "dwarf2out.h", "omp-general.h", - "omp-offload.h", "ipa-modref-tree.h", "ipa-modref.h", "symtab-thunks.h", - "symtab-clones.h", "diagnostic-spec.h", "ctfc.h", + "sreal.h", "ipa-cp.h", "ipa-prop.h", "ipa-fnsummary.h", "dwarf2out.h", + "omp-general.h", "omp-offload.h", "ipa-modref-tree.h", "ipa-modref.h", + "symtab-thunks.h", "symtab-clones.h", "diagnostic-spec.h", "ctfc.h", NULL }; const char *const *ifp; diff --git a/gcc/gimple-range-fold.cc b/gcc/gimple-range-fold.cc index 0cc5319..9c4ad1e 100644 --- a/gcc/gimple-range-fold.cc +++ b/gcc/gimple-range-fold.cc @@ -48,6 +48,8 @@ along with GCC; see the file COPYING3. If not see #include "alloc-pool.h" #include "symbol-summary.h" #include "ipa-utils.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" // Construct a fur_source, and set the m_query field. diff --git a/gcc/ipa-cp.cc b/gcc/ipa-cp.cc index e85477d..2a1da63 100644 --- a/gcc/ipa-cp.cc +++ b/gcc/ipa-cp.cc @@ -109,6 +109,7 @@ along with GCC; see the file COPYING3. If not see #include "gimple-expr.h" #include "gimple.h" #include "predict.h" +#include "sreal.h" #include "alloc-pool.h" #include "tree-pass.h" #include "cgraph.h" @@ -118,6 +119,7 @@ along with GCC; see the file COPYING3. If not see #include "gimple-fold.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "tree-pretty-print.h" #include "tree-inline.h" @@ -130,274 +132,6 @@ along with GCC; see the file COPYING3. If not see #include "symtab-clones.h" #include "gimple-range.h" -template class ipcp_value; - -/* Describes a particular source for an IPA-CP value. */ - -template -struct ipcp_value_source -{ -public: - /* Aggregate offset of the source, negative if the source is scalar value of - the argument itself. */ - HOST_WIDE_INT offset; - /* The incoming edge that brought the value. */ - cgraph_edge *cs; - /* If the jump function that resulted into his value was a pass-through or an - ancestor, this is the ipcp_value of the caller from which the described - value has been derived. Otherwise it is NULL. */ - ipcp_value *val; - /* Next pointer in a linked list of sources of a value. */ - ipcp_value_source *next; - /* If the jump function that resulted into his value was a pass-through or an - ancestor, this is the index of the parameter of the caller the jump - function references. */ - int index; -}; - -/* Common ancestor for all ipcp_value instantiations. */ - -class ipcp_value_base -{ -public: - /* Time benefit and that specializing the function for this value would bring - about in this function alone. */ - sreal local_time_benefit; - /* Time benefit that specializing the function for this value can bring about - in it's callees. */ - sreal prop_time_benefit; - /* Size cost that specializing the function for this value would bring about - in this function alone. */ - int local_size_cost; - /* Size cost that specializing the function for this value can bring about in - it's callees. */ - int prop_size_cost; - - ipcp_value_base () - : local_time_benefit (0), prop_time_benefit (0), - local_size_cost (0), prop_size_cost (0) {} -}; - -/* Describes one particular value stored in struct ipcp_lattice. */ - -template -class ipcp_value : public ipcp_value_base -{ -public: - /* The actual value for the given parameter. */ - valtype value; - /* The list of sources from which this value originates. */ - ipcp_value_source *sources = nullptr; - /* Next pointers in a linked list of all values in a lattice. */ - ipcp_value *next = nullptr; - /* Next pointers in a linked list of values in a strongly connected component - of values. */ - ipcp_value *scc_next = nullptr; - /* Next pointers in a linked list of SCCs of values sorted topologically - according their sources. */ - ipcp_value *topo_next = nullptr; - /* A specialized node created for this value, NULL if none has been (so far) - created. */ - cgraph_node *spec_node = nullptr; - /* Depth first search number and low link for topological sorting of - values. */ - int dfs = 0; - int low_link = 0; - /* SCC number to identify values which recursively feed into each other. - Values in the same SCC have the same SCC number. */ - int scc_no = 0; - /* Non zero if the value is generated from another value in the same lattice - for a self-recursive call, the actual number is how many times the - operation has been performed. In the unlikely event of the value being - present in two chains fo self-recursive value generation chains, it is the - maximum. */ - unsigned self_recursion_generated_level = 0; - /* True if this value is currently on the topo-sort stack. */ - bool on_stack = false; - - void add_source (cgraph_edge *cs, ipcp_value *src_val, int src_idx, - HOST_WIDE_INT offset); - - /* Return true if both THIS value and O feed into each other. */ - - bool same_scc (const ipcp_value *o) - { - return o->scc_no == scc_no; - } - -/* Return true, if a this value has been generated for a self-recursive call as - a result of an arithmetic pass-through jump-function acting on a value in - the same lattice function. */ - - bool self_recursion_generated_p () - { - return self_recursion_generated_level > 0; - } -}; - -/* Lattice describing potential values of a formal parameter of a function, or - a part of an aggregate. TOP is represented by a lattice with zero values - and with contains_variable and bottom flags cleared. BOTTOM is represented - by a lattice with the bottom flag set. In that case, values and - contains_variable flag should be disregarded. */ - -template -struct ipcp_lattice -{ -public: - /* The list of known values and types in this lattice. Note that values are - not deallocated if a lattice is set to bottom because there may be value - sources referencing them. */ - ipcp_value *values; - /* Number of known values and types in this lattice. */ - int values_count; - /* The lattice contains a variable component (in addition to values). */ - bool contains_variable; - /* The value of the lattice is bottom (i.e. variable and unusable for any - propagation). */ - bool bottom; - - inline bool is_single_const (); - inline bool set_to_bottom (); - inline bool set_contains_variable (); - bool add_value (valtype newval, cgraph_edge *cs, - ipcp_value *src_val = NULL, - int src_idx = 0, HOST_WIDE_INT offset = -1, - ipcp_value **val_p = NULL, - unsigned same_lat_gen_level = 0); - void print (FILE * f, bool dump_sources, bool dump_benefits); -}; - -/* Lattice of tree values with an offset to describe a part of an - aggregate. */ - -struct ipcp_agg_lattice : public ipcp_lattice -{ -public: - /* Offset that is being described by this lattice. */ - HOST_WIDE_INT offset; - /* Size so that we don't have to re-compute it every time we traverse the - list. Must correspond to TYPE_SIZE of all lat values. */ - HOST_WIDE_INT size; - /* Next element of the linked list. */ - struct ipcp_agg_lattice *next; -}; - -/* Lattice of known bits, only capable of holding one value. - Bitwise constant propagation propagates which bits of a - value are constant. - For eg: - int f(int x) - { - return some_op (x); - } - - int f1(int y) - { - if (cond) - return f (y & 0xff); - else - return f (y & 0xf); - } - - In the above case, the param 'x' will always have all - the bits (except the bits in lsb) set to 0. - Hence the mask of 'x' would be 0xff. The mask - reflects that the bits in lsb are unknown. - The actual propagated value is given by m_value & ~m_mask. */ - -class ipcp_bits_lattice -{ -public: - bool bottom_p () const { return m_lattice_val == IPA_BITS_VARYING; } - bool top_p () const { return m_lattice_val == IPA_BITS_UNDEFINED; } - bool constant_p () const { return m_lattice_val == IPA_BITS_CONSTANT; } - bool set_to_bottom (); - bool set_to_constant (widest_int, widest_int); - bool known_nonzero_p () const; - - widest_int get_value () const { return m_value; } - widest_int get_mask () const { return m_mask; } - - bool meet_with (ipcp_bits_lattice& other, unsigned, signop, - enum tree_code, tree, bool); - - bool meet_with (widest_int, widest_int, unsigned); - - void print (FILE *); - -private: - enum { IPA_BITS_UNDEFINED, IPA_BITS_CONSTANT, IPA_BITS_VARYING } m_lattice_val; - - /* Similar to ccp_lattice_t, mask represents which bits of value are constant. - If a bit in mask is set to 0, then the corresponding bit in - value is known to be constant. */ - widest_int m_value, m_mask; - - bool meet_with_1 (widest_int, widest_int, unsigned, bool); - void get_value_and_mask (tree, widest_int *, widest_int *); -}; - -/* Lattice of value ranges. */ - -class ipcp_vr_lattice -{ -public: - Value_Range m_vr; - - inline bool bottom_p () const; - inline bool top_p () const; - inline bool set_to_bottom (); - bool meet_with (const vrange &p_vr); - bool meet_with (const ipcp_vr_lattice &other); - void init (tree type); - void print (FILE * f); - -private: - bool meet_with_1 (const vrange &other_vr); -}; - -inline void -ipcp_vr_lattice::init (tree type) -{ - if (type) - m_vr.set_type (type); - - // Otherwise m_vr will default to unsupported_range. -} - -/* Structure containing lattices for a parameter itself and for pieces of - aggregates that are passed in the parameter or by a reference in a parameter - plus some other useful flags. */ - -class ipcp_param_lattices -{ -public: - /* Lattice describing the value of the parameter itself. */ - ipcp_lattice itself; - /* Lattice describing the polymorphic contexts of a parameter. */ - ipcp_lattice ctxlat; - /* Lattices describing aggregate parts. */ - ipcp_agg_lattice *aggs; - /* Lattice describing known bits. */ - ipcp_bits_lattice bits_lattice; - /* Lattice describing value range. */ - ipcp_vr_lattice m_value_range; - /* Number of aggregate lattices */ - int aggs_count; - /* True if aggregate data were passed by reference (as opposed to by - value). */ - bool aggs_by_ref; - /* All aggregate lattices contain a variable component (in addition to - values). */ - bool aggs_contain_variable; - /* The value of all aggregate lattices is bottom (i.e. variable and unusable - for any propagation). */ - bool aggs_bottom; - - /* There is a virtual call based on this parameter. */ - bool virt_call; -}; /* Allocation pools for values and their sources in ipa-cp. */ @@ -431,7 +165,6 @@ ipa_get_parm_lattices (class ipa_node_params *info, int i) { gcc_assert (i >= 0 && i < ipa_get_param_count (info)); gcc_checking_assert (!info->ipcp_orig_node); - gcc_checking_assert (info->lattices); return &(info->lattices[i]); } @@ -1821,7 +1554,7 @@ ipa_value_from_jfunc (class ipa_node_params *info, struct ipa_jump_func *jfunc, { ipcp_lattice *lat; - if (!info->lattices + if (info->lattices.is_empty () || idx >= ipa_get_param_count (info)) return NULL_TREE; lat = ipa_get_scalar_lat (info, idx); @@ -1884,7 +1617,7 @@ ipa_context_from_jfunc (ipa_node_params *info, cgraph_edge *cs, int csidx, } else { - if (!info->lattices + if (info->lattices.is_empty () || srcidx >= ipa_get_param_count (info)) return ctx; ipcp_lattice *lat; @@ -2056,7 +1789,7 @@ ipa_agg_value_from_jfunc (ipa_node_params *info, cgraph_node *node, item->value.load_agg.by_ref); } } - else if (info->lattices) + else if (!info->lattices.is_empty ()) { class ipcp_param_lattices *src_plats = ipa_get_parm_lattices (info, src_idx); @@ -2937,7 +2670,6 @@ merge_agg_lats_step (class ipcp_param_lattices *dest_plats, return false; dest_plats->aggs_count++; new_al = ipcp_agg_lattice_pool.allocate (); - memset (new_al, 0, sizeof (*new_al)); new_al->offset = offset; new_al->size = val_size; @@ -4295,8 +4027,7 @@ ipcp_propagate_stage (class ipa_topo_info *topo) determine_versionability (node, info); unsigned nlattices = ipa_get_param_count (info); - void *chunk = XCNEWVEC (class ipcp_param_lattices, nlattices); - info->lattices = new (chunk) ipcp_param_lattices[nlattices]; + info->lattices.safe_grow_cleared (nlattices, true); initialize_node_lattices (node); } ipa_size_summary *s = ipa_size_summaries->get (node); @@ -6568,7 +6299,7 @@ ipcp_store_vr_results (void) if (info->ipcp_orig_node) info = ipa_node_params_sum->get (info->ipcp_orig_node); - if (!info->lattices) + if (info->lattices.is_empty ()) /* Newly expanded artificial thunks do not have lattices. */ continue; diff --git a/gcc/ipa-cp.h b/gcc/ipa-cp.h new file mode 100644 index 0000000..0b3cfe4 --- /dev/null +++ b/gcc/ipa-cp.h @@ -0,0 +1,292 @@ +/* Interprocedural constant propagation + Copyright (C) 2024 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#ifndef IPA_CP_H +#define IPA_CP_H + +template class ipcp_value; + +/* Describes a particular source for an IPA-CP value. */ + +template +struct ipcp_value_source +{ +public: + /* Aggregate offset of the source, negative if the source is scalar value of + the argument itself. */ + HOST_WIDE_INT offset; + /* The incoming edge that brought the value. */ + cgraph_edge *cs; + /* If the jump function that resulted into his value was a pass-through or an + ancestor, this is the ipcp_value of the caller from which the described + value has been derived. Otherwise it is NULL. */ + ipcp_value *val; + /* Next pointer in a linked list of sources of a value. */ + ipcp_value_source *next; + /* If the jump function that resulted into his value was a pass-through or an + ancestor, this is the index of the parameter of the caller the jump + function references. */ + int index; +}; + +/* Common ancestor for all ipcp_value instantiations. */ + +class ipcp_value_base +{ +public: + /* Time benefit and that specializing the function for this value would bring + about in this function alone. */ + sreal local_time_benefit = 0; + /* Time benefit that specializing the function for this value can bring about + in it's callees. */ + sreal prop_time_benefit = 0; + /* Size cost that specializing the function for this value would bring about + in this function alone. */ + int local_size_cost = 0; + /* Size cost that specializing the function for this value can bring about in + it's callees. */ + int prop_size_cost = 0; +}; + +/* Describes one particular value stored in struct ipcp_lattice. */ + +template +class ipcp_value : public ipcp_value_base +{ +public: + /* The actual value for the given parameter. */ + valtype value; + /* The list of sources from which this value originates. */ + ipcp_value_source *sources = nullptr; + /* Next pointers in a linked list of all values in a lattice. */ + ipcp_value *next = nullptr; + /* Next pointers in a linked list of values in a strongly connected component + of values. */ + ipcp_value *scc_next = nullptr; + /* Next pointers in a linked list of SCCs of values sorted topologically + according their sources. */ + ipcp_value *topo_next = nullptr; + /* A specialized node created for this value, NULL if none has been (so far) + created. */ + cgraph_node *spec_node = nullptr; + /* Depth first search number and low link for topological sorting of + values. */ + int dfs = 0; + int low_link = 0; + /* SCC number to identify values which recursively feed into each other. + Values in the same SCC have the same SCC number. */ + int scc_no = 0; + /* Non zero if the value is generated from another value in the same lattice + for a self-recursive call, the actual number is how many times the + operation has been performed. In the unlikely event of the value being + present in two chains fo self-recursive value generation chains, it is the + maximum. */ + unsigned self_recursion_generated_level = 0; + /* True if this value is currently on the topo-sort stack. */ + bool on_stack = false; + + void add_source (cgraph_edge *cs, ipcp_value *src_val, int src_idx, + HOST_WIDE_INT offset); + + /* Return true if both THIS value and O feed into each other. */ + + bool same_scc (const ipcp_value *o) + { + return o->scc_no == scc_no; + } + +/* Return true, if a this value has been generated for a self-recursive call as + a result of an arithmetic pass-through jump-function acting on a value in + the same lattice function. */ + + bool self_recursion_generated_p () + { + return self_recursion_generated_level > 0; + } +}; + +/* Lattice describing potential values of a formal parameter of a function, or + a part of an aggregate. TOP is represented by a lattice with zero values + and with contains_variable and bottom flags cleared. BOTTOM is represented + by a lattice with the bottom flag set. In that case, values and + contains_variable flag should be disregarded. */ + +template +struct ipcp_lattice +{ +public: + /* The list of known values and types in this lattice. Note that values are + not deallocated if a lattice is set to bottom because there may be value + sources referencing them. */ + ipcp_value *values = nullptr; + /* Number of known values and types in this lattice. */ + int values_count = 0; + /* The lattice contains a variable component (in addition to values). */ + bool contains_variable = false; + /* The value of the lattice is bottom (i.e. variable and unusable for any + propagation). */ + bool bottom = false; + + inline bool is_single_const (); + inline bool set_to_bottom (); + inline bool set_contains_variable (); + bool add_value (valtype newval, cgraph_edge *cs, + ipcp_value *src_val = NULL, + int src_idx = 0, HOST_WIDE_INT offset = -1, + ipcp_value **val_p = NULL, + unsigned same_lat_gen_level = 0); + void print (FILE * f, bool dump_sources, bool dump_benefits); +}; + +/* Lattice of tree values with an offset to describe a part of an + aggregate. */ + +struct ipcp_agg_lattice : public ipcp_lattice +{ +public: + /* Offset that is being described by this lattice. */ + HOST_WIDE_INT offset = 0; + /* Size so that we don't have to re-compute it every time we traverse the + list. Must correspond to TYPE_SIZE of all lat values. */ + HOST_WIDE_INT size = 0; + /* Next element of the linked list. */ + struct ipcp_agg_lattice *next = nullptr; +}; + +/* Lattice of known bits, only capable of holding one value. + Bitwise constant propagation propagates which bits of a + value are constant. + For eg: + int f(int x) + { + return some_op (x); + } + + int f1(int y) + { + if (cond) + return f (y & 0xff); + else + return f (y & 0xf); + } + + In the above case, the param 'x' will always have all + the bits (except the bits in lsb) set to 0. + Hence the mask of 'x' would be 0xff. The mask + reflects that the bits in lsb are unknown. + The actual propagated value is given by m_value & ~m_mask. */ + +class ipcp_bits_lattice +{ +public: + bool bottom_p () const { return m_lattice_val == IPA_BITS_VARYING; } + bool top_p () const { return m_lattice_val == IPA_BITS_UNDEFINED; } + bool constant_p () const { return m_lattice_val == IPA_BITS_CONSTANT; } + bool set_to_bottom (); + bool set_to_constant (widest_int, widest_int); + bool known_nonzero_p () const; + + widest_int get_value () const { return m_value; } + widest_int get_mask () const { return m_mask; } + + bool meet_with (ipcp_bits_lattice& other, unsigned, signop, + enum tree_code, tree, bool); + + bool meet_with (widest_int, widest_int, unsigned); + + void print (FILE *); + +private: + enum { IPA_BITS_UNDEFINED, IPA_BITS_CONSTANT, IPA_BITS_VARYING } + m_lattice_val = IPA_BITS_UNDEFINED; + + /* Similar to ccp_lattice_t, mask represents which bits of value are constant. + If a bit in mask is set to 0, then the corresponding bit in + value is known to be constant. */ + widest_int m_value, m_mask; + + bool meet_with_1 (widest_int, widest_int, unsigned, bool); + void get_value_and_mask (tree, widest_int *, widest_int *); +}; + +/* Lattice of value ranges. */ + +class ipcp_vr_lattice +{ +public: + Value_Range m_vr; + + inline bool bottom_p () const; + inline bool top_p () const; + inline bool set_to_bottom (); + bool meet_with (const vrange &p_vr); + bool meet_with (const ipcp_vr_lattice &other); + void init (tree type); + void print (FILE * f); + +private: + bool meet_with_1 (const vrange &other_vr); +}; + +inline void +ipcp_vr_lattice::init (tree type) +{ + if (type) + m_vr.set_type (type); + + // Otherwise m_vr will default to unsupported_range. +} + +/* Structure containing lattices for a parameter itself and for pieces of + aggregates that are passed in the parameter or by a reference in a parameter + plus some other useful flags. + + Even after construction, m_value_range parts still need to be initialized + with the type they represent with the init method. */ + +class ipcp_param_lattices +{ +public: + /* Lattice describing the value of the parameter itself. */ + ipcp_lattice itself; + /* Lattice describing the polymorphic contexts of a parameter. */ + ipcp_lattice ctxlat; + /* Lattices describing aggregate parts. */ + ipcp_agg_lattice *aggs = nullptr; + /* Lattice describing known bits. */ + ipcp_bits_lattice bits_lattice; + /* Lattice describing value range. */ + ipcp_vr_lattice m_value_range; + /* Number of aggregate lattices */ + int aggs_count = 0; + /* True if aggregate data were passed by reference (as opposed to by + value). */ + bool aggs_by_ref = false; + /* All aggregate lattices contain a variable component (in addition to + values). */ + bool aggs_contain_variable = false; + /* The value of all aggregate lattices is bottom (i.e. variable and unusable + for any propagation). */ + bool aggs_bottom = false; + + /* There is a virtual call based on this parameter. */ + bool virt_call = false; +}; + +#endif /* IPA_CP_H */ diff --git a/gcc/ipa-devirt.cc b/gcc/ipa-devirt.cc index caf8548..a7ce434 100644 --- a/gcc/ipa-devirt.cc +++ b/gcc/ipa-devirt.cc @@ -124,6 +124,8 @@ along with GCC; see the file COPYING3. If not see #include "gimple-fold.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "demangle.h" diff --git a/gcc/ipa-fnsummary.cc b/gcc/ipa-fnsummary.cc index 74c9b4e..dff40cd 100644 --- a/gcc/ipa-fnsummary.cc +++ b/gcc/ipa-fnsummary.cc @@ -75,6 +75,8 @@ along with GCC; see the file COPYING3. If not see #include "tree-ssa-loop-niter.h" #include "tree-ssa-loop.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "cfgloop.h" diff --git a/gcc/ipa-icf.cc b/gcc/ipa-icf.cc index f568913..5d5a42f 100644 --- a/gcc/ipa-icf.cc +++ b/gcc/ipa-icf.cc @@ -73,6 +73,8 @@ along with GCC; see the file COPYING3. If not see #include "gimple-iterator.h" #include "tree-cfg.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "except.h" diff --git a/gcc/ipa-inline-analysis.cc b/gcc/ipa-inline-analysis.cc index 24ac4cb..a190cb6 100644 --- a/gcc/ipa-inline-analysis.cc +++ b/gcc/ipa-inline-analysis.cc @@ -40,6 +40,8 @@ along with GCC; see the file COPYING3. If not see #include "tree-ssa-loop-niter.h" #include "tree-ssa-loop.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "ipa-inline.h" diff --git a/gcc/ipa-inline-transform.cc b/gcc/ipa-inline-transform.cc index a05631a..73ae4e6 100644 --- a/gcc/ipa-inline-transform.cc +++ b/gcc/ipa-inline-transform.cc @@ -40,6 +40,8 @@ along with GCC; see the file COPYING3. If not see #include "tree-cfg.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "ipa-inline.h" diff --git a/gcc/ipa-inline.cc b/gcc/ipa-inline.cc index be2ca58..cc509b0 100644 --- a/gcc/ipa-inline.cc +++ b/gcc/ipa-inline.cc @@ -108,11 +108,12 @@ along with GCC; see the file COPYING3. If not see #include "profile.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "ipa-inline.h" #include "ipa-utils.h" -#include "sreal.h" #include "auto-profile.h" #include "builtins.h" #include "fibonacci_heap.h" diff --git a/gcc/ipa-modref.cc b/gcc/ipa-modref.cc index cec730d..a5adce8 100644 --- a/gcc/ipa-modref.cc +++ b/gcc/ipa-modref.cc @@ -75,6 +75,8 @@ along with GCC; see the file COPYING3. If not see #include "ipa-modref-tree.h" #include "ipa-modref.h" #include "value-range.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "attr-fnspec.h" diff --git a/gcc/ipa-param-manipulation.cc b/gcc/ipa-param-manipulation.cc index 02f71a4..3e0df6a 100644 --- a/gcc/ipa-param-manipulation.cc +++ b/gcc/ipa-param-manipulation.cc @@ -47,6 +47,8 @@ along with GCC; see the file COPYING3. If not see #include "tree-phinodes.h" #include "cfgexpand.h" #include "attribs.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" /* Actual prefixes of different newly synthetized parameters. Keep in sync diff --git a/gcc/ipa-predicate.cc b/gcc/ipa-predicate.cc index d3b3227..164aba4 100644 --- a/gcc/ipa-predicate.cc +++ b/gcc/ipa-predicate.cc @@ -27,6 +27,8 @@ along with GCC; see the file COPYING3. If not see #include "tree-vrp.h" #include "alloc-pool.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "real.h" diff --git a/gcc/ipa-profile.cc b/gcc/ipa-profile.cc index 5e89f67..27f411c 100644 --- a/gcc/ipa-profile.cc +++ b/gcc/ipa-profile.cc @@ -55,6 +55,8 @@ along with GCC; see the file COPYING3. If not see #include "tree-inline.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" diff --git a/gcc/ipa-prop.cc b/gcc/ipa-prop.cc index bec0ebd..e22c4f7 100644 --- a/gcc/ipa-prop.cc +++ b/gcc/ipa-prop.cc @@ -41,6 +41,8 @@ along with GCC; see the file COPYING3. If not see #include "gimplify-me.h" #include "gimple-walk.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "tree-cfg.h" #include "tree-dfa.h" @@ -4561,7 +4563,7 @@ ipa_node_params_t::duplicate(cgraph_node *, cgraph_node *, ipa_node_params *new_info) { new_info->descriptors = vec_safe_copy (old_info->descriptors); - new_info->lattices = NULL; + gcc_assert (new_info->lattices.is_empty ()); new_info->ipcp_orig_node = old_info->ipcp_orig_node; new_info->known_csts = old_info->known_csts.copy (); new_info->known_contexts = old_info->known_contexts.copy (); diff --git a/gcc/ipa-prop.h b/gcc/ipa-prop.h index 9c78dc9..ee3c000 100644 --- a/gcc/ipa-prop.h +++ b/gcc/ipa-prop.h @@ -627,7 +627,7 @@ public: vec *descriptors; /* Pointer to an array of structures describing individual formal parameters. */ - class ipcp_param_lattices * GTY((skip)) lattices; + vec GTY((skip)) lattices; /* Only for versioned nodes this field would not be NULL, it points to the node that IPA cp cloned from. */ struct cgraph_node * GTY((skip)) ipcp_orig_node; @@ -662,7 +662,7 @@ public: inline ipa_node_params::ipa_node_params () -: descriptors (NULL), lattices (NULL), ipcp_orig_node (NULL), +: descriptors (NULL), lattices (vNULL), ipcp_orig_node (NULL), known_csts (vNULL), known_contexts (vNULL), analysis_done (0), node_enqueued (0), do_clone_for_all_contexts (0), is_all_contexts_clone (0), node_dead (0), node_within_scc (0), node_is_self_scc (0), @@ -673,8 +673,8 @@ ipa_node_params::ipa_node_params () inline ipa_node_params::~ipa_node_params () { - free (lattices); vec_free (descriptors); + lattices.release (); known_csts.release (); known_contexts.release (); } diff --git a/gcc/ipa-pure-const.cc b/gcc/ipa-pure-const.cc index 7e9ece2..d285462 100644 --- a/gcc/ipa-pure-const.cc +++ b/gcc/ipa-pure-const.cc @@ -59,6 +59,8 @@ along with GCC; see the file COPYING3. If not see #include "ssa.h" #include "alloc-pool.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "symtab-thunks.h" diff --git a/gcc/ipa-split.cc b/gcc/ipa-split.cc index 8e6aa01..39ad822 100644 --- a/gcc/ipa-split.cc +++ b/gcc/ipa-split.cc @@ -95,6 +95,8 @@ along with GCC; see the file COPYING3. If not see #include "gimplify-me.h" #include "gimple-walk.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "tree-cfg.h" #include "tree-into-ssa.h" diff --git a/gcc/ipa-sra.cc b/gcc/ipa-sra.cc index 14c2a34..6d6da40 100644 --- a/gcc/ipa-sra.cc +++ b/gcc/ipa-sra.cc @@ -84,6 +84,8 @@ along with GCC; see the file COPYING3. If not see #include "internal-fn.h" #include "symtab-clones.h" #include "attribs.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" static void ipa_sra_summarize_function (cgraph_node *); diff --git a/gcc/ipa-strub.cc b/gcc/ipa-strub.cc index 0ee063c..09db1e0 100644 --- a/gcc/ipa-strub.cc +++ b/gcc/ipa-strub.cc @@ -43,6 +43,8 @@ along with GCC; see the file COPYING3. If not see #include "cgraph.h" #include "alloc-pool.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "gimple-fold.h" diff --git a/gcc/ipa-utils.cc b/gcc/ipa-utils.cc index 1567874..3be0ddb 100644 --- a/gcc/ipa-utils.cc +++ b/gcc/ipa-utils.cc @@ -33,6 +33,8 @@ along with GCC; see the file COPYING3. If not see #include "ipa-utils.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "tree-eh.h" diff --git a/gcc/ipa.cc b/gcc/ipa.cc index 82d8c59..c453fca 100644 --- a/gcc/ipa.cc +++ b/gcc/ipa.cc @@ -33,6 +33,8 @@ along with GCC; see the file COPYING3. If not see #include "ipa-utils.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "dbgcnt.h" diff --git a/gcc/lto/lto-common.cc b/gcc/lto/lto-common.cc index e54ddf2..2ce94cc 100644 --- a/gcc/lto/lto-common.cc +++ b/gcc/lto/lto-common.cc @@ -37,6 +37,8 @@ along with GCC; see the file COPYING3. If not see #include "stor-layout.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "common.h" #include "debug.h" diff --git a/gcc/lto/lto-partition.cc b/gcc/lto/lto-partition.cc index 7165747..19f91e5 100644 --- a/gcc/lto/lto-partition.cc +++ b/gcc/lto/lto-partition.cc @@ -31,10 +31,11 @@ along with GCC; see the file COPYING3. If not see #include "lto-streamer.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-fnsummary.h" #include "lto-partition.h" -#include "sreal.h" vec ltrans_partitions; diff --git a/gcc/lto/lto.cc b/gcc/lto/lto.cc index f7c0623..91aa2fb 100644 --- a/gcc/lto/lto.cc +++ b/gcc/lto/lto.cc @@ -38,6 +38,8 @@ along with GCC; see the file COPYING3. If not see #include "stor-layout.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "debug.h" #include "lto.h" diff --git a/gcc/toplev.cc b/gcc/toplev.cc index 175d4cd..2cd4096 100644 --- a/gcc/toplev.cc +++ b/gcc/toplev.cc @@ -74,6 +74,8 @@ along with GCC; see the file COPYING3. If not see #include "ipa-reference.h" #include "symbol-summary.h" #include "tree-vrp.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "ipa-utils.h" #include "gcse.h" diff --git a/gcc/tree-ssa-ccp.cc b/gcc/tree-ssa-ccp.cc index ad3b9b8..f6a5cd0 100644 --- a/gcc/tree-ssa-ccp.cc +++ b/gcc/tree-ssa-ccp.cc @@ -150,6 +150,8 @@ along with GCC; see the file COPYING3. If not see #include "alloc-pool.h" #include "symbol-summary.h" #include "ipa-utils.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "internal-fn.h" diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index 38b8066..3e93685 100644 --- a/gcc/tree-ssa-sccvn.cc +++ b/gcc/tree-ssa-sccvn.cc @@ -76,6 +76,8 @@ along with GCC; see the file COPYING3. If not see #include "tree-ssa-sccvn.h" #include "alloc-pool.h" #include "symbol-summary.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "target.h" diff --git a/gcc/tree-vrp.cc b/gcc/tree-vrp.cc index 978025b..b0f21e3 100644 --- a/gcc/tree-vrp.cc +++ b/gcc/tree-vrp.cc @@ -56,6 +56,8 @@ along with GCC; see the file COPYING3. If not see #include "cgraph.h" #include "symbol-summary.h" #include "ipa-utils.h" +#include "sreal.h" +#include "ipa-cp.h" #include "ipa-prop.h" #include "attribs.h" -- cgit v1.1 From 161a67b2bee84d8fd5ab7711e411f76221c1ea52 Mon Sep 17 00:00:00 2001 From: Gaius Mulley Date: Wed, 21 Feb 2024 16:21:05 +0000 Subject: PR modula2/114026 Incorrect location during for loop type checking If a for loop contains an incompatible type expression between the designator and the second expression then the location used when generating the error message is set to token 0. The bug is fixed by extending the range checking InitForLoopBeginRangeCheck. The range checking is processed after all types, constants have been resolved (and converted into gcc trees). The range check will check for assignment compatibility between des and expr1, expression compatibility between des and expr2. Separate token positions for des, exp1, expr2 and by are stored in the Range record and used to create virtual tokens if they are on the same source line. gcc/m2/ChangeLog: PR modula2/114026 * gm2-compiler/M2GenGCC.mod (Import): Remove DisplayQuadruples. Remove DisplayQuadList. (MixTypesBinary): Replace check with overflowCheck. New variable typeChecking. Use GenQuadOTypetok to retrieve typeChecking. Use typeChecking to suppress error message. * gm2-compiler/M2LexBuf.def (MakeVirtual2Tok): New procedure function. * gm2-compiler/M2LexBuf.mod (MakeVirtualTok): Improve comment. (MakeVirtual2Tok): New procedure function. * gm2-compiler/M2Quads.def (GetQuadOTypetok): New procedure. * gm2-compiler/M2Quads.mod (QuadFrame): New field CheckType. (PutQuadO): Rewrite using PutQuadOType. (PutQuadOType): New procedure. (GetQuadOTypetok): New procedure. (BuildPseudoBy): Rewrite. (BuildForToByDo): Remove type checking. Add parameters e2, e2tok, BySym, bytok to InitForLoopBeginRange. Push the RangeId. (BuildEndFor): Pop the RangeId. Use GenQuadOTypetok to generate AddOp without type checking. Call PutRangeForIncrement with the RangeId and IncQuad. (GenQuadOtok): Rewrite using GenQuadOTypetok. (GenQuadOTypetok): New procedure. * gm2-compiler/M2Range.def (InitForLoopBeginRangeCheck): Rename d as des, e as expr. Add expr1, expr1tok, expr2, expr2tok, byconst, byconsttok parameters. (PutRangeForIncrement): New procedure. * gm2-compiler/M2Range.mod (Import): MakeVirtual2Tok. (Range): Add expr2, byconst, destok, exprtok, expr2tok, incrementquad. (InitRange): Initialize expr2 to NulSym. Initialize byconst to NulSym. Initialize tokenNo, destok, exprtok, expr2tok, byconst to UnknownTokenNo. Initialize incrementquad to 0. (PutRangeForIncrement): New procedure. (PutRangeDesExpr2): New procedure. (InitForLoopBeginRangeCheck): Rewrite. (ForLoopBeginTypeCompatible): New procedure function. (CodeForLoopBegin): Call ForLoopBeginTypeCompatible and only code the for loop assignment if all the type checks succeed. gcc/testsuite/ChangeLog: PR modula2/114026 * gm2/extensions/run/pass/callingc10.mod: New test. * gm2/extensions/run/pass/callingc11.mod: New test. * gm2/extensions/run/pass/callingc9.mod: New test. * gm2/extensions/run/pass/strconst.def: New test. * gm2/pim/fail/forloop.mod: New test. * gm2/pim/pass/forloop2.mod: New test. Signed-off-by: Gaius Mulley --- gcc/m2/gm2-compiler/M2GenGCC.mod | 26 ++-- gcc/m2/gm2-compiler/M2LexBuf.def | 13 +- gcc/m2/gm2-compiler/M2LexBuf.mod | 13 +- gcc/m2/gm2-compiler/M2Quads.def | 12 ++ gcc/m2/gm2-compiler/M2Quads.mod | 142 ++++++++++++++----- gcc/m2/gm2-compiler/M2Range.def | 18 ++- gcc/m2/gm2-compiler/M2Range.mod | 153 +++++++++++++++++++-- .../gm2/extensions/run/pass/callingc10.mod | 16 +++ .../gm2/extensions/run/pass/callingc11.mod | 17 +++ .../gm2/extensions/run/pass/callingc9.mod | 7 + gcc/testsuite/gm2/extensions/run/pass/strconst.def | 6 + gcc/testsuite/gm2/pim/fail/forloop.mod | 17 +++ gcc/testsuite/gm2/pim/pass/forloop2.mod | 18 +++ 13 files changed, 386 insertions(+), 72 deletions(-) create mode 100644 gcc/testsuite/gm2/extensions/run/pass/callingc10.mod create mode 100644 gcc/testsuite/gm2/extensions/run/pass/callingc11.mod create mode 100644 gcc/testsuite/gm2/extensions/run/pass/callingc9.mod create mode 100644 gcc/testsuite/gm2/extensions/run/pass/strconst.def create mode 100644 gcc/testsuite/gm2/pim/fail/forloop.mod create mode 100644 gcc/testsuite/gm2/pim/pass/forloop2.mod (limited to 'gcc') diff --git a/gcc/m2/gm2-compiler/M2GenGCC.mod b/gcc/m2/gm2-compiler/M2GenGCC.mod index c7581f8..aeba48d 100644 --- a/gcc/m2/gm2-compiler/M2GenGCC.mod +++ b/gcc/m2/gm2-compiler/M2GenGCC.mod @@ -93,7 +93,7 @@ FROM M2Error IMPORT InternalError, WriteFormat0, WriteFormat1, WriteFormat2, War FROM M2MetaError IMPORT MetaErrorT0, MetaErrorT1, MetaErrorT2, MetaErrorT3, MetaError1, MetaError2, MetaErrorStringT1 ; -FROM M2Options IMPORT DisplayQuadruples, UnboundedByReference, PedanticCast, +FROM M2Options IMPORT UnboundedByReference, PedanticCast, VerboseUnbounded, Iso, Pim, DebugBuiltins, WholeProgram, StrictTypeChecking, AutoInit, cflag, ScaffoldMain, ScaffoldDynamic, ScaffoldStatic, @@ -256,9 +256,9 @@ FROM m2except IMPORT BuildThrow, BuildTryBegin, BuildTryEnd, FROM M2Quads IMPORT QuadOperator, GetQuad, IsReferenced, GetNextQuad, SubQuad, PutQuad, MustCheckOverflow, GetQuadOtok, + GetQuadOTypetok, QuadToTokenNo, DisplayQuad, GetQuadtok, - GetM2OperatorDesc, GetQuadOp, - DisplayQuadList ; + GetM2OperatorDesc, GetQuadOp ; FROM M2Check IMPORT ParameterTypeCompatible, AssignmentTypeCompatible, ExpressionTypeCompatible ; FROM M2SSA IMPORT EnableSSA ; @@ -644,11 +644,6 @@ BEGIN Changed := TRUE END UNTIL NoChange ; - IF Debugging AND DisplayQuadruples AND FALSE - THEN - printf0('after resolving expressions with gcc\n') ; - DisplayQuadList - END ; RETURN Changed END ResolveConstantExpressions ; @@ -3660,13 +3655,13 @@ END CodeBinaryCheck ; (* - MixTypesBinary - depending upon check do not check pointer arithmetic. + MixTypesBinary - depending upon overflowCheck do not check pointer arithmetic. *) PROCEDURE MixTypesBinary (left, right: CARDINAL; - tokpos: CARDINAL; check: BOOLEAN) : CARDINAL ; + tokpos: CARDINAL; overflowCheck: BOOLEAN) : CARDINAL ; BEGIN - IF (NOT check) AND + IF (NOT overflowCheck) AND (IsPointer (GetTypeMode (left)) OR IsPointer (GetTypeMode (right))) THEN RETURN Address @@ -3743,6 +3738,7 @@ VAR lefttype, righttype, des, left, right: CARDINAL ; + typeChecking, overflowChecking: BOOLEAN ; despos, leftpos, rightpos, @@ -3750,10 +3746,10 @@ VAR subexprpos : CARDINAL ; op : QuadOperator ; BEGIN - GetQuadOtok (quad, operatorpos, op, - des, left, right, overflowChecking, - despos, leftpos, rightpos) ; - IF ((op # LogicalRotateOp) AND (op # LogicalShiftOp)) + GetQuadOTypetok (quad, operatorpos, op, + des, left, right, overflowChecking, typeChecking, + despos, leftpos, rightpos) ; + IF typeChecking AND (op # LogicalRotateOp) AND (op # LogicalShiftOp) THEN subexprpos := MakeVirtualTok (operatorpos, leftpos, rightpos) ; lefttype := GetType (left) ; diff --git a/gcc/m2/gm2-compiler/M2LexBuf.def b/gcc/m2/gm2-compiler/M2LexBuf.def index dd49f45..27610ec 100644 --- a/gcc/m2/gm2-compiler/M2LexBuf.def +++ b/gcc/m2/gm2-compiler/M2LexBuf.def @@ -42,7 +42,8 @@ EXPORT QUALIFIED OpenSource, CloseSource, ReInitialize, GetToken, InsertToken, FindFileNameFromToken, GetFileName, ResetForNewPass, currenttoken, currentstring, currentinteger, - AddTok, AddTokCharStar, AddTokInteger, MakeVirtualTok, + AddTok, AddTokCharStar, AddTokInteger, + MakeVirtualTok, MakeVirtual2Tok, SetFile, PushFile, PopFile, PrintTokenNo, DisplayToken, DumpTokens, BuiltinTokenNo, UnknownTokenNo ; @@ -197,12 +198,20 @@ PROCEDURE GetFileName () : String ; (* MakeVirtualTok - creates and return a new tokenno which is created from - tokenno range1 and range2. + tokenno caret, left and right. *) PROCEDURE MakeVirtualTok (caret, left, right: CARDINAL) : CARDINAL ; +(* + MakeVirtual2Tok - creates and return a new tokenno which is created from + two tokens left and right. +*) + +PROCEDURE MakeVirtual2Tok (left, right: CARDINAL) : CARDINAL ; + + (* *********************************************************************** * * These functions allow m2.lex to deliver tokens into the buffer diff --git a/gcc/m2/gm2-compiler/M2LexBuf.mod b/gcc/m2/gm2-compiler/M2LexBuf.mod index 84a0e25..af43855 100644 --- a/gcc/m2/gm2-compiler/M2LexBuf.mod +++ b/gcc/m2/gm2-compiler/M2LexBuf.mod @@ -1154,7 +1154,7 @@ END isSrcToken ; MakeVirtualTok - providing caret, left, right are associated with a source file and exist on the same src line then create and return a new tokenno which is created from - tokenno range1 and range2. Otherwise return caret. + tokenno left and right. Otherwise return caret. *) PROCEDURE MakeVirtualTok (caret, left, right: CARDINAL) : CARDINAL ; @@ -1184,6 +1184,17 @@ BEGIN END MakeVirtualTok ; +(* + MakeVirtual2Tok - creates and return a new tokenno which is created from + two tokens left and right. +*) + +PROCEDURE MakeVirtual2Tok (left, right: CARDINAL) : CARDINAL ; +BEGIN + RETURN MakeVirtualTok (left, left, right) +END MakeVirtual2Tok ; + + (* *********************************************************************** * * These functions allow m2.flex to deliver tokens into the buffer diff --git a/gcc/m2/gm2-compiler/M2Quads.def b/gcc/m2/gm2-compiler/M2Quads.def index e9fd122..3e92e31 100644 --- a/gcc/m2/gm2-compiler/M2Quads.def +++ b/gcc/m2/gm2-compiler/M2Quads.def @@ -132,6 +132,7 @@ EXPORT QUALIFIED StartBuildDefFile, StartBuildModFile, EndBuildFile, SubQuad, EraseQuad, GetRealQuad, GetQuadtok, GetQuadOtok, PutQuadOtok, GetQuadOp, GetM2OperatorDesc, + GetQuadOTypetok, CountQuads, GetLastFileQuad, GetLastQuadNo, @@ -549,6 +550,17 @@ PROCEDURE GetQuadOtok (QuadNo: CARDINAL; (* + GetQuadOTypetok - returns the fields associated with quadruple QuadNo. +*) + +PROCEDURE GetQuadOTypetok (QuadNo: CARDINAL; + VAR tok: CARDINAL; + VAR Op: QuadOperator; + VAR Oper1, Oper2, Oper3: CARDINAL; + VAR overflowChecking, typeChecking: BOOLEAN ; + VAR Op1Pos, Op2Pos, Op3Pos: CARDINAL) ; + +(* PutQuadOtok - alters a quadruple QuadNo with Op, Oper1, Oper2, Oper3, and sets a boolean to determinine whether overflow should be checked. *) diff --git a/gcc/m2/gm2-compiler/M2Quads.mod b/gcc/m2/gm2-compiler/M2Quads.mod index e40e07d..1275ad2f 100644 --- a/gcc/m2/gm2-compiler/M2Quads.mod +++ b/gcc/m2/gm2-compiler/M2Quads.mod @@ -255,6 +255,7 @@ FROM M2Range IMPORT InitAssignmentRangeCheck, InitWholeZeroDivisionCheck, InitWholeZeroRemainderCheck, InitParameterRangeCheck, + PutRangeForIncrement, WriteRangeCheck ; FROM M2CaseList IMPORT PushCase, PopCase, AddRange, BeginCaseList, EndCaseList, ElseCase ; @@ -298,6 +299,7 @@ TYPE LineNo : CARDINAL ; (* Line No of source text. *) TokenNo : CARDINAL ; (* Token No of source text. *) NoOfTimesReferenced: CARDINAL ; (* No of times quad is referenced. *) + CheckType, CheckOverflow : BOOLEAN ; (* should backend check overflow *) op1pos, op2pos, @@ -1343,6 +1345,19 @@ PROCEDURE PutQuadO (QuadNo: CARDINAL; Op: QuadOperator; Oper1, Oper2, Oper3: CARDINAL; overflow: BOOLEAN) ; +BEGIN + PutQuadOType (QuadNo, Op, Oper1, Oper2, Oper3, overflow, TRUE) +END PutQuadO ; + + +(* + PutQuadOType - +*) + +PROCEDURE PutQuadOType (QuadNo: CARDINAL; + Op: QuadOperator; + Oper1, Oper2, Oper3: CARDINAL; + overflow, checktype: BOOLEAN) ; VAR f: QuadFrame ; BEGIN @@ -1360,10 +1375,11 @@ BEGIN Operand1 := Oper1 ; Operand2 := Oper2 ; Operand3 := Oper3 ; - CheckOverflow := overflow + CheckOverflow := overflow ; + CheckType := checktype END END -END PutQuadO ; +END PutQuadOType ; (* @@ -1379,6 +1395,36 @@ END PutQuad ; (* + GetQuadOtok - returns the fields associated with quadruple QuadNo. +*) + +PROCEDURE GetQuadOTypetok (QuadNo: CARDINAL; + VAR tok: CARDINAL; + VAR Op: QuadOperator; + VAR Oper1, Oper2, Oper3: CARDINAL; + VAR overflowChecking, typeChecking: BOOLEAN ; + VAR Op1Pos, Op2Pos, Op3Pos: CARDINAL) ; +VAR + f: QuadFrame ; +BEGIN + f := GetQF (QuadNo) ; + LastQuadNo := QuadNo ; + WITH f^ DO + Op := Operator ; + Oper1 := Operand1 ; + Oper2 := Operand2 ; + Oper3 := Operand3 ; + Op1Pos := op1pos ; + Op2Pos := op2pos ; + Op3Pos := op3pos ; + tok := TokenNo ; + overflowChecking := CheckOverflow ; + typeChecking := CheckType + END +END GetQuadOTypetok ; + + +(* UndoReadWriteInfo - *) @@ -4379,15 +4425,22 @@ END PushZero ; PROCEDURE BuildPseudoBy ; VAR - e, t, dotok: CARDINAL ; + expr, type, dotok: CARDINAL ; BEGIN - PopTFtok (e, t, dotok) ; (* as there is no BY token this position is the DO at the end of the last expression. *) - PushTFtok (e, t, dotok) ; - IF t=NulSym + (* As there is no BY token this position is the DO at the end of the last expression. *) + PopTFtok (expr, type, dotok) ; + PushTFtok (expr, type, dotok) ; + IF type = NulSym + THEN + (* type := ZType *) + ELSIF IsEnumeration (SkipType (type)) OR (SkipType (type) = Char) THEN - t := GetSType (e) + (* Use type. *) + ELSIF IsOrdinalType (SkipType (type)) + THEN + type := ZType END ; - PushOne (dotok, t, 'the implied FOR loop increment will cause an overflow {%1ad}') + PushOne (dotok, type, 'the implied {%kFOR} loop increment will cause an overflow {%1ad}') END BuildPseudoBy ; @@ -4418,8 +4471,9 @@ END BuildForLoopToRangeCheck ; Entry Exit ===== ==== - - Ptr -> <- Ptr + <- Ptr + +----------------+ + Ptr -> | RangeId | +----------------+ |----------------| | BySym | ByType | | ForQuad | |----------------| |----------------| @@ -4490,6 +4544,7 @@ VAR BySym, ByType, ForLoop, + RangeId, t, f : CARDINAL ; etype, t1 : CARDINAL ; @@ -4503,24 +4558,8 @@ BEGIN PopTtok (e1, e1tok) ; PopTtok (Id, idtok) ; IdSym := RequestSym (idtok, Id) ; - IF NOT IsExpressionCompatible (GetSType (e1), GetSType (e2)) - THEN - MetaError2 ('incompatible types found in {%EkFOR} loop header, initial expression {%1tsad} and final expression {%2tsad}', - e1, e2) ; - CheckExpressionCompatible (idtok, GetSType (e1), GetSType (e2)) - END ; - IF NOT IsExpressionCompatible( GetSType (e1), ByType) - THEN - MetaError2 ('incompatible types found in {%EkFOR} loop header, initial expression {%1tsad} and {%kBY} {%2tsad}', - e2, BySym) ; - CheckExpressionCompatible (e1tok, GetSType (e1), ByType) - ELSIF NOT IsExpressionCompatible (GetSType (e2), ByType) - THEN - MetaError2 ('incompatible types found in {%EkFOR} loop header, final expression {%1tsad} and {%kBY} {%2tsad}', - e2, BySym) ; - CheckExpressionCompatible (e1tok, GetSType (e2), ByType) - END ; - BuildRange (InitForLoopBeginRangeCheck (IdSym, e1)) ; + RangeId := InitForLoopBeginRangeCheck (IdSym, idtok, e1, e1tok, e2, e2tok, BySym, bytok) ; + BuildRange (RangeId) ; PushTtok (IdSym, idtok) ; PushTtok (e1, e1tok) ; BuildAssignmentWithoutBounds (idtok, TRUE, TRUE) ; @@ -4593,7 +4632,8 @@ BEGIN PushTFtok (IdSym, GetSym (IdSym), idtok) ; PushTFtok (BySym, ByType, bytok) ; PushTFtok (FinalValue, GetSType (FinalValue), e2tok) ; - PushT (ForLoop) + PushT (ForLoop) ; + PushT (RangeId) END BuildForToByDo ; @@ -4622,6 +4662,7 @@ PROCEDURE BuildEndFor (endpostok: CARDINAL) ; VAR t, f, tsym, + RangeId, IncQuad, ForQuad: CARDINAL ; LastSym, @@ -4631,6 +4672,7 @@ VAR IdSym, idtok : CARDINAL ; BEGIN + PopT (RangeId) ; PopT (ForQuad) ; PopT (LastSym) ; PopTFtok (BySym, ByType, bytok) ; @@ -4661,10 +4703,11 @@ BEGIN is counting down. The above test will generate a more precise error message, so we suppress overflow detection here. *) - GenQuadOtok (bytok, AddOp, tsym, tsym, BySym, FALSE, - bytok, bytok, bytok) ; + GenQuadOTypetok (bytok, AddOp, tsym, tsym, BySym, FALSE, FALSE, + idtok, idtok, bytok) ; CheckPointerThroughNil (idtok, IdSym) ; - GenQuadOtok (idtok, XIndrOp, IdSym, GetSType (IdSym), tsym, FALSE, + GenQuadOtok (idtok, XIndrOp, IdSym, GetSType (IdSym), + tsym, FALSE, idtok, idtok, idtok) ELSE BuildRange (InitForLoopEndRangeCheck (IdSym, BySym)) ; @@ -4673,13 +4716,20 @@ BEGIN this addition can legitimately overflow if a cardinal type is counting down. The above test will generate a more precise error message, so we suppress overflow detection - here. *) - GenQuadOtok (idtok, AddOp, IdSym, IdSym, BySym, FALSE, - bytok, bytok, bytok) + here. + + This quadruple suppresses the generic binary op type + check (performed in M2GenGCC.mod) as there + will be a more informative/exhaustive check performed by the + InitForLoopBeginRangeCheck setup in BuildForToByDo and + performed by M2Range.mod. *) + GenQuadOTypetok (idtok, AddOp, IdSym, IdSym, BySym, FALSE, FALSE, + idtok, idtok, bytok) END ; GenQuadO (endpostok, GotoOp, NulSym, NulSym, ForQuad, FALSE) ; BackPatch (PopFor (), NextQuad) ; - AddForInfo (ForQuad, NextQuad-1, IncQuad, IdSym, idtok) + AddForInfo (ForQuad, NextQuad-1, IncQuad, IdSym, idtok) ; + PutRangeForIncrement (RangeId, IncQuad) END BuildEndFor ; @@ -13188,6 +13238,22 @@ PROCEDURE GenQuadOtok (TokPos: CARDINAL; Operation: QuadOperator; Op1, Op2, Op3: CARDINAL; overflow: BOOLEAN; Op1Pos, Op2Pos, Op3Pos: CARDINAL) ; +BEGIN + GenQuadOTypetok (TokPos, Operation, Op1, Op2, Op3, overflow, TRUE, + Op1Pos, Op2Pos, Op3Pos) +END GenQuadOtok ; + + +(* + GenQuadOTypetok - assigns the fields of the quadruple with + the parameters. +*) + +PROCEDURE GenQuadOTypetok (TokPos: CARDINAL; + Operation: QuadOperator; + Op1, Op2, Op3: CARDINAL; + overflow, typecheck: BOOLEAN; + Op1Pos, Op2Pos, Op3Pos: CARDINAL) ; VAR f: QuadFrame ; BEGIN @@ -13199,7 +13265,7 @@ BEGIN f := GetQF (NextQuad-1) ; f^.Next := NextQuad END ; - PutQuadO (NextQuad, Operation, Op1, Op2, Op3, overflow) ; + PutQuadOType (NextQuad, Operation, Op1, Op2, Op3, overflow, typecheck) ; f := GetQF (NextQuad) ; WITH f^ DO Next := 0 ; @@ -13221,7 +13287,7 @@ BEGIN (* DisplayQuad(NextQuad) ; *) NewQuad (NextQuad) END -END GenQuadOtok ; +END GenQuadOTypetok ; (* diff --git a/gcc/m2/gm2-compiler/M2Range.def b/gcc/m2/gm2-compiler/M2Range.def index 14c30a7..2ffd74f 100644 --- a/gcc/m2/gm2-compiler/M2Range.def +++ b/gcc/m2/gm2-compiler/M2Range.def @@ -117,11 +117,23 @@ PROCEDURE InitDecRangeCheck (d, e: CARDINAL) : CARDINAL ; (* InitForLoopBeginRangeCheck - returns a range check node which remembers the information necessary - so that a range check for FOR d := e TO .. DO - can be generated later on. + so that a range check for + FOR des := expr1 TO expr2 DO + can be generated later on. expr2 is + only used to type check with des. *) -PROCEDURE InitForLoopBeginRangeCheck (d, e: CARDINAL) : CARDINAL ; +PROCEDURE InitForLoopBeginRangeCheck (des, destok, + expr1, expr1tok, + expr2, expr2tok, + byconst, byconsttok: CARDINAL) : CARDINAL ; + + +(* + PutRangeForIncrement - places incrementquad into the range record. +*) + +PROCEDURE PutRangeForIncrement (range: CARDINAL; incrementquad: CARDINAL) ; (* diff --git a/gcc/m2/gm2-compiler/M2Range.mod b/gcc/m2/gm2-compiler/M2Range.mod index 97abd3e..fa1ef35 100644 --- a/gcc/m2/gm2-compiler/M2Range.mod +++ b/gcc/m2/gm2-compiler/M2Range.mod @@ -69,7 +69,9 @@ FROM M2MetaError IMPORT MetaError1, MetaError2, MetaError3, MetaErrorStringT1, MetaErrorStringT2, MetaErrorStringT3, MetaString3 ; -FROM M2LexBuf IMPORT UnknownTokenNo, GetTokenNo, FindFileNameFromToken, TokenToLineNo, TokenToColumnNo, TokenToLocation ; +FROM M2LexBuf IMPORT UnknownTokenNo, GetTokenNo, FindFileNameFromToken, + TokenToLineNo, TokenToColumnNo, TokenToLocation, MakeVirtual2Tok ; + FROM StrIO IMPORT WriteString, WriteLn ; FROM M2GCCDeclare IMPORT TryDeclareConstant, DeclareConstructor ; FROM M2Quads IMPORT QuadOperator, PutQuad, SubQuad, WriteOperand ; @@ -122,7 +124,8 @@ TYPE Range = POINTER TO RECORD type : TypeOfRange ; des, - expr, + expr, expr2, + byconst, desLowestType, exprLowestType: CARDINAL ; procedure : CARDINAL ; @@ -131,7 +134,12 @@ TYPE only used in pointernil *) dimension : CARDINAL ; caseList : CARDINAL ; + destok, + exprtok, + expr2tok, + byconsttok, tokenNo : CARDINAL ; + incrementquad : CARDINAL ; (* Increment quad used in FOR the loop. *) errorReported : BOOLEAN ; (* error message reported yet? *) strict : BOOLEAN ; (* is it a comparison expression? *) isin : BOOLEAN ; (* expression created by IN operator? *) @@ -293,12 +301,19 @@ BEGIN type := none ; des := NulSym ; expr := NulSym ; + expr2 := NulSym ; + byconst := NulSym ; desLowestType := NulSym ; exprLowestType := NulSym ; isLeftValue := FALSE ; (* ignored in all cases other *) dimension := 0 ; caseList := 0 ; - tokenNo := 0 ; (* than pointernil *) + tokenNo := UnknownTokenNo ; (* than pointernil *) + destok := UnknownTokenNo ; + exprtok := UnknownTokenNo ; + expr2tok := UnknownTokenNo ; + byconsttok := UnknownTokenNo ; + incrementquad := 0 ; errorReported := FALSE END ; PutIndice(RangeIndex, r, p) @@ -335,6 +350,19 @@ END setReported ; (* + PutRangeForIncrement - places incrementquad into the range record. +*) + +PROCEDURE PutRangeForIncrement (range: CARDINAL; incrementquad: CARDINAL) ; +VAR + p: Range ; +BEGIN + p := GetIndice (RangeIndex, range) ; + p^.incrementquad := incrementquad +END PutRangeForIncrement ; + + +(* PutRange - initializes contents of, p, to d, e and their lowest types. It also fills in the current token no @@ -358,6 +386,38 @@ END PutRange ; (* + PutRangeDesExpr2 - initializes contents of, p, to + des, expr1 and their lowest types. + It also fills in the token numbers for + des, expr, expr2 and returns, p. +*) + +PROCEDURE PutRangeDesExpr2 (p: Range; t: TypeOfRange; + des, destok, + expr1, expr1tok, + expr2, expr2tok, + byconst, byconsttok: CARDINAL) : Range ; +BEGIN + p^.des := des ; + p^.destok := destok ; + p^.expr := expr1 ; + p^.exprtok := expr1tok ; + p^.expr2 := expr2 ; + p^.expr2tok := expr2tok ; + p^.byconst := byconst ; + p^.byconsttok := byconsttok ; + WITH p^ DO + type := t ; + desLowestType := GetLowestType (des) ; + exprLowestType := GetLowestType (expr1) ; + strict := FALSE ; + isin := FALSE + END ; + RETURN p +END PutRangeDesExpr2 ; + + +(* chooseTokenPos - returns, tokenpos, if it is not the unknown location, otherwise it returns GetTokenNo. *) @@ -808,16 +868,25 @@ END InitTypesExpressionCheck ; (* InitForLoopBeginRangeCheck - returns a range check node which remembers the information necessary - so that a range check for FOR d := e TO .. DO - can be generated later on. + so that a range check for + FOR des := expr1 TO expr2 DO + can be generated later on. expr2 is + only used to type check with des. *) -PROCEDURE InitForLoopBeginRangeCheck (d, e: CARDINAL) : CARDINAL ; +PROCEDURE InitForLoopBeginRangeCheck (des, destok, + expr1, expr1tok, + expr2, expr2tok, + byconst, byconsttok: CARDINAL) : CARDINAL ; VAR r: CARDINAL ; BEGIN r := InitRange () ; - Assert (PutRange (GetTokenNo (), GetIndice (RangeIndex, r), forloopbegin, d, e) # NIL) ; + Assert (PutRangeDesExpr2 (GetIndice (RangeIndex, r), forloopbegin, + des, destok, + expr1, expr1tok, + expr2, expr2tok, + byconst, byconsttok) # NIL) ; RETURN r END InitForLoopBeginRangeCheck ; @@ -1786,6 +1855,58 @@ END CodeTypeCheck ; (* + ForLoopBeginTypeCompatible - check for designator assignment compatibility with + expr1 and designator expression compatibility with expr2. + FOR des := expr1 TO expr2 BY byconst DO + END + It generates composite tokens if the tokens are on + the same source line. +*) + +PROCEDURE ForLoopBeginTypeCompatible (p: Range) : BOOLEAN ; +VAR + combinedtok: CARDINAL ; + success : BOOLEAN ; +BEGIN + success := TRUE ; + WITH p^ DO + combinedtok := MakeVirtual2Tok (destok, exprtok) ; + IF NOT AssignmentTypeCompatible (combinedtok, "", des, expr) + THEN + MetaErrorT2 (combinedtok, + 'type incompatibility between {%1Et} and {%2t} detected during the assignment of the designator {%1a} to the first expression {%2a} in the {%kFOR} loop', + des, expr) ; + success := FALSE + END ; + combinedtok := MakeVirtual2Tok (destok, expr2tok) ; + IF NOT ExpressionTypeCompatible (combinedtok, "", des, expr2, TRUE, FALSE) + THEN + MetaErrorT2 (combinedtok, + 'type expression incompatibility between {%1Et} and {%2t} detected when comparing the designator {%1a} against the second expression {%2a} in the {%kFOR} loop', + des, expr2) ; + success := FALSE + END ; +(* + combinedtok := MakeVirtual2Tok (destok, byconsttok) ; + IF NOT ExpressionTypeCompatible (combinedtok, "", des, byconst, TRUE, FALSE) + THEN + MetaErrorT2 (combinedtok, + 'type expression incompatibility between {%1Et} and {%2t} detected between the the designator {%1a} and the {%kBY} constant expression {%2a} in the {%kFOR} loop', + des, byconst) ; + success := FALSE + END ; +*) + IF (NOT success) AND (incrementquad # 0) + THEN + (* Avoid a subsequent generic type check error. *) + SubQuad (incrementquad) + END + END ; + RETURN success +END ForLoopBeginTypeCompatible ; + + +(* FoldForLoopBegin - *) @@ -1802,14 +1923,17 @@ BEGIN IF GccKnowsAbout(expr) AND IsConst(expr) AND GetMinMax(tokenno, desLowestType, min, max) THEN - IF OutOfRange(tokenno, min, expr, max, desLowestType) + IF NOT ForLoopBeginTypeCompatible (p) THEN - MetaErrorT2(tokenNo, + SubQuad (q) + ELSIF OutOfRange (tokenno, min, expr, max, desLowestType) + THEN + MetaErrorT2 (tokenNo, 'attempting to assign a value {%2Wa} to a FOR loop designator {%1a} which will exceed the range of type {%1tad}', - des, expr) ; - PutQuad(q, ErrorOp, NulSym, NulSym, r) + des, expr) ; + PutQuad (q, ErrorOp, NulSym, NulSym, r) ELSE - SubQuad(q) + SubQuad (q) END END END @@ -2872,7 +2996,10 @@ END CodeDynamicArraySubscript ; PROCEDURE CodeForLoopBegin (tokenno: CARDINAL; r: CARDINAL; function, message: String) ; BEGIN - DoCodeAssignment(tokenno, r, function, message) + IF ForLoopBeginTypeCompatible (GetIndice (RangeIndex, r)) + THEN + DoCodeAssignment(tokenno, r, function, message) + END END CodeForLoopBegin ; diff --git a/gcc/testsuite/gm2/extensions/run/pass/callingc10.mod b/gcc/testsuite/gm2/extensions/run/pass/callingc10.mod new file mode 100644 index 0000000..3a2d3e2 --- /dev/null +++ b/gcc/testsuite/gm2/extensions/run/pass/callingc10.mod @@ -0,0 +1,16 @@ +MODULE callingc10 ; + +FROM cvararg IMPORT funcptr ; +FROM SYSTEM IMPORT ADR ; + +BEGIN + IF funcptr (1, "hello", 5) = 1 + THEN + END ; + IF funcptr (1, "hello" + " ", 6) = 1 + THEN + END ; + IF funcptr (1, "hello" + " " + "world", 11) = 1 + THEN + END +END callingc10. diff --git a/gcc/testsuite/gm2/extensions/run/pass/callingc11.mod b/gcc/testsuite/gm2/extensions/run/pass/callingc11.mod new file mode 100644 index 0000000..9b8cb82 --- /dev/null +++ b/gcc/testsuite/gm2/extensions/run/pass/callingc11.mod @@ -0,0 +1,17 @@ +MODULE callingc11 ; + +FROM cvararg IMPORT funcptr ; +FROM SYSTEM IMPORT ADR ; +FROM strconst IMPORT WORLD ; + +BEGIN + IF funcptr (1, "hello", 5) = 1 + THEN + END ; + IF funcptr (1, "hello" + " ", 6) = 1 + THEN + END ; + IF funcptr (1, "hello" + " " + WORLD, 11) = 1 + THEN + END +END callingc11. diff --git a/gcc/testsuite/gm2/extensions/run/pass/callingc9.mod b/gcc/testsuite/gm2/extensions/run/pass/callingc9.mod new file mode 100644 index 0000000..7e19a0a --- /dev/null +++ b/gcc/testsuite/gm2/extensions/run/pass/callingc9.mod @@ -0,0 +1,7 @@ +MODULE callingc9 ; + +VAR + array: ARRAY [0..9] OF CHAR ; +BEGIN + array := '0123456789' +END callingc9. diff --git a/gcc/testsuite/gm2/extensions/run/pass/strconst.def b/gcc/testsuite/gm2/extensions/run/pass/strconst.def new file mode 100644 index 0000000..af1111c --- /dev/null +++ b/gcc/testsuite/gm2/extensions/run/pass/strconst.def @@ -0,0 +1,6 @@ +DEFINITION MODULE FOR "C" strconst ; + +CONST + WORLD = "world" ; + +END strconst. diff --git a/gcc/testsuite/gm2/pim/fail/forloop.mod b/gcc/testsuite/gm2/pim/fail/forloop.mod new file mode 100644 index 0000000..be86a84 --- /dev/null +++ b/gcc/testsuite/gm2/pim/fail/forloop.mod @@ -0,0 +1,17 @@ +MODULE forloop ; + + +PROCEDURE init ; +VAR + i: INTEGER ; + c: CARDINAL ; +BEGIN + c := 10 ; + FOR i := 0 TO c DO (* INTEGER CARDINAL expression incompatible. *) + END +END init ; + + +BEGIN + init +END forloop. diff --git a/gcc/testsuite/gm2/pim/pass/forloop2.mod b/gcc/testsuite/gm2/pim/pass/forloop2.mod new file mode 100644 index 0000000..0bbc95d --- /dev/null +++ b/gcc/testsuite/gm2/pim/pass/forloop2.mod @@ -0,0 +1,18 @@ +MODULE forloop2 ; + +TYPE + colour = (red, green, blue) ; + + +PROCEDURE init ; +VAR + c: colour ; +BEGIN + FOR c := red TO blue DO + END +END init ; + + +BEGIN + init +END forloop2. -- cgit v1.1 From 5772ea772d1dce5bd9a3be99bf095f6f67810db2 Mon Sep 17 00:00:00 2001 From: David Faust Date: Tue, 20 Feb 2024 14:48:33 -0800 Subject: bpf: add inline memmove and memcpy expansion BPF programs are not typically linked, which means we cannot fall back on library calls to implement __builtin_{memmove,memcpy} and should always expand them inline if possible. GCC already successfully expands these builtins inline in many cases, but failed to do so for a few for simple cases involving overlapping memmove in the kernel BPF selftests and was instead emitting a libcall. This patch implements a simple inline expansion of memcpy and memmove in the BPF backend in a verifier-friendly way, with the caveat that the size must be an integer constant, which is also required by clang. gcc/ * config/bpf/bpf-protos.h (bpf_expand_cpymem): New. * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New. * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands. gcc/testsuite/ * gcc.target/bpf/memcpy-1.c: New test. * gcc.target/bpf/memmove-1.c: New test. * gcc.target/bpf/memmove-2.c: New test. --- gcc/config/bpf/bpf-protos.h | 2 + gcc/config/bpf/bpf.cc | 115 +++++++++++++++++++++++++++++++ gcc/config/bpf/bpf.md | 36 ++++++++++ gcc/testsuite/gcc.target/bpf/memcpy-1.c | 26 +++++++ gcc/testsuite/gcc.target/bpf/memmove-1.c | 46 +++++++++++++ gcc/testsuite/gcc.target/bpf/memmove-2.c | 23 +++++++ 6 files changed, 248 insertions(+) create mode 100644 gcc/testsuite/gcc.target/bpf/memcpy-1.c create mode 100644 gcc/testsuite/gcc.target/bpf/memmove-1.c create mode 100644 gcc/testsuite/gcc.target/bpf/memmove-2.c (limited to 'gcc') diff --git a/gcc/config/bpf/bpf-protos.h b/gcc/config/bpf/bpf-protos.h index 46d950b..366acb8 100644 --- a/gcc/config/bpf/bpf-protos.h +++ b/gcc/config/bpf/bpf-protos.h @@ -35,4 +35,6 @@ const char *bpf_add_core_reloc (rtx *operands, const char *templ); class gimple_opt_pass; gimple_opt_pass *make_pass_lower_bpf_core (gcc::context *ctxt); +bool bpf_expand_cpymem (rtx *, bool); + #endif /* ! GCC_BPF_PROTOS_H */ diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc index d6ca47e..f9ac263 100644 --- a/gcc/config/bpf/bpf.cc +++ b/gcc/config/bpf/bpf.cc @@ -1184,6 +1184,121 @@ bpf_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \ bpf_use_by_pieces_infrastructure_p +/* Helper for bpf_expand_cpymem. Emit an unrolled loop moving the bytes + from SRC to DST. */ + +static void +emit_move_loop (rtx src, rtx dst, machine_mode mode, int offset, int inc, + unsigned iters, unsigned remainder) +{ + rtx reg = gen_reg_rtx (mode); + + /* First copy in chunks as large as alignment permits. */ + for (unsigned int i = 0; i < iters; i++) + { + emit_move_insn (reg, adjust_address (src, mode, offset)); + emit_move_insn (adjust_address (dst, mode, offset), reg); + offset += inc; + } + + /* Handle remaining bytes which might be smaller than the chunks + used above. */ + if (remainder & 4) + { + emit_move_insn (reg, adjust_address (src, SImode, offset)); + emit_move_insn (adjust_address (dst, SImode, offset), reg); + offset += (inc < 0 ? -4 : 4); + remainder -= 4; + } + if (remainder & 2) + { + emit_move_insn (reg, adjust_address (src, HImode, offset)); + emit_move_insn (adjust_address (dst, HImode, offset), reg); + offset += (inc < 0 ? -2 : 2); + remainder -= 2; + } + if (remainder & 1) + { + emit_move_insn (reg, adjust_address (src, QImode, offset)); + emit_move_insn (adjust_address (dst, QImode, offset), reg); + } +} + +/* Expand cpymem/movmem, as from __builtin_memcpy/memmove. + OPERANDS are the same as the cpymem/movmem patterns. + IS_MOVE is true if this is a memmove, false for memcpy. + Return true if we successfully expanded, or false if we cannot + and must punt to a libcall. */ + +bool +bpf_expand_cpymem (rtx *operands, bool is_move) +{ + /* Size must be constant for this expansion to work. */ + if (!CONST_INT_P (operands[2])) + { + const char *name = is_move ? "memmove" : "memcpy"; + if (flag_building_libgcc) + warning (0, "could not inline call to %<__builtin_%s%>: " + "size must be constant", name); + else + error ("could not inline call to %<__builtin_%s%>: " + "size must be constant", name); + return false; + } + + /* Alignment is a CONST_INT. */ + gcc_assert (CONST_INT_P (operands[3])); + + rtx dst = operands[0]; + rtx src = operands[1]; + rtx size = operands[2]; + unsigned HOST_WIDE_INT size_bytes = UINTVAL (size); + unsigned align = UINTVAL (operands[3]); + enum machine_mode mode; + switch (align) + { + case 1: mode = QImode; break; + case 2: mode = HImode; break; + case 4: mode = SImode; break; + case 8: mode = DImode; break; + default: + gcc_unreachable (); + } + + unsigned iters = size_bytes >> ceil_log2 (align); + unsigned remainder = size_bytes & (align - 1); + + int inc = GET_MODE_SIZE (mode); + rtx_code_label *fwd_label, *done_label; + if (is_move) + { + /* For memmove, be careful of overlap. It is not a concern for memcpy. + To handle overlap, we check (at runtime) if SRC < DST, and if so do + the move "backwards" starting from SRC + SIZE. */ + fwd_label = gen_label_rtx (); + done_label = gen_label_rtx (); + + rtx dst_addr = copy_to_mode_reg (Pmode, XEXP (dst, 0)); + rtx src_addr = copy_to_mode_reg (Pmode, XEXP (src, 0)); + emit_cmp_and_jump_insns (src_addr, dst_addr, GEU, NULL_RTX, Pmode, + true, fwd_label, profile_probability::even ()); + + /* Emit the "backwards" unrolled loop. */ + emit_move_loop (src, dst, mode, size_bytes, -inc, iters, remainder); + emit_jump_insn (gen_jump (done_label)); + emit_barrier (); + + emit_label (fwd_label); + } + + emit_move_loop (src, dst, mode, 0, inc, iters, remainder); + + if (is_move) + emit_label (done_label); + + return true; +} + /* Finally, build the GCC target. */ struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md index 50df1aa..ca677bc 100644 --- a/gcc/config/bpf/bpf.md +++ b/gcc/config/bpf/bpf.md @@ -627,4 +627,40 @@ "{ldabs\t%0|r0 = *( *) skb[%0]}" [(set_attr "type" "ld")]) +;;; memmove and memcopy + +;; 0 is dst +;; 1 is src +;; 2 is size of copy in bytes +;; 3 is alignment + +(define_expand "cpymemdi" + [(match_operand:BLK 0 "memory_operand") + (match_operand:BLK 1 "memory_operand") + (match_operand:DI 2 "general_operand") + (match_operand:DI 3 "immediate_operand")] + "" +{ + if (bpf_expand_cpymem (operands, false)) + DONE; + FAIL; +}) + +;; 0 is dst +;; 1 is src +;; 2 is size of copy in bytes +;; 3 is alignment + +(define_expand "movmemdi" + [(match_operand:BLK 0 "memory_operand") + (match_operand:BLK 1 "memory_operand") + (match_operand:DI 2 "general_operand") + (match_operand:DI 3 "immediate_operand")] + "" +{ + if (bpf_expand_cpymem (operands, true)) + DONE; + FAIL; +}) + (include "atomic.md") diff --git a/gcc/testsuite/gcc.target/bpf/memcpy-1.c b/gcc/testsuite/gcc.target/bpf/memcpy-1.c new file mode 100644 index 0000000..6c9707f --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/memcpy-1.c @@ -0,0 +1,26 @@ +/* Ensure memcpy is expanded inline rather than emitting a libcall. */ + +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct context { + unsigned int data; + unsigned int data_end; + unsigned int data_meta; + unsigned int ingress; + unsigned int queue_index; + unsigned int egress; +}; + +void +cpy_1(struct context *ctx) +{ + void *data = (void *)(long)ctx->data; + char *dest; + dest = data; + dest += 16; + + __builtin_memcpy (dest, data, 8); +} + +/* { dg-final { scan-assembler-times "call" 0 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/memmove-1.c b/gcc/testsuite/gcc.target/bpf/memmove-1.c new file mode 100644 index 0000000..3b8ba82 --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/memmove-1.c @@ -0,0 +1,46 @@ +/* Ensure memmove is expanded inline rather than emitting a libcall. */ + +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct context { + unsigned int data; + unsigned int data_end; + unsigned int data_meta; + unsigned int ingress; + unsigned int queue_index; + unsigned int egress; +}; + +void +mov_1_nooverlap (struct context *ctx) +{ + void *data = (void *)(long)ctx->data; + char *dest; + dest = data; + dest += 16; + + __builtin_memmove (dest, data, 12); +} + +void +mov_1_overlap (struct context *ctx) +{ + void *data = (void *)(long)ctx->data; + char *dest; + dest = data; + dest += 4; + + __builtin_memmove (dest, data, 12); +} + +void +mov_1_arbitrary (struct context *ctx_a, struct context *ctx_b) +{ + void *src = (void *)(long)ctx_a->data; + void *dst = (void *)(long)ctx_b->data; + + __builtin_memmove (dst, src, 12); +} + +/* { dg-final { scan-assembler-times "call" 0 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/memmove-2.c b/gcc/testsuite/gcc.target/bpf/memmove-2.c new file mode 100644 index 0000000..c0f92d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/memmove-2.c @@ -0,0 +1,23 @@ +/* Test that we error if memmove cannot be expanded inline. */ + +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef unsigned int __u32; + +struct context { + unsigned int data; + unsigned int data_end; + unsigned int data_meta; +}; + +void +mov_2_unsupported (struct context *ctx) +{ + void *data = (void *)(long)ctx->data; + char *dest; + dest = data; + dest += 4; + + __builtin_memmove (dest, data, ctx->data_meta); /* { dg-error "could not inline call" } */ +} -- cgit v1.1 From 3232ebd91ed55b275b9d5a6e8355336382c4afd5 Mon Sep 17 00:00:00 2001 From: Edwin Lu Date: Tue, 20 Feb 2024 13:53:40 -0800 Subject: RISC-V: Specify mtune and march for PR113742 The testcase pr113742.c is failing for 32 bit targets due to the following cc1 error: cc1: error: ABI requries '-march=rv64' Specify '-march=rv64gc' with '-mtune=sifive-p600-series' PR target/113742 gcc/testsuite/ChangeLog: * gcc.target/riscv/pr113742.c: change mcpu to mtune and add march Signed-off-by: Edwin Lu --- gcc/testsuite/gcc.target/riscv/pr113742.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/riscv/pr113742.c b/gcc/testsuite/gcc.target/riscv/pr113742.c index ab8934c..573afd6 100644 --- a/gcc/testsuite/gcc.target/riscv/pr113742.c +++ b/gcc/testsuite/gcc.target/riscv/pr113742.c @@ -1,4 +1,4 @@ -//* { dg-do compile } */ -/* { dg-options "-O2 -finstrument-functions -mabi=lp64d -mcpu=sifive-p670" } */ +/* { dg-do compile } */ +/* { dg-options "-O2 -finstrument-functions -march=rv64gc -mabi=lp64d -mtune=sifive-p600-series" } */ void foo(void) {} -- cgit v1.1 From f5964f1a3567e078f3fa4921380301f5690a787a Mon Sep 17 00:00:00 2001 From: Jonathan Wakely Date: Wed, 21 Feb 2024 18:01:09 +0000 Subject: doc: Fix typos in -Wmismatched-dealloc docs gcc/ChangeLog: * doc/invoke.texi (Warning Options): Fix typos. --- gcc/doc/invoke.texi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d75b284..b4e4ee9 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -7262,7 +7262,7 @@ when non-existent profile data is justified. @item -Wmismatched-dealloc Warn for calls to deallocation functions with pointer arguments returned -from from allocations functions for which the former isn't a suitable +from allocation functions for which the former isn't a suitable deallocator. A pair of functions can be associated as matching allocators and deallocators by use of attribute @code{malloc}. Unless disabled by the @option{-fno-builtin} option the standard functions @code{calloc}, -- cgit v1.1 From 57b95223cb0ee472c86b34fc79d1193f3561451d Mon Sep 17 00:00:00 2001 From: Edwin Lu Date: Wed, 14 Feb 2024 12:01:22 -0800 Subject: RISC-V: Add non-vector types to dfa pipelines This patch adds non-vector related insn reservations and updates/creates new insn reservations so all non-vector typed instructions have a reservation. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation (generic_ooo_branch): Ditto * config/riscv/generic.md (generic_sfb_alu): Ditto (generic_fmul_half): Ditto * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation (sifive_7_popcount): Ditto * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto * config/riscv/vector.md: Change rdfrm to fmove * config/riscv/zc.md: Change pushpop to load/store Signed-off-by: Edwin Lu --- gcc/config/riscv/generic-ooo.md | 15 ++++++- gcc/config/riscv/generic.md | 20 +++++++-- gcc/config/riscv/riscv.md | 16 +++---- gcc/config/riscv/sifive-7.md | 17 +++++++- gcc/config/riscv/sifive-p400.md | 10 ++++- gcc/config/riscv/sifive-p600.md | 10 ++++- gcc/config/riscv/vector.md | 2 +- gcc/config/riscv/zc.md | 96 ++++++++++++++++++++--------------------- 8 files changed, 117 insertions(+), 69 deletions(-) (limited to 'gcc') diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md index a22f8a3..83cd062 100644 --- a/gcc/config/riscv/generic-ooo.md +++ b/gcc/config/riscv/generic-ooo.md @@ -115,9 +115,20 @@ (define_insn_reservation "generic_ooo_alu" 1 (and (eq_attr "tune" "generic_ooo") (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\ - move,bitmanip,min,max,minu,maxu,clz,ctz")) + move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\ + condmove,mvpair,zicond")) "generic_ooo_issue,generic_ooo_ixu_alu") +(define_insn_reservation "generic_ooo_sfb_alu" 2 + (and (eq_attr "tune" "generic_ooo") + (eq_attr "type" "sfb_alu")) + "generic_ooo_issue,generic_ooo_ixu_alu") + +;; Branch instructions +(define_insn_reservation "generic_ooo_branch" 1 + (and (eq_attr "tune" "generic_ooo") + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) + "generic_ooo_issue,generic_ooo_ixu_alu") ;; Float move, convert and compare. (define_insn_reservation "generic_ooo_float_move" 3 @@ -184,7 +195,7 @@ (define_insn_reservation "generic_ooo_vec_alu" 3 (and (eq_attr "tune" "generic_ooo") (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ - vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov")) + vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector")) "generic_ooo_vxu_issue,generic_ooo_vxu_alu") ;; Vector float comparison, conversion etc. diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md index 3f0eaa2..4f6e63b 100644 --- a/gcc/config/riscv/generic.md +++ b/gcc/config/riscv/generic.md @@ -27,7 +27,9 @@ (define_insn_reservation "generic_alu" 1 (and (eq_attr "tune" "generic") - (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop")) + (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\ + move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,\ + condmove,crypto,mvpair,zicond")) "alu") (define_insn_reservation "generic_load" 3 @@ -47,12 +49,17 @@ (define_insn_reservation "generic_branch" 1 (and (eq_attr "tune" "generic") - (eq_attr "type" "branch,jump,call,jalr")) + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) + "alu") + +(define_insn_reservation "generic_sfb_alu" 2 + (and (eq_attr "tune" "generic") + (eq_attr "type" "sfb_alu")) "alu") (define_insn_reservation "generic_imul" 10 (and (eq_attr "tune" "generic") - (eq_attr "type" "imul,clmul")) + (eq_attr "type" "imul,clmul,cpop")) "imuldiv*10") (define_insn_reservation "generic_idivsi" 34 @@ -67,6 +74,12 @@ (eq_attr "mode" "DI"))) "imuldiv*66") +(define_insn_reservation "generic_fmul_half" 5 + (and (eq_attr "tune" "generic") + (and (eq_attr "type" "fadd,fmul,fmadd") + (eq_attr "mode" "HF"))) + "alu") + (define_insn_reservation "generic_fmul_single" 5 (and (eq_attr "tune" "generic") (and (eq_attr "type" "fadd,fmul,fmadd") @@ -88,3 +101,4 @@ (and (eq_attr "tune" "generic") (eq_attr "type" "fsqrt")) "fdivsqrt*25") + diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 3f7a023..3c64c7c 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -328,9 +328,7 @@ ;; rotate rotation instructions ;; atomic atomic instructions ;; condmove conditional moves -;; cbo cache block instructions ;; crypto cryptography instructions -;; pushpop zc push and pop instructions ;; mvpair zc move pair instructions ;; zicond zicond instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. @@ -470,7 +468,7 @@ mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fcvt_i2f,fcvt_f2i,fsqrt,multi,auipc,sfb_alu,nop,trap, ghost,bitmanip,rotate,clmul,min,max,minu,maxu,clz,ctz,cpop, - atomic,condmove,cbo,crypto,pushpop,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm, + atomic,condmove,crypto,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm, rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff, @@ -3675,7 +3673,7 @@ UNSPECV_CLEAN)] "TARGET_ZICBOM" "cbo.clean\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "riscv_flush_" @@ -3683,7 +3681,7 @@ UNSPECV_FLUSH)] "TARGET_ZICBOM" "cbo.flush\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "riscv_inval_" @@ -3691,7 +3689,7 @@ UNSPECV_INVAL)] "TARGET_ZICBOM" "cbo.inval\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "riscv_zero_" @@ -3699,7 +3697,7 @@ UNSPECV_ZERO)] "TARGET_ZICBOZ" "cbo.zero\t%a0" - [(set_attr "type" "cbo")] + [(set_attr "type" "store")] ) (define_insn "prefetch" @@ -3715,7 +3713,7 @@ default: gcc_unreachable (); } } - [(set_attr "type" "cbo")]) + [(set_attr "type" "store")]) (define_insn "riscv_prefetchi_" [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r") @@ -3723,7 +3721,7 @@ UNSPECV_PREI)] "TARGET_ZICBOP" "prefetch.i\t%a0" - [(set_attr "type" "cbo")]) + [(set_attr "type" "store")]) (define_expand "extv" [(set (match_operand:GPR 0 "register_operand" "=r") diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md index 48bdba4..c208541 100644 --- a/gcc/config/riscv/sifive-7.md +++ b/gcc/config/riscv/sifive-7.md @@ -34,7 +34,7 @@ (define_insn_reservation "sifive_7_branch" 1 (and (eq_attr "tune" "sifive_7") - (eq_attr "type" "branch")) + (eq_attr "type" "branch,ret,trap")) "sifive_7_B") (define_insn_reservation "sifive_7_sfb_alu" 2 @@ -59,7 +59,8 @@ (define_insn_reservation "sifive_7_alu" 2 (and (eq_attr "tune" "sifive_7") - (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move")) + (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move,bitmanip,\ + rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,mvpair,zicond")) "sifive_7_A|sifive_7_B") (define_insn_reservation "sifive_7_load_immediate" 1 @@ -67,6 +68,12 @@ (eq_attr "type" "nop,const,auipc")) "sifive_7_A|sifive_7_B") +(define_insn_reservation "sifive_7_hfma" 5 + (and (eq_attr "tune" "sifive_7") + (and (eq_attr "type" "fadd,fmul,fmadd") + (eq_attr "mode" "HF"))) + "sifive_7_B") + (define_insn_reservation "sifive_7_sfma" 5 (and (eq_attr "tune" "sifive_7") (and (eq_attr "type" "fadd,fmul,fmadd") @@ -106,6 +113,12 @@ (eq_attr "type" "mfc")) "sifive_7_A") +;; Popcount and clmul. +(define_insn_reservation "sifive_7_popcount" 2 + (and (eq_attr "tune" "sifive_7") + (eq_attr "type" "cpop,clmul")) + "sifive_7_A") + (define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu" "sifive_7_alu,sifive_7_branch") diff --git a/gcc/config/riscv/sifive-p400.md b/gcc/config/riscv/sifive-p400.md index cc244d3..ed8b8ec 100644 --- a/gcc/config/riscv/sifive-p400.md +++ b/gcc/config/riscv/sifive-p400.md @@ -89,7 +89,7 @@ (define_insn_reservation "sifive_p400_branch" 1 (and (eq_attr "tune" "sifive_p400") - (eq_attr "type" "branch,jump,call")) + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) "sifive_p400_B+sifive_p400_bru") (define_insn_reservation "sifive_p400_sfb_alu" 1 @@ -114,7 +114,8 @@ (define_insn_reservation "sifive_p400_alu" 1 (and (eq_attr "tune" "sifive_p400") - (eq_attr "type" "unknown,arith,logical,shift,slt,multi,bitmanip,clz,ctz,rotate")) + (eq_attr "type" "unknown,arith,logical,shift,slt,multi,bitmanip,\ + clz,ctz,rotate,min,max,minu,maxu,condmove,mvpair,zicond")) "p400_int_pipe+sifive_p400_ialu") (define_insn_reservation "sifive_p400_cpop" 3 @@ -122,6 +123,11 @@ (eq_attr "type" "cpop")) "p400_int_pipe,sifive_p400_ialu*2") +(define_insn_reservation "sifive_p400_clmul" 3 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "clmul")) + "p400_int_pipe,sifive_p400_ialu*2") + (define_insn_reservation "sifive_p400_load_immediate" 1 (and (eq_attr "tune" "sifive_p400") (eq_attr "type" "nop,const,auipc,move")) diff --git a/gcc/config/riscv/sifive-p600.md b/gcc/config/riscv/sifive-p600.md index c048649..2401349 100644 --- a/gcc/config/riscv/sifive-p600.md +++ b/gcc/config/riscv/sifive-p600.md @@ -93,7 +93,7 @@ (define_insn_reservation "sifive_p600_branch" 1 (and (eq_attr "tune" "sifive_p600") - (eq_attr "type" "branch,jump,call")) + (eq_attr "type" "branch,jump,call,jalr,ret,trap")) "branch_pipe+sifive_p600_bru") (define_insn_reservation "sifive_p600_sfb_alu" 1 @@ -118,7 +118,8 @@ (define_insn_reservation "sifive_p600_alu" 1 (and (eq_attr "tune" "sifive_p600") - (eq_attr "type" "unknown,arith,logical,shift,slt,multi,bitmanip,clz,ctz,rotate")) + (eq_attr "type" "unknown,arith,logical,shift,slt,multi,bitmanip,\ + clz,ctz,rotate,min,max,minu,maxu,condmove,mvpair,zicond")) "int_pipe+sifive_p600_ialu") (define_insn_reservation "sifive_p600_cpop" 3 @@ -126,6 +127,11 @@ (eq_attr "type" "cpop")) "int_pipe,sifive_p600_ialu*2") +(define_insn_reservation "sifive_p600_clmul" 3 + (and (eq_attr "tune" "sifive_p600") + (eq_attr "type" "clmul")) + "int_pipe,sifive_p600_ialu*2") + (define_insn_reservation "sifive_p600_load_immediate" 1 (and (eq_attr "tune" "sifive_p600") (eq_attr "type" "nop,const,auipc,move")) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index ab6e099..f89f9c2 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1054,7 +1054,7 @@ (reg:SI FRM_REGNUM))] "TARGET_VECTOR" "frrm\t%0" - [(set_attr "type" "rdfrm") + [(set_attr "type" "fmove") (set_attr "mode" "SI")] ) diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md index 216232c..462ab37 100644 --- a/gcc/config/riscv/zc.md +++ b/gcc/config/riscv/zc.md @@ -27,7 +27,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -41,7 +41,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -58,7 +58,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -78,7 +78,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -101,7 +101,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -127,7 +127,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -156,7 +156,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -188,7 +188,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -223,7 +223,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -261,7 +261,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -302,7 +302,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_pop_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -349,7 +349,7 @@ (const_int ))))] "TARGET_ZCMP" "cm.pop {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_ra_" [(set (reg:X SP_REGNUM) @@ -362,7 +362,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -378,7 +378,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -397,7 +397,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -419,7 +419,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -444,7 +444,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -472,7 +472,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -503,7 +503,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -537,7 +537,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -574,7 +574,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -614,7 +614,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -657,7 +657,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popret_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -706,7 +706,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popret {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_ra_" [(set (reg:X SP_REGNUM) @@ -722,7 +722,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s0_" [(set (reg:X SP_REGNUM) @@ -741,7 +741,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s1_" [(set (reg:X SP_REGNUM) @@ -763,7 +763,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s2_" [(set (reg:X SP_REGNUM) @@ -788,7 +788,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s3_" [(set (reg:X SP_REGNUM) @@ -816,7 +816,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s4_" [(set (reg:X SP_REGNUM) @@ -847,7 +847,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s5_" [(set (reg:X SP_REGNUM) @@ -881,7 +881,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s6_" [(set (reg:X SP_REGNUM) @@ -918,7 +918,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s7_" [(set (reg:X SP_REGNUM) @@ -958,7 +958,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s8_" [(set (reg:X SP_REGNUM) @@ -1001,7 +1001,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s9_" [(set (reg:X SP_REGNUM) @@ -1047,7 +1047,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_popretz_up_to_s11_" [(set (reg:X SP_REGNUM) @@ -1099,7 +1099,7 @@ (use (reg:SI RETURN_ADDR_REGNUM))] "TARGET_ZCMP" "cm.popretz {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "load")]) (define_insn "@gpr_multi_push_up_to_ra_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1110,7 +1110,7 @@ (match_operand 0 "stack_push_up_to_ra_operand" "I")))] "TARGET_ZCMP" "cm.push {ra}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s0_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1124,7 +1124,7 @@ (match_operand 0 "stack_push_up_to_s0_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s1_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1141,7 +1141,7 @@ (match_operand 0 "stack_push_up_to_s1_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s1}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s2_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1161,7 +1161,7 @@ (match_operand 0 "stack_push_up_to_s2_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s2}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s3_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1184,7 +1184,7 @@ (match_operand 0 "stack_push_up_to_s3_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s3}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s4_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1210,7 +1210,7 @@ (match_operand 0 "stack_push_up_to_s4_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s4}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s5_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1239,7 +1239,7 @@ (match_operand 0 "stack_push_up_to_s5_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s5}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s6_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1271,7 +1271,7 @@ (match_operand 0 "stack_push_up_to_s6_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s6}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s7_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1306,7 +1306,7 @@ (match_operand 0 "stack_push_up_to_s7_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s7}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s8_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1344,7 +1344,7 @@ (match_operand 0 "stack_push_up_to_s8_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s8}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s9_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1385,7 +1385,7 @@ (match_operand 0 "stack_push_up_to_s9_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s9}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) (define_insn "@gpr_multi_push_up_to_s11_" [(set (mem:X (plus:X (reg:X SP_REGNUM) @@ -1432,7 +1432,7 @@ (match_operand 0 "stack_push_up_to_s11_operand" "I")))] "TARGET_ZCMP" "cm.push {ra, s0-s11}, %0" -[(set_attr "type" "pushpop")]) +[(set_attr "type" "store")]) ;; ZCMP mv (define_insn "*mva01s" -- cgit v1.1 From 6ec84c45a19403d3435b2affe4ec60e518fc1f97 Mon Sep 17 00:00:00 2001 From: Edwin Lu Date: Wed, 14 Feb 2024 12:03:37 -0800 Subject: RISC-V: Add vector related pipelines Creates new generic vector pipeline file common to all cpu tunes. Moves all vector related pipelines from generic-ooo to generic-vector-ooo. Creates new vector crypto related insn reservations. gcc/ChangeLog: * config/riscv/generic-ooo.md (generic_ooo): Move reservation (generic_ooo_vec_load): Ditto (generic_ooo_vec_store): Ditto (generic_ooo_vec_loadstore_seg): Ditto (generic_ooo_vec_alu): Ditto (generic_ooo_vec_fcmp): Ditto (generic_ooo_vec_imul): Ditto (generic_ooo_vec_fadd): Ditto (generic_ooo_vec_fmul): Ditto (generic_ooo_crypto): Ditto (generic_ooo_perm): Ditto (generic_ooo_vec_reduction): Ditto (generic_ooo_vec_ordered_reduction): Ditto (generic_ooo_vec_idiv): Ditto (generic_ooo_vec_float_divsqrt): Ditto (generic_ooo_vec_mask): Ditto (generic_ooo_vec_vesetvl): Ditto (generic_ooo_vec_setrm): Ditto (generic_ooo_vec_readlen): Ditto * config/riscv/riscv.md: Include generic-vector-ooo * config/riscv/generic-vector-ooo.md: New file. To here Signed-off-by: Edwin Lu Co-authored-by: Robin Dapp --- gcc/config/riscv/generic-ooo.md | 127 +---------------------------- gcc/config/riscv/generic-vector-ooo.md | 143 +++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.md | 1 + 3 files changed, 145 insertions(+), 126 deletions(-) create mode 100644 gcc/config/riscv/generic-vector-ooo.md (limited to 'gcc') diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md index 83cd062..e70df63 100644 --- a/gcc/config/riscv/generic-ooo.md +++ b/gcc/config/riscv/generic-ooo.md @@ -1,5 +1,5 @@ ;; RISC-V generic out-of-order core scheduling model. -;; Copyright (C) 2017-2024 Free Software Foundation, Inc. +;; Copyright (C) 2023-2024 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -48,9 +48,6 @@ ;; Integer/float issue queues. (define_cpu_unit "issue0,issue1,issue2,issue3,issue4" "generic_ooo") -;; Separate issue queue for vector instructions. -(define_cpu_unit "generic_ooo_vxu_issue" "generic_ooo") - ;; Integer/float execution units. (define_cpu_unit "ixu0,ixu1,ixu2,ixu3" "generic_ooo") (define_cpu_unit "fxu0,fxu1" "generic_ooo") @@ -58,12 +55,6 @@ ;; Integer subunit for division. (define_cpu_unit "generic_ooo_div" "generic_ooo") -;; Vector execution unit. -(define_cpu_unit "generic_ooo_vxu_alu" "generic_ooo") - -;; Vector subunit that does mult/div/sqrt. -(define_cpu_unit "generic_ooo_vxu_multicycle" "generic_ooo") - ;; Shortcuts (define_reservation "generic_ooo_issue" "issue0|issue1|issue2|issue3|issue4") (define_reservation "generic_ooo_ixu_alu" "ixu0|ixu1|ixu2|ixu3") @@ -92,25 +83,6 @@ (eq_attr "type" "fpstore")) "generic_ooo_issue,generic_ooo_fxu") -;; Vector load/store -(define_insn_reservation "generic_ooo_vec_load" 6 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -(define_insn_reservation "generic_ooo_vec_store" 6 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector segment loads/stores. -(define_insn_reservation "generic_ooo_vec_loadstore_seg" 10 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\ - vssegte,vssegts,vssegtux,vssegtox")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - - ;; Generic integer instructions. (define_insn_reservation "generic_ooo_alu" 1 (and (eq_attr "tune" "generic_ooo") @@ -191,103 +163,6 @@ (eq_attr "type" "cpop,clmul")) "generic_ooo_issue,generic_ooo_ixu_alu") -;; Regular vector operations and integer comparisons. -(define_insn_reservation "generic_ooo_vec_alu" 3 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ - vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector float comparison, conversion etc. -(define_insn_reservation "generic_ooo_vec_fcmp" 3 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\ - vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ - vfncvtftoi,vfncvtftof")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector integer multiplication. -(define_insn_reservation "generic_ooo_vec_imul" 4 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector float addition. -(define_insn_reservation "generic_ooo_vec_fadd" 4 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfalu,vfwalu")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector float multiplication and FMA. -(define_insn_reservation "generic_ooo_vec_fmul" 6 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector crypto, assumed to be a generic operation for now. -(define_insn_reservation "generic_ooo_crypto" 4 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "crypto")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector permute. -(define_insn_reservation "generic_ooo_perm" 3 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\ - vislide1down,vfslide1up,vfslide1down,vgather,vcompress")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector reduction. -(define_insn_reservation "generic_ooo_vec_reduction" 8 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vired,viwred,vfredu,vfwredu")) - "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle") - -;; Vector ordered reduction, assume the latency number is for -;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost -;; for larger vectors. -(define_insn_reservation "generic_ooo_vec_ordered_reduction" 10 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfredo,vfwredo")) - "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3") - -;; Vector integer division, assume not pipelined. -(define_insn_reservation "generic_ooo_vec_idiv" 16 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vidiv")) - "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3") - -;; Vector float divisions and sqrt, assume not pipelined. -(define_insn_reservation "generic_ooo_vec_float_divsqrt" 16 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vfdiv,vfsqrt")) - "generic_ooo_vxu_issue,generic_ooo_vxu_multicycle*3") - -;; Vector mask operations. -(define_insn_reservation "generic_ooo_vec_mask" 2 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\ - vfmovvf,vfmovfv")) - "generic_ooo_vxu_issue,generic_ooo_vxu_alu") - -;; Vector vsetvl. -(define_insn_reservation "generic_ooo_vec_vesetvl" 1 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "vsetvl,vsetvl_pre")) - "generic_ooo_vxu_issue") - -;; Vector rounding mode setters, assume pipeline barrier. -(define_insn_reservation "generic_ooo_vec_setrm" 20 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "wrvxrm,wrfrm")) - "generic_ooo_vxu_issue,generic_ooo_vxu_issue*3") - -;; Vector read vlen/vlenb. -(define_insn_reservation "generic_ooo_vec_readlen" 4 - (and (eq_attr "tune" "generic_ooo") - (eq_attr "type" "rdvlenb,rdvl")) - "generic_ooo_vxu_issue,generic_ooo_vxu_issue") - ;; Transfer from/to coprocessor. Assume not pipelined. (define_insn_reservation "generic_ooo_xfer" 4 (and (eq_attr "tune" "generic_ooo") diff --git a/gcc/config/riscv/generic-vector-ooo.md b/gcc/config/riscv/generic-vector-ooo.md new file mode 100644 index 0000000..96cb1a0 --- /dev/null +++ b/gcc/config/riscv/generic-vector-ooo.md @@ -0,0 +1,143 @@ +;; Copyright (C) 2024-2024 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . +;; Vector load/store + +(define_automaton "vector_ooo") + +;; Separate issue queue for vector instructions. +(define_cpu_unit "vxu_ooo_issue" "vector_ooo") + +;; Vector execution unit. +(define_cpu_unit "vxu_ooo_alu" "vector_ooo") + +;; Vector subunit that does mult/div/sqrt. +(define_cpu_unit "vxu_ooo_multicycle" "vector_ooo") + +(define_insn_reservation "vec_load" 6 + (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr") + "vxu_ooo_issue,vxu_ooo_alu") + +(define_insn_reservation "vec_store" 6 + (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector segment loads/stores. +(define_insn_reservation "vec_loadstore_seg" 10 + (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\ + vssegte,vssegts,vssegtux,vssegtox") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Regular vector operations and integer comparisons. +(define_insn_reservation "vec_alu" 3 + (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\ + vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\ + vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector float comparison, conversion etc. +(define_insn_reservation "vec_fcmp" 3 + (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\ + vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ + vfncvtftoi,vfncvtftof") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector integer multiplication. +(define_insn_reservation "vec_imul" 4 + (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\ + vghsh,vgmul") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector float addition. +(define_insn_reservation "vec_fadd" 4 + (eq_attr "type" "vfalu,vfwalu") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector float multiplication and FMA. +(define_insn_reservation "vec_fmul" 6 + (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector crypto, assumed to be a generic operation for now. +(define_insn_reservation "vec_crypto" 4 + (eq_attr "type" "crypto") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector crypto, AES +(define_insn_reservation "vec_crypto_aes" 4 + (eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector crypto, sha +(define_insn_reservation "vec_crypto_sha" 4 + (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector crypto, SM3/4 +(define_insn_reservation "vec_crypto_sm" 4 + (eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector permute. +(define_insn_reservation "vec_perm" 3 + (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\ + vislide1down,vfslide1up,vfslide1down,vgather,vcompress") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector reduction. +(define_insn_reservation "vec_reduction" 8 + (eq_attr "type" "vired,viwred,vfredu,vfwredu") + "vxu_ooo_issue,vxu_ooo_multicycle") + +;; Vector ordered reduction, assume the latency number is for +;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost +;; for larger vectors. +(define_insn_reservation "vec_ordered_reduction" 10 + (eq_attr "type" "vfredo,vfwredo") + "vxu_ooo_issue,vxu_ooo_multicycle*3") + +;; Vector integer division, assume not pipelined. +(define_insn_reservation "vec_idiv" 16 + (eq_attr "type" "vidiv") + "vxu_ooo_issue,vxu_ooo_multicycle*3") + +;; Vector float divisions and sqrt, assume not pipelined. +(define_insn_reservation "vec_float_divsqrt" 16 + (eq_attr "type" "vfdiv,vfsqrt") + "vxu_ooo_issue,vxu_ooo_multicycle*3") + +;; Vector mask operations. +(define_insn_reservation "vec_mask" 2 + (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\ + vfmovvf,vfmovfv") + "vxu_ooo_issue,vxu_ooo_alu") + +;; Vector vsetvl. +(define_insn_reservation "vec_vesetvl" 1 + (eq_attr "type" "vsetvl,vsetvl_pre") + "vxu_ooo_issue") + +;; Vector rounding mode setters, assume pipeline barrier. +(define_insn_reservation "vec_setrm" 20 + (eq_attr "type" "wrvxrm,wrfrm") + "vxu_ooo_issue,vxu_ooo_issue*3") + +;; Vector read vlen/vlenb. +(define_insn_reservation "vec_readlen" 4 + (eq_attr "type" "rdvlenb,rdvl") + "vxu_ooo_issue,vxu_ooo_issue") + diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 3c64c7c..1fec130 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3851,6 +3851,7 @@ (include "sifive-p400.md") (include "sifive-p600.md") (include "thead.md") +(include "generic-vector-ooo.md") (include "generic-ooo.md") (include "vector.md") (include "vector-crypto.md") -- cgit v1.1 From 67a29f99cc81384b9245ac5997e47bcf3ff84545 Mon Sep 17 00:00:00 2001 From: Edwin Lu Date: Wed, 14 Feb 2024 12:04:59 -0800 Subject: RISC-V: Use default cost model for insn scheduling Use default cost model scheduling on these test cases. All these tests introduce scan dump failures with -mtune generic-ooo. Since the vector cost models are the same across all three tunes, some of the tests in PR113249 will be fixed with this patch series. PR target/113249 gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/bug-1.C: Use default scheduling * gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: Ditto * gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: Ditto * gcc.target/riscv/rvv/base/pr108185-1.c: Ditto * gcc.target/riscv/rvv/base/pr108185-2.c: Ditto * gcc.target/riscv/rvv/base/pr108185-3.c: Ditto * gcc.target/riscv/rvv/base/pr108185-4.c: Ditto * gcc.target/riscv/rvv/base/pr108185-5.c: Ditto * gcc.target/riscv/rvv/base/pr108185-6.c: Ditto * gcc.target/riscv/rvv/base/pr108185-7.c: Ditto * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto * gfortran.dg/vect/vect-8.f90: Ditto Signed-off-by: Edwin Lu --- gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 2 ++ gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 2 ++ gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 2 ++ 58 files changed, 116 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C index c1070f9..6f62a64 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" template < class T > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c index 7be22d6..17a6b6f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c index 4b24b97..8386b42 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c index 99acc51..e2ed4b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c index d595c44..61340be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c index 0b51175..0f1485e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, uint64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c index 634c12a..173ac62 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c index 651d610..1edba89 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c index d19a9fd..75340c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c index 16f4315..7e4aedc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c index 347c846..755e92a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c index bc41444..2c82dc0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c index ce3f3af..e2ac6a3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c index 4946f84..436a0e8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c index 5f2eede..72b3216 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c index 5f2eede..72b3216 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c index 88fcba6..6908c78 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c index 88fcba6..6908c78 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c index 87a1645..ee1db1c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c index c0321ce..fb969eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c index ab0f13b..542f43e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c index 3893e17..31109a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c index b0ea553..924f450 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c index 350697d..659d8d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c index 0f138c5..6387460 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c index f4cbf09..a214d70 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c index d606078..efa659b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c index 9bf9ff5..6a26248 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c index bca55b2..429fe12 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, uint64_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c index 586e264..0cd0af7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c index d1bbb78..bb1690e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" void f (void * in, void *out, int32_t x, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c index 7e73878..37ef0f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c index c3d0b10..4c6e88e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c index bd13ba9..0844e3e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c index 99928f7..49a5744 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c index 321cd5c..cef0a11 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zve64d -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c index 575a784..3f0d677 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c index 95a11d3..4ed6588 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c index 8f6f0b1..95b7ff9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c index 250e017..9e0b41c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c index 110e55b..5e1859c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c index 4583504..f4f0e52 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c index f16f4b9..7e01b81 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c index 43b443b..5615cb1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c index 6785558..c906b15 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c index 960c9bf..006df7e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c index 5f22e8d..cc6d822 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c index e5f35c0..9704e444 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c index 0532c7d..476735d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c index b664c4b..c7b7db3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c index 04c4b88..80ff75f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c index 1404c9d..127dc7f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c index 1404c9d..127dc7f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c index 609c68d..e19e869 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c index 043f177..90eca5b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c index 0bedde8..17b217b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c index 0bedde8..17b217b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +// PR113249 +/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gfortran.dg/vect/vect-8.f90 b/gcc/testsuite/gfortran.dg/vect/vect-8.f90 index 938dfc2..f77ec9f 100644 --- a/gcc/testsuite/gfortran.dg/vect/vect-8.f90 +++ b/gcc/testsuite/gfortran.dg/vect/vect-8.f90 @@ -1,6 +1,8 @@ ! { dg-do compile } ! { dg-require-effective-target vect_double } ! { dg-additional-options "-fno-tree-loop-distribute-patterns -finline-matmul-limit=0" } +! PR113249 +! { dg-options "-fno-schedule-insns -fno-schedule-insns2" { target { riscv*-*-* } } } module lfk_prec integer, parameter :: dp=kind(1.d0) -- cgit v1.1 From bc6b42666cfe1467774b942c7afabe480e3b5ccb Mon Sep 17 00:00:00 2001 From: Edwin Lu Date: Wed, 14 Feb 2024 12:06:38 -0800 Subject: RISC-V: Quick and simple fixes to testcases that break due to reordering The following test cases are easily fixed with small updates to the expected assembly order. Additionally make calling-convention testcases more robust PR target/113249 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Rearrange and adjust asm-checker times * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Ditto * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: Rearrange assembly * gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto * gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Change expected vsetvl Signed-off-by: Edwin Lu --- .../riscv/rvv/autovec/vls/calling-convention-1.c | 27 +++++++++++++++++++--- .../riscv/rvv/autovec/vls/calling-convention-2.c | 23 ++++++++++++++++-- .../riscv/rvv/autovec/vls/calling-convention-3.c | 18 ++++++++++++++- .../riscv/rvv/autovec/vls/calling-convention-4.c | 12 +++++++++- .../riscv/rvv/autovec/vls/calling-convention-5.c | 22 +++++++++++++++++- .../riscv/rvv/autovec/vls/calling-convention-6.c | 17 ++++++++++++++ .../riscv/rvv/autovec/vls/calling-convention-7.c | 12 +++++++++- .../riscv/rvv/base/binop_vx_constraint-12.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-16.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-17.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-19.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-21.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-23.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-25.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-27.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-29.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-31.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-33.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-35.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-4.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-40.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-44.c | 4 +--- .../riscv/rvv/base/binop_vx_constraint-8.c | 4 +--- .../riscv/rvv/base/shift_vx_constraint-1.c | 5 +--- .../gcc.target/riscv/rvv/vsetvl/avl_single-107.c | 2 +- 25 files changed, 140 insertions(+), 62 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c index 41e31c2..217885c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c @@ -143,12 +143,33 @@ DEF_RET1_ARG9 (v1024qi) DEF_RET1_ARG9 (v2048qi) DEF_RET1_ARG9 (v4096qi) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 9 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1qi tests: return value (lbu) and function prologue (sb) +// 1 lbu per test, argnum sb's when args > 1 /* { dg-final { scan-assembler-times {lbu\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {lhu\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 35 } } */ /* { dg-final { scan-assembler-times {sb\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v2qi test: return value (lhu) and function prologue (sh) +// 1 lhu per test, argnum sh's when args > 1 +/* { dg-final { scan-assembler-times {lhu\s+a0,\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sh\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v4qi tests: return value (lw) and function prologue (sw) +// 1 lw per test, argnum sw's when args > 1 +/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v8qi and v16qi tests: return value (ld) and function prologue (sd) +// - 1 ld per v8qi and 2 ld per v16qi with args > 1 +// - 2 * argnum sd's per v8qi and 3 * argnum sd's per v16qi when argnum > 1 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v32-4096qi tests: return value (vse8.v) +/* { dg-final { scan-assembler-times {vse8.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */ +// v1024-4096qi_ARG1 tests: return value (vse64.v) +// for some reason ARG1 returns using vse64 instead of vse8 +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c index 8544f16..f45e6a7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c @@ -133,10 +133,29 @@ DEF_RET1_ARG9 (v512hi) DEF_RET1_ARG9 (v1024hi) DEF_RET1_ARG9 (v2048hi) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 8 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1hi tests: return value (lhu) and function prologue (sh) +// 1 lhu per test, argnum sh's when args > 1 /* { dg-final { scan-assembler-times {lhu\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 33 } } */ /* { dg-final { scan-assembler-times {sh\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v2hi tests: return value (lw) and function prologue (sw) +// 1 lw per test, argnum sw's when args > 1 +/* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v4hi and v8hi tests: return value (ld) and function prologue (sd) +// - 1 ld per v4hi and 2 ld per v8hi with args > 1 +// - argnum sd's per v4hi when argnum > 1 +// - 2 * argnum sd's per v8hi when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v16-2048hi tests: return value (vse16.v) +/* { dg-final { scan-assembler-times {vse16.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */ +// v512-2048qi_ARG1 tests: return value (vse64.v) +// for some reason ARG1 returns using vse64 instead of vse16 +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c index 17b0693..6716b0a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c @@ -123,8 +123,24 @@ DEF_RET1_ARG9 (v256si) DEF_RET1_ARG9 (v512si) DEF_RET1_ARG9 (v1024si) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 7 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1si tests: return value (lw) and function prologue (sw) +// 1 lw per test, argnum sw's when args > 1 /* { dg-final { scan-assembler-times {lw\s+a0,\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 31 } } */ /* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v2si and v4si tests: return value (ld) and function prologue (sd) +// - 1 ld per v2si and 2 ld per v4si with args > 1 +// - argnum sd's per v2si when argnum > 1 +// - 2 * argnum sd's per v4si when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v8-1024si tests: return value (vse32.v) +/* { dg-final { scan-assembler-times {vse32.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */ +// 256-1024si tests: return value (vse64.v) +// for some reason ARG1 returns using vse64 instead of vse32 +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c index 8c3f6ba..0a649ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c @@ -113,6 +113,16 @@ DEF_RET1_ARG9 (v128di) DEF_RET1_ARG9 (v256di) DEF_RET1_ARG9 (v512di) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 6 } } */ -/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 29 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1di and v2di tests: return value (ld) and function prologue (sd) +// - 1 ld per v1di and 2 ld per v2di with args > 1 +// - argnum sd's per v1di when argnum > 1 +// - 2 * argnum sd's per v2di when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v4-512di tests: return value (vse64.v) +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)} 77 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c index a0208d8..fd5146f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c @@ -133,9 +133,29 @@ DEF_RET1_ARG9 (v512hf) DEF_RET1_ARG9 (v1024hf) DEF_RET1_ARG9 (v2048hf) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 8 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1hf tests: return value (lhu) and function prologue (sh) +// 1 lhu per test, argnum sh's when args > 1 /* { dg-final { scan-assembler-times {lhu\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */ -/* { dg-final { scan-assembler-times {lw\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sh\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v2hf tests: return value (lw) and function prologue (sw) +// 1 lw per test, argnum sw's when args > 1 +/* { dg-final { scan-assembler-times {lw\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v4hf and v8hf tests: return value (ld) and function prologue (sd) +// - 1 ld per v4hf and 2 ld per v8hf with args > 1 +// - argnum sd's per v4hf when argnum > 1 +// - 2 * argnum sd's per v8hf when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v16-2048hf tests: return value (vse16.v) +/* { dg-final { scan-assembler-times {vse16.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */ +// v512-2048qf_ARG1 tests: return value (vse64.v) +// for some reason ARG1 returns using vse64 instead of vse16 +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c index 58ef8bf..4723312 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c @@ -123,7 +123,24 @@ DEF_RET1_ARG9 (v256sf) DEF_RET1_ARG9 (v512sf) DEF_RET1_ARG9 (v1024sf) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 7 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1sf tests: return value (lw) and function prologue (sw) +// 1 lw per test, argnum sw's when args > 1 /* { dg-final { scan-assembler-times {lw\s+a[0-1],\s*[0-9]+\(sp\)} 8 } } */ /* { dg-final { scan-assembler-times {sw\s+a[0-7],\s*[0-9]+\(sp\)} 43 } } */ + +// v2sf and v4sf tests: return value (ld) and function prologue (sd) +// - 1 ld per v2sf and 2 ld per v4sf with args > 1 +// - argnum sd's per v2sf when argnum > 1 +// - 2 * argnum sd's per v4sf when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v8-1024sf tests: return value (vse32.v) +/* { dg-final { scan-assembler-times {vse32.v\s+v[0-9],\s*[0-9]+\(a0\)} 74 } } */ +// 256-1024sf tests: return value (vse64.v) +// for some reason ARG1 returns using vse64 instead of vse32 +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)\s+ret} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c index e35ccd5..40e1b93 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c @@ -113,6 +113,16 @@ DEF_RET1_ARG9 (v128df) DEF_RET1_ARG9 (v256df) DEF_RET1_ARG9 (v512df) +// RET1_ARG0 tests /* { dg-final { scan-assembler-times {li\s+a[0-1],\s*0} 6 } } */ -/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 29 } } */ +/* { dg-final { scan-assembler-times {mv\s+s0,a0\s+call\s+memset\s+mv\s+a0,s0} 3 } } */ + +// v1df and v2df tests: return value (ld) and function prologue (sd) +// - 1 ld per v1df and 2 ld per v2df with args > 1 +// - argnum sd's per v1df when argnum > 1 +// - 2 * argnum sd's per v2df when argnum > 0 +/* { dg-final { scan-assembler-times {ld\s+a[0-1],\s*[0-9]+\(sp\)} 24 } } */ /* { dg-final { scan-assembler-times {sd\s+a[0-7],\s*[0-9]+\(sp\)} 103 } } */ + +// v4-512df tests: return value (vse64.v) +/* { dg-final { scan-assembler-times {vse64.v\s+v[0-9],\s*[0-9]+\(a0\)} 77 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c index 173ac62..9a3327c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c index 1edba89..e83187d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c index 75340c3..9321b8f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c index 7e4aedc..9a64c13 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c index 755e92a..93249b2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c index 2c82dc0..0d6cb4f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c index e2ac6a3..228359d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c index 436a0e8..1960afb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c index 72b3216..6d2c074 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c index 72b3216..6d2c074 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c index 6908c78..4b2a6c0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c index 6908c78..4b2a6c0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c index ee1db1c..cebe6a6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c index fb969eb..4379310 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c index 542f43e..806d9db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c index 6a26248..83d5071 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -122,8 +120,8 @@ void f5 (void * in, void *out, int8_t x) ** f6: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... ** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ... ** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t ** vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c index 9e0b41c..622c890 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c @@ -1,7 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -// PR113249 -/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" @@ -28,9 +26,8 @@ void f1 (void * in, void *out) ** f2: ** ... ** vlm.v\tv[0-9]+,0\([a-x0-9]+\) -** ... -** ... ** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** ... ** vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ ** vsll\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t ** vse32.v\tv[0-9]+,0\([a-x0-9]+\) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c index 2b5e9f7..7b8acc2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c @@ -38,4 +38,4 @@ foo (int vl, int n, int m, int32_t *in, int32_t *out) } /* { dg-final { scan-assembler-times {vsetvli} 4 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ -/* { dg-final { scan-assembler-times {vsetvli\tzero,zero,e32,m1,t[au],m[au]} 1 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\tzero,a0,e32,m1,t[au],m[au]} 1 { target { { any-opts "-O2" "-O3" } && { no-opts "-g" "-funroll-loops" } } } } } */ -- cgit v1.1 From d7d79c466dd4f2763974cc33545275fa37cafc1f Mon Sep 17 00:00:00 2001 From: Edwin Lu Date: Wed, 14 Feb 2024 12:09:43 -0800 Subject: RISC-V: Enable assert for insn_has_dfa_reservation Enables assert that every typed instruction is associated with a dfa reservation gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv.cc | 2 -- 1 file changed, 2 deletions(-) (limited to 'gcc') diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4100abc..5e984ee 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -8269,9 +8269,7 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more) /* If we ever encounter an insn without an insn reservation, trip an assert so we can find and fix this problem. */ -#if 0 gcc_assert (insn_has_dfa_reservation_p (insn)); -#endif return more - 1; } -- cgit v1.1 From 98004ca00e4bf7a513cf3de65d3c3d9ad373872e Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Thu, 22 Feb 2024 00:18:58 +0000 Subject: Daily bump. --- gcc/ChangeLog | 184 +++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 16 ++++ gcc/lto/ChangeLog | 7 ++ gcc/m2/ChangeLog | 49 +++++++++++ gcc/rust/ChangeLog | 47 +++++++++++ gcc/testsuite/ChangeLog | 213 ++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 517 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9fe70cb..c770937 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,187 @@ +2024-02-21 Edwin Lu + + * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert + +2024-02-21 Edwin Lu + Robin Dapp + + * config/riscv/generic-ooo.md (generic_ooo): Move reservation + (generic_ooo_vec_load): Ditto + (generic_ooo_vec_store): Ditto + (generic_ooo_vec_loadstore_seg): Ditto + (generic_ooo_vec_alu): Ditto + (generic_ooo_vec_fcmp): Ditto + (generic_ooo_vec_imul): Ditto + (generic_ooo_vec_fadd): Ditto + (generic_ooo_vec_fmul): Ditto + (generic_ooo_crypto): Ditto + (generic_ooo_perm): Ditto + (generic_ooo_vec_reduction): Ditto + (generic_ooo_vec_ordered_reduction): Ditto + (generic_ooo_vec_idiv): Ditto + (generic_ooo_vec_float_divsqrt): Ditto + (generic_ooo_vec_mask): Ditto + (generic_ooo_vec_vesetvl): Ditto + (generic_ooo_vec_setrm): Ditto + (generic_ooo_vec_readlen): Ditto + * config/riscv/riscv.md: Include generic-vector-ooo + * config/riscv/generic-vector-ooo.md: New file. To here + +2024-02-21 Edwin Lu + + * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation + (generic_ooo_branch): Ditto + * config/riscv/generic.md (generic_sfb_alu): Ditto + (generic_fmul_half): Ditto + * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types + * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation + (sifive_7_popcount): Ditto + * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto + * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto + * config/riscv/vector.md: Change rdfrm to fmove + * config/riscv/zc.md: Change pushpop to load/store + +2024-02-21 Jonathan Wakely + + * doc/invoke.texi (Warning Options): Fix typos. + +2024-02-21 David Faust + + * config/bpf/bpf-protos.h (bpf_expand_cpymem): New. + * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New. + * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands. + +2024-02-21 Martin Jambor + + PR ipa/113476 + * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust + initializers in the contructor. + (ipa_node_params::~ipa_node_params): Release lattices as a vector. + * ipa-cp.h: New file. + * ipa-cp.cc: Include sreal.h and ipa-cp.h. + (ipcp_value_source): Move to ipa-cp.h. + (ipcp_value_base): Likewise. + (ipcp_value): Likewise. + (ipcp_lattice): Likewise. + (ipcp_agg_lattice): Likewise. + (ipcp_bits_lattice): Likewise. + (ipcp_vr_lattice): Likewise. + (ipcp_param_lattices): Likewise. + (ipa_get_parm_lattices): Remove assert latticess is non-NULL. + (ipa_value_from_jfunc): Adjust a check for empty lattices. + (ipa_context_from_jfunc): Likewise. + (ipa_agg_value_from_jfunc): Likewise. + (merge_agg_lats_step): Do not memset new aggregate lattices to zero. + (ipcp_propagate_stage): Allocate lattices in a vector as opposed to + just in contiguous memory. + (ipcp_store_vr_results): Adjust a check for empty lattices. + * auto-profile.cc: Include sreal.h and ipa-cp.h. + * cgraph.cc: Likewise. + * cgraphclones.cc: Likewise. + * cgraphunit.cc: Likewise. + * config/aarch64/aarch64.cc: Likewise. + * config/i386/i386-builtins.cc: Likewise. + * config/i386/i386-expand.cc: Likewise. + * config/i386/i386-features.cc: Likewise. + * config/i386/i386-options.cc: Likewise. + * config/i386/i386.cc: Likewise. + * config/rs6000/rs6000.cc: Likewise. + * config/s390/s390.cc: Likewise. + * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the + files to be included in gtype-desc.cc. + * gimple-range-fold.cc: Include sreal.h and ipa-cp.h. + * ipa-devirt.cc: Likewise. + * ipa-fnsummary.cc: Likewise. + * ipa-icf.cc: Likewise. + * ipa-inline-analysis.cc: Likewise. + * ipa-inline-transform.cc: Likewise. + * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher. + * ipa-modref.cc: Include sreal.h and ipa-cp.h. + * ipa-param-manipulation.cc: Likewise. + * ipa-predicate.cc: Likewise. + * ipa-profile.cc: Likewise. + * ipa-prop.cc: Likewise. + (ipa_node_params_t::duplicate): Assert new lattices remain empty + instead of setting them to NULL. + * ipa-pure-const.cc: Include sreal.h and ipa-cp.h. + * ipa-split.cc: Likewise. + * ipa-sra.cc: Likewise. + * ipa-strub.cc: Likewise. + * ipa-utils.cc: Likewise. + * ipa.cc: Likewise. + * toplev.cc: Likewise. + * tree-ssa-ccp.cc: Likewise. + * tree-ssa-sccvn.cc: Likewise. + * tree-vrp.cc: Likewise. + +2024-02-21 Tamar Christina + + * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from + Armv8.7-a. + +2024-02-21 Richard Sandiford + + * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state): + Use aarch64_gen_compare_zero_and_branch rather than emitting + a CBZ directly. + +2024-02-21 Richard Sandiford + + * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p): + Remove duplicated call. + +2024-02-21 Richard Sandiford + + * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall): + Check that each individual piece of state is shared in the same + way, rather than using an aggregate check for PSTATE.ZA. + +2024-02-21 Richard Sandiford + + * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state): + In the code that commits a lazy save, only zero ZA if the function + has ZA state. Similarly zero ZT0 if the function has ZT0 state. + +2024-02-21 Richard Sandiford + + * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove, + directly inserting the associated sequence + * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state): + ...here instead. + +2024-02-21 Richard Sandiford + + PR target/113995 + * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't + fold the SVE allocation into the initial allocation if the + initial allocation includes a VG save. + +2024-02-21 Richard Sandiford + + PR target/113220 + * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that + contain jumps even if called after initial RTL expansion. + * mode-switching.cc: Include cfgbuild.h. + (optimize_mode_switching): Allow the sequence returned by the + emit hook to contain internal jumps. Record which blocks + contain such jumps and split the blocks at the end. + * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for + non-debug insns when scanning the sequence. + +2024-02-21 Tobias Burnus + + * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch. + * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise. + +2024-02-21 Dimitar Dimitrov + + * doc/invoke.texi (-mmcu): Add information about MCU specs. + +2024-02-21 Dimitar Dimitrov + + * doc/invoke.texi (-minrt): Clarify that main + must take no arguments. + 2024-02-20 Georg-Johann Lay * config/avr/builtins.def: Use function prototypes of given size diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 6f470e7..768ab7e 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240221 +20240222 diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index d8165bb..61b7aa1 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,19 @@ +2024-02-21 David Malcolm + + PR analyzer/113999 + * analyzer.h (get_string_cst_size): New decl. + * region-model-manager.cc (get_string_cst_size): New. + (region_model_manager::maybe_get_char_from_string_cst): Treat + single-byte accesses within string_cst but beyond + TREE_STRING_LENGTH as being 0. + * region-model.cc (string_cst_has_null_terminator): Likewise. + +2024-02-21 David Malcolm + + PR analyzer/113998 + * ranges.cc (symbolic_byte_range::intersection): Handle empty ranges. + (selftest::test_intersects): Add test coverage for empty ranges. + 2024-02-19 David Malcolm PR analyzer/111289 diff --git a/gcc/lto/ChangeLog b/gcc/lto/ChangeLog index e206544..dd9310e 100644 --- a/gcc/lto/ChangeLog +++ b/gcc/lto/ChangeLog @@ -1,3 +1,10 @@ +2024-02-21 Martin Jambor + + PR ipa/113476 + * lto-common.cc: Include sreal.h and ipa-cp.h. + * lto-partition.cc: Include ipa-cp.h, move inclusion of sreal higher. + * lto.cc: Include sreal.h and ipa-cp.h. + 2024-02-10 Jakub Jelinek * lto-common.cc (print_lto_report_1): Use HOST_SIZE_T_PRINT_DEC diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog index 6c075b2..10cbe90 100644 --- a/gcc/m2/ChangeLog +++ b/gcc/m2/ChangeLog @@ -1,3 +1,52 @@ +2024-02-21 Gaius Mulley + + PR modula2/114026 + * gm2-compiler/M2GenGCC.mod (Import): Remove DisplayQuadruples. + Remove DisplayQuadList. + (MixTypesBinary): Replace check with overflowCheck. + New variable typeChecking. + Use GenQuadOTypetok to retrieve typeChecking. + Use typeChecking to suppress error message. + * gm2-compiler/M2LexBuf.def (MakeVirtual2Tok): New procedure + function. + * gm2-compiler/M2LexBuf.mod (MakeVirtualTok): Improve comment. + (MakeVirtual2Tok): New procedure function. + * gm2-compiler/M2Quads.def (GetQuadOTypetok): New procedure. + * gm2-compiler/M2Quads.mod (QuadFrame): New field CheckType. + (PutQuadO): Rewrite using PutQuadOType. + (PutQuadOType): New procedure. + (GetQuadOTypetok): New procedure. + (BuildPseudoBy): Rewrite. + (BuildForToByDo): Remove type checking. + Add parameters e2, e2tok, BySym, bytok to + InitForLoopBeginRange. + Push the RangeId. + (BuildEndFor): Pop the RangeId. + Use GenQuadOTypetok to generate AddOp without type checking. + Call PutRangeForIncrement with the RangeId and IncQuad. + (GenQuadOtok): Rewrite using GenQuadOTypetok. + (GenQuadOTypetok): New procedure. + * gm2-compiler/M2Range.def (InitForLoopBeginRangeCheck): + Rename d as des, e as expr. + Add expr1, expr1tok, expr2, expr2tok, byconst, byconsttok + parameters. + (PutRangeForIncrement): New procedure. + * gm2-compiler/M2Range.mod (Import): MakeVirtual2Tok. + (Range): Add expr2, byconst, destok, exprtok, expr2tok, + incrementquad. + (InitRange): Initialize expr2 to NulSym. + Initialize byconst to NulSym. + Initialize tokenNo, destok, exprtok, expr2tok, byconst to + UnknownTokenNo. + Initialize incrementquad to 0. + (PutRangeForIncrement): New procedure. + (PutRangeDesExpr2): New procedure. + (InitForLoopBeginRangeCheck): Rewrite. + (ForLoopBeginTypeCompatible): New procedure function. + (CodeForLoopBegin): Call ForLoopBeginTypeCompatible and + only code the for loop assignment if all the type checks + succeed. + 2024-02-19 Gaius Mulley PR modula2/113889 diff --git a/gcc/rust/ChangeLog b/gcc/rust/ChangeLog index b04423a..c8049e3 100644 --- a/gcc/rust/ChangeLog +++ b/gcc/rust/ChangeLog @@ -1,3 +1,50 @@ +2024-02-21 0xn4utilus + + * checks/errors/rust-ast-validation.cc (ASTValidation::visit): + Add variadic check on all parameters. + +2024-02-21 Owen Avery + + * backend/rust-compile-pattern.cc + (CompilePatternLet::visit): + Lookup type of sub-pattern, not tuple pattern itself. + +2024-02-21 Marc Poulhiès + + * backend/rust-builtins.cc + (BuiltinsContext::register_rust_mappings): Add powi and reformat. + * backend/rust-builtins.h: Add missing copyright header. + +2024-02-21 Arthur Cohen + + * expand/rust-macro-expand.h (struct MacroExpander): Nitpick: fix + formatting of emitted error. + +2024-02-21 Owen Avery + + * resolve/rust-ast-resolve-item.cc + (flatten_glob): Use Import class. + (flatten_rebind): Likewise. + (flatten_list): Likewise. + (flatten): Likewise. + (flatten_use_dec_to_paths): Likewise. + (flatten_use_dec_to_imports): Likewise. + (ResolveItem::visit): Likewise. + (Import::add_prefix): New. + (rust_flatten_nested_glob): Adjust test. + (rust_flatten_glob): Likewise. + (rust_flatten_rebind_none): Likewise. + (rust_flatten_rebind): Likewise. + (rust_flatten_rebind_nested): Likewise. + (rust_flatten_list): Likewise. + * resolve/rust-ast-resolve-item.h + (class Import): New. + +2024-02-21 Arthur Cohen + + * typecheck/rust-hir-type-check-implitem.h: Fix typo in field + (region_costraints -> region_constraints). + 2024-02-07 Kushal Pal * parse/rust-parse-impl.h (Parser::parse_trait_item): diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c9c2db7..2f1b15f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,216 @@ +2024-02-21 Edwin Lu + + PR target/113249 + * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: + Rearrange and adjust asm-checker times + * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Ditto + * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Ditto + * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Ditto + * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Ditto + * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Ditto + * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: + Rearrange assembly + * gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto + * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto + * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Change expected vsetvl + +2024-02-21 Edwin Lu + + PR target/113249 + * g++.target/riscv/rvv/base/bug-1.C: Use default scheduling + * gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: Ditto + * gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: Ditto + * gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: Ditto + * gcc.target/riscv/rvv/base/pr108185-1.c: Ditto + * gcc.target/riscv/rvv/base/pr108185-2.c: Ditto + * gcc.target/riscv/rvv/base/pr108185-3.c: Ditto + * gcc.target/riscv/rvv/base/pr108185-4.c: Ditto + * gcc.target/riscv/rvv/base/pr108185-5.c: Ditto + * gcc.target/riscv/rvv/base/pr108185-6.c: Ditto + * gcc.target/riscv/rvv/base/pr108185-7.c: Ditto + * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto + * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto + * gfortran.dg/vect/vect-8.f90: Ditto + +2024-02-21 Edwin Lu + + PR target/113742 + * gcc.target/riscv/pr113742.c: change mcpu to mtune and add march + +2024-02-21 David Faust + + * gcc.target/bpf/memcpy-1.c: New test. + * gcc.target/bpf/memmove-1.c: New test. + * gcc.target/bpf/memmove-2.c: New test. + +2024-02-21 Gaius Mulley + + PR modula2/114026 + * gm2/extensions/run/pass/callingc10.mod: New test. + * gm2/extensions/run/pass/callingc11.mod: New test. + * gm2/extensions/run/pass/callingc9.mod: New test. + * gm2/extensions/run/pass/strconst.def: New test. + * gm2/pim/fail/forloop.mod: New test. + * gm2/pim/pass/forloop2.mod: New test. + +2024-02-21 0xn4utilus + + * rust/compile/issue-2850.rs: New test. + +2024-02-21 Owen Avery + + * rust/compile/issue-2847-b.rs: New test. + +2024-02-21 Marc Poulhiès + + * rust/compile/torture/intrinsics-math.rs: Adjust pow test, add + test for powi. + +2024-02-21 Arthur Cohen + + * rust/compile/rustc_const_stable.rs: New test. + +2024-02-21 Owen Avery + + * rust/compile/use_2.rs: New test. + +2024-02-21 Arthur Cohen + + * rust/execute/torture/matches_macro.rs: New test. + +2024-02-21 Tamar Christina + + * g++.target/aarch64/acle/ls64.C: Add +ls64. + * g++.target/aarch64/acle/ls64_lto.C: Likewise. + * gcc.target/aarch64/acle/ls64_lto.c: Likewise. + * gcc.target/aarch64/acle/pr110100.c: Likewise. + * gcc.target/aarch64/acle/pr110132.c: Likewise. + * gcc.target/aarch64/options_set_28.c: Drop check for nols64. + * gcc.target/aarch64/pragma_cpp_predefs_2.c: Correct header checks. + +2024-02-21 Tamar Christina + + PR fortran/107071 + * gfortran.dg/ieee/modes_1.f90: skip aarch64, arm. + +2024-02-21 Richard Sandiford + + * gcc.target/aarch64/sme/locally_streaming_1_ts.c: New test. + * gcc.target/aarch64/sme/sibcall_7_ts.c: Likewise. + +2024-02-21 Richard Sandiford + + * gcc.target/aarch64/sme/sibcall_9.c: New test. + +2024-02-21 Richard Sandiford + + * gcc.target/aarch64/sme/zt0_state_5.c (test3): Expect ZT0 rather + than ZA to be zeroed. + (test5): Remove zeroing of ZA. + +2024-02-21 Richard Sandiford + + * gcc.target/aarch64/sme/zt0_state_5.c (test3, test5): Expect + zero { za }s. + +2024-02-21 Richard Sandiford + + PR target/113995 + * gcc.target/aarch64/sme/locally_streaming_1.c: Require + -fno-stack-clash-protection. + * gcc.target/aarch64/sme/locally_streaming_1_scp.c: New test. + +2024-02-21 Richard Sandiford + + PR target/113220 + * gcc.target/aarch64/sme/call_sm_switch_5.c: Add + -fno-stack-clash-protection. + * gcc.target/aarch64/sme/call_sm_switch_5_scp.c: New test. + * gcc.target/aarch64/sme/sibcall_6_scp.c: New test. + * gcc.target/aarch64/sme/za_state_4.c: Add + -fno-stack-clash-protection. + * gcc.target/aarch64/sme/za_state_4_scp.c: New test. + * gcc.target/aarch64/sme/za_state_5.c: Add + -fno-stack-clash-protection. + * gcc.target/aarch64/sme/za_state_5_scp.c: New test. + +2024-02-21 Ilya Leoshkevich + + * gcc.target/s390/zvector/autovec-double-signaling-eq.c: + Preserve exceptions. + * gcc.target/s390/zvector/autovec-float-signaling-eq.c: + Likewise. + +2024-02-21 David Malcolm + + PR analyzer/113999 + * c-c++-common/analyzer/strlen-pr113999.c: New test. + * gcc.dg/analyzer/strlen-1.c: More test coverage. + +2024-02-21 David Malcolm + + PR analyzer/113998 + * c-c++-common/analyzer/overlapping-buffers-pr113998.c: New test. + 2024-02-20 Peter Hill PR fortran/105658 -- cgit v1.1 From 9ca4c1bf082a4691482ca9f4814fea68f04e2cb3 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 30 Jan 2024 20:41:12 -0800 Subject: RISC-V: Add tests for constraints "i" and "s" The constraints "i" and "s" can be used with a symbol that binds externally, e.g. ``` namespace ns { extern int var, a[4]; } void foo() { asm(".pushsection .xxx,\"aw\"; .dc.a %0; .popsection" :: "s"(&ns::var)); asm(".reloc ., BFD_RELOC_NONE, %0" :: "s"(&ns::a[3])); } ``` gcc/testsuite/ChangeLog: * gcc.target/riscv/asm-raw-symbol.c: New test. --- gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c b/gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c new file mode 100644 index 0000000..28305a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-fpic" } */ + +extern int var, arr[2][2]; + +void +test (void) +{ + __asm__ ("@ %0" : : "i"(&var)); + __asm__ ("@ %0 %1 %2" : : "s"(&var), "s"(&arr[1][1]), "s"(test)); +} + +/* { dg-final { scan-assembler "@ var arr\\+12 test" } } */ +/* { dg-final { scan-assembler "@ var" } } */ -- cgit v1.1 From 3688c2b1a604a16b9ff46935770976960016b15c Mon Sep 17 00:00:00 2001 From: Pan Li Date: Wed, 21 Feb 2024 12:06:22 +0800 Subject: RISC-V: Upgrade RVV intrinsic version to 0.12 Upgrade the version of RVV intrinsic from 0.11 to 0.12. PR target/114017 gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade the version to 0.12. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-__riscv_v_intrinsic.c: Update the version to 0.12. * gcc.target/riscv/rvv/base/pr114017-1.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-c.cc | 2 +- .../gcc.target/riscv/predef-__riscv_v_intrinsic.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c | 19 +++++++++++++++++++ 3 files changed, 21 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c (limited to 'gcc') diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 3ef06dc..3755ec0 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -139,7 +139,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) { builtin_define ("__riscv_vector"); builtin_define_with_int_value ("__riscv_v_intrinsic", - riscv_ext_version_value (0, 11)); + riscv_ext_version_value (0, 12)); } if (TARGET_XTHEADVECTOR) diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c index dbbedf5..07f1f15 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c @@ -3,7 +3,7 @@ int main () { -#if __riscv_v_intrinsic != 11000 +#if __riscv_v_intrinsic != 12000 #error "__riscv_v_intrinsic" #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c new file mode 100644 index 0000000..8eee7c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +vuint8mf2_t +test (vuint16m1_t val, size_t shift, size_t vl) +{ +#if __riscv_v_intrinsic == 11000 + #warning "RVV Intrinsics v0.11" + return __riscv_vnclipu (val, shift, vl); +#endif + +#if __riscv_v_intrinsic == 12000 + #warning "RVV Intrinsics v0.12" /* { dg-warning "RVV Intrinsics v0.12" } */ + return __riscv_vnclipu (val, shift, 0, vl); +#endif +} + -- cgit v1.1 From 438ef143679e8421960f0484958664c6c92b1d7e Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Wed, 21 Feb 2024 20:41:18 -0600 Subject: rs6000: Neuter option -mpower{8,9}-vector [PR109987] As PR109987 and its duplicated bugs show, -mno-power8-vector (and -mno-power9-vector) cause some problems and as Segher pointed out in [1] they are workaround options, so this patch is to remove -m{no,}-power{8,9}-options. Like what we did for option -mdirect-move before, this patch still keep the corresponding internal flags and they are automatically set based on -mcpu. The test suite update takes some efforts, it consists of some aspects: - effective target powerpc_p{8,9}vector_ok are removed and replaced with powerpc_vsx_ok. - Some cases having -mpower{8,9}-vector are updated with -mvsx, some of them already have -mdejagnu-cpu. For those that don't have -mdejagnu-cpu, if -mdejagnu-cpu is needed for the test point, then it's appended; otherwise, add additional-options -mdejagnu-cpu=power{8,9} if has_arch_pwr{8,9} isn't satisfied. - Some test cases are updated with explicit -mvsx. - Some test cases with those two option mixed are adjusted to keep the test points, like -mpower8-vector -mno-power9-vector are updated with -mdejagnu-cpu=power8 -mvsx etc. - Some test cases with -mno-power{8,9}-vector are updated by replacing -mno-power{8,9}-vector with -mno-vsx, or just removing it. - For some cases, we don't always specify -mdejagnu-cpu to avoid to restrict the testing coverage, it would check has_arch_pwr{8,9} and appended that as need. - For vect test cases run, it doesn't specify -mcpu=power9 for power10 and up. Bootstrapped and regtested on: - powerpc64-linux-gnu P7/P8/P9 {-m32,-m64} - powerpc64le-linux-gnu P8/P9/P10 Although it's stage4 now, as the discussion in PR113115 we are still eager to neuter these two options, so is it ok for trunk? [1] https://gcc.gnu.org/pipermail/gcc-patches/2022-January/589303.html PR target/109987 gcc/ChangeLog: * config/rs6000/constraints.md (we): Update internal doc without referring to option -mpower9-vector. * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector special handlings. * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS, OTHER_P8_VECTOR_MASKS): Merge to ... (OTHER_VSX_VECTOR_MASKS): ... here. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove some error message handlings and explicit option mask adjustments on explicit option power{8,9}-vector conflicting with other options. (rs6000_print_isa_options): Update comments. (rs6000_disable_incompatible_switches): Remove power{8,9}-vector related array items and handlings. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector special handlings. * config/rs6000/rs6000.opt: Make option power{8,9}-vector as WarnRemoved. * doc/extend.texi: Remove documentation referring to option -mpower8-vector. * doc/invoke.texi: Remove documentation for option -mpower{8,9}-vector and adjust some documentation referring to them. * doc/md.texi: Update documentation for constraint we. * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok. libgcc/ChangeLog: * config/rs6000/t-float128-hw: Replace options -mpower{8,9}-vector with -mcpu=power9. * configure.ac: Update use of option -mpower9-vector with -mcpu=power9. * configure: Regenerate. gcc/testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_powerpc_p8vector_ok): Remove. (check_effective_target_powerpc_p9vector_ok): Remove. (check_p8vector_hw_available): Replace -mpower8-vector with -mcpu=power8. (check_p9vector_hw_available): Replace -mpower9-vector with -mcpu=power9. (check_ppc_float128_hw_available): Likewise. (check_vect_support_and_set_flags): Replace -mpower8-vector with -mcpu=power8, replace -mpower9-vector with -mcpu=power9 or nothing if check_power10_hw_available and place -mcpu=970 first if needed to avoid possible overriding. * g++.target/powerpc/altivec-19.C: Replace powerpc_p9vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-10.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-11.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-6.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-7.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-8.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-9.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-10.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-11.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-5.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-6.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-7.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-8.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-data-class-9.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-0.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-4.c: Likewise. * gcc.target/powerpc/bfp/scalar-test-neg-5.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-0.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-1.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-2.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-exp-3.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-0.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-1.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-2.c: Likewise. * gcc.target/powerpc/bfp/vec-extract-sig-3.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-0.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-1.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-2.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-3.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-4.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-5.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-6.c: Likewise. * gcc.target/powerpc/bfp/vec-insert-exp-7.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-0.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-1.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-2.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-3.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-4.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-5.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-6.c: Likewise. * gcc.target/powerpc/bfp/vec-test-data-class-7.c: Likewise. * gcc.target/powerpc/builtins-3-p9.c: Likewise. * gcc.target/powerpc/byte-in-either-range-0.c: Likewise. * gcc.target/powerpc/byte-in-either-range-1.c: Likewise. * gcc.target/powerpc/byte-in-range-0.c: Likewise. * gcc.target/powerpc/byte-in-range-1.c: Likewise. * gcc.target/powerpc/byte-in-set-0.c: Likewise. * gcc.target/powerpc/byte-in-set-1.c: Likewise. * gcc.target/powerpc/byte-in-set-2.c: Likewise. * gcc.target/powerpc/clone1.c: Likewise. * gcc.target/powerpc/ctz-3.c: Likewise. * gcc.target/powerpc/ctz-4.c: Likewise. * gcc.target/powerpc/darn-0.c: Likewise. * gcc.target/powerpc/darn-1.c: Likewise. * gcc.target/powerpc/darn-2.c: Likewise. * gcc.target/powerpc/dform-3.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-0.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-1.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-10.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-11.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-12.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-13.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-14.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-15.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-16.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-17.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-18.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-19.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-2.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-20.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-21.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-22.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-23.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-24.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-25.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-26.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-27.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-28.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-29.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-3.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-30.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-31.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-32.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-33.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-34.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-35.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-36.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-37.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-38.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-39.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-4.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-40.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-41.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-42.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-43.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-44.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-45.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-46.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-47.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-48.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-49.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-5.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-50.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-51.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-52.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-53.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-54.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-55.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-56.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-57.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-58.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-59.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-6.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-60.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-61.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-62.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-63.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-64.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-65.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-66.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-67.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-68.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-69.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-7.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-70.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-71.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-72.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-73.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-74.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-75.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-76.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-77.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-78.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-79.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-8.c: Likewise. * gcc.target/powerpc/dfp/dtstsfi-9.c: Likewise. * gcc.target/powerpc/direct-move-vector.c: Likewise. * gcc.target/powerpc/float128-type-2.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: Likewise. * gcc.target/powerpc/fold-vec-abs-int.p9.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong.p9.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-char.p9.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-short.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-char.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-float.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-int.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-longlong.p9.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-float-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-int-p9.c: Likewise. * gcc.target/powerpc/fold-vec-insert-short-p9.c: Likewise. * gcc.target/powerpc/fold-vec-mult-int128-p9.c: Likewise. * gcc.target/powerpc/fold-vec-neg-int.p9.c: Likewise. * gcc.target/powerpc/fold-vec-neg-longlong.p9.c: Likewise. * gcc.target/powerpc/p9-dimode1.c: Likewise. * gcc.target/powerpc/p9-dimode2.c: Likewise. * gcc.target/powerpc/p9-extract-1.c: Likewise. * gcc.target/powerpc/p9-extract-2.c: Likewise. * gcc.target/powerpc/p9-extract-3.c: Likewise. * gcc.target/powerpc/p9-extract-4.c: Likewise. * gcc.target/powerpc/p9-fpcvt-1.c: Likewise. * gcc.target/powerpc/p9-fpcvt-2.c: Likewise. * gcc.target/powerpc/p9-fpcvt-3.c: Likewise. * gcc.target/powerpc/p9-lxvx-stxvx-1.c: Likewise. * gcc.target/powerpc/p9-lxvx-stxvx-2.c: Likewise. * gcc.target/powerpc/p9-lxvx-stxvx-3.c: Likewise. * gcc.target/powerpc/p9-minmax-1.c: Likewise. * gcc.target/powerpc/p9-minmax-2.c: Likewise. * gcc.target/powerpc/p9-minmax-3.c: Likewise. * gcc.target/powerpc/p9-novsx.c: Likewise. * gcc.target/powerpc/p9-permute.c: Likewise. * gcc.target/powerpc/p9-sign_extend-runnable.c: Likewise. * gcc.target/powerpc/p9-splat-1.c: Likewise. * gcc.target/powerpc/p9-splat-2.c: Likewise. * gcc.target/powerpc/p9-splat-3.c: Likewise. * gcc.target/powerpc/p9-splat-4.c: Likewise. * gcc.target/powerpc/p9-splat-5.c: Likewise. * gcc.target/powerpc/p9-vbpermd.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-1.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-2.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-3.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-4.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-5.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-6.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-7.c: Likewise. * gcc.target/powerpc/p9-vec-length-epil-8.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-1.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-2.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-3.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-4.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-5.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-6.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-7.c: Likewise. * gcc.target/powerpc/p9-vec-length-full-8.c: Likewise. * gcc.target/powerpc/p9-vneg.c: Likewise. * gcc.target/powerpc/p9-vparity.c: Likewise. * gcc.target/powerpc/p9-vpermr.c: Likewise. * gcc.target/powerpc/p9-xxbr-1.c: Likewise. * gcc.target/powerpc/p9-xxbr-2.c: Likewise. * gcc.target/powerpc/p9-xxbr-3.c: Likewise. * gcc.target/powerpc/ppc-fortran/pr80108-1.f90: Likewise. * gcc.target/powerpc/ppc-round3.c: Likewise. * gcc.target/powerpc/pr103124.c: Likewise. * gcc.target/powerpc/pr104015-1.c: Likewise. * gcc.target/powerpc/pr106769-p9.c: Likewise. * gcc.target/powerpc/pr107412.c: Likewise. * gcc.target/powerpc/pr110429.c: Likewise. * gcc.target/powerpc/pr66144-1.c: Likewise. * gcc.target/powerpc/pr71186.c: Likewise. * gcc.target/powerpc/pr71309.c: Likewise. * gcc.target/powerpc/pr71670.c: Likewise. * gcc.target/powerpc/pr71698.c: Likewise. * gcc.target/powerpc/pr71720.c: Likewise. * gcc.target/powerpc/pr72853.c: Likewise. * gcc.target/powerpc/pr78056-1.c: Likewise. * gcc.target/powerpc/pr78658.c: Likewise. * gcc.target/powerpc/pr78953.c: Likewise. * gcc.target/powerpc/pr79004.c: Likewise. * gcc.target/powerpc/pr79038-1.c: Likewise. * gcc.target/powerpc/pr79179.c: Likewise. * gcc.target/powerpc/pr79251.p9.c: Likewise. * gcc.target/powerpc/pr79799-1.c: Likewise. * gcc.target/powerpc/pr79799-2.c: Likewise. * gcc.target/powerpc/pr79799-3.c: Likewise. * gcc.target/powerpc/pr79799-5.c: Likewise. * gcc.target/powerpc/pr80695-p9.c: Likewise. * gcc.target/powerpc/pr81348.c: Likewise. * gcc.target/powerpc/pr81622.c: Likewise. * gcc.target/powerpc/pr84154-3.c: Likewise. * gcc.target/powerpc/pr90763.c: Likewise. * gcc.target/powerpc/pr96933-1.c: Likewise. * gcc.target/powerpc/sad-vectorize-1.c: Likewise. * gcc.target/powerpc/sad-vectorize-2.c: Likewise. * gcc.target/powerpc/signbit-2.c: Likewise. * gcc.target/powerpc/vadsdu-0.c: Likewise. * gcc.target/powerpc/vadsdu-1.c: Likewise. * gcc.target/powerpc/vadsdu-2.c: Likewise. * gcc.target/powerpc/vadsdu-3.c: Likewise. * gcc.target/powerpc/vadsdu-4.c: Likewise. * gcc.target/powerpc/vadsdu-5.c: Likewise. * gcc.target/powerpc/vadsdub-1.c: Likewise. * gcc.target/powerpc/vadsdub-2.c: Likewise. * gcc.target/powerpc/vadsduh-1.c: Likewise. * gcc.target/powerpc/vadsduh-2.c: Likewise. * gcc.target/powerpc/vadsduw-1.c: Likewise. * gcc.target/powerpc/vadsduw-2.c: Likewise. * gcc.target/powerpc/vec-extract-4.c: Likewise. * gcc.target/powerpc/vec-init-3.c: Likewise. * gcc.target/powerpc/vec-minmax-1.c: Likewise. * gcc.target/powerpc/vec-minmax-2.c: Likewise. * gcc.target/powerpc/vec-set-char.c: Likewise. * gcc.target/powerpc/vec-set-int.c: Likewise. * gcc.target/powerpc/vec-set-short.c: Likewise. * gcc.target/powerpc/vec_reve_2.c: Likewise. * gcc.target/powerpc/vector_float.c: Likewise. * gcc.target/powerpc/vslv-0.c: Likewise. * gcc.target/powerpc/vslv-1.c: Likewise. * gcc.target/powerpc/vsrv-0.c: Likewise. * gcc.target/powerpc/vsrv-1.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-0.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-1.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-10.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-11.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-12.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-13.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-14.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-2.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-3.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-4.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-5.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-6.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-7.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-8.c: Likewise. * gcc.target/powerpc/vsu/vec-all-ne-9.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-1.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-2.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-3.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-4.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-5.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-6.c: Likewise. * gcc.target/powerpc/vsu/vec-all-nez-7.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-0.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-1.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-10.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-11.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-12.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-13.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-14.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-2.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-3.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-4.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-5.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-6.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-7.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-8.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eq-9.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-1.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-2.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-3.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-4.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-5.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-6.c: Likewise. * gcc.target/powerpc/vsu/vec-any-eqz-7.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-0.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-4.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-5.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-6.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-8.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpne-9.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-4.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-5.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-6.c: Likewise. * gcc.target/powerpc/vsu/vec-cmpnez-7.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-10.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-11.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-12.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-13.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-8.c: Likewise. * gcc.target/powerpc/vsu/vec-xl-len-9.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xlx-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xrx-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-0.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-1.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-10.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-11.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-12.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-13.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-2.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-3.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-4.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-5.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-6.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-7.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-8.c: Likewise. * gcc.target/powerpc/vsu/vec-xst-len-9.c: Likewise. * gcc.target/powerpc/vsx-builtin-msum.c: Likewise. * gcc.target/powerpc/vsx-himode.c: Likewise. * gcc.target/powerpc/vsx-himode2.c: Likewise. * gcc.target/powerpc/vsx-himode3.c: Likewise. * gcc.target/powerpc/vsx-qimode.c: Likewise. * gcc.target/powerpc/vsx-qimode2.c: Likewise. * gcc.target/powerpc/vsx-qimode3.c: Likewise. * g++.target/powerpc/pr65240-1.C: Replace powerpc_p8vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * g++.target/powerpc/pr65240-2.C: Likewise. * g++.target/powerpc/pr65240-3.C: Likewise. * g++.target/powerpc/pr65242.C: Likewise. * g++.target/powerpc/pr67211.C: Likewise. * g++.target/powerpc/pr71294.C: Likewise. * g++.target/powerpc/pr84279.C: Likewise. * g++.target/powerpc/pr93974.C: Likewise. * gcc.target/powerpc/atomic-p8.c: Likewise. * gcc.target/powerpc/atomic_load_store-p8.c: Likewise. * gcc.target/powerpc/bcd-2.c: Likewise. * gcc.target/powerpc/bcd-3.c: Likewise. * gcc.target/powerpc/bool2-p8.c: Likewise. * gcc.target/powerpc/bool3-p8.c: Likewise. * gcc.target/powerpc/builtins-1.c: Likewise. * gcc.target/powerpc/builtins-3-p8.c: Likewise. * gcc.target/powerpc/builtins-5.c: Likewise. * gcc.target/powerpc/builtins-9.c: Likewise. * gcc.target/powerpc/crypto-builtin-1.c: Likewise. * gcc.target/powerpc/crypto-builtin-2.c: Likewise. * gcc.target/powerpc/direct-move-double1.c: Likewise. * gcc.target/powerpc/direct-move-float1.c: Likewise. * gcc.target/powerpc/direct-move-long1.c: Likewise. * gcc.target/powerpc/direct-move-vint1.c: Likewise. * gcc.target/powerpc/float128-type-1.c: Likewise. * gcc.target/powerpc/fold-vec-extract-char.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-double.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-longlong.p8.c: Likewise. * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-char-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-float-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-int-p8.c: Likewise. * gcc.target/powerpc/fold-vec-insert-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-insert-short-p8.c: Likewise. * gcc.target/powerpc/fold-vec-neg-char.c: Likewise. * gcc.target/powerpc/fold-vec-neg-floatdouble.c: Likewise. * gcc.target/powerpc/fold-vec-neg-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-neg-short.c: Likewise. * gcc.target/powerpc/fold-vec-select-double.c: Likewise. * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c: Likewise. * gcc.target/powerpc/fusion.c: Likewise. * gcc.target/powerpc/fusion2.c: Likewise. * gcc.target/powerpc/mul-vectorize-1.c: Likewise. * gcc.target/powerpc/p8-vec-xl-xst-v2.c: Likewise. * gcc.target/powerpc/p8-vec-xl-xst.c: Likewise. * gcc.target/powerpc/p8vector-builtin-1.c: Likewise. * gcc.target/powerpc/p8vector-builtin-2.c: Likewise. * gcc.target/powerpc/p8vector-builtin-3.c: Likewise. * gcc.target/powerpc/p8vector-builtin-4.c: Likewise. * gcc.target/powerpc/p8vector-builtin-5.c: Likewise. * gcc.target/powerpc/p8vector-builtin-6.c: Likewise. * gcc.target/powerpc/p8vector-builtin-7.c: Likewise. * gcc.target/powerpc/p8vector-fp.c: Likewise. * gcc.target/powerpc/p8vector-int128-1.c: Likewise. * gcc.target/powerpc/p8vector-ldst.c: Likewise. * gcc.target/powerpc/p8vector-vbpermq.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-1.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-2.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-3.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-4.c: Likewise. * gcc.target/powerpc/p8vector-vectorize-5.c: Likewise. * gcc.target/powerpc/ppc-round2.c: Likewise. * gcc.target/powerpc/pr100866-1.c: Likewise. * gcc.target/powerpc/pr100866-2.c: Likewise. * gcc.target/powerpc/pr104239-1.c: Likewise. * gcc.target/powerpc/pr104239-2.c: Likewise. * gcc.target/powerpc/pr104239-3.c: Likewise. * gcc.target/powerpc/pr106769-p8.c: Likewise. * gcc.target/powerpc/pr108396.c: Likewise. * gcc.target/powerpc/pr111449-1.c: Likewise. * gcc.target/powerpc/pr57744.c: Likewise. * gcc.target/powerpc/pr58673-1.c: Likewise. * gcc.target/powerpc/pr58673-2.c: Likewise. * gcc.target/powerpc/pr60137.c: Likewise. * gcc.target/powerpc/pr60203.c: Likewise. * gcc.target/powerpc/pr66144-2.c: Likewise. * gcc.target/powerpc/pr66144-3.c: Likewise. * gcc.target/powerpc/pr68163.c: Likewise. * gcc.target/powerpc/pr69548.c: Likewise. * gcc.target/powerpc/pr70669.c: Likewise. * gcc.target/powerpc/pr71977-1.c: Likewise. * gcc.target/powerpc/pr71977-2.c: Likewise. * gcc.target/powerpc/pr72717.c: Likewise. * gcc.target/powerpc/pr78056-3.c: Likewise. * gcc.target/powerpc/pr78056-4.c: Likewise. * gcc.target/powerpc/pr78102.c: Likewise. * gcc.target/powerpc/pr78543.c: Likewise. * gcc.target/powerpc/pr78604.c: Likewise. * gcc.target/powerpc/pr79251.p8.c: Likewise. * gcc.target/powerpc/pr79354.c: Likewise. * gcc.target/powerpc/pr79544.c: Likewise. * gcc.target/powerpc/pr79907.c: Likewise. * gcc.target/powerpc/pr79951.c: Likewise. * gcc.target/powerpc/pr80315-1.c: Likewise. * gcc.target/powerpc/pr80315-2.c: Likewise. * gcc.target/powerpc/pr80315-3.c: Likewise. * gcc.target/powerpc/pr80315-4.c: Likewise. * gcc.target/powerpc/pr80510-2.c: Likewise. * gcc.target/powerpc/pr80695-p8.c: Likewise. * gcc.target/powerpc/pr80718.c: Likewise. * gcc.target/powerpc/pr84154-2.c: Likewise. * gcc.target/powerpc/pr88558-p8.c: Likewise. * gcc.target/powerpc/pr88845.c: Likewise. * gcc.target/powerpc/pr91903.c: Likewise. * gcc.target/powerpc/pr92923-2.c: Likewise. * gcc.target/powerpc/pr96933-2.c: Likewise. * gcc.target/powerpc/pr97019.c: Likewise. * gcc.target/powerpc/pragma_power8.c: Likewise. * gcc.target/powerpc/signbit-1.c: Likewise. * gcc.target/powerpc/swaps-p8-1.c: Likewise. * gcc.target/powerpc/swaps-p8-12.c: Likewise. * gcc.target/powerpc/swaps-p8-14.c: Likewise. * gcc.target/powerpc/swaps-p8-15.c: Likewise. * gcc.target/powerpc/swaps-p8-16.c: Likewise. * gcc.target/powerpc/swaps-p8-17.c: Likewise. * gcc.target/powerpc/swaps-p8-18.c: Likewise. * gcc.target/powerpc/swaps-p8-19.c: Likewise. * gcc.target/powerpc/swaps-p8-2.c: Likewise. * gcc.target/powerpc/swaps-p8-22.c: Likewise. * gcc.target/powerpc/swaps-p8-23.c: Likewise. * gcc.target/powerpc/swaps-p8-24.c: Likewise. * gcc.target/powerpc/swaps-p8-25.c: Likewise. * gcc.target/powerpc/swaps-p8-26.c: Likewise. * gcc.target/powerpc/swaps-p8-27.c: Likewise. * gcc.target/powerpc/swaps-p8-3.c: Likewise. * gcc.target/powerpc/swaps-p8-30.c: Likewise. * gcc.target/powerpc/swaps-p8-33.c: Likewise. * gcc.target/powerpc/swaps-p8-36.c: Likewise. * gcc.target/powerpc/swaps-p8-39.c: Likewise. * gcc.target/powerpc/swaps-p8-4.c: Likewise. * gcc.target/powerpc/swaps-p8-42.c: Likewise. * gcc.target/powerpc/swaps-p8-45.c: Likewise. * gcc.target/powerpc/swaps-p8-46.c: Likewise. * gcc.target/powerpc/swaps-p8-5.c: Likewise. * gcc.target/powerpc/unpack-vectorize-3.c: Likewise. * gcc.target/powerpc/upper-regs-sf.c: Likewise. * gcc.target/powerpc/vec-cmp.c: Likewise. * gcc.target/powerpc/vec-extract-1.c: Likewise. * gcc.target/powerpc/vec-extract-3.c: Likewise. * gcc.target/powerpc/vec-extract-5.c: Likewise. * gcc.target/powerpc/vec-extract-6.c: Likewise. * gcc.target/powerpc/vec-extract-7.c: Likewise. * gcc.target/powerpc/vec-extract-8.c: Likewise. * gcc.target/powerpc/vec-extract-9.c: Likewise. * gcc.target/powerpc/vec-init-10.c: Likewise. * gcc.target/powerpc/vec-init-6.c: Likewise. * gcc.target/powerpc/vec-init-7.c: Likewise. * gcc.target/powerpc/vsx-extract-3.c: Likewise. * gcc.target/powerpc/vsx-extract-4.c: Likewise. * gcc.target/powerpc/vsx-extract-5.c: Likewise. * gcc.target/powerpc/vsx-simode.c: Likewise. * gcc.target/powerpc/vsx-simode2.c: Likewise. * gcc.target/powerpc/vsx-simode3.c: Likewise. * gcc.target/powerpc/builtins-4-int128-runnable.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, replace -mpower8-vector with -mvsx, and add dg-additional-options -mdejagnu-cpu=power8 if !has_arch_pwr8. * gcc.target/powerpc/builtins-mergew-mergow.c: Likewise. * gcc.target/powerpc/direct-move-float3.c: Likewise. * gcc.target/powerpc/divkc3-2.c: Likewise. * gcc.target/powerpc/divkc3-3.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-add-4.c: Likewise. * gcc.target/powerpc/fold-vec-add-7.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-int.h: Likewise. * gcc.target/powerpc/fold-vec-cmp-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-short.h: Likewise. * gcc.target/powerpc/fold-vec-cntlz-char.c: Likewise. * gcc.target/powerpc/fold-vec-cntlz-int.c: Likewise. * gcc.target/powerpc/fold-vec-cntlz-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-cntlz-short.c: Likewise. * gcc.target/powerpc/fold-vec-ld-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-char.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-float.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-int.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-eqv-short.c: Likewise. * gcc.target/powerpc/fold-vec-logical-ors-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-char.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-int.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-logical-other-short.c: Likewise. * gcc.target/powerpc/fold-vec-mergehl-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-minmax-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-mult-int.c: Likewise. * gcc.target/powerpc/fold-vec-mult-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-neg-int.c: Likewise. * gcc.target/powerpc/fold-vec-neg-longlong.h: Likewise. * gcc.target/powerpc/fold-vec-pack-double.c: Likewise. * gcc.target/powerpc/fold-vec-pack-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c: Likewise. * gcc.target/powerpc/fold-vec-shift-left-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-shift-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-st-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-sub-int128.c: Likewise. * gcc.target/powerpc/fold-vec-sub-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-unpack-float.c: Likewise. * gcc.target/powerpc/fold-vec-unpack-int.c: Likewise. * gcc.target/powerpc/mmx-packs.c: Likewise. * gcc.target/powerpc/mmx-packssdw-1.c: Likewise. * gcc.target/powerpc/mmx-packsswb-1.c: Likewise. * gcc.target/powerpc/mmx-packuswb-1.c: Likewise. * gcc.target/powerpc/mmx-paddb-1.c: Likewise. * gcc.target/powerpc/mmx-paddd-1.c: Likewise. * gcc.target/powerpc/mmx-paddsb-1.c: Likewise. * gcc.target/powerpc/mmx-paddsw-1.c: Likewise. * gcc.target/powerpc/mmx-paddusb-1.c: Likewise. * gcc.target/powerpc/mmx-paddusw-1.c: Likewise. * gcc.target/powerpc/mmx-paddw-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpeqb-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpeqd-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpeqw-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpgtb-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpgtd-1.c: Likewise. * gcc.target/powerpc/mmx-pcmpgtw-1.c: Likewise. * gcc.target/powerpc/mmx-pmaddwd-1.c: Likewise. * gcc.target/powerpc/mmx-pmulhw-1.c: Likewise. * gcc.target/powerpc/mmx-pmullw-1.c: Likewise. * gcc.target/powerpc/mmx-pslld-1.c: Likewise. * gcc.target/powerpc/mmx-psllw-1.c: Likewise. * gcc.target/powerpc/mmx-psrad-1.c: Likewise. * gcc.target/powerpc/mmx-psraw-1.c: Likewise. * gcc.target/powerpc/mmx-psrld-1.c: Likewise. * gcc.target/powerpc/mmx-psrlw-1.c: Likewise. * gcc.target/powerpc/mmx-psubb-2.c: Likewise. * gcc.target/powerpc/mmx-psubd-2.c: Likewise. * gcc.target/powerpc/mmx-psubsb-1.c: Likewise. * gcc.target/powerpc/mmx-psubsw-1.c: Likewise. * gcc.target/powerpc/mmx-psubusb-1.c: Likewise. * gcc.target/powerpc/mmx-psubusw-1.c: Likewise. * gcc.target/powerpc/mmx-psubw-2.c: Likewise. * gcc.target/powerpc/mmx-punpckhbw-1.c: Likewise. * gcc.target/powerpc/mmx-punpckhdq-1.c: Likewise. * gcc.target/powerpc/mmx-punpckhwd-1.c: Likewise. * gcc.target/powerpc/mmx-punpcklbw-1.c: Likewise. * gcc.target/powerpc/mmx-punpckldq-1.c: Likewise. * gcc.target/powerpc/mmx-punpcklwd-1.c: Likewise. * gcc.target/powerpc/mulkc3-2.c: Likewise. * gcc.target/powerpc/mulkc3-3.c: Likewise. * gcc.target/powerpc/p8vector-builtin-8.c: Likewise. * gcc.target/powerpc/pr37191.c: Likewise. * gcc.target/powerpc/pr83862.c: Likewise. * gcc.target/powerpc/pr84154-1.c: Likewise. * gcc.target/powerpc/pr84220-sld2.c: Likewise. * gcc.target/powerpc/pr85456.c: Likewise. * gcc.target/powerpc/pr86731-longlong.c: Likewise. * gcc.target/powerpc/sse-addps-1.c: Likewise. * gcc.target/powerpc/sse-addss-1.c: Likewise. * gcc.target/powerpc/sse-andnps-1.c: Likewise. * gcc.target/powerpc/sse-andps-1.c: Likewise. * gcc.target/powerpc/sse-cmpss-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi16ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi32ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi32x2ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi8ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpspi16-1.c: Likewise. * gcc.target/powerpc/sse-cvtpspi8-1.c: Likewise. * gcc.target/powerpc/sse-cvtpu16ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpu8ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtsi2ss-1.c: Likewise. * gcc.target/powerpc/sse-cvtsi2ss-2.c: Likewise. * gcc.target/powerpc/sse-cvtss2si-1.c: Likewise. * gcc.target/powerpc/sse-cvtss2si-2.c: Likewise. * gcc.target/powerpc/sse-cvttss2si-1.c: Likewise. * gcc.target/powerpc/sse-cvttss2si-2.c: Likewise. * gcc.target/powerpc/sse-divps-1.c: Likewise. * gcc.target/powerpc/sse-divss-1.c: Likewise. * gcc.target/powerpc/sse-maxps-1.c: Likewise. * gcc.target/powerpc/sse-maxps-2.c: Likewise. * gcc.target/powerpc/sse-maxss-1.c: Likewise. * gcc.target/powerpc/sse-minps-1.c: Likewise. * gcc.target/powerpc/sse-minps-2.c: Likewise. * gcc.target/powerpc/sse-minss-1.c: Likewise. * gcc.target/powerpc/sse-movaps-1.c: Likewise. * gcc.target/powerpc/sse-movaps-2.c: Likewise. * gcc.target/powerpc/sse-movhlps-1.c: Likewise. * gcc.target/powerpc/sse-movhps-1.c: Likewise. * gcc.target/powerpc/sse-movhps-2.c: Likewise. * gcc.target/powerpc/sse-movlhps-1.c: Likewise. * gcc.target/powerpc/sse-movlps-1.c: Likewise. * gcc.target/powerpc/sse-movlps-2.c: Likewise. * gcc.target/powerpc/sse-movmskb-1.c: Likewise. * gcc.target/powerpc/sse-movmskps-1.c: Likewise. * gcc.target/powerpc/sse-movss-1.c: Likewise. * gcc.target/powerpc/sse-movss-2.c: Likewise. * gcc.target/powerpc/sse-movss-3.c: Likewise. * gcc.target/powerpc/sse-mulps-1.c: Likewise. * gcc.target/powerpc/sse-mulss-1.c: Likewise. * gcc.target/powerpc/sse-orps-1.c: Likewise. * gcc.target/powerpc/sse-pavgw-1.c: Likewise. * gcc.target/powerpc/sse-pmaxsw-1.c: Likewise. * gcc.target/powerpc/sse-pmaxub-1.c: Likewise. * gcc.target/powerpc/sse-pminsw-1.c: Likewise. * gcc.target/powerpc/sse-pminub-1.c: Likewise. * gcc.target/powerpc/sse-pmulhuw-1.c: Likewise. * gcc.target/powerpc/sse-psadbw-1.c: Likewise. * gcc.target/powerpc/sse-rcpps-1.c: Likewise. * gcc.target/powerpc/sse-rsqrtps-1.c: Likewise. * gcc.target/powerpc/sse-shufps-1.c: Likewise. * gcc.target/powerpc/sse-sqrtps-1.c: Likewise. * gcc.target/powerpc/sse-subps-1.c: Likewise. * gcc.target/powerpc/sse-subss-1.c: Likewise. * gcc.target/powerpc/sse-ucomiss-1.c: Likewise. * gcc.target/powerpc/sse-ucomiss-2.c: Likewise. * gcc.target/powerpc/sse-ucomiss-3.c: Likewise. * gcc.target/powerpc/sse-ucomiss-4.c: Likewise. * gcc.target/powerpc/sse-ucomiss-5.c: Likewise. * gcc.target/powerpc/sse-ucomiss-6.c: Likewise. * gcc.target/powerpc/sse-unpckhps-1.c: Likewise. * gcc.target/powerpc/sse-unpcklps-1.c: Likewise. * gcc.target/powerpc/sse-xorps-1.c: Likewise. * gcc.target/powerpc/sse2-addpd-1.c: Likewise. * gcc.target/powerpc/sse2-addsd-1.c: Likewise. * gcc.target/powerpc/sse2-andnpd-1.c: Likewise. * gcc.target/powerpc/sse2-andpd-1.c: Likewise. * gcc.target/powerpc/sse2-cmppd-1.c: Likewise. * gcc.target/powerpc/sse2-cmpsd-1.c: Likewise. * gcc.target/powerpc/sse2-comisd-1.c: Likewise. * gcc.target/powerpc/sse2-comisd-2.c: Likewise. * gcc.target/powerpc/sse2-comisd-3.c: Likewise. * gcc.target/powerpc/sse2-comisd-4.c: Likewise. * gcc.target/powerpc/sse2-comisd-5.c: Likewise. * gcc.target/powerpc/sse2-comisd-6.c: Likewise. * gcc.target/powerpc/sse2-cvtdq2pd-1.c: Likewise. * gcc.target/powerpc/sse2-cvtdq2ps-1.c: Likewise. * gcc.target/powerpc/sse2-cvtpd2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvtpd2ps-1.c: Likewise. * gcc.target/powerpc/sse2-cvtps2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvtps2pd-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsd2si-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsd2si-2.c: Likewise. * gcc.target/powerpc/sse2-cvtsd2ss-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsi2sd-1.c: Likewise. * gcc.target/powerpc/sse2-cvtsi2sd-2.c: Likewise. * gcc.target/powerpc/sse2-cvtss2sd-1.c: Likewise. * gcc.target/powerpc/sse2-cvttpd2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvttps2dq-1.c: Likewise. * gcc.target/powerpc/sse2-cvttsd2si-1.c: Likewise. * gcc.target/powerpc/sse2-cvttsd2si-2.c: Likewise. * gcc.target/powerpc/sse2-divpd-1.c: Likewise. * gcc.target/powerpc/sse2-divsd-1.c: Likewise. * gcc.target/powerpc/sse2-maxpd-1.c: Likewise. * gcc.target/powerpc/sse2-maxsd-1.c: Likewise. * gcc.target/powerpc/sse2-minpd-1.c: Likewise. * gcc.target/powerpc/sse2-minsd-1.c: Likewise. * gcc.target/powerpc/sse2-mmx.c: Likewise. * gcc.target/powerpc/sse2-movhpd-1.c: Likewise. * gcc.target/powerpc/sse2-movhpd-2.c: Likewise. * gcc.target/powerpc/sse2-movlpd-1.c: Likewise. * gcc.target/powerpc/sse2-movlpd-2.c: Likewise. * gcc.target/powerpc/sse2-movmskpd-1.c: Likewise. * gcc.target/powerpc/sse2-movq-1.c: Likewise. * gcc.target/powerpc/sse2-movq-2.c: Likewise. * gcc.target/powerpc/sse2-movq-3.c: Likewise. * gcc.target/powerpc/sse2-movsd-1.c: Likewise. * gcc.target/powerpc/sse2-movsd-2.c: Likewise. * gcc.target/powerpc/sse2-movsd-3.c: Likewise. * gcc.target/powerpc/sse2-mulpd-1.c: Likewise. * gcc.target/powerpc/sse2-mulsd-1.c: Likewise. * gcc.target/powerpc/sse2-orpd-1.c: Likewise. * gcc.target/powerpc/sse2-packssdw-1.c: Likewise. * gcc.target/powerpc/sse2-packsswb-1.c: Likewise. * gcc.target/powerpc/sse2-packuswb-1.c: Likewise. * gcc.target/powerpc/sse2-paddb-1.c: Likewise. * gcc.target/powerpc/sse2-paddd-1.c: Likewise. * gcc.target/powerpc/sse2-paddq-1.c: Likewise. * gcc.target/powerpc/sse2-paddsb-1.c: Likewise. * gcc.target/powerpc/sse2-paddsw-1.c: Likewise. * gcc.target/powerpc/sse2-paddusb-1.c: Likewise. * gcc.target/powerpc/sse2-paddusw-1.c: Likewise. * gcc.target/powerpc/sse2-paddw-1.c: Likewise. * gcc.target/powerpc/sse2-pand-1.c: Likewise. * gcc.target/powerpc/sse2-pandn-1.c: Likewise. * gcc.target/powerpc/sse2-pavgb-1.c: Likewise. * gcc.target/powerpc/sse2-pavgw-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpeqb-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpeqd-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpeqw-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpgtb-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpgtd-1.c: Likewise. * gcc.target/powerpc/sse2-pcmpgtw-1.c: Likewise. * gcc.target/powerpc/sse2-pextrw.c: Likewise. * gcc.target/powerpc/sse2-pinsrw.c: Likewise. * gcc.target/powerpc/sse2-pmaddwd-1.c: Likewise. * gcc.target/powerpc/sse2-pmaxsw-1.c: Likewise. * gcc.target/powerpc/sse2-pmaxub-1.c: Likewise. * gcc.target/powerpc/sse2-pminsw-1.c: Likewise. * gcc.target/powerpc/sse2-pminub-1.c: Likewise. * gcc.target/powerpc/sse2-pmovmskb-1.c: Likewise. * gcc.target/powerpc/sse2-pmulhuw-1.c: Likewise. * gcc.target/powerpc/sse2-pmulhw-1.c: Likewise. * gcc.target/powerpc/sse2-pmullw-1.c: Likewise. * gcc.target/powerpc/sse2-pmuludq-1.c: Likewise. * gcc.target/powerpc/sse2-por-1.c: Likewise. * gcc.target/powerpc/sse2-psadbw-1.c: Likewise. * gcc.target/powerpc/sse2-pshufd-1.c: Likewise. * gcc.target/powerpc/sse2-pshufhw-1.c: Likewise. * gcc.target/powerpc/sse2-pshuflw-1.c: Likewise. * gcc.target/powerpc/sse2-pslld-1.c: Likewise. * gcc.target/powerpc/sse2-pslld-2.c: Likewise. * gcc.target/powerpc/sse2-pslldq-1.c: Likewise. * gcc.target/powerpc/sse2-psllq-1.c: Likewise. * gcc.target/powerpc/sse2-psllq-2.c: Likewise. * gcc.target/powerpc/sse2-psllw-1.c: Likewise. * gcc.target/powerpc/sse2-psllw-2.c: Likewise. * gcc.target/powerpc/sse2-psrad-1.c: Likewise. * gcc.target/powerpc/sse2-psrad-2.c: Likewise. * gcc.target/powerpc/sse2-psraw-1.c: Likewise. * gcc.target/powerpc/sse2-psraw-2.c: Likewise. * gcc.target/powerpc/sse2-psrld-1.c: Likewise. * gcc.target/powerpc/sse2-psrld-2.c: Likewise. * gcc.target/powerpc/sse2-psrldq-1.c: Likewise. * gcc.target/powerpc/sse2-psrlq-1.c: Likewise. * gcc.target/powerpc/sse2-psrlq-2.c: Likewise. * gcc.target/powerpc/sse2-psrlw-1.c: Likewise. * gcc.target/powerpc/sse2-psrlw-2.c: Likewise. * gcc.target/powerpc/sse2-psubb-1.c: Likewise. * gcc.target/powerpc/sse2-psubd-1.c: Likewise. * gcc.target/powerpc/sse2-psubq-1.c: Likewise. * gcc.target/powerpc/sse2-psubsb-1.c: Likewise. * gcc.target/powerpc/sse2-psubsw-1.c: Likewise. * gcc.target/powerpc/sse2-psubusb-1.c: Likewise. * gcc.target/powerpc/sse2-psubusw-1.c: Likewise. * gcc.target/powerpc/sse2-psubw-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhbw-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhdq-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhqdq-1.c: Likewise. * gcc.target/powerpc/sse2-punpckhwd-1.c: Likewise. * gcc.target/powerpc/sse2-punpcklbw-1.c: Likewise. * gcc.target/powerpc/sse2-punpckldq-1.c: Likewise. * gcc.target/powerpc/sse2-punpcklqdq-1.c: Likewise. * gcc.target/powerpc/sse2-punpcklwd-1.c: Likewise. * gcc.target/powerpc/sse2-pxor-1.c: Likewise. * gcc.target/powerpc/sse2-shufpd-1.c: Likewise. * gcc.target/powerpc/sse2-sqrtpd-1.c: Likewise. * gcc.target/powerpc/sse2-subpd-1.c: Likewise. * gcc.target/powerpc/sse2-subsd-1.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-1.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-2.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-3.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-4.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-5.c: Likewise. * gcc.target/powerpc/sse2-ucomisd-6.c: Likewise. * gcc.target/powerpc/sse2-unpckhpd-1.c: Likewise. * gcc.target/powerpc/sse2-unpcklpd-1.c: Likewise. * gcc.target/powerpc/sse2-xorpd-1.c: Likewise. * gcc.target/powerpc/sse3-addsubpd.c: Likewise. * gcc.target/powerpc/sse3-addsubps.c: Likewise. * gcc.target/powerpc/sse3-haddpd.c: Likewise. * gcc.target/powerpc/sse3-haddps.c: Likewise. * gcc.target/powerpc/sse3-hsubpd.c: Likewise. * gcc.target/powerpc/sse3-hsubps.c: Likewise. * gcc.target/powerpc/sse3-lddqu.c: Likewise. * gcc.target/powerpc/sse3-movddup.c: Likewise. * gcc.target/powerpc/sse3-movshdup.c: Likewise. * gcc.target/powerpc/sse3-movsldup.c: Likewise. * gcc.target/powerpc/sse4_1-blendpd.c: Likewise. * gcc.target/powerpc/sse4_1-blendps-2.c: Likewise. * gcc.target/powerpc/sse4_1-blendps.c: Likewise. * gcc.target/powerpc/sse4_1-blendvpd.c: Likewise. * gcc.target/powerpc/sse4_1-blendvps.c: Likewise. * gcc.target/powerpc/sse4_1-ceilpd.c: Likewise. * gcc.target/powerpc/sse4_1-ceilps.c: Likewise. * gcc.target/powerpc/sse4_1-ceilsd.c: Likewise. * gcc.target/powerpc/sse4_1-ceilss.c: Likewise. * gcc.target/powerpc/sse4_1-floorpd.c: Likewise. * gcc.target/powerpc/sse4_1-floorps.c: Likewise. * gcc.target/powerpc/sse4_1-floorsd.c: Likewise. * gcc.target/powerpc/sse4_1-floorss.c: Likewise. * gcc.target/powerpc/sse4_1-pblendvb.c: Likewise. * gcc.target/powerpc/sse4_1-pblendw-2.c: Likewise. * gcc.target/powerpc/sse4_1-pblendw.c: Likewise. * gcc.target/powerpc/sse4_1-pcmpeqq.c: Likewise. * gcc.target/powerpc/sse4_1-pinsrb.c: Likewise. * gcc.target/powerpc/sse4_1-pinsrd.c: Likewise. * gcc.target/powerpc/sse4_1-pinsrq.c: Likewise. * gcc.target/powerpc/sse4_1-pmovsxbq.c: Likewise. * gcc.target/powerpc/sse4_1-pmovsxdq.c: Likewise. * gcc.target/powerpc/sse4_1-pmovsxwq.c: Likewise. * gcc.target/powerpc/sse4_1-pmuldq.c: Likewise. * gcc.target/powerpc/sse4_1-ptest-1.c: Likewise. * gcc.target/powerpc/sse4_1-roundpd-2.c: Likewise. * gcc.target/powerpc/sse4_1-roundpd-3.c: Likewise. * gcc.target/powerpc/sse4_2-pcmpgtq.c: Likewise. * gcc.target/powerpc/ssse3-pabsb.c: Likewise. * gcc.target/powerpc/ssse3-pabsd.c: Likewise. * gcc.target/powerpc/ssse3-pabsw.c: Likewise. * gcc.target/powerpc/ssse3-palignr.c: Likewise. * gcc.target/powerpc/ssse3-phaddd.c: Likewise. * gcc.target/powerpc/ssse3-phaddsw.c: Likewise. * gcc.target/powerpc/ssse3-phaddw.c: Likewise. * gcc.target/powerpc/ssse3-phsubd.c: Likewise. * gcc.target/powerpc/ssse3-phsubsw.c: Likewise. * gcc.target/powerpc/ssse3-phsubw.c: Likewise. * gcc.target/powerpc/ssse3-pmaddubsw.c: Likewise. * gcc.target/powerpc/ssse3-pmulhrsw.c: Likewise. * gcc.target/powerpc/ssse3-pshufb.c: Likewise. * gcc.target/powerpc/ssse3-psignb.c: Likewise. * gcc.target/powerpc/ssse3-psignd.c: Likewise. * gcc.target/powerpc/ssse3-psignw.c: Likewise. * gcc.target/powerpc/vec-cmp-sel.c: Likewise. * gcc.target/powerpc/vec-sld-modulo.c: Likewise. * gcc.target/powerpc/vec-srad-modulo.c: Likewise. * gcc.target/powerpc/vec-srd-modulo.c: Likewise. * gcc.target/powerpc/amo1.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok, replace -mpower9-vector with -mvsx, and add dg-additional-options -mdejagnu-cpu=power9 if !has_arch_pwr9. * gcc.target/powerpc/amo2.c: Likewise. * gcc.target/powerpc/dform-1.c: Likewise. * gcc.target/powerpc/dform-2.c: Likewise. * gcc.target/powerpc/float128-5.c: Likewise. * gcc.target/powerpc/float128-complex-2.c: Likewise. * gcc.target/powerpc/float128-fma1.c: Likewise. * gcc.target/powerpc/float128-hw.c: Likewise. * gcc.target/powerpc/float128-hw10.c: Likewise. * gcc.target/powerpc/float128-hw11.c: Likewise. * gcc.target/powerpc/float128-hw2.c: Likewise. * gcc.target/powerpc/float128-hw3.c: Likewise. * gcc.target/powerpc/float128-hw4.c: Likewise. * gcc.target/powerpc/float128-hw5.c: Likewise. * gcc.target/powerpc/float128-hw6.c: Likewise. * gcc.target/powerpc/float128-hw7.c: Likewise. * gcc.target/powerpc/float128-hw8.c: Likewise. * gcc.target/powerpc/float128-hw9.c: Likewise. * gcc.target/powerpc/float128-minmax.c: Likewise. * gcc.target/powerpc/float128-odd.c: Likewise. * gcc.target/powerpc/float128-sqrt1.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-int.p9.c: Likewise. * gcc.target/powerpc/gnuattr2.c: Likewise. * gcc.target/powerpc/pr71656-1.c: Likewise. * gcc.target/powerpc/pr71656-2.c: Likewise. * gcc.target/powerpc/pr81959.c: Likewise. * gcc.target/powerpc/pr82748-1.c: Likewise. * gcc.target/powerpc/pr82748-2.c: Likewise. * gcc.target/powerpc/pr111449-2.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok. * gcc.target/powerpc/pr98914.c: Likewise. * gcc.target/powerpc/versioned-copy-loop.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * gcc.target/powerpc/clone2.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok. * gcc.target/powerpc/p9-options-1.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok, replace -mno-power9-vector with -mno-vsx. * gcc.target/powerpc/pr84226.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * g++.dg/pr69667.C: Replace powerpc_p8vector_ok with powerpc_vsx_ok and append -mvsx to dg-options. * gcc.dg/vect/costmodel/ppc/costmodel-slp-perm.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok and replace -mpower9-vector with -mvsx. * gcc.dg/vect/pr109011-1.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, and replace -mpower8-vector with -mdejagnu-cpu=power8 -mvsx or -mvsx under different conditions. * gcc.dg/vect/pr109011-2.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok, and replace -mpower9-vector with -mdejagnu-cpu=power9 -mvsx or -mvsx under different conditions. * gcc.dg/vect/pr109011-4.c: Likewise. * gcc.dg/vect/pr109011-3.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, and replace -mpower8-vector -mno-power9-vector with -mdejagnu-cpu=power8 -mvsx. * gcc.dg/vect/pr109011-5.c: Likewise. * gcc.target/powerpc/altivec-35.c: Remove -mno-power8-vector. * gcc.target/powerpc/vsx-vector-7.c: Replace -mno-power8-vector with -mdejagnu-cpu=power7. * gcc.dg/vect/O3-pr70130.c: Replace -mcpu=power7 with options -mdejagnu-cpu=power7 -mvsx and remove option -mno-power9-vector -mno-power8-vector. * gfortran.dg/vect/pr45714-b.f: Likewise. * gcc.dg/vect/pr48765.c: Remove dg-skip-if and replace -mcpu=power7 with option -mdejagnu-cpu=power6. * gcc.target/powerpc/pr78056-2.c: Likewise. * gcc.target/powerpc/altivec-2-runnable.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, remove -mpower8-vector and add dg-additional-options -mdejagnu-cpu=power8 if !has_arch_pwr8. * gcc.target/powerpc/altivec-37.c: Likewise. * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok and replace -mpower8-vector with -mvsx. * gcc.target/powerpc/fold-vec-abs-longlong.p8.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-char.p8.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-int.p8.c: Likewise. * gcc.target/powerpc/fold-vec-cmp-short.p8.c: Likewise. * gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c: Likewise. * gcc.target/powerpc/fold-vec-mergeeo-int.c: Likewise. * gcc.target/powerpc/fold-vec-mergeeo-longlong.c: Likewise. * gcc.target/powerpc/fold-vec-mult-int128-p8.c: Likewise. * gcc.target/powerpc/fold-vec-neg-longlong.p8.c: Likewise. * gcc.target/powerpc/pr104124.c: Likewise. * gcc.target/powerpc/vec-cmpne-long.c: Likewise. * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok, replace -mpower8-vector with -mvsx and add dg-additional-options -mdejagnu-cpu=power8 if !has_arch_pwr8. * gcc.target/powerpc/pr80098-1.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok and replace -mno-power9-vector with -mno-vsx. * gcc.target/powerpc/pr80098-2.c: Replace powerpc_p8vector_ok with powerpc_vsx_ok and replace -mno-power8-vector with -mno-vsx. * gcc.target/powerpc/pragma_misc9.c: Replace powerpc_p9vector_ok with powerpc_vsx_ok. --- gcc/config/rs6000/constraints.md | 4 +- gcc/config/rs6000/driver-rs6000.cc | 7 +- gcc/config/rs6000/rs6000-cpus.def | 20 ++---- gcc/config/rs6000/rs6000.cc | 60 ++---------------- gcc/config/rs6000/rs6000.h | 8 +-- gcc/config/rs6000/rs6000.opt | 4 +- gcc/doc/extend.texi | 4 +- gcc/doc/invoke.texi | 26 +++----- gcc/doc/md.texi | 4 +- gcc/doc/sourcebuild.texi | 3 - gcc/testsuite/g++.dg/pr69667.C | 4 +- gcc/testsuite/g++.target/powerpc/altivec-19.C | 4 +- gcc/testsuite/g++.target/powerpc/pr65240-1.C | 4 +- gcc/testsuite/g++.target/powerpc/pr65240-2.C | 4 +- gcc/testsuite/g++.target/powerpc/pr65240-3.C | 4 +- gcc/testsuite/g++.target/powerpc/pr65242.C | 4 +- gcc/testsuite/g++.target/powerpc/pr67211.C | 2 +- gcc/testsuite/g++.target/powerpc/pr71294.C | 4 +- gcc/testsuite/g++.target/powerpc/pr84279.C | 4 +- gcc/testsuite/g++.target/powerpc/pr93974.C | 4 +- gcc/testsuite/gcc.dg/vect/O3-pr70130.c | 2 +- .../gcc.dg/vect/costmodel/ppc/costmodel-slp-perm.c | 4 +- gcc/testsuite/gcc.dg/vect/pr109011-1.c | 7 +- gcc/testsuite/gcc.dg/vect/pr109011-2.c | 5 +- gcc/testsuite/gcc.dg/vect/pr109011-3.c | 4 +- gcc/testsuite/gcc.dg/vect/pr109011-4.c | 5 +- gcc/testsuite/gcc.dg/vect/pr109011-5.c | 4 +- gcc/testsuite/gcc.dg/vect/pr48765.c | 3 +- .../gcc.target/powerpc/altivec-2-runnable.c | 7 +- gcc/testsuite/gcc.target/powerpc/altivec-35.c | 2 +- gcc/testsuite/gcc.target/powerpc/altivec-37.c | 7 +- gcc/testsuite/gcc.target/powerpc/amo1.c | 5 +- gcc/testsuite/gcc.target/powerpc/amo2.c | 5 +- gcc/testsuite/gcc.target/powerpc/atomic-p8.c | 4 +- .../gcc.target/powerpc/atomic_load_store-p8.c | 4 +- gcc/testsuite/gcc.target/powerpc/bcd-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/bcd-3.c | 4 +- .../gcc.target/powerpc/bfp/scalar-cmp-exp-eq-0.c | 4 +- .../gcc.target/powerpc/bfp/scalar-cmp-exp-eq-1.c | 4 +- .../gcc.target/powerpc/bfp/scalar-cmp-exp-eq-2.c | 4 +- .../gcc.target/powerpc/bfp/scalar-cmp-exp-gt-0.c | 4 +- .../gcc.target/powerpc/bfp/scalar-cmp-exp-gt-1.c | 4 +- .../gcc.target/powerpc/bfp/scalar-cmp-exp-gt-2.c | 4 +- .../gcc.target/powerpc/bfp/scalar-cmp-exp-lt-0.c | 4 +- .../gcc.target/powerpc/bfp/scalar-cmp-exp-lt-1.c | 4 +- .../gcc.target/powerpc/bfp/scalar-cmp-exp-lt-2.c | 4 +- .../powerpc/bfp/scalar-cmp-exp-unordered-0.c | 4 +- .../powerpc/bfp/scalar-cmp-exp-unordered-1.c | 4 +- .../powerpc/bfp/scalar-cmp-exp-unordered-2.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-exp-0.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-exp-1.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-exp-3.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-exp-4.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-exp-5.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-sig-0.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-sig-1.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-sig-2.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-sig-3.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-sig-4.c | 4 +- .../gcc.target/powerpc/bfp/scalar-extract-sig-5.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-0.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-1.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-10.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-11.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-2.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-3.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-4.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-5.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-6.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-7.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-8.c | 4 +- .../gcc.target/powerpc/bfp/scalar-insert-exp-9.c | 4 +- .../powerpc/bfp/scalar-test-data-class-0.c | 4 +- .../powerpc/bfp/scalar-test-data-class-1.c | 4 +- .../powerpc/bfp/scalar-test-data-class-10.c | 4 +- .../powerpc/bfp/scalar-test-data-class-11.c | 4 +- .../powerpc/bfp/scalar-test-data-class-2.c | 4 +- .../powerpc/bfp/scalar-test-data-class-3.c | 4 +- .../powerpc/bfp/scalar-test-data-class-4.c | 4 +- .../powerpc/bfp/scalar-test-data-class-5.c | 4 +- .../powerpc/bfp/scalar-test-data-class-6.c | 4 +- .../powerpc/bfp/scalar-test-data-class-7.c | 4 +- .../powerpc/bfp/scalar-test-data-class-8.c | 4 +- .../powerpc/bfp/scalar-test-data-class-9.c | 4 +- .../gcc.target/powerpc/bfp/scalar-test-neg-0.c | 4 +- .../gcc.target/powerpc/bfp/scalar-test-neg-1.c | 4 +- .../gcc.target/powerpc/bfp/scalar-test-neg-2.c | 4 +- .../gcc.target/powerpc/bfp/scalar-test-neg-3.c | 4 +- .../gcc.target/powerpc/bfp/scalar-test-neg-4.c | 4 +- .../gcc.target/powerpc/bfp/scalar-test-neg-5.c | 4 +- .../gcc.target/powerpc/bfp/vec-extract-exp-0.c | 4 +- .../gcc.target/powerpc/bfp/vec-extract-exp-1.c | 4 +- .../gcc.target/powerpc/bfp/vec-extract-exp-2.c | 4 +- .../gcc.target/powerpc/bfp/vec-extract-exp-3.c | 4 +- .../gcc.target/powerpc/bfp/vec-extract-sig-0.c | 4 +- .../gcc.target/powerpc/bfp/vec-extract-sig-1.c | 4 +- .../gcc.target/powerpc/bfp/vec-extract-sig-2.c | 4 +- .../gcc.target/powerpc/bfp/vec-extract-sig-3.c | 4 +- .../gcc.target/powerpc/bfp/vec-insert-exp-0.c | 4 +- .../gcc.target/powerpc/bfp/vec-insert-exp-1.c | 4 +- .../gcc.target/powerpc/bfp/vec-insert-exp-2.c | 4 +- .../gcc.target/powerpc/bfp/vec-insert-exp-3.c | 4 +- .../gcc.target/powerpc/bfp/vec-insert-exp-4.c | 4 +- .../gcc.target/powerpc/bfp/vec-insert-exp-5.c | 4 +- .../gcc.target/powerpc/bfp/vec-insert-exp-6.c | 4 +- .../gcc.target/powerpc/bfp/vec-insert-exp-7.c | 4 +- .../gcc.target/powerpc/bfp/vec-test-data-class-0.c | 4 +- .../gcc.target/powerpc/bfp/vec-test-data-class-1.c | 4 +- .../gcc.target/powerpc/bfp/vec-test-data-class-2.c | 4 +- .../gcc.target/powerpc/bfp/vec-test-data-class-3.c | 4 +- .../gcc.target/powerpc/bfp/vec-test-data-class-4.c | 4 +- .../gcc.target/powerpc/bfp/vec-test-data-class-5.c | 4 +- .../gcc.target/powerpc/bfp/vec-test-data-class-6.c | 4 +- .../gcc.target/powerpc/bfp/vec-test-data-class-7.c | 4 +- gcc/testsuite/gcc.target/powerpc/bool2-p8.c | 4 +- gcc/testsuite/gcc.target/powerpc/bool3-p8.c | 4 +- gcc/testsuite/gcc.target/powerpc/builtins-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c | 4 +- gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c | 4 +- .../powerpc/builtins-4-int128-runnable.c | 3 +- gcc/testsuite/gcc.target/powerpc/builtins-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/builtins-9.c | 4 +- .../gcc.target/powerpc/builtins-mergew-mergow.c | 3 +- .../gcc.target/powerpc/byte-in-either-range-0.c | 4 +- .../gcc.target/powerpc/byte-in-either-range-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/byte-in-range-0.c | 4 +- gcc/testsuite/gcc.target/powerpc/byte-in-range-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/byte-in-set-0.c | 4 +- gcc/testsuite/gcc.target/powerpc/byte-in-set-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/clone1.c | 4 +- gcc/testsuite/gcc.target/powerpc/clone2.c | 2 +- .../gcc.target/powerpc/crypto-builtin-1.c | 4 +- .../gcc.target/powerpc/crypto-builtin-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/ctz-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/ctz-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/darn-0.c | 4 +- gcc/testsuite/gcc.target/powerpc/darn-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/darn-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/dform-1.c | 5 +- gcc/testsuite/gcc.target/powerpc/dform-2.c | 5 +- gcc/testsuite/gcc.target/powerpc/dform-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c | 4 +- gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c | 4 +- .../gcc.target/powerpc/direct-move-double1.c | 4 +- .../gcc.target/powerpc/direct-move-float1.c | 4 +- .../gcc.target/powerpc/direct-move-float3.c | 5 +- .../gcc.target/powerpc/direct-move-long1.c | 4 +- .../gcc.target/powerpc/direct-move-vector.c | 4 +- .../gcc.target/powerpc/direct-move-vint1.c | 4 +- gcc/testsuite/gcc.target/powerpc/divkc3-2.c | 5 +- gcc/testsuite/gcc.target/powerpc/divkc3-3.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-5.c | 5 +- .../gcc.target/powerpc/float128-complex-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/float128-fma1.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-hw.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-hw10.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-hw11.c | 3 +- gcc/testsuite/gcc.target/powerpc/float128-hw2.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-hw3.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-hw4.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-hw5.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-hw6.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-hw7.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-hw8.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-hw9.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-minmax.c | 3 +- gcc/testsuite/gcc.target/powerpc/float128-odd.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-sqrt1.c | 5 +- gcc/testsuite/gcc.target/powerpc/float128-type-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/float128-type-2.c | 4 +- .../powerpc/fold-vec-abs-int-fwrapv.p9.c | 4 +- .../gcc.target/powerpc/fold-vec-abs-int.p9.c | 4 +- .../powerpc/fold-vec-abs-longlong-fwrapv.c | 5 +- .../powerpc/fold-vec-abs-longlong-fwrapv.p8.c | 4 +- .../powerpc/fold-vec-abs-longlong-fwrapv.p9.c | 4 +- .../gcc.target/powerpc/fold-vec-abs-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-abs-longlong.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-abs-longlong.p9.c | 4 +- gcc/testsuite/gcc.target/powerpc/fold-vec-add-4.c | 5 +- gcc/testsuite/gcc.target/powerpc/fold-vec-add-7.c | 5 +- .../gcc.target/powerpc/fold-vec-cmp-char.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-cmp-char.p9.c | 4 +- .../gcc.target/powerpc/fold-vec-cmp-int.h | 5 +- .../gcc.target/powerpc/fold-vec-cmp-int.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-cmp-int.p9.c | 5 +- .../gcc.target/powerpc/fold-vec-cmp-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-cmp-short.h | 5 +- .../gcc.target/powerpc/fold-vec-cmp-short.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-cmp-short.p9.c | 4 +- .../gcc.target/powerpc/fold-vec-cntlz-char.c | 5 +- .../gcc.target/powerpc/fold-vec-cntlz-int.c | 5 +- .../gcc.target/powerpc/fold-vec-cntlz-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-cntlz-short.c | 5 +- .../gcc.target/powerpc/fold-vec-extract-char.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-extract-char.p9.c | 4 +- .../powerpc/fold-vec-extract-double.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-extract-float.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-extract-float.p9.c | 4 +- .../gcc.target/powerpc/fold-vec-extract-int.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-extract-int.p9.c | 4 +- .../powerpc/fold-vec-extract-longlong.p8.c | 4 +- .../powerpc/fold-vec-extract-longlong.p9.c | 4 +- .../gcc.target/powerpc/fold-vec-extract-short.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-extract-short.p9.c | 4 +- .../gcc.target/powerpc/fold-vec-insert-char-p8.c | 4 +- .../gcc.target/powerpc/fold-vec-insert-char-p9.c | 4 +- .../gcc.target/powerpc/fold-vec-insert-float-p8.c | 4 +- .../gcc.target/powerpc/fold-vec-insert-float-p9.c | 4 +- .../gcc.target/powerpc/fold-vec-insert-int-p8.c | 4 +- .../gcc.target/powerpc/fold-vec-insert-int-p9.c | 4 +- .../gcc.target/powerpc/fold-vec-insert-longlong.c | 4 +- .../gcc.target/powerpc/fold-vec-insert-short-p8.c | 4 +- .../gcc.target/powerpc/fold-vec-insert-short-p9.c | 4 +- .../gcc.target/powerpc/fold-vec-ld-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-logical-eqv-char.c | 5 +- .../powerpc/fold-vec-logical-eqv-float.c | 5 +- .../powerpc/fold-vec-logical-eqv-floatdouble.c | 5 +- .../gcc.target/powerpc/fold-vec-logical-eqv-int.c | 5 +- .../powerpc/fold-vec-logical-eqv-longlong.c | 5 +- .../powerpc/fold-vec-logical-eqv-short.c | 5 +- .../powerpc/fold-vec-logical-ors-longlong.c | 7 +- .../powerpc/fold-vec-logical-other-char.c | 5 +- .../powerpc/fold-vec-logical-other-int.c | 5 +- .../powerpc/fold-vec-logical-other-longlong.c | 5 +- .../powerpc/fold-vec-logical-other-short.c | 5 +- .../powerpc/fold-vec-mergeeo-floatdouble.c | 4 +- .../gcc.target/powerpc/fold-vec-mergeeo-int.c | 4 +- .../gcc.target/powerpc/fold-vec-mergeeo-longlong.c | 4 +- .../gcc.target/powerpc/fold-vec-mergehl-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-minmax-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-mult-int.c | 5 +- .../gcc.target/powerpc/fold-vec-mult-int128-p8.c | 4 +- .../gcc.target/powerpc/fold-vec-mult-int128-p9.c | 4 +- .../gcc.target/powerpc/fold-vec-mult-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-neg-char.c | 2 +- .../gcc.target/powerpc/fold-vec-neg-floatdouble.c | 4 +- .../gcc.target/powerpc/fold-vec-neg-int.c | 5 +- .../gcc.target/powerpc/fold-vec-neg-int.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-neg-int.p9.c | 4 +- .../gcc.target/powerpc/fold-vec-neg-longlong.h | 5 +- .../gcc.target/powerpc/fold-vec-neg-longlong.p8.c | 4 +- .../gcc.target/powerpc/fold-vec-neg-longlong.p9.c | 4 +- .../gcc.target/powerpc/fold-vec-neg-short.c | 2 +- .../gcc.target/powerpc/fold-vec-pack-double.c | 5 +- .../gcc.target/powerpc/fold-vec-pack-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-select-double.c | 4 +- .../powerpc/fold-vec-shift-left-longlong-fwrapv.c | 5 +- .../powerpc/fold-vec-shift-left-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-shift-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-st-longlong.c | 5 +- .../fold-vec-store-builtin_vec_xst-longlong.c | 2 +- .../gcc.target/powerpc/fold-vec-sub-int128.c | 5 +- .../gcc.target/powerpc/fold-vec-sub-longlong.c | 5 +- .../gcc.target/powerpc/fold-vec-unpack-float.c | 5 +- .../gcc.target/powerpc/fold-vec-unpack-int.c | 5 +- gcc/testsuite/gcc.target/powerpc/fusion.c | 2 +- gcc/testsuite/gcc.target/powerpc/fusion2.c | 2 +- gcc/testsuite/gcc.target/powerpc/gnuattr2.c | 5 +- gcc/testsuite/gcc.target/powerpc/mmx-packs.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/mul-vectorize-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/mulkc3-2.c | 5 +- gcc/testsuite/gcc.target/powerpc/mulkc3-3.c | 5 +- .../gcc.target/powerpc/p8-vec-xl-xst-v2.c | 4 +- gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c | 4 +- .../gcc.target/powerpc/p8vector-builtin-1.c | 4 +- .../gcc.target/powerpc/p8vector-builtin-2.c | 4 +- .../gcc.target/powerpc/p8vector-builtin-3.c | 4 +- .../gcc.target/powerpc/p8vector-builtin-4.c | 4 +- .../gcc.target/powerpc/p8vector-builtin-5.c | 4 +- .../gcc.target/powerpc/p8vector-builtin-6.c | 4 +- .../gcc.target/powerpc/p8vector-builtin-7.c | 4 +- .../gcc.target/powerpc/p8vector-builtin-8.c | 5 +- gcc/testsuite/gcc.target/powerpc/p8vector-fp.c | 4 +- .../gcc.target/powerpc/p8vector-int128-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c | 4 +- .../gcc.target/powerpc/p8vector-vbpermq.c | 4 +- .../gcc.target/powerpc/p8vector-vectorize-1.c | 4 +- .../gcc.target/powerpc/p8vector-vectorize-2.c | 4 +- .../gcc.target/powerpc/p8vector-vectorize-3.c | 4 +- .../gcc.target/powerpc/p8vector-vectorize-4.c | 4 +- .../gcc.target/powerpc/p8vector-vectorize-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-dimode1.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-dimode2.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-extract-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-extract-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-extract-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-extract-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-fpcvt-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-fpcvt-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-novsx.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-options-1.c | 8 +-- gcc/testsuite/gcc.target/powerpc/p9-permute.c | 4 +- .../gcc.target/powerpc/p9-sign_extend-runnable.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-splat-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-splat-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-splat-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-splat-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-splat-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-vbpermd.c | 4 +- .../gcc.target/powerpc/p9-vec-length-epil-1.c | 4 +- .../gcc.target/powerpc/p9-vec-length-epil-2.c | 4 +- .../gcc.target/powerpc/p9-vec-length-epil-3.c | 4 +- .../gcc.target/powerpc/p9-vec-length-epil-4.c | 4 +- .../gcc.target/powerpc/p9-vec-length-epil-5.c | 4 +- .../gcc.target/powerpc/p9-vec-length-epil-6.c | 4 +- .../gcc.target/powerpc/p9-vec-length-epil-7.c | 4 +- .../gcc.target/powerpc/p9-vec-length-epil-8.c | 4 +- .../gcc.target/powerpc/p9-vec-length-full-1.c | 4 +- .../gcc.target/powerpc/p9-vec-length-full-2.c | 4 +- .../gcc.target/powerpc/p9-vec-length-full-3.c | 4 +- .../gcc.target/powerpc/p9-vec-length-full-4.c | 4 +- .../gcc.target/powerpc/p9-vec-length-full-5.c | 4 +- .../gcc.target/powerpc/p9-vec-length-full-6.c | 4 +- .../gcc.target/powerpc/p9-vec-length-full-7.c | 4 +- .../gcc.target/powerpc/p9-vec-length-full-8.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-vneg.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-vparity.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-vpermr.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/p9-xxbr-3.c | 4 +- .../gcc.target/powerpc/ppc-fortran/pr80108-1.f90 | 2 +- gcc/testsuite/gcc.target/powerpc/ppc-round2.c | 4 +- gcc/testsuite/gcc.target/powerpc/ppc-round3.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr100866-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr100866-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr103124.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr104015-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr104124.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr104239-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr104239-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr104239-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr106769-p8.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr106769-p9.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr107412.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr108396.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr110429.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr111449-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr111449-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr37191.c | 3 +- gcc/testsuite/gcc.target/powerpc/pr57744.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr58673-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr58673-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr60137.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr60203.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr66144-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr66144-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr66144-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr68163.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr69548.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr70669.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr71186.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr71309.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr71656-1.c | 5 +- gcc/testsuite/gcc.target/powerpc/pr71656-2.c | 5 +- gcc/testsuite/gcc.target/powerpc/pr71670.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr71698.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr71720.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr71977-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr71977-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr72717.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr72853.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr78056-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr78056-2.c | 6 +- gcc/testsuite/gcc.target/powerpc/pr78056-3.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr78056-4.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr78102.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr78543.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr78604.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr78658.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr78953.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79004.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79038-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79179.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79251.p8.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr79251.p9.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr79354.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79544.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79799-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79799-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79799-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79799-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79907.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr79951.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr80098-1.c | 6 +- gcc/testsuite/gcc.target/powerpc/pr80098-2.c | 6 +- gcc/testsuite/gcc.target/powerpc/pr80315-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr80315-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr80315-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr80315-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr80510-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr80695-p8.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr80695-p9.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr80718.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr81348.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr81622.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr81959.c | 5 +- gcc/testsuite/gcc.target/powerpc/pr82748-1.c | 5 +- gcc/testsuite/gcc.target/powerpc/pr82748-2.c | 5 +- gcc/testsuite/gcc.target/powerpc/pr83862.c | 5 +- gcc/testsuite/gcc.target/powerpc/pr84154-1.c | 5 +- gcc/testsuite/gcc.target/powerpc/pr84154-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr84154-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c | 5 +- gcc/testsuite/gcc.target/powerpc/pr84226.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr85456.c | 5 +- .../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 7 +- .../gcc.target/powerpc/pr86731-longlong.c | 5 +- gcc/testsuite/gcc.target/powerpc/pr88558-p8.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr88845.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr90763.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr91903.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr92923-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr96933-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr96933-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr97019.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr98914.c | 2 +- gcc/testsuite/gcc.target/powerpc/pragma_misc9.c | 2 +- gcc/testsuite/gcc.target/powerpc/pragma_power8.c | 2 +- gcc/testsuite/gcc.target/powerpc/sad-vectorize-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/sad-vectorize-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/signbit-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/signbit-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/sse-addps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-addss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-andps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cmpss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtpi16ps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtpi32ps-1.c | 3 +- .../gcc.target/powerpc/sse-cvtpi32x2ps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtpi8ps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtpspi16-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtpspi8-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtpu16ps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtpu8ps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtsi2ss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtsi2ss-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvttss2si-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-cvttss2si-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-divps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-divss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-maxps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-maxps-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-maxss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-minps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-minps-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-minss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movaps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movaps-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movhlps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movhps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movhps-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movlhps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movlps-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movmskb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movmskps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movss-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-movss-3.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-mulps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-mulss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-orps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-pavgw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-pmaxsw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-pmaxub-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-pminsw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-pminub-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-pmulhuw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-psadbw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-rcpps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-rsqrtps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-shufps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-sqrtps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-subps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-subss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-ucomiss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-ucomiss-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-ucomiss-3.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-ucomiss-4.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-ucomiss-5.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-ucomiss-6.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-unpckhps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-unpcklps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse-xorps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-addpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-addsd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-andpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cmppd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cmpsd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-comisd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-comisd-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-comisd-3.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-comisd-4.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-comisd-5.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-comisd-6.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtdq2pd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtdq2ps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtpd2dq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtpd2ps-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtps2dq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtps2pd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2si-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2si-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2ss-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtsi2sd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtsi2sd-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-cvtss2sd-1.c | 3 +- .../gcc.target/powerpc/sse2-cvttpd2dq-1.c | 3 +- .../gcc.target/powerpc/sse2-cvttps2dq-1.c | 3 +- .../gcc.target/powerpc/sse2-cvttsd2si-1.c | 3 +- .../gcc.target/powerpc/sse2-cvttsd2si-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-divpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-divsd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-maxpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-maxsd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-minpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-minsd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-mmx.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movhpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movhpd-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movlpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movlpd-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movmskpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movq-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movq-3.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movsd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movsd-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-movsd-3.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-mulpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-mulsd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-orpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-packssdw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-packsswb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-packuswb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-paddb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-paddd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-paddq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-paddsb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-paddsw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-paddusb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-paddusw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-paddw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pand-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pandn-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pavgb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pavgw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pextrw.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pinsrw.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pmaddwd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pmaxsw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pmaxub-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pminsw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pminub-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pmovmskb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pmulhuw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pmulhw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pmullw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pmuludq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-por-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psadbw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pshufd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pshufhw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pshuflw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pslld-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pslld-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pslldq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psllq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psllq-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psllw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psllw-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psrad-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psrad-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psraw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psraw-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psrld-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psrld-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psrldq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psrlq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psrlq-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psrlw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psrlw-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psubb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psubd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psubq-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psubsb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psubsw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psubusb-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psubusw-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-psubw-1.c | 3 +- .../gcc.target/powerpc/sse2-punpckhbw-1.c | 3 +- .../gcc.target/powerpc/sse2-punpckhdq-1.c | 3 +- .../gcc.target/powerpc/sse2-punpckhqdq-1.c | 3 +- .../gcc.target/powerpc/sse2-punpckhwd-1.c | 3 +- .../gcc.target/powerpc/sse2-punpcklbw-1.c | 3 +- .../gcc.target/powerpc/sse2-punpckldq-1.c | 3 +- .../gcc.target/powerpc/sse2-punpcklqdq-1.c | 3 +- .../gcc.target/powerpc/sse2-punpcklwd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-pxor-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-shufpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-sqrtpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-subpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-subsd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-3.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-4.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-5.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-6.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-unpckhpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-unpcklpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse2-xorpd-1.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse3-addsubpd.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse3-addsubps.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse3-haddpd.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse3-haddps.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse3-hsubpd.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse3-hsubps.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse3-lddqu.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse3-movddup.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse3-movshdup.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse3-movsldup.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-blendpd.c | 3 +- .../gcc.target/powerpc/sse4_1-blendps-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-blendps.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-blendvpd.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-ceilpd.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-ceilps.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-ceilsd.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-ceilss.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-floorpd.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-floorps.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-floorsd.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-floorss.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-pblendvb.c | 3 +- .../gcc.target/powerpc/sse4_1-pblendw-2.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-pblendw.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrb.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrd.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrq.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_1-ptest-1.c | 3 +- .../gcc.target/powerpc/sse4_1-roundpd-2.c | 3 +- .../gcc.target/powerpc/sse4_1-roundpd-3.c | 3 +- gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-pabsb.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-pabsd.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-pabsw.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-palignr.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-phaddd.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-phaddsw.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-phaddw.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-phsubd.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-phsubsw.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-phsubw.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-pmaddubsw.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-pmulhrsw.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-pshufb.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-psignb.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-psignd.c | 3 +- gcc/testsuite/gcc.target/powerpc/ssse3-psignw.c | 3 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-12.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-14.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-15.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-16.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-17.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-18.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-19.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-22.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-23.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-24.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-25.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-30.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-33.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-36.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-39.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-42.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-45.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c | 4 +- gcc/testsuite/gcc.target/powerpc/swaps-p8-5.c | 4 +- .../gcc.target/powerpc/unpack-vectorize-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsdu-0.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsdu-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsdu-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsdu-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsdu-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsdu-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsdub-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsdub-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsduh-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsduh-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsduw-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/vadsduw-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c | 5 +- gcc/testsuite/gcc.target/powerpc/vec-cmp.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-cmpne-long.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-extract-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-extract-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-extract-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-extract-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-extract-6.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-extract-7.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-extract-8.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-extract-9.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-init-10.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-init-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-init-6.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-init-7.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-minmax-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-minmax-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-set-char.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-set-int.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-set-short.c | 4 +- gcc/testsuite/gcc.target/powerpc/vec-sld-modulo.c | 3 +- gcc/testsuite/gcc.target/powerpc/vec-srad-modulo.c | 3 +- gcc/testsuite/gcc.target/powerpc/vec-srd-modulo.c | 3 +- gcc/testsuite/gcc.target/powerpc/vec_reve_2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vector_float.c | 4 +- .../gcc.target/powerpc/versioned-copy-loop.c | 4 +- gcc/testsuite/gcc.target/powerpc/vslv-0.c | 4 +- gcc/testsuite/gcc.target/powerpc/vslv-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsrv-0.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsrv-1.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-0.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-1.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-10.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-11.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-12.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-13.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-14.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-2.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-3.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-4.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-5.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-6.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-7.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-8.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-ne-9.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-nez-1.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-nez-2.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-nez-3.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-nez-4.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-nez-5.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-nez-6.c | 4 +- .../gcc.target/powerpc/vsu/vec-all-nez-7.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-0.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-1.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-10.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-11.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-12.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-13.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-14.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-2.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-3.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-4.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-5.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-6.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-7.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-8.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eq-9.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eqz-1.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eqz-2.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eqz-3.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eqz-4.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eqz-5.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eqz-6.c | 4 +- .../gcc.target/powerpc/vsu/vec-any-eqz-7.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-8.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-9.c | 4 +- .../gcc.target/powerpc/vsu/vec-cmpnez-1.c | 4 +- .../gcc.target/powerpc/vsu/vec-cmpnez-2.c | 4 +- .../gcc.target/powerpc/vsu/vec-cmpnez-3.c | 4 +- .../gcc.target/powerpc/vsu/vec-cmpnez-4.c | 4 +- .../gcc.target/powerpc/vsu/vec-cmpnez-5.c | 4 +- .../gcc.target/powerpc/vsu/vec-cmpnez-6.c | 4 +- .../gcc.target/powerpc/vsu/vec-cmpnez-7.c | 4 +- .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c | 4 +- .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c | 4 +- .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c | 4 +- .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c | 4 +- .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c | 4 +- .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c | 4 +- .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c | 4 +- .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c | 4 +- .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c | 4 +- .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-0.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-1.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-10.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-11.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-12.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-13.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-2.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-3.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-4.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-5.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-6.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-7.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-8.c | 4 +- .../gcc.target/powerpc/vsu/vec-xl-len-9.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-0.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-6.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-7.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-0.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-6.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-7.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-0.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-1.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-10.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-11.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-12.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-13.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-2.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-3.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-4.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-5.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-6.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-7.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-8.c | 4 +- .../gcc.target/powerpc/vsu/vec-xst-len-9.c | 4 +- .../gcc.target/powerpc/vsx-builtin-msum.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-extract-4.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-extract-5.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-himode.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-himode2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-himode3.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-qimode.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-simode.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-simode2.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-simode3.c | 4 +- gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c | 2 +- gcc/testsuite/gfortran.dg/vect/pr45714-b.f | 2 +- gcc/testsuite/lib/target-supports.exp | 74 ++++------------------ 1000 files changed, 2094 insertions(+), 1833 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index c99997b..369a7b7 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -78,8 +78,8 @@ ;; It is currently used for that purpose in LLVM. (define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]" - "@internal Like @code{wa}, if @option{-mpower9-vector} and @option{-m64} are - used; otherwise, @code{NO_REGS}.") + "@internal Like @code{wa}, if this is a POWER9 or later and @option{-mvsx} + and @option{-m64} are used; otherwise, @code{NO_REGS}.") ;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use ;; direct move directly, and movsf can't to move between the register sets. diff --git a/gcc/config/rs6000/driver-rs6000.cc b/gcc/config/rs6000/driver-rs6000.cc index 244b338..3ebbaa4 100644 --- a/gcc/config/rs6000/driver-rs6000.cc +++ b/gcc/config/rs6000/driver-rs6000.cc @@ -476,13 +476,13 @@ static const struct asm_name asm_names[] = { { "power6", "-mpower6 %{!mvsx:%{!maltivec:-maltivec}}" }, { "power6x", "-mpower6 %{!mvsx:%{!maltivec:-maltivec}}" }, { "power7", "-mpower7" }, - { "power8", "%{mpower9-vector:-mpower9;:-mpower8}" }, + { "power8", "-mpower8" }, { "power9", "-mpower9" }, { "power10", "-mpower10" }, { "a2", "-ma2" }, { "powerpc", "-mppc" }, { "powerpc64", "-mppc64" }, - { "powerpc64le", "%{mpower9-vector:-mpower9;:-mpower8}" }, + { "powerpc64le", "-mpower8" }, { "rs64", "-mppc64" }, { "401", "-mppc" }, { "403", "-m403" }, @@ -526,8 +526,7 @@ static const struct asm_name asm_names[] = { { "e6500", "-me6500" }, { "titan", "-mtitan" }, { NULL, "\ -%{mpower9-vector: -mpower9; \ - mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ +%{mcrypto|mdirect-move|mhtm: -mpower8; \ mvsx: -mpower7; \ mpowerpc64: -mppc64; \ : %(asm_default)}" }, diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 276f3cd..2824960 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -86,21 +86,15 @@ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) -/* Flags that need to be turned off if -mno-power9-vector. */ -#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ - | OPTION_MASK_P9_MINMAX) - -/* Flags that need to be turned off if -mno-power8-vector. */ -#define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \ - | OPTION_MASK_P9_VECTOR \ - | OPTION_MASK_DIRECT_MOVE \ - | OPTION_MASK_CRYPTO) - /* Flags that need to be turned off if -mno-vsx. */ -#define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \ - | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ +#define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_KEYWORD \ - | OPTION_MASK_P8_VECTOR) + | OPTION_MASK_P8_VECTOR \ + | OPTION_MASK_DIRECT_MOVE \ + | OPTION_MASK_CRYPTO \ + | OPTION_MASK_P9_VECTOR \ + | OPTION_MASK_FLOAT128_HW \ + | OPTION_MASK_P9_MINMAX) /* Flags that need to be turned off if -mno-altivec. */ #define OTHER_ALTIVEC_MASKS (OTHER_VSX_VECTOR_MASKS \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index a2a679d..6ba9df4 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3866,8 +3866,8 @@ rs6000_option_override_internal (bool global_init_p) dwarf_offset_size = POINTER_SIZE_UNITS; #endif - /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn - off all of the options that depend on those flags. */ + /* Handle explicit -mno-{altivec,vsx} and turn off all of + the options that depend on those flags. */ ignore_masks = rs6000_disable_incompatible_switches (); /* For the newer switches (vsx, dfp, etc.) set some of the older options, @@ -3947,31 +3947,10 @@ rs6000_option_override_internal (bool global_init_p) } if (TARGET_P8_VECTOR && !TARGET_ALTIVEC) - { - if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) - error ("%qs requires %qs", "-mpower8-vector", "-maltivec"); - rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR; - } + rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR; if (TARGET_P8_VECTOR && !TARGET_VSX) - { - if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) - && (rs6000_isa_flags_explicit & OPTION_MASK_VSX)) - error ("%qs requires %qs", "-mpower8-vector", "-mvsx"); - else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0) - { - rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR; - if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) - rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR; - } - else - { - /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is - not explicit. */ - rs6000_isa_flags |= OPTION_MASK_VSX; - rs6000_isa_flags_explicit |= OPTION_MASK_VSX; - } - } + rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR; if (TARGET_DFP && !TARGET_HARD_FLOAT) { @@ -4058,28 +4037,7 @@ rs6000_option_override_internal (bool global_init_p) /* ISA 3.0 vector instructions include ISA 2.07. */ if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR) - { - /* We prefer to not mention undocumented options in - error messages. However, if users have managed to select - power9-vector without selecting power8-vector, they - already know about undocumented flags. */ - if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) && - (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)) - error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector"); - else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0) - { - rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR; - if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) - rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR; - } - else - { - /* OPTION_MASK_P9_VECTOR is explicit and - OPTION_MASK_P8_VECTOR is not explicit. */ - rs6000_isa_flags |= OPTION_MASK_P8_VECTOR; - rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR; - } - } + rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR; /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07 support. If we only have ISA 2.06 support, and the user did not specify @@ -25190,12 +25148,6 @@ rs6000_print_isa_options (FILE *file, int indent, const char *string, 2.07, and 3.0 options that relate to the vector unit (-mdirect-move, -mupper-regs-df, etc.). - If the user used -mno-power8-vector, we need to turn off all of the implicit - ISA 2.07 and 3.0 options that relate to the vector unit. - - If the user used -mno-power9-vector, we need to turn off all of the implicit - ISA 3.0 options that relate to the vector unit. - This function does not handle explicit options such as the user specifying -mdirect-move. These are handled in rs6000_option_override_internal, and the appropriate error is given if needed. @@ -25214,8 +25166,6 @@ rs6000_disable_incompatible_switches (void) const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */ const char *const name; /* name of the switch. */ } flags[] = { - { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" }, - { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" }, { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" }, { OPTION_MASK_ALTIVEC, OTHER_ALTIVEC_MASKS, "altivec" }, }; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 2291fe8..68bc45d 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -103,13 +103,12 @@ /* Common ASM definitions used by ASM_SPEC among the various targets for handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.cc to provide the default assembler options if the user uses -mcpu=native, so if - you make changes here, make them also there. PR63177: Do not pass -mpower8 - to the assembler if -mpower9-vector was also used. */ + you make changes here, make them also there. */ #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ mcpu=power10: -mpower10; \ mcpu=power9: -mpower9; \ - mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \ + mcpu=power8|mcpu=powerpc64le: -mpower8; \ mcpu=power7: -mpower7; \ mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ @@ -163,8 +162,7 @@ mcpu=e5500: -me5500; \ mcpu=e6500: -me6500; \ mcpu=titan: -mtitan; \ - !mcpu*: %{mpower9-vector: -mpower9; \ - mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ + !mcpu*: %{mcrypto|mdirect-move|mhtm: -mpower8; \ mvsx: -mpower7; \ mpowerpc64: -mppc64;: %(asm_default)}; \ :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \ diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 5e32ee9..8319768 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -479,7 +479,7 @@ Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) Allow sign extension in fusion operations. mpower8-vector -Target Mask(P8_VECTOR) Var(rs6000_isa_flags) +Target Undocumented Mask(P8_VECTOR) Var(rs6000_isa_flags) WarnRemoved Use vector and scalar instructions added in ISA 2.07. mpower10-fusion @@ -522,7 +522,7 @@ Target Undocumented Mask(P9_MISC) Var(rs6000_isa_flags) Use certain scalar instructions added in ISA 3.0. mpower9-vector -Target Undocumented Mask(P9_VECTOR) Var(rs6000_isa_flags) +Target Undocumented Mask(P9_VECTOR) Var(rs6000_isa_flags) WarnRemoved Use vector instructions added in ISA 3.0. mpower9-minmax diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 2135dfd..52b5a1f 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21381,8 +21381,8 @@ available on the PowerPC family of processors starting with ISA 2.07 or later. Unless specific options are explicitly disabled on the command line, specifying option @option{-mcpu=power8} has the effect of enabling all the same options as for @option{-mcpu=power7} in -addition to the @option{-mpower8-fusion}, @option{-mpower8-vector}, -@option{-mcrypto}, @option{-mhtm}, @option{-mquad-memory}, and +addition to the @option{-mpower8-fusion}, @option{-mcrypto}, +@option{-mhtm}, @option{-mquad-memory}, and @option{-mquad-memory-atomic} options. This section intentionally empty. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b4e4ee9..8219a6a 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1317,7 +1317,7 @@ See RS/6000 and PowerPC Options. -mveclibabi=@var{type} -mfriz -mno-friz -mpointers-to-nested-functions -mno-pointers-to-nested-functions -msave-toc-indirect -mno-save-toc-indirect --mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector +-mpower8-fusion -mno-mpower8-fusion -mcrypto -mno-crypto -mhtm -mno-htm -mquad-memory -mno-quad-memory -mquad-memory-atomic -mno-quad-memory-atomic @@ -31160,7 +31160,7 @@ following options: -mpopcntb -mpopcntd -mpowerpc64 -mpowerpc-gpopt -mpowerpc-gfxopt -mmulhw -mdlmzb -mmfpgpr -mvsx --mcrypto -mhtm -mpower8-fusion -mpower8-vector +-mcrypto -mhtm -mpower8-fusion -mquad-memory -mquad-memory-atomic -mfloat128 -mfloat128-hardware -mprefixed -mpcrel -mmma -mrop-protect} @@ -31283,15 +31283,6 @@ Generate code that keeps (does not keeps) some integer operations adjacent so that the instructions can be fused together on power8 and later processors. -@opindex mpower8-vector -@opindex mno-power8-vector -@item -mpower8-vector -@itemx -mno-power8-vector -Generate code that uses (does not use) the vector and scalar -instructions that were added in version 2.07 of the PowerPC ISA. Also -enable the use of built-in functions that allow more direct access to -the vector instructions. - @opindex mquad-memory @opindex mno-quad-memory @item -mquad-memory @@ -31323,13 +31314,12 @@ supported on Linux. The default for @option{-mfloat128} is enabled on PowerPC Linux systems using the VSX instruction set, and disabled on other systems. -If you use the ISA 3.0 instruction set (@option{-mpower9-vector} or -@option{-mcpu=power9}) on a 64-bit system, the IEEE 128-bit floating -point support will also enable the generation of ISA 3.0 IEEE 128-bit -floating point instructions. Otherwise, if you do not specify to -generate ISA 3.0 instructions or you are targeting a 32-bit big endian -system, IEEE 128-bit floating point will be done with software -emulation. +If you use the ISA 3.0 instruction set (@option{-mcpu=power9}) on a +64-bit system, the IEEE 128-bit floating point support will also enable +the generation of ISA 3.0 IEEE 128-bit floating point instructions. +Otherwise, if you do not specify to generate ISA 3.0 instructions or you +are targeting a 32-bit big endian system, IEEE 128-bit floating point +will be done with software emulation. @opindex mfloat128-hardware @opindex mno-float128-hardware diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 33b37e7..5730bda 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3425,8 +3425,8 @@ Any condition register field, @code{cr0}@dots{}@code{cr7}. The carry bit, @code{XER[CA]}. @item we -Like @code{wa}, if @option{-mpower9-vector} and @option{-m64} are used; -otherwise, @code{NO_REGS}. +Like @code{wa}, if this is a POWER9 or later and @option{-mvsx} +and @option{-m64} are used; otherwise, @code{NO_REGS}. @item wn No register (@code{NO_REGS}). diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 7b747bfa..efab862 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2443,9 +2443,6 @@ PowerPC target supports hardware double-precision floating-point. @item powerpc_htm_ok PowerPC target supports @code{-mhtm} -@item powerpc_p8vector_ok -PowerPC target supports @code{-mpower8-vector} - @item powerpc_popcntb_ok PowerPC target supports the @code{popcntb} instruction, indicating that this target supports @code{-mcpu=power5}. diff --git a/gcc/testsuite/g++.dg/pr69667.C b/gcc/testsuite/g++.dg/pr69667.C index 422116d..cfe25a8 100644 --- a/gcc/testsuite/g++.dg/pr69667.C +++ b/gcc/testsuite/g++.dg/pr69667.C @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -w -std=c++14" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -w -std=c++14" } */ /* target/69667, compiler got internal compiler error: Max. number of generated reload insns per insn is achieved (90) */ diff --git a/gcc/testsuite/g++.target/powerpc/altivec-19.C b/gcc/testsuite/g++.target/powerpc/altivec-19.C index 5879e72..4a1bf18 100644 --- a/gcc/testsuite/g++.target/powerpc/altivec-19.C +++ b/gcc/testsuite/g++.target/powerpc/altivec-19.C @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 " } */ #include diff --git a/gcc/testsuite/g++.target/powerpc/pr65240-1.C b/gcc/testsuite/g++.target/powerpc/pr65240-1.C index 1cf158c..c22c2c2 100644 --- a/gcc/testsuite/g++.target/powerpc/pr65240-1.C +++ b/gcc/testsuite/g++.target/powerpc/pr65240-1.C @@ -1,6 +1,6 @@ /* { dg-skip-if "" { *-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -ffast-math -mno-fp-in-toc -Wno-return-type" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -ffast-math -mno-fp-in-toc -Wno-return-type" } */ /* { dg-additional-options "-mcmodel=small" { target lp64 } } */ /* target/65240, compiler got a 'insn does not satisfy its constraints' error. */ diff --git a/gcc/testsuite/g++.target/powerpc/pr65240-2.C b/gcc/testsuite/g++.target/powerpc/pr65240-2.C index 32d1c79..99ca68c 100644 --- a/gcc/testsuite/g++.target/powerpc/pr65240-2.C +++ b/gcc/testsuite/g++.target/powerpc/pr65240-2.C @@ -1,6 +1,6 @@ /* { dg-skip-if "" { *-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -ffast-math -mfp-in-toc -Wno-return-type" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -ffast-math -mfp-in-toc -Wno-return-type" } */ /* { dg-additional-options "-mcmodel=small" { target lp64 } } */ /* target/65240, compiler got a 'insn does not satisfy its constraints' error. */ diff --git a/gcc/testsuite/g++.target/powerpc/pr65240-3.C b/gcc/testsuite/g++.target/powerpc/pr65240-3.C index 0256764..a8869d5 100644 --- a/gcc/testsuite/g++.target/powerpc/pr65240-3.C +++ b/gcc/testsuite/g++.target/powerpc/pr65240-3.C @@ -1,6 +1,6 @@ /* { dg-skip-if "" { *-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -ffast-math -Wno-return-type" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -ffast-math -Wno-return-type" } */ /* { dg-additional-options "-mcmodel=medium" { target lp64 } } */ /* target/65240, compiler got a 'insn does not satisfy its constraints' error. */ diff --git a/gcc/testsuite/g++.target/powerpc/pr65242.C b/gcc/testsuite/g++.target/powerpc/pr65242.C index 3f5c2ea..278fe96 100644 --- a/gcc/testsuite/g++.target/powerpc/pr65242.C +++ b/gcc/testsuite/g++.target/powerpc/pr65242.C @@ -1,6 +1,6 @@ /* { dg-skip-if "" { *-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ class A { public: diff --git a/gcc/testsuite/g++.target/powerpc/pr67211.C b/gcc/testsuite/g++.target/powerpc/pr67211.C index 7d5dd42..95d90da 100644 --- a/gcc/testsuite/g++.target/powerpc/pr67211.C +++ b/gcc/testsuite/g++.target/powerpc/pr67211.C @@ -1,5 +1,5 @@ /* { dg-skip-if "" { *-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mdejagnu-cpu=power7 -mdejagnu-tune=power8 -O3 -w" } */ /* target/67211, compiler got a 'insn does not satisfy its constraints' error. */ diff --git a/gcc/testsuite/g++.target/powerpc/pr71294.C b/gcc/testsuite/g++.target/powerpc/pr71294.C index 7f12c8d..85b9f81 100644 --- a/gcc/testsuite/g++.target/powerpc/pr71294.C +++ b/gcc/testsuite/g++.target/powerpc/pr71294.C @@ -1,5 +1,5 @@ -// { dg-require-effective-target powerpc_p8vector_ok } */ -// { dg-options "-mdejagnu-cpu=power8 -O3 -fstack-protector" } +// { dg-require-effective-target powerpc_vsx_ok } */ +// { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -fstack-protector" } // PAR target/71294 failed because RELOAD could not figure how create a V2DI // vector that auto vectorization created with each element being the same diff --git a/gcc/testsuite/g++.target/powerpc/pr84279.C b/gcc/testsuite/g++.target/powerpc/pr84279.C index 0263242..ee9747c 100644 --- a/gcc/testsuite/g++.target/powerpc/pr84279.C +++ b/gcc/testsuite/g++.target/powerpc/pr84279.C @@ -1,8 +1,8 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target fpic } */ -/* { dg-options "-O3 -mdejagnu-cpu=power8 -g -fPIC -fvisibility=hidden -fstack-protector-strong" } */ +/* { dg-options "-O3 -mdejagnu-cpu=power8 -mvsx -g -fPIC -fvisibility=hidden -fstack-protector-strong" } */ template struct E { T e; }; struct J { diff --git a/gcc/testsuite/g++.target/powerpc/pr93974.C b/gcc/testsuite/g++.target/powerpc/pr93974.C index 562de0a..86401bd 100644 --- a/gcc/testsuite/g++.target/powerpc/pr93974.C +++ b/gcc/testsuite/g++.target/powerpc/pr93974.C @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -fstack-protector-strong" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -fstack-protector-strong" } */ class a { double b[2]; diff --git a/gcc/testsuite/gcc.dg/vect/O3-pr70130.c b/gcc/testsuite/gcc.dg/vect/O3-pr70130.c index 17ce6c3..378ec51 100644 --- a/gcc/testsuite/gcc.dg/vect/O3-pr70130.c +++ b/gcc/testsuite/gcc.dg/vect/O3-pr70130.c @@ -1,5 +1,5 @@ /* { dg-require-effective-target vsx_hw { target powerpc*-*-* } } */ -/* { dg-additional-options "-mcpu=power7 -mno-power9-vector -mno-power8-vector" { target powerpc*-*-* } } */ +/* { dg-additional-options "-mdejagnu-cpu=power7 -mvsx" { target powerpc*-*-* } } */ #include "tree-vect.h" diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-perm.c b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-perm.c index e5c4dce..624881b 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-perm.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-slp-perm.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ /* { dg-require-effective-target vect_int } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* Specify power9 to ensure the vectorization is profitable and test point stands, otherwise it could be not profitable to vectorize. */ -/* { dg-additional-options "-mdejagnu-cpu=power9 -mpower9-vector" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9 -mvsx" } */ /* Verify we cost the exact count for required vec_perm. */ diff --git a/gcc/testsuite/gcc.dg/vect/pr109011-1.c b/gcc/testsuite/gcc.dg/vect/pr109011-1.c index 9bb8ee1..98362d6 100644 --- a/gcc/testsuite/gcc.dg/vect/pr109011-1.c +++ b/gcc/testsuite/gcc.dg/vect/pr109011-1.c @@ -3,7 +3,8 @@ /* { dg-options "-O3 -fno-unroll-loops --param=vect-epilogues-nomask=0 -fdump-tree-optimized" } */ /* { dg-additional-options "-mavx512cd" { target { { i?86-*-* x86_64-*-* } && avx512cd } } } */ /* { dg-additional-options "-mavx512vpopcntdq" { target { { i?86-*-* x86_64-*-* } && avx512vpopcntdq } } } */ -/* { dg-additional-options "-mpower8-vector" { target powerpc_p8vector_ok } } */ +/* { dg-additional-options "-mvsx" { target { powerpc_vsx_ok && has_arch_pwr8 } } } */ +/* { dg-additional-options "-mdejagnu-cpu=power8 -mvsx" { target { powerpc_vsx_ok && { ! has_arch_pwr8 } } } } */ /* { dg-additional-options "-march=z13 -mzarch" { target s390_vx } } */ void @@ -15,7 +16,7 @@ foo (long long *p, long long *q) } /* { dg-final { scan-tree-dump-times " = \.POPCOUNT \\\(vect" 1 "optimized" { target { { i?86-*-* x86_64-*-* } && avx512vpopcntdq } } } } */ -/* { dg-final { scan-tree-dump-times " = \.POPCOUNT \\\(vect" 1 "optimized" { target { powerpc_p8vector_ok || s390_vx } } } } */ +/* { dg-final { scan-tree-dump-times " = \.POPCOUNT \\\(vect" 1 "optimized" { target { powerpc_vsx_ok || s390_vx } } } } */ void bar (long long *p, long long *q) @@ -26,4 +27,4 @@ bar (long long *p, long long *q) } /* { dg-final { scan-tree-dump-times " = \.CLZ \\\(vect" 1 "optimized" { target { { i?86-*-* x86_64-*-* } && avx512cd } } } } */ -/* { dg-final { scan-tree-dump-times " = \.CLZ \\\(vect" 1 "optimized" { target { powerpc_p8vector_ok || s390_vx } } } } */ +/* { dg-final { scan-tree-dump-times " = \.CLZ \\\(vect" 1 "optimized" { target { powerpc_vsx_ok || s390_vx } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr109011-2.c b/gcc/testsuite/gcc.dg/vect/pr109011-2.c index 6d18eb2..a737e3f 100644 --- a/gcc/testsuite/gcc.dg/vect/pr109011-2.c +++ b/gcc/testsuite/gcc.dg/vect/pr109011-2.c @@ -2,7 +2,8 @@ /* { dg-do compile } */ /* { dg-options "-O3 -fno-unroll-loops --param=vect-epilogues-nomask=0 -fdump-tree-optimized" } */ /* { dg-additional-options "-mavx512cd -mbmi -mlzcnt -mno-avx512vpopcntdq" { target { { { { i?86-*-* x86_64-*-* } && avx512cd } && lzcnt } && bmi } } } */ -/* { dg-additional-options "-mpower9-vector" { target powerpc_p9vector_ok } } */ +/* { dg-additional-options "-mvsx" { target { powerpc_vsx_ok && has_arch_pwr9 } } } */ +/* { dg-additional-options "-mdejagnu-cpu=power9 -mvsx" { target { powerpc_vsx_ok && { ! has_arch_pwr9 } } } } */ /* { dg-additional-options "-march=z13 -mzarch" { target s390_vx } } */ void @@ -30,6 +31,6 @@ baz (int *p, int *q) } /* { dg-final { scan-tree-dump-times " = \.CLZ \\\(vect" 3 "optimized" { target { { { { i?86-*-* x86_64-*-* } && avx512cd } && lzcnt } && bmi } } } } */ -/* { dg-final { scan-tree-dump-times " = \.CTZ \\\(vect" 3 "optimized" { target powerpc_p9vector_ok } } } */ +/* { dg-final { scan-tree-dump-times " = \.CTZ \\\(vect" 3 "optimized" { target powerpc_vsx_ok } } } */ /* { dg-final { scan-tree-dump-times " = \.CTZ \\\(vect" 2 "optimized" { target s390_vx } } } */ /* { dg-final { scan-tree-dump-times " = \.POPCOUNT \\\(vect" 1 "optimized" { target s390_vx } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr109011-3.c b/gcc/testsuite/gcc.dg/vect/pr109011-3.c index 0c6c826..21c364d 100644 --- a/gcc/testsuite/gcc.dg/vect/pr109011-3.c +++ b/gcc/testsuite/gcc.dg/vect/pr109011-3.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-options "-O3 -fno-unroll-loops --param=vect-epilogues-nomask=0 -fdump-tree-optimized" } */ /* { dg-additional-options "-mno-avx512cd -mbmi -mlzcnt -mavx512vpopcntdq" { target { { { { i?86-*-* x86_64-*-* } && avx512vpopcntdq } && lzcnt } && bmi } } } */ -/* { dg-additional-options "-mpower8-vector -mno-power9-vector" { target powerpc_p8vector_ok } } */ +/* { dg-additional-options "-mdejagnu-cpu=power8 -mvsx" { target powerpc_vsx_ok } } */ void foo (int *p, int *q) @@ -29,4 +29,4 @@ baz (int *p, int *q) } /* { dg-final { scan-tree-dump-times " = \.POPCOUNT \\\(vect" 3 "optimized" { target { { { { i?86-*-* x86_64-*-* } && avx512vpopcntdq } && lzcnt } && bmi } } } } */ -/* { dg-final { scan-tree-dump-times " = \.CLZ \\\(vect" 3 "optimized" { target powerpc_p8vector_ok } } } */ +/* { dg-final { scan-tree-dump-times " = \.CLZ \\\(vect" 3 "optimized" { target powerpc_vsx_ok } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr109011-4.c b/gcc/testsuite/gcc.dg/vect/pr109011-4.c index 7bb3377..76af788 100644 --- a/gcc/testsuite/gcc.dg/vect/pr109011-4.c +++ b/gcc/testsuite/gcc.dg/vect/pr109011-4.c @@ -2,7 +2,8 @@ /* { dg-do compile } */ /* { dg-options "-O3 -fno-unroll-loops --param=vect-epilogues-nomask=0 -fdump-tree-optimized" } */ /* { dg-additional-options "-mavx512cd -mbmi -mlzcnt -mno-avx512vpopcntdq" { target { { { { i?86-*-* x86_64-*-* } && avx512cd } && lzcnt } && bmi } } } */ -/* { dg-additional-options "-mpower9-vector" { target powerpc_p9vector_ok } } */ +/* { dg-additional-options "-mvsx" { target { powerpc_vsx_ok && has_arch_pwr9 } } } */ +/* { dg-additional-options "-mdejagnu-cpu=power9 -mvsx" { target { powerpc_vsx_ok && { ! has_arch_pwr9 } } } } */ /* { dg-additional-options "-march=z13 -mzarch" { target s390_vx } } */ void @@ -30,6 +31,6 @@ baz (long long *p, long long *q) } /* { dg-final { scan-tree-dump-times " = \.CLZ \\\(vect" 3 "optimized" { target { { { { i?86-*-* x86_64-*-* } && avx512cd } && lzcnt } && bmi } } } } */ -/* { dg-final { scan-tree-dump-times " = \.CTZ \\\(vect" 3 "optimized" { target powerpc_p9vector_ok } } } */ +/* { dg-final { scan-tree-dump-times " = \.CTZ \\\(vect" 3 "optimized" { target powerpc_vsx_ok } } } */ /* { dg-final { scan-tree-dump-times " = \.CTZ \\\(vect" 2 "optimized" { target s390_vx } } } */ /* { dg-final { scan-tree-dump-times " = \.POPCOUNT \\\(vect" 1 "optimized" { target s390_vx } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr109011-5.c b/gcc/testsuite/gcc.dg/vect/pr109011-5.c index 61fac0b..19dbfb3 100644 --- a/gcc/testsuite/gcc.dg/vect/pr109011-5.c +++ b/gcc/testsuite/gcc.dg/vect/pr109011-5.c @@ -2,7 +2,7 @@ /* { dg-do compile } */ /* { dg-options "-O3 -fno-unroll-loops --param=vect-epilogues-nomask=0 -fdump-tree-optimized" } */ /* { dg-additional-options "-mno-avx512cd -mbmi -mlzcnt -mavx512vpopcntdq" { target { { { { i?86-*-* x86_64-*-* } && avx512vpopcntdq } && lzcnt } && bmi } } } */ -/* { dg-additional-options "-mpower8-vector -mno-power9-vector" { target powerpc_p8vector_ok } } */ +/* { dg-additional-options "-mdejagnu-cpu=power8 -mvsx" { target powerpc_vsx_ok } } */ void foo (long long *p, long long *q) @@ -29,4 +29,4 @@ baz (long long *p, long long *q) } /* { dg-final { scan-tree-dump-times " = \.POPCOUNT \\\(vect" 3 "optimized" { target { { { { i?86-*-* x86_64-*-* } && avx512vpopcntdq } && lzcnt } && bmi } } } } */ -/* { dg-final { scan-tree-dump-times " = \.CLZ \\\(vect" 3 "optimized" { target powerpc_p8vector_ok } } } */ +/* { dg-final { scan-tree-dump-times " = \.CLZ \\\(vect" 3 "optimized" { target powerpc_vsx_ok } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr48765.c b/gcc/testsuite/gcc.dg/vect/pr48765.c index b091a14..23748a9 100644 --- a/gcc/testsuite/gcc.dg/vect/pr48765.c +++ b/gcc/testsuite/gcc.dg/vect/pr48765.c @@ -1,6 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */ -/* { dg-additional-options "-O3 -mcpu=power6 -mno-power9-vector -mno-power8-vector -mno-vsx" } */ +/* { dg-additional-options "-O3 -mdejagnu-cpu=power6 -mno-vsx" } */ enum reg_class { diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c b/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c index 041edcb..7d1eda90 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-2-runnable.c @@ -1,6 +1,7 @@ /* { dg-do compile { target powerpc*-*-* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -mvsx" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include @@ -33,7 +34,7 @@ int main () /* Use of 'double' and ‘long long’ in AltiVec types requires -mvsx */ /* __builtin_altivec_vupkhsw and __builtin_altivec_vupklsw - requires the -mpower8-vector option */ + requires the -mcpu=power8 -mvsx option */ vec_bi_arg = (vector bool int){ 0, 1, 1, 0 }; diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-35.c b/gcc/testsuite/gcc.target/powerpc/altivec-35.c index 0836528..8173dca 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-35.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-35.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_altivec_ok } */ -/* { dg-options "-maltivec -mno-vsx -mno-power8-vector -O0" } */ +/* { dg-options "-maltivec -mno-vsx -O0" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-37.c b/gcc/testsuite/gcc.target/powerpc/altivec-37.c index 06d4bb1..2a84e0b 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-37.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-37.c @@ -1,6 +1,7 @@ /* { dg-do compile { target powerpc*-*-* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -mvsx" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include @@ -14,7 +15,7 @@ int main () /* use of ‘long long’ in AltiVec types requires -mvsx */ /* __builtin_altivec_vupkhsw and __builtin_altivec_vupklsw - requires the -mpower8-vector option */ + requires the -mcpu=power8 and -mvsx option */ *vecublli++ = vec_unpackh(vecubi[0]); *vecublli++ = vec_unpackl(vecubi[0]); *vecslli++ = vec_unpackh(vecsi[0]); diff --git a/gcc/testsuite/gcc.target/powerpc/amo1.c b/gcc/testsuite/gcc.target/powerpc/amo1.c index 152f0e5..d2a67d8 100644 --- a/gcc/testsuite/gcc.target/powerpc/amo1.c +++ b/gcc/testsuite/gcc.target/powerpc/amo1.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mpower9-vector -mpower9-misc -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -mpower9-misc -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ /* Verify P9 atomic memory operations. */ diff --git a/gcc/testsuite/gcc.target/powerpc/amo2.c b/gcc/testsuite/gcc.target/powerpc/amo2.c index cc7cfe4..9cb493d 100644 --- a/gcc/testsuite/gcc.target/powerpc/amo2.c +++ b/gcc/testsuite/gcc.target/powerpc/amo2.c @@ -1,6 +1,7 @@ /* { dg-do run { target { powerpc*-*-linux* && { lp64 && p9vector_hw } } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mpower9-vector -mpower9-misc" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mvsx -mpower9-misc" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/atomic-p8.c b/gcc/testsuite/gcc.target/powerpc/atomic-p8.c index 1588d74..b24ca4c 100644 --- a/gcc/testsuite/gcc.target/powerpc/atomic-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/atomic-p8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-final { scan-assembler-times "lbarx" 7 } } */ /* { dg-final { scan-assembler-times "lharx" 7 } } */ /* { dg-final { scan-assembler-times "lwarx" 7 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c b/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c index 1fc96ae..94b21ba 100644 --- a/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-final { scan-assembler-times "lq" 1 } } */ /* { dg-final { scan-assembler-times "stq" 1 } } */ /* { dg-final { scan-assembler-not "bl __atomic" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bcd-2.c b/gcc/testsuite/gcc.target/powerpc/bcd-2.c index 95c3699..a5b4f2c 100644 --- a/gcc/testsuite/gcc.target/powerpc/bcd-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bcd-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-final { scan-assembler-times "bcdadd\[.\] " 2 } } */ /* { dg-final { scan-assembler-times "bcdsub\[.\] " 2 } } */ /* { dg-final { scan-assembler-not "bl __builtin" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bcd-3.c b/gcc/testsuite/gcc.target/powerpc/bcd-3.c index 9891f4f..ff35ef5 100644 --- a/gcc/testsuite/gcc.target/powerpc/bcd-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bcd-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-final { scan-assembler-times "bcdadd\[.\] " 4 } } */ /* { dg-final { scan-assembler-times "bcdsub\[.\] " 6 } } */ /* { dg-final { scan-assembler-not "bl __builtin" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-0.c index 92fea89..f1b3bc3 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-1.c index fec8b9b..720ba5d 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-2.c index 604dbbc..46c459c 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-eq-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-0.c index 0eb99ce..e412d73 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-1.c index 33f1555..bd9f522 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-2.c index 2f01b87..b9f306d 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-gt-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-0.c index 511f79f..ca25ac2 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-1.c index 6ee364f..77302a3 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-2.c index 75969c2..6045bda 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-lt-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-0.c index 4852859..1893fc5 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-1.c index 8bc1eac..45acdb4 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-2.c index f59b4a3..6417631 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed on 32-bit and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c index d971833..b59fdd6 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c index 1cb438f..32179cd 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-3.c index 8ddf87c..48a0ee2 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed only on 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-4.c index 850ff62..ae3ab80 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-4.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed only on 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-5.c index 8cbb319..79956d7 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-5.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test only runs on 32-bit configurations, where a compiler error should be issued because this builtin is not available on diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c index d22f7d1..92e8944 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* { dg-require-effective-target has_arch_ppc64 } */ /* This test should succeed only on 64-bit configurations. */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c index 64747d7..848fce3 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* { dg-require-effective-target has_arch_ppc64 } */ /* This test should succeed only on 64-bit configurations. */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c index 148b5fb..b8c89ac 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { has_arch_ppc64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test only runs on 32-bit configurations, producing a compiler error because the builtin requires 64 bits. */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-3.c index 3225a55..d3ae94b 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed only on 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-4.c index 32a53c6..24e382f 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-4.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed only on 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-5.c index f3b6473..7f86801 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-5.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test only runs on 32-bit configurations, producing a compiler error because the builtin requires 64 bits. */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c index 88d7756..ae34591 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* { dg-require-effective-target has_arch_ppc64 } */ /* This test should succeed only on 64-bit configurations. */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c index 2f219dd..50a21f9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* { dg-require-effective-target has_arch_ppc64 } */ /* This test should succeed only on 64-bit configurations. */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-10.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-10.c index 769d3b0..743cf44 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-10.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-10.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed only on 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-11.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-11.c index bee5460..469f6d9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-11.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-11.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test only runs on 32-bit configurations, where a compiler error should be issued because this builtin is not available on diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c index 956c118..a3ab1f2 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { has_arch_ppc64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test only runs on 32-bit configurations, where a compiler error should be issued because this builtin is not available on diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c index afa2b83..fe0a7a7 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* { dg-require-effective-target has_arch_ppc64 } */ /* This test should succeed only on 64-bit configurations. */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c index 6dc06dd..7078a67 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* { dg-require-effective-target has_arch_ppc64 } */ /* This test should succeed only on 64-bit configurations. */ diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c index 9a7949f..5ccc7ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { has_arch_ppc64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test only runs on 32-bit configurations, where a compiler error should be issued because this builtin is not available on diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-6.c index f81dff4..3aca1ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-6.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-6.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed only on 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-7.c index 2e03e15..2651745 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-7.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-7.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed only on 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c index b1be828..265b4ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test only runs on 32-bit configurations, where a compiler error should be issued because this builtin is not available on diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-9.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-9.c index 209f82d..84a0156 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-9.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-9.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed only on 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-0.c index a74028b..7d69447 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-1.c index ec31cff..403f54b 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-10.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-10.c index fcf6a9d..45f380f 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-10.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-10.c @@ -2,8 +2,8 @@ /* Require 64-bit target to select expected error message below. 32-bit target produces different error message. */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-11.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-11.c index 7c6fca2..170f641 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-11.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-11.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-2.c index 9130c97..b519dd6 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-3.c index b863bb2..3beb620 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-4.c index 83ddffa..1687f96 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-4.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-5.c index 101a919..465af2d 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-6.c index 7fb6601..014ebb7 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-6.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-7.c index 02e9ec5..4c46db9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-7.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-8.c index a9e107a..7fa834e8 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-8.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-9.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-9.c index f87851c..3998d45f 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-9.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-data-class-9.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-0.c index cebca0a..941187e 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-1.c index 65a6462..215437c 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c index 46d743a..abdac3a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c index bfc892b..f4774a9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-4.c index 4a3f25e..112023c 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-4.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c index 8c55c1c..3bee45d 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-test-neg-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-0.c index 4147891..9979aa9 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-1.c index ca67a75..981bcb4 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-2.c index 86d0260..efd7d4a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-3.c index e909a26..94f8c79 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-exp-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-0.c index afac623..03a91b2 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-1.c index ee243fe..60e090d 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-2.c index eab6673..4f079e8 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-3.c index ab1967b..7843cb5 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-extract-sig-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-0.c index dcdf668..96dc96a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-1.c index 5f2c350..fcc6bee 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-2.c index 6aa6b40..6d8198f 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-3.c index ab4c2f1..b4b88c2 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-4.c index d69a315..c654f7e 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-4.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-5.c index 95ceb83..f0a41e1 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-6.c index 70ed82b..0a893a1 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-6.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-7.c index eb5dda4..b0f81a5 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-7.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-insert-exp-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-0.c index ddf8bb4..1cad09c 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-0.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-1.c index 90dcf13..4baa2ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-1.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-2.c index f53efdc..f463152 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-2.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-3.c index 5ec7019..e0e346a 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-3.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-4.c index 448406c..f6fa7d0 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-4.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-5.c index 64a52a1..2938707 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-5.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-6.c index 5f35e0e..4165277 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-6.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-7.c b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-7.c index bda2c6d..d6301d0 100644 --- a/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-7.c +++ b/gcc/testsuite/gcc.target/powerpc/bfp/vec-test-data-class-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/bool2-p8.c b/gcc/testsuite/gcc.target/powerpc/bool2-p8.c index 76f6043..545d523 100644 --- a/gcc/testsuite/gcc.target/powerpc/bool2-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/bool2-p8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* { dg-final { scan-assembler-not "\[ \t\]and " } } */ /* { dg-final { scan-assembler-not "\[ \t\]or " } } */ /* { dg-final { scan-assembler-not "\[ \t\]xor " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/bool3-p8.c b/gcc/testsuite/gcc.target/powerpc/bool3-p8.c index 3660e69..f2b1b1d 100644 --- a/gcc/testsuite/gcc.target/powerpc/bool3-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/bool3-p8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* { dg-final { scan-assembler "\[ \t\]and " } } */ /* { dg-final { scan-assembler "\[ \t\]or " } } */ /* { dg-final { scan-assembler "\[ \t\]xor " } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc/testsuite/gcc.target/powerpc/builtins-1.c index 28cd1aa..155895f 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-additional-options "-mbig" { target powerpc64le-*-* } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c index 1633dfa..e5a7db6 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-maltivec -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c index 96bdc48..c354fd5 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-p9.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c index 4f4e7a9..62c1113 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c @@ -1,7 +1,8 @@ /* { dg-do run } */ /* { dg-require-effective-target int128 } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-mpower8-vector" } */ +/* { dg-options "-mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include #include // vector diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-5.c b/gcc/testsuite/gcc.target/powerpc/builtins-5.c index c6c7ebf..fc3cf21 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-5.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O0 -dp" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O0 -dp" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-9.c b/gcc/testsuite/gcc.target/powerpc/builtins-9.c index fa486e0..d1b7dba 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-9.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-9.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-maltivec -mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mdejagnu-cpu=power8 -mvsx -O3" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-mergew-mergow.c b/gcc/testsuite/gcc.target/powerpc/builtins-mergew-mergow.c index 51c8701..e17f200 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-mergew-mergow.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-mergew-mergow.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-mpower8-vector" } */ +/* { dg-options "-mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include // vector #include diff --git a/gcc/testsuite/gcc.target/powerpc/byte-in-either-range-0.c b/gcc/testsuite/gcc.target/powerpc/byte-in-either-range-0.c index 647186d..c93e2ef 100644 --- a/gcc/testsuite/gcc.target/powerpc/byte-in-either-range-0.c +++ b/gcc/testsuite/gcc.target/powerpc/byte-in-either-range-0.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/byte-in-either-range-1.c b/gcc/testsuite/gcc.target/powerpc/byte-in-either-range-1.c index 3a07f7f..59040a5 100644 --- a/gcc/testsuite/gcc.target/powerpc/byte-in-either-range-1.c +++ b/gcc/testsuite/gcc.target/powerpc/byte-in-either-range-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/byte-in-range-0.c b/gcc/testsuite/gcc.target/powerpc/byte-in-range-0.c index 9603177..12668b7 100644 --- a/gcc/testsuite/gcc.target/powerpc/byte-in-range-0.c +++ b/gcc/testsuite/gcc.target/powerpc/byte-in-range-0.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/byte-in-range-1.c b/gcc/testsuite/gcc.target/powerpc/byte-in-range-1.c index ec1740d..fb97f3e 100644 --- a/gcc/testsuite/gcc.target/powerpc/byte-in-range-1.c +++ b/gcc/testsuite/gcc.target/powerpc/byte-in-range-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/byte-in-set-0.c b/gcc/testsuite/gcc.target/powerpc/byte-in-set-0.c index 16126bf..b709378 100644 --- a/gcc/testsuite/gcc.target/powerpc/byte-in-set-0.c +++ b/gcc/testsuite/gcc.target/powerpc/byte-in-set-0.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed only on 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/byte-in-set-1.c b/gcc/testsuite/gcc.target/powerpc/byte-in-set-1.c index 53fa5d8..6b8b414 100644 --- a/gcc/testsuite/gcc.target/powerpc/byte-in-set-1.c +++ b/gcc/testsuite/gcc.target/powerpc/byte-in-set-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c b/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c index 4c676ba..bbdcbbd 100644 --- a/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c +++ b/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/clone1.c b/gcc/testsuite/gcc.target/powerpc/clone1.c index 74323ca..0506b14 100644 --- a/gcc/testsuite/gcc.target/powerpc/clone1.c +++ b/gcc/testsuite/gcc.target/powerpc/clone1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target ppc_cpu_supports_hw } */ /* Power9 (aka, ISA 3.0) has a MODSD instruction to do modulus, while Power8 diff --git a/gcc/testsuite/gcc.target/powerpc/clone2.c b/gcc/testsuite/gcc.target/powerpc/clone2.c index ecad5eb..e64940b 100644 --- a/gcc/testsuite/gcc.target/powerpc/clone2.c +++ b/gcc/testsuite/gcc.target/powerpc/clone2.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc*-*-linux* } } } */ /* { dg-options "-mvsx -O2" } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target ppc_cpu_supports_hw } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c index 89895bd..b8ff3b5 100644 --- a/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ #include typedef vector unsigned long long crypto_t; diff --git a/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c index b3a6c73..734f1ac 100644 --- a/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/crypto-builtin-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-crypto" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx -mno-crypto" } */ void use_builtins_d (__vector unsigned long long *p, __vector unsigned long long *q, __vector unsigned long long *r, __vector unsigned long long *s) { diff --git a/gcc/testsuite/gcc.target/powerpc/ctz-3.c b/gcc/testsuite/gcc.target/powerpc/ctz-3.c index a36a5c8..0481d02 100644 --- a/gcc/testsuite/gcc.target/powerpc/ctz-3.c +++ b/gcc/testsuite/gcc.target/powerpc/ctz-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ #ifndef SIZE #define SIZE 1024 diff --git a/gcc/testsuite/gcc.target/powerpc/ctz-4.c b/gcc/testsuite/gcc.target/powerpc/ctz-4.c index 74d305a..ebff89f 100644 --- a/gcc/testsuite/gcc.target/powerpc/ctz-4.c +++ b/gcc/testsuite/gcc.target/powerpc/ctz-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/darn-0.c b/gcc/testsuite/gcc.target/powerpc/darn-0.c index 64d98f5..ca339a1 100644 --- a/gcc/testsuite/gcc.target/powerpc/darn-0.c +++ b/gcc/testsuite/gcc.target/powerpc/darn-0.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "" { powerpc*-*-aix* } } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/darn-1.c b/gcc/testsuite/gcc.target/powerpc/darn-1.c index f483a89..d3a2a62 100644 --- a/gcc/testsuite/gcc.target/powerpc/darn-1.c +++ b/gcc/testsuite/gcc.target/powerpc/darn-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "" { powerpc*-*-aix* } } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/darn-2.c b/gcc/testsuite/gcc.target/powerpc/darn-2.c index 56a9ffb..0bbd69b 100644 --- a/gcc/testsuite/gcc.target/powerpc/darn-2.c +++ b/gcc/testsuite/gcc.target/powerpc/darn-2.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "" { powerpc*-*-aix* } } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dform-1.c b/gcc/testsuite/gcc.target/powerpc/dform-1.c index 1a0b0cf..9d0e870 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-1.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-1.c @@ -1,8 +1,9 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* Now O2 enables vectorization by default, which makes expected scalar loads gone, so simply disable it. */ -/* { dg-options "-mpower9-vector -O2 -fno-tree-vectorize" } */ +/* { dg-options "-mvsx -O2 -fno-tree-vectorize" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ #ifndef TYPE #define TYPE double diff --git a/gcc/testsuite/gcc.target/powerpc/dform-2.c b/gcc/testsuite/gcc.target/powerpc/dform-2.c index cc91f55..d9d0111 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-2.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-2.c @@ -1,8 +1,9 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* Now O2 enables vectorization by default, which generates unexpected float conversion for vector construction, so simply disable it. */ -/* { dg-options "-mpower9-vector -O2 -fno-tree-vectorize" } */ +/* { dg-options "-mvsx -O2 -fno-tree-vectorize" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ #ifndef TYPE #define TYPE float diff --git a/gcc/testsuite/gcc.target/powerpc/dform-3.c b/gcc/testsuite/gcc.target/powerpc/dform-3.c index d4114f5..84885ec 100644 --- a/gcc/testsuite/gcc.target/powerpc/dform-3.c +++ b/gcc/testsuite/gcc.target/powerpc/dform-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #ifndef TYPE #define TYPE vector double diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c index 4f7562b..4903184 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-0.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c index 6338a0e..6e1750d 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c index 822030b..b8d5662 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-10.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c index 044e768..706ba22 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-11.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c index 4feb391..642814a 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-12.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c index cc54c6b..ec22452 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-13.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c index ef4d6ad..1b9fe41 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-14.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c index 54d2557..19158a1 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-15.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c index 8626c57..da3ba1c 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-16.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c index 5a9ab51..6c5b608 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-17.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c index 8ce9390..c612e66 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-18.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c index f1918a2..586b43a 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-19.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c index b353d63..daf1230 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c index ee098bc..03e8c2e 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-20.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c index 0d47cc2..0d157ee 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-21.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c index 464dc66..3d9249b 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-22.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c index 236f393..66bc0d2 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-23.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c index 6e5e07b..eb58202 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-24.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c index 1390c83..98dbba4 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-25.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c index f070a0c..9a96dd9 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-26.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c index d8760ce..6ffd1e7 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-27.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c index a2b9229..f8dbc8d 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-28.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c index fed06bb..dcc8557 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-29.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c index af07fbb..01c0d69 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c index 6d8869e..d7a8df1 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-30.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c index 439fcb2..97bf3d5 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-31.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c index 868146c..2ca7e11 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-32.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c index 6d978a0..9253950 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-33.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c index de17499..0731a89 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-34.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c index fdafaf9..5dd564e 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-35.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c index 822f6d5..e7aca95 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-36.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c index 1e5ff35..01f7154 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-37.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c index fce744c..6f8fddb 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-38.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c index b5f886d..ee77999 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-39.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c index ad840bf..485f8a7 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c index 4663fc6..a6a2c59 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-40.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c index 451a9e7..a790ed5 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-41.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c index 586c86f..68827dc 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-42.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c index 9c19437..0e4c4bc 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-43.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c index dc01b7f..dc3580a 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-44.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c index 5c6fcc4..3097f1e 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-45.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c index d0833c8..a36df7f 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-46.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c index 9ff4126..a49dfea 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-47.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c index 9a94371d..65a920f 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-48.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c index 5040ac8..1d4db33 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-49.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c index 6f57baf..c5be1ca 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c index 25b35ed..d67c0a3 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-50.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c index e6b5fe5..a359034 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-51.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c index a79e6b5..817ea46 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-52.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c index d11f497..85e2ec8 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-53.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c index 5e9a93f..57590d8 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-54.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c index 912ae7f..6646d8e 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-55.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c index 218d2f6..b80d4fe 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-56.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c index ec2abc6..04f729d 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-57.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c index 0626d87..ff81cbb 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-58.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c index 6f63d0f..dfd566d 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-59.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c index d889bdd..c3ab62d 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-6.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c index c584d98..06c2ed8 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-60.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c index 1a54150..dbdf64f 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-61.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c index 4786be7..f0f8cbb 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-62.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c index e7d2a27..527f656 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-63.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c index c406d4d..f2de23a 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-64.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c index 7c75265d..a1ddc10 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-65.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c index 74269fa..b7adb7e 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-66.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c index d7b3b6f..9f4961c 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-67.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c index 1bda795..35de6a5 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-68.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c index bc9ced3..ed9bc04 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-69.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c index dcfe162..52a34f6 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-7.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c index 875354c..7ef9f4c 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-70.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c index 68758cf..1848b1e 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-71.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c index 04d950e..55aa7c8 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-72.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c index f368c38..8c525ca4 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-73.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c index 369312d..c8b108d 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-74.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c index 910fb7d..089a71f 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-75.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c index d867a98..f335479 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-76.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c index ca6c739..6bca0d6 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-77.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c index 3034300..300e5b6 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-78.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c index 9ee60cf..53ac646 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-79.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c index 28bc10c..59df46e 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c index 9a9ff38..c6749f2 100644 --- a/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c +++ b/gcc/testsuite/gcc.target/powerpc/dfp/dtstsfi-9.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c index e75daec..03402f1 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target lp64 } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-final { scan-assembler "mtvsrd" } } */ /* { dg-final { scan-assembler "mfvsrd" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c index 285aca6..5e5097b 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target lp64 } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-final { scan-assembler {\mmtvsrd\M} } } */ /* { dg-final { scan-assembler {\mmfvsrwz\M} } } */ /* { dg-final { scan-assembler {\mxscvdpspn\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-float3.c b/gcc/testsuite/gcc.target/powerpc/direct-move-float3.c index f6c5f23..0eb1945 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-float3.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-float3.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* Test that we generate XSCVDPSP instead of FRSP and XSCVDPSPN when we combine a round from double to float and moving the float value to a GPR. */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c index ad90b2e..931f1e9 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target lp64 } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-final { scan-assembler "mtvsrd" } } */ /* { dg-final { scan-assembler "mfvsrd" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-vector.c b/gcc/testsuite/gcc.target/powerpc/direct-move-vector.c index 16f2674..1d06cd8 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-vector.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-vector.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Check code generation for direct move for long types. */ diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c b/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c index 2db8dbc..8e22297 100644 --- a/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c +++ b/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target lp64 } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-final { scan-assembler "mtvsrd" } } */ /* { dg-final { scan-assembler "mfvsrd" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/divkc3-2.c b/gcc/testsuite/gcc.target/powerpc/divkc3-2.c index e34ed40..223f413 100644 --- a/gcc/testsuite/gcc.target/powerpc/divkc3-2.c +++ b/gcc/testsuite/gcc.target/powerpc/divkc3-2.c @@ -1,7 +1,8 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target longdouble128 } */ -/* { dg-options "-O2 -mpower8-vector -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* Check that complex multiply generates the right call when long double is IEEE 128-bit floating point. */ diff --git a/gcc/testsuite/gcc.target/powerpc/divkc3-3.c b/gcc/testsuite/gcc.target/powerpc/divkc3-3.c index c0fda8b..3a33b50 100644 --- a/gcc/testsuite/gcc.target/powerpc/divkc3-3.c +++ b/gcc/testsuite/gcc.target/powerpc/divkc3-3.c @@ -1,7 +1,8 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target longdouble128 } */ -/* { dg-options "-O2 -mpower8-vector -mabi=ibmlongdouble -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -mabi=ibmlongdouble -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* Check that complex multiply generates the right call when long double is IBM extended double floating point. */ diff --git a/gcc/testsuite/gcc.target/powerpc/float128-5.c b/gcc/testsuite/gcc.target/powerpc/float128-5.c index 17f2fb2..85da4b8 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-5.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-5.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mpower9-vector -mno-float128" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mvsx -mno-float128" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ /* Test that we can use #pragma GCC target to enable -mfloat128 and generate code on ISA 3.0 for the float128 built-in functions. Lp64 is required diff --git a/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c b/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c index 01f45b1..339af47 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-linux* } } } */ /* { dg-require-effective-target powerpc_float128_hw_ok } */ -/* { dg-options "-O2 -mpower9-vector -mfloat128-hardware" } */ +/* { dg-options "-O2 -mvsx -mfloat128-hardware" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ #ifndef NO_FLOAT typedef _Complex float float_complex; diff --git a/gcc/testsuite/gcc.target/powerpc/float128-fma1.c b/gcc/testsuite/gcc.target/powerpc/float128-fma1.c index 5c90e7e..1ce1caa 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-fma1.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-fma1.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2" } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ __float128 xfma (__float128 a, __float128 b, __float128 c) diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw.c b/gcc/testsuite/gcc.target/powerpc/float128-hw.c index 8c9beaf..74c0e92 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2" } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ #ifndef TYPE #define TYPE _Float128 diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw10.c b/gcc/testsuite/gcc.target/powerpc/float128-hw10.c index 539337c..983c372 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw10.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw10.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2" } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ extern _Float128 floorf128 (_Float128); extern _Float128 ceilf128 (_Float128); diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw11.c b/gcc/testsuite/gcc.target/powerpc/float128-hw11.c index dc78cf2..a3fe8d0 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw11.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw11.c @@ -1,7 +1,8 @@ /* { dg-do run { target lp64 } } */ /* { dg-require-effective-target p9vector_hw } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2" } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ #define __STDC_WANT_IEC_60559_TYPES_EXT__ 1 #define __STDC_WANT_IEC_60559_FUNCS_EXT__ 1 diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw2.c b/gcc/testsuite/gcc.target/powerpc/float128-hw2.c index 1e3408b..663032e 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw2.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw2.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2 -ffast-math -std=gnu11" } */ +/* { dg-options "-mvsx -O2 -ffast-math -std=gnu11" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ /* Test to make sure the compiler handles the standard _Float128 functions that have hardware support in ISA 3.0/power9. */ diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw3.c b/gcc/testsuite/gcc.target/powerpc/float128-hw3.c index 630c93d..7f9bb6c 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw3.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw3.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2 -ffast-math -std=c11 -mno-pcrel" } */ +/* { dg-options "-mvsx -O2 -ffast-math -std=c11 -mno-pcrel" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ /* Test to make sure the compiler calls the external function instead of doing the built-in processing for _Float128 functions that have hardware support diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw4.c b/gcc/testsuite/gcc.target/powerpc/float128-hw4.c index fc14916..c07d34d 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw4.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw4.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2 -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-options "-mvsx -O2 -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ /* Insure that the ISA 3.0 IEEE 128-bit floating point built-in functions can be used with long double when the default is IEEE 128-bit. */ diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw5.c b/gcc/testsuite/gcc.target/powerpc/float128-hw5.c index b0edafb..3dd960a 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw5.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw5.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2 -ffast-math" } */ +/* { dg-options "-mvsx -O2 -ffast-math" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ extern _Float128 copysignf128 (_Float128, _Float128); diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw6.c b/gcc/testsuite/gcc.target/powerpc/float128-hw6.c index a96edc8..05bb2dc 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw6.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw6.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2" } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ extern _Float128 fabsf128 (_Float128); extern _Float128 copysignf128 (_Float128, _Float128); diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw7.c b/gcc/testsuite/gcc.target/powerpc/float128-hw7.c index ffed847..300ca23 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw7.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw7.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2" } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ extern _Float128 fabsf128 (_Float128); extern _Float128 copysignf128 (_Float128, _Float128); diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw8.c b/gcc/testsuite/gcc.target/powerpc/float128-hw8.c index 23f9ec2..6555fed 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw8.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw8.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2" } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ extern _Float128 fminf128 (_Float128, _Float128); extern _Float128 fmaxf128 (_Float128, _Float128); diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw9.c b/gcc/testsuite/gcc.target/powerpc/float128-hw9.c index e37fd1b..ac6cf68 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-hw9.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-hw9.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2 -ffast-math" } */ +/* { dg-options "-mvsx -O2 -ffast-math" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ extern _Float128 sqrtf128 (_Float128); diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c index ef8f729..e9ace19 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c @@ -1,5 +1,6 @@ /* { dg-require-effective-target ppc_float128_hw } */ -/* { dg-options "-mpower9-vector -O2 -ffast-math" } */ +/* { dg-options "-mvsx -O2 -ffast-math" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ #ifndef TYPE #define TYPE _Float128 diff --git a/gcc/testsuite/gcc.target/powerpc/float128-odd.c b/gcc/testsuite/gcc.target/powerpc/float128-odd.c index 8c8a34c..3b82568 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-odd.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-odd.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2" } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ /* Test the generation of the round to odd instructions. */ __float128 diff --git a/gcc/testsuite/gcc.target/powerpc/float128-sqrt1.c b/gcc/testsuite/gcc.target/powerpc/float128-sqrt1.c index 7020664..ca9b24a 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-sqrt1.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-sqrt1.c @@ -1,7 +1,8 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target float128 } */ -/* { dg-options "-mpower9-vector -O2" } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ __float128 xsqrt (__float128 a) diff --git a/gcc/testsuite/gcc.target/powerpc/float128-type-1.c b/gcc/testsuite/gcc.target/powerpc/float128-type-1.c index 53f9e35..0fbd7f2 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-type-1.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-type-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { *-*-linux* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -mno-float128" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -mno-float128" } */ /* This test tests whether the underlying IEEE 128-bit floating point) is enabled by default on VSX Linux 64-bit systems, even if the keyword diff --git a/gcc/testsuite/gcc.target/powerpc/float128-type-2.c b/gcc/testsuite/gcc.target/powerpc/float128-type-2.c index 02dbad1..4594021 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-type-2.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-type-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { *-*-linux* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -mno-float128" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mno-float128" } */ /* This test tests whether the underlying IEEE 128-bit floating point) is enabled by default on VSX Linux 64-bit systems, even if the keyword diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c index 07d5890..d7fc9d3 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c @@ -2,8 +2,8 @@ inputs produce the right results when -mcpu=power9 is specified. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-maltivec -O2 -mdejagnu-cpu=power9 -fwrapv" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -O2 -mdejagnu-cpu=power9 -mvsx -fwrapv" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c index 3c0ffb0..569104e 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-int.p9.c @@ -2,8 +2,8 @@ inputs produce the right code when -mcpu=power9 is specified. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-maltivec -O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -O2 -mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c index 6c3108c..cd681d6 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2 -fwrapv" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2 -fwrapv" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c index 5b746e5..d4062a7 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c @@ -3,8 +3,8 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c index fb8dffc..471244b 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c @@ -2,8 +2,8 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mpower9-vector -O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c index 4f5148e..edd2c4e 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c index 6a499f4..9650a47 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p8.c @@ -2,8 +2,8 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c index fb8dffc..471244b 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-abs-longlong.p9.c @@ -2,8 +2,8 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mpower9-vector -O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-add-4.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-add-4.c index 389a20c..3db3ff1 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-add-4.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-add-4.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-maltivec -mvsx -mpower8-vector" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-add-7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-add-7.c index 71de0b6..38f1fcb 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-add-7.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-add-7.c @@ -2,9 +2,10 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target int128 } */ -/* { dg-options "-maltivec -mvsx -mpower8-vector" } */ +/* { dg-options "-maltivec -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */ #include "altivec.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.p8.c index bf17dea..606b773 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.p8.c @@ -2,8 +2,8 @@ char inputs produce the right code when -mcpu=power8 is specified. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ #include "fold-vec-cmp-char.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.p9.c index 66c14cf..385df08 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-char.p9.c @@ -2,8 +2,8 @@ char inputs produce the right code when -mcpu=power9 is specified. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mpower8-vector -mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include "fold-vec-cmp-char.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.h b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.h index 0da58e0..5de4ff9 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.h +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.h @@ -2,8 +2,9 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.p8.c index c8ce72c..8a5128e 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.p8.c @@ -2,8 +2,8 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ #include "fold-vec-cmp-int.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.p9.c index 3ece8fc..9f5b4bd 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-int.p9.c @@ -2,8 +2,9 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mpower9-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ #include "fold-vec-cmp-int.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c index 536ee75..36f90b1 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-longlong.c @@ -2,8 +2,9 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.h b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.h index 5729db4..596be67 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.h +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.h @@ -2,8 +2,9 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.p8.c index 36cad0c..832ea69 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.p8.c @@ -2,8 +2,8 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ #include "fold-vec-cmp-short.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.p9.c index 46b1be1..87a87f3 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cmp-short.p9.c @@ -2,8 +2,8 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mpower9-vector -mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include "fold-vec-cmp-short.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-char.c index 61dfbcc..4257bef 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-char.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-char.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-maltivec -mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-int.c index ae4dd57..36ff165 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-int.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-int.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-maltivec -mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-longlong.c index 1a72a2d..1811a6f 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-longlong.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mvsx -mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-short.c index 0f05cac..afecc24 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-short.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-cntlz-short.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-maltivec -mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c index f3b9556..2f65899 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p8.c @@ -2,8 +2,8 @@ inputs produce the right code with a P8 (LE or BE) target. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ // six tests total. Targeting P8LE / P8BE. // P8 LE variable offset: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, sradi, rlwinm, (extsb) diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p9.c index 8a4c380..f96eb7b 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p9.c @@ -2,8 +2,8 @@ inputs produce the right code with a P9 (LE) target. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 " } */ /* { dg-final { scan-assembler-times {\mli\M} 3 { target lp64 } } } */ /* Endian sensitive, vextubrx or vextublx. */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p8.c index 2b8dbb0..42e83f4 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p8.c @@ -2,8 +2,8 @@ double inputs produce the right code with a P8 (LE or BE) target. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ // targeting P8, BE and LE. 2 tests. // P8 (LE) constants: xxlor diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c index 4b1d75e..ce4e43c 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c @@ -2,8 +2,8 @@ inputs produce the right code with a P8 (LE or BE) target. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ // targeting P8, BE and LE. 2 tests. // P8 (LE) constants: xxsldwi, xscvspdp diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p9.c index aaa8a92..19a84e9 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p9.c @@ -2,8 +2,8 @@ inputs produce the right code. */ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 " } */ /* { dg-final { scan-assembler-times {\mxscvspdp\M} 2 } } */ /* { dg-final { scan-assembler-times {\mrldicl\M} 1 { target le } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c index f5f9533..152fbdd 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c @@ -2,8 +2,8 @@ inputs produce the right code with a P8 (LE or BE) target. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ // Targeting P8 (LE) and (BE). 6 tests total. // P8 LE constant: vspltw, mfvsrwz, (1:extsw/2:rldicl) diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p9.c index 1abf19d..d6e71b9 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p9.c @@ -2,8 +2,8 @@ inputs produce the right code with a P9 (LE) target. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 " } */ // Targeting P9 (LE). 6 tests total. // P9 constant: li, vextuwrx, (1:extsw) diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p8.c index 8ddce3fd..a49822d 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p8.c @@ -2,8 +2,8 @@ inputs produce the right code with a P8 (LE or BE) target. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ // Targeting P8LE and P8BE, six tests total. // P8 (LE) constants: mfvsrd diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p9.c index 29814ed..0b83f38 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p9.c @@ -2,8 +2,8 @@ inputs produce the right code for a P9 target. */ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ // targeting P9 (LE), six tests. // p9 constants: mfvsrd diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c index 0ddecb4..9eabc50 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c @@ -2,8 +2,8 @@ inputs produce the right results with a P8 (LE or BE) target. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ // six tests total. Targeting P8, both LE and BE. // p8 (le) variable offset: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, srdi, (1:extsh/2:rlwinm) diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p9.c index fac35cb..7e6c122 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p9.c @@ -2,8 +2,8 @@ inputs produce the right code for a P9 target. */ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ // six tests total. Targeting P9. // p9 (le) variable offset: slwi, vextuhlx, extsh diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c index e0c7ee1..209f3c4 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p8.c @@ -2,8 +2,8 @@ inputs produce the right codegen. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* The below contains vec_insert () calls with both variable and constant values. Only the constant value calls are early-gimple folded, but all diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c index c18444d..7fdcad5 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-char-p9.c @@ -2,8 +2,8 @@ inputs produce the right codegen. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ /* The below contains vec_insert () calls with both variable and constant values. Only the constant value calls are early-gimple folded, but all diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c index 1866ce2..fef29c8 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p8.c @@ -2,8 +2,8 @@ inputs produce the right codegen. Power8 variant. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c index 1c57672..c2eacc0 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-float-p9.c @@ -2,8 +2,8 @@ inputs produce the right codegen. Power9 variant. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c index bcee9b2..78e74ec 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p8.c @@ -2,8 +2,8 @@ inputs produce the right codegen. Power8 variant. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c index 5512810..95c03ed 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-int-p9.c @@ -2,8 +2,8 @@ inputs produce the right codegen. Power9 variant. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c index 8ca4ac7..bf982b6 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-longlong.c @@ -2,8 +2,8 @@ inputs produce the right codegen. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c index 0d9d4e7..2ac7230 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p8.c @@ -2,8 +2,8 @@ inputs produce the right codegen. Power8 variant. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c index 050adb2..10fb3c3 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c @@ -2,8 +2,8 @@ inputs produce the right codegen. Power9 variant. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c index 9b4a952..d5dd84c 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-ld-longlong.c @@ -2,8 +2,9 @@ inputs produce the right code. */ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-char.c index 6810848..75d913b 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-char.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-char.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-float.c index d206cfe..edbf2d4 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-float.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-float.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c index 56b7cac..7a1ff0b 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c @@ -2,8 +2,9 @@ double inputs for VSX produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-int.c index f5d292e..ea07852 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-int.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-int.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-longlong.c index 342b2bd..45673c1 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-longlong.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-short.c index 79ca8aa..995c6cb 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-short.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-short.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c index 10c69d3..d15ee5b 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-ors-longlong.c @@ -2,8 +2,9 @@ * long long inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include @@ -153,7 +154,7 @@ test6_nor (vector unsigned long long x, vector unsigned long long y) // The number of xxlor instructions generated varies between 6 and 24 for // older systems (power6,power7), as well as for 32-bit versus 64-bit targets. -// For simplicity, this test now only targets "powerpc_p8vector_ok" environments +// For simplicity, this test now only targets "powerpc_vsx_ok" environments // where the answer is expected to be 6. /* { dg-final { scan-assembler-times {\mxxlor\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c index 7fe3e0b..62a084f 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-char.c @@ -3,8 +3,9 @@ * vec_nand) were added as part of ISA 2.07 (P8). */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O1" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-int.c index 61d3405..4dde6bc 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-int.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-int.c @@ -3,8 +3,9 @@ * vec_nand) were added as part of ISA 2.07 (P8). */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O1" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-longlong.c index d33006c..a8af3b0 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-longlong.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O1" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-short.c index cc354b9..dbb7884 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-short.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-other-short.c @@ -3,8 +3,9 @@ * vec_nand) were added as part of ISA 2.07 (P8). */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O1" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c index b604b3f..4e4f445 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c @@ -2,8 +2,8 @@ with float and double inputs produce the right codegen. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -mpower8-vector " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c index 4c67a32..815e466 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c @@ -2,8 +2,8 @@ with int inputs produce the right codegen. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c index 73d1e73..c733522 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c @@ -2,8 +2,8 @@ with long long inputs produce the right codegen. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergehl-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergehl-longlong.c index 3cb566c..ad7e51b 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergehl-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergehl-longlong.c @@ -2,8 +2,9 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-longlong.c index 234d078..af6ba51 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-minmax-longlong.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c index b536bce..49c28f0 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c index 83052e7..b1250d5 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p8.c @@ -2,10 +2,10 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target int128 } */ /* { dg-require-effective-target lp64 } */ -/* { dg-options "-mpower8-vector -mdejagnu-cpu=power8 -O2" } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */ #include "altivec.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c index 0223191..dc82b59 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-int128-p9.c @@ -2,9 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target int128 } */ -/* { dg-options "-mpower9-vector -mdejagnu-cpu=power9 -O2" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */ #include "altivec.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c index dff073d..2d79183 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-maltivec -mvsx -mpower8-vector" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-char.c index 116b249..8cb686b 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-char.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-char.c @@ -2,7 +2,7 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mvsx -O2 -mdejagnu-cpu=power8" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-floatdouble.c index 1202eea..ad4b874 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-floatdouble.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-floatdouble.c @@ -2,8 +2,8 @@ double inputs for VSX produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mvsx -O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c index f7682ad..35b211f 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.c @@ -2,8 +2,9 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p8.c index 058ea0d..878cf79 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p8.c @@ -2,8 +2,8 @@ inputs produce the right code when -mcpu=power8 is specified. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p9.c index cc9f886..7635d0a 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-int.p9.c @@ -2,8 +2,8 @@ inputs produce the right code when -mcpu=power9 is specified. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-maltivec -O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -O2 -mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.h b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.h index 53312ac..2c9daa4 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.h +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.h @@ -4,8 +4,9 @@ /* vec_neg testcase, included by fold-vec-neg-longlong.p*.c */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p8.c index 16e0560..ceb28a7 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p8.c @@ -2,8 +2,8 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ #include "fold-vec-neg-longlong.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p9.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p9.c index af59037..54b5837 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-longlong.p9.c @@ -2,8 +2,8 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include "fold-vec-neg-longlong.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-short.c index 8b4e71b..e777d35 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-short.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-neg-short.c @@ -2,7 +2,7 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mvsx -O2 -mdejagnu-cpu=power8" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-pack-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-pack-double.c index 362ba0c..d5164f4 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-pack-double.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-pack-double.c @@ -2,8 +2,9 @@ double inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mvsx -mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-pack-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-pack-longlong.c index 25c3c37..b5e8db2 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-pack-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-pack-longlong.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mvsx -mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-double.c index bb7dce1..14dcd12 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-select-double.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-select-double.c @@ -2,8 +2,8 @@ double inputs for VSX produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c index 486426a..72aa5f0 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c @@ -2,8 +2,9 @@ /* This test covers the shift left tests with the -fwrapv option. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2 -fwrapv" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2 -fwrapv" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c index 4116dbc..6afa917 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-left-longlong.c @@ -2,8 +2,9 @@ * This is a counterpart to the fold-vec-shift-left-frwapv test. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c index 97b82cf..9403552 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-shift-longlong.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-st-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-st-longlong.c index a33f64e..bc81123 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-st-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-st-longlong.c @@ -2,8 +2,9 @@ inputs produce the right code. */ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c index bb72d9b..6df1151 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c @@ -1,7 +1,7 @@ /* Verify that overloaded built-ins for __builtin_vec_xst with long long inputs produce the right code. */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mvsx -O2 -mdejagnu-cpu=power8" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c index 13caa9e..2c7b454 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-int128.c @@ -2,9 +2,10 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target int128 } */ -/* { dg-options "-maltivec -mvsx -mpower8-vector" } */ +/* { dg-options "-maltivec -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */ #include "altivec.h" diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c index 889fba4..f38312cb 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-sub-longlong.c @@ -2,8 +2,9 @@ inputs produce the right results. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-maltivec -mvsx -mpower8-vector" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-unpack-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-unpack-float.c index 78e8eb3..4e1d603 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-unpack-float.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-unpack-float.c @@ -2,8 +2,9 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-unpack-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-unpack-int.c index 621c4eb..17e4ad7 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-unpack-int.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-unpack-int.c @@ -2,8 +2,9 @@ inputs produce the right code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/fusion.c b/gcc/testsuite/gcc.target/powerpc/fusion.c index 2a11558..2906f8a 100644 --- a/gcc/testsuite/gcc.target/powerpc/fusion.c +++ b/gcc/testsuite/gcc.target/powerpc/fusion.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mdejagnu-cpu=power7 -mdejagnu-tune=power8 -O3 -dp" } */ #define LARGE 0x12345 diff --git a/gcc/testsuite/gcc.target/powerpc/fusion2.c b/gcc/testsuite/gcc.target/powerpc/fusion2.c index 40ca00a..925b6d8 100644 --- a/gcc/testsuite/gcc.target/powerpc/fusion2.c +++ b/gcc/testsuite/gcc.target/powerpc/fusion2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-skip-if "" { powerpc*le-*-* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mdejagnu-cpu=power7 -mdejagnu-tune=power8 -O3" } */ vector double fusion_vector (vector double *p) { return p[2]; } diff --git a/gcc/testsuite/gcc.target/powerpc/gnuattr2.c b/gcc/testsuite/gcc.target/powerpc/gnuattr2.c index 32a4ba2..70efb7b 100644 --- a/gcc/testsuite/gcc.target/powerpc/gnuattr2.c +++ b/gcc/testsuite/gcc.target/powerpc/gnuattr2.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-linux-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mpower9-vector -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mvsx -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ /* { dg-final { scan-assembler "gnu_attribute 4, 13" } } */ /* Check that if we can do the long double operation without doing an emulator diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packs.c b/gcc/testsuite/gcc.target/powerpc/mmx-packs.c index dd8cc96..b6da584 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-packs.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packs.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c index ecfe2d6..dff0e3c 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c index 4ca69b1..63f787a 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c index 2f74e13..54c63f0 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c index 0affc3a..7b4cc27 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c index ed7ca44..517de1d 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c index 16b7589..16afd1f 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddsb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c index d53e08a..166fb33 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddsw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c index 1336cdc..4cd3d3a 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddusb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c index 16f2ce8..8f41090 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddusw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c index 0768de7..be0b711 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-paddw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c index b4b62b3..58f93ad 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c index e9bc6d5..d3c9489 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c index ee90ab4..7e691e0 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpeqw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c index ab81bd4..d278386 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c index 8407472..39a8170 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c index 348d1bf..99d2a49 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pcmpgtw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c index 1a8bd3f..e92aa8b 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pmaddwd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c index 631324c..ce357702 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c index c3c33f5..9377dd7 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pmullw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c index 857d0d9..73b46e7 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-pslld-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c index 1c072f9..5671398 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psllw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c index a421a16..5f62c7a 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psrad-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c index 1f486ae..595bf5d 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psraw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c index 97c74f8..bfdade7a 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psrld-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c index 4b039e8..d3206a1 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psrlw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c index 6dfb88dc..9dee536 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubb-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c index 1785901..db4fd5e 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubd-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c index 70dff88a9..b74c9c0 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubsb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c index e204dd4..5dd89c9 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubsw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c index f98f550..3721887 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubusb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c index 52fbe41..eca45de 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubusw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c b/gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c index 04b57bf..1b70c1e 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-psubw-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c index 26c6f44..2a7363a 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhbw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c index 81b9f6d..040721a 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhdq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c index 8c44fe90..177ad52 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckhwd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c index 4030850..af9bf04 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklbw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c index df76e05..9a68bbc 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpckldq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c index ef8ae17..a8e61c2 100644 --- a/gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mmx-punpcklwd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/mul-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/mul-vectorize-1.c index ba01d5c..bd9e1f9 100644 --- a/gcc/testsuite/gcc.target/powerpc/mul-vectorize-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mul-vectorize-1.c @@ -1,5 +1,5 @@ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */ /* Test vectorizer can exploit ISA 2.07 instruction vmuluwm (Vector Multiply Unsigned Word Modulo) for both signed and unsigned word multiplication. */ diff --git a/gcc/testsuite/gcc.target/powerpc/mulkc3-2.c b/gcc/testsuite/gcc.target/powerpc/mulkc3-2.c index eee6de9..6c59a28 100644 --- a/gcc/testsuite/gcc.target/powerpc/mulkc3-2.c +++ b/gcc/testsuite/gcc.target/powerpc/mulkc3-2.c @@ -1,7 +1,8 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target longdouble128 } */ -/* { dg-options "-O2 -mpower8-vector -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* Check that complex multiply generates the right call when long double is IEEE 128-bit floating point. */ diff --git a/gcc/testsuite/gcc.target/powerpc/mulkc3-3.c b/gcc/testsuite/gcc.target/powerpc/mulkc3-3.c index b6d2bdf..54671f8 100644 --- a/gcc/testsuite/gcc.target/powerpc/mulkc3-3.c +++ b/gcc/testsuite/gcc.target/powerpc/mulkc3-3.c @@ -1,7 +1,8 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target longdouble128 } */ -/* { dg-options "-O2 -mpower8-vector -mabi=ibmlongdouble -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -mabi=ibmlongdouble -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* Check that complex multiply generates the right call when long double is IBM extended double floating point. */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst-v2.c b/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst-v2.c index f5c3858..7a62429 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst-v2.c +++ b/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst-v2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { le } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* Verify fix for problem where vec_xl and vec_xst are not recognized for the vector char and vector short cases on P8 only. diff --git a/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c b/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c index ed31e60..46d5d6f 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c +++ b/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { le } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* Verify fix for problem where vec_xl and vec_xst are not recognized for the vector char and vector short cases on P8 only. */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c index f1dd62c..47a5f88 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ #ifndef TYPE #define TYPE long long diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c index 102e1d1..d3aab19 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c index 33304fe..ca354c5 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -ftree-vectorize -fvect-cost-model=dynamic" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -ftree-vectorize -fvect-cost-model=dynamic" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c index 8329e2b..074d23c 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -ftree-vectorize -fvect-cost-model=dynamic" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -ftree-vectorize -fvect-cost-model=dynamic" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c index 1f50043..35b7e2a 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c index 0a349ba..6a10054 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ vector float dbl_to_float_p8 (double x) { return __builtin_vsx_xscvdpspn (x); } double float_to_dbl_p8 (vector float x) { return __builtin_vsx_xscvspdpn (x); } diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c index fcfac7c..9f2d80c 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c index 0cfbe68..d8f23d1 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c @@ -1,7 +1,8 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target int128 } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c b/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c index a86f05b..d990691 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -fno-math-errno" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -fno-math-errno" } */ float abs_sf (float *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c index 28b148c..c763187 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c @@ -1,8 +1,8 @@ /* { dg-do compile } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target int128 } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c b/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c index 856029f..6ac5d46 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ float load_store_sf (unsigned long num, diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c index c2ab68b..486ae40 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O3 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mdejagnu-cpu=power8 -mvsx" } */ /* { dg-final { scan-assembler "vbpermq" } } */ /* { dg-final { scan-assembler "mfvsrd" } } */ /* { dg-final { scan-assembler-not "stfd" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c index a58d959..a2dd1a4 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ #ifndef SIZE #define SIZE 1024 diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c index 78ff176..46dc318 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fvect-cost-model=dynamic" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c index 2f32b35..b464bdc 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fvect-cost-model=dynamic" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c index e767af3..1f2a0cd 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ #ifndef SIZE #define SIZE 1024 diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c index bd27a9e..1d16196 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */ #ifndef SIZE #define SIZE 1024 diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c b/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c index 9914f94..125252e 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-dimode1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Verify P9 changes to allow DImode into Altivec registers, and generate constants using XXSPLTIB. */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c b/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c index 6d74728..d4392d4 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-dimode2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Verify that large integer constants are loaded via direct move instead of being loaded from memory. */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-extract-1.c b/gcc/testsuite/gcc.target/powerpc/p9-extract-1.c index d7d3ad7..5c0f00e 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-extract-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-extract-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Test to make sure VEXTU{B,H,W}{L,R}X is generated for various vector extract operations for ISA 3.0 (-mcpu=power9). In addition, make sure that neither diff --git a/gcc/testsuite/gcc.target/powerpc/p9-extract-2.c b/gcc/testsuite/gcc.target/powerpc/p9-extract-2.c index ffbc6b9..824665a 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-extract-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-extract-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p9-extract-3.c b/gcc/testsuite/gcc.target/powerpc/p9-extract-3.c index 3c1361d..1317c59 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-extract-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-extract-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Test that under ISA 3.0 (-mcpu=power9), the compiler optimizes conversion to double after a vec_extract to use the VEXTRACTU{B,H} or XXEXTRACTUW diff --git a/gcc/testsuite/gcc.target/powerpc/p9-extract-4.c b/gcc/testsuite/gcc.target/powerpc/p9-extract-4.c index 347f63d..8968696 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-extract-4.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-extract-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* This file tests the extraction of 64-bit values. On Power 9, the direct move is prefered for the 64-bit extract as it is either lower latency or diff --git a/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-1.c b/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-1.c index 3ad8198..19b2c0d 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ void sc (signed char *p, double x) { *p = x; } void uc (unsigned char *p, double x) { *p = x; } diff --git a/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-2.c b/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-2.c index c7ea1c2..2356815 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ double sc (signed char *p) { return (double)*p; } double uc (unsigned char *p) { return (double)*p; } diff --git a/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c b/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c index 19701c8..fbb73a5 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-fpcvt-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Note that for unsigned cases, the differences from those ones in p9-fpcvt-2.c is that they will be converted to int implicitly first diff --git a/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-1.c b/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-1.c index 5539429..936a037 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O3" } */ /* { dg-final { scan-assembler "lxvx" } } */ /* { dg-final { scan-assembler "stxvx" } } */ /* { dg-final { scan-assembler-not "lxvd2x" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-2.c b/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-2.c index edab616..b8e1e78 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O1" } */ /* { dg-final { scan-assembler "lxvx" } } */ /* { dg-final { scan-assembler "stvewx" } } */ /* { dg-final { scan-assembler-not "lxvd2x" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c b/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c index 3cb28ee..2d3f63f 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-lxvx-stxvx-3.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target ppc_float128_sw } */ -/* { dg-options "-mdejagnu-cpu=power9 -O3 -mfloat128" } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O3 -mfloat128" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-final { scan-assembler "lxvx" } } */ /* { dg-final { scan-assembler "stxvx" } } */ /* { dg-final { scan-assembler-not "lxvd2x" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c b/gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c index 686fdcc..616c2f0 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -mpower9-minmax -ffast-math" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mpower9-minmax -ffast-math" } */ /* { dg-final { scan-assembler-not "fsel" } } */ /* { dg-final { scan-assembler "xscmpeqdp" } } */ /* { dg-final { scan-assembler "xscmpgtdp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c index 78a3d9a..73ec160 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -mpower9-minmax" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mpower9-minmax" } */ /* { dg-final { scan-assembler-not "fsel" } } */ /* { dg-final { scan-assembler "xscmpeqdp" } } */ /* { dg-final { scan-assembler "xscmpgtdp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c b/gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c index 3248b9a..c97eede 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -mpower9-minmax" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mpower9-minmax" } */ /* { dg-final { scan-assembler-not "xsmaxcdp" } } */ /* { dg-final { scan-assembler-not "xsmincdp" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-novsx.c b/gcc/testsuite/gcc.target/powerpc/p9-novsx.c index d847274..7192676 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-novsx.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-novsx.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -mno-vsx -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -mno-vsx -O1" } */ /* { dg-final { scan-assembler-times "lvx %?v?2,%?r?3" 1 } } */ /* { dg-final { scan-assembler-times "stvx %?v?2,%?r?3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-options-1.c b/gcc/testsuite/gcc.target/powerpc/p9-options-1.c index 5685b4a..9da4d36 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-options-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-options-1.c @@ -1,11 +1,11 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -mno-power9-vector" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mno-vsx" } */ #include /* This program's "test for excess errors" demonstrates that combining - the target options -mcpu=power9 and -mno-power9-vector does not + the target options -mcpu=power9 and -mno-vsx does not result in an error. A previous version of the compiler aborted with the error message: @@ -14,7 +14,7 @@ when these two options were used in combination. The newer version of the compiler, instead, automatically disables - power9-dform when the -mno-power9-vector command-line option is + power9-dform when the -mno-vsx command-line option is specified. */ int test_any_equal (vector bool char *arg1_p, vector bool char *arg2_p) diff --git a/gcc/testsuite/gcc.target/powerpc/p9-permute.c b/gcc/testsuite/gcc.target/powerpc/p9-permute.c index b9bf05a..9ac9493 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-permute.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-permute.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p9-sign_extend-runnable.c b/gcc/testsuite/gcc.target/powerpc/p9-sign_extend-runnable.c index 03c0f12..f051499 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-sign_extend-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-sign_extend-runnable.c @@ -1,6 +1,6 @@ /* { dg-do run { target { *-*-linux* && { lp64 && p9vector_hw } } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9 -save-temps" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx -save-temps" } */ /* These builtins were not defined until ISA 3.1 but only require ISA 3.0 support. */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-1.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-1.c index ecb8d26..72ff87c 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-splat-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c index efbe7e1..5549250 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-3.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-3.c index 3cfacb29..8bd3fec 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-splat-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c index b317445..886a75c 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p9-splat-5.c b/gcc/testsuite/gcc.target/powerpc/p9-splat-5.c index 46faa38..3f9e729 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-splat-5.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-splat-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* { dg-final { scan-assembler "vspltish" } } */ /* { dg-final { scan-assembler-not "xxspltib" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vbpermd.c b/gcc/testsuite/gcc.target/powerpc/p9-vbpermd.c index b26a8f9..83606dd 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vbpermd.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vbpermd.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Verify P9 vector bit-permute doubleword instruction. */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-1.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-1.c index f57d945..e28da9e 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-1.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=1" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-2.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-2.c index 1985640..499dcef 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-2.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=1" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-3.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-3.c index eaea96d..cf28122 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-3.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=1" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-4.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-4.c index 0199132..83c67ff 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-4.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-4.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=1" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-5.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-5.c index c68faa8..0f31dcd 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-5.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-5.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=1" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-6.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-6.c index 18076cc..ac4de8f 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-6.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-6.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=1" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c index 4e37c0a..89f8d34 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-7.c @@ -1,7 +1,7 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ /* Pass cunroll isn't disabled by -fno-unroll-loops, so use explicit disabling option for it. */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -ffast-math -fdisable-tree-cunroll" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -ffast-math -fdisable-tree-cunroll" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=1" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-8.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-8.c index 0f3cd07..fbd1a35 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-8.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-epil-8.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=1" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c index 2818bac..a501873 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-1.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c index b476910..d30feff 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-2.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-3.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-3.c index 0f50242..ecef0fd 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-3.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-4.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-4.c index 20ddfb3..0c8f223 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-4.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-4.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-5.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-5.c index 0bad693..0165eed 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-5.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-5.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c index a73178e..ff66a11 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-6.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c index b50ff3c..f5b2d1a 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-7.c @@ -1,7 +1,7 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ /* Pass cunroll isn't disabled by -fno-unroll-loops, so use explicit disabling option for it. */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -ffast-math -fdisable-tree-cunroll" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -ffast-math -fdisable-tree-cunroll" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-8.c b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-8.c index 94f2aa4..daf62ac 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-8.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vec-length-full-8.c @@ -1,5 +1,5 @@ -/* { dg-do compile { target { lp64 && powerpc_p9vector_ok } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ +/* { dg-do compile { target { lp64 && powerpc_vsx_ok } } } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fno-trapping-math" } */ /* { dg-additional-options "--param=vect-partial-vector-usage=2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vneg.c b/gcc/testsuite/gcc.target/powerpc/p9-vneg.c index 7d6e9bc..e07bc43 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vneg.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vneg.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Verify P9 vector negate instructions. */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c index 8f6f123..978ddef 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vparity.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vparity.c @@ -1,8 +1,8 @@ /* { dg-do compile { target lp64 } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target int128 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p9-vpermr.c b/gcc/testsuite/gcc.target/powerpc/p9-vpermr.c index 6f87640..07c86e6 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-vpermr.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-vpermr.c @@ -1,6 +1,6 @@ /* { dg-do compile { target le } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Test generation of VPERMR/XXPERMR on ISA 3.0 in little endian. */ diff --git a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c index a449dda..956f6c1 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O3" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c index a14ac68..7e89daa 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-3.c b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-3.c index 62a946f..efb9acf 100644 --- a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-3.c +++ b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Verify that the XXBR{H,W} instructions are generated if the value is forced to be in a vector register, and XXBRD is generated all of the diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-fortran/pr80108-1.f90 b/gcc/testsuite/gcc.target/powerpc/ppc-fortran/pr80108-1.f90 index dac5c36..00392b5 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-fortran/pr80108-1.f90 +++ b/gcc/testsuite/gcc.target/powerpc/ppc-fortran/pr80108-1.f90 @@ -1,6 +1,6 @@ ! Originally contributed by Tobias Burnas. ! { dg-do compile { target { powerpc*-*-* } } } -! { dg-require-effective-target powerpc_p9vector_ok } +! { dg-require-effective-target powerpc_vsx_ok } ! { dg-options "-mdejagnu-cpu=405 -mpower9-minmax -mfloat128" } ! { dg-excess-errors "expect error due to conflicting target options" } ! Since the error message is not associated with a particular line diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round2.c b/gcc/testsuite/gcc.target/powerpc/ppc-round2.c index bebecfa..c50f008 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-round2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* { dg-final { scan-assembler-times "fcfid \|xscvsxddp " 2 } } */ /* { dg-final { scan-assembler-times "fcfids \|xscvsxdsp " 2 } } */ /* { dg-final { scan-assembler-times "fctiwz \|xscvdpsxws " 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round3.c b/gcc/testsuite/gcc.target/powerpc/ppc-round3.c index 043fce7..873c90a 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-round3.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ /* { dg-final { scan-assembler-times "fcfid \|xscvsxddp " 2 } } */ /* { dg-final { scan-assembler-times "fcfids \|xscvsxdsp " 2 } } */ /* { dg-final { scan-assembler-times "fctiwz \|xscvdpsxws " 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr100866-1.c b/gcc/testsuite/gcc.target/powerpc/pr100866-1.c index 63872f2..856d7b7 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr100866-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr100866-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* { dg-final { scan-assembler-not {\mxxlnor\M} } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr100866-2.c b/gcc/testsuite/gcc.target/powerpc/pr100866-2.c index 4357d1b..79193cf 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr100866-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr100866-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* { dg-final { scan-assembler {\mvspltish\M} } } */ /* { dg-final { scan-assembler {\mvrlh\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr103124.c b/gcc/testsuite/gcc.target/powerpc/pr103124.c index dc7bb9c..c6942e4 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr103124.c +++ b/gcc/testsuite/gcc.target/powerpc/pr103124.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target int128 } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ /* { dg-final { scan-assembler-not {\mmr\M} } } */ vector __int128 add (long long a) diff --git a/gcc/testsuite/gcc.target/powerpc/pr104015-1.c b/gcc/testsuite/gcc.target/powerpc/pr104015-1.c index 895c243..272499c 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr104015-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr104015-1.c @@ -1,5 +1,5 @@ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ /* As PR104015, we don't expect vectorizer will re-try some vector modes for epilogues on Power9, since Power9 doesn't support partial vector diff --git a/gcc/testsuite/gcc.target/powerpc/pr104124.c b/gcc/testsuite/gcc.target/powerpc/pr104124.c index 30e3b6f..7859ca2 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr104124.c +++ b/gcc/testsuite/gcc.target/powerpc/pr104124.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-mdejagnu-cpu=power8 -mpower8-vector -O2" } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-final { scan-assembler {\mvspltisw\M} } } */ /* { dg-final { scan-assembler {\mvupkhsw\M} } } */ /* { dg-final { scan-assembler-not {\mlvx\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr104239-1.c b/gcc/testsuite/gcc.target/powerpc/pr104239-1.c index eacdedd..8c1862a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr104239-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr104239-1.c @@ -1,7 +1,7 @@ /* PR target/104239 */ /* { dg-do compile } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8 -DNO_WARN_X86_INTRINSICS" } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx -DNO_WARN_X86_INTRINSICS" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ #if __has_include() #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr104239-2.c b/gcc/testsuite/gcc.target/powerpc/pr104239-2.c index 1bf316f..b021550 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr104239-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr104239-2.c @@ -1,7 +1,7 @@ /* PR target/104239 */ /* { dg-do compile } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8 -DNO_WARN_X86_INTRINSICS" } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx -DNO_WARN_X86_INTRINSICS" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ #if __has_include() #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr104239-3.c b/gcc/testsuite/gcc.target/powerpc/pr104239-3.c index 6d64e5d..7436597 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr104239-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr104239-3.c @@ -1,7 +1,7 @@ /* PR target/104239 */ /* { dg-do compile } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8 -DNO_WARN_X86_INTRINSICS -std=c89" } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx -DNO_WARN_X86_INTRINSICS -std=c89" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr106769-p8.c b/gcc/testsuite/gcc.target/powerpc/pr106769-p8.c index e7cdbc7..51e7247 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106769-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106769-p8.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-require-effective-target has_arch_ppc64 } */ #include "pr106769.h" diff --git a/gcc/testsuite/gcc.target/powerpc/pr106769-p9.c b/gcc/testsuite/gcc.target/powerpc/pr106769-p9.c index 2248b52..b602e7d 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106769-p9.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106769-p9.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* { dg-require-effective-target has_arch_ppc64 } */ #include "pr106769.h" diff --git a/gcc/testsuite/gcc.target/powerpc/pr107412.c b/gcc/testsuite/gcc.target/powerpc/pr107412.c index 4526ea8..9e21f96 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr107412.c +++ b/gcc/testsuite/gcc.target/powerpc/pr107412.c @@ -1,6 +1,6 @@ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target lp64 } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -ftree-vectorize -fno-vect-cost-model -funroll-loops -fno-tree-loop-distribute-patterns --param vect-partial-vector-usage=2 -fdump-tree-optimized" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -funroll-loops -fno-tree-loop-distribute-patterns --param vect-partial-vector-usage=2 -fdump-tree-optimized" } */ /* Verify there is only one IFN call LEN_LOAD and IFN_STORE separately. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr108396.c b/gcc/testsuite/gcc.target/powerpc/pr108396.c index a783f08..262a446 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr108396.c +++ b/gcc/testsuite/gcc.target/powerpc/pr108396.c @@ -1,6 +1,6 @@ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target int128 } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* Verify there is no error message. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr110429.c b/gcc/testsuite/gcc.target/powerpc/pr110429.c index d0ea3e5..b9241ed 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr110429.c +++ b/gcc/testsuite/gcc.target/powerpc/pr110429.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* { dg-require-effective-target has_arch_ppc64 } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr111449-1.c b/gcc/testsuite/gcc.target/powerpc/pr111449-1.c index 0c9e176..ce97e4f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr111449-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr111449-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* Ensure vector mode is used for 16-byte by pieces equality compare. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr111449-2.c b/gcc/testsuite/gcc.target/powerpc/pr111449-2.c index 7003bdc..49871ca 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr111449-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr111449-2.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { has_arch_pwr8 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mvsx -O2" } */ /* Ensure 16-byte by pieces move is enabled. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr37191.c b/gcc/testsuite/gcc.target/powerpc/pr37191.c index 1b69c3b7..bff90df 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr37191.c +++ b/gcc/testsuite/gcc.target/powerpc/pr37191.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/pr57744.c b/gcc/testsuite/gcc.target/powerpc/pr57744.c index 617ac56..9e51dc7 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr57744.c +++ b/gcc/testsuite/gcc.target/powerpc/pr57744.c @@ -1,7 +1,7 @@ /* { dg-do run { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ void abort (void); diff --git a/gcc/testsuite/gcc.target/powerpc/pr58673-1.c b/gcc/testsuite/gcc.target/powerpc/pr58673-1.c index dd2194f..9ebe3c5 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr58673-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr58673-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O1" } */ enum typecode { diff --git a/gcc/testsuite/gcc.target/powerpc/pr58673-2.c b/gcc/testsuite/gcc.target/powerpc/pr58673-2.c index d70f061..d59cc21 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr58673-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr58673-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -funroll-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -funroll-loops" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr60137.c b/gcc/testsuite/gcc.target/powerpc/pr60137.c index 6ec6adf..1b1b69a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr60137.c +++ b/gcc/testsuite/gcc.target/powerpc/pr60137.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -mno-vsx" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -mno-vsx" } */ /* target/60137, compiler got a 'could not split insn error'. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr60203.c b/gcc/testsuite/gcc.target/powerpc/pr60203.c index a5a574a..56b676f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr60203.c +++ b/gcc/testsuite/gcc.target/powerpc/pr60203.c @@ -1,8 +1,8 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target longdouble128 } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ #if defined(__LONG_DOUBLE_IEEE128__) /* If long double is IEEE 128-bit, we need to use the __ibm128 type instead of diff --git a/gcc/testsuite/gcc.target/powerpc/pr66144-1.c b/gcc/testsuite/gcc.target/powerpc/pr66144-1.c index dea4d00..4fd5fc5 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr66144-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr66144-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Verify that we optimize vector1 = (vector2 == vector3) by not loading up 0/-1. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr66144-2.c b/gcc/testsuite/gcc.target/powerpc/pr66144-2.c index 7f4a193..6b12f25 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr66144-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr66144-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* Verify that we optimize vector1 = (vector2 != vector3) by not loading up 0/-1. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr66144-3.c b/gcc/testsuite/gcc.target/powerpc/pr66144-3.c index 488bb6c..46bf2e3 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr66144-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr66144-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize" } */ /* Verify that we can optimize a vector conditional move, where one of the arms is all 1's into using the mask as one of the inputs to XXSEL. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr68163.c b/gcc/testsuite/gcc.target/powerpc/pr68163.c index 25371ca..736fad1 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr68163.c +++ b/gcc/testsuite/gcc.target/powerpc/pr68163.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* Make sure that the register allocator does not move SF values to GPR registers in order to do an offsettable store. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr69548.c b/gcc/testsuite/gcc.target/powerpc/pr69548.c index 6782f6b..259d8d2 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr69548.c +++ b/gcc/testsuite/gcc.target/powerpc/pr69548.c @@ -1,7 +1,7 @@ /* { dg-do assemble { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -Os -mbig" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -Os -mbig" } */ __int128 quad_exchange (__int128 *ptr, __int128 newval) diff --git a/gcc/testsuite/gcc.target/powerpc/pr70669.c b/gcc/testsuite/gcc.target/powerpc/pr70669.c index 225681d..3082e29 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr70669.c +++ b/gcc/testsuite/gcc.target/powerpc/pr70669.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8 -mfloat128" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx -mfloat128" } */ #ifndef TYPE #define TYPE __float128 diff --git a/gcc/testsuite/gcc.target/powerpc/pr71186.c b/gcc/testsuite/gcc.target/powerpc/pr71186.c index 3d01609..acc354f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71186.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71186.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ static unsigned short x[(16384/sizeof(unsigned short))] __attribute__ ((aligned (16))); static unsigned short y[(16384/sizeof(unsigned short))] __attribute__ ((aligned (16))); diff --git a/gcc/testsuite/gcc.target/powerpc/pr71309.c b/gcc/testsuite/gcc.target/powerpc/pr71309.c index e1cbcea..97489ad 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71309.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71309.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target lp64 } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ #define TYPE void* #define TYPE2 void* diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c index 52e2295..7009d99 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71656-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-1.c @@ -1,7 +1,8 @@ /* Test for reload ICE arising from POWER9 Vector Dform code generation. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O1 -mpower9-vector" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O1 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ typedef __attribute__((altivec(vector__))) int type_t; type_t diff --git a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c index c2a054f..9ec1fca 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71656-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71656-2.c @@ -1,7 +1,8 @@ /* Test for reload ICE arising from POWER9 Vector Dform code generation. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O3 -mpower9-vector -funroll-loops -fno-aggressive-loop-optimizations" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mvsx -funroll-loops -fno-aggressive-loop-optimizations" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ typedef double vec[3]; struct vec_t diff --git a/gcc/testsuite/gcc.target/powerpc/pr71670.c b/gcc/testsuite/gcc.target/powerpc/pr71670.c index fec3e87..f6a38ebb 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71670.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71670.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O1" } */ volatile int a; int b; diff --git a/gcc/testsuite/gcc.target/powerpc/pr71698.c b/gcc/testsuite/gcc.target/powerpc/pr71698.c index e763741..a34c410 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71698.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71698.c @@ -1,8 +1,8 @@ /* Test for a reload ICE arising from trying to direct move a TDmode value. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target dfp } */ -/* { dg-options "-O1 -mdejagnu-cpu=power9" } */ +/* { dg-options "-O1 -mdejagnu-cpu=power9 -mvsx" } */ extern void testvad128 (int n, ...); void diff --git a/gcc/testsuite/gcc.target/powerpc/pr71720.c b/gcc/testsuite/gcc.target/powerpc/pr71720.c index dba540d..236faa6 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71720.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71720.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* Verify that we generate xxspltw ,,0 for V4SFmode splat. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr71977-1.c b/gcc/testsuite/gcc.target/powerpc/pr71977-1.c index 6b6ff09..ca60f20 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71977-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71977-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr71977-2.c b/gcc/testsuite/gcc.target/powerpc/pr71977-2.c index efb7288..85b7a22 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr71977-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr71977-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr72717.c b/gcc/testsuite/gcc.target/powerpc/pr72717.c index d6565fa..d9bea5a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr72717.c +++ b/gcc/testsuite/gcc.target/powerpc/pr72717.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ typedef long V __attribute__((__vector_size__(32))); diff --git a/gcc/testsuite/gcc.target/powerpc/pr72853.c b/gcc/testsuite/gcc.target/powerpc/pr72853.c index 89c73cb..de69bd9 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr72853.c +++ b/gcc/testsuite/gcc.target/powerpc/pr72853.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O3 -funroll-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O3 -funroll-loops" } */ /* derived from 20021120-1.c, compiled for -mcpu=power9. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-1.c b/gcc/testsuite/gcc.target/powerpc/pr78056-1.c index 0b9bec8..1af4229 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78056-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "" { powerpc*-*-aix* } } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-2.c b/gcc/testsuite/gcc.target/powerpc/pr78056-2.c index da650fa..5cda9d6 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78056-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-2.c @@ -1,8 +1,8 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-skip-if "" { powerpc_p9vector_ok } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-skip-if "" { powerpc_vsx_ok } } */ /* { dg-skip-if "" { powerpc*-*-aix* } } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-3.c b/gcc/testsuite/gcc.target/powerpc/pr78056-3.c index fcdfbfc..545e93b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78056-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-3.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "" { powerpc*-*-aix* } } */ /* { dg-options "-mdejagnu-cpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78056-4.c b/gcc/testsuite/gcc.target/powerpc/pr78056-4.c index 2a66359..0bea0f8 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78056-4.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78056-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* powerpc_vsx_ok represents power7 */ /* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-skip-if "" { powerpc_p8vector_ok } } */ +/* { dg-skip-if "" { powerpc_vsx_ok } } */ /* { dg-skip-if "" { powerpc*-*-aix* } } */ /* { dg-options "-mdejagnu-cpu=power7" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78102.c b/gcc/testsuite/gcc.target/powerpc/pr78102.c index 0b50910..7ae0d02 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78102.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78102.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8 -DNO_WARN_X86_INTRINSICS" } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx -DNO_WARN_X86_INTRINSICS" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr78543.c b/gcc/testsuite/gcc.target/powerpc/pr78543.c index ac2dfd5..9c5454d 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78543.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78543.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O1" } */ typedef long a; enum c { e, f, g, h, i, ab } j(); diff --git a/gcc/testsuite/gcc.target/powerpc/pr78604.c b/gcc/testsuite/gcc.target/powerpc/pr78604.c index 7a371af..f6ac7f1 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78604.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78604.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fdump-tree-vect-details -fno-unroll-loops" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fdump-tree-vect-details -fno-unroll-loops" } */ #ifndef SIZE #define SIZE 1024 diff --git a/gcc/testsuite/gcc.target/powerpc/pr78658.c b/gcc/testsuite/gcc.target/powerpc/pr78658.c index 303c4fc..228736a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78658.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78658.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* This caused an unrecognizable insn message on development versions of GCC 7. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr78953.c b/gcc/testsuite/gcc.target/powerpc/pr78953.c index 9ee8ead..a1b66cb 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr78953.c +++ b/gcc/testsuite/gcc.target/powerpc/pr78953.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c b/gcc/testsuite/gcc.target/powerpc/pr79004.c index 30cdeba..caf1f6c 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79004.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -mfloat128" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr79038-1.c b/gcc/testsuite/gcc.target/powerpc/pr79038-1.c index bf93595..fdf0c1a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79038-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79038-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -mfloat128" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */ #ifndef TYPE #define TYPE _Float128 diff --git a/gcc/testsuite/gcc.target/powerpc/pr79179.c b/gcc/testsuite/gcc.target/powerpc/pr79179.c index ed09702..f2f48c4 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79179.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79179.c @@ -1,6 +1,6 @@ /* { dg-do assemble { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O3" } */ /* Compile with -O3 -mcpu=power9. It originally generated diff --git a/gcc/testsuite/gcc.target/powerpc/pr79251.p8.c b/gcc/testsuite/gcc.target/powerpc/pr79251.p8.c index 4fc3ea0..7d83e72 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79251.p8.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79251.p8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c b/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c index 9312aa6..8ce6858 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79251.p9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr79354.c b/gcc/testsuite/gcc.target/powerpc/pr79354.c index c9b1bb5..cdb2c36 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79354.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79354.c @@ -1,7 +1,7 @@ /* PR target/79354 */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-final { scan-assembler-not {\mstxssp\M} } } */ int b, f, g; diff --git a/gcc/testsuite/gcc.target/powerpc/pr79544.c b/gcc/testsuite/gcc.target/powerpc/pr79544.c index 3f78248..172b951 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79544.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79544.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr79799-1.c b/gcc/testsuite/gcc.target/powerpc/pr79799-1.c index 8d56840..a8d8d1d 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79799-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79799-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr79799-2.c b/gcc/testsuite/gcc.target/powerpc/pr79799-2.c index fb1dd8c..fe27e5c 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79799-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79799-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr79799-3.c b/gcc/testsuite/gcc.target/powerpc/pr79799-3.c index c1fd7aa..5426016 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79799-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79799-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr79799-5.c b/gcc/testsuite/gcc.target/powerpc/pr79799-5.c index be01bb8..037bfc0 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79799-5.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79799-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr79907.c b/gcc/testsuite/gcc.target/powerpc/pr79907.c index 385d03a..9597201 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79907.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79907.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ int foo (short a[], int x) { diff --git a/gcc/testsuite/gcc.target/powerpc/pr79951.c b/gcc/testsuite/gcc.target/powerpc/pr79951.c index 6b070c5..796fa7c 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr79951.c +++ b/gcc/testsuite/gcc.target/powerpc/pr79951.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -S -mno-cmpb" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -S -mno-cmpb" } */ float testf (float x, float y) { diff --git a/gcc/testsuite/gcc.target/powerpc/pr80098-1.c b/gcc/testsuite/gcc.target/powerpc/pr80098-1.c index 202c4bf..f22c8d9 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80098-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80098-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -mno-power9-vector -mpower9-minmax" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mno-vsx -mpower9-minmax" } */ int i; -/* { dg-error "'-mno-power9-vector' turns off '-mpower9-minmax'" "PR80098" { target *-*-* } 0 } */ +/* { dg-error "'-mno-vsx' turns off '-mpower9-minmax'" "PR80098" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr80098-2.c b/gcc/testsuite/gcc.target/powerpc/pr80098-2.c index 7bf474a..964b849 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80098-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80098-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -mno-power8-vector -mcrypto" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mno-vsx -mcrypto" } */ int i; -/* { dg-error "'-mno-power8-vector' turns off '-mcrypto'" "PR80098" { target *-*-* } 0 } */ +/* { dg-error "'-mno-vsx' turns off '-mcrypto'" "PR80098" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c index 7198611..b846e19 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80315-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ int main() diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c index 0f77f77..64b0628 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80315-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ int main () diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c index 398c512..2c335e7 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80315-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c index 4326ff6..c003c9b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80315-4.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80315-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c index d041d96..627e524 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c @@ -1,9 +1,9 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* Now O2 enables vectorization by default, which generates unexpected VSR to GPR movement for vector construction, so simply disable it. */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -fno-tree-vectorize" } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -fno-tree-vectorize" } */ /* Make sure that STXSSPX is generated for float scalars in Altivec registers on power7 instead of moving the value to a FPR register and doing a X-FORM diff --git a/gcc/testsuite/gcc.target/powerpc/pr80695-p8.c b/gcc/testsuite/gcc.target/powerpc/pr80695-p8.c index 9719f29..7d2d818 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80695-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80695-p8.c @@ -1,6 +1,6 @@ -/* { dg-do compile { target { powerpc_p8vector_ok } } } */ +/* { dg-do compile { target { powerpc_vsx_ok } } } */ /* { dg-require-effective-target vect_int } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -fdump-tree-slp-details" } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -fdump-tree-slp-details" } */ /* PR80695: Verify cost model for vec_construct on POWER8. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr80695-p9.c b/gcc/testsuite/gcc.target/powerpc/pr80695-p9.c index dc2488a..f35e45b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80695-p9.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80695-p9.c @@ -1,6 +1,6 @@ -/* { dg-do compile { target { powerpc_p9vector_ok } } } */ +/* { dg-do compile { target { powerpc_vsx_ok } } } */ /* { dg-require-effective-target vect_int } */ -/* { dg-options "-mdejagnu-cpu=power9 -O3 -fdump-tree-slp-details" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O3 -fdump-tree-slp-details" } */ /* PR80695: Verify cost model for vec_construct on POWER9. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr80718.c b/gcc/testsuite/gcc.target/powerpc/pr80718.c index a72fc94..8ef2e80 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr80718.c +++ b/gcc/testsuite/gcc.target/powerpc/pr80718.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -ffast-math" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -ffast-math" } */ /* Taken from the Spec 2006 milc brenchmark. Ultimately, GCC wants to generate a DF splat from offsettable memory. The register allocator decided it was diff --git a/gcc/testsuite/gcc.target/powerpc/pr81348.c b/gcc/testsuite/gcc.target/powerpc/pr81348.c index 16a46c8..c275d5b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr81348.c +++ b/gcc/testsuite/gcc.target/powerpc/pr81348.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -Og" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -Og" } */ /* PR target/81348: Compiler died in doing short->float conversion due to using the wrong register in a define_split. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr81622.c b/gcc/testsuite/gcc.target/powerpc/pr81622.c index 34dcfb2..4cd4528 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr81622.c +++ b/gcc/testsuite/gcc.target/powerpc/pr81622.c @@ -1,7 +1,7 @@ /* PR target/81622 */ /* { dg-do compile { target { powerpc*-*-linux* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ void foo (void) diff --git a/gcc/testsuite/gcc.target/powerpc/pr81959.c b/gcc/testsuite/gcc.target/powerpc/pr81959.c index c4cc373..31d2163 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr81959.c +++ b/gcc/testsuite/gcc.target/powerpc/pr81959.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mpower9-vector -O2 -mfloat128" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2 -mfloat128" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ /* PR 81959, the compiler raised on unrecognizable insn message in converting int to __float128, where the int had a PRE_INC in the address. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr82748-1.c b/gcc/testsuite/gcc.target/powerpc/pr82748-1.c index 15a746b..fe053d9 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr82748-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr82748-1.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mpower9-vector -O2 -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2 -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ /* Make sure the old 'q' builtin functions work correctly when the long double default has been changed to be IEEE 128-bit floating point. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr82748-2.c b/gcc/testsuite/gcc.target/powerpc/pr82748-2.c index 0079394..fb8e9a5 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr82748-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr82748-2.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mpower9-vector -O2 -mabi=ibmlongdouble -Wno-psabi" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2 -mabi=ibmlongdouble -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power9" { target { ! has_arch_pwr9 } } } */ /* Make sure the old 'q' builtin functions work correctly when the long double default uses the IBM double-double format. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr83862.c b/gcc/testsuite/gcc.target/powerpc/pr83862.c index 3cadb57..e605194 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr83862.c +++ b/gcc/testsuite/gcc.target/powerpc/pr83862.c @@ -1,8 +1,9 @@ /* PR target/83862.c */ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-require-effective-target ppc_float128_sw } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2 -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2 -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* On little endian systems, optimizing signbit of IEEE 128-bit values from memory could abort if the memory address was indexed (reg+reg). The diff --git a/gcc/testsuite/gcc.target/powerpc/pr84154-1.c b/gcc/testsuite/gcc.target/powerpc/pr84154-1.c index c7c61be..286b885 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr84154-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr84154-1.c @@ -1,7 +1,8 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mpower8-vector -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* PR target/84154. Make sure conversion to char/short does not generate a store and a load on ISA 2.07 and newer systems. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr84154-2.c b/gcc/testsuite/gcc.target/powerpc/pr84154-2.c index acf00cb..64b355f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr84154-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr84154-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* PR target/84154. Make sure on ISA 2.07 (power8) that we store the result of a conversion to char/short using an offsettable address does not generate diff --git a/gcc/testsuite/gcc.target/powerpc/pr84154-3.c b/gcc/testsuite/gcc.target/powerpc/pr84154-3.c index 6afadc2..3bb663e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr84154-3.c +++ b/gcc/testsuite/gcc.target/powerpc/pr84154-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* PR target/84154. Make sure on ISA 3.0 we store the result of a conversion to char/short using an offsettable address does not generate direct moves diff --git a/gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c b/gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c index 5e973e0..9f31986 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr84220-sld2.c @@ -2,8 +2,9 @@ /* Test to ensure we generate invalid parameter errors rather than an ICE when calling builtin_vec_sld() with invalid parameters. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-maltivec -mpower8-vector" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr84226.c b/gcc/testsuite/gcc.target/powerpc/pr84226.c index aae922b..e3e771f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr84226.c +++ b/gcc/testsuite/gcc.target/powerpc/pr84226.c @@ -1,6 +1,6 @@ /* PR target/84226 */ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mpower9-misc -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -mpower9-misc -O1" } */ #include "builtins-revb-runnable.c" diff --git a/gcc/testsuite/gcc.target/powerpc/pr85456.c b/gcc/testsuite/gcc.target/powerpc/pr85456.c index 3f327fc..7fb7a7a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr85456.c +++ b/gcc/testsuite/gcc.target/powerpc/pr85456.c @@ -1,7 +1,8 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target longdouble128 } */ -/* { dg-options "-O2 -mpower8-vector -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -mabi=ieeelongdouble -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* Check that the __builtin_powil generates a call to the correct function when long double uses IEEE 128-bit floating point. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c index 018e1cf..ea759d5 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c @@ -3,12 +3,13 @@ explicitly specifies -fwrapv, which is a condition for the gimple folding of the vec_sl() intrinsic. */ -/* specify -mpower8-vector, which provides vec_sl(long long,...) support. */ +/* specify -mcpu=power8 -mvsx, which provides vec_sl(long long,...) support. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target lp64 } */ -/* { dg-options "-maltivec -O3 -fwrapv -mpower8-vector " } */ +/* { dg-options "-maltivec -O3 -fwrapv -mvsx " } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-longlong.c index b862091..8a7a9ce 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr86731-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/pr86731-longlong.c @@ -2,9 +2,10 @@ left shift properly. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target lp64 } */ -/* { dg-options "-maltivec -O3 -mpower8-vector " } */ +/* { dg-options "-maltivec -O3 -mvsx " } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558-p8.c b/gcc/testsuite/gcc.target/powerpc/pr88558-p8.c index fffb5b8..c1fe3e0 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr88558-p8.c +++ b/gcc/testsuite/gcc.target/powerpc/pr88558-p8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -fno-math-errno -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -fno-math-errno -mdejagnu-cpu=power8 -mvsx" } */ /* -fno-math-errno is required to make {i,l,ll}rint{,f} inlined */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr88845.c b/gcc/testsuite/gcc.target/powerpc/pr88845.c index f3d02c5..002690a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr88845.c +++ b/gcc/testsuite/gcc.target/powerpc/pr88845.c @@ -1,7 +1,7 @@ /* { dg-do compile { target powerpc*-*-linux* } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* { dg-final { scan-assembler {\mmtvsrd\M} { target { lp64 } } } } */ /* { dg-final { scan-assembler {\mxscvspdpn\M} { target { lp64 } } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr90763.c b/gcc/testsuite/gcc.target/powerpc/pr90763.c index 2f4c4f4..0094b4ef 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr90763.c +++ b/gcc/testsuite/gcc.target/powerpc/pr90763.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target int128 } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ /* PR90763: PowerPC vec_xl_len should take const. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr91903.c b/gcc/testsuite/gcc.target/powerpc/pr91903.c index 7f9470e..b304a9e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr91903.c +++ b/gcc/testsuite/gcc.target/powerpc/pr91903.c @@ -1,6 +1,6 @@ /* { dg-do compile */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/pr92923-2.c b/gcc/testsuite/gcc.target/powerpc/pr92923-2.c index ebecb69..9dea626 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr92923-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr92923-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -fdump-tree-gimple" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -fdump-tree-gimple" } */ /* Verify that overloaded built-ins for "eqv", "nand" and "orc" do not produce VIEW_CONVERT_EXPR operations on their operands. Like so: diff --git a/gcc/testsuite/gcc.target/powerpc/pr96933-1.c b/gcc/testsuite/gcc.target/powerpc/pr96933-1.c index 71d7208..7c42572 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr96933-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr96933-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ /* Test vector constructions with char/short type values whether use 128bit direct move instructions mtvsrdd on Power9 or later, rather than transfering diff --git a/gcc/testsuite/gcc.target/powerpc/pr96933-2.c b/gcc/testsuite/gcc.target/powerpc/pr96933-2.c index 9fa1512..2eacc24 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr96933-2.c +++ b/gcc/testsuite/gcc.target/powerpc/pr96933-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* Test vector constructions with char/short type values whether use direct move instructions like mtvsrd/mtvsrwz on Power8, rather than transfering diff --git a/gcc/testsuite/gcc.target/powerpc/pr97019.c b/gcc/testsuite/gcc.target/powerpc/pr97019.c index 81b1bda..d82866b 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr97019.c +++ b/gcc/testsuite/gcc.target/powerpc/pr97019.c @@ -2,8 +2,8 @@ the built-in functions vec_ld/vec_st can use lxvd2x/stxvd2x (P8 big-endian) or lxv/stxv (P9 and later) for some cases, those rldicr instructions fed to them are necessary. */ -/* { dg-do compile { target { powerpc_p8vector_ok && le } } } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-do compile { target { powerpc_vsx_ok && le } } } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* Test there are no useless instructions "rldicr x,y,0,59" to align the addresses for lvx/stvx. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr98914.c b/gcc/testsuite/gcc.target/powerpc/pr98914.c index e4d78e3..54d9f48 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr98914.c +++ b/gcc/testsuite/gcc.target/powerpc/pr98914.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-Og -mvsx" } */ vector int diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c index c1667d9..b99b3e2 100644 --- a/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c +++ b/gcc/testsuite/gcc.target/powerpc/pragma_misc9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target lp64 } */ /* { dg-options "-mdejagnu-cpu=power9 -maltivec -O2" } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pragma_power8.c b/gcc/testsuite/gcc.target/powerpc/pragma_power8.c index cb0f308..8de815e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pragma_power8.c +++ b/gcc/testsuite/gcc.target/powerpc/pragma_power8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mdejagnu-cpu=power6 -maltivec -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/sad-vectorize-1.c b/gcc/testsuite/gcc.target/powerpc/sad-vectorize-1.c index 326a821..1049437 100644 --- a/gcc/testsuite/gcc.target/powerpc/sad-vectorize-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sad-vectorize-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O3 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mdejagnu-cpu=power9 -mvsx" } */ /* Verify that we vectorize this SAD loop using vabsdub. */ diff --git a/gcc/testsuite/gcc.target/powerpc/sad-vectorize-2.c b/gcc/testsuite/gcc.target/powerpc/sad-vectorize-2.c index 3ae5c48..73a68eb 100644 --- a/gcc/testsuite/gcc.target/powerpc/sad-vectorize-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sad-vectorize-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O3 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mdejagnu-cpu=power9 -mvsx" } */ /* Verify that we vectorize this SAD loop using vabsduh. */ diff --git a/gcc/testsuite/gcc.target/powerpc/signbit-1.c b/gcc/testsuite/gcc.target/powerpc/signbit-1.c index 1642bf4..21c5b77 100644 --- a/gcc/testsuite/gcc.target/powerpc/signbit-1.c +++ b/gcc/testsuite/gcc.target/powerpc/signbit-1.c @@ -1,8 +1,8 @@ /* { dg-do compile } */ /* { dg-require-effective-target lp64 } */ /* { dg-require-effective-target ppc_float128_sw } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -mfloat128" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -mfloat128" } */ int do_signbit_kf (__float128 a) { return __builtin_signbit (a); } int do_signbit_if (__ibm128 a) { return __builtin_signbit (a); } diff --git a/gcc/testsuite/gcc.target/powerpc/signbit-2.c b/gcc/testsuite/gcc.target/powerpc/signbit-2.c index 1b79291..a5b669f 100644 --- a/gcc/testsuite/gcc.target/powerpc/signbit-2.c +++ b/gcc/testsuite/gcc.target/powerpc/signbit-2.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target ppc_float128_sw } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2 -mfloat128" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */ int do_signbit_kf (__float128 *a) { return __builtin_signbit (*a); } diff --git a/gcc/testsuite/gcc.target/powerpc/sse-addps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-addps-1.c index c5827e1..5e2ffd3 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-addps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-addps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-addss-1.c b/gcc/testsuite/gcc.target/powerpc/sse-addss-1.c index 782bae8..004f7eb 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-addss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-addss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c index 9851621..e376d31 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c @@ -1,5 +1,6 @@ /* { dg-do run { target le } } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-andps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-andps-1.c index 3a63666..a4ffaac 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-andps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-andps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cmpss-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cmpss-1.c index 1826949d..ab8440a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cmpss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cmpss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtpi16ps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtpi16ps-1.c index 5b8b535..ca163ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtpi16ps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtpi16ps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtpi32ps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtpi32ps-1.c index 4b313b5..b5f300b 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtpi32ps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtpi32ps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtpi32x2ps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtpi32x2ps-1.c index a2539af..ea90185 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtpi32x2ps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtpi32x2ps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtpi8ps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtpi8ps-1.c index 5278980..c8ef487 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtpi8ps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtpi8ps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtpspi16-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtpspi16-1.c index ca66afc..6b0d9c7 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtpspi16-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtpspi16-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtpspi8-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtpspi8-1.c index fd80648..dcff665 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtpspi8-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtpspi8-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtpu16ps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtpu16ps-1.c index 0cf187b..90b1479 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtpu16ps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtpu16ps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtpu8ps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtpu8ps-1.c index 742f572..39803c2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtpu8ps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtpu8ps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtsi2ss-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtsi2ss-1.c index 42c2967..228a25a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtsi2ss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtsi2ss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtsi2ss-2.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtsi2ss-2.c index 8782d1f..7d934ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtsi2ss-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtsi2ss-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-1.c index c12a981..7bf48b0 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-2.c b/gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-2.c index 023446e..226b9f2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvttss2si-1.c b/gcc/testsuite/gcc.target/powerpc/sse-cvttss2si-1.c index c7f68af..ebbe1f8 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvttss2si-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvttss2si-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-cvttss2si-2.c b/gcc/testsuite/gcc.target/powerpc/sse-cvttss2si-2.c index af0a184..6cfa339 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-cvttss2si-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-cvttss2si-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-divps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-divps-1.c index 2e60dad..ac8cf91 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-divps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-divps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-divss-1.c b/gcc/testsuite/gcc.target/powerpc/sse-divss-1.c index c1dea93..ebeebc9 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-divss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-divss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-maxps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-maxps-1.c index f8a4422..5a88ca2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-maxps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-maxps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-maxps-2.c b/gcc/testsuite/gcc.target/powerpc/sse-maxps-2.c index 002aee9..9ce55ca 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-maxps-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-maxps-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-maxss-1.c b/gcc/testsuite/gcc.target/powerpc/sse-maxss-1.c index cc78fba..05634ce 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-maxss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-maxss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-minps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-minps-1.c index a27cd79..93b7bfe 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-minps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-minps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-minps-2.c b/gcc/testsuite/gcc.target/powerpc/sse-minps-2.c index 212c896..8d9b530 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-minps-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-minps-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-minss-1.c b/gcc/testsuite/gcc.target/powerpc/sse-minss-1.c index c1ada31..a3cdc5c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-minss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-minss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movaps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-movaps-1.c index de3bb39..418305b 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movaps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movaps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movaps-2.c b/gcc/testsuite/gcc.target/powerpc/sse-movaps-2.c index 964e291..6a86eec 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movaps-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movaps-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movhlps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-movhlps-1.c index 5bd2d90..3d8a325 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movhlps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movhlps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movhps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-movhps-1.c index a0666e5..2ee93f1 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movhps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movhps-1.c @@ -1,5 +1,6 @@ /* { dg-do run { target le } } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movhps-2.c b/gcc/testsuite/gcc.target/powerpc/sse-movhps-2.c index 29dde68..0f5523a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movhps-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movhps-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movlhps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-movlhps-1.c index cf44d69..b8cb1be 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movlhps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movlhps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c index 281d49c..622bc43 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c @@ -1,5 +1,6 @@ /* { dg-do run { target le } } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movlps-2.c b/gcc/testsuite/gcc.target/powerpc/sse-movlps-2.c index a2f1ed1..d098b1d 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movlps-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movlps-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movmskb-1.c b/gcc/testsuite/gcc.target/powerpc/sse-movmskb-1.c index ab68dc4..ed493d9 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movmskb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movmskb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movmskps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-movmskps-1.c index 427e349..8b621ff 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movmskps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movmskps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movss-1.c b/gcc/testsuite/gcc.target/powerpc/sse-movss-1.c index 8d09892..c7d005c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movss-2.c b/gcc/testsuite/gcc.target/powerpc/sse-movss-2.c index fe85f6f..6a885dc 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movss-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movss-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-movss-3.c b/gcc/testsuite/gcc.target/powerpc/sse-movss-3.c index 81d4def..17ca36b 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-movss-3.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-movss-3.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-mulps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-mulps-1.c index 59a58d1..6a0f68c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-mulps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-mulps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-mulss-1.c b/gcc/testsuite/gcc.target/powerpc/sse-mulss-1.c index da152dc..af90997 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-mulss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-mulss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-orps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-orps-1.c index 645c4ef..1a489fc 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-orps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-orps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-pavgw-1.c b/gcc/testsuite/gcc.target/powerpc/sse-pavgw-1.c index 6f8721a..d7361da 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-pavgw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-pavgw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-pmaxsw-1.c b/gcc/testsuite/gcc.target/powerpc/sse-pmaxsw-1.c index 456864b..7a9ceef 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-pmaxsw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-pmaxsw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-pmaxub-1.c b/gcc/testsuite/gcc.target/powerpc/sse-pmaxub-1.c index c046a09..7413dbd 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-pmaxub-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-pmaxub-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-pminsw-1.c b/gcc/testsuite/gcc.target/powerpc/sse-pminsw-1.c index ca81962..d8c09cf 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-pminsw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-pminsw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-pminub-1.c b/gcc/testsuite/gcc.target/powerpc/sse-pminub-1.c index 875e567..0bc263723 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-pminub-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-pminub-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-pmulhuw-1.c b/gcc/testsuite/gcc.target/powerpc/sse-pmulhuw-1.c index f2c2dd3..75cc9d5 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-pmulhuw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-pmulhuw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-psadbw-1.c b/gcc/testsuite/gcc.target/powerpc/sse-psadbw-1.c index c06f498..63e1dbb 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-psadbw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-psadbw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-rcpps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-rcpps-1.c index e90b729..dde2085 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-rcpps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-rcpps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-rsqrtps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-rsqrtps-1.c index 9f5d05a..98fabe7 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-rsqrtps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-rsqrtps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-shufps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-shufps-1.c index 29658b7..5f82fae 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-shufps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-shufps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-sqrtps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-sqrtps-1.c index ba865a4..a45971f 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-sqrtps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-sqrtps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-subps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-subps-1.c index 01a1a6c..636c66c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-subps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-subps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-subss-1.c b/gcc/testsuite/gcc.target/powerpc/sse-subss-1.c index 329404c..54c6ae1 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-subss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-subss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-1.c b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-1.c index ef3e4a7..8c43ef8 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-2.c b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-2.c index dbac47f..cf8c814 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-3.c b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-3.c index d407223..1d6b769 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-3.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-3.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-4.c b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-4.c index efaf673..f1c0702 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-4.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-4.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-5.c b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-5.c index 6d4468b..37b76f1 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-5.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-5.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-6.c b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-6.c index 76027d5..bc1d749 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-6.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-ucomiss-6.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-unpckhps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-unpckhps-1.c index 2526936..db5e3a6 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-unpckhps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-unpckhps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-unpcklps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-unpcklps-1.c index 060105a..c22188c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-unpcklps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-unpcklps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse-xorps-1.c b/gcc/testsuite/gcc.target/powerpc/sse-xorps-1.c index a0ae423..6083d9c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse-xorps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse-xorps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-addpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-addpd-1.c index 1cba6bc..e87c54e 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-addpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-addpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-addsd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-addsd-1.c index 634746a..00f2265 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-addsd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-addsd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c index 747bcc9..f6eebd5 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run { target le } } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-andpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-andpd-1.c index 5034bf9..0a9df60 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-andpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-andpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cmppd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cmppd-1.c index 1890535..458e0d4 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cmppd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cmppd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cmpsd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cmpsd-1.c index 0c8babf..3ca25a2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cmpsd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cmpsd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-1.c index ed3e5eb..f1d6c71 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-2.c index 941a4fd..8653ea7 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-3.c b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-3.c index 5bb03c3..94cffb7 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-3.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-3.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-4.c b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-4.c index 8732e1a..991436b 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-4.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-4.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-5.c b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-5.c index bbc12ae..e915c75 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-5.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-5.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-6.c b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-6.c index 1ec5089..0af8994 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-comisd-6.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-comisd-6.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtdq2pd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtdq2pd-1.c index 6565b42..141d838 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtdq2pd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtdq2pd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtdq2ps-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtdq2ps-1.c index 2b2c631..cfa2f12 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtdq2ps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtdq2ps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtpd2dq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtpd2dq-1.c index 26efa7f..4378723 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtpd2dq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtpd2dq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtpd2ps-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtpd2ps-1.c index 80be7fd..82096bd 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtpd2ps-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtpd2ps-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtps2dq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtps2dq-1.c index b9cd6f1..a2e493a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtps2dq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtps2dq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtps2pd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtps2pd-1.c index 8e1b67b..1217a25 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtps2pd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtps2pd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2si-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2si-1.c index 7f71527..4aead4a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2si-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2si-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2si-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2si-2.c index 00387a7..12a673e 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2si-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2si-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2ss-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2ss-1.c index fc76d3b..aedf55a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2ss-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtsd2ss-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtsi2sd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtsi2sd-1.c index 91f936c..d596f25 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtsi2sd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtsi2sd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtsi2sd-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtsi2sd-2.c index 2ed11ed..4150c54 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtsi2sd-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtsi2sd-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvtss2sd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvtss2sd-1.c index 5b3ebe6..19f2aa0 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvtss2sd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvtss2sd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvttpd2dq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvttpd2dq-1.c index 8ea6bef..29f1668 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvttpd2dq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvttpd2dq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvttps2dq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvttps2dq-1.c index 67ce967..695c3a4 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvttps2dq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvttps2dq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvttsd2si-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvttsd2si-1.c index 0523a13..5420bce 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvttsd2si-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvttsd2si-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-cvttsd2si-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-cvttsd2si-2.c index e944d4a..4331f83 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-cvttsd2si-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-cvttsd2si-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-divpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-divpd-1.c index 2350289..b2d660a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-divpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-divpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-divsd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-divsd-1.c index 6d5ac9a..7d441f8 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-divsd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-divsd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-maxpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-maxpd-1.c index 021cc4c..faebbd0 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-maxpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-maxpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-maxsd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-maxsd-1.c index 7bb70b7..494d5cb 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-maxsd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-maxsd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-minpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-minpd-1.c index 2af5a08..fc6c905 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-minpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-minpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-minsd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-minsd-1.c index 1d085a3..5ec5b64 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-minsd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-minsd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-mmx.c b/gcc/testsuite/gcc.target/powerpc/sse2-mmx.c index 1841a460..6e95a60 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-mmx.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-mmx.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector" } */ +/* { dg-options "-O3 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #include "sse2-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movhpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-movhpd-1.c index 168f470..a9f4fa9 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movhpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movhpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movhpd-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-movhpd-2.c index 4aacbe0..d89cb7d 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movhpd-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movhpd-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movlpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-movlpd-1.c index 38bbc9d..0a16551 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movlpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movlpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movlpd-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-movlpd-2.c index de17866..9d82a91 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movlpd-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movlpd-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movmskpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-movmskpd-1.c index 933412a..d66874e 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movmskpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movmskpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-movq-1.c index 1eaf2f3..47dbda1 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movq-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-movq-2.c index b3e3a79..a2e22d1 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movq-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movq-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movq-3.c b/gcc/testsuite/gcc.target/powerpc/sse2-movq-3.c index a1cc90d..8edfd43 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movq-3.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movq-3.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movsd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-movsd-1.c index 4f51376..f31bace 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movsd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movsd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movsd-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-movsd-2.c index f9c4934..cd611d1 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movsd-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movsd-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-movsd-3.c b/gcc/testsuite/gcc.target/powerpc/sse2-movsd-3.c index beb908d..040c403 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-movsd-3.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-movsd-3.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-mulpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-mulpd-1.c index 06adddd..76fdd89 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-mulpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-mulpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-mulsd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-mulsd-1.c index 02b50d0..2731924 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-mulsd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-mulsd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-orpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-orpd-1.c index cdc057e..e2c2362 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-orpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-orpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-packssdw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-packssdw-1.c index 9fbc750..d0c52a3 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-packssdw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-packssdw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-packsswb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-packsswb-1.c index ed09138..526eb33 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-packsswb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-packsswb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-packuswb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-packuswb-1.c index 3024e54e..123fc78 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-packuswb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-packuswb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-paddb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-paddb-1.c index f3dcfb0..2d93dc5 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-paddb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-paddb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-paddd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-paddd-1.c index 7d5307d..895a60c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-paddd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-paddd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-paddq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-paddq-1.c index 033a202..702deb8 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-paddq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-paddq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-paddsb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-paddsb-1.c index 3864185..9166f8c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-paddsb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-paddsb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-paddsw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-paddsw-1.c index 40e3665..6bffbd8 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-paddsw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-paddsw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-paddusb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-paddusb-1.c index b706609..85416a2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-paddusb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-paddusb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-paddusw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-paddusw-1.c index 9347177..0b62723 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-paddusw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-paddusw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-paddw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-paddw-1.c index 6b3a9e1..d50413d 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-paddw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-paddw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pand-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pand-1.c index 0ccd5f4..f2e8177 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pand-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pand-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pandn-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pandn-1.c index 05e8407..14938db 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pandn-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pandn-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pavgb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pavgb-1.c index dbe2d47..4fb4e98 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pavgb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pavgb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pavgw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pavgw-1.c index 1afff28..48c46be 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pavgw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pavgw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqb-1.c index 67c46cd..2f11b7b 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqd-1.c index 6707529..376c97a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqw-1.c index 03050d2..b1b5d40 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpeqw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtb-1.c index 3497a3b..893369e 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtd-1.c index 9f32a1c..13f1957 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtw-1.c index 1ed268f..ad4b50c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pcmpgtw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pextrw.c b/gcc/testsuite/gcc.target/powerpc/sse2-pextrw.c index 93aabfa..54926bd 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pextrw.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pextrw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pinsrw.c b/gcc/testsuite/gcc.target/powerpc/sse2-pinsrw.c index 7ca4859..aa87e29 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pinsrw.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pinsrw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pmaddwd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pmaddwd-1.c index 674c4d4..b20924c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pmaddwd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pmaddwd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pmaxsw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pmaxsw-1.c index 287ab3c..6bc48a2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pmaxsw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pmaxsw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pmaxub-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pmaxub-1.c index c0c939e..8ab8eec 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pmaxub-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pmaxub-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pminsw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pminsw-1.c index a9dc4ad..7f0c883 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pminsw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pminsw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pminub-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pminub-1.c index d00f92d..ac41d76 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pminub-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pminub-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pmovmskb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pmovmskb-1.c index 921cfe3..8740835 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pmovmskb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pmovmskb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pmulhuw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pmulhuw-1.c index 0b4dd2e..71bca1d 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pmulhuw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pmulhuw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pmulhw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pmulhw-1.c index b15d2e2..0d2e16a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pmulhw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pmulhw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pmullw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pmullw-1.c index 62a0524..e824e8e 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pmullw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pmullw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pmuludq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pmuludq-1.c index 1e41d46..883f1bb 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pmuludq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pmuludq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-por-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-por-1.c index b4ae880..b853856 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-por-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-por-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psadbw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psadbw-1.c index 82b8230..03b25cc 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psadbw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psadbw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pshufd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pshufd-1.c index b8263ba..b40ef6c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pshufd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pshufd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pshufhw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pshufhw-1.c index 7830fd4..e7c4f33 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pshufhw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pshufhw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pshuflw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pshuflw-1.c index 5a01475..3f407e8 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pshuflw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pshuflw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pslld-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pslld-1.c index 094dfb4..5b4e4dd 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pslld-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pslld-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pslld-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-pslld-2.c index 00a8596..f12b63e 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pslld-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pslld-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pslldq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pslldq-1.c index 22a31d0..7b3afb9 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pslldq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pslldq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psllq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psllq-1.c index bb1167f..63f40b0 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psllq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psllq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psllq-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-psllq-2.c index 253793e..d9d3d1c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psllq-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psllq-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psllw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psllw-1.c index beca23c..aafbe6b 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psllw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psllw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psllw-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-psllw-2.c index cb132aa..0ac9e40 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psllw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psllw-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psrad-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psrad-1.c index caf3e75..86abf25 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psrad-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psrad-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psrad-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-psrad-2.c index 782b47a..43f79ac 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psrad-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psrad-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psraw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psraw-1.c index c667338..86d97bd 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psraw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psraw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psraw-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-psraw-2.c index b00988c..c72e736 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psraw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psraw-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psrld-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psrld-1.c index 594cd15..28cf784 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psrld-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psrld-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psrld-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-psrld-2.c index 083c09a..806e68a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psrld-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psrld-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psrldq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psrldq-1.c index 41bfc4f..81b35d9 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psrldq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psrldq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psrlq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psrlq-1.c index 09df3e7..e33504f 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psrlq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psrlq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psrlq-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-psrlq-2.c index 3d160d9..ded7537 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psrlq-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psrlq-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psrlw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psrlw-1.c index 5104cf8..aabec71 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psrlw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psrlw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psrlw-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-psrlw-2.c index a2cef44..f94c50b 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psrlw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psrlw-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psubb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psubb-1.c index 112fe27..4ad02a2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psubb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psubb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psubd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psubd-1.c index 1390b0d..509d263 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psubd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psubd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psubq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psubq-1.c index 45d2148..162dab2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psubq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psubq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psubsb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psubsb-1.c index f1afb92..2b5ada2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psubsb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psubsb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psubsw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psubsw-1.c index 7dac4b0..b022b10 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psubsw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psubsw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psubusb-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psubusb-1.c index b9efa6c..623cd95 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psubusb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psubusb-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psubusw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psubusw-1.c index 125e5fe..5abc594 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psubusw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psubusw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-psubw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-psubw-1.c index 6eaee9a..138d793 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-psubw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-psubw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-punpckhbw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-punpckhbw-1.c index 1d25a4d..4c7e8a2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-punpckhbw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-punpckhbw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-punpckhdq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-punpckhdq-1.c index 0fbcb16..a89166c 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-punpckhdq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-punpckhdq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-punpckhqdq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-punpckhqdq-1.c index 46df9b9..3be80f7 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-punpckhqdq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-punpckhqdq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-punpckhwd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-punpckhwd-1.c index 2216c01..6f6dae4 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-punpckhwd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-punpckhwd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-punpcklbw-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-punpcklbw-1.c index f439751..ba7488a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-punpcklbw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-punpcklbw-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-punpckldq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-punpckldq-1.c index 4905f1c..1453448 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-punpckldq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-punpckldq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-punpcklqdq-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-punpcklqdq-1.c index 43439bb..b49843d 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-punpcklqdq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-punpcklqdq-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-punpcklwd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-punpcklwd-1.c index 516e80f..0ccc038 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-punpcklwd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-punpcklwd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-pxor-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-pxor-1.c index aca917e..95e6ad8 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-pxor-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-pxor-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-shufpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-shufpd-1.c index 7760bcb..a58eb21 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-shufpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-shufpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-sqrtpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-sqrtpd-1.c index 44dd421..7a2de5e 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-sqrtpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-sqrtpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-subpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-subpd-1.c index 645d644..b0bc7ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-subpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-subpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-subsd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-subsd-1.c index 7962baf..602692d8 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-subsd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-subsd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-1.c index 1eae74c..cefa0d9 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-2.c b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-2.c index ee12269..45fd910 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-3.c b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-3.c index dcbc985..d530df4 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-3.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-3.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-4.c b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-4.c index 3205e0d..ab53117 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-4.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-4.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-5.c b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-5.c index cce5f84..a52ada2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-5.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-5.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-6.c b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-6.c index 2240e8b..0c36f5d 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-6.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-6.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-unpckhpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-unpckhpd-1.c index 61b2282..f3e2204 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-unpckhpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-unpckhpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-unpcklpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-unpcklpd-1.c index 142b60a..dae8d77 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-unpcklpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-unpcklpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse2-xorpd-1.c b/gcc/testsuite/gcc.target/powerpc/sse2-xorpd-1.c index e2fa493..9e15fc5 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse2-xorpd-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse2-xorpd-1.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse3-addsubpd.c b/gcc/testsuite/gcc.target/powerpc/sse3-addsubpd.c index 5685a4a..287a857 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse3-addsubpd.c +++ b/gcc/testsuite/gcc.target/powerpc/sse3-addsubpd.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse3-addsubps.c b/gcc/testsuite/gcc.target/powerpc/sse3-addsubps.c index d01ee61..b341ba8 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse3-addsubps.c +++ b/gcc/testsuite/gcc.target/powerpc/sse3-addsubps.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse3-haddpd.c b/gcc/testsuite/gcc.target/powerpc/sse3-haddpd.c index ec90f63..67c995b 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse3-haddpd.c +++ b/gcc/testsuite/gcc.target/powerpc/sse3-haddpd.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse3-haddps.c b/gcc/testsuite/gcc.target/powerpc/sse3-haddps.c index 149ddd2..f0b5d8b 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse3-haddps.c +++ b/gcc/testsuite/gcc.target/powerpc/sse3-haddps.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse3-hsubpd.c b/gcc/testsuite/gcc.target/powerpc/sse3-hsubpd.c index 498ae81..2550c97 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse3-hsubpd.c +++ b/gcc/testsuite/gcc.target/powerpc/sse3-hsubpd.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse3-hsubps.c b/gcc/testsuite/gcc.target/powerpc/sse3-hsubps.c index 1282f15..a1b8b87 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse3-hsubps.c +++ b/gcc/testsuite/gcc.target/powerpc/sse3-hsubps.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse3-lddqu.c b/gcc/testsuite/gcc.target/powerpc/sse3-lddqu.c index 9de0ca1..8e01862 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse3-lddqu.c +++ b/gcc/testsuite/gcc.target/powerpc/sse3-lddqu.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse3-movddup.c b/gcc/testsuite/gcc.target/powerpc/sse3-movddup.c index 2b2e2c2..7eda0af 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse3-movddup.c +++ b/gcc/testsuite/gcc.target/powerpc/sse3-movddup.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse3-movshdup.c b/gcc/testsuite/gcc.target/powerpc/sse3-movshdup.c index e44ae43..3a911a7 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse3-movshdup.c +++ b/gcc/testsuite/gcc.target/powerpc/sse3-movshdup.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse3-movsldup.c b/gcc/testsuite/gcc.target/powerpc/sse3-movsldup.c index c6bbc20..c6cbffb 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse3-movsldup.c +++ b/gcc/testsuite/gcc.target/powerpc/sse3-movsldup.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendpd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendpd.c index ca17804..b98d42d 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendpd.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendpd.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #ifndef CHECK_H #define CHECK_H "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendps-2.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendps-2.c index 768b6e6..c755702 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendps-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendps-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendps.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendps.c index 2f114b6..e90bc1a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendps.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendps.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #ifndef CHECK_H #define CHECK_H "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvpd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvpd.c index b82cd28..e95ede6 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvpd.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvpd.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c index 8fcb553..871e35a 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-blendvps.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilpd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilpd.c index f532fdb..cf77c50 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilpd.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilpd.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #define NO_WARN_X86_INTRINSICS 1 #include diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilps.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilps.c index 1e29999..7f95cf2 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilps.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilps.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #define NO_WARN_X86_INTRINSICS 1 #include diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilsd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilsd.c index cc0d9c1..0781cb5 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilsd.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilsd.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #define NO_WARN_X86_INTRINSICS 1 #include diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilss.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilss.c index cf1a039..6c4d417 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilss.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-ceilss.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #define NO_WARN_X86_INTRINSICS 1 #include diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-floorpd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-floorpd.c index ad21644..e6702b5 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-floorpd.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-floorpd.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #define NO_WARN_X86_INTRINSICS 1 #include diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-floorps.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-floorps.c index a53ef9a..1d5f94f 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-floorps.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-floorps.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #define NO_WARN_X86_INTRINSICS 1 #include diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-floorsd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-floorsd.c index e4ebc55..8051c0d 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-floorsd.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-floorsd.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #define NO_WARN_X86_INTRINSICS 1 #include diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-floorss.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-floorss.c index cfbfe2b..d9b8928 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-floorss.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-floorss.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #define NO_WARN_X86_INTRINSICS 1 #include diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendvb.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendvb.c index 6aa77fe..091a039 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendvb.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendvb.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendw-2.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendw-2.c index d3f96e8..20a6650 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendw-2.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendw.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendw.c index 1c48c76..386e9dc 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendw.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pblendw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #define NO_WARN_X86_INTRINSICS 1 diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c index 39b9f01..8d1f271 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pcmpeqq.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mpower8-vector" } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrb.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrb.c index 4fa5e83..66d8815 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrb.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrb.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrd.c index 0bec936..221b334 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrd.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrd.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrq.c index 395c20e..63dd008 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrq.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrq.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c index 9ec1ab7..2040b9e 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxbq.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector" } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #ifndef CHECK_H #define CHECK_H "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c index 1c26378..0fd9a17 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxdq.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector" } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #ifndef CHECK_H #define CHECK_H "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c index 6786469..96da563 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmovsxwq.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector" } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #ifndef CHECK_H #define CHECK_H "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c index 6a884f4..59c7b35 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pmuldq.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mpower8-vector" } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-ptest-1.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-ptest-1.c index 69d13d5..e4c85be 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-ptest-1.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-ptest-1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #ifndef CHECK_H #define CHECK_H "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd-2.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd-2.c index cec1617..1a84f02 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd-2.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd-2.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #ifndef CHECK_H #define CHECK_H "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd-3.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd-3.c index 88a5f07..0ae2247 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd-3.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-roundpd-3.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target p8vector_hw } */ -/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O2 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #ifndef CHECK_H #define CHECK_H "sse4_1-check.h" diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c b/gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c index 36b9bd7..ce705fb 100644 --- a/gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c +++ b/gcc/testsuite/gcc.target/powerpc/sse4_2-pcmpgtq.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mpower8-vector" } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-pabsb.c b/gcc/testsuite/gcc.target/powerpc/ssse3-pabsb.c index 180ae34..d0358d3 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-pabsb.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-pabsb.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-pabsd.c b/gcc/testsuite/gcc.target/powerpc/ssse3-pabsd.c index 4a47030..e8f4419 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-pabsd.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-pabsd.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-pabsw.c b/gcc/testsuite/gcc.target/powerpc/ssse3-pabsw.c index e068b0a..509c44c 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-pabsw.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-pabsw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-palignr.c b/gcc/testsuite/gcc.target/powerpc/ssse3-palignr.c index cdd00c4..e76bbef 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-palignr.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-palignr.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-phaddd.c b/gcc/testsuite/gcc.target/powerpc/ssse3-phaddd.c index e8108fa..4040ffa 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-phaddd.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-phaddd.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-phaddsw.c b/gcc/testsuite/gcc.target/powerpc/ssse3-phaddsw.c index efbdd55..1c39ae5 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-phaddsw.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-phaddsw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-phaddw.c b/gcc/testsuite/gcc.target/powerpc/ssse3-phaddw.c index fa4b9a5..c571456 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-phaddw.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-phaddw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-phsubd.c b/gcc/testsuite/gcc.target/powerpc/ssse3-phsubd.c index c8291be..e3aad94 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-phsubd.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-phsubd.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-phsubsw.c b/gcc/testsuite/gcc.target/powerpc/ssse3-phsubsw.c index e03ae60..7a642e2 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-phsubsw.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-phsubsw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-phsubw.c b/gcc/testsuite/gcc.target/powerpc/ssse3-phsubw.c index 87ed6b4..8d23dd0 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-phsubw.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-phsubw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-pmaddubsw.c b/gcc/testsuite/gcc.target/powerpc/ssse3-pmaddubsw.c index 46fbd0e..3bf5810 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-pmaddubsw.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-pmaddubsw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-pmulhrsw.c b/gcc/testsuite/gcc.target/powerpc/ssse3-pmulhrsw.c index ab7e840..6f64320 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-pmulhrsw.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-pmulhrsw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-pshufb.c b/gcc/testsuite/gcc.target/powerpc/ssse3-pshufb.c index 404ca4d..042a1ee 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-pshufb.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-pshufb.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-psignb.c b/gcc/testsuite/gcc.target/powerpc/ssse3-psignb.c index 0ad08f0..75b1ff6 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-psignb.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-psignb.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-psignd.c b/gcc/testsuite/gcc.target/powerpc/ssse3-psignd.c index 5258510..97f959c 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-psignd.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-psignd.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/ssse3-psignw.c b/gcc/testsuite/gcc.target/powerpc/ssse3-psignw.c index b0f0122..bae1ee5 100644 --- a/gcc/testsuite/gcc.target/powerpc/ssse3-psignw.c +++ b/gcc/testsuite/gcc.target/powerpc/ssse3-psignw.c @@ -1,5 +1,6 @@ /* { dg-do run } */ -/* { dg-options "-O3 -mpower8-vector -Wno-psabi" } */ +/* { dg-options "-O3 -mvsx -Wno-psabi" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-require-effective-target p8vector_hw } */ #ifndef CHECK_H diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-1.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-1.c index ff7b67d..53e3bbd 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-1.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target le } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler-not "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-12.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-12.c index c71918c..2c0a9a6 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-12.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-12.c @@ -1,6 +1,6 @@ /* { dg-do compile { target le } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler-not "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-14.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-14.c index 01c4d73..b20ec88 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-14.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-14.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler "stxsdx" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-15.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-15.c index 6b3534a..5607b56 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-15.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-15.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler "xxspltw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-16.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-16.c index e8205e1..a09269a 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-16.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-16.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler "vspltw" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-17.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-17.c index 342ccd6..88ad9ac 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-17.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-17.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { le } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O1" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-18.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-18.c index dadc420..00e52c1 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-18.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-18.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* { dg-final { scan-assembler-not "xxpermdi" } } */ /* This is a test for a specific convert-splat permute removal. */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-19.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-19.c index d09db20..f4698d5 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-19.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-19.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -ftree-vectorize -mdejagnu-cpu=power8 -ffast-math -fvect-cost-model=unlimited" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mdejagnu-cpu=power8 -mvsx -ffast-math -fvect-cost-model=unlimited" } */ /* This tests special handling for various uses of xxpermdi, other than to perform doubleword swaps. */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-2.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-2.c index 9b3c367..c927daf 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-2.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target le } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler-not "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-22.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-22.c index 847aebc..b6fb0bb 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-22.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-22.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { *-*-aix* || { *-*-linux* && lp64 } } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec -mcmodel=large" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx -maltivec -mcmodel=large" } */ /* The expansion for vector character multiply introduces a vperm operation. This tests that changing the vperm mask allows us to remove all swaps diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-23.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-23.c index bcbc889..d2d88e0 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-23.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-23.c @@ -1,6 +1,6 @@ /* { dg-do compile { target le } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -ffast-math" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -ffast-math" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler-not "xxpermdi" { target le } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-24.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-24.c index fdc9e96..1c9badd 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-24.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-24.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 -ffast-math" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 -ffast-math" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler-not "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-25.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-25.c index 51fab6a..44631ea 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-25.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-25.c @@ -1,6 +1,6 @@ /* { dg-do compile { target le } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 " } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler-not "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c index 88f1dc6..cc952fc 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 " } */ /* { dg-final { scan-assembler-times "lxvd2x" 2 } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler-not "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c index 758542a..a41b8cd 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 " } */ /* { dg-final { scan-assembler-times "lxvd2x" 2 } } */ /* { dg-final { scan-assembler-times "stxvd2x" 1 } } */ /* { dg-final { scan-assembler-times "xxpermdi" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-3.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-3.c index a05d4cc..6c3d155 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-3.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target le } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler-not "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-30.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-30.c index 03d63fd..44a67ac 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-30.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-30.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 " } */ /* Previous versions of this test required that the assembler does not contain xxpermdi or xxswapd. However, with the more sophisticated diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-33.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-33.c index 6b53991..aa51db4 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-33.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-33.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 " } */ /* Previous versions of this test required that the assembler does not contain xxpermdi or xxswapd. However, with the more sophisticated diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-36.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-36.c index f05aee0..29ffcba 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-36.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-36.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 " } */ /* Previous versions of this test required that the assembler does not contain xxpermdi or xxswapd. However, with the more sophisticated diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-39.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-39.c index 937828b..8dca8f5 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-39.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-39.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 " } */ /* Previous versions of this test required that the assembler does not contain xxpermdi or xxswapd. However, with the more sophisticated diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-4.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-4.c index 7ec5977..ffb89e1 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-4.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target le } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler-not "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-42.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-42.c index bd29d3f..5c0b29c 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-42.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-42.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 " } */ /* Previous versions of this test required that the assembler does not contain xxpermdi or xxswapd. However, with the more sophisticated diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-45.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-45.c index 716a8b4..0bb4c7a 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-45.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-45.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3 " } */ /* Previous versions of this test required that the assembler does not contain xxpermdi or xxswapd. However, with the more sophisticated diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c index 4738d5e..3b5154b 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-46.c @@ -1,6 +1,6 @@ /* { dg-do run { target le } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 " } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 " } */ typedef __attribute__ ((__aligned__ (8))) unsigned long long __m64; typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-5.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-5.c index 3c73569..5fc9fcc 100644 --- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-5.c +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target le } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* { dg-final { scan-assembler "lxvd2x" } } */ /* { dg-final { scan-assembler "stxvd2x" } } */ /* { dg-final { scan-assembler-not "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/unpack-vectorize-3.c b/gcc/testsuite/gcc.target/powerpc/unpack-vectorize-3.c index 520a279..bb56dab 100644 --- a/gcc/testsuite/gcc.target/powerpc/unpack-vectorize-3.c +++ b/gcc/testsuite/gcc.target/powerpc/unpack-vectorize-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */ /* Test if signed int unpack vectorization succeeds. */ diff --git a/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c b/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c index a488b89..8eb18ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c +++ b/gcc/testsuite/gcc.target/powerpc/upper-regs-sf.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ /* Test make sure single precision values are allocated to the Altivec registers as well as the traditional FPR registers. */ diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c index e02ba44..218c546 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c index 2f02d39..a6534df 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c index 2530e67..8fc2277 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c index 17d7c8d..2b46484 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c index d6e56cc..2373c39 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c b/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c index ff6d436..2af053b 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c b/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c index a460962..64678c9 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c b/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c index c3d1bc8..ef0aab6 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c b/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c index d08395a..ad434a6 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c b/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c index 7f17694..1e9c359 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c b/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c index 8a809d5..de363d4 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c b/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c index a330f52..66a7497 100644 --- a/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* This test should succeed on both 32- and 64-bit configurations. */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c b/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c index f74a117..ef000c1 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmp-sel.c @@ -1,7 +1,8 @@ /* { dg-do compile { target powerpc64*-*-* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ /* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-maltivec -O2 -mvsx -mpower8-vector" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-maltivec -O2 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ /* { dg-final { scan-assembler "vcmpgtsd" } } */ /* { dg-final { scan-assembler-not "xxlnor" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmp.c b/gcc/testsuite/gcc.target/powerpc/vec-cmp.c index eaeb4c6..5376308 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-cmp.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmp.c @@ -1,7 +1,7 @@ /* { dg-do compile { target lp64 } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* { dg-final { scan-assembler-times "vcmpgtsb" 4 } } */ /* { dg-final { scan-assembler-times "vcmpgtub" 4 } } */ /* { dg-final { scan-assembler-times "vcmpgtsh" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmpne-long.c b/gcc/testsuite/gcc.target/powerpc/vec-cmpne-long.c index d6ab201..7086156 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-cmpne-long.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmpne-long.c @@ -1,6 +1,6 @@ /* { dg-do run { target { powerpc64*-*-* && { p8vector_hw } } } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -mpower8-vector -O3" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O3" } */ /* Test that the vec_cmpne builtin works as expected for long long and double vectors. */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c index c694466..1cb5b1b 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-3.c index a470742..4a15d1e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-4.c index 3dc7ae1..fd2bdf1 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-5.c index 9e0d0ef..229ed3d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-5.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-6.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-6.c index 27c0811..9c2cff9 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-6.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-7.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-7.c index 2ad0193..22192f7 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-7.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-8.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-8.c index 527f2cf..ea0bcc8 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-9.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-9.c index c004473..0648f59 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-extract-9.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-9.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-init-10.c b/gcc/testsuite/gcc.target/powerpc/vec-init-10.c index 23587b3..4307e5e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-init-10.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-init-10.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* Check that we can optimize sldi + or to rldimi for vector int init. */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-init-3.c b/gcc/testsuite/gcc.target/powerpc/vec-init-3.c index 3265e2a..f64a8b0 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-init-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-init-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ vector long merge (long a, long b) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-init-6.c b/gcc/testsuite/gcc.target/powerpc/vec-init-6.c index 3b17300..6e78095 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-init-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-init-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ vector int merge (int a, int b, int c, int d) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-init-7.c b/gcc/testsuite/gcc.target/powerpc/vec-init-7.c index f75177c..965960a 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-init-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-init-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ vector int splat (int a) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-minmax-1.c b/gcc/testsuite/gcc.target/powerpc/vec-minmax-1.c index 3f6e376..6c8347f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-minmax-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-minmax-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ /* { dg-final { scan-assembler-times {\mxvmaxdp\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvmaxsp\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvmindp\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/vec-minmax-2.c index b27bebb..79739a3 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-minmax-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-minmax-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9 -ffast-math" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx -ffast-math" } */ /* { dg-final { scan-assembler-times {\mxsmaxcdp\M} 2 } } */ /* { dg-final { scan-assembler-times {\mxsmincdp\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-set-char.c b/gcc/testsuite/gcc.target/powerpc/vec-set-char.c index eb7296d..460324a 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-set-char.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-set-char.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-set-int.c b/gcc/testsuite/gcc.target/powerpc/vec-set-int.c index 6dc7d73..6ea954f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-set-int.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-set-int.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-set-short.c b/gcc/testsuite/gcc.target/powerpc/vec-set-short.c index a03ada7..78188c6 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-set-short.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-set-short.c @@ -1,6 +1,6 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-sld-modulo.c b/gcc/testsuite/gcc.target/powerpc/vec-sld-modulo.c index d8dd14e..8379fde 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-sld-modulo.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-sld-modulo.c @@ -2,7 +2,8 @@ for a doubleword vector works correctly after gimple folding. */ /* { dg-do run { target { p8vector_hw } } } */ -/* { dg-options "-O2 -mpower8-vector" } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-srad-modulo.c b/gcc/testsuite/gcc.target/powerpc/vec-srad-modulo.c index f1330fd..ae04705 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-srad-modulo.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-srad-modulo.c @@ -2,7 +2,8 @@ for a doubleword vector works correctly after gimple folding. */ /* { dg-do run { target { p8vector_hw } } } */ -/* { dg-options "-O2 -mpower8-vector" } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec-srd-modulo.c b/gcc/testsuite/gcc.target/powerpc/vec-srd-modulo.c index 70b6e85..9d6624f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-srd-modulo.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-srd-modulo.c @@ -2,7 +2,8 @@ for a doubleword vector works correctly after gimple folding. */ /* { dg-do run { target { p8vector_hw } } } */ -/* { dg-options "-O2 -mpower8-vector" } */ +/* { dg-options "-O2 -mvsx" } */ +/* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vec_reve_2.c b/gcc/testsuite/gcc.target/powerpc/vec_reve_2.c index 9661939..ab7c2d9 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec_reve_2.c +++ b/gcc/testsuite/gcc.target/powerpc/vec_reve_2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vector_float.c b/gcc/testsuite/gcc.target/powerpc/vector_float.c index 4ac2d9f..50c3cae 100644 --- a/gcc/testsuite/gcc.target/powerpc/vector_float.c +++ b/gcc/testsuite/gcc.target/powerpc/vector_float.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target lp64 } */ -/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ +/* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */ vector float test (float *a, float *b, float *c, float *d) diff --git a/gcc/testsuite/gcc.target/powerpc/versioned-copy-loop.c b/gcc/testsuite/gcc.target/powerpc/versioned-copy-loop.c index bbfd165..b8baaa3 100644 --- a/gcc/testsuite/gcc.target/powerpc/versioned-copy-loop.c +++ b/gcc/testsuite/gcc.target/powerpc/versioned-copy-loop.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O3 -fdump-tree-vect-details" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mvsx -fdump-tree-vect-details" } */ /* Verify that a pure copy loop with a vectorization factor of two that requires alignment will not be vectorized. See the cost diff --git a/gcc/testsuite/gcc.target/powerpc/vslv-0.c b/gcc/testsuite/gcc.target/powerpc/vslv-0.c index f921b2c..cc8df73 100644 --- a/gcc/testsuite/gcc.target/powerpc/vslv-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vslv-0.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vslv-1.c b/gcc/testsuite/gcc.target/powerpc/vslv-1.c index 37407c1..2714e4e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vslv-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vslv-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsrv-0.c b/gcc/testsuite/gcc.target/powerpc/vsrv-0.c index 8ecd326..410e6de 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsrv-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsrv-0.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsrv-1.c b/gcc/testsuite/gcc.target/powerpc/vsrv-1.c index 186e79a..9ba985a 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsrv-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsrv-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-0.c index d73ec0e..6c42d94 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-1.c index ad90ee2..50208b8 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-10.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-10.c index e2e84a2..f2f8f5b 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-10.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-10.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-11.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-11.c index a05b504..e708dd1 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-11.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-11.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-12.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-12.c index b4c669d..b9084f5 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-12.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-12.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-13.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-13.c index 5501377..0812652 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-13.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-13.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-14.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-14.c index a048185..f2d00ab 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-14.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-14.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-2.c index abc19c2..3378f9f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-3.c index 5048ac1..38aa56a 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-4.c index 13fdb57..5a60dff 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-5.c index c0474d3..9efbbb1 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-6.c index f25ba4e..4eb1dbc 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-7.c index 9c77e08..1b4f0ad 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-8.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-8.c index 3069b70..050f07c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-8.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-9.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-9.c index d21412a..c0b6845 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-9.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-ne-9.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-1.c index a1c7cb5..dcbc661 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-2.c index 4458327..3666b45 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-3.c index c3d9005..09b0078 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-4.c index 0591904..7226c0c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-5.c index d47aceb..153e728 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-6.c index 6109730..29440ea 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c index a41e82e..45d7493 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-all-nez-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-0.c index 909c8a5..1c6a727 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-1.c index a721ce8..35da926 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c index 3d83d45..30dfc83 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-11.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-11.c index d993912..d9d7d3f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-11.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-11.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-12.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-12.c index be0c127..8bd5b24 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-12.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-12.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-13.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-13.c index 35a24c9..90a59c4 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-13.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-13.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c index 7b0b4f4..4375bfe 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-2.c index 910ad8b..c359975 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-3.c index 7b0b23d..677db19 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-4.c index a2dac32..2f2f08c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-5.c index 7b98aab..8d15550 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-6.c index ad7d121..5fea9ac 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c index 707f7eb..254a116 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c index 45078c5..d94ef89 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c index 525b1a4..efe83cf 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-1.c index 36b13ef..4fdc538 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-2.c index cd8b762..9aee034 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-3.c index 6883477..2af3cdf 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-4.c index 947fe4d..ea48d18 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-5.c index 269ffd8..747fcaf 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-6.c index 35a5da5..8d5c155 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c index 3bf8a32..6e94fee 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eqz-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c index a780b9b..bfea50c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c index 454b42f..1860fe8 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c index 52436e1..1bce646 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c index 0436434..c1448ac 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c index c8f2cd5..9cf0cd7 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c index 5aa0740..cd509a9 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c index db8c9ff..28d2bf4 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O1" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O1" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-8.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-8.c index 99caf06..ac8b6e6 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-8.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-9.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-9.c index ef1796f..5a11b8f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-9.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpne-9.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-1.c index f538d18..f279184 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-2.c index 6fc9b71..36e8008 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-3.c index 97a2ce4..2e29024 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-4.c index 04a289f..a5ca7c7 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-5.c index 272bda9..0dbe16f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-6.c index ee56d7d..9fcefa0 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c index 52110af..95bacc3 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cmpnez-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c index f430152..c963fc8 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* { dg-additional-options "-mbig" { target powerpc64le-*-* } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c index b0e4bee..d15c33d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* { dg-additional-options "-mbig" { target powerpc64le-*-* } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c index 892a078..2251453 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c index c817118..2d803da 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -mlittle" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c index c45048e..d12eb57 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -mlittle" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c index 9f30719..3a93cf2 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* { dg-additional-options "-mbig" { target powerpc64le-*-* } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c index 703f8fe..1ef7845 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ /* { dg-additional-options "-mbig" { target powerpc64le-*-* } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c index f0c380d..5f68e3c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c index 844fb5d..be8f91b 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -mlittle" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c index 7b05f77..2927f25 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-linux* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -mlittle" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-0.c index 43bfc55..34bfe59 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-0.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-1.c index c7ccf28..48463ab 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-10.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-10.c index 742488f..aa7855a 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-10.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-10.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-11.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-11.c index 5f3f305..f3e0156 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-11.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-11.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-12.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-12.c index 92b0d0dd..729b386 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-12.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-12.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ /* The vec_xl_len() function is not available on power8 configurations. */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c index 0f601fb..62df33e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-2.c index fea1679..cd0d3d0 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-3.c index 64596dd..b51a386 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-4.c index d7e04de..053414c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-5.c index 68979cd..2f13ee2 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-5.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-6.c index 5c7235e..e4fcbd4 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-6.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-7.c index e3264ed..eea0326 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-7.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-8.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-8.c index 4e396cb..59fb4d8 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-9.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-9.c index ffac864..b0a35f3 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-9.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-9.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-0.c index c85b6c3..22a636e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-1.c index 9715863..7fb2e26 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-2.c index 32754d1..ba78936 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-3.c index 7c684e3..f9f03d2 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-4.c index da14d8a..3ea2182 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-5.c index 3e5096b..e322d3c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-6.c index 65d43a1..71ddafe 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-7.c index c6f7b5c..acd46c7 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xlx-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-0.c index 8392713..0d6c772 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-1.c index 150a525..6b3f6d6 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-2.c index 5e22110..32392ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-2.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-3.c index 5bddede..b56a3af 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-3.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-4.c index 8d34e19..cd42d10 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-4.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-5.c index 617afee..4d694ce 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-5.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-6.c index b2e8edd..f9566a4 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-6.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-7.c index fd6b5be..04dead1 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xrx-7.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-0.c index e798631..4133bcb 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-0.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-1.c index 842b5f8..a91d3a0 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-10.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-10.c index c043711..b267a1e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-10.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-10.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-11.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-11.c index 158196b..1d49754 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-11.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-11.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c index f30d49c..e563515 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-12.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c index 2a6a7da..f471419 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target ilp32 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-2.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-2.c index 1d1b4a9..38804cd 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-3.c index e2395ac..4986c47 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c index e43896b..739732f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-5.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-5.c index 93cafd3..4a8752e 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-5.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-6.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-6.c index e5bd928..10f8df3 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-6.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-6.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-7.c index 6753264..d42e9a6 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-7.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-8.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-8.c index afeeb6c..20ee3a1 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-8.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-8.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-9.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-9.c index 0661196..cc43528 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-9.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-9.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target lp64 } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx" } */ #include #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-msum.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-msum.c index 058ca0b..51eefd6 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-msum.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-msum.c @@ -2,9 +2,9 @@ inputs generate the proper code. */ /* { dg-do compile } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-require-effective-target int128 } */ -/* { dg-options "-mdejagnu-cpu=power9 -O3" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O3" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c index 525007d..b313364 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-extract-3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O3 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O3 -mdejagnu-cpu=power8 -mvsx" } */ /* { dg-final { scan-assembler "mfvsrd" } } */ /* { dg-final { scan-assembler-not "stfd" } } */ /* { dg-final { scan-assembler-not "stxvd2x" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-extract-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-extract-4.c index dd990d9..991e7aa 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-extract-4.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-extract-4.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* { dg-final { scan-assembler-times "vspltw" 6 } } */ /* { dg-final { scan-assembler-times "xvcvsxwdp" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-extract-5.c b/gcc/testsuite/gcc.target/powerpc/vsx-extract-5.c index 60a666f..34bebc4 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-extract-5.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-extract-5.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8 -mvsx" } */ /* { dg-final { scan-assembler-times "vspltw" 6 } } */ /* { dg-final { scan-assembler-times "xvcvsxwdp" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode.c index a00ce18..b5d8c17 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ double load_asm_d_constraint (short *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c index eca2ccc..299f61c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ unsigned int foo (unsigned short u) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c index 39b0bfb..0e77c0c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-himode3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ double load_asm_v_constraint (short *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c index 8d11b67..62885ad 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ double load_asm_d_constraint (signed char *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c index 1033901..b42a32f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ unsigned int foo (unsigned char u) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c index fd39645..4dce4f0 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-qimode3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2" } */ double load_asm_v_constraint (signed char *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode.c index b3063c7..1344e0d 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ double load_asm_d_constraint (int *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c index 65c007a..7e941cc 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode2.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ unsigned int foo (unsigned int u) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c b/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c index 48201b4..b10d6e5 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-simode3.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p8vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */ double load_asm_v_constraint (int *p) { diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c index 6032be4..f6746c6 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-7.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-mvsx -mno-power8-vector -O2" } */ +/* { dg-options "-mvsx -mdejagnu-cpu=power7 -O2" } */ #include diff --git a/gcc/testsuite/gfortran.dg/vect/pr45714-b.f b/gcc/testsuite/gfortran.dg/vect/pr45714-b.f index abf33cd..bf2a2eb 100644 --- a/gcc/testsuite/gfortran.dg/vect/pr45714-b.f +++ b/gcc/testsuite/gfortran.dg/vect/pr45714-b.f @@ -1,5 +1,5 @@ ! { dg-do compile { target powerpc*-*-* } } -! { dg-additional-options "-O3 -mcpu=power7 -mno-power9-vector -mno-power8-vector -ffast-math -mveclibabi=mass" } +! { dg-additional-options "-O3 -mdejagnu-cpu=power7 -mvsx -ffast-math -mveclibabi=mass" } integer index(18),i,j,k,l,ipiv(18),info,ichange,neq,lda,ldb, & nrhs,iplas diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 6f4e25f..ded6ab9 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2642,7 +2642,7 @@ proc check_p8vector_hw_available { } { || [istarget *-*-darwin*]} { expr 0 } else { - set options "-mpower8-vector" + set options "-mcpu=power8" check_runtime_nocache p8vector_hw_available { int main() { @@ -2670,7 +2670,7 @@ proc check_p9vector_hw_available { } { || [istarget *-*-darwin*]} { expr 0 } else { - set options "-mpower9-vector" + set options "-mcpu=power9" check_runtime_nocache p9vector_hw_available { int main() { @@ -2814,7 +2814,7 @@ proc check_ppc_float128_hw_available { } { || [istarget *-*-darwin*]} { expr 0 } else { - set options "-mfloat128 -mvsx -mfloat128-hardware -mpower9-vector" + set options "-mfloat128 -mvsx -mfloat128-hardware -mcpu=power9" check_runtime_nocache ppc_float128_hw_available { volatile __float128 x = 1.0q; volatile __float128 y = 2.0q; @@ -6969,62 +6969,6 @@ proc check_effective_target_powerpc_altivec_ok { } { } "-maltivec"] } -# Return 1 if this is a PowerPC target supporting -mpower8-vector - -proc check_effective_target_powerpc_p8vector_ok { } { - if { ([istarget powerpc*-*-*] - && ![istarget powerpc-*-linux*paired*]) - || [istarget rs6000-*-*] } { - # AltiVec is not supported on AIX before 5.3. - if { [istarget powerpc*-*-aix4*] - || [istarget powerpc*-*-aix5.1*] - || [istarget powerpc*-*-aix5.2*] } { - return 0 - } - # Darwin doesn't run on power8, so far. - if { [istarget *-*-darwin*] } { - return 0 - } - return [check_no_compiler_messages powerpc_p8vector_ok object { - int main (void) { - asm volatile ("xxlorc 0,0,0"); - return 0; - } - } "-mpower8-vector"] - } else { - return 0 - } -} - -# Return 1 if this is a PowerPC target supporting -mpower9-vector - -proc check_effective_target_powerpc_p9vector_ok { } { - if { ([istarget powerpc*-*-*] - && ![istarget powerpc-*-linux*paired*]) - || [istarget rs6000-*-*] } { - # AltiVec is not supported on AIX before 5.3. - if { [istarget powerpc*-*-aix4*] - || [istarget powerpc*-*-aix5.1*] - || [istarget powerpc*-*-aix5.2*] } { - return 0 - } - # Darwin doesn't run on power9, so far. - if { [istarget *-*-darwin*] } { - return 0 - } - return [check_no_compiler_messages powerpc_p9vector_ok object { - int main (void) { - long e = -1; - vector double v = (vector double) { 0.0, 0.0 }; - asm ("xsxexpdp %0,%1" : "+r" (e) : "wa" (v)); - return e; - } - } "-mpower9-vector"] - } else { - return 0 - } -} - # Return 1 if this is a PowerPC target supporting -mmodulo proc check_effective_target_powerpc_p9modulo_ok { } { @@ -11686,9 +11630,13 @@ proc check_vect_support_and_set_flags { } { lappend DEFAULT_VECTCFLAGS "-maltivec" if [check_p9vector_hw_available] { - lappend DEFAULT_VECTCFLAGS "-mpower9-vector" + # For power10 and up, don't specify -mcpu=power9, so that we + # can have more testing coverage with higher cpu types. + if ![check_power10_hw_available] { + lappend DEFAULT_VECTCFLAGS "-mcpu=power9" + } } elseif [check_p8vector_hw_available] { - lappend DEFAULT_VECTCFLAGS "-mpower8-vector" + lappend DEFAULT_VECTCFLAGS "-mcpu=power8" } elseif [check_vsx_hw_available] { lappend DEFAULT_VECTCFLAGS "-mvsx" "-mno-allow-movmisalign" } @@ -11698,7 +11646,9 @@ proc check_vect_support_and_set_flags { } { } else { if [is-effective-target ilp32] { # Specify a cpu that supports VMX for compile-only tests. - lappend DEFAULT_VECTCFLAGS "-mcpu=970" + # Place -mcpu=970 first to avoid possible overriding on + # some other cpu type specified above. + set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0 "-mcpu=970"] } set dg-do-what-default compile } -- cgit v1.1 From 00bc8c0998d83fd08c567607f2e052108bfa39c7 Mon Sep 17 00:00:00 2001 From: YunQiang Su Date: Thu, 22 Feb 2024 13:05:06 +0800 Subject: invoke.texi: Fix some skipping UrlSuffix problem for MIPS The problem is that, there are these lines in mips.opt.urls: ; skipping UrlSuffix for 'mabi=' due to finding no URLs ; skipping UrlSuffix for 'mno-flush-func' due to finding no URLs ; skipping UrlSuffix for 'mexplicit-relocs' due to finding no URLs These lines is not fixed by this patch due to that we don't document these options: ; skipping UrlSuffix for 'mlra' due to finding no URLs ; skipping UrlSuffix for 'mdebug' due to finding no URLs ; skipping UrlSuffix for 'meb' due to finding no URLs ; skipping UrlSuffix for 'mel' due to finding no URLs gcc * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix problem of mabi=, mno-flush-func, mexplicit-relocs; add missing leading - of mbranch-cost option. * config/mips/mips.opt.urls: Regenerate. --- gcc/config/mips/mips.opt.urls | 12 ++++++++++-- gcc/doc/invoke.texi | 14 +++++--------- 2 files changed, 15 insertions(+), 11 deletions(-) (limited to 'gcc') diff --git a/gcc/config/mips/mips.opt.urls b/gcc/config/mips/mips.opt.urls index ff2f0ae..96aba04 100644 --- a/gcc/config/mips/mips.opt.urls +++ b/gcc/config/mips/mips.opt.urls @@ -6,7 +6,8 @@ UrlSuffix(gcc/MIPS-Options.html#index-EB-2) EL UrlSuffix(gcc/MIPS-Options.html#index-EL-2) -; skipping UrlSuffix for 'mabi=' due to finding no URLs +mabi= +UrlSuffix(gcc/MIPS-Options.html#index-mabi-3) mabicalls UrlSuffix(gcc/MIPS-Options.html#index-mabicalls) @@ -65,9 +66,15 @@ UrlSuffix(gcc/MIPS-Options.html#index-membedded-data) meva UrlSuffix(gcc/MIPS-Options.html#index-meva) +mexplicit-relocs= +UrlSuffix(gcc/MIPS-Options.html#index-mexplicit-relocs-2) + mexplicit-relocs UrlSuffix(gcc/MIPS-Options.html#index-mexplicit-relocs-2) +mno-explicit-relocs +UrlSuffix(gcc/MIPS-Options.html#index-mno-explicit-relocs-2) + mextern-sdata UrlSuffix(gcc/MIPS-Options.html#index-mextern-sdata) @@ -173,7 +180,8 @@ UrlSuffix(gcc/MIPS-Options.html#index-mno-float) mmcu UrlSuffix(gcc/MIPS-Options.html#index-mmcu-1) -; skipping UrlSuffix for 'mno-flush-func' due to finding no URLs +mno-flush-func +UrlSuffix(gcc/MIPS-Options.html#index-mno-flush-func-1) mno-mdmx UrlSuffix(gcc/MIPS-Options.html#index-mno-mdmx) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8219a6a..58527e1 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -27995,11 +27995,7 @@ Aliases of @option{-minterlink-compressed} and @option{-mno-interlink-compressed}. These options predate the microMIPS ASE and are retained for backwards compatibility. -@opindex mabi=32 -@opindex mabi=o64 -@opindex mabi=n32 -@opindex mabi=64 -@opindex mabi=eabi +@opindex mabi @item -mabi=32 @itemx -mabi=o64 @itemx -mabi=n32 @@ -28486,9 +28482,8 @@ Enable (disable) use of the @code{%hi()} and @code{%lo()} assembler relocation operators. This option has been superseded by @option{-mexplicit-relocs} but is retained for backwards compatibility. -@opindex mexplicit-relocs=none -@opindex mexplicit-relocs=base -@opindex mexplicit-relocs=pcrel +@opindex mexplicit-relocs +@opindex mno-explicit-relocs @item -mexplicit-relocs=none @itemx -mexplicit-relocs=base @itemx -mexplicit-relocs=pcrel @@ -28767,6 +28762,7 @@ Disable the insertion of cache barriers. This is the default setting. @end table @opindex mflush-func +@opindex mno-flush-func @item -mflush-func=@var{func} @itemx -mno-flush-func Specifies the function to call to flush the I and D caches, or to not @@ -28778,7 +28774,7 @@ depends on the target GCC was configured for, but commonly is either @code{_flush_func} or @code{__cpu_flush}. @opindex mbranch-cost -@item mbranch-cost=@var{num} +@item -mbranch-cost=@var{num} Set the cost of branches to roughly @var{num} ``simple'' instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases. A zero cost redundantly selects -- cgit v1.1 From 853cbcb7a74ecd95efcba25279b270f0a868d584 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 22 Feb 2024 10:14:00 +0100 Subject: bitintlower: Fix .MUL_OVERFLOW overflow checking [PR114038] Currently, bitint_large_huge::lower_mul_overflow uses cnt 1 only if startlimb == endlimb and in that case doesn't use a loop and handles everything in a special if: unsigned cnt; bool use_loop = false; if (startlimb == endlimb) cnt = 1; else if (startlimb + 1 == endlimb) cnt = 2; else if ((end % limb_prec) == 0) { cnt = 2; use_loop = true; } else { cnt = 3; use_loop = startlimb + 2 < endlimb; } if (cnt == 1) { ... } else The loop handling for the loop exit condition wants to compare if the incremented index is equal to endlimb, but that is correct only if end is not divisible by limb_prec and there will be a straight line check after the loop as well for the most significant limb. The code used endlimb + (cnt == 1) for that, but cnt == 1 is never true here, because cnt is either 2 or 3, so the right check is (cnt == 2). 2024-02-22 Jakub Jelinek PR tree-optimization/114038 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix loop exit condition if end is divisible by limb_prec. * gcc.dg/torture/bitint-59.c: New test. --- gcc/gimple-lower-bitint.cc | 2 +- gcc/testsuite/gcc.dg/torture/bitint-59.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/torture/bitint-59.c (limited to 'gcc') diff --git a/gcc/gimple-lower-bitint.cc b/gcc/gimple-lower-bitint.cc index 13b9b20..fb03063 100644 --- a/gcc/gimple-lower-bitint.cc +++ b/gcc/gimple-lower-bitint.cc @@ -4497,7 +4497,7 @@ bitint_large_huge::lower_mul_overflow (tree obj, gimple *stmt) size_one_node); insert_before (g); g = gimple_build_cond (NE_EXPR, idx_next, - size_int (endlimb + (cnt == 1)), + size_int (endlimb + (cnt == 2)), NULL_TREE, NULL_TREE); insert_before (g); edge true_edge, false_edge; diff --git a/gcc/testsuite/gcc.dg/torture/bitint-59.c b/gcc/testsuite/gcc.dg/torture/bitint-59.c new file mode 100644 index 0000000..ef17424 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/bitint-59.c @@ -0,0 +1,22 @@ +/* PR tree-optimization/114038 */ +/* { dg-do run { target bitint } } */ +/* { dg-options "-std=c23 -pedantic-errors" } */ +/* { dg-skip-if "" { ! run_expensive_tests } { "*" } { "-O0" "-O2" } } */ +/* { dg-skip-if "" { ! run_expensive_tests } { "-flto" } { "" } } */ + +#if __BITINT_MAXWIDTH__ >= 129 +int +foo (unsigned _BitInt(63) x, unsigned _BitInt(129) y) +{ + return __builtin_mul_overflow_p (y, x, 0); +} +#endif + +int +main () +{ +#if __BITINT_MAXWIDTH__ >= 129 + if (!foo (90, 0x80000000000000000000000000000000uwb)) + __builtin_abort (); +#endif +} -- cgit v1.1 From 7ed800c9c94b57077ba5911974a63bc06a5e1c35 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 22 Feb 2024 10:19:15 +0100 Subject: call-cdce: Add missing BUILT_IN_*F{32,64}X handling and improve BUILT_IN_*L [PR113993] The following testcase ICEs, because can_test_argument_range returns true for BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X} among many other builtins, but get_no_error_domain doesn't handle those. float32x_type_node when supported in GCC always has DFmode, so that case is easy (and call-cdce assumes that SFmode is IEEE float and DFmode is IEEE double). So *F32X is simply handled by adding those cases next to *F64. float64x_type_node when supported in GCC by definition has a mode with larger precision and exponent range than DFmode, so it can be XFmode, TFmode or KFmode. I went through all the l/f128 suffixed builtins and verified that the float128x_type_node no error domain range is actually identical to the Intel extended long double no error domain range; it isn't that surprising, both IEEE quad and Intel/Motorola extended have the same exponent range [-16381, 16384] (well, Motorola -16382 probably because of different behavior for denormals, but that has nothing to do with get_no_error_domain which is about large inputs overflowing into +-Inf or triggering NaN, denormals could in theory do something solely for sqrt and even that is fine). In theory some target could have different larger type, so for *F64X the code verifies that REAL_MODE_FORMAT (TYPE_MODE (float64x_type_node))->emax == 16384 and if so, uses the *F128 domains, otherwise falls back to the non-suffixed ones (aka *F64), that is certainly the conservative minimum. While at it, the patch also changes the *L suffixed cases to do pretty much the same, the comment said that the function just assumes for *L the *F64 ranges, but that is unnecessarily conservative. All we currently have for long double is: 1) IEEE quad (emax 16384, *F128 ranges) 2) XFmode Intel/Motorola extended (emax 16384, same as *F128 ranges) 3) IBM extended (double double, emax 1024, the extra precision doesn't really help and the domains are the same as for *F64) 4) same as double (*F64 again) So, the patch uses also for *L REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384 checks and either tail recurses into the *F128 case for that or to non-suffixed (aka *F64) case otherwise. BUILT_IN_*F128X not handled because no target has those and it doesn't seem something is on the horizon and who knows what would be used for that. Thus, all we get this wrong for are probably VAX floats or something similar, no intent from me to look at that, that is preexisting issue. BTW, I'm surprised we don't have BUILT_IN_EXP10F{16,32,64,128,32X,64X,128X} builtins, seems glibc has those (sure, I think except *16 and *128x). 2024-02-22 Jakub Jelinek PR tree-optimization/113993 * tree-call-cdce.cc (get_no_error_domain): Handle BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384 the as the F128 suffixed cases, otherwise as non-suffixed ones. Handle BUILT_IN_{EXP,POW}10L for REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384 as (-inf, 4932). * gcc.dg/tree-ssa/pr113993.c: New test. --- gcc/testsuite/gcc.dg/tree-ssa/pr113993.c | 299 +++++++++++++++++++++++++++++++ gcc/tree-call-cdce.cc | 63 +++++-- 2 files changed, 347 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr113993.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr113993.c b/gcc/testsuite/gcc.dg/tree-ssa/pr113993.c new file mode 100644 index 0000000..e92b455 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr113993.c @@ -0,0 +1,299 @@ +/* PR tree-optimization/113993 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-add-options float32 } */ +/* { dg-add-options float64 } */ +/* { dg-add-options float128 } */ +/* { dg-add-options float32x } */ +/* { dg-add-options float64x } */ +/* { dg-final { scan-tree-dump-not "__builtin_\[a-z0-9\] \\\(\[^\n\r\]\\\);" "optimized" } } */ + +void +flt (float f1, float f2, float f3, float f4, float f5, + float f6, float f7, float f8, float f9, float f10) +{ + if (!(f1 >= -1.0f && f1 <= 1.0f)) __builtin_unreachable (); + __builtin_acosf (f1); + __builtin_asinf (f1); + if (!(f2 >= 1.0f && f2 <= __builtin_inff ())) __builtin_unreachable (); + __builtin_acoshf (f2); + if (!(f3 > -1.0f && f3 < 1.0f)) __builtin_unreachable (); + __builtin_atanhf (f3); + if (!(f4 > 0.0f && f4 < __builtin_inff ())) __builtin_unreachable (); + __builtin_logf (f4); + __builtin_log2f (f4); + __builtin_log10f (f4); + if (!(f5 > -1.0f && f5 < __builtin_inff ())) __builtin_unreachable (); + __builtin_log1pf (f5); + if (!(f6 >= 0.0f && f6 < __builtin_inff ())) __builtin_unreachable (); + __builtin_sqrtf (f6); +#if __FLT_MANT_DIG__ == __FLT32_MANT_DIG__ && __FLT_MAX_EXP__ == __FLT32_MAX_EXP__ + if (!(f7 > -89.0f && f7 < 89.0f)) __builtin_unreachable (); + __builtin_coshf (f7); + __builtin_sinhf (f7); + if (!(f8 > -__builtin_inff () && f8 < 88.0f)) __builtin_unreachable (); + __builtin_expf (f8); + if (!(f9 > -__builtin_inff () && f9 < 128.0f)) __builtin_unreachable (); + __builtin_exp2f (f9); + if (!(f10 > -__builtin_inff () && f10 < 38.0f)) __builtin_unreachable (); + __builtin_exp10f (f10); +#endif +} + +#if defined(__FLT16_MANT_DIG__) && 0 /* No library routines here, these don't actually fold away. */ +void +flt16 (_Float16 f1, _Float16 f2, _Float16 f3, _Float16 f4, _Float16 f5, + _Float16 f6, _Float16 f7, _Float16 f8, _Float16 f9) +{ + if (!(f1 >= -1.0f16 && f1 <= 1.0f16)) __builtin_unreachable (); + __builtin_acosf16 (f1); + __builtin_asinf16 (f1); + if (!(f2 >= 1.0f16 && f2 <= __builtin_inff16 ())) __builtin_unreachable (); + __builtin_acoshf16 (f2); + if (!(f3 > -1.0f16 && f3 < 1.0f16)) __builtin_unreachable (); + __builtin_atanhf16 (f3); + if (!(f4 > 0.0f16 && f4 < __builtin_inff16 ())) __builtin_unreachable (); + __builtin_logf16 (f4); + __builtin_log2f16 (f4); + __builtin_log10f16 (f4); + if (!(f5 > -1.0f16 && f5 < __builtin_inff16 ())) __builtin_unreachable (); + __builtin_log1pf16 (f5); + if (!(f6 >= 0.0f16 && f6 < __builtin_inff16 ())) __builtin_unreachable (); + __builtin_sqrtf16 (f6); + if (!(f7 > -11.0f16 && f7 < 11.0f16)) __builtin_unreachable (); + __builtin_coshf16 (f7); + __builtin_sinhf16 (f7); + if (!(f8 > -__builtin_inff16 () && f8 < 11.0f16)) __builtin_unreachable (); + __builtin_expf16 (f8); + if (!(f9 > -__builtin_inff16 () && f9 < 16.0f16)) __builtin_unreachable (); + __builtin_exp2f16 (f9); +} +#endif + +#ifdef __FLT32_MANT_DIG__ +void +flt32 (_Float32 f1, _Float32 f2, _Float32 f3, _Float32 f4, _Float32 f5, + _Float32 f6, _Float32 f7, _Float32 f8, _Float32 f9) +{ + if (!(f1 >= -1.0f32 && f1 <= 1.0f32)) __builtin_unreachable (); + __builtin_acosf32 (f1); + __builtin_asinf32 (f1); + if (!(f2 >= 1.0f32 && f2 <= __builtin_inff32 ())) __builtin_unreachable (); + __builtin_acoshf32 (f2); + if (!(f3 > -1.0f32 && f3 < 1.0f32)) __builtin_unreachable (); + __builtin_atanhf32 (f3); + if (!(f4 > 0.0f32 && f4 < __builtin_inff32 ())) __builtin_unreachable (); + __builtin_logf32 (f4); + __builtin_log2f32 (f4); + __builtin_log10f32 (f4); + if (!(f5 > -1.0f32 && f5 < __builtin_inff32 ())) __builtin_unreachable (); + __builtin_log1pf32 (f5); + if (!(f6 >= 0.0f32 && f6 < __builtin_inff32 ())) __builtin_unreachable (); + __builtin_sqrtf32 (f6); + if (!(f7 > -89.0f32 && f7 < 89.0f32)) __builtin_unreachable (); + __builtin_coshf32 (f7); + __builtin_sinhf32 (f7); + if (!(f8 > -__builtin_inff32 () && f8 < 88.0f32)) __builtin_unreachable (); + __builtin_expf32 (f8); + if (!(f9 > -__builtin_inff32 () && f9 < 128.0f32)) __builtin_unreachable (); + __builtin_exp2f32 (f9); +} +#endif + +void +dbl (double f1, double f2, double f3, double f4, double f5, + double f6, double f7, double f8, double f9, double f10) +{ + if (!(f1 >= -1.0 && f1 <= 1.0)) __builtin_unreachable (); + __builtin_acos (f1); + __builtin_asin (f1); + if (!(f2 >= 1.0 && f2 <= __builtin_inf ())) __builtin_unreachable (); + __builtin_acosh (f2); + if (!(f3 > -1.0 && f3 < 1.0)) __builtin_unreachable (); + __builtin_atanh (f3); + if (!(f4 > 0.0 && f4 < __builtin_inf ())) __builtin_unreachable (); + __builtin_log (f4); + __builtin_log2 (f4); + __builtin_log10 (f4); + if (!(f5 > -1.0 && f5 < __builtin_inf ())) __builtin_unreachable (); + __builtin_log1p (f5); + if (!(f6 >= 0.0 && f6 < __builtin_inf ())) __builtin_unreachable (); + __builtin_sqrt (f6); +#if __DBL_MANT_DIG__ == __FLT64_MANT_DIG__ && __DBL_MAX_EXP__ == __FLT64_MAX_EXP__ + if (!(f7 > -710.0 && f7 < 710.0)) __builtin_unreachable (); + __builtin_cosh (f7); + __builtin_sinh (f7); + if (!(f8 > -__builtin_inf () && f8 < 709.0)) __builtin_unreachable (); + __builtin_exp (f8); + if (!(f9 > -__builtin_inf () && f9 < 1024.0)) __builtin_unreachable (); + __builtin_exp2 (f9); + if (!(f10 > -__builtin_inf () && f10 < 308.0)) __builtin_unreachable (); + __builtin_exp10 (f10); +#endif +} + +#ifdef __FLT64_MANT_DIG__ +void +flt64 (_Float64 f1, _Float64 f2, _Float64 f3, _Float64 f4, _Float64 f5, + _Float64 f6, _Float64 f7, _Float64 f8, _Float64 f9) +{ + if (!(f1 >= -1.0f64 && f1 <= 1.0f64)) __builtin_unreachable (); + __builtin_acosf64 (f1); + __builtin_asinf64 (f1); + if (!(f2 >= 1.0f64 && f2 <= __builtin_inff64 ())) __builtin_unreachable (); + __builtin_acoshf64 (f2); + if (!(f3 > -1.0f64 && f3 < 1.0f64)) __builtin_unreachable (); + __builtin_atanhf64 (f3); + if (!(f4 > 0.0f64 && f4 < __builtin_inff64 ())) __builtin_unreachable (); + __builtin_logf64 (f4); + __builtin_log2f64 (f4); + __builtin_log10f64 (f4); + if (!(f5 > -1.0f64 && f5 < __builtin_inff64 ())) __builtin_unreachable (); + __builtin_log1pf64 (f5); + if (!(f6 >= 0.0f64 && f6 < __builtin_inff64 ())) __builtin_unreachable (); + __builtin_sqrtf64 (f6); + if (!(f7 > -710.0f64 && f7 < 710.0f64)) __builtin_unreachable (); + __builtin_coshf64 (f7); + __builtin_sinhf64 (f7); + if (!(f8 > -__builtin_inff64 () && f8 < 709.0f64)) __builtin_unreachable (); + __builtin_expf64 (f8); + if (!(f9 > -__builtin_inff64 () && f9 < 1024.0f64)) __builtin_unreachable (); + __builtin_exp2f64 (f9); +} +#endif + +#ifdef __FLT32X_MANT_DIG__ +void +flt32x (_Float32x f1, _Float32x f2, _Float32x f3, _Float32x f4, _Float32x f5, + _Float32x f6, _Float32x f7, _Float32x f8, _Float32x f9) +{ + if (!(f1 >= -1.0f32x && f1 <= 1.0f32x)) __builtin_unreachable (); + __builtin_acosf32x (f1); + __builtin_asinf32x (f1); + if (!(f2 >= 1.0f32x && f2 <= __builtin_inff32x ())) __builtin_unreachable (); + __builtin_acoshf32x (f2); + if (!(f3 > -1.0f32x && f3 < 1.0f32x)) __builtin_unreachable (); + __builtin_atanhf32x (f3); + if (!(f4 > 0.0f32x && f4 < __builtin_inff32x ())) __builtin_unreachable (); + __builtin_logf32x (f4); + __builtin_log2f32x (f4); + __builtin_log10f32x (f4); + if (!(f5 > -1.0f32x && f5 < __builtin_inff32x ())) __builtin_unreachable (); + __builtin_log1pf32x (f5); + if (!(f6 >= 0.0f32x && f6 < __builtin_inff32x ())) __builtin_unreachable (); + __builtin_sqrtf32x (f6); +#if __FLT32X_MANT_DIG__ == __FLT64_MANT_DIG__ && __FLT32X_MAX_EXP__ == __FLT64_MAX_EXP__ + if (!(f7 > -710.0f32x && f7 < 710.0f32x)) __builtin_unreachable (); + __builtin_coshf32x (f7); + __builtin_sinhf32x (f7); + if (!(f8 > -__builtin_inff32x () && f8 < 709.0f32x)) __builtin_unreachable (); + __builtin_expf32x (f8); + if (!(f9 > -__builtin_inff32x () && f9 < 1024.0f32x)) __builtin_unreachable (); + __builtin_exp2f32x (f9); +#endif +} +#endif + +void +ldbl (long double f1, long double f2, long double f3, long double f4, long double f5, + long double f6, long double f7, long double f8, long double f9, long double f10) +{ + if (!(f1 >= -1.0L && f1 <= 1.0L)) __builtin_unreachable (); + __builtin_acosl (f1); + __builtin_asinl (f1); + if (!(f2 >= 1.0L && f2 <= __builtin_infl ())) __builtin_unreachable (); + __builtin_acoshl (f2); + if (!(f3 > -1.0L && f3 < 1.0L)) __builtin_unreachable (); + __builtin_atanhl (f3); + if (!(f4 > 0.0L && f4 < __builtin_infl ())) __builtin_unreachable (); + __builtin_logl (f4); + __builtin_log2l (f4); + __builtin_log10l (f4); + if (!(f5 > -1.0L && f5 < __builtin_infl ())) __builtin_unreachable (); + __builtin_log1pl (f5); + if (!(f6 >= 0.0L && f6 < __builtin_infl ())) __builtin_unreachable (); + __builtin_sqrtl (f6); +#if __LDBL_MAX_EXP__ == 16384 + if (!(f7 > -11357.0L && f7 < 11357.0L)) __builtin_unreachable (); + __builtin_coshl (f7); + __builtin_sinhl (f7); + if (!(f8 > -__builtin_infl () && f8 < 11356.0L)) __builtin_unreachable (); + __builtin_expl (f8); + if (!(f9 > -__builtin_infl () && f9 < 16384.0L)) __builtin_unreachable (); + __builtin_exp2l (f9); + if (!(f10 > -__builtin_infl () && f10 < 4932.0L)) __builtin_unreachable (); + __builtin_exp10l (f10); +#elif __LDBL_MANT_DIG__ == __FLT64_MANT_DIG__ && __LDBL_MAX_EXP__ == __FLT64_MAX_EXP__ + if (!(f7 > -710.0L && f7 < 710.0L)) __builtin_unreachable (); + __builtin_coshl (f7); + __builtin_sinhl (f7); + if (!(f8 > -__builtin_infl () && f8 < 709.0L)) __builtin_unreachable (); + __builtin_expl (f8); + if (!(f9 > -__builtin_infl () && f9 < 1024.0L)) __builtin_unreachable (); + __builtin_exp2l (f9); + if (!(f10 > -__builtin_infl () && f10 < 308.0L)) __builtin_unreachable (); + __builtin_exp10l (f10); +#endif +} + +#ifdef __FLT128_MANT_DIG__ +void +flt128 (_Float128 f1, _Float128 f2, _Float128 f3, _Float128 f4, _Float128 f5, + _Float128 f6, _Float128 f7, _Float128 f8, _Float128 f9) +{ + if (!(f1 >= -1.0f128 && f1 <= 1.0f128)) __builtin_unreachable (); + __builtin_acosf128 (f1); + __builtin_asinf128 (f1); + if (!(f2 >= 1.0f128 && f2 <= __builtin_inff128 ())) __builtin_unreachable (); + __builtin_acoshf128 (f2); + if (!(f3 > -1.0f128 && f3 < 1.0f128)) __builtin_unreachable (); + __builtin_atanhf128 (f3); + if (!(f4 > 0.0f128 && f4 < __builtin_inff128 ())) __builtin_unreachable (); + __builtin_logf128 (f4); + __builtin_log2f128 (f4); + __builtin_log10f128 (f4); + if (!(f5 > -1.0f128 && f5 < __builtin_inff128 ())) __builtin_unreachable (); + __builtin_log1pf128 (f5); + if (!(f6 >= 0.0f128 && f6 < __builtin_inff128 ())) __builtin_unreachable (); + __builtin_sqrtf128 (f6); + if (!(f7 > -11357.0f128 && f7 < 11357.0f128)) __builtin_unreachable (); + __builtin_coshf128 (f7); + __builtin_sinhf128 (f7); + if (!(f8 > -__builtin_inff128 () && f8 < 11356.0f128)) __builtin_unreachable (); + __builtin_expf128 (f8); + if (!(f9 > -__builtin_inff128 () && f9 < 16384.0f128)) __builtin_unreachable (); + __builtin_exp2f128 (f9); +} +#endif + +#ifdef __FLT64X_MANT_DIG__ +void +flt64x (_Float64x f1, _Float64x f2, _Float64x f3, _Float64x f4, _Float64x f5, + _Float64x f6, _Float64x f7, _Float64x f8, _Float64x f9) +{ + if (!(f1 >= -1.0f64x && f1 <= 1.0f64x)) __builtin_unreachable (); + __builtin_acosf64x (f1); + __builtin_asinf64x (f1); + if (!(f2 >= 1.0f64x && f2 <= __builtin_inff64x ())) __builtin_unreachable (); + __builtin_acoshf64x (f2); + if (!(f3 > -1.0f64x && f3 < 1.0f64x)) __builtin_unreachable (); + __builtin_atanhf64x (f3); + if (!(f4 > 0.0f64x && f4 < __builtin_inff64x ())) __builtin_unreachable (); + __builtin_logf64x (f4); + __builtin_log2f64x (f4); + __builtin_log10f64x (f4); + if (!(f5 > -1.0f64x && f5 < __builtin_inff64x ())) __builtin_unreachable (); + __builtin_log1pf64x (f5); + if (!(f6 >= 0.0f64x && f6 < __builtin_inff64x ())) __builtin_unreachable (); + __builtin_sqrtf64x (f6); +#if __FLT64X_MAX_EXP__ == 16384 + if (!(f7 > -11357.0f64x && f7 < 11357.0f64x)) __builtin_unreachable (); + __builtin_coshf64x (f7); + __builtin_sinhf64x (f7); + if (!(f8 > -__builtin_inff64x () && f8 < 11356.0f64x)) __builtin_unreachable (); + __builtin_expf64x (f8); + if (!(f9 > -__builtin_inff64x () && f9 < 16384.0f64x)) __builtin_unreachable (); + __builtin_exp2f64x (f9); +#endif +} +#endif diff --git a/gcc/tree-call-cdce.cc b/gcc/tree-call-cdce.cc index ae5220c..7f67a0b 100644 --- a/gcc/tree-call-cdce.cc +++ b/gcc/tree-call-cdce.cc @@ -677,14 +677,14 @@ gen_conditions_for_pow (gcall *pow_call, vec conds, Since IEEE only sets minimum requirements for long double format, different long double formats exist under different implementations (e.g, 64 bit double precision (DF), 80 bit double-extended - precision (XF), and 128 bit quad precision (QF) ). For simplicity, + precision (XF), and 128 bit quad precision (TF) ). For simplicity, in this implementation, the computed bounds for long double assume - 64 bit format (DF), and are therefore conservative. Another - assumption is that single precision float type is always SF mode, - and double type is DF mode. This function is quite - implementation specific, so it may not be suitable to be part of - builtins.cc. This needs to be revisited later to see if it can - be leveraged in x87 assembly expansion. */ + 64 bit format (DF) except when it is IEEE quad or extended with the same + emax, and are therefore sometimes conservative. Another assumption is + that single precision float type is always SF mode, and double type is DF + mode. This function is quite implementation specific, so it may not be + suitable to be part of builtins.cc. This needs to be revisited later + to see if it can be leveraged in x87 assembly expansion. */ static inp_domain get_no_error_domain (enum built_in_function fnc) @@ -723,10 +723,10 @@ get_no_error_domain (enum built_in_function fnc) 89, true, false); case BUILT_IN_COSH: case BUILT_IN_SINH: - case BUILT_IN_COSHL: - case BUILT_IN_SINHL: case BUILT_IN_COSHF64: case BUILT_IN_SINHF64: + case BUILT_IN_COSHF32X: + case BUILT_IN_SINHF32X: /* cosh: (-710, +710) */ return get_domain (-710, true, false, 710, true, false); @@ -735,6 +735,16 @@ get_no_error_domain (enum built_in_function fnc) /* coshf128: (-11357, +11357) */ return get_domain (-11357, true, false, 11357, true, false); + case BUILT_IN_COSHL: + case BUILT_IN_SINHL: + if (REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384) + return get_no_error_domain (BUILT_IN_COSHF128); + return get_no_error_domain (BUILT_IN_COSH); + case BUILT_IN_COSHF64X: + case BUILT_IN_SINHF64X: + if (REAL_MODE_FORMAT (TYPE_MODE (float64x_type_node))->emax == 16384) + return get_no_error_domain (BUILT_IN_COSHF128); + return get_no_error_domain (BUILT_IN_COSH); /* Log functions: (0, +inf) */ CASE_FLT_FN (BUILT_IN_LOG): CASE_FLT_FN_FLOATN_NX (BUILT_IN_LOG): @@ -751,7 +761,7 @@ get_no_error_domain (enum built_in_function fnc) /* Exp functions. */ case BUILT_IN_EXPF16: case BUILT_IN_EXPM1F16: - /* expf: (-inf, 11) */ + /* expf16: (-inf, 11) */ return get_domain (-1, false, false, 11, true, false); case BUILT_IN_EXPF: @@ -763,10 +773,10 @@ get_no_error_domain (enum built_in_function fnc) 88, true, false); case BUILT_IN_EXP: case BUILT_IN_EXPM1: - case BUILT_IN_EXPL: - case BUILT_IN_EXPM1L: case BUILT_IN_EXPF64: case BUILT_IN_EXPM1F64: + case BUILT_IN_EXPF32X: + case BUILT_IN_EXPM1F32X: /* exp: (-inf, 709) */ return get_domain (-1, false, false, 709, true, false); @@ -775,6 +785,16 @@ get_no_error_domain (enum built_in_function fnc) /* expf128: (-inf, 11356) */ return get_domain (-1, false, false, 11356, true, false); + case BUILT_IN_EXPL: + case BUILT_IN_EXPM1L: + if (REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384) + return get_no_error_domain (BUILT_IN_EXPF128); + return get_no_error_domain (BUILT_IN_EXP); + case BUILT_IN_EXPF64X: + case BUILT_IN_EXPM1F64X: + if (REAL_MODE_FORMAT (TYPE_MODE (float64x_type_node))->emax == 16384) + return get_no_error_domain (BUILT_IN_EXPF128); + return get_no_error_domain (BUILT_IN_EXP); case BUILT_IN_EXP2F16: /* exp2f16: (-inf, 16) */ return get_domain (-1, false, false, @@ -785,8 +805,8 @@ get_no_error_domain (enum built_in_function fnc) return get_domain (-1, false, false, 128, true, false); case BUILT_IN_EXP2: - case BUILT_IN_EXP2L: case BUILT_IN_EXP2F64: + case BUILT_IN_EXP2F32X: /* exp2: (-inf, 1024) */ return get_domain (-1, false, false, 1024, true, false); @@ -794,6 +814,14 @@ get_no_error_domain (enum built_in_function fnc) /* exp2f128: (-inf, 16384) */ return get_domain (-1, false, false, 16384, true, false); + case BUILT_IN_EXP2L: + if (REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384) + return get_no_error_domain (BUILT_IN_EXP2F128); + return get_no_error_domain (BUILT_IN_EXP2); + case BUILT_IN_EXP2F64X: + if (REAL_MODE_FORMAT (TYPE_MODE (float64x_type_node))->emax == 16384) + return get_no_error_domain (BUILT_IN_EXP2F128); + return get_no_error_domain (BUILT_IN_EXP2); case BUILT_IN_EXP10F: case BUILT_IN_POW10F: /* exp10f: (-inf, 38) */ @@ -801,11 +829,16 @@ get_no_error_domain (enum built_in_function fnc) 38, true, false); case BUILT_IN_EXP10: case BUILT_IN_POW10: - case BUILT_IN_EXP10L: - case BUILT_IN_POW10L: /* exp10: (-inf, 308) */ return get_domain (-1, false, false, 308, true, false); + case BUILT_IN_EXP10L: + case BUILT_IN_POW10L: + if (REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384) + /* exp10l: (-inf, 4932) */ + return get_domain (-1, false, false, + 4932, true, false); + return get_no_error_domain (BUILT_IN_EXP10); /* sqrt: [0, +inf) */ CASE_FLT_FN (BUILT_IN_SQRT): CASE_FLT_FN_FLOATN_NX (BUILT_IN_SQRT): -- cgit v1.1 From a0782531b8270f0fdb3f3e09b4ce544d5d1eef14 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 22 Feb 2024 13:07:25 +0100 Subject: profile-count: Don't dump through a temporary buffer [PR111960] The profile_count::dump (char *, struct function * = NULL) const; method has a single caller, the profile_count::dump (FILE *f, struct function *fun) const; method and for that going through a temporary buffer is just slower and opens doors for buffer overflows, which is exactly why this P1 was filed. The buffer size is 64 bytes, the previous maximum "%" PRId64 " (%s)" would print up to 61 bytes in there (19 bytes for arbitrary uint64_t:61 bitfield printed as signed, "estimated locally, globally 0 adjusted" i.e. 38 bytes longest %s and 4 other characters). Now, after the r14-2389 changes, it can be 19 + 38 plus 11 other characters + %.4f, which is worst case 309 chars before decimal point, decimal point and 4 digits after it, so total 382 bytes. So, either we could bump the buffer[64] to buffer[400], or the following patch just drops the indirection through buffer and prints it directly to stream. After all, having APIs which fill in some buffer without passing down the size of the buffer is just asking for buffer overflows over time. 2024-02-22 Jakub Jelinek PR ipa/111960 * profile-count.h (profile_count::dump): Remove overload with char * first argument. * profile-count.cc (profile_count::dump): Change overload with char * first argument which uses sprintf into the overfload with FILE * first argument and use fprintf instead. Remove overload which wrapped it. --- gcc/profile-count.cc | 20 +++++--------------- gcc/profile-count.h | 3 --- 2 files changed, 5 insertions(+), 18 deletions(-) (limited to 'gcc') diff --git a/gcc/profile-count.cc b/gcc/profile-count.cc index 0cb1220..b26f38e 100644 --- a/gcc/profile-count.cc +++ b/gcc/profile-count.cc @@ -84,34 +84,24 @@ const char *profile_quality_display_names[] = "precise" }; -/* Dump THIS to BUFFER. */ +/* Dump THIS to F. */ void -profile_count::dump (char *buffer, struct function *fun) const +profile_count::dump (FILE *f, struct function *fun) const { if (!initialized_p ()) - sprintf (buffer, "uninitialized"); + fprintf (f, "uninitialized"); else if (fun && initialized_p () && fun->cfg && ENTRY_BLOCK_PTR_FOR_FN (fun)->count.initialized_p ()) - sprintf (buffer, "%" PRId64 " (%s, freq %.4f)", m_val, + fprintf (f, "%" PRId64 " (%s, freq %.4f)", m_val, profile_quality_display_names[m_quality], to_sreal_scale (ENTRY_BLOCK_PTR_FOR_FN (fun)->count).to_double ()); else - sprintf (buffer, "%" PRId64 " (%s)", m_val, + fprintf (f, "%" PRId64 " (%s)", m_val, profile_quality_display_names[m_quality]); } -/* Dump THIS to F. */ - -void -profile_count::dump (FILE *f, struct function *fun) const -{ - char buffer[64]; - dump (buffer, fun); - fputs (buffer, f); -} - /* Dump THIS to stderr. */ void diff --git a/gcc/profile-count.h b/gcc/profile-count.h index b773b4e..b3d7764 100644 --- a/gcc/profile-count.h +++ b/gcc/profile-count.h @@ -1299,9 +1299,6 @@ public: /* Output THIS to F. */ void dump (FILE *f, struct function *fun = NULL) const; - /* Output THIS to BUFFER. */ - void dump (char *buffer, struct function *fun = NULL) const; - /* Print THIS to stderr. */ void debug () const; -- cgit v1.1 From 549f251f055e3a0b0084189a3012c4f15d635e75 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 22 Feb 2024 10:50:12 +0100 Subject: tree-optimization/114027 - conditional reduction chain When we classify a conditional reduction chain as CONST_COND_REDUCTION we fail to verify all involved conditionals have the same constant. That's a quite unlikely situation so the following simply disables such classification when there's more than one reduction statement. PR tree-optimization/114027 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized condition reduction classification only for single-element chains. * gcc.dg/vect/pr114027.c: New testcase. --- gcc/testsuite/gcc.dg/vect/pr114027.c | 26 ++++++++++++++++++++++++++ gcc/tree-vect-loop.cc | 11 ++++++----- 2 files changed, 32 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/pr114027.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/vect/pr114027.c b/gcc/testsuite/gcc.dg/vect/pr114027.c new file mode 100644 index 0000000..ead9cdd --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr114027.c @@ -0,0 +1,26 @@ +#include "tree-vect.h" + +int __attribute__((noipa)) +foo (int *f, int n) +{ + int res = 0; + for (int i = 0; i < n; ++i) + { + if (f[2*i]) + res = 2; + if (f[2*i+1]) + res = -2; + } + return res; +} + +int f[] = { 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 0 }; + +int +main () +{ + if (foo (f, 16) != 2) + __builtin_abort (); + return 0; +} diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc index 5a5865c..35f1f8c 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -7759,17 +7759,18 @@ vectorizable_reduction (loop_vec_info loop_vinfo, < GET_MODE_SIZE (SCALAR_TYPE_MODE (TREE_TYPE (vectype_op[i])))))) vectype_in = vectype_op[i]; - if (op.code == COND_EXPR) + /* Record how the non-reduction-def value of COND_EXPR is defined. + ??? For a chain of multiple CONDs we'd have to match them up all. */ + if (op.code == COND_EXPR && reduc_chain_length == 1) { - /* Record how the non-reduction-def value of COND_EXPR is defined. */ if (dt == vect_constant_def) { cond_reduc_dt = dt; cond_reduc_val = op.ops[i]; } - if (dt == vect_induction_def - && def_stmt_info - && is_nonwrapping_integer_induction (def_stmt_info, loop)) + else if (dt == vect_induction_def + && def_stmt_info + && is_nonwrapping_integer_induction (def_stmt_info, loop)) { cond_reduc_dt = dt; cond_stmt_vinfo = def_stmt_info; -- cgit v1.1 From 92c40297991f51e7fa942f29517bc4398fce33f9 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 22 Feb 2024 14:22:29 +0100 Subject: tree-optimization/114048 - ICE in copy_reference_ops_from_ref The following adds another omission to the assert verifying we're not running into spurious off == -1. PR tree-optimization/114048 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF can also produce -1 off. * gcc.dg/torture/pr114048.c: New testcase. --- gcc/testsuite/gcc.dg/torture/pr114048.c | 25 +++++++++++++++++++++++++ gcc/tree-ssa-sccvn.cc | 2 ++ 2 files changed, 27 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/torture/pr114048.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/torture/pr114048.c b/gcc/testsuite/gcc.dg/torture/pr114048.c new file mode 100644 index 0000000..338000b --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr114048.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ + +typedef struct { + void *child[2]; + char otherbits; +} critbit0_node; + +int allprefixed_traverse(char *top) +{ + if (top) + { + critbit0_node *q = (void *)top - 1; + int direction = 0; + for (;; ++direction) + switch (allprefixed_traverse(q->child[direction])) + { + case 1: + break; + case 0: + return 0; + default: + return 1; + } + } +} diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index 3e93685..2587eb1 100644 --- a/gcc/tree-ssa-sccvn.cc +++ b/gcc/tree-ssa-sccvn.cc @@ -1185,6 +1185,8 @@ copy_reference_ops_from_ref (tree ref, vec *result) else { gcc_assert (known_ne (op.off, -1) + /* The constant offset can be -1. */ + || op.opcode == MEM_REF /* Out-of-bound indices can compute to a known -1 offset. */ || ((op.opcode == ARRAY_REF -- cgit v1.1 From c1667b1ef538e4da10cf83bdf1ae62d7bdd96128 Mon Sep 17 00:00:00 2001 From: Gaius Mulley Date: Thu, 22 Feb 2024 15:02:19 +0000 Subject: PR modula2/114055 improve error message when checking the BY constant The fix marks a constant created during the default BY clause of the FOR loop as internal. The type checker will always return true if checking against an internal const. gcc/m2/ChangeLog: PR modula2/114055 * gm2-compiler/M2Check.mod (Import): IsConstLitInternal and IsConstLit. (isInternal): New procedure function. (doCheck): Test for isInternal in either operand and early return true. * gm2-compiler/M2Quads.mod (PushOne): Rewrite with extra parameter internal. (BuildPseudoBy): Add TRUE parameter to PushOne call. (BuildIncProcedure): Add FALSE parameter to PushOne call. (BuildDecProcedure): Add FALSE parameter to PushOne call. * gm2-compiler/M2Range.mod (ForLoopBeginTypeCompatible): Uncomment code and tidy up error string. * gm2-compiler/SymbolTable.def (PutConstLitInternal): New procedure. (IsConstLitInternal): New procedure function. * gm2-compiler/SymbolTable.mod (PutConstLitInternal): New procedure. (IsConstLitInternal): New procedure function. (SymConstLit): New field IsInternal. (CreateConstLit): Initialize IsInternal to FALSE. gcc/testsuite/ChangeLog: PR modula2/114055 * gm2/pim/fail/forloopby.mod: New test. * gm2/pim/pass/forloopby2.mod: New test. Signed-off-by: Gaius Mulley --- gcc/m2/gm2-compiler/M2Check.mod | 28 ++++++++++++++++- gcc/m2/gm2-compiler/M2Quads.mod | 29 ++++++++++++----- gcc/m2/gm2-compiler/M2Range.mod | 4 +-- gcc/m2/gm2-compiler/SymbolTable.def | 19 +++++++++++ gcc/m2/gm2-compiler/SymbolTable.mod | 52 ++++++++++++++++++++++++++++++- gcc/testsuite/gm2/pim/fail/forloopby.mod | 17 ++++++++++ gcc/testsuite/gm2/pim/pass/forloopby2.mod | 18 +++++++++++ 7 files changed, 154 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/gm2/pim/fail/forloopby.mod create mode 100644 gcc/testsuite/gm2/pim/pass/forloopby2.mod (limited to 'gcc') diff --git a/gcc/m2/gm2-compiler/M2Check.mod b/gcc/m2/gm2-compiler/M2Check.mod index a296766..5b45ad3 100644 --- a/gcc/m2/gm2-compiler/M2Check.mod +++ b/gcc/m2/gm2-compiler/M2Check.mod @@ -39,7 +39,15 @@ FROM M2Error IMPORT Error, InternalError, NewError, ErrorString, ChainError ; FROM M2MetaError IMPORT MetaErrorStringT2, MetaErrorStringT3, MetaErrorStringT4, MetaString2, MetaString3, MetaString4 ; FROM StrLib IMPORT StrEqual ; FROM M2Debug IMPORT Assert ; -FROM SymbolTable IMPORT NulSym, IsRecord, IsSet, GetDType, GetSType, IsType, SkipType, IsProcedure, NoOfParam, IsVarParam, GetNth, GetNthParam, IsProcType, IsVar, IsEnumeration, IsArray, GetDeclaredMod, IsSubrange, GetArraySubscript, IsConst, IsReallyPointer, IsPointer, IsParameter, ModeOfAddr, GetMode, GetType, IsUnbounded, IsComposite, IsConstructor, IsParameter, IsConstString ; + +FROM SymbolTable IMPORT NulSym, IsRecord, IsSet, GetDType, GetSType, IsType, + SkipType, IsProcedure, NoOfParam, IsVarParam, GetNth, + GetNthParam, IsProcType, IsVar, IsEnumeration, IsArray, + GetDeclaredMod, IsSubrange, GetArraySubscript, IsConst, + IsReallyPointer, IsPointer, IsParameter, ModeOfAddr, + GetMode, GetType, IsUnbounded, IsComposite, IsConstructor, + IsParameter, IsConstString, IsConstLitInternal, IsConstLit ; + FROM M2GCCDeclare IMPORT GetTypeMin, GetTypeMax ; FROM M2System IMPORT Address ; FROM M2ALU IMPORT Equ, PushIntegerTree ; @@ -1371,6 +1379,17 @@ END get ; (* + isInternal - return TRUE if sym is a constant lit which was declared + as internal. +*) + +PROCEDURE isInternal (sym: CARDINAL) : BOOLEAN ; +BEGIN + RETURN IsConstLit (sym) AND IsConstLitInternal (sym) +END isInternal ; + + +(* doCheck - keep obtaining an unresolved pair and check for the type compatibility. This is the main check routine used by parameter, assignment and expression compatibility. @@ -1393,6 +1412,13 @@ BEGIN printf ("doCheck (%d, %d)\n", left, right) ; dumptInfo (tinfo) END ; + IF isInternal (left) OR isInternal (right) + THEN + (* Do not check constants which have been generated internally. + Currently these are generated by the default BY constant value + in a FOR loop. *) + RETURN TRUE + END ; (* IF in (tinfo^.visited, left, right) THEN diff --git a/gcc/m2/gm2-compiler/M2Quads.mod b/gcc/m2/gm2-compiler/M2Quads.mod index 1275ad2f..ff0fda9 100644 --- a/gcc/m2/gm2-compiler/M2Quads.mod +++ b/gcc/m2/gm2-compiler/M2Quads.mod @@ -85,6 +85,7 @@ FROM SymbolTable IMPORT ModeOfAddr, GetMode, PutMode, GetSymName, IsUnknown, PutPriority, GetPriority, PutProcedureBegin, PutProcedureEnd, PutVarConst, IsVarConst, + PutConstLitInternal, PutVarHeap, IsVarParam, IsProcedure, IsPointer, IsParameter, IsUnboundedParam, IsEnumeration, IsDefinitionForC, @@ -4347,11 +4348,16 @@ END BuildElsif2 ; |------------| *) -PROCEDURE PushOne (tok: CARDINAL; type: CARDINAL; message: ARRAY OF CHAR) ; +PROCEDURE PushOne (tok: CARDINAL; type: CARDINAL; + message: ARRAY OF CHAR; internal: BOOLEAN) ; +VAR + const: CARDINAL ; BEGIN IF type = NulSym THEN - PushTF (MakeConstLit (tok, MakeKey('1'), NulSym), NulSym) + const := MakeConstLit (tok, MakeKey('1'), NulSym) ; + PutConstLitInternal (const, TRUE) ; + PushTFtok (const, NulSym, tok) ELSIF IsEnumeration (type) THEN IF NoOfElements (type) = 0 @@ -4361,14 +4367,16 @@ BEGIN type) ; PushZero (tok, type) ELSE - PushTF (Convert, NulSym) ; + PushTFtok (Convert, NulSym, tok) ; PushT (type) ; - PushT (MakeConstLit (tok, MakeKey ('1'), ZType)) ; + PushTFtok (MakeConstLit (tok, MakeKey ('1'), ZType), ZType, tok) ; PushT (2) ; (* Two parameters *) BuildConvertFunction END ELSE - PushTF (MakeConstLit (tok, MakeKey ('1'), type), type) + const := MakeConstLit (tok, MakeKey ('1'), type) ; + PutConstLitInternal (const, TRUE) ; + PushTFtok (const, type, tok) END END PushOne ; @@ -4440,7 +4448,8 @@ BEGIN THEN type := ZType END ; - PushOne (dotok, type, 'the implied {%kFOR} loop increment will cause an overflow {%1ad}') + PushOne (dotok, type, + 'the implied {%kFOR} loop increment will cause an overflow {%1ad}', TRUE) END BuildPseudoBy ; @@ -4648,6 +4657,8 @@ END BuildForToByDo ; Ptr -> +----------------+ + | RangeId | + |----------------| | ForQuad | |----------------| | LastValue | @@ -7294,7 +7305,8 @@ BEGIN THEN OperandSym := DereferenceLValue (OperandTok (1), OperandT (1)) ELSE - PushOne (proctok, dtype, 'the {%EkINC} will cause an overflow {%1ad}') ; + PushOne (proctok, dtype, + 'the {%EkINC} will cause an overflow {%1ad}', FALSE) ; PopT (OperandSym) END ; @@ -7366,7 +7378,8 @@ BEGIN THEN OperandSym := DereferenceLValue (OperandTok (1), OperandT (1)) ELSE - PushOne (proctok, dtype, 'the {%EkDEC} will cause an overflow {%1ad}') ; + PushOne (proctok, dtype, + 'the {%EkDEC} will cause an overflow {%1ad}', FALSE) ; PopT (OperandSym) END ; diff --git a/gcc/m2/gm2-compiler/M2Range.mod b/gcc/m2/gm2-compiler/M2Range.mod index fa1ef35..654ac04 100644 --- a/gcc/m2/gm2-compiler/M2Range.mod +++ b/gcc/m2/gm2-compiler/M2Range.mod @@ -1886,16 +1886,14 @@ BEGIN des, expr2) ; success := FALSE END ; -(* combinedtok := MakeVirtual2Tok (destok, byconsttok) ; IF NOT ExpressionTypeCompatible (combinedtok, "", des, byconst, TRUE, FALSE) THEN MetaErrorT2 (combinedtok, - 'type expression incompatibility between {%1Et} and {%2t} detected between the the designator {%1a} and the {%kBY} constant expression {%2a} in the {%kFOR} loop', + 'type expression incompatibility between {%1Et} and {%2t} detected between the designator {%1a} and the {%kBY} constant expression {%2a} in the {%kFOR} loop', des, byconst) ; success := FALSE END ; -*) IF (NOT success) AND (incrementquad # 0) THEN (* Avoid a subsequent generic type check error. *) diff --git a/gcc/m2/gm2-compiler/SymbolTable.def b/gcc/m2/gm2-compiler/SymbolTable.def index 508b818..ec48631 100644 --- a/gcc/m2/gm2-compiler/SymbolTable.def +++ b/gcc/m2/gm2-compiler/SymbolTable.def @@ -3315,4 +3315,23 @@ PROCEDURE PutProcedureParameterHeapVars (sym: CARDINAL) ; PROCEDURE IsProcedureBuiltinAvailable (procedure: CARDINAL) : BOOLEAN ; +(* + PutConstLitInternal - marks the sym as being an internal constant. + Currently this is used when generating a default + BY constant expression during a FOR loop. + A constant marked as internal will always pass + an expression type check. +*) + +PROCEDURE PutConstLitInternal (sym: CARDINAL; value: BOOLEAN) ; + + +(* + IsConstLitInternal - returns the value of the IsInternal field within + a constant expression. +*) + +PROCEDURE IsConstLitInternal (sym: CARDINAL) : BOOLEAN ; + + END SymbolTable. diff --git a/gcc/m2/gm2-compiler/SymbolTable.mod b/gcc/m2/gm2-compiler/SymbolTable.mod index 6fe36da..c57c033 100644 --- a/gcc/m2/gm2-compiler/SymbolTable.mod +++ b/gcc/m2/gm2-compiler/SymbolTable.mod @@ -487,7 +487,8 @@ TYPE Value : PtrToValue ; (* Value of the constant. *) Type : CARDINAL ; (* TYPE of constant, char etc *) IsSet : BOOLEAN ; (* is the constant a set? *) - IsConstructor: BOOLEAN ; (* is the constant a set? *) + IsConstructor: BOOLEAN ; (* is it a constructor? *) + IsInternal : BOOLEAN ; (* Generated internally? *) FromType : CARDINAL ; (* type is determined FromType *) RangeError : BOOLEAN ; (* Have we reported an error? *) UnresFromType: BOOLEAN ; (* is Type unresolved? *) @@ -4865,6 +4866,8 @@ BEGIN PopInto (ConstLit.Value) ; ConstLit.Type := constType ; ConstLit.IsSet := FALSE ; + ConstLit.IsInternal := FALSE ; (* Is it a default BY constant + expression? *) ConstLit.IsConstructor := FALSE ; ConstLit.FromType := NulSym ; (* type is determined FromType *) ConstLit.RangeError := overflow ; @@ -6791,6 +6794,53 @@ END PutConst ; (* + PutConstLitInternal - marks the sym as being an internal constant. + Currently this is used when generating a default + BY constant expression during a FOR loop. + A constant marked as internal will always pass + an expression type check. +*) + +PROCEDURE PutConstLitInternal (sym: CARDINAL; value: BOOLEAN) ; +VAR + pSym: PtrToSymbol ; +BEGIN + pSym := GetPsym (sym) ; + WITH pSym^ DO + CASE SymbolType OF + + ConstLitSym: ConstLit.IsInternal := value + + ELSE + InternalError ('expecting ConstLitSym') + END + END +END PutConstLitInternal ; + + +(* + IsConstLitInternal - returns the value of the IsInternal field within + a constant expression. +*) + +PROCEDURE IsConstLitInternal (sym: CARDINAL) : BOOLEAN ; +VAR + pSym: PtrToSymbol ; +BEGIN + pSym := GetPsym (sym) ; + WITH pSym^ DO + CASE SymbolType OF + + ConstLitSym: RETURN ConstLit.IsInternal + + ELSE + InternalError ('expecting ConstLitSym') + END + END +END IsConstLitInternal ; + + +(* PutVarArrayRef - assigns ArrayRef field with value. *) diff --git a/gcc/testsuite/gm2/pim/fail/forloopby.mod b/gcc/testsuite/gm2/pim/fail/forloopby.mod new file mode 100644 index 0000000..522563b --- /dev/null +++ b/gcc/testsuite/gm2/pim/fail/forloopby.mod @@ -0,0 +1,17 @@ +MODULE forloopby ; + + +PROCEDURE init ; +CONST + increment = CARDINAL (1) ; +VAR + i: INTEGER ; +BEGIN + FOR i := 0 TO 10 BY increment DO + END +END init ; + + +BEGIN + init +END forloopby. diff --git a/gcc/testsuite/gm2/pim/pass/forloopby2.mod b/gcc/testsuite/gm2/pim/pass/forloopby2.mod new file mode 100644 index 0000000..a81ecb0 --- /dev/null +++ b/gcc/testsuite/gm2/pim/pass/forloopby2.mod @@ -0,0 +1,18 @@ +MODULE forloopby2 ; + +TYPE + negative = [-10..-1] ; + + +PROCEDURE init ; +VAR + i: negative ; +BEGIN + FOR i := MIN (negative) TO MAX (negative) DO + END +END init ; + + +BEGIN + init +END forloopby2. -- cgit v1.1 From 7d8585c0c0e5934780281abdee256ae6553e56e8 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Thu, 22 Feb 2024 15:32:08 +0000 Subject: AArch64: update vget_set_lane_1.c test output In the vget_set_lane_1.c test the following entries now generate a zip1 instead of an INS BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0) BUILD_TEST (int32x2_t, int32x2_t, , , s32, 1, 0) BUILD_TEST (uint32x2_t, uint32x2_t, , , u32, 1, 0) This is because the non-Q variant for indices 0 and 1 are just shuffling values. There is no perf difference between INS SIMD to SIMD and ZIP on Arm uArches but preferring the INS alternative has a drawback on all uArches as ZIP being a three operand instruction can be used to tie the result to the return register whereas INS would require an fmov. As such just update the test file for now. gcc/testsuite/ChangeLog: PR target/112375 * gcc.target/aarch64/vget_set_lane_1.c: Update test output. --- gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c b/gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c index 07a77de..a3978f6 100644 --- a/gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c @@ -22,7 +22,7 @@ BUILD_TEST (uint16x4_t, uint16x4_t, , , u16, 3, 2) BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0) BUILD_TEST (int32x2_t, int32x2_t, , , s32, 1, 0) BUILD_TEST (uint32x2_t, uint32x2_t, , , u32, 1, 0) -/* { dg-final { scan-assembler-times "ins\\tv0.s\\\[1\\\], v1.s\\\[0\\\]" 3 } } */ +/* { dg-final { scan-assembler-times "zip1\\tv0.2s, v0.2s, v1.2s" 3 } } */ BUILD_TEST (poly8x8_t, poly8x16_t, , q, p8, 7, 15) BUILD_TEST (int8x8_t, int8x16_t, , q, s8, 7, 15) -- cgit v1.1 From 1076ffda6ce5e6d5fc9577deaf8233e549e5787a Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Wed, 21 Feb 2024 20:12:21 -0800 Subject: warn-access: Fix handling of unnamed types [PR109804] This looks like an oversight of handling DEMANGLE_COMPONENT_UNNAMED_TYPE. DEMANGLE_COMPONENT_UNNAMED_TYPE only has the u.s_number.number set while the code expected newc.u.s_binary.left would be valid. So this treats DEMANGLE_COMPONENT_UNNAMED_TYPE like we treat function paramaters (DEMANGLE_COMPONENT_FUNCTION_PARAM) and template paramaters (DEMANGLE_COMPONENT_TEMPLATE_PARAM). Note the code in the demangler does this when it sets DEMANGLE_COMPONENT_UNNAMED_TYPE: ret->type = DEMANGLE_COMPONENT_UNNAMED_TYPE; ret->u.s_number.number = num; Committed as obvious after bootstrap/test on x86_64-linux-gnu PR tree-optimization/109804 gcc/ChangeLog: * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle DEMANGLE_COMPONENT_UNNAMED_TYPE. gcc/testsuite/ChangeLog: * g++.dg/warn/Wmismatched-new-delete-8.C: New test. Signed-off-by: Andrew Pinski --- gcc/gimple-ssa-warn-access.cc | 1 + .../g++.dg/warn/Wmismatched-new-delete-8.C | 42 ++++++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-8.C (limited to 'gcc') diff --git a/gcc/gimple-ssa-warn-access.cc b/gcc/gimple-ssa-warn-access.cc index cd083ab..dedaae2 100644 --- a/gcc/gimple-ssa-warn-access.cc +++ b/gcc/gimple-ssa-warn-access.cc @@ -1701,6 +1701,7 @@ new_delete_mismatch_p (const demangle_component &newc, case DEMANGLE_COMPONENT_FUNCTION_PARAM: case DEMANGLE_COMPONENT_TEMPLATE_PARAM: + case DEMANGLE_COMPONENT_UNNAMED_TYPE: return newc.u.s_number.number != delc.u.s_number.number; case DEMANGLE_COMPONENT_CHARACTER: diff --git a/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-8.C b/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-8.C new file mode 100644 index 0000000..0ddc056 --- /dev/null +++ b/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-8.C @@ -0,0 +1,42 @@ +/* PR tree-optimization/109804 */ +/* { dg-do compile { target c++11 } } */ +/* { dg-options "-Wall" } */ + +/* Here we used to ICE in new_delete_mismatch_p because + we didn't handle unnamed types from the demangler (DEMANGLE_COMPONENT_UNNAMED_TYPE). */ + +template +static inline T * construct_at(void *at, ARGS && args) +{ + struct Placeable : T + { + Placeable(ARGS && args) : T(args) { } + void * operator new (long unsigned int, void *ptr) { return ptr; } + void operator delete (void *, void *) { } + }; + return new (at) Placeable(static_cast(args)); +} +template +struct Reconstructible +{ + char _space[sizeof(MT)]; + Reconstructible() { } +}; +template +struct Constructible : Reconstructible +{ + Constructible(){} +}; +struct A { }; +struct B +{ + Constructible a { }; + B(int) { } +}; +Constructible b { }; +void f() +{ + enum { ENUM_A = 1 }; + enum { ENUM_B = 1 }; + construct_at(b._space, ENUM_B); +} -- cgit v1.1 From 37127ed975e09813eaa2d1cf1062055fce45dd16 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 22 Feb 2024 19:32:02 +0100 Subject: c: Handle scoped attributes in __has*attribute and scoped attribute parsing changes in -std=c11 etc. modes [PR114007] We aren't able to parse __has_attribute (vendor::attr) (and __has_c_attribute and __has_cpp_attribute) in strict C < C23 modes. While in -std=gnu* modes or in -std=c23 there is CPP_SCOPE token, in -std=c* (except for -std=c23) there are is just a pair of CPP_COLON tokens. The c-lex.cc hunk adds support for that. That leads to a question if we should return 1 or 0 from __has_attribute (gnu::unused) or not, because while [[gnu::unused]] is parsed fine in -std=gnu*/-std=c23 modes (sure, with pedwarn for < C23), we do not parse it at all in -std=c* (except for -std=c23), we only parse [[__extension__ gnu::unused]] there. While the __extension__ in there helps to avoid the pedwarn, I think it is better to be consistent between GNU and strict C < C23 modes and parse [[gnu::unused]] too; on the other side, I think parsing [[__extension__ gnu : : unused]] is too weird and undesirable. So, the following patch adds a flag during preprocessing at the point where we normally create CPP_SCOPE tokens out of 2 consecutive colons on the first CPP_COLON to mark the consecutive case (as we are tight on the bits, I've reused the PURE_ZERO flag, which is used just by the C++ FE and only ever set (both C and C++) on CPP_NUMBER tokens, this new flag has the same value and is only ever used on CPP_COLON tokens) and instead of checking loose_scope_p argument (i.e. whether it is [[__extension__ ...]] or not), it just parses CPP_SCOPE or CPP_COLON with CLONE_SCOPE flag followed by another CPP_COLON the same. The latter will never appear in >= C23 or -std=gnu* modes, though guarding its use say with flag_iso && !flag_isoc23 && doesn't really work because the __extension__ case temporarily clears flag_iso flag. This makes the -std=c11 etc. behavior more similar to -std=gnu11 or -std=c23, the only difference I'm aware of are the #define JOIN2(A, B) A##B [[vendor JOIN2(:,:) attr]] [[__extension__ vendor JOIN2(:,:) attr]] cases, which are accepted in the latter modes, but results in error in -std=c11; but the error is during preprocessing that :: doesn't form a valid preprocessing token, which is true, so just don't do that if you try to have __STRICT_ANSI__ && __STDC_VERSION__ <= 201710L compatibility. 2024-02-22 Jakub Jelinek PR c/114007 gcc/ * doc/extend.texi: (__extension__): Remove comments about scope tokens vs. two colons. gcc/c-family/ * c-lex.cc (c_common_has_attribute): Parse 2 CPP_COLONs with the first one with COLON_SCOPE flag the same as CPP_SCOPE. gcc/c/ * c-parser.cc (c_parser_std_attribute): Remove loose_scope_p argument. Instead of checking it, parse 2 CPP_COLONs with the first one with COLON_SCOPE flag the same as CPP_SCOPE. (c_parser_std_attribute_list): Remove loose_scope_p argument, don't pass it to c_parser_std_attribute. (c_parser_std_attribute_specifier): Adjust c_parser_std_attribute_list caller. gcc/testsuite/ * gcc.dg/c23-attr-syntax-6.c: Adjust testcase for :: being valid even in -std=c11 even without __extension__ and : : etc. not being valid anymore even with __extension__. * gcc.dg/c23-attr-syntax-7.c: Likewise. * gcc.dg/c23-attr-syntax-8.c: New test. libcpp/ * include/cpplib.h (COLON_SCOPE): Define to PURE_ZERO. * lex.cc (_cpp_lex_direct): When lexing CPP_COLON with another colon after it, if !CPP_OPTION (pfile, scope) set COLON_SCOPE flag on the first CPP_COLON token. --- gcc/c-family/c-lex.cc | 22 +++++++++++- gcc/c/c-parser.cc | 14 ++++---- gcc/doc/extend.texi | 5 +-- gcc/testsuite/gcc.dg/c23-attr-syntax-6.c | 57 +++++++++++++++++++++++--------- gcc/testsuite/gcc.dg/c23-attr-syntax-7.c | 54 +++++++++++++++++++++--------- gcc/testsuite/gcc.dg/c23-attr-syntax-8.c | 12 +++++++ 6 files changed, 119 insertions(+), 45 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/c23-attr-syntax-8.c (limited to 'gcc') diff --git a/gcc/c-family/c-lex.cc b/gcc/c-family/c-lex.cc index 8b0987e..ff5ce2b 100644 --- a/gcc/c-family/c-lex.cc +++ b/gcc/c-family/c-lex.cc @@ -357,7 +357,27 @@ c_common_has_attribute (cpp_reader *pfile, bool std_syntax) do nxt_token = cpp_peek_token (pfile, idx++); while (nxt_token->type == CPP_PADDING); - if (nxt_token->type == CPP_SCOPE) + if (!c_dialect_cxx () + && nxt_token->type == CPP_COLON + && (nxt_token->flags & COLON_SCOPE) != 0) + { + const cpp_token *prev_token = nxt_token; + do + nxt_token = cpp_peek_token (pfile, idx++); + while (nxt_token->type == CPP_PADDING); + if (nxt_token->type == CPP_COLON) + { + /* __has_attribute (vendor::attr) in -std=c17 etc. modes. + :: isn't CPP_SCOPE but 2 CPP_COLON tokens, where the + first one should have COLON_SCOPE flag to distinguish + it from : :. */ + have_scope = true; + get_token_no_padding (pfile); // Eat first colon. + } + else + nxt_token = prev_token; + } + if (nxt_token->type == CPP_SCOPE || have_scope) { have_scope = true; get_token_no_padding (pfile); // Eat scope. diff --git a/gcc/c/c-parser.cc b/gcc/c/c-parser.cc index 3be91d6..8019e60 100644 --- a/gcc/c/c-parser.cc +++ b/gcc/c/c-parser.cc @@ -5705,8 +5705,7 @@ c_parser_omp_sequence_args (c_parser *parser, tree attribute) indicates whether this relaxation is in effect. */ static tree -c_parser_std_attribute (c_parser *parser, bool for_tm, - bool loose_scope_p = false) +c_parser_std_attribute (c_parser *parser, bool for_tm) { c_token *token = c_parser_peek_token (parser); tree ns, name, attribute; @@ -5720,8 +5719,8 @@ c_parser_std_attribute (c_parser *parser, bool for_tm, name = canonicalize_attr_name (token->value); c_parser_consume_token (parser); if (c_parser_next_token_is (parser, CPP_SCOPE) - || (loose_scope_p - && c_parser_next_token_is (parser, CPP_COLON) + || (c_parser_next_token_is (parser, CPP_COLON) + && (c_parser_peek_token (parser)->flags & COLON_SCOPE) != 0 && c_parser_peek_2nd_token (parser)->type == CPP_COLON)) { ns = name; @@ -5841,8 +5840,7 @@ c_parser_std_attribute (c_parser *parser, bool for_tm, } static tree -c_parser_std_attribute_list (c_parser *parser, bool for_tm, - bool loose_scope_p = false) +c_parser_std_attribute_list (c_parser *parser, bool for_tm) { tree attributes = NULL_TREE; while (true) @@ -5855,7 +5853,7 @@ c_parser_std_attribute_list (c_parser *parser, bool for_tm, c_parser_consume_token (parser); continue; } - tree attribute = c_parser_std_attribute (parser, for_tm, loose_scope_p); + tree attribute = c_parser_std_attribute (parser, for_tm); if (attribute != error_mark_node) { TREE_CHAIN (attribute) = attributes; @@ -5883,7 +5881,7 @@ c_parser_std_attribute_specifier (c_parser *parser, bool for_tm) { auto ext = disable_extension_diagnostics (); c_parser_consume_token (parser); - attributes = c_parser_std_attribute_list (parser, for_tm, true); + attributes = c_parser_std_attribute_list (parser, for_tm); restore_extension_diagnostics (ext); } else diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 52b5a1f..efd78014 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -12626,10 +12626,7 @@ In C, writing: @end smallexample suppresses warnings about using @samp{[[]]} attributes in C versions -that predate C23@. Since the scope token @samp{::} is not a single -lexing token in earlier versions of C, this construct also allows two colons -to be used in place of @code{::}. GCC does not check whether the two -colons are immediately adjacent. +that predate C23@. @end itemize @code{__extension__} has no effect aside from this. diff --git a/gcc/testsuite/gcc.dg/c23-attr-syntax-6.c b/gcc/testsuite/gcc.dg/c23-attr-syntax-6.c index ae1e757..f8c5b0f 100644 --- a/gcc/testsuite/gcc.dg/c23-attr-syntax-6.c +++ b/gcc/testsuite/gcc.dg/c23-attr-syntax-6.c @@ -9,19 +9,14 @@ typedef int [[__extension__ gnu::vector_size (4)]] g1; typedef int [[__extension__ gnu :: vector_size (4)]] g2; -typedef int [[__extension__ gnu : : vector_size (4)]] g3; -typedef int [[__extension__ gnu: :vector_size (4)]] g4; -typedef int [[__extension__ gnu FOO vector_size (4)]] g5; -typedef int [[__extension__ gnu BAR BAR vector_size (4)]] g6; -typedef int [[__extension__ gnu :/**/: vector_size (4)]] g7; -typedef int [[__extension__ gnu JOIN(:,:) vector_size (4)]] g8; -typedef int [[__extension__ gnu :: vector_size (sizeof (void (*)(...)))]] g10; -typedef int [[__extension__]] g11; -typedef int [[__extension__,]] g12; -typedef int [[__extension__, ,,,, ,, ,]] g13; -[[__extension__ deprecated]] int g14 (); -[[__extension__ nodiscard]] int g15 (); -[[__extension__ noreturn]] void g16 (); +typedef int [[__extension__ gnu FOO vector_size (4)]] g3; +typedef int [[__extension__ gnu :: vector_size (sizeof (void (*)(...)))]] g4; +typedef int [[__extension__]] g5; +typedef int [[__extension__,]] g6; +typedef int [[__extension__, ,,,, ,, ,]] g7; +[[__extension__ deprecated]] int g8 (); +[[__extension__ nodiscard]] int g9 (); +[[__extension__ noreturn]] void g10 (); int cases (int x) @@ -51,12 +46,42 @@ typedef int [[__extension__ unknown_attribute]] b3; /* { dg-error {'unknown_attr typedef int [[__extension__ gnu:vector_size(4)]] b4; /* { dg-error {expected '\]' before ':'} } */ /* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ typedef int [[__extension__ gnu JOIN2(:,:) vector_size (4)]] b5; /* { dg-error {pasting ":" and ":" does not give a valid preprocessing token} } */ -typedef int [[gnu::vector_size(4)]] b6; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {expected '\]' before ':'} "" { target *-*-* } .-1 } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-2 } */ +typedef int [[__extension__ gnu : : vector_size (4)]] b6; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +typedef int [[__extension__ gnu: :vector_size (4)]] b7; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +typedef int [[__extension__ gnu BAR BAR vector_size (4)]] b8; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +typedef int [[__extension__ gnu :/**/: vector_size (4)]] b9; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +typedef int [[__extension__ gnu JOIN(:,:) vector_size (4)]] b10; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +typedef int [[gnu::vector_size(4)]] b11; /* { dg-error {attributes before C23} } */ +typedef int [[gnu : : vector_size(4)]] b12; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +/* { dg-error {attributes before C23} "" { target *-*-* } .-2 } */ +typedef int [[gnu : vector_size(4)]] b13; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +/* { dg-error {attributes before C23} "" { target *-*-* } .-2 } */ +typedef int [[gnu: :vector_size (4)]] b14; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +/* { dg-error {attributes before C23} "" { target *-*-* } .-2 } */ +typedef int [[gnu BAR BAR vector_size (4)]] b15; /* { dg-error {expected '\]' before ':'} } */ /* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ /* { dg-error {attributes before C23} "" { target *-*-* } .-2 } */ -typedef int [[gnu : : vector_size(4)]] b7; /* { dg-error {expected '\]' before ':'} } */ +typedef int [[gnu :/**/: vector_size (4)]] b16; /* { dg-error {expected '\]' before ':'} } */ /* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ /* { dg-error {attributes before C23} "" { target *-*-* } .-2 } */ -typedef int [[gnu : vector_size(4)]] b8; /* { dg-error {expected '\]' before ':'} } */ +typedef int [[gnu JOIN(:,:) vector_size (4)]] b17; /* { dg-error {expected '\]' before ':'} } */ /* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ /* { dg-error {attributes before C23} "" { target *-*-* } .-2 } */ +typedef int [[gnu :: vector_size (4)]] b18; /* { dg-error {attributes before C23} } */ +typedef int [[gnu FOO vector_size (4)]] b19; /* { dg-error {attributes before C23} } */ +typedef int [[gnu :: vector_size (sizeof (void (*)(...)))]] b20; /* { dg-error {attributes before C23} } */ +/* { dg-error {requires a named argument before} "" { target *-*-* } .-1 } */ +typedef int [[gnu JOIN2(:,:) vector_size (4)]] b21; /* { dg-error {pasting ":" and ":" does not give a valid preprocessing token} } */ +/* { dg-error {expected '\]' before ':'} "" { target *-*-* } .-1 } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-2 } */ +/* { dg-error {attributes before C23} "" { target *-*-* } .-3 } */ diff --git a/gcc/testsuite/gcc.dg/c23-attr-syntax-7.c b/gcc/testsuite/gcc.dg/c23-attr-syntax-7.c index cf3b1ff..b34b73a 100644 --- a/gcc/testsuite/gcc.dg/c23-attr-syntax-7.c +++ b/gcc/testsuite/gcc.dg/c23-attr-syntax-7.c @@ -9,19 +9,14 @@ typedef int [[__extension__ gnu::vector_size (4)]] g1; typedef int [[__extension__ gnu :: vector_size (4)]] g2; -typedef int [[__extension__ gnu : : vector_size (4)]] g3; -typedef int [[__extension__ gnu: :vector_size (4)]] g4; -typedef int [[__extension__ gnu FOO vector_size (4)]] g5; -typedef int [[__extension__ gnu BAR BAR vector_size (4)]] g6; -typedef int [[__extension__ gnu :/**/: vector_size (4)]] g7; -typedef int [[__extension__ gnu JOIN(:,:) vector_size (4)]] g8; -typedef int [[__extension__ gnu :: vector_size (sizeof (void (*)(...)))]] g10; -typedef int [[__extension__]] g11; -typedef int [[__extension__,]] g12; -typedef int [[__extension__, ,,,, ,, ,]] g13; -[[__extension__ deprecated]] int g14 (); -[[__extension__ nodiscard]] int g15 (); -[[__extension__ noreturn]] void g16 (); +typedef int [[__extension__ gnu FOO vector_size (4)]] g3; +typedef int [[__extension__ gnu :: vector_size (sizeof (void (*)(...)))]] g4; +typedef int [[__extension__]] g5; +typedef int [[__extension__,]] g6; +typedef int [[__extension__, ,,,, ,, ,]] g7; +[[__extension__ deprecated]] int g8 (); +[[__extension__ nodiscard]] int g9 (); +[[__extension__ noreturn]] void g10 (); int cases (int x) @@ -51,10 +46,37 @@ typedef int [[__extension__ unknown_attribute]] b3; /* { dg-error {'unknown_attr typedef int [[__extension__ gnu:vector_size(4)]] b4; /* { dg-error {expected '\]' before ':'} } */ /* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ typedef int [[__extension__ gnu JOIN2(:,:) vector_size (4)]] b5; -typedef int [[gnu::vector_size(4)]] b6; /* { dg-warning {attributes before C23} } */ -typedef int [[gnu : : vector_size(4)]] b7; /* { dg-error {expected '\]' before ':'} } */ +typedef int [[__extension__ gnu : : vector_size (4)]] b6; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +typedef int [[__extension__ gnu: :vector_size (4)]] b7; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +typedef int [[__extension__ gnu BAR BAR vector_size (4)]] b8; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +typedef int [[__extension__ gnu :/**/: vector_size (4)]] b9; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +typedef int [[__extension__ gnu JOIN(:,:) vector_size (4)]] b10; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +typedef int [[gnu::vector_size(4)]] b11; /* { dg-warning {attributes before C23} } */ +typedef int [[gnu : : vector_size(4)]] b12; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +/* { dg-warning {attributes before C23} "" { target *-*-* } .-2 } */ +typedef int [[gnu : vector_size(4)]] b13; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +/* { dg-warning {attributes before C23} "" { target *-*-* } .-2 } */ +typedef int [[gnu: :vector_size (4)]] b14; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +/* { dg-warning {attributes before C23} "" { target *-*-* } .-2 } */ +typedef int [[gnu BAR BAR vector_size (4)]] b15; /* { dg-error {expected '\]' before ':'} } */ +/* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ +/* { dg-warning {attributes before C23} "" { target *-*-* } .-2 } */ +typedef int [[gnu :/**/: vector_size (4)]] b16; /* { dg-error {expected '\]' before ':'} } */ /* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ /* { dg-warning {attributes before C23} "" { target *-*-* } .-2 } */ -typedef int [[gnu : vector_size(4)]] b8; /* { dg-error {expected '\]' before ':'} } */ +typedef int [[gnu JOIN(:,:) vector_size (4)]] b17; /* { dg-error {expected '\]' before ':'} } */ /* { dg-error {'gnu' attribute ignored} "" { target *-*-* } .-1 } */ /* { dg-warning {attributes before C23} "" { target *-*-* } .-2 } */ +typedef int [[gnu :: vector_size (4)]] b18; /* { dg-warning {attributes before C23} } */ +typedef int [[gnu FOO vector_size (4)]] b19; /* { dg-warning {attributes before C23} } */ +typedef int [[gnu :: vector_size (sizeof (void (*)(...)))]] b20; /* { dg-warning {attributes before C23} } */ +/* { dg-warning {requires a named argument before} "" { target *-*-* } .-1 } */ +typedef int [[gnu JOIN2(:,:) vector_size (4)]] b21; /* { dg-warning {attributes before C23} } */ diff --git a/gcc/testsuite/gcc.dg/c23-attr-syntax-8.c b/gcc/testsuite/gcc.dg/c23-attr-syntax-8.c new file mode 100644 index 0000000..6fff160 --- /dev/null +++ b/gcc/testsuite/gcc.dg/c23-attr-syntax-8.c @@ -0,0 +1,12 @@ +/* PR c/114007 */ +/* { dg-do compile } */ +/* { dg-options "-std=c11" } */ + +#if __has_c_attribute (gnu::unused) +[[gnu::unused]] +#endif +int i; +#if __has_cpp_attribute (gnu::unused) +[[gnu::unused]] +#endif +int j; -- cgit v1.1 From d34d7c74d51d365a3a4ddcd4383fc7c9f29020a1 Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Thu, 22 Feb 2024 18:52:32 -0500 Subject: testsuite: fix Wmismatched-new-delete-8.C with -m32 This fixes error: 'operator new' takes type 'size_t' ('unsigned int') as first parameter [-fpermissive] gcc/testsuite/ChangeLog: * g++.dg/warn/Wmismatched-new-delete-8.C: Use __SIZE_TYPE__. --- gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-8.C | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-8.C b/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-8.C index 0ddc056..e8fd7a8 100644 --- a/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-8.C +++ b/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-8.C @@ -11,7 +11,7 @@ static inline T * construct_at(void *at, ARGS && args) struct Placeable : T { Placeable(ARGS && args) : T(args) { } - void * operator new (long unsigned int, void *ptr) { return ptr; } + void * operator new (__SIZE_TYPE__, void *ptr) { return ptr; } void operator delete (void *, void *) { } }; return new (at) Placeable(static_cast(args)); -- cgit v1.1 From 77de8b722db811e0d95af503552cd2acad8deaad Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Fri, 23 Feb 2024 00:16:46 +0000 Subject: Daily bump. --- gcc/ChangeLog | 93 ++++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 6 + gcc/c/ChangeLog | 11 + gcc/m2/ChangeLog | 24 ++ gcc/testsuite/ChangeLog | 1101 +++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 1236 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c770937..cafa866 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,96 @@ +2024-02-22 Jakub Jelinek + + PR c/114007 + * doc/extend.texi: (__extension__): Remove comments about scope + tokens vs. two colons. + +2024-02-22 Andrew Pinski + + PR tree-optimization/109804 + * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle + DEMANGLE_COMPONENT_UNNAMED_TYPE. + +2024-02-22 Richard Biener + + PR tree-optimization/114048 + * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF + can also produce -1 off. + +2024-02-22 Richard Biener + + PR tree-optimization/114027 + * tree-vect-loop.cc (vecctorizable_reduction): Use optimized + condition reduction classification only for single-element + chains. + +2024-02-22 Jakub Jelinek + + PR ipa/111960 + * profile-count.h (profile_count::dump): Remove overload with + char * first argument. + * profile-count.cc (profile_count::dump): Change overload with char * + first argument which uses sprintf into the overfload with FILE * + first argument and use fprintf instead. Remove overload which wrapped + it. + +2024-02-22 Jakub Jelinek + + PR tree-optimization/113993 + * tree-call-cdce.cc (get_no_error_domain): Handle + BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle + BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for + REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384 + the as the F128 suffixed cases, otherwise as non-suffixed ones. + Handle BUILT_IN_{EXP,POW}10L for + REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384 + as (-inf, 4932). + +2024-02-22 Jakub Jelinek + + PR tree-optimization/114038 + * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix + loop exit condition if end is divisible by limb_prec. + +2024-02-22 YunQiang Su + + * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix + problem of mabi=, mno-flush-func, mexplicit-relocs; + add missing leading - of mbranch-cost option. + * config/mips/mips.opt.urls: Regenerate. + +2024-02-22 Kewen Lin + + PR target/109987 + * config/rs6000/constraints.md (we): Update internal doc without + referring to option -mpower9-vector. + * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector + special handlings. + * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS, + OTHER_P8_VECTOR_MASKS): Merge to ... + (OTHER_VSX_VECTOR_MASKS): ... here. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove + some error message handlings and explicit option mask adjustments on + explicit option power{8,9}-vector conflicting with other options. + (rs6000_print_isa_options): Update comments. + (rs6000_disable_incompatible_switches): Remove power{8,9}-vector + related array items and handlings. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector + special handlings. + * config/rs6000/rs6000.opt: Make option power{8,9}-vector as + WarnRemoved. + * doc/extend.texi: Remove documentation referring to option + -mpower8-vector. + * doc/invoke.texi: Remove documentation for option + -mpower{8,9}-vector and adjust some documentation referring to them. + * doc/md.texi: Update documentation for constraint we. + * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok. + +2024-02-22 Pan Li + + PR target/114017 + * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade + the version to 0.12. + 2024-02-21 Edwin Lu * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 768ab7e..bb29f6e 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240222 +20240223 diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 11589f4..6a81681 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,9 @@ +2024-02-22 Jakub Jelinek + + PR c/114007 + * c-lex.cc (c_common_has_attribute): Parse 2 CPP_COLONs with + the first one with COLON_SCOPE flag the same as CPP_SCOPE. + 2024-02-10 Marek Polacek DR 2237 diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 553b7a2..b8c3eb1 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,14 @@ +2024-02-22 Jakub Jelinek + + PR c/114007 + * c-parser.cc (c_parser_std_attribute): Remove loose_scope_p argument. + Instead of checking it, parse 2 CPP_COLONs with the first one with + COLON_SCOPE flag the same as CPP_SCOPE. + (c_parser_std_attribute_list): Remove loose_scope_p argument, don't + pass it to c_parser_std_attribute. + (c_parser_std_attribute_specifier): Adjust c_parser_std_attribute_list + caller. + 2024-02-13 Tobias Burnus PR middle-end/113904 diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog index 10cbe90..6e9c770 100644 --- a/gcc/m2/ChangeLog +++ b/gcc/m2/ChangeLog @@ -1,3 +1,27 @@ +2024-02-22 Gaius Mulley + + PR modula2/114055 + * gm2-compiler/M2Check.mod (Import): IsConstLitInternal and + IsConstLit. + (isInternal): New procedure function. + (doCheck): Test for isInternal in either operand and early + return true. + * gm2-compiler/M2Quads.mod (PushOne): Rewrite with extra + parameter internal. + (BuildPseudoBy): Add TRUE parameter to PushOne call. + (BuildIncProcedure): Add FALSE parameter to PushOne call. + (BuildDecProcedure): Add FALSE parameter to PushOne call. + * gm2-compiler/M2Range.mod (ForLoopBeginTypeCompatible): + Uncomment code and tidy up error string. + * gm2-compiler/SymbolTable.def (PutConstLitInternal): + New procedure. + (IsConstLitInternal): New procedure function. + * gm2-compiler/SymbolTable.mod (PutConstLitInternal): + New procedure. + (IsConstLitInternal): New procedure function. + (SymConstLit): New field IsInternal. + (CreateConstLit): Initialize IsInternal to FALSE. + 2024-02-21 Gaius Mulley PR modula2/114026 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2f1b15f..61abc60 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,1104 @@ +2024-02-22 Marek Polacek + + * g++.dg/warn/Wmismatched-new-delete-8.C: Use __SIZE_TYPE__. + +2024-02-22 Jakub Jelinek + + PR c/114007 + * gcc.dg/c23-attr-syntax-6.c: Adjust testcase for :: being valid + even in -std=c11 even without __extension__ and : : etc. not being + valid anymore even with __extension__. + * gcc.dg/c23-attr-syntax-7.c: Likewise. + * gcc.dg/c23-attr-syntax-8.c: New test. + +2024-02-22 Andrew Pinski + + PR tree-optimization/109804 + * g++.dg/warn/Wmismatched-new-delete-8.C: New test. + +2024-02-22 Tamar Christina + + PR target/112375 + * gcc.target/aarch64/vget_set_lane_1.c: Update test output. + +2024-02-22 Gaius Mulley + + PR modula2/114055 + * gm2/pim/fail/forloopby.mod: New test. + * gm2/pim/pass/forloopby2.mod: New test. + +2024-02-22 Richard Biener + + PR tree-optimization/114048 + * gcc.dg/torture/pr114048.c: New testcase. + +2024-02-22 Richard Biener + + PR tree-optimization/114027 + * gcc.dg/vect/pr114027.c: New testcase. + +2024-02-22 Jakub Jelinek + + PR tree-optimization/113993 + * gcc.dg/tree-ssa/pr113993.c: New test. + +2024-02-22 Jakub Jelinek + + PR tree-optimization/114038 + * gcc.dg/torture/bitint-59.c: New test. + +2024-02-22 Kewen Lin + + PR target/109987 + * lib/target-supports.exp + (check_effective_target_powerpc_p8vector_ok): Remove. + (check_effective_target_powerpc_p9vector_ok): Remove. + (check_p8vector_hw_available): Replace -mpower8-vector with + -mcpu=power8. + (check_p9vector_hw_available): Replace -mpower9-vector with + -mcpu=power9. + (check_ppc_float128_hw_available): Likewise. + (check_vect_support_and_set_flags): Replace -mpower8-vector with + -mcpu=power8, replace -mpower9-vector with -mcpu=power9 or + nothing if check_power10_hw_available and place -mcpu=970 first + if needed to avoid possible overriding. + * g++.target/powerpc/altivec-19.C: Replace powerpc_p9vector_ok with + powerpc_vsx_ok and append -mvsx to dg-options. + * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-0.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-1.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-eq-2.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-0.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-1.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-gt-2.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-0.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-1.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-lt-2.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-0.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-1.c: Likewise. + * gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-2.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-exp-1.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-exp-3.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-exp-4.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-exp-5.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-sig-1.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-sig-2.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-sig-3.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-sig-4.c: Likewise. + * gcc.target/powerpc/bfp/scalar-extract-sig-5.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-10.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-11.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-6.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-7.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-8.c: Likewise. + * gcc.target/powerpc/bfp/scalar-insert-exp-9.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-0.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-1.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-10.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-11.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-2.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-3.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-4.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-5.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-6.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-7.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-8.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-data-class-9.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-neg-0.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-neg-1.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-neg-2.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-neg-3.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-neg-4.c: Likewise. + * gcc.target/powerpc/bfp/scalar-test-neg-5.c: Likewise. + * gcc.target/powerpc/bfp/vec-extract-exp-0.c: Likewise. + * gcc.target/powerpc/bfp/vec-extract-exp-1.c: Likewise. + * gcc.target/powerpc/bfp/vec-extract-exp-2.c: Likewise. + * gcc.target/powerpc/bfp/vec-extract-exp-3.c: Likewise. + * gcc.target/powerpc/bfp/vec-extract-sig-0.c: Likewise. + * gcc.target/powerpc/bfp/vec-extract-sig-1.c: Likewise. + * gcc.target/powerpc/bfp/vec-extract-sig-2.c: Likewise. + * gcc.target/powerpc/bfp/vec-extract-sig-3.c: Likewise. + * gcc.target/powerpc/bfp/vec-insert-exp-0.c: Likewise. + * gcc.target/powerpc/bfp/vec-insert-exp-1.c: Likewise. + * gcc.target/powerpc/bfp/vec-insert-exp-2.c: Likewise. + * gcc.target/powerpc/bfp/vec-insert-exp-3.c: Likewise. + * gcc.target/powerpc/bfp/vec-insert-exp-4.c: Likewise. + * gcc.target/powerpc/bfp/vec-insert-exp-5.c: Likewise. + * gcc.target/powerpc/bfp/vec-insert-exp-6.c: Likewise. + * gcc.target/powerpc/bfp/vec-insert-exp-7.c: Likewise. + * gcc.target/powerpc/bfp/vec-test-data-class-0.c: Likewise. + * gcc.target/powerpc/bfp/vec-test-data-class-1.c: Likewise. + * gcc.target/powerpc/bfp/vec-test-data-class-2.c: Likewise. + * gcc.target/powerpc/bfp/vec-test-data-class-3.c: Likewise. + * gcc.target/powerpc/bfp/vec-test-data-class-4.c: Likewise. + * gcc.target/powerpc/bfp/vec-test-data-class-5.c: Likewise. + * gcc.target/powerpc/bfp/vec-test-data-class-6.c: Likewise. + * gcc.target/powerpc/bfp/vec-test-data-class-7.c: Likewise. + * gcc.target/powerpc/builtins-3-p9.c: Likewise. + * gcc.target/powerpc/byte-in-either-range-0.c: Likewise. + * gcc.target/powerpc/byte-in-either-range-1.c: Likewise. + * gcc.target/powerpc/byte-in-range-0.c: Likewise. + * gcc.target/powerpc/byte-in-range-1.c: Likewise. + * gcc.target/powerpc/byte-in-set-0.c: Likewise. + * gcc.target/powerpc/byte-in-set-1.c: Likewise. + * gcc.target/powerpc/byte-in-set-2.c: Likewise. + * gcc.target/powerpc/clone1.c: Likewise. + * gcc.target/powerpc/ctz-3.c: Likewise. + * gcc.target/powerpc/ctz-4.c: Likewise. + * gcc.target/powerpc/darn-0.c: Likewise. + * gcc.target/powerpc/darn-1.c: Likewise. + * gcc.target/powerpc/darn-2.c: Likewise. + * gcc.target/powerpc/dform-3.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-0.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-1.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-10.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-11.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-12.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-13.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-14.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-15.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-16.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-17.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-18.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-19.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-2.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-20.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-21.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-22.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-23.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-24.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-25.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-26.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-27.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-28.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-29.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-3.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-30.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-31.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-32.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-33.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-34.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-35.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-36.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-37.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-38.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-39.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-4.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-40.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-41.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-42.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-43.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-44.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-45.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-46.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-47.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-48.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-49.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-5.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-50.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-51.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-52.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-53.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-54.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-55.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-56.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-57.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-58.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-59.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-6.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-60.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-61.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-62.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-63.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-64.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-65.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-66.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-67.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-68.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-69.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-7.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-70.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-71.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-72.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-73.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-74.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-75.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-76.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-77.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-78.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-79.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-8.c: Likewise. + * gcc.target/powerpc/dfp/dtstsfi-9.c: Likewise. + * gcc.target/powerpc/direct-move-vector.c: Likewise. + * gcc.target/powerpc/float128-type-2.c: Likewise. + * gcc.target/powerpc/fold-vec-abs-int-fwrapv.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-abs-int.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-abs-longlong.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-cmp-char.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-cmp-short.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-char.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-float.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-int.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-longlong.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-short.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-float-p9.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-int-p9.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-short-p9.c: Likewise. + * gcc.target/powerpc/fold-vec-mult-int128-p9.c: Likewise. + * gcc.target/powerpc/fold-vec-neg-int.p9.c: Likewise. + * gcc.target/powerpc/fold-vec-neg-longlong.p9.c: Likewise. + * gcc.target/powerpc/p9-dimode1.c: Likewise. + * gcc.target/powerpc/p9-dimode2.c: Likewise. + * gcc.target/powerpc/p9-extract-1.c: Likewise. + * gcc.target/powerpc/p9-extract-2.c: Likewise. + * gcc.target/powerpc/p9-extract-3.c: Likewise. + * gcc.target/powerpc/p9-extract-4.c: Likewise. + * gcc.target/powerpc/p9-fpcvt-1.c: Likewise. + * gcc.target/powerpc/p9-fpcvt-2.c: Likewise. + * gcc.target/powerpc/p9-fpcvt-3.c: Likewise. + * gcc.target/powerpc/p9-lxvx-stxvx-1.c: Likewise. + * gcc.target/powerpc/p9-lxvx-stxvx-2.c: Likewise. + * gcc.target/powerpc/p9-lxvx-stxvx-3.c: Likewise. + * gcc.target/powerpc/p9-minmax-1.c: Likewise. + * gcc.target/powerpc/p9-minmax-2.c: Likewise. + * gcc.target/powerpc/p9-minmax-3.c: Likewise. + * gcc.target/powerpc/p9-novsx.c: Likewise. + * gcc.target/powerpc/p9-permute.c: Likewise. + * gcc.target/powerpc/p9-sign_extend-runnable.c: Likewise. + * gcc.target/powerpc/p9-splat-1.c: Likewise. + * gcc.target/powerpc/p9-splat-2.c: Likewise. + * gcc.target/powerpc/p9-splat-3.c: Likewise. + * gcc.target/powerpc/p9-splat-4.c: Likewise. + * gcc.target/powerpc/p9-splat-5.c: Likewise. + * gcc.target/powerpc/p9-vbpermd.c: Likewise. + * gcc.target/powerpc/p9-vec-length-epil-1.c: Likewise. + * gcc.target/powerpc/p9-vec-length-epil-2.c: Likewise. + * gcc.target/powerpc/p9-vec-length-epil-3.c: Likewise. + * gcc.target/powerpc/p9-vec-length-epil-4.c: Likewise. + * gcc.target/powerpc/p9-vec-length-epil-5.c: Likewise. + * gcc.target/powerpc/p9-vec-length-epil-6.c: Likewise. + * gcc.target/powerpc/p9-vec-length-epil-7.c: Likewise. + * gcc.target/powerpc/p9-vec-length-epil-8.c: Likewise. + * gcc.target/powerpc/p9-vec-length-full-1.c: Likewise. + * gcc.target/powerpc/p9-vec-length-full-2.c: Likewise. + * gcc.target/powerpc/p9-vec-length-full-3.c: Likewise. + * gcc.target/powerpc/p9-vec-length-full-4.c: Likewise. + * gcc.target/powerpc/p9-vec-length-full-5.c: Likewise. + * gcc.target/powerpc/p9-vec-length-full-6.c: Likewise. + * gcc.target/powerpc/p9-vec-length-full-7.c: Likewise. + * gcc.target/powerpc/p9-vec-length-full-8.c: Likewise. + * gcc.target/powerpc/p9-vneg.c: Likewise. + * gcc.target/powerpc/p9-vparity.c: Likewise. + * gcc.target/powerpc/p9-vpermr.c: Likewise. + * gcc.target/powerpc/p9-xxbr-1.c: Likewise. + * gcc.target/powerpc/p9-xxbr-2.c: Likewise. + * gcc.target/powerpc/p9-xxbr-3.c: Likewise. + * gcc.target/powerpc/ppc-fortran/pr80108-1.f90: Likewise. + * gcc.target/powerpc/ppc-round3.c: Likewise. + * gcc.target/powerpc/pr103124.c: Likewise. + * gcc.target/powerpc/pr104015-1.c: Likewise. + * gcc.target/powerpc/pr106769-p9.c: Likewise. + * gcc.target/powerpc/pr107412.c: Likewise. + * gcc.target/powerpc/pr110429.c: Likewise. + * gcc.target/powerpc/pr66144-1.c: Likewise. + * gcc.target/powerpc/pr71186.c: Likewise. + * gcc.target/powerpc/pr71309.c: Likewise. + * gcc.target/powerpc/pr71670.c: Likewise. + * gcc.target/powerpc/pr71698.c: Likewise. + * gcc.target/powerpc/pr71720.c: Likewise. + * gcc.target/powerpc/pr72853.c: Likewise. + * gcc.target/powerpc/pr78056-1.c: Likewise. + * gcc.target/powerpc/pr78658.c: Likewise. + * gcc.target/powerpc/pr78953.c: Likewise. + * gcc.target/powerpc/pr79004.c: Likewise. + * gcc.target/powerpc/pr79038-1.c: Likewise. + * gcc.target/powerpc/pr79179.c: Likewise. + * gcc.target/powerpc/pr79251.p9.c: Likewise. + * gcc.target/powerpc/pr79799-1.c: Likewise. + * gcc.target/powerpc/pr79799-2.c: Likewise. + * gcc.target/powerpc/pr79799-3.c: Likewise. + * gcc.target/powerpc/pr79799-5.c: Likewise. + * gcc.target/powerpc/pr80695-p9.c: Likewise. + * gcc.target/powerpc/pr81348.c: Likewise. + * gcc.target/powerpc/pr81622.c: Likewise. + * gcc.target/powerpc/pr84154-3.c: Likewise. + * gcc.target/powerpc/pr90763.c: Likewise. + * gcc.target/powerpc/pr96933-1.c: Likewise. + * gcc.target/powerpc/sad-vectorize-1.c: Likewise. + * gcc.target/powerpc/sad-vectorize-2.c: Likewise. + * gcc.target/powerpc/signbit-2.c: Likewise. + * gcc.target/powerpc/vadsdu-0.c: Likewise. + * gcc.target/powerpc/vadsdu-1.c: Likewise. + * gcc.target/powerpc/vadsdu-2.c: Likewise. + * gcc.target/powerpc/vadsdu-3.c: Likewise. + * gcc.target/powerpc/vadsdu-4.c: Likewise. + * gcc.target/powerpc/vadsdu-5.c: Likewise. + * gcc.target/powerpc/vadsdub-1.c: Likewise. + * gcc.target/powerpc/vadsdub-2.c: Likewise. + * gcc.target/powerpc/vadsduh-1.c: Likewise. + * gcc.target/powerpc/vadsduh-2.c: Likewise. + * gcc.target/powerpc/vadsduw-1.c: Likewise. + * gcc.target/powerpc/vadsduw-2.c: Likewise. + * gcc.target/powerpc/vec-extract-4.c: Likewise. + * gcc.target/powerpc/vec-init-3.c: Likewise. + * gcc.target/powerpc/vec-minmax-1.c: Likewise. + * gcc.target/powerpc/vec-minmax-2.c: Likewise. + * gcc.target/powerpc/vec-set-char.c: Likewise. + * gcc.target/powerpc/vec-set-int.c: Likewise. + * gcc.target/powerpc/vec-set-short.c: Likewise. + * gcc.target/powerpc/vec_reve_2.c: Likewise. + * gcc.target/powerpc/vector_float.c: Likewise. + * gcc.target/powerpc/vslv-0.c: Likewise. + * gcc.target/powerpc/vslv-1.c: Likewise. + * gcc.target/powerpc/vsrv-0.c: Likewise. + * gcc.target/powerpc/vsrv-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-0.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-10.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-11.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-12.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-13.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-14.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-5.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-6.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-7.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-8.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-ne-9.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-nez-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-nez-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-nez-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-nez-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-nez-5.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-nez-6.c: Likewise. + * gcc.target/powerpc/vsu/vec-all-nez-7.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-0.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-10.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-11.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-12.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-13.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-14.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-5.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-6.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-7.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-8.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eq-9.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eqz-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eqz-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eqz-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eqz-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eqz-5.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eqz-6.c: Likewise. + * gcc.target/powerpc/vsu/vec-any-eqz-7.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpne-0.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpne-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpne-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpne-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpne-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpne-5.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpne-6.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpne-8.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpne-9.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpnez-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpnez-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpnez-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpnez-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpnez-5.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpnez-6.c: Likewise. + * gcc.target/powerpc/vsu/vec-cmpnez-7.c: Likewise. + * gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: Likewise. + * gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-cntlz-lsbb-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: Likewise. + * gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-cnttz-lsbb-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-0.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-10.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-11.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-12.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-13.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-5.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-6.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-7.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-8.c: Likewise. + * gcc.target/powerpc/vsu/vec-xl-len-9.c: Likewise. + * gcc.target/powerpc/vsu/vec-xlx-0.c: Likewise. + * gcc.target/powerpc/vsu/vec-xlx-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-xlx-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-xlx-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-xlx-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-xlx-5.c: Likewise. + * gcc.target/powerpc/vsu/vec-xlx-6.c: Likewise. + * gcc.target/powerpc/vsu/vec-xlx-7.c: Likewise. + * gcc.target/powerpc/vsu/vec-xrx-0.c: Likewise. + * gcc.target/powerpc/vsu/vec-xrx-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-xrx-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-xrx-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-xrx-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-xrx-5.c: Likewise. + * gcc.target/powerpc/vsu/vec-xrx-6.c: Likewise. + * gcc.target/powerpc/vsu/vec-xrx-7.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-0.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-1.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-10.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-11.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-12.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-13.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-2.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-3.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-4.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-5.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-6.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-7.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-8.c: Likewise. + * gcc.target/powerpc/vsu/vec-xst-len-9.c: Likewise. + * gcc.target/powerpc/vsx-builtin-msum.c: Likewise. + * gcc.target/powerpc/vsx-himode.c: Likewise. + * gcc.target/powerpc/vsx-himode2.c: Likewise. + * gcc.target/powerpc/vsx-himode3.c: Likewise. + * gcc.target/powerpc/vsx-qimode.c: Likewise. + * gcc.target/powerpc/vsx-qimode2.c: Likewise. + * gcc.target/powerpc/vsx-qimode3.c: Likewise. + * g++.target/powerpc/pr65240-1.C: Replace powerpc_p8vector_ok with + powerpc_vsx_ok and append -mvsx to dg-options. + * g++.target/powerpc/pr65240-2.C: Likewise. + * g++.target/powerpc/pr65240-3.C: Likewise. + * g++.target/powerpc/pr65242.C: Likewise. + * g++.target/powerpc/pr67211.C: Likewise. + * g++.target/powerpc/pr71294.C: Likewise. + * g++.target/powerpc/pr84279.C: Likewise. + * g++.target/powerpc/pr93974.C: Likewise. + * gcc.target/powerpc/atomic-p8.c: Likewise. + * gcc.target/powerpc/atomic_load_store-p8.c: Likewise. + * gcc.target/powerpc/bcd-2.c: Likewise. + * gcc.target/powerpc/bcd-3.c: Likewise. + * gcc.target/powerpc/bool2-p8.c: Likewise. + * gcc.target/powerpc/bool3-p8.c: Likewise. + * gcc.target/powerpc/builtins-1.c: Likewise. + * gcc.target/powerpc/builtins-3-p8.c: Likewise. + * gcc.target/powerpc/builtins-5.c: Likewise. + * gcc.target/powerpc/builtins-9.c: Likewise. + * gcc.target/powerpc/crypto-builtin-1.c: Likewise. + * gcc.target/powerpc/crypto-builtin-2.c: Likewise. + * gcc.target/powerpc/direct-move-double1.c: Likewise. + * gcc.target/powerpc/direct-move-float1.c: Likewise. + * gcc.target/powerpc/direct-move-long1.c: Likewise. + * gcc.target/powerpc/direct-move-vint1.c: Likewise. + * gcc.target/powerpc/float128-type-1.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-char.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-double.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-longlong.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-char-p8.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-float-p8.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-int-p8.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-insert-short-p8.c: Likewise. + * gcc.target/powerpc/fold-vec-neg-char.c: Likewise. + * gcc.target/powerpc/fold-vec-neg-floatdouble.c: Likewise. + * gcc.target/powerpc/fold-vec-neg-int.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-neg-short.c: Likewise. + * gcc.target/powerpc/fold-vec-select-double.c: Likewise. + * gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c: Likewise. + * gcc.target/powerpc/fusion.c: Likewise. + * gcc.target/powerpc/fusion2.c: Likewise. + * gcc.target/powerpc/mul-vectorize-1.c: Likewise. + * gcc.target/powerpc/p8-vec-xl-xst-v2.c: Likewise. + * gcc.target/powerpc/p8-vec-xl-xst.c: Likewise. + * gcc.target/powerpc/p8vector-builtin-1.c: Likewise. + * gcc.target/powerpc/p8vector-builtin-2.c: Likewise. + * gcc.target/powerpc/p8vector-builtin-3.c: Likewise. + * gcc.target/powerpc/p8vector-builtin-4.c: Likewise. + * gcc.target/powerpc/p8vector-builtin-5.c: Likewise. + * gcc.target/powerpc/p8vector-builtin-6.c: Likewise. + * gcc.target/powerpc/p8vector-builtin-7.c: Likewise. + * gcc.target/powerpc/p8vector-fp.c: Likewise. + * gcc.target/powerpc/p8vector-int128-1.c: Likewise. + * gcc.target/powerpc/p8vector-ldst.c: Likewise. + * gcc.target/powerpc/p8vector-vbpermq.c: Likewise. + * gcc.target/powerpc/p8vector-vectorize-1.c: Likewise. + * gcc.target/powerpc/p8vector-vectorize-2.c: Likewise. + * gcc.target/powerpc/p8vector-vectorize-3.c: Likewise. + * gcc.target/powerpc/p8vector-vectorize-4.c: Likewise. + * gcc.target/powerpc/p8vector-vectorize-5.c: Likewise. + * gcc.target/powerpc/ppc-round2.c: Likewise. + * gcc.target/powerpc/pr100866-1.c: Likewise. + * gcc.target/powerpc/pr100866-2.c: Likewise. + * gcc.target/powerpc/pr104239-1.c: Likewise. + * gcc.target/powerpc/pr104239-2.c: Likewise. + * gcc.target/powerpc/pr104239-3.c: Likewise. + * gcc.target/powerpc/pr106769-p8.c: Likewise. + * gcc.target/powerpc/pr108396.c: Likewise. + * gcc.target/powerpc/pr111449-1.c: Likewise. + * gcc.target/powerpc/pr57744.c: Likewise. + * gcc.target/powerpc/pr58673-1.c: Likewise. + * gcc.target/powerpc/pr58673-2.c: Likewise. + * gcc.target/powerpc/pr60137.c: Likewise. + * gcc.target/powerpc/pr60203.c: Likewise. + * gcc.target/powerpc/pr66144-2.c: Likewise. + * gcc.target/powerpc/pr66144-3.c: Likewise. + * gcc.target/powerpc/pr68163.c: Likewise. + * gcc.target/powerpc/pr69548.c: Likewise. + * gcc.target/powerpc/pr70669.c: Likewise. + * gcc.target/powerpc/pr71977-1.c: Likewise. + * gcc.target/powerpc/pr71977-2.c: Likewise. + * gcc.target/powerpc/pr72717.c: Likewise. + * gcc.target/powerpc/pr78056-3.c: Likewise. + * gcc.target/powerpc/pr78056-4.c: Likewise. + * gcc.target/powerpc/pr78102.c: Likewise. + * gcc.target/powerpc/pr78543.c: Likewise. + * gcc.target/powerpc/pr78604.c: Likewise. + * gcc.target/powerpc/pr79251.p8.c: Likewise. + * gcc.target/powerpc/pr79354.c: Likewise. + * gcc.target/powerpc/pr79544.c: Likewise. + * gcc.target/powerpc/pr79907.c: Likewise. + * gcc.target/powerpc/pr79951.c: Likewise. + * gcc.target/powerpc/pr80315-1.c: Likewise. + * gcc.target/powerpc/pr80315-2.c: Likewise. + * gcc.target/powerpc/pr80315-3.c: Likewise. + * gcc.target/powerpc/pr80315-4.c: Likewise. + * gcc.target/powerpc/pr80510-2.c: Likewise. + * gcc.target/powerpc/pr80695-p8.c: Likewise. + * gcc.target/powerpc/pr80718.c: Likewise. + * gcc.target/powerpc/pr84154-2.c: Likewise. + * gcc.target/powerpc/pr88558-p8.c: Likewise. + * gcc.target/powerpc/pr88845.c: Likewise. + * gcc.target/powerpc/pr91903.c: Likewise. + * gcc.target/powerpc/pr92923-2.c: Likewise. + * gcc.target/powerpc/pr96933-2.c: Likewise. + * gcc.target/powerpc/pr97019.c: Likewise. + * gcc.target/powerpc/pragma_power8.c: Likewise. + * gcc.target/powerpc/signbit-1.c: Likewise. + * gcc.target/powerpc/swaps-p8-1.c: Likewise. + * gcc.target/powerpc/swaps-p8-12.c: Likewise. + * gcc.target/powerpc/swaps-p8-14.c: Likewise. + * gcc.target/powerpc/swaps-p8-15.c: Likewise. + * gcc.target/powerpc/swaps-p8-16.c: Likewise. + * gcc.target/powerpc/swaps-p8-17.c: Likewise. + * gcc.target/powerpc/swaps-p8-18.c: Likewise. + * gcc.target/powerpc/swaps-p8-19.c: Likewise. + * gcc.target/powerpc/swaps-p8-2.c: Likewise. + * gcc.target/powerpc/swaps-p8-22.c: Likewise. + * gcc.target/powerpc/swaps-p8-23.c: Likewise. + * gcc.target/powerpc/swaps-p8-24.c: Likewise. + * gcc.target/powerpc/swaps-p8-25.c: Likewise. + * gcc.target/powerpc/swaps-p8-26.c: Likewise. + * gcc.target/powerpc/swaps-p8-27.c: Likewise. + * gcc.target/powerpc/swaps-p8-3.c: Likewise. + * gcc.target/powerpc/swaps-p8-30.c: Likewise. + * gcc.target/powerpc/swaps-p8-33.c: Likewise. + * gcc.target/powerpc/swaps-p8-36.c: Likewise. + * gcc.target/powerpc/swaps-p8-39.c: Likewise. + * gcc.target/powerpc/swaps-p8-4.c: Likewise. + * gcc.target/powerpc/swaps-p8-42.c: Likewise. + * gcc.target/powerpc/swaps-p8-45.c: Likewise. + * gcc.target/powerpc/swaps-p8-46.c: Likewise. + * gcc.target/powerpc/swaps-p8-5.c: Likewise. + * gcc.target/powerpc/unpack-vectorize-3.c: Likewise. + * gcc.target/powerpc/upper-regs-sf.c: Likewise. + * gcc.target/powerpc/vec-cmp.c: Likewise. + * gcc.target/powerpc/vec-extract-1.c: Likewise. + * gcc.target/powerpc/vec-extract-3.c: Likewise. + * gcc.target/powerpc/vec-extract-5.c: Likewise. + * gcc.target/powerpc/vec-extract-6.c: Likewise. + * gcc.target/powerpc/vec-extract-7.c: Likewise. + * gcc.target/powerpc/vec-extract-8.c: Likewise. + * gcc.target/powerpc/vec-extract-9.c: Likewise. + * gcc.target/powerpc/vec-init-10.c: Likewise. + * gcc.target/powerpc/vec-init-6.c: Likewise. + * gcc.target/powerpc/vec-init-7.c: Likewise. + * gcc.target/powerpc/vsx-extract-3.c: Likewise. + * gcc.target/powerpc/vsx-extract-4.c: Likewise. + * gcc.target/powerpc/vsx-extract-5.c: Likewise. + * gcc.target/powerpc/vsx-simode.c: Likewise. + * gcc.target/powerpc/vsx-simode2.c: Likewise. + * gcc.target/powerpc/vsx-simode3.c: Likewise. + * gcc.target/powerpc/builtins-4-int128-runnable.c: Replace + powerpc_p8vector_ok with powerpc_vsx_ok, replace -mpower8-vector + with -mvsx, and add dg-additional-options -mdejagnu-cpu=power8 + if !has_arch_pwr8. + * gcc.target/powerpc/builtins-mergew-mergow.c: Likewise. + * gcc.target/powerpc/direct-move-float3.c: Likewise. + * gcc.target/powerpc/divkc3-2.c: Likewise. + * gcc.target/powerpc/divkc3-3.c: Likewise. + * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.c: Likewise. + * gcc.target/powerpc/fold-vec-abs-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-add-4.c: Likewise. + * gcc.target/powerpc/fold-vec-add-7.c: Likewise. + * gcc.target/powerpc/fold-vec-cmp-int.h: Likewise. + * gcc.target/powerpc/fold-vec-cmp-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-cmp-short.h: Likewise. + * gcc.target/powerpc/fold-vec-cntlz-char.c: Likewise. + * gcc.target/powerpc/fold-vec-cntlz-int.c: Likewise. + * gcc.target/powerpc/fold-vec-cntlz-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-cntlz-short.c: Likewise. + * gcc.target/powerpc/fold-vec-ld-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-eqv-char.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-eqv-float.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-eqv-int.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-eqv-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-eqv-short.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-ors-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-other-char.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-other-int.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-other-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-logical-other-short.c: Likewise. + * gcc.target/powerpc/fold-vec-mergehl-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-minmax-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-mult-int.c: Likewise. + * gcc.target/powerpc/fold-vec-mult-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-neg-int.c: Likewise. + * gcc.target/powerpc/fold-vec-neg-longlong.h: Likewise. + * gcc.target/powerpc/fold-vec-pack-double.c: Likewise. + * gcc.target/powerpc/fold-vec-pack-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c: Likewise. + * gcc.target/powerpc/fold-vec-shift-left-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-shift-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-st-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-sub-int128.c: Likewise. + * gcc.target/powerpc/fold-vec-sub-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-unpack-float.c: Likewise. + * gcc.target/powerpc/fold-vec-unpack-int.c: Likewise. + * gcc.target/powerpc/mmx-packs.c: Likewise. + * gcc.target/powerpc/mmx-packssdw-1.c: Likewise. + * gcc.target/powerpc/mmx-packsswb-1.c: Likewise. + * gcc.target/powerpc/mmx-packuswb-1.c: Likewise. + * gcc.target/powerpc/mmx-paddb-1.c: Likewise. + * gcc.target/powerpc/mmx-paddd-1.c: Likewise. + * gcc.target/powerpc/mmx-paddsb-1.c: Likewise. + * gcc.target/powerpc/mmx-paddsw-1.c: Likewise. + * gcc.target/powerpc/mmx-paddusb-1.c: Likewise. + * gcc.target/powerpc/mmx-paddusw-1.c: Likewise. + * gcc.target/powerpc/mmx-paddw-1.c: Likewise. + * gcc.target/powerpc/mmx-pcmpeqb-1.c: Likewise. + * gcc.target/powerpc/mmx-pcmpeqd-1.c: Likewise. + * gcc.target/powerpc/mmx-pcmpeqw-1.c: Likewise. + * gcc.target/powerpc/mmx-pcmpgtb-1.c: Likewise. + * gcc.target/powerpc/mmx-pcmpgtd-1.c: Likewise. + * gcc.target/powerpc/mmx-pcmpgtw-1.c: Likewise. + * gcc.target/powerpc/mmx-pmaddwd-1.c: Likewise. + * gcc.target/powerpc/mmx-pmulhw-1.c: Likewise. + * gcc.target/powerpc/mmx-pmullw-1.c: Likewise. + * gcc.target/powerpc/mmx-pslld-1.c: Likewise. + * gcc.target/powerpc/mmx-psllw-1.c: Likewise. + * gcc.target/powerpc/mmx-psrad-1.c: Likewise. + * gcc.target/powerpc/mmx-psraw-1.c: Likewise. + * gcc.target/powerpc/mmx-psrld-1.c: Likewise. + * gcc.target/powerpc/mmx-psrlw-1.c: Likewise. + * gcc.target/powerpc/mmx-psubb-2.c: Likewise. + * gcc.target/powerpc/mmx-psubd-2.c: Likewise. + * gcc.target/powerpc/mmx-psubsb-1.c: Likewise. + * gcc.target/powerpc/mmx-psubsw-1.c: Likewise. + * gcc.target/powerpc/mmx-psubusb-1.c: Likewise. + * gcc.target/powerpc/mmx-psubusw-1.c: Likewise. + * gcc.target/powerpc/mmx-psubw-2.c: Likewise. + * gcc.target/powerpc/mmx-punpckhbw-1.c: Likewise. + * gcc.target/powerpc/mmx-punpckhdq-1.c: Likewise. + * gcc.target/powerpc/mmx-punpckhwd-1.c: Likewise. + * gcc.target/powerpc/mmx-punpcklbw-1.c: Likewise. + * gcc.target/powerpc/mmx-punpckldq-1.c: Likewise. + * gcc.target/powerpc/mmx-punpcklwd-1.c: Likewise. + * gcc.target/powerpc/mulkc3-2.c: Likewise. + * gcc.target/powerpc/mulkc3-3.c: Likewise. + * gcc.target/powerpc/p8vector-builtin-8.c: Likewise. + * gcc.target/powerpc/pr37191.c: Likewise. + * gcc.target/powerpc/pr83862.c: Likewise. + * gcc.target/powerpc/pr84154-1.c: Likewise. + * gcc.target/powerpc/pr84220-sld2.c: Likewise. + * gcc.target/powerpc/pr85456.c: Likewise. + * gcc.target/powerpc/pr86731-longlong.c: Likewise. + * gcc.target/powerpc/sse-addps-1.c: Likewise. + * gcc.target/powerpc/sse-addss-1.c: Likewise. + * gcc.target/powerpc/sse-andnps-1.c: Likewise. + * gcc.target/powerpc/sse-andps-1.c: Likewise. + * gcc.target/powerpc/sse-cmpss-1.c: Likewise. + * gcc.target/powerpc/sse-cvtpi16ps-1.c: Likewise. + * gcc.target/powerpc/sse-cvtpi32ps-1.c: Likewise. + * gcc.target/powerpc/sse-cvtpi32x2ps-1.c: Likewise. + * gcc.target/powerpc/sse-cvtpi8ps-1.c: Likewise. + * gcc.target/powerpc/sse-cvtpspi16-1.c: Likewise. + * gcc.target/powerpc/sse-cvtpspi8-1.c: Likewise. + * gcc.target/powerpc/sse-cvtpu16ps-1.c: Likewise. + * gcc.target/powerpc/sse-cvtpu8ps-1.c: Likewise. + * gcc.target/powerpc/sse-cvtsi2ss-1.c: Likewise. + * gcc.target/powerpc/sse-cvtsi2ss-2.c: Likewise. + * gcc.target/powerpc/sse-cvtss2si-1.c: Likewise. + * gcc.target/powerpc/sse-cvtss2si-2.c: Likewise. + * gcc.target/powerpc/sse-cvttss2si-1.c: Likewise. + * gcc.target/powerpc/sse-cvttss2si-2.c: Likewise. + * gcc.target/powerpc/sse-divps-1.c: Likewise. + * gcc.target/powerpc/sse-divss-1.c: Likewise. + * gcc.target/powerpc/sse-maxps-1.c: Likewise. + * gcc.target/powerpc/sse-maxps-2.c: Likewise. + * gcc.target/powerpc/sse-maxss-1.c: Likewise. + * gcc.target/powerpc/sse-minps-1.c: Likewise. + * gcc.target/powerpc/sse-minps-2.c: Likewise. + * gcc.target/powerpc/sse-minss-1.c: Likewise. + * gcc.target/powerpc/sse-movaps-1.c: Likewise. + * gcc.target/powerpc/sse-movaps-2.c: Likewise. + * gcc.target/powerpc/sse-movhlps-1.c: Likewise. + * gcc.target/powerpc/sse-movhps-1.c: Likewise. + * gcc.target/powerpc/sse-movhps-2.c: Likewise. + * gcc.target/powerpc/sse-movlhps-1.c: Likewise. + * gcc.target/powerpc/sse-movlps-1.c: Likewise. + * gcc.target/powerpc/sse-movlps-2.c: Likewise. + * gcc.target/powerpc/sse-movmskb-1.c: Likewise. + * gcc.target/powerpc/sse-movmskps-1.c: Likewise. + * gcc.target/powerpc/sse-movss-1.c: Likewise. + * gcc.target/powerpc/sse-movss-2.c: Likewise. + * gcc.target/powerpc/sse-movss-3.c: Likewise. + * gcc.target/powerpc/sse-mulps-1.c: Likewise. + * gcc.target/powerpc/sse-mulss-1.c: Likewise. + * gcc.target/powerpc/sse-orps-1.c: Likewise. + * gcc.target/powerpc/sse-pavgw-1.c: Likewise. + * gcc.target/powerpc/sse-pmaxsw-1.c: Likewise. + * gcc.target/powerpc/sse-pmaxub-1.c: Likewise. + * gcc.target/powerpc/sse-pminsw-1.c: Likewise. + * gcc.target/powerpc/sse-pminub-1.c: Likewise. + * gcc.target/powerpc/sse-pmulhuw-1.c: Likewise. + * gcc.target/powerpc/sse-psadbw-1.c: Likewise. + * gcc.target/powerpc/sse-rcpps-1.c: Likewise. + * gcc.target/powerpc/sse-rsqrtps-1.c: Likewise. + * gcc.target/powerpc/sse-shufps-1.c: Likewise. + * gcc.target/powerpc/sse-sqrtps-1.c: Likewise. + * gcc.target/powerpc/sse-subps-1.c: Likewise. + * gcc.target/powerpc/sse-subss-1.c: Likewise. + * gcc.target/powerpc/sse-ucomiss-1.c: Likewise. + * gcc.target/powerpc/sse-ucomiss-2.c: Likewise. + * gcc.target/powerpc/sse-ucomiss-3.c: Likewise. + * gcc.target/powerpc/sse-ucomiss-4.c: Likewise. + * gcc.target/powerpc/sse-ucomiss-5.c: Likewise. + * gcc.target/powerpc/sse-ucomiss-6.c: Likewise. + * gcc.target/powerpc/sse-unpckhps-1.c: Likewise. + * gcc.target/powerpc/sse-unpcklps-1.c: Likewise. + * gcc.target/powerpc/sse-xorps-1.c: Likewise. + * gcc.target/powerpc/sse2-addpd-1.c: Likewise. + * gcc.target/powerpc/sse2-addsd-1.c: Likewise. + * gcc.target/powerpc/sse2-andnpd-1.c: Likewise. + * gcc.target/powerpc/sse2-andpd-1.c: Likewise. + * gcc.target/powerpc/sse2-cmppd-1.c: Likewise. + * gcc.target/powerpc/sse2-cmpsd-1.c: Likewise. + * gcc.target/powerpc/sse2-comisd-1.c: Likewise. + * gcc.target/powerpc/sse2-comisd-2.c: Likewise. + * gcc.target/powerpc/sse2-comisd-3.c: Likewise. + * gcc.target/powerpc/sse2-comisd-4.c: Likewise. + * gcc.target/powerpc/sse2-comisd-5.c: Likewise. + * gcc.target/powerpc/sse2-comisd-6.c: Likewise. + * gcc.target/powerpc/sse2-cvtdq2pd-1.c: Likewise. + * gcc.target/powerpc/sse2-cvtdq2ps-1.c: Likewise. + * gcc.target/powerpc/sse2-cvtpd2dq-1.c: Likewise. + * gcc.target/powerpc/sse2-cvtpd2ps-1.c: Likewise. + * gcc.target/powerpc/sse2-cvtps2dq-1.c: Likewise. + * gcc.target/powerpc/sse2-cvtps2pd-1.c: Likewise. + * gcc.target/powerpc/sse2-cvtsd2si-1.c: Likewise. + * gcc.target/powerpc/sse2-cvtsd2si-2.c: Likewise. + * gcc.target/powerpc/sse2-cvtsd2ss-1.c: Likewise. + * gcc.target/powerpc/sse2-cvtsi2sd-1.c: Likewise. + * gcc.target/powerpc/sse2-cvtsi2sd-2.c: Likewise. + * gcc.target/powerpc/sse2-cvtss2sd-1.c: Likewise. + * gcc.target/powerpc/sse2-cvttpd2dq-1.c: Likewise. + * gcc.target/powerpc/sse2-cvttps2dq-1.c: Likewise. + * gcc.target/powerpc/sse2-cvttsd2si-1.c: Likewise. + * gcc.target/powerpc/sse2-cvttsd2si-2.c: Likewise. + * gcc.target/powerpc/sse2-divpd-1.c: Likewise. + * gcc.target/powerpc/sse2-divsd-1.c: Likewise. + * gcc.target/powerpc/sse2-maxpd-1.c: Likewise. + * gcc.target/powerpc/sse2-maxsd-1.c: Likewise. + * gcc.target/powerpc/sse2-minpd-1.c: Likewise. + * gcc.target/powerpc/sse2-minsd-1.c: Likewise. + * gcc.target/powerpc/sse2-mmx.c: Likewise. + * gcc.target/powerpc/sse2-movhpd-1.c: Likewise. + * gcc.target/powerpc/sse2-movhpd-2.c: Likewise. + * gcc.target/powerpc/sse2-movlpd-1.c: Likewise. + * gcc.target/powerpc/sse2-movlpd-2.c: Likewise. + * gcc.target/powerpc/sse2-movmskpd-1.c: Likewise. + * gcc.target/powerpc/sse2-movq-1.c: Likewise. + * gcc.target/powerpc/sse2-movq-2.c: Likewise. + * gcc.target/powerpc/sse2-movq-3.c: Likewise. + * gcc.target/powerpc/sse2-movsd-1.c: Likewise. + * gcc.target/powerpc/sse2-movsd-2.c: Likewise. + * gcc.target/powerpc/sse2-movsd-3.c: Likewise. + * gcc.target/powerpc/sse2-mulpd-1.c: Likewise. + * gcc.target/powerpc/sse2-mulsd-1.c: Likewise. + * gcc.target/powerpc/sse2-orpd-1.c: Likewise. + * gcc.target/powerpc/sse2-packssdw-1.c: Likewise. + * gcc.target/powerpc/sse2-packsswb-1.c: Likewise. + * gcc.target/powerpc/sse2-packuswb-1.c: Likewise. + * gcc.target/powerpc/sse2-paddb-1.c: Likewise. + * gcc.target/powerpc/sse2-paddd-1.c: Likewise. + * gcc.target/powerpc/sse2-paddq-1.c: Likewise. + * gcc.target/powerpc/sse2-paddsb-1.c: Likewise. + * gcc.target/powerpc/sse2-paddsw-1.c: Likewise. + * gcc.target/powerpc/sse2-paddusb-1.c: Likewise. + * gcc.target/powerpc/sse2-paddusw-1.c: Likewise. + * gcc.target/powerpc/sse2-paddw-1.c: Likewise. + * gcc.target/powerpc/sse2-pand-1.c: Likewise. + * gcc.target/powerpc/sse2-pandn-1.c: Likewise. + * gcc.target/powerpc/sse2-pavgb-1.c: Likewise. + * gcc.target/powerpc/sse2-pavgw-1.c: Likewise. + * gcc.target/powerpc/sse2-pcmpeqb-1.c: Likewise. + * gcc.target/powerpc/sse2-pcmpeqd-1.c: Likewise. + * gcc.target/powerpc/sse2-pcmpeqw-1.c: Likewise. + * gcc.target/powerpc/sse2-pcmpgtb-1.c: Likewise. + * gcc.target/powerpc/sse2-pcmpgtd-1.c: Likewise. + * gcc.target/powerpc/sse2-pcmpgtw-1.c: Likewise. + * gcc.target/powerpc/sse2-pextrw.c: Likewise. + * gcc.target/powerpc/sse2-pinsrw.c: Likewise. + * gcc.target/powerpc/sse2-pmaddwd-1.c: Likewise. + * gcc.target/powerpc/sse2-pmaxsw-1.c: Likewise. + * gcc.target/powerpc/sse2-pmaxub-1.c: Likewise. + * gcc.target/powerpc/sse2-pminsw-1.c: Likewise. + * gcc.target/powerpc/sse2-pminub-1.c: Likewise. + * gcc.target/powerpc/sse2-pmovmskb-1.c: Likewise. + * gcc.target/powerpc/sse2-pmulhuw-1.c: Likewise. + * gcc.target/powerpc/sse2-pmulhw-1.c: Likewise. + * gcc.target/powerpc/sse2-pmullw-1.c: Likewise. + * gcc.target/powerpc/sse2-pmuludq-1.c: Likewise. + * gcc.target/powerpc/sse2-por-1.c: Likewise. + * gcc.target/powerpc/sse2-psadbw-1.c: Likewise. + * gcc.target/powerpc/sse2-pshufd-1.c: Likewise. + * gcc.target/powerpc/sse2-pshufhw-1.c: Likewise. + * gcc.target/powerpc/sse2-pshuflw-1.c: Likewise. + * gcc.target/powerpc/sse2-pslld-1.c: Likewise. + * gcc.target/powerpc/sse2-pslld-2.c: Likewise. + * gcc.target/powerpc/sse2-pslldq-1.c: Likewise. + * gcc.target/powerpc/sse2-psllq-1.c: Likewise. + * gcc.target/powerpc/sse2-psllq-2.c: Likewise. + * gcc.target/powerpc/sse2-psllw-1.c: Likewise. + * gcc.target/powerpc/sse2-psllw-2.c: Likewise. + * gcc.target/powerpc/sse2-psrad-1.c: Likewise. + * gcc.target/powerpc/sse2-psrad-2.c: Likewise. + * gcc.target/powerpc/sse2-psraw-1.c: Likewise. + * gcc.target/powerpc/sse2-psraw-2.c: Likewise. + * gcc.target/powerpc/sse2-psrld-1.c: Likewise. + * gcc.target/powerpc/sse2-psrld-2.c: Likewise. + * gcc.target/powerpc/sse2-psrldq-1.c: Likewise. + * gcc.target/powerpc/sse2-psrlq-1.c: Likewise. + * gcc.target/powerpc/sse2-psrlq-2.c: Likewise. + * gcc.target/powerpc/sse2-psrlw-1.c: Likewise. + * gcc.target/powerpc/sse2-psrlw-2.c: Likewise. + * gcc.target/powerpc/sse2-psubb-1.c: Likewise. + * gcc.target/powerpc/sse2-psubd-1.c: Likewise. + * gcc.target/powerpc/sse2-psubq-1.c: Likewise. + * gcc.target/powerpc/sse2-psubsb-1.c: Likewise. + * gcc.target/powerpc/sse2-psubsw-1.c: Likewise. + * gcc.target/powerpc/sse2-psubusb-1.c: Likewise. + * gcc.target/powerpc/sse2-psubusw-1.c: Likewise. + * gcc.target/powerpc/sse2-psubw-1.c: Likewise. + * gcc.target/powerpc/sse2-punpckhbw-1.c: Likewise. + * gcc.target/powerpc/sse2-punpckhdq-1.c: Likewise. + * gcc.target/powerpc/sse2-punpckhqdq-1.c: Likewise. + * gcc.target/powerpc/sse2-punpckhwd-1.c: Likewise. + * gcc.target/powerpc/sse2-punpcklbw-1.c: Likewise. + * gcc.target/powerpc/sse2-punpckldq-1.c: Likewise. + * gcc.target/powerpc/sse2-punpcklqdq-1.c: Likewise. + * gcc.target/powerpc/sse2-punpcklwd-1.c: Likewise. + * gcc.target/powerpc/sse2-pxor-1.c: Likewise. + * gcc.target/powerpc/sse2-shufpd-1.c: Likewise. + * gcc.target/powerpc/sse2-sqrtpd-1.c: Likewise. + * gcc.target/powerpc/sse2-subpd-1.c: Likewise. + * gcc.target/powerpc/sse2-subsd-1.c: Likewise. + * gcc.target/powerpc/sse2-ucomisd-1.c: Likewise. + * gcc.target/powerpc/sse2-ucomisd-2.c: Likewise. + * gcc.target/powerpc/sse2-ucomisd-3.c: Likewise. + * gcc.target/powerpc/sse2-ucomisd-4.c: Likewise. + * gcc.target/powerpc/sse2-ucomisd-5.c: Likewise. + * gcc.target/powerpc/sse2-ucomisd-6.c: Likewise. + * gcc.target/powerpc/sse2-unpckhpd-1.c: Likewise. + * gcc.target/powerpc/sse2-unpcklpd-1.c: Likewise. + * gcc.target/powerpc/sse2-xorpd-1.c: Likewise. + * gcc.target/powerpc/sse3-addsubpd.c: Likewise. + * gcc.target/powerpc/sse3-addsubps.c: Likewise. + * gcc.target/powerpc/sse3-haddpd.c: Likewise. + * gcc.target/powerpc/sse3-haddps.c: Likewise. + * gcc.target/powerpc/sse3-hsubpd.c: Likewise. + * gcc.target/powerpc/sse3-hsubps.c: Likewise. + * gcc.target/powerpc/sse3-lddqu.c: Likewise. + * gcc.target/powerpc/sse3-movddup.c: Likewise. + * gcc.target/powerpc/sse3-movshdup.c: Likewise. + * gcc.target/powerpc/sse3-movsldup.c: Likewise. + * gcc.target/powerpc/sse4_1-blendpd.c: Likewise. + * gcc.target/powerpc/sse4_1-blendps-2.c: Likewise. + * gcc.target/powerpc/sse4_1-blendps.c: Likewise. + * gcc.target/powerpc/sse4_1-blendvpd.c: Likewise. + * gcc.target/powerpc/sse4_1-blendvps.c: Likewise. + * gcc.target/powerpc/sse4_1-ceilpd.c: Likewise. + * gcc.target/powerpc/sse4_1-ceilps.c: Likewise. + * gcc.target/powerpc/sse4_1-ceilsd.c: Likewise. + * gcc.target/powerpc/sse4_1-ceilss.c: Likewise. + * gcc.target/powerpc/sse4_1-floorpd.c: Likewise. + * gcc.target/powerpc/sse4_1-floorps.c: Likewise. + * gcc.target/powerpc/sse4_1-floorsd.c: Likewise. + * gcc.target/powerpc/sse4_1-floorss.c: Likewise. + * gcc.target/powerpc/sse4_1-pblendvb.c: Likewise. + * gcc.target/powerpc/sse4_1-pblendw-2.c: Likewise. + * gcc.target/powerpc/sse4_1-pblendw.c: Likewise. + * gcc.target/powerpc/sse4_1-pcmpeqq.c: Likewise. + * gcc.target/powerpc/sse4_1-pinsrb.c: Likewise. + * gcc.target/powerpc/sse4_1-pinsrd.c: Likewise. + * gcc.target/powerpc/sse4_1-pinsrq.c: Likewise. + * gcc.target/powerpc/sse4_1-pmovsxbq.c: Likewise. + * gcc.target/powerpc/sse4_1-pmovsxdq.c: Likewise. + * gcc.target/powerpc/sse4_1-pmovsxwq.c: Likewise. + * gcc.target/powerpc/sse4_1-pmuldq.c: Likewise. + * gcc.target/powerpc/sse4_1-ptest-1.c: Likewise. + * gcc.target/powerpc/sse4_1-roundpd-2.c: Likewise. + * gcc.target/powerpc/sse4_1-roundpd-3.c: Likewise. + * gcc.target/powerpc/sse4_2-pcmpgtq.c: Likewise. + * gcc.target/powerpc/ssse3-pabsb.c: Likewise. + * gcc.target/powerpc/ssse3-pabsd.c: Likewise. + * gcc.target/powerpc/ssse3-pabsw.c: Likewise. + * gcc.target/powerpc/ssse3-palignr.c: Likewise. + * gcc.target/powerpc/ssse3-phaddd.c: Likewise. + * gcc.target/powerpc/ssse3-phaddsw.c: Likewise. + * gcc.target/powerpc/ssse3-phaddw.c: Likewise. + * gcc.target/powerpc/ssse3-phsubd.c: Likewise. + * gcc.target/powerpc/ssse3-phsubsw.c: Likewise. + * gcc.target/powerpc/ssse3-phsubw.c: Likewise. + * gcc.target/powerpc/ssse3-pmaddubsw.c: Likewise. + * gcc.target/powerpc/ssse3-pmulhrsw.c: Likewise. + * gcc.target/powerpc/ssse3-pshufb.c: Likewise. + * gcc.target/powerpc/ssse3-psignb.c: Likewise. + * gcc.target/powerpc/ssse3-psignd.c: Likewise. + * gcc.target/powerpc/ssse3-psignw.c: Likewise. + * gcc.target/powerpc/vec-cmp-sel.c: Likewise. + * gcc.target/powerpc/vec-sld-modulo.c: Likewise. + * gcc.target/powerpc/vec-srad-modulo.c: Likewise. + * gcc.target/powerpc/vec-srd-modulo.c: Likewise. + * gcc.target/powerpc/amo1.c: Replace powerpc_p9vector_ok with + powerpc_vsx_ok, replace -mpower9-vector with -mvsx, and add + dg-additional-options -mdejagnu-cpu=power9 if !has_arch_pwr9. + * gcc.target/powerpc/amo2.c: Likewise. + * gcc.target/powerpc/dform-1.c: Likewise. + * gcc.target/powerpc/dform-2.c: Likewise. + * gcc.target/powerpc/float128-5.c: Likewise. + * gcc.target/powerpc/float128-complex-2.c: Likewise. + * gcc.target/powerpc/float128-fma1.c: Likewise. + * gcc.target/powerpc/float128-hw.c: Likewise. + * gcc.target/powerpc/float128-hw10.c: Likewise. + * gcc.target/powerpc/float128-hw11.c: Likewise. + * gcc.target/powerpc/float128-hw2.c: Likewise. + * gcc.target/powerpc/float128-hw3.c: Likewise. + * gcc.target/powerpc/float128-hw4.c: Likewise. + * gcc.target/powerpc/float128-hw5.c: Likewise. + * gcc.target/powerpc/float128-hw6.c: Likewise. + * gcc.target/powerpc/float128-hw7.c: Likewise. + * gcc.target/powerpc/float128-hw8.c: Likewise. + * gcc.target/powerpc/float128-hw9.c: Likewise. + * gcc.target/powerpc/float128-minmax.c: Likewise. + * gcc.target/powerpc/float128-odd.c: Likewise. + * gcc.target/powerpc/float128-sqrt1.c: Likewise. + * gcc.target/powerpc/fold-vec-cmp-int.p9.c: Likewise. + * gcc.target/powerpc/gnuattr2.c: Likewise. + * gcc.target/powerpc/pr71656-1.c: Likewise. + * gcc.target/powerpc/pr71656-2.c: Likewise. + * gcc.target/powerpc/pr81959.c: Likewise. + * gcc.target/powerpc/pr82748-1.c: Likewise. + * gcc.target/powerpc/pr82748-2.c: Likewise. + * gcc.target/powerpc/pr111449-2.c: Replace powerpc_p8vector_ok + with powerpc_vsx_ok. + * gcc.target/powerpc/pr98914.c: Likewise. + * gcc.target/powerpc/versioned-copy-loop.c: Replace + powerpc_p8vector_ok with powerpc_vsx_ok and append -mvsx to + dg-options. + * gcc.target/powerpc/clone2.c: Replace powerpc_p9vector_ok with + powerpc_vsx_ok. + * gcc.target/powerpc/p9-options-1.c: Replace powerpc_p9vector_ok + with powerpc_vsx_ok, replace -mno-power9-vector with -mno-vsx. + * gcc.target/powerpc/pr84226.c: Replace powerpc_p9vector_ok with + powerpc_vsx_ok and append -mvsx to dg-options. + * g++.dg/pr69667.C: Replace powerpc_p8vector_ok with + powerpc_vsx_ok and append -mvsx to dg-options. + * gcc.dg/vect/costmodel/ppc/costmodel-slp-perm.c: Replace + powerpc_p9vector_ok with powerpc_vsx_ok and replace + -mpower9-vector with -mvsx. + * gcc.dg/vect/pr109011-1.c: Replace powerpc_p8vector_ok with + powerpc_vsx_ok, and replace -mpower8-vector with + -mdejagnu-cpu=power8 -mvsx or -mvsx under different conditions. + * gcc.dg/vect/pr109011-2.c: Replace powerpc_p9vector_ok + with powerpc_vsx_ok, and replace -mpower9-vector with + -mdejagnu-cpu=power9 -mvsx or -mvsx under different conditions. + * gcc.dg/vect/pr109011-4.c: Likewise. + * gcc.dg/vect/pr109011-3.c: Replace powerpc_p8vector_ok with + powerpc_vsx_ok, and replace -mpower8-vector -mno-power9-vector + with -mdejagnu-cpu=power8 -mvsx. + * gcc.dg/vect/pr109011-5.c: Likewise. + * gcc.target/powerpc/altivec-35.c: Remove -mno-power8-vector. + * gcc.target/powerpc/vsx-vector-7.c: Replace -mno-power8-vector + with -mdejagnu-cpu=power7. + * gcc.dg/vect/O3-pr70130.c: Replace -mcpu=power7 with options + -mdejagnu-cpu=power7 -mvsx and remove option -mno-power9-vector + -mno-power8-vector. + * gfortran.dg/vect/pr45714-b.f: Likewise. + * gcc.dg/vect/pr48765.c: Remove dg-skip-if and replace -mcpu=power7 + with option -mdejagnu-cpu=power6. + * gcc.target/powerpc/pr78056-2.c: Likewise. + * gcc.target/powerpc/altivec-2-runnable.c: Replace + powerpc_p8vector_ok with powerpc_vsx_ok, remove -mpower8-vector + and add dg-additional-options -mdejagnu-cpu=power8 if !has_arch_pwr8. + * gcc.target/powerpc/altivec-37.c: Likewise. + * gcc.target/powerpc/fold-vec-abs-longlong-fwrapv.p8.c: Replace + powerpc_p8vector_ok with powerpc_vsx_ok and replace -mpower8-vector + with -mvsx. + * gcc.target/powerpc/fold-vec-abs-longlong.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-cmp-char.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-cmp-int.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-cmp-short.p8.c: Likewise. + * gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c: Likewise. + * gcc.target/powerpc/fold-vec-mergeeo-int.c: Likewise. + * gcc.target/powerpc/fold-vec-mergeeo-longlong.c: Likewise. + * gcc.target/powerpc/fold-vec-mult-int128-p8.c: Likewise. + * gcc.target/powerpc/fold-vec-neg-longlong.p8.c: Likewise. + * gcc.target/powerpc/pr104124.c: Likewise. + * gcc.target/powerpc/vec-cmpne-long.c: Likewise. + * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Replace + powerpc_p8vector_ok with powerpc_vsx_ok, replace -mpower8-vector with + -mvsx and add dg-additional-options -mdejagnu-cpu=power8 if + !has_arch_pwr8. + * gcc.target/powerpc/pr80098-1.c: Replace powerpc_p9vector_ok with + powerpc_vsx_ok and replace -mno-power9-vector with -mno-vsx. + * gcc.target/powerpc/pr80098-2.c: Replace powerpc_p8vector_ok with + powerpc_vsx_ok and replace -mno-power8-vector with -mno-vsx. + * gcc.target/powerpc/pragma_misc9.c: Replace powerpc_p9vector_ok + with powerpc_vsx_ok. + +2024-02-22 Pan Li + + PR target/114017 + * gcc.target/riscv/predef-__riscv_v_intrinsic.c: Update the + version to 0.12. + * gcc.target/riscv/rvv/base/pr114017-1.c: New test. + +2024-02-22 Fangrui Song + + * gcc.target/riscv/asm-raw-symbol.c: New test. + 2024-02-21 Edwin Lu PR target/113249 -- cgit v1.1 From 33abf74108f37fb7792572e538617fd15c8ade29 Mon Sep 17 00:00:00 2001 From: Lulu Cheng Date: Wed, 21 Feb 2024 11:17:14 +0800 Subject: LoongArch: When checking whether the assembler supports conditional branch relaxation, add compilation parameter "--fatal-warnings" to the assembler. In binutils 2.40 and earlier versions, only a warning will be reported when a relocation immediate value is out of bounds. As a result, the value of the macro HAVE_AS_COND_BRANCH_RELAXATION will also be defined as 1 when the assembler does not support conditional branch relaxation. Therefore, add the compilation option "--fatal-warnings" to avoid this problem. gcc/ChangeLog: * configure: Regenerate. * configure.ac: Add parameter "--fatal-warnings" to assemble when checking whether the assemble support conditional branch relaxation. --- gcc/configure | 2 +- gcc/configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/configure b/gcc/configure index 41b978b..f1d434f 100755 --- a/gcc/configure +++ b/gcc/configure @@ -31136,7 +31136,7 @@ else nop .endr beq $a0,$a1,a' > conftest.s - if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5' + if { ac_try='$gcc_cv_as $gcc_cv_as_flags --fatal-warnings -o conftest.o conftest.s >&5' { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 (eval $ac_try) 2>&5 ac_status=$? diff --git a/gcc/configure.ac b/gcc/configure.ac index 72012d6..9ebc578 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -5486,7 +5486,7 @@ x: [Define if your assembler supports -mrelax option.])]) gcc_GAS_CHECK_FEATURE([conditional branch relaxation support], gcc_cv_as_loongarch_cond_branch_relax, - [], + [--fatal-warnings], [a: .rept 32769 nop -- cgit v1.1 From 1c5da882bf77400748aeb0b01bf9a7faba1a4f32 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Tue, 20 Feb 2024 07:45:38 -0800 Subject: doc: RISC-V: Document that -mcpu doesn't override -march or -mtune This came up recently as Edwin was looking through the test suite. A few of us were talking about this during the patchwork meeting and were surprised. Looks like this is the desired behavior, so let's at least document it. gcc/ChangeLog: * doc/invoke.texi: Document -mcpu. Signed-off-by: Palmer Dabbelt --- gcc/doc/invoke.texi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'gcc') diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 58527e1..4f4ca2b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30750,6 +30750,8 @@ Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21}, @samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450}, @samp{sifive-x670}. +Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}. + @opindex mtune @item -mtune=@var{processor-string} Optimize the output for the given processor, specified by microarchitecture or -- cgit v1.1 From 23f5da91ccb4927562ea4d1c245639bfd4a0088b Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Fri, 9 Feb 2024 08:53:24 -0800 Subject: RISC-V: Point our Python scripts at python3 This builds for me, and I frequently have python-is-python3 type packages installed so I think I've been implicitly testing it for a while. Looks like Kito's tested similar configurations, and the bugzilla indicates we should be moving over. gcc/ChangeLog: PR other/109668 * config/riscv/arch-canonicalize: Move to python3 * config/riscv/multilib-generator: Likewise --- gcc/config/riscv/arch-canonicalize | 2 +- gcc/config/riscv/multilib-generator | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index 629bed8..8f7d040 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # Tool for canonical RISC-V architecture string. # Copyright (C) 2011-2024 Free Software Foundation, Inc. diff --git a/gcc/config/riscv/multilib-generator b/gcc/config/riscv/multilib-generator index 1a95787..25cb676 100755 --- a/gcc/config/riscv/multilib-generator +++ b/gcc/config/riscv/multilib-generator @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # RISC-V multilib list generator. # Copyright (C) 2011-2024 Free Software Foundation, Inc. -- cgit v1.1 From 6837c4503735d1bbcad0fb6e30cc139f3598f027 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Fri, 23 Feb 2024 10:06:41 +0100 Subject: testsuite: plugin: Fix gcc.dg/plugin/crash-test-write-though-null-sarif.c on Solaris gcc.dg/plugin/crash-test-write-though-null-sarif.c FAILs on Solaris: FAIL: gcc.dg/plugin/crash-test-write-though-null-sarif.c -fplugin=./crash_test_plugin.so scan-sarif-file "text": "Segmentation fault Comparing the sarif files between Linux and Solaris reveals - "message": {"text": "Segmentation fault"}, + "message": {"text": "Segmentation Fault"}, This patch allows for both forms. Tested on i386-pc-solaris2.11, sparc-sun-solaris2.11, and x86_64-pc-linux-gnu. 2024-02-22 Rainer Orth gcc/testsuite: * gcc.dg/plugin/crash-test-write-though-null-sarif.c (scan-sarif-file): Allow for "Segmentation Fault", too. --- gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c b/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c index 513d66c..d5d824d 100644 --- a/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c +++ b/gcc/testsuite/gcc.dg/plugin/crash-test-write-though-null-sarif.c @@ -61,4 +61,4 @@ void test_inject_write_through_null (void) { dg-final { scan-sarif-file "\"startColumn\": 3" } } { dg-final { scan-sarif-file "\"endColumn\": 31" } } { dg-final { scan-sarif-file "\"message\": " } } - { dg-final { scan-sarif-file "\"text\": \"Segmentation fault" } } */ + { dg-final { scan-sarif-file "\"text\": \"Segmentation \[Ff\]ault" } } */ -- cgit v1.1 From 818094a07a0b550643ecd0090647dc29cc9e153a Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Fri, 23 Feb 2024 10:14:31 +0100 Subject: testsuite: vect: Actually skip gcc.dg/vect/vect-bic-bitmask-12.c etc. on SPARC gcc.dg/vect/vect-bic-bitmask-12.c and gcc.dg/vect/vect-bic-bitmask-23.c currently FAIL on 32 and 64-bit Solaris/SPARC FAIL: gcc.dg/vect/vect-bic-bitmask-12.c -flto -ffat-lto-objects scan-tree-dump dce7 "<=\\\\s*.+{ 255,.+}" FAIL: gcc.dg/vect/vect-bic-bitmask-12.c scan-tree-dump dce7 "<=\\\\s*.+{ 255,.+}" FAIL: gcc.dg/vect/vect-bic-bitmask-23.c -flto -ffat-lto-objects scan-tree-dump dce7 "<=\\\\s*.+{ 255, 15, 1, 65535 }" FAIL: gcc.dg/vect/vect-bic-bitmask-23.c scan-tree-dump dce7 "<=\\\\s*.+{ 255, 15, 1, 65535 }" although they should be skipped since commit 5f07095d22f58572c06997aa6d4f3bc456e1925d Author: Tamar Christina Date: Tue Mar 8 11:32:59 2022 +0000 vect: disable bitmask tests on sparc The problem is that dg-skip-if must come after dg-do, although this isn't currently documented unfortunately. Fixed by reordering the directives. Tested on sparc-sun-solaris2.11 and i386-pc-solaris2.11. 2024-02-22 Rainer Orth gcc/testsuite: * gcc.dg/vect/vect-bic-bitmask-12.c: Move dg-skip-if down. * gcc.dg/vect/vect-bic-bitmask-23.c: Likewise. --- gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c index 213e4c2..70e609a 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c +++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-12.c @@ -1,6 +1,6 @@ -/* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */ /* { dg-do compile } */ /* { dg-additional-options "-O3 -fdump-tree-dce -w" } */ +/* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */ #include diff --git a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c index 5dceb4b..95e2800 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c +++ b/gcc/testsuite/gcc.dg/vect/vect-bic-bitmask-23.c @@ -1,6 +1,6 @@ -/* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */ /* { dg-do compile } */ /* { dg-additional-options "-O1 -fdump-tree-dce -w" } */ +/* { dg-skip-if "missing optab for vectorization" { sparc*-*-* } } */ #include -- cgit v1.1 From bff1cbf2f61d9532eceaa6ebe71185f4b0902a76 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Fri, 23 Feb 2024 08:59:12 +0100 Subject: Add ia64*-*-* to the list of obsolete targets The following deprecates ia64*-*-* for GCC 14. Since we plan to force LRA for GCC 15 and the target only has slim chances of getting updated this notifies people in advance. Given both Linux and glibc have axed the target further development is also made difficult. There is no listed maintainer for ia64 either. PR target/90785 gcc/ * config.gcc: Add ia64*-*-* to the list of obsoleted targets. contrib/ * config-list.mk (LIST): --enable-obsolete for ia64*-*-*. --- gcc/config.gcc | 1 + 1 file changed, 1 insertion(+) (limited to 'gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index a0f9c67..2e35a11 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -273,6 +273,7 @@ esac # Obsolete configurations. case ${target}${target_min} in *-*-solaris2.11.[0-3]* \ + | ia64*-*-* \ ) if test "x$enable_obsolete" != xyes; then echo "*** Configuration ${target}${target_min} is obsolete." >&2 -- cgit v1.1 From be1f2bc4522f772184a4d16d8f3fec75baed89cf Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 23 Feb 2024 11:36:15 +0100 Subject: bitintlower: Fix .{ADD,SUB}_OVERFLOW lowering [PR114040] The following testcases show 2 bugs in the .{ADD,SUB}_OVERFLOW lowering, both related to storing of the REALPART_EXPR part of the result. On the first testcase prec is 255, prec_limbs is 4 and for the second limb in the loop the store of the REALPART_EXPR of .USUBC (_30) is stored through: if (_27 <= 3) goto ; [80.00%] else goto ; [20.00%] [local count: 1073741824]: if (_27 < 3) goto ; [80.00%] else goto ; [20.00%] [local count: 1073741824]: bitint.3[_27] = _30; goto ; [100.00%] [local count: 858993464]: MEM[(unsigned long *)&bitint.3 + 24B] = _30; [local count: 1073741824]: The first check is right, as prec_limbs is 4, we don't want to store bitint.3[4] or above at all, those limbs are just computed for the overflow checking and nothing else, so _27 > 4 leads to no store. But the other condition is exact opposite of what should be done, if the current index of the second limb (_27) is < 3, then it should bitint.3[_27] = _30; and if it is == 3, it should MEM[(unsigned long *)&bitint.3 + 24B] = _30; and (especially important for the targets which would bitinfo.extended = 1) should actually in this case zero extend it from the 63 bits to 64, that is the handling of the partial limb. The if_then_if_then_else helper if there are 2 conditions sets m_gsi to be at the start of the edge_true_false->dest bb, i.e. when the first condition is true and second false, and that is where we store the SSA_NAME indexed limb store, so the condition needs to be reversed. The following patch does that and adds the cast as well, the usual assumption that already handle_operand has the partial limb type doesn't have to be true here, because the source operand could have much larger precision than the REALPART_EXPR of the lhs. 2024-02-23 Jakub Jelinek PR tree-optimization/114040 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow): Use EQ_EXPR rather than LT_EXPR for g2 condition and change its probability from likely to unlikely. When handling the true true store, first cast to limb_access_type and then to l's type. * gcc.dg/torture/bitint-60.c: New test. * gcc.dg/torture/bitint-61.c: New test. --- gcc/gimple-lower-bitint.cc | 11 ++++++---- gcc/testsuite/gcc.dg/torture/bitint-60.c | 24 +++++++++++++++++++++ gcc/testsuite/gcc.dg/torture/bitint-61.c | 36 ++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/torture/bitint-60.c create mode 100644 gcc/testsuite/gcc.dg/torture/bitint-61.c (limited to 'gcc') diff --git a/gcc/gimple-lower-bitint.cc b/gcc/gimple-lower-bitint.cc index fb03063..3552fdd 100644 --- a/gcc/gimple-lower-bitint.cc +++ b/gcc/gimple-lower-bitint.cc @@ -4255,12 +4255,12 @@ bitint_large_huge::lower_addsub_overflow (tree obj, gimple *stmt) NULL_TREE, NULL_TREE); gimple *g2 = NULL; if (!single_comparison) - g2 = gimple_build_cond (LT_EXPR, idx, + g2 = gimple_build_cond (EQ_EXPR, idx, size_int (prec_limbs - 1), NULL_TREE, NULL_TREE); edge edge_true_true, edge_true_false, edge_false; if_then_if_then_else (g, g2, profile_probability::likely (), - profile_probability::likely (), + profile_probability::unlikely (), edge_true_true, edge_true_false, edge_false); tree l = limb_access (type, var ? var : obj, idx, true); @@ -4269,8 +4269,11 @@ bitint_large_huge::lower_addsub_overflow (tree obj, gimple *stmt) if (!single_comparison) { m_gsi = gsi_after_labels (edge_true_true->src); - l = limb_access (type, var ? var : obj, - size_int (prec_limbs - 1), true); + tree plm1idx = size_int (prec_limbs - 1); + tree plm1type = limb_access_type (type, plm1idx); + l = limb_access (type, var ? var : obj, plm1idx, true); + if (!useless_type_conversion_p (plm1type, TREE_TYPE (rhs))) + rhs = add_cast (plm1type, rhs); if (!useless_type_conversion_p (TREE_TYPE (l), TREE_TYPE (rhs))) rhs = add_cast (TREE_TYPE (l), rhs); diff --git a/gcc/testsuite/gcc.dg/torture/bitint-60.c b/gcc/testsuite/gcc.dg/torture/bitint-60.c new file mode 100644 index 0000000..d2d27a1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/bitint-60.c @@ -0,0 +1,24 @@ +/* PR tree-optimization/114040 */ +/* { dg-do run { target bitint } } */ +/* { dg-options "-std=c23 -pedantic-errors" } */ +/* { dg-skip-if "" { ! run_expensive_tests } { "*" } { "-O0" "-O2" } } */ +/* { dg-skip-if "" { ! run_expensive_tests } { "-flto" } { "" } } */ + +#if __BITINT_MAXWIDTH__ >= 8671 +__attribute__((noipa)) unsigned +foo (unsigned _BitInt(8671) x, unsigned y, unsigned _BitInt(512) z) +{ + unsigned _BitInt (8671) r + = x * __builtin_sub_overflow_p (y * z, 0, (unsigned _BitInt(255)) 0); + return r; +} +#endif + +int +main () +{ +#if __BITINT_MAXWIDTH__ >= 8671 + if (foo (1, 1, 0xfffa46471e7c2dd60000000000000000wb)) + __builtin_abort (); +#endif +} diff --git a/gcc/testsuite/gcc.dg/torture/bitint-61.c b/gcc/testsuite/gcc.dg/torture/bitint-61.c new file mode 100644 index 0000000..e5651f10 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/bitint-61.c @@ -0,0 +1,36 @@ +/* PR tree-optimization/114040 */ +/* { dg-do run { target { bitint && int128 } } } */ +/* { dg-options "-std=c23" } */ +/* { dg-skip-if "" { ! run_expensive_tests } { "*" } { "-O0" "-O2" } } */ +/* { dg-skip-if "" { ! run_expensive_tests } { "-flto" } { "" } } */ + +unsigned a; +signed char b; +short c; +long d; +__int128 e; +int f; + +#if __BITINT_MAXWIDTH__ >= 511 +__attribute__((noinline)) void +foo (_BitInt(3) x, unsigned _BitInt(511) y, unsigned *z) +{ + int g = __builtin_sub_overflow_p (y ^ x, 0, (unsigned _BitInt(255)) 0); + unsigned h = y + e, i = h + d; + unsigned _BitInt(2) j = i + g; + unsigned k = j + c; + unsigned l = k + a + f + b; + *z = l; +} +#endif + +int +main () +{ +#if __BITINT_MAXWIDTH__ >= 511 + unsigned x; + foo (0, 0x81e4a5fa7c408f370000000000000000uwb, &x); + if (x) + __builtin_abort (); +#endif +} -- cgit v1.1 From 22121546e0315d25ee419d2389022e3974750885 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 23 Feb 2024 11:38:18 +0100 Subject: expr: Fix REDUCE_BIT_FIELD in multiplication expansion [PR114054] The following testcase ICEs, because the REDUCE_BIT_FIELD macro uses the target variable implicitly: #define REDUCE_BIT_FIELD(expr) (reduce_bit_field \ ? reduce_to_bit_field_precision ((expr), \ target, \ type) \ : (expr)) and so when the code below reuses the target variable, documented to be The value may be stored in TARGET if TARGET is nonzero. TARGET is just a suggestion; callers must assume that the rtx returned may not be the same as TARGET. for something unrelated (the value that should be returned), this misbehaves (in the testcase target is set to a CONST_INT, which has VOIDmode and reduce_to_bit_field_precision assert checking doesn't like that). Needed to say that If TARGET is CONST0_RTX, it means that the value will be ignored. but in expand_expr_real_2 does at the start: ignore = (target == const0_rtx || ((CONVERT_EXPR_CODE_P (code) || code == COND_EXPR || code == VIEW_CONVERT_EXPR) && TREE_CODE (type) == VOID_TYPE)); /* We should be called only if we need the result. */ gcc_assert (!ignore); - so such target is mainly meant for calls and the like in other routines. Certainly doesn't expect that target changes from not being ignored initially to ignore later on and other CONST_INT results as well as anything which is not an object into which anything can be stored. So, the following patch fixes that by using a more appripriate temporary for the result, which other code is using. 2024-02-23 Jakub Jelinek PR rtl-optimization/114054 * expr.cc (expand_expr_real_2) : Use temp variable instead of target parameter for result. * gcc.dg/bitint-92.c: New test. --- gcc/expr.cc | 12 ++++++------ gcc/testsuite/gcc.dg/bitint-92.c | 17 +++++++++++++++++ 2 files changed, 23 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/bitint-92.c (limited to 'gcc') diff --git a/gcc/expr.cc b/gcc/expr.cc index e238811..8d34d02 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -10259,12 +10259,12 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode, &algorithm, &variant, cost) : cost < mul_cost (speed, mode)) { - target = bit0_p ? expand_and (mode, negate_rtx (mode, op0), - op1, target) - : expand_and (mode, op0, - negate_rtx (mode, op1), - target); - return REDUCE_BIT_FIELD (target); + temp = bit0_p ? expand_and (mode, negate_rtx (mode, op0), + op1, target) + : expand_and (mode, op0, + negate_rtx (mode, op1), + target); + return REDUCE_BIT_FIELD (temp); } } } diff --git a/gcc/testsuite/gcc.dg/bitint-92.c b/gcc/testsuite/gcc.dg/bitint-92.c new file mode 100644 index 0000000..c567d63 --- /dev/null +++ b/gcc/testsuite/gcc.dg/bitint-92.c @@ -0,0 +1,17 @@ +/* PR rtl-optimization/114054 */ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-Og -fwhole-program -fno-tree-ccp -fprofile-use -fno-tree-copy-prop -w" } */ + +int x; + +void +foo (int i, unsigned u) +{ + x = __builtin_mul_overflow_p ((unsigned _BitInt(1)) u, i, (_BitInt(33)) 0); +} + +int +main () +{ + foo (11, 0); +} -- cgit v1.1 From 016c4eed368b80a97101f6156ed99e4c5474fbb7 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Thu, 22 Feb 2024 16:47:20 +0000 Subject: arm: fix ICE with vectorized reciprocal division [PR108120] The expand pattern for reciprocal division was enabled for all math optimization modes, but the patterns it was generating were not enabled unless -funsafe-math-optimizations were enabled, this leads to an ICE when the pattern we generate cannot be recognized. Fixed by only enabling vector division when doing unsafe math. gcc: PR target/108120 * config/arm/neon.md (div3): Rename from div3. Gate with ARM_HAVE_NEON__ARITH. gcc/testsuite: PR target/108120 * gcc.target/arm/neon-recip-div-1.c: New file. --- gcc/config/arm/neon.md | 4 ++-- gcc/testsuite/gcc.target/arm/neon-recip-div-1.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/neon-recip-div-1.c (limited to 'gcc') diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 17c90f4..fa4a7ae 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -553,11 +553,11 @@ Enabled with -funsafe-math-optimizations -freciprocal-math and disabled for -Os since it increases code size . */ -(define_expand "div3" +(define_expand "div3" [(set (match_operand:VCVTF 0 "s_register_operand") (div:VCVTF (match_operand:VCVTF 1 "s_register_operand") (match_operand:VCVTF 2 "s_register_operand")))] - "TARGET_NEON && !optimize_size + "ARM_HAVE_NEON__ARITH && !optimize_size && flag_reciprocal_math" { rtx rec = gen_reg_rtx (mode); diff --git a/gcc/testsuite/gcc.target/arm/neon-recip-div-1.c b/gcc/testsuite/gcc.target/arm/neon-recip-div-1.c new file mode 100644 index 0000000..e15c3ca --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/neon-recip-div-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-O3 -freciprocal-math -fno-unsafe-math-optimizations -save-temps" } */ +/* { dg-add-options arm_neon } */ + +int *a; +int n; +void b() { + int c; + for (c = 0; c < 100000; c++) + a[c] = (float)c / n; +} +/* We should not ICE, or get a vectorized reciprocal instruction when unsafe + math optimizations are disabled. */ +/* { dg-final { scan-assembler-not "vrecpe\\.f32\\t\[qd\].*" } } */ +/* { dg-final { scan-assembler-not "vrecps\\.f32\\t\[qd\].*" } } */ -- cgit v1.1 From 9266d9fce2ca8ec704b932e8af7ab04432772c44 Mon Sep 17 00:00:00 2001 From: Tobias Burnus Date: Fri, 23 Feb 2024 13:12:48 +0100 Subject: Fortran/Openmp: Use OPT_Wopenmp for gfc_match_omp_depobj warning gcc/fortran/ChangeLog: * openmp.cc (gfc_match_omp_depobj): Use OPT_Wopenmp as warning category in gfc_warning. --- gcc/fortran/openmp.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/fortran/openmp.cc b/gcc/fortran/openmp.cc index 77f6e17..38de602 100644 --- a/gcc/fortran/openmp.cc +++ b/gcc/fortran/openmp.cc @@ -4768,8 +4768,8 @@ gfc_match_omp_depobj (void) if (gfc_match (" ( %v ) ", &destroyobj) == MATCH_YES) { if (destroyobj->symtree != depobj->symtree) - gfc_warning (0, "The same depend object should be used as DEPOBJ " - "argument at %L and as DESTROY argument at %L", + gfc_warning (OPT_Wopenmp, "The same depend object should be used as" + " DEPOBJ argument at %L and as DESTROY argument at %L", &depobj->where, &destroyobj->where); gfc_free_expr (destroyobj); } -- cgit v1.1 From 7f2cf0c45f4ba7df4277cde4b1b7493cfc49a89d Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sun, 4 Feb 2024 07:46:35 -0800 Subject: x86-64: Check R_X86_64_CODE_6_GOTTPOFF support If assembler and linker supports add %reg1, name@gottpoff(%rip), %reg2 with R_X86_64_CODE_6_GOTTPOFF, we can generate it instead of mov name@gottpoff(%rip), %reg2 add %reg1, %reg2 gcc/ * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1 if R_X86_64_CODE_6_GOTTPOFF is supported. * config.in: Regenerated. * configure: Likewise. * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported. gcc/testsuite/ * gcc.target/i386/apx-ndd-tls-1b.c: New test. * lib/target-supports.exp (check_effective_target_code_6_gottpoff_reloc): New. --- gcc/config.in | 7 +++ gcc/config/i386/predicates.md | 6 ++- gcc/configure | 68 ++++++++++++++++++++++++++ gcc/configure.ac | 44 +++++++++++++++++ gcc/testsuite/gcc.target/i386/apx-ndd-tls-1b.c | 9 ++++ gcc/testsuite/lib/target-supports.exp | 48 ++++++++++++++++++ 6 files changed, 181 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/apx-ndd-tls-1b.c (limited to 'gcc') diff --git a/gcc/config.in b/gcc/config.in index ce1d073..f3de4ba 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -737,6 +737,13 @@ #endif +/* Define 0/1 if your assembler and linker support R_X86_64_CODE_6_GOTTPOFF. + */ +#ifndef USED_FOR_TARGET +#undef HAVE_AS_R_X86_64_CODE_6_GOTTPOFF +#endif + + /* Define if your assembler supports relocs needed by -fpic. */ #ifndef USED_FOR_TARGET #undef HAVE_AS_SMALL_PIC_RELOCS diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 4c1aedd..391f108 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -2299,10 +2299,14 @@ ;; Return true if OP is a memory operand which can be used in APX NDD ;; ADD with register source operand. UNSPEC_GOTNTPOFF memory operand -;; isn't allowed with APX NDD ADD. +;; is allowed with APX NDD ADD only if R_X86_64_CODE_6_GOTTPOFF works. (define_predicate "apx_ndd_add_memory_operand" (match_operand 0 "memory_operand") { + /* OK if "add %reg1, name@gottpoff(%rip), %reg2" is supported. */ + if (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF) + return true; + op = XEXP (op, 0); /* Disallow APX NDD ADD with UNSPEC_GOTNTPOFF. */ diff --git a/gcc/configure b/gcc/configure index f1d434f..266ab8f 100755 --- a/gcc/configure +++ b/gcc/configure @@ -29834,6 +29834,74 @@ cat >>confdefs.h <<_ACEOF _ACEOF + # Check if gas and gld support "addq %r23,foo@GOTTPOFF(%rip), %r15" + # with R_X86_64_CODE_6_GOTTPOFF relocation. + if echo "$ld_ver" | grep GNU > /dev/null; then + if $gcc_cv_ld -V 2>/dev/null | grep elf_x86_64_sol2 > /dev/null; then + ld_ix86_gld_64_opt="-melf_x86_64_sol2" + else + ld_ix86_gld_64_opt="-melf_x86_64" + fi + fi + # Enforce 64-bit output with gas and gld. + if test x$gas = xyes; then + as_ix86_gas_64_opt="--64" + fi + conftest_s=' + .text + .globl _start + .type _start, @function +_start: + addq %r23,foo@GOTTPOFF(%rip), %r15 + .section .tdata,"awT",@progbits + .type foo, @object +foo: + .quad 0' + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for R_X86_64_CODE_6_GOTTPOFF reloc" >&5 +$as_echo_n "checking assembler for R_X86_64_CODE_6_GOTTPOFF reloc... " >&6; } +if ${gcc_cv_as_x86_64_code_6_gottpoff+:} false; then : + $as_echo_n "(cached) " >&6 +else + gcc_cv_as_x86_64_code_6_gottpoff=no + if test x$gcc_cv_as != x; then + $as_echo "$conftest_s" > conftest.s + if { ac_try='$gcc_cv_as $gcc_cv_as_flags $as_ix86_gas_64_opt -o conftest.o conftest.s >&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; } + then + if test x$gcc_cv_ld != x && test x$gcc_cv_objdump != x \ + && test x$gcc_cv_readelf != x \ + && $gcc_cv_readelf --relocs --wide conftest.o 2>&1 \ + | grep R_X86_64_CODE_6_GOTTPOFF > /dev/null 2>&1 \ + && $gcc_cv_ld $ld_ix86_gld_64_opt -o conftest conftest.o > /dev/null 2>&1; then + if $gcc_cv_objdump -dw conftest 2>&1 \ + | grep "add \+\$0xf\+8,%r23,%r15" > /dev/null 2>&1; then + gcc_cv_as_x86_64_code_6_gottpoff=yes + else + gcc_cv_as_x86_64_code_6_gottpoff=no + fi + fi + rm -f conftest + else + echo "configure: failed program was" >&5 + cat conftest.s >&5 + fi + rm -f conftest.o conftest.s + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_x86_64_code_6_gottpoff" >&5 +$as_echo "$gcc_cv_as_x86_64_code_6_gottpoff" >&6; } + + + +cat >>confdefs.h <<_ACEOF +#define HAVE_AS_R_X86_64_CODE_6_GOTTPOFF `if test x"$gcc_cv_as_x86_64_code_6_gottpoff" = xyes; then echo 1; else echo 0; fi` +_ACEOF + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for GOTOFF in data" >&5 $as_echo_n "checking assembler for GOTOFF in data... " >&6; } if ${gcc_cv_as_ix86_gotoff_in_data+:} false; then : diff --git a/gcc/configure.ac b/gcc/configure.ac index 9ebc578..a5aec1b 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -5057,6 +5057,50 @@ _start: [`if test x"$gcc_cv_as_ix86_got32x" = xyes; then echo 1; else echo 0; fi`], [Define 0/1 if your assembler and linker support @GOT.]) + # Check if gas and gld support "addq %r23,foo@GOTTPOFF(%rip), %r15" + # with R_X86_64_CODE_6_GOTTPOFF relocation. + if echo "$ld_ver" | grep GNU > /dev/null; then + if $gcc_cv_ld -V 2>/dev/null | grep elf_x86_64_sol2 > /dev/null; then + ld_ix86_gld_64_opt="-melf_x86_64_sol2" + else + ld_ix86_gld_64_opt="-melf_x86_64" + fi + fi + # Enforce 64-bit output with gas and gld. + if test x$gas = xyes; then + as_ix86_gas_64_opt="--64" + fi + conftest_s=' + .text + .globl _start + .type _start, @function +_start: + addq %r23,foo@GOTTPOFF(%rip), %r15 + .section .tdata,"awT",@progbits + .type foo, @object +foo: + .quad 0' + gcc_GAS_CHECK_FEATURE([R_X86_64_CODE_6_GOTTPOFF reloc], + gcc_cv_as_x86_64_code_6_gottpoff, + [$as_ix86_gas_64_opt], + [$conftest_s], + [if test x$gcc_cv_ld != x && test x$gcc_cv_objdump != x \ + && test x$gcc_cv_readelf != x \ + && $gcc_cv_readelf --relocs --wide conftest.o 2>&1 \ + | grep R_X86_64_CODE_6_GOTTPOFF > /dev/null 2>&1 \ + && $gcc_cv_ld $ld_ix86_gld_64_opt -o conftest conftest.o > /dev/null 2>&1; then + if $gcc_cv_objdump -dw conftest 2>&1 \ + | grep "add \+\$0xf\+8,%r23,%r15" > /dev/null 2>&1; then + gcc_cv_as_x86_64_code_6_gottpoff=yes + else + gcc_cv_as_x86_64_code_6_gottpoff=no + fi + fi + rm -f conftest]) + AC_DEFINE_UNQUOTED(HAVE_AS_R_X86_64_CODE_6_GOTTPOFF, + [`if test x"$gcc_cv_as_x86_64_code_6_gottpoff" = xyes; then echo 1; else echo 0; fi`], + [Define 0/1 if your assembler and linker support R_X86_64_CODE_6_GOTTPOFF.]) + gcc_GAS_CHECK_FEATURE([GOTOFF in data], gcc_cv_as_ix86_gotoff_in_data, [$as_ix86_gas_32_opt], diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd-tls-1b.c b/gcc/testsuite/gcc.target/i386/apx-ndd-tls-1b.c new file mode 100644 index 0000000..a3eb810 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-ndd-tls-1b.c @@ -0,0 +1,9 @@ +/* PR target/113733 */ +/* { dg-do assemble { target { apxf && { ! ia32 } } } } */ +/* { dg-require-effective-target tls } */ +/* { dg-require-effective-target code_6_gottpoff_reloc } */ +/* { dg-options "-save-temps -mapxf -O3 -w" } */ + +#include "apx-ndd-tls-1a.c" + +/* { dg-final { scan-assembler-times "addq\[ \t]+%r\[a-z0-9\]+, a@gottpoff\\(%rip\\), %r\[a-z0-9\]+" 1 { target lp64 } } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index ded6ab9..4138cc9 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -12191,6 +12191,54 @@ proc check_effective_target_pie_copyreloc { } { }] } +# Return 1 if the x86-64 target supports R_X86_64_CODE_6_GOTTPOFF +# relocation, 0 otherwise. Cache the result. + +proc check_effective_target_code_6_gottpoff_reloc { } { + global tool + global GCC_UNDER_TEST + + if { !([istarget i?86-*-*] || [istarget x86_64-*-*]) } { + return 0 + } + + # Need auto-host.h to check linker support. + if { ![file exists ../../auto-host.h ] } { + return 0 + } + + return [check_cached_effective_target code_6_gottpoff_reloc { + # Include the current process ID in the file names to prevent + # conflicts with invocations for multiple testsuites. + + set src code_6_gottpoff[pid].c + set obj code_6_gottpoff[pid].o + + set f [open $src "w"] + puts $f "#include \"../../auto-host.h\"" + puts $f "#if HAVE_AS_R_X86_64_CODE_6_GOTTPOFF == 0" + puts $f "# error Assembler does not support R_X86_64_CODE_6_GOTTPOFF." + puts $f "#endif" + close $f + + verbose "check_effective_target_code_6_gottpoff_reloc compiling testfile $src" 2 + set lines [${tool}_target_compile $src $obj object ""] + + file delete $src + file delete $obj + + if [string match "" $lines] then { + verbose "check_effective_target_code_6_gottpoff_reloc testfile compilation passed" 2 + return 1 + } else { + verbose "check_effective_target_code_6_gottpoff_reloc testfile compilation failed" 2 + return 0 + } + }] + + return $code_6_gottpoff_reloc_available_saved +} + # Return 1 if the x86 target supports R_386_GOT32X relocation, 0 # otherwise. Cache the result. -- cgit v1.1 From 8a16e06da97f51574cfad17e2cece2e58571305d Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Fri, 23 Feb 2024 14:12:54 +0000 Subject: aarch64: Add missing early-ra bookkeeping [PR113295] 416.gamess showed up two wrong-code bugs in early-ra. This patch fixes the first of them. It was difficult to reduce the source code to something that would meaningfully show the situation, so the testcase uses a direct RTL sequence instead. In the sequence: (a) register <2> is set more than once (b) register <2> is copied to a temporary (<4>) (c) register <2> is the destination of an FCSEL between <4> and another value (<5>) (d) <4> and <2> are equivalent for <4>'s live range (e) <5>'s and <2>'s live ranges do not intersect, and there is a pseudo-copy between <5> and <2> On its own, (d) implies that <4> can be treated as equivalent to <2>. And on its own, (e) implies that <5> can share <2>'s register. But <4>'s and <5>'s live ranges conflict, meaning that they cannot both share the register together. A bit of missing bookkeeping meant that the mechanism for detecting this didn't fire. We therefore ended up with an FCSEL in which both inputs were the same register. gcc/ PR target/113295 * config/aarch64/aarch64-early-ra.cc (early_ra::find_related_start): Account for definitions by shared registers when testing for a single register definition. (early_ra::accumulate_defs): New function. (early_ra::record_copy): If A shares B's register, fold A's definition information into B's. Fold A's use information into B's. gcc/testsuite/ PR target/113295 * gcc.dg/rtl/aarch64/pr113295-1.c: New test. --- gcc/config/aarch64/aarch64-early-ra.cc | 27 ++++++++++++++ gcc/testsuite/gcc.dg/rtl/aarch64/pr113295-1.c | 53 +++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/rtl/aarch64/pr113295-1.c (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-early-ra.cc b/gcc/config/aarch64/aarch64-early-ra.cc index 1a03d86..58ae5a4 100644 --- a/gcc/config/aarch64/aarch64-early-ra.cc +++ b/gcc/config/aarch64/aarch64-early-ra.cc @@ -440,6 +440,7 @@ private: void record_allocno_use (allocno_info *); void record_allocno_def (allocno_info *); allocno_info *find_related_start (allocno_info *, allocno_info *, bool); + void accumulate_defs (allocno_info *, allocno_info *); void record_copy (rtx, rtx, bool = false); void record_constraints (rtx_insn *); void record_artificial_refs (unsigned int); @@ -1569,6 +1570,8 @@ early_ra::find_related_start (allocno_info *dest_allocno, } if (dest_allocno->group_size != 1 + // Account for definitions by shared registers. + || dest_allocno->num_defs > 1 || DF_REG_DEF_COUNT (dest_allocno->group ()->regno) != 1) // Currently only single allocnos that are defined once can // share registers with non-equivalent allocnos. This could be @@ -1593,6 +1596,20 @@ early_ra::find_related_start (allocno_info *dest_allocno, } } +// Add FROM_ALLOCNO's definition information to TO_ALLOCNO's. +void +early_ra::accumulate_defs (allocno_info *to_allocno, + allocno_info *from_allocno) +{ + if (from_allocno->num_defs > 0) + { + to_allocno->num_defs = MIN (from_allocno->num_defs + + to_allocno->num_defs, 2); + to_allocno->last_def_point = MAX (to_allocno->last_def_point, + from_allocno->last_def_point); + } +} + // Record any relevant allocno-related information for an actual or imagined // copy from SRC to DEST. FROM_MOVE_P is true if the copy was an explicit // move instruction, false if it represents one way of satisfying the previous @@ -1687,6 +1704,16 @@ early_ra::record_copy (rtx dest, rtx src, bool from_move_p) next_allocno->related_allocno = src_allocno->id; next_allocno->is_equiv = (start_allocno == dest_allocno && from_move_p); + // If we're sharing two allocnos that are not equivalent, + // carry across the definition information. This is needed + // to prevent multiple incompatible attempts to share with + // the same register. + if (next_allocno->is_shared ()) + accumulate_defs (src_allocno, next_allocno); + src_allocno->last_use_point + = MAX (src_allocno->last_use_point, + next_allocno->last_use_point); + if (next_allocno == start_allocno) break; next_allocno = m_allocnos[next_allocno->copy_dest]; diff --git a/gcc/testsuite/gcc.dg/rtl/aarch64/pr113295-1.c b/gcc/testsuite/gcc.dg/rtl/aarch64/pr113295-1.c new file mode 100644 index 0000000..481fb81 --- /dev/null +++ b/gcc/testsuite/gcc.dg/rtl/aarch64/pr113295-1.c @@ -0,0 +1,53 @@ +// { dg-options "-O2" } +// { dg-do run } + +struct data { + double x; + double y; + long long cond; + double res; +}; + +void __RTL (startwith ("early_ra")) foo (struct data *ptr) +{ + (function "foo" + (param "ptr" + (DECL_RTL (reg/v:DI <0> [ ptr ])) + (DECL_RTL_INCOMING (reg/v:DI x0 [ ptr ])) + ) ;; param "ptr" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 3 [bb 2] NOTE_INSN_BASIC_BLOCK) + (insn 4 (set (reg:DI <0>) (reg:DI x0))) + (insn 5 (set (reg:DF <1>) (mem:DF (reg:DI <0>) [1 S8 A8]))) + (insn 6 (set (reg:DF <2>) (mem:DF (plus:DI (reg:DI <0>) + (const_int 8)) [1 S8 A8]))) + (insn 7 (set (reg:DI <3>) (mem:DI (plus:DI (reg:DI <0>) + (const_int 16)) [1 S8 A8]))) + (insn 8 (set (reg:CC cc) (compare:CC (reg:DI <3>) (const_int 0)))) + (insn 9 (set (reg:DF <4>) (reg:DF <2>))) + (insn 10 (set (reg:DF <5>) (plus:DF (reg:DF <1>) (reg:DF <2>)))) + (insn 11 (set (reg:DF <2>) (if_then_else:DF + (ge (reg:CC cc) (const_int 0)) + (reg:DF <4>) + (reg:DF <5>)))) + (insn 12 (set (mem:DF (plus:DI (reg:DI <0>) + (const_int 24)) [1 S8 A8]) + (reg:DF <2>))) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain + ) ;; function +} + +int +main (void) +{ + struct data d1 = { 1, 2, -1, 0 }; + struct data d2 = { 3, 4, 1, 0 }; + foo (&d1); + foo (&d2); + if (d1.res != 3 || d2.res != 4) + __builtin_abort (); +} -- cgit v1.1 From 9f105cfdc1bca6c9224384b3044c4ca5894e1e4c Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Fri, 23 Feb 2024 14:12:55 +0000 Subject: aarch64: Tighten early-ra chain test for wide registers [PR113295] Most code in early-ra used is_chain_candidate to check whether we should chain two allocnos. This included both tests that matter for correctness and tests for certain heuristics. Once that test passes for one pair of allocnos, we test whether it's safe to chain the containing groups (which might contain multiple allocnos for x2, x3 and x4 modes). This test used an inline test for correctness only, deliberately skipping the heuristics. However, this instance of the test was missing some handling of equivalent allocnos. This patch fixes things by making is_chain_candidate take a strictness parameter: correctness only, or correctness + heuristics. It then makes the group-chaining test use the correctness version rather than trying to replicate it inline. gcc/ PR target/113295 * config/aarch64/aarch64-early-ra.cc (early_ra::test_strictness): New enum. (early_ra::is_chain_candidate): Add a strictness parameter to control whether only correctness matters, or whether both correctness and heuristics should be used. Handle multiple levels of equivalence. (early_ra::find_related_start): Update call accordingly. (early_ra::strided_polarity_pref): Likewise. (early_ra::form_chains): Likewise. (early_ra::try_to_chain_allocnos): Use is_chain_candidate in correctness mode rather than trying to inline the test. gcc/testsuite/ PR target/113295 * gcc.target/aarch64/pr113295-2.c: New test. --- gcc/config/aarch64/aarch64-early-ra.cc | 48 +++++++++++----------- gcc/testsuite/gcc.target/aarch64/pr113295-2.c | 57 +++++++++++++++++++++++++++ 2 files changed, 82 insertions(+), 23 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr113295-2.c (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-early-ra.cc b/gcc/config/aarch64/aarch64-early-ra.cc index 58ae5a4..9ac9ec1 100644 --- a/gcc/config/aarch64/aarch64-early-ra.cc +++ b/gcc/config/aarch64/aarch64-early-ra.cc @@ -95,6 +95,10 @@ public: void execute (); private: + // Whether to test only things that are required for correctness, + // or whether to take optimization heuristics into account as well. + enum test_strictness { CORRECTNESS_ONLY, ALL_REASONS }; + static_assert (MAX_RECOG_OPERANDS <= 32, "Operand mask is 32 bits"); using operand_mask = uint32_t; @@ -452,7 +456,7 @@ private: template static int cmp_increasing (const void *, const void *); - bool is_chain_candidate (allocno_info *, allocno_info *); + bool is_chain_candidate (allocno_info *, allocno_info *, test_strictness); int rate_chain (allocno_info *, allocno_info *); static int cmp_chain_candidates (const void *, const void *); void chain_allocnos (unsigned int &, unsigned int &); @@ -1588,7 +1592,7 @@ early_ra::find_related_start (allocno_info *dest_allocno, return res; auto *next_allocno = m_allocnos[dest_allocno->copy_dest]; - if (!is_chain_candidate (dest_allocno, next_allocno)) + if (!is_chain_candidate (dest_allocno, next_allocno, ALL_REASONS)) return res; dest_allocno = next_allocno; @@ -2011,7 +2015,7 @@ early_ra::strided_polarity_pref (allocno_info *allocno1, if (allocno1->offset + 1 < allocno1->group_size && allocno2->offset + 1 < allocno2->group_size) { - if (is_chain_candidate (allocno1 + 1, allocno2 + 1)) + if (is_chain_candidate (allocno1 + 1, allocno2 + 1, ALL_REASONS)) return 1; else return -1; @@ -2019,7 +2023,7 @@ early_ra::strided_polarity_pref (allocno_info *allocno1, if (allocno1->offset > 0 && allocno2->offset > 0) { - if (is_chain_candidate (allocno1 - 1, allocno2 - 1)) + if (is_chain_candidate (allocno1 - 1, allocno2 - 1, ALL_REASONS)) return 1; else return -1; @@ -2215,38 +2219,37 @@ early_ra::cmp_increasing (const void *allocno1_ptr, const void *allocno2_ptr) } // Return true if we should consider chaining ALLOCNO1 onto the head -// of ALLOCNO2. This is just a local test of the two allocnos; it doesn't -// guarantee that chaining them would give a self-consistent system. +// of ALLOCNO2. STRICTNESS says whether we should take copy-elision +// heuristics into account, or whether we should just consider things +// that matter for correctness. +// +// This is just a local test of the two allocnos; it doesn't guarantee +// that chaining them would give a self-consistent system. bool -early_ra::is_chain_candidate (allocno_info *allocno1, allocno_info *allocno2) +early_ra::is_chain_candidate (allocno_info *allocno1, allocno_info *allocno2, + test_strictness strictness) { if (allocno2->is_shared ()) return false; - if (allocno1->is_equiv) + while (allocno1->is_equiv) allocno1 = m_allocnos[allocno1->related_allocno]; if (allocno2->start_point >= allocno1->end_point && !allocno2->is_equiv_to (allocno1->id)) return false; - if (allocno2->is_strong_copy_dest) - { - if (!allocno1->is_strong_copy_src - || allocno1->copy_dest != allocno2->id) - return false; - } - else if (allocno2->is_copy_dest) + if (allocno1->is_earlyclobbered + && allocno1->end_point == allocno2->start_point + 1) + return false; + + if (strictness == ALL_REASONS && allocno2->is_copy_dest) { if (allocno1->copy_dest != allocno2->id) return false; - } - else if (allocno1->is_earlyclobbered) - { - if (allocno1->end_point == allocno2->start_point + 1) + if (allocno2->is_strong_copy_dest && !allocno1->is_strong_copy_src) return false; } - return true; } @@ -2470,8 +2473,7 @@ early_ra::try_to_chain_allocnos (allocno_info *allocno1, auto *head2 = m_allocnos[headi2]; if (head1->chain_next != INVALID_ALLOCNO) return false; - if (!head2->is_equiv_to (head1->id) - && head1->end_point <= head2->start_point) + if (!is_chain_candidate (head1, head2, CORRECTNESS_ONLY)) return false; } } @@ -2620,7 +2622,7 @@ early_ra::form_chains () auto *allocno2 = m_sorted_allocnos[sci]; if (allocno2->chain_prev == INVALID_ALLOCNO) { - if (!is_chain_candidate (allocno1, allocno2)) + if (!is_chain_candidate (allocno1, allocno2, ALL_REASONS)) continue; chain_candidate_info candidate; candidate.allocno = allocno2; diff --git a/gcc/testsuite/gcc.target/aarch64/pr113295-2.c b/gcc/testsuite/gcc.target/aarch64/pr113295-2.c new file mode 100644 index 0000000..6fa29bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr113295-2.c @@ -0,0 +1,57 @@ +// { dg-do run } +// { dg-options "-O2" } + +#include + +void __attribute__ ((noinline)) +foo (int8_t **ptr) +{ + int8x16_t v0 = vld1q_s8 (ptr[0]); + int8x16_t v1 = vld1q_s8 (ptr[1]); + int8x16_t v2 = vld1q_s8 (ptr[2]); + int8x16_t v3 = vld1q_s8 (ptr[3]); + int8x16_t v4 = vld1q_s8 (ptr[4]); + + int8x16x4_t res0 = { v0, v1, v2, v3 }; + vst4q_s8 (ptr[5], res0); + + int8x16_t add = vaddq_s8 (v2, v3); + int8x16x3_t res1 = { v1, add, v3 }; + vst3q_s8 (ptr[6], res1); + + int8x16x3_t res2 = { v0, v1, v2 }; + vst3q_s8 (ptr[7], res2); +} + +int8_t arr0[16] = { 1 }; +int8_t arr1[16] = { 2 }; +int8_t arr2[16] = { 4 }; +int8_t arr3[16] = { 8 }; +int8_t arr4[16] = { 16 }; +int8_t arr5[16 * 4]; +int8_t arr6[16 * 3]; +int8_t arr7[16 * 3]; +int8_t *ptr[] = +{ + arr0, + arr1, + arr2, + arr3, + arr4, + arr5, + arr6, + arr7 +}; + +int +main (void) +{ + foo (ptr); + if (arr5[0] != 1 || arr5[1] != 2 || arr5[2] != 4 || arr5[3] != 8) + __builtin_abort (); + if (arr6[0] != 2 || arr6[1] != 12 || arr6[2] != 8) + __builtin_abort (); + if (arr7[0] != 1 || arr7[1] != 2 || arr7[2] != 4) + __builtin_abort (); + return 0; +} -- cgit v1.1 From ff442719cdb64c9df9d069af88e90d51bee6fb56 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Fri, 23 Feb 2024 14:12:55 +0000 Subject: aarch64: Spread out FPR usage between RA regions [PR113613] early-ra already had code to do regrename-style "broadening" of the allocation, to promote scheduling freedom. However, the pass divides the function into allocation regions and this broadening only worked within a single region. This meant that if a basic block contained one subblock of FPR use, followed by a point at which no FPRs were live, followed by another subblock of FPR use, the two subblocks would tend to reuse the same registers. This in turn meant that it wasn't possible to form LDP/STP pairs between them. The failure to form LDPs and STPs in the testcase was a regression from GCC 13. The patch adds a simple heuristic to prefer less recently used registers in the event of a tie. gcc/ PR target/113613 * config/aarch64/aarch64-early-ra.cc (early_ra::m_current_region): New member variable. (early_ra::m_fpr_recency): Likewise. (early_ra::start_new_region): Bump m_current_region. (early_ra::allocate_colors): Prefer less recently used registers in the event of a tie. Add a comment to explain why we prefer(ed) higher-numbered registers. (early_ra::find_oldest_color): Prefer less recently used registers here too. (early_ra::finalize_allocation): Update recency information for allocated registers. (early_ra::process_blocks): Initialize m_current_region and m_fpr_recency. gcc/testsuite/ PR target/113613 * gcc.target/aarch64/pr113613.c: New test. --- gcc/config/aarch64/aarch64-early-ra.cc | 55 ++++++++++++++++++++++++----- gcc/testsuite/gcc.target/aarch64/pr113613.c | 13 +++++++ 2 files changed, 59 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr113613.c (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-early-ra.cc b/gcc/config/aarch64/aarch64-early-ra.cc index 9ac9ec1..8530b0a 100644 --- a/gcc/config/aarch64/aarch64-early-ra.cc +++ b/gcc/config/aarch64/aarch64-early-ra.cc @@ -532,6 +532,12 @@ private: // The set of FPRs that are currently live. unsigned int m_live_fprs; + // A unique one-based identifier for the current region. + unsigned int m_current_region; + + // The region in which each FPR was last used, or 0 if none. + unsigned int m_fpr_recency[32]; + // ---------------------------------------------------------------------- // A mask of the FPRs that have already been allocated. @@ -1305,6 +1311,7 @@ early_ra::start_new_region () m_allocated_fprs = 0; m_call_preserved_fprs = 0; m_allocation_successful = true; + m_current_region += 1; } // Create and return an allocno group of size SIZE for register REGNO. @@ -2819,19 +2826,30 @@ early_ra::allocate_colors () candidates &= ~(m_allocated_fprs >> i); unsigned int best = INVALID_REGNUM; int best_weight = 0; + unsigned int best_recency = 0; for (unsigned int fpr = 0; fpr <= 32U - color->group->size; ++fpr) { if ((candidates & (1U << fpr)) == 0) continue; int weight = color->fpr_preferences[fpr]; + unsigned int recency = 0; // Account for registers that the current function must preserve. for (unsigned int i = 0; i < color->group->size; ++i) - if (m_call_preserved_fprs & (1U << (fpr + i))) - weight -= 1; - if (best == INVALID_REGNUM || best_weight <= weight) + { + if (m_call_preserved_fprs & (1U << (fpr + i))) + weight -= 1; + recency = MAX (recency, m_fpr_recency[fpr + i]); + } + // Prefer higher-numbered registers in the event of a tie. + // This should tend to keep lower-numbered registers free + // for allocnos that require V0-V7 or V0-V15. + if (best == INVALID_REGNUM + || best_weight < weight + || (best_weight == weight && recency <= best_recency)) { best = fpr; best_weight = weight; + best_recency = recency; } } @@ -2888,19 +2906,27 @@ early_ra::find_oldest_color (unsigned int first_color, { color_info *best = nullptr; unsigned int best_start_point = ~0U; + unsigned int best_recency = 0; for (unsigned int ci = first_color; ci < m_colors.length (); ++ci) { auto *color = m_colors[ci]; - if (fpr_conflicts & (1U << (color->hard_regno - V0_REGNUM))) + unsigned int fpr = color->hard_regno - V0_REGNUM; + if (fpr_conflicts & (1U << fpr)) continue; - if (!color->group) - return color; - auto chain_head = color->group->chain_heads ()[0]; - auto start_point = m_allocnos[chain_head]->start_point; - if (!best || best_start_point > start_point) + unsigned int start_point = 0; + if (color->group) + { + auto chain_head = color->group->chain_heads ()[0]; + start_point = m_allocnos[chain_head]->start_point; + } + unsigned int recency = m_fpr_recency[fpr]; + if (!best + || best_start_point > start_point + || (best_start_point == start_point && recency < best_recency)) { best = color; best_start_point = start_point; + best_recency = recency; } } return best; @@ -3004,6 +3030,13 @@ early_ra::broaden_colors () void early_ra::finalize_allocation () { + for (auto *color : m_colors) + if (color->group) + { + unsigned int fpr = color->hard_regno - V0_REGNUM; + for (unsigned int i = 0; i < color->group->size; ++i) + m_fpr_recency[fpr + i] = m_current_region; + } for (auto *allocno : m_allocnos) { if (allocno->is_shared ()) @@ -3521,6 +3554,10 @@ early_ra::process_blocks () bitmap_set_bit (fpr_pseudos_live_in, bb->index); } + // This is incremented by 1 at the start of each region. + m_current_region = 0; + memset (m_fpr_recency, 0, sizeof (m_fpr_recency)); + struct stack_node { edge_iterator ei; basic_block bb; }; auto_vec stack; diff --git a/gcc/testsuite/gcc.target/aarch64/pr113613.c b/gcc/testsuite/gcc.target/aarch64/pr113613.c new file mode 100644 index 0000000..382e4a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr113613.c @@ -0,0 +1,13 @@ +// { dg-options "-O2" } + +typedef float __attribute__((vector_size(8))) v2sf; +v2sf a[4]; +v2sf b[4]; +void f() +{ + b[0] += a[0]; + b[1] += a[1]; +} + +// { dg-final { scan-assembler-times {\tldp\t} 2 } } +// { dg-final { scan-assembler-times {\tstp\t} 1 } } -- cgit v1.1 From fdf9df9d55802e1d8ff0bd14585ea61b2bb9d798 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 23 Feb 2024 18:55:12 +0100 Subject: c++: Fix ICE due to folding a call to constructor on cdtor_returns_this arches (aka arm32) [PR113083] When targetm.cxx.cdtor_returns_this () (aka on arm32 TARGET_AAPCS_BASED) constructor is supposed to return this pointer, but when we cp_fold such a call, we don't take that into account and just INIT_EXPR the object, so we can later ICE during gimplification, because the expression doesn't have the right type. 2024-02-23 Jakub Jelinek PR c++/113083 * cp-gimplify.cc (cp_fold): For targetm.cxx.cdtor_returns_this () wrap r into a COMPOUND_EXPR and return folded CALL_EXPR_ARG (x, 0). * g++.dg/cpp0x/constexpr-113083.C: New test. --- gcc/cp/cp-gimplify.cc | 10 ++++++++-- gcc/testsuite/g++.dg/cpp0x/constexpr-113083.C | 16 ++++++++++++++++ 2 files changed, 24 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-113083.C (limited to 'gcc') diff --git a/gcc/cp/cp-gimplify.cc b/gcc/cp/cp-gimplify.cc index 30e9479..f3baae6 100644 --- a/gcc/cp/cp-gimplify.cc +++ b/gcc/cp/cp-gimplify.cc @@ -3412,9 +3412,15 @@ cp_fold (tree x, fold_flags_t flags) if (DECL_CONSTRUCTOR_P (callee)) { loc = EXPR_LOCATION (x); - tree s = build_fold_indirect_ref_loc (loc, - CALL_EXPR_ARG (x, 0)); + tree a = CALL_EXPR_ARG (x, 0); + bool return_this = targetm.cxx.cdtor_returns_this (); + if (return_this) + a = cp_save_expr (a); + tree s = build_fold_indirect_ref_loc (loc, a); r = cp_build_init_expr (s, r); + if (return_this) + r = build2_loc (loc, COMPOUND_EXPR, TREE_TYPE (x), r, + fold_convert_loc (loc, TREE_TYPE (x), a)); } x = r; break; diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-113083.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-113083.C new file mode 100644 index 0000000..3829ac5 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-113083.C @@ -0,0 +1,16 @@ +// PR c++/113083 +// { dg-do compile { target c++11 } } +// { dg-options "-Os" } + +struct A { constexpr A (); }; + +void +foo () +{ + A b; +} + +constexpr +A::A () +{ +} -- cgit v1.1 From 85c12ae8b80902ed46c97f33dbb61533e07f2905 Mon Sep 17 00:00:00 2001 From: Robin Dapp Date: Thu, 22 Feb 2024 13:40:55 +0100 Subject: RISC-V: Fix vec_init for simple sequences [PR114028]. For a vec_init (_a, _a, _a, _a) with _a of mode DImode we try to construct a "superword" of two "_a"s. This only works for modes < Pmode when we can "shift and or" both halves into one Pmode register. This patch disallows the optimization for inner_mode == Pmode and emits a simple broadcast in such a case. gcc/ChangeLog: PR target/114028 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p): Return false if inner mode is already Pmode. (rvv_builder::is_all_same_sequence): New function. (expand_vec_init): Emit broadcast if sequence is all same. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr114028.c: New test. --- gcc/config/riscv/riscv-v.cc | 25 +++++++++++++++++++++- .../gcc.target/riscv/rvv/autovec/pr114028.c | 25 ++++++++++++++++++++++ 2 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114028.c (limited to 'gcc') diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 0cfbd21..29d58de 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -443,6 +443,7 @@ public: } bool can_duplicate_repeating_sequence_p (); + bool is_repeating_sequence (); rtx get_merged_repeating_sequence (); bool repeating_sequence_use_merge_profitable_p (); @@ -483,7 +484,8 @@ rvv_builder::can_duplicate_repeating_sequence_p () { poly_uint64 new_size = exact_div (full_nelts (), npatterns ()); unsigned int new_inner_size = m_inner_bits_size * npatterns (); - if (!int_mode_for_size (new_inner_size, 0).exists (&m_new_inner_mode) + if (m_inner_mode == Pmode + || !int_mode_for_size (new_inner_size, 0).exists (&m_new_inner_mode) || GET_MODE_SIZE (m_new_inner_mode) > UNITS_PER_WORD || !get_vector_mode (m_new_inner_mode, new_size).exists (&m_new_mode)) return false; @@ -492,6 +494,18 @@ rvv_builder::can_duplicate_repeating_sequence_p () return nelts_per_pattern () == 1; } +/* Return true if the vector is a simple sequence with one pattern and all + elements the same. */ +bool +rvv_builder::is_repeating_sequence () +{ + if (npatterns () > 1) + return false; + if (full_nelts ().is_constant ()) + return repeating_sequence_p (0, full_nelts ().to_constant (), 1); + return nelts_per_pattern () == 1; +} + /* Return true if it is a repeating sequence that using merge approach has better codegen than using default approach (slide1down). @@ -2544,6 +2558,15 @@ expand_vec_init (rtx target, rtx vals) v.quick_push (XVECEXP (vals, 0, i)); v.finalize (); + /* If the sequence is v = { a, a, a, a } just broadcast an element. */ + if (v.is_repeating_sequence ()) + { + machine_mode mode = GET_MODE (target); + rtx dup = expand_vector_broadcast (mode, v.elt (0)); + emit_move_insn (target, dup); + return; + } + if (nelts > 3) { /* Case 1: Convert v = { a, b, a, b } into v = { ab, ab }. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114028.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114028.c new file mode 100644 index 0000000..e41f272 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114028.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */ + +int a, d = 55003; +long c = 0, h; +long e = 1; +short i; + +int +main () +{ + for (int g = 0; g < 16; g++) + { + d |= c; + short l = d; + i = l < 0 || a >> 4 ? d : a; + h = i - 8L; + e &= h; + } + + if (e != 1) + __builtin_abort (); +} + +/* { dg-final { scan-assembler-not "vmv\.v\.i\tv\[0-9\],0" } } */ -- cgit v1.1 From 80d126ba99f4b9bc64d4861b3c4bae666497f2d4 Mon Sep 17 00:00:00 2001 From: Steve Kargl Date: Fri, 23 Feb 2024 22:05:04 +0100 Subject: Fortran: ALLOCATE statement, SOURCE/MOLD expressions with subrefs [PR114024] PR fortran/114024 gcc/fortran/ChangeLog: * trans-stmt.cc (gfc_trans_allocate): When a source expression has substring references, part-refs, or %re/%im inquiries, wrap the entity in parentheses to force evaluation of the expression. gcc/testsuite/ChangeLog: * gfortran.dg/allocate_with_source_27.f90: New test. * gfortran.dg/allocate_with_source_28.f90: New test. Co-Authored-By: Harald Anlauf --- gcc/fortran/trans-stmt.cc | 10 ++- .../gfortran.dg/allocate_with_source_27.f90 | 20 +++++ .../gfortran.dg/allocate_with_source_28.f90 | 90 ++++++++++++++++++++++ 3 files changed, 118 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/allocate_with_source_27.f90 create mode 100644 gcc/testsuite/gfortran.dg/allocate_with_source_28.f90 (limited to 'gcc') diff --git a/gcc/fortran/trans-stmt.cc b/gcc/fortran/trans-stmt.cc index 5247d3d..e09828e 100644 --- a/gcc/fortran/trans-stmt.cc +++ b/gcc/fortran/trans-stmt.cc @@ -6355,8 +6355,14 @@ gfc_trans_allocate (gfc_code * code, gfc_omp_namelist *omp_allocate) vtab_needed = (al->expr->ts.type == BT_CLASS); gfc_init_se (&se, NULL); - /* When expr3 is a variable, i.e., a very simple expression, - then convert it once here. */ + /* When expr3 is a variable, i.e., a very simple expression, then + convert it once here. If one has a source expression that has + substring references, part-refs, or %re/%im inquiries, wrap the + entity in parentheses to force evaluation of the expression. */ + if (code->expr3->expr_type == EXPR_VARIABLE + && is_subref_array (code->expr3)) + code->expr3 = gfc_get_parentheses (code->expr3); + if (code->expr3->expr_type == EXPR_VARIABLE || code->expr3->expr_type == EXPR_ARRAY || code->expr3->expr_type == EXPR_CONSTANT) diff --git a/gcc/testsuite/gfortran.dg/allocate_with_source_27.f90 b/gcc/testsuite/gfortran.dg/allocate_with_source_27.f90 new file mode 100644 index 0000000..d0f0f3c --- /dev/null +++ b/gcc/testsuite/gfortran.dg/allocate_with_source_27.f90 @@ -0,0 +1,20 @@ +! +! { dg-do run } +! +! fortran/PR114024 +! https://github.com/fujitsu/compiler-test-suite +! Modified from Fortran/0093/0093_0130.f90 +! +program foo + implicit none + complex :: cmp(3) + real, allocatable :: xx(:), yy(:), zz(:) + cmp = (3., 6.78) + allocate(xx, source = cmp%re) ! This caused an ICE. + allocate(yy, source = cmp(1:3)%re) ! This caused an ICE. + allocate(zz, source = (cmp%re)) + if (any(xx /= [3., 3., 3.])) stop 1 + if (any(yy /= [3., 3., 3.])) stop 2 + if (any(zz /= [3., 3., 3.])) stop 3 +end program foo + diff --git a/gcc/testsuite/gfortran.dg/allocate_with_source_28.f90 b/gcc/testsuite/gfortran.dg/allocate_with_source_28.f90 new file mode 100644 index 0000000..8548ccb --- /dev/null +++ b/gcc/testsuite/gfortran.dg/allocate_with_source_28.f90 @@ -0,0 +1,90 @@ +! { dg-do run } +! +! PR fortran/114024 + +program foo + implicit none + complex :: cmp(3) = (3.,4.) + type ci ! pseudo "complex integer" type + integer :: re + integer :: im + end type ci + type cr ! pseudo "complex" type + real :: re + real :: im + end type cr + type u + type(ci) :: ii(3) + type(cr) :: rr(3) + end type u + type(u) :: cc + + cc% ii% re = nint (cmp% re) + cc% ii% im = nint (cmp% im) + cc% rr% re = cmp% re + cc% rr% im = cmp% im + + call test_substring () + call test_int_real () + call test_poly () + +contains + + subroutine test_substring () + character(4) :: str(3) = ["abcd","efgh","ijkl"] + character(:), allocatable :: ac(:) + allocate (ac, source=str(1::2)(2:4)) + if (size (ac) /= 2 .or. len (ac) /= 3) stop 11 + if (ac(2) /= "jkl") stop 12 + deallocate (ac) + allocate (ac, mold=str(1::2)(2:4)) + if (size (ac) /= 2 .or. len (ac) /= 3) stop 13 + deallocate (ac) + end + + subroutine test_int_real () + integer, allocatable :: aa(:) + real, pointer :: pp(:) + allocate (aa, source = cc% ii% im) + if (size (aa) /= 3) stop 21 + if (any (aa /= cmp% im)) stop 22 + allocate (pp, source = cc% rr% re) + if (size (pp) /= 3) stop 23 + if (any (pp /= cmp% re)) stop 24 + deallocate (aa, pp) + end + + subroutine test_poly () + class(*), allocatable :: uu(:), vv(:) + allocate (uu, source = cc% ii% im) + allocate (vv, source = cc% rr% re) + if (size (uu) /= 3) stop 31 + if (size (vv) /= 3) stop 32 + call check (uu) + call check (vv) + deallocate (uu, vv) + allocate (uu, mold = cc% ii% im) + allocate (vv, mold = cc% rr% re) + if (size (uu) /= 3) stop 33 + if (size (vv) /= 3) stop 34 + deallocate (uu, vv) + end + + subroutine check (x) + class(*), intent(in) :: x(:) + select type (x) + type is (integer) + if (any (x /= cmp% im)) then + print *, "'integer':", x + stop 41 + end if + type is (real) + if (any (x /= cmp% re)) then + print *, "'real':", x + stop 42 + end if + type is (character(*)) + print *, "'character':", x + end select + end +end -- cgit v1.1 From 4d9da4199d1cc067a43c29a40d4f4b17ac10319c Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sat, 24 Feb 2024 00:17:42 +0000 Subject: Daily bump. --- gcc/ChangeLog | 100 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog | 6 +++ gcc/fortran/ChangeLog | 13 +++++++ gcc/testsuite/ChangeLog | 63 ++++++++++++++++++++++++++++++ 5 files changed, 183 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cafa866..3af0b7e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,103 @@ +2024-02-23 Robin Dapp + + PR target/114028 + * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p): + Return false if inner mode is already Pmode. + (rvv_builder::is_all_same_sequence): New function. + (expand_vec_init): Emit broadcast if sequence is all same. + +2024-02-23 Richard Sandiford + + PR target/113613 + * config/aarch64/aarch64-early-ra.cc + (early_ra::m_current_region): New member variable. + (early_ra::m_fpr_recency): Likewise. + (early_ra::start_new_region): Bump m_current_region. + (early_ra::allocate_colors): Prefer less recently used registers + in the event of a tie. Add a comment to explain why we prefer(ed) + higher-numbered registers. + (early_ra::find_oldest_color): Prefer less recently used registers + here too. + (early_ra::finalize_allocation): Update recency information for + allocated registers. + (early_ra::process_blocks): Initialize m_current_region and + m_fpr_recency. + +2024-02-23 Richard Sandiford + + PR target/113295 + * config/aarch64/aarch64-early-ra.cc + (early_ra::test_strictness): New enum. + (early_ra::is_chain_candidate): Add a strictness parameter to + control whether only correctness matters, or whether both correctness + and heuristics should be used. Handle multiple levels of equivalence. + (early_ra::find_related_start): Update call accordingly. + (early_ra::strided_polarity_pref): Likewise. + (early_ra::form_chains): Likewise. + (early_ra::try_to_chain_allocnos): Use is_chain_candidate in + correctness mode rather than trying to inline the test. + +2024-02-23 Richard Sandiford + + PR target/113295 + * config/aarch64/aarch64-early-ra.cc + (early_ra::find_related_start): Account for definitions by shared + registers when testing for a single register definition. + (early_ra::accumulate_defs): New function. + (early_ra::record_copy): If A shares B's register, fold A's + definition information into B's. Fold A's use information into B's. + +2024-02-23 H.J. Lu + + * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1 + if R_X86_64_CODE_6_GOTTPOFF is supported. + * config.in: Regenerated. + * configure: Likewise. + * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow + UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported. + +2024-02-23 Richard Earnshaw + + PR target/108120 + * config/arm/neon.md (div3): Rename from div3. + Gate with ARM_HAVE_NEON__ARITH. + +2024-02-23 Jakub Jelinek + + PR rtl-optimization/114054 + * expr.cc (expand_expr_real_2) : Use + temp variable instead of target parameter for result. + +2024-02-23 Jakub Jelinek + + PR tree-optimization/114040 + * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow): + Use EQ_EXPR rather than LT_EXPR for g2 condition and change its + probability from likely to unlikely. When handling the true true + store, first cast to limb_access_type and then to l's type. + +2024-02-23 Richard Biener + + PR target/90785 + * config.gcc: Add ia64*-*-* to the list of obsoleted targets. + +2024-02-23 Palmer Dabbelt + + PR other/109668 + * config/riscv/arch-canonicalize: Move to python3 + * config/riscv/multilib-generator: Likewise + +2024-02-23 Palmer Dabbelt + + * doc/invoke.texi: Document -mcpu. + +2024-02-23 Lulu Cheng + + * configure: Regenerate. + * configure.ac: Add parameter "--fatal-warnings" to assemble + when checking whether the assemble support conditional branch + relaxation. + 2024-02-22 Jakub Jelinek PR c/114007 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index bb29f6e..4e5d4ad 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240223 +20240224 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 387e41e..e1a4084 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2024-02-23 Jakub Jelinek + + PR c++/113083 + * cp-gimplify.cc (cp_fold): For targetm.cxx.cdtor_returns_this () + wrap r into a COMPOUND_EXPR and return folded CALL_EXPR_ARG (x, 0). + 2024-02-19 Patrick Palka PR c++/113966 diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index f86cbe3..2a21185 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,16 @@ +2024-02-23 Steve Kargl + Harald Anlauf + + PR fortran/114024 + * trans-stmt.cc (gfc_trans_allocate): When a source expression has + substring references, part-refs, or %re/%im inquiries, wrap the + entity in parentheses to force evaluation of the expression. + +2024-02-23 Tobias Burnus + + * openmp.cc (gfc_match_omp_depobj): Use OPT_Wopenmp + as warning category in gfc_warning. + 2024-02-20 Peter Hill PR fortran/105658 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 61abc60..669978d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,66 @@ +2024-02-23 Steve Kargl + Harald Anlauf + + PR fortran/114024 + * gfortran.dg/allocate_with_source_27.f90: New test. + * gfortran.dg/allocate_with_source_28.f90: New test. + +2024-02-23 Robin Dapp + + * gcc.target/riscv/rvv/autovec/pr114028.c: New test. + +2024-02-23 Jakub Jelinek + + PR c++/113083 + * g++.dg/cpp0x/constexpr-113083.C: New test. + +2024-02-23 Richard Sandiford + + PR target/113613 + * gcc.target/aarch64/pr113613.c: New test. + +2024-02-23 Richard Sandiford + + PR target/113295 + * gcc.target/aarch64/pr113295-2.c: New test. + +2024-02-23 Richard Sandiford + + PR target/113295 + * gcc.dg/rtl/aarch64/pr113295-1.c: New test. + +2024-02-23 H.J. Lu + + * gcc.target/i386/apx-ndd-tls-1b.c: New test. + * lib/target-supports.exp + (check_effective_target_code_6_gottpoff_reloc): New. + +2024-02-23 Richard Earnshaw + + PR target/108120 + * gcc.target/arm/neon-recip-div-1.c: New file. + +2024-02-23 Jakub Jelinek + + PR rtl-optimization/114054 + * gcc.dg/bitint-92.c: New test. + +2024-02-23 Jakub Jelinek + + PR tree-optimization/114040 + * gcc.dg/torture/bitint-60.c: New test. + * gcc.dg/torture/bitint-61.c: New test. + +2024-02-23 Rainer Orth + + * gcc.dg/vect/vect-bic-bitmask-12.c: Move dg-skip-if down. + * gcc.dg/vect/vect-bic-bitmask-23.c: Likewise. + +2024-02-23 Rainer Orth + + * gcc.dg/plugin/crash-test-write-though-null-sarif.c + (scan-sarif-file): Allow for "Segmentation Fault", too. + 2024-02-22 Marek Polacek * g++.dg/warn/Wmismatched-new-delete-8.C: Use __SIZE_TYPE__. -- cgit v1.1 From 2541c9d9105b5c0dff23cf41fc1a14d002e6f31a Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Sat, 24 Feb 2024 10:10:36 +0000 Subject: Restrict gcc.dg/rtl/aarch64/pr113295-1.c to aarch64 I keep forgetting that gcc.dg/rtl is the one testsuite where tests in target-specific subdirectories aren't automatically restricted to that target. gcc/testsuite/ * gcc.dg/rtl/aarch64/pr113295-1.c: Restrict to aarc64*-*-*. --- gcc/testsuite/gcc.dg/rtl/aarch64/pr113295-1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/rtl/aarch64/pr113295-1.c b/gcc/testsuite/gcc.dg/rtl/aarch64/pr113295-1.c index 481fb81..bf6c5d1 100644 --- a/gcc/testsuite/gcc.dg/rtl/aarch64/pr113295-1.c +++ b/gcc/testsuite/gcc.dg/rtl/aarch64/pr113295-1.c @@ -1,5 +1,5 @@ +// { dg-do run { target aarch64*-*-* } } // { dg-options "-O2" } -// { dg-do run } struct data { double x; -- cgit v1.1 From 5e7a176e88a2a37434cef9b1b6a37a4f8274854a Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Sat, 24 Feb 2024 12:44:34 +0100 Subject: bitint: Handle VIEW_CONVERT_EXPRs between large/huge BITINT_TYPEs and VECTOR/COMPLEX_TYPE etc. [PR114073] The following patch implements support for VIEW_CONVERT_EXPRs from/to large/huge _BitInt to/from vector or complex types or anything else but integral/pointer types which doesn't need to live in memory. 2024-02-24 Jakub Jelinek PR middle-end/114073 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer types like vector or complex types. (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral types. Fix up VIEW_CONVERT_EXPR handling. Allow merging VIEW_CONVERT_EXPR from non-integral/pointer types with a store. * gcc.dg/bitint-93.c: New test. --- gcc/gimple-lower-bitint.cc | 74 +++++++++--- gcc/testsuite/gcc.dg/bitint-93.c | 253 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 310 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/bitint-93.c (limited to 'gcc') diff --git a/gcc/gimple-lower-bitint.cc b/gcc/gimple-lower-bitint.cc index 3552fdd..d7bf029 100644 --- a/gcc/gimple-lower-bitint.cc +++ b/gcc/gimple-lower-bitint.cc @@ -5305,27 +5305,21 @@ bitint_large_huge::lower_stmt (gimple *stmt) else if (TREE_CODE (TREE_TYPE (rhs1)) == BITINT_TYPE && bitint_precision_kind (TREE_TYPE (rhs1)) >= bitint_prec_large && (INTEGRAL_TYPE_P (TREE_TYPE (lhs)) - || POINTER_TYPE_P (TREE_TYPE (lhs)))) + || POINTER_TYPE_P (TREE_TYPE (lhs)) + || gimple_assign_rhs_code (stmt) == VIEW_CONVERT_EXPR)) { final_cast_p = true; - if (TREE_CODE (TREE_TYPE (lhs)) == INTEGER_TYPE - && TYPE_PRECISION (TREE_TYPE (lhs)) > MAX_FIXED_MODE_SIZE + if (((TREE_CODE (TREE_TYPE (lhs)) == INTEGER_TYPE + && TYPE_PRECISION (TREE_TYPE (lhs)) > MAX_FIXED_MODE_SIZE) + || (!INTEGRAL_TYPE_P (TREE_TYPE (lhs)) + && !POINTER_TYPE_P (TREE_TYPE (lhs)))) && gimple_assign_rhs_code (stmt) == VIEW_CONVERT_EXPR) { /* Handle VIEW_CONVERT_EXPRs to not generally supported huge INTEGER_TYPEs like uint256_t or uint512_t. These are usually emitted from memcpy folding and backends - support moves with them but that is usually it. */ - if (TREE_CODE (rhs1) == INTEGER_CST) - { - rhs1 = fold_unary (VIEW_CONVERT_EXPR, TREE_TYPE (lhs), - rhs1); - gcc_assert (rhs1 && TREE_CODE (rhs1) == INTEGER_CST); - gimple_assign_set_rhs1 (stmt, rhs1); - gimple_assign_set_rhs_code (stmt, INTEGER_CST); - update_stmt (stmt); - return; - } + support moves with them but that is usually it. + Similarly handle VCEs to vector/complex types etc. */ gcc_assert (TREE_CODE (rhs1) == SSA_NAME); if (SSA_NAME_IS_DEFAULT_DEF (rhs1) && (!SSA_NAME_VAR (rhs1) || VAR_P (SSA_NAME_VAR (rhs1)))) @@ -5376,6 +5370,18 @@ bitint_large_huge::lower_stmt (gimple *stmt) } } } + else if (TREE_CODE (TREE_TYPE (lhs)) == BITINT_TYPE + && bitint_precision_kind (TREE_TYPE (lhs)) >= bitint_prec_large + && !INTEGRAL_TYPE_P (TREE_TYPE (rhs1)) + && !POINTER_TYPE_P (TREE_TYPE (rhs1)) + && gimple_assign_rhs_code (stmt) == VIEW_CONVERT_EXPR) + { + int part = var_to_partition (m_map, lhs); + gcc_assert (m_vars[part] != NULL_TREE); + lhs = build1 (VIEW_CONVERT_EXPR, TREE_TYPE (rhs1), m_vars[part]); + insert_before (gimple_build_assign (lhs, rhs1)); + return; + } } if (gimple_store_p (stmt)) { @@ -5411,6 +5417,28 @@ bitint_large_huge::lower_stmt (gimple *stmt) case IMAGPART_EXPR: lower_cplxpart_stmt (lhs, g); goto handled; + case VIEW_CONVERT_EXPR: + { + tree rhs1 = gimple_assign_rhs1 (g); + rhs1 = TREE_OPERAND (rhs1, 0); + if (!INTEGRAL_TYPE_P (TREE_TYPE (rhs1)) + && !POINTER_TYPE_P (TREE_TYPE (rhs1))) + { + tree ltype = TREE_TYPE (rhs1); + addr_space_t as = TYPE_ADDR_SPACE (TREE_TYPE (lhs)); + ltype + = build_qualified_type (ltype, + TYPE_QUALS (TREE_TYPE (lhs)) + | ENCODE_QUAL_ADDR_SPACE (as)); + lhs = build1 (VIEW_CONVERT_EXPR, ltype, lhs); + gimple_assign_set_lhs (stmt, lhs); + gimple_assign_set_rhs1 (stmt, rhs1); + gimple_assign_set_rhs_code (stmt, TREE_CODE (rhs1)); + update_stmt (stmt); + return; + } + } + break; default: break; } @@ -6235,6 +6263,14 @@ gimple_lower_bitint (void) if (gimple_assign_cast_p (SSA_NAME_DEF_STMT (s))) { tree rhs1 = gimple_assign_rhs1 (SSA_NAME_DEF_STMT (s)); + if (TREE_CODE (rhs1) == VIEW_CONVERT_EXPR) + { + rhs1 = TREE_OPERAND (rhs1, 0); + if (!INTEGRAL_TYPE_P (TREE_TYPE (rhs1)) + && !POINTER_TYPE_P (TREE_TYPE (rhs1)) + && gimple_store_p (use_stmt)) + continue; + } if (INTEGRAL_TYPE_P (TREE_TYPE (rhs1)) && ((is_gimple_assign (use_stmt) && (gimple_assign_rhs_code (use_stmt) @@ -6279,11 +6315,15 @@ gimple_lower_bitint (void) goto force_name; break; case VIEW_CONVERT_EXPR: - /* Don't merge with VIEW_CONVERT_EXPRs to - huge INTEGER_TYPEs used sometimes in memcpy - expansion. */ { tree lhs = gimple_assign_lhs (use_stmt); + /* Don't merge with VIEW_CONVERT_EXPRs to + non-integral types. */ + if (!INTEGRAL_TYPE_P (TREE_TYPE (lhs))) + goto force_name; + /* Don't merge with VIEW_CONVERT_EXPRs to + huge INTEGER_TYPEs used sometimes in memcpy + expansion. */ if (TREE_CODE (TREE_TYPE (lhs)) == INTEGER_TYPE && (TYPE_PRECISION (TREE_TYPE (lhs)) > MAX_FIXED_MODE_SIZE)) diff --git a/gcc/testsuite/gcc.dg/bitint-93.c b/gcc/testsuite/gcc.dg/bitint-93.c new file mode 100644 index 0000000..ead24da --- /dev/null +++ b/gcc/testsuite/gcc.dg/bitint-93.c @@ -0,0 +1,253 @@ +/* PR middle-end/114073 */ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-O2 -Wno-psabi" } */ +/* { dg-additional-options "-mavx512f" { target i?86-*-* x86_64-*-* } } */ + +typedef int V __attribute__((vector_size (sizeof (_BitInt(256))))); +typedef int W __attribute__((vector_size (sizeof (_BitInt(512))))); + +#if __BITINT_MAXWIDTH__ >= 256 && defined (__SIZEOF_INT128__) +_Complex __int128 +f1 (_BitInt(256) x) +{ + union U { _BitInt(256) x; _Complex __int128 y; } u; + u.x = x; + return u.y; +} + +_Complex __int128 +f2 (_BitInt(254) x) +{ + union U { _BitInt(254) x; _Complex __int128 y; } u; + u.x = x; + return u.y; +} + +_BitInt(256) +f3 (_Complex __int128 x) +{ + union U { _BitInt(256) x; _Complex __int128 y; } u; + u.y = x; + return u.x; +} + +_BitInt(252) +f4 (_Complex __int128 x) +{ + union U { _BitInt(252) x; _Complex __int128 y; } u; + u.y = x; + return u.x; +} + +_Complex __int128 +f5 (_BitInt(256) x) +{ + union U { _BitInt(256) x; _Complex __int128 y; } u; + u.x = x + 1; + return u.y; +} + +_Complex __int128 +f6 (_BitInt(254) x) +{ + union U { _BitInt(254) x; _Complex __int128 y; } u; + u.x = x + 1; + return u.y; +} + +_Complex __int128 +f7 (_BitInt(256) *x) +{ + union U { _BitInt(256) x; _Complex __int128 y; } u; + u.x = *x + 1; + return u.y; +} + +_Complex __int128 +f8 (_BitInt(254) *x) +{ + union U { _BitInt(254) x; _Complex __int128 y; } u; + u.x = *x + 1; + return u.y; +} + +_BitInt(256) +f9 (_Complex __int128 x) +{ + union U { _BitInt(256) x; _Complex __int128 y; } u; + u.y = x; + return u.x + 1; +} + +_BitInt(252) +f10 (_Complex __int128 x) +{ + union U { _BitInt(252) x; _Complex __int128 y; } u; + u.y = x; + return u.x + 1; +} +#endif + +#if __BITINT_MAXWIDTH__ >= 256 +V +f11 (_BitInt(256) x) +{ + union U { _BitInt(256) x; V y; } u; + u.x = x; + return u.y; +} + +V +f12 (_BitInt(254) x) +{ + union U { _BitInt(254) x; V y; } u; + u.x = x; + return u.y; +} + +_BitInt(256) +f13 (V x) +{ + union U { _BitInt(256) x; V y; } u; + u.y = x; + return u.x; +} + +_BitInt(252) +f14 (V x) +{ + union U { _BitInt(252) x; V y; } u; + u.y = x; + return u.x; +} + +V +f15 (_BitInt(256) x) +{ + union U { _BitInt(256) x; V y; } u; + u.x = x + 1; + return u.y; +} + +V +f16 (_BitInt(254) x) +{ + union U { _BitInt(254) x; V y; } u; + u.x = x + 1; + return u.y; +} + +V +f17 (_BitInt(256) *x) +{ + union U { _BitInt(256) x; V y; } u; + u.x = *x + 1; + return u.y; +} + +V +f18 (_BitInt(254) *x) +{ + union U { _BitInt(254) x; V y; } u; + u.x = *x + 1; + return u.y; +} + +_BitInt(256) +f19 (V x) +{ + union U { _BitInt(256) x; V y; } u; + u.y = x; + return u.x + 1; +} + +_BitInt(252) +f20 (V x) +{ + union U { _BitInt(252) x; V y; } u; + u.y = x; + return u.x + 1; +} +#endif + +#if __BITINT_MAXWIDTH__ >= 512 +W +f21 (_BitInt(512) x) +{ + union U { _BitInt(512) x; W y; } u; + u.x = x; + return u.y; +} + +W +f22 (_BitInt(509) x) +{ + union U { _BitInt(509) x; W y; } u; + u.x = x; + return u.y; +} + +_BitInt(512) +f23 (W x) +{ + union U { _BitInt(512) x; W y; } u; + u.y = x; + return u.x; +} + +_BitInt(506) +f24 (W x) +{ + union U { _BitInt(506) x; W y; } u; + u.y = x; + return u.x; +} + +W +f25 (_BitInt(512) x) +{ + union U { _BitInt(512) x; W y; } u; + u.x = x + 1; + return u.y; +} + +W +f26 (_BitInt(509) x) +{ + union U { _BitInt(509) x; W y; } u; + u.x = x + 1; + return u.y; +} + +W +f27 (_BitInt(512) *x) +{ + union U { _BitInt(512) x; W y; } u; + u.x = *x + 1; + return u.y; +} + +W +f28 (_BitInt(509) *x) +{ + union U { _BitInt(509) x; W y; } u; + u.x = *x + 1; + return u.y; +} + +_BitInt(512) +f29 (W x) +{ + union U { _BitInt(512) x; W y; } u; + u.y = x; + return u.x + 1; +} + +_BitInt(506) +f30 (W x) +{ + union U { _BitInt(506) x; W y; } u; + u.y = x; + return u.x + 1; +} +#endif -- cgit v1.1 From d8b74d0b1ce0d5c31fad7ef6aa970a9b7fa4e7be Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Sat, 24 Feb 2024 12:45:40 +0100 Subject: Use HOST_WIDE_INT_{C,UC,0,0U,1,1U} macros some more I've searched for some uses of (HOST_WIDE_INT) constant or (unsigned HOST_WIDE_INT) constant and turned them into uses of the appropriate macros. THere are quite a few cases in non-i386 backends but I've left that out for now. The only behavior change is in build_replicated_int_cst where the left shift was done in HOST_WIDE_INT type but assigned to unsigned HOST_WIDE_INT, which I've changed into unsigned HOST_WIDE_INT shift. 2024-02-24 Jakub Jelinek gcc/ * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro. * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro. * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros. * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro. (mk_attr_alt): Use HOST_WIDE_INT_0 macro. * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1 macros. * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro. * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro. * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and HOST_WIDE_INT_UC macros. * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro. * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro. * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro. * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U macros. * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro. * config/i386/constraints.md (define_constraint "L"): Use HOST_WIDE_INT_C macro. * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C macro. (movl + movb peephole2): Likewise. * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise. (const_32bit_mask): Likewise. gcc/objc/ * objc-encoding.cc (encode_array): Use HOST_WIDE_INT_0 macros. --- gcc/builtins.cc | 2 +- gcc/combine.cc | 2 +- gcc/config/i386/constraints.md | 2 +- gcc/config/i386/i386.md | 4 ++-- gcc/config/i386/predicates.md | 4 ++-- gcc/double-int.cc | 4 ++-- gcc/genattrtab.cc | 4 ++-- gcc/genautomata.cc | 6 +++--- gcc/ipa-strub.cc | 2 +- gcc/loop-iv.cc | 2 +- gcc/objc/objc-encoding.cc | 4 ++-- gcc/pretty-print.cc | 13 ++++++++----- gcc/rtlanal.cc | 2 +- gcc/tree-ssa-structalias.cc | 5 ++--- gcc/tree.cc | 2 +- gcc/tree.h | 2 +- gcc/wide-int.cc | 3 +-- 17 files changed, 32 insertions(+), 31 deletions(-) (limited to 'gcc') diff --git a/gcc/builtins.cc b/gcc/builtins.cc index 4c04ae0..eda8bea 100644 --- a/gcc/builtins.cc +++ b/gcc/builtins.cc @@ -9326,7 +9326,7 @@ fold_builtin_isascii (location_t loc, tree arg) /* Transform isascii(c) -> ((c & ~0x7f) == 0). */ arg = fold_build2 (BIT_AND_EXPR, integer_type_node, arg, build_int_cst (integer_type_node, - ~ (unsigned HOST_WIDE_INT) 0x7f)); + ~ HOST_WIDE_INT_UC (0x7f))); return fold_build2_loc (loc, EQ_EXPR, integer_type_node, arg, integer_zero_node); } diff --git a/gcc/combine.cc b/gcc/combine.cc index 812553c..76543d8 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -9745,7 +9745,7 @@ make_field_assignment (rtx x) if (width >= HOST_BITS_PER_WIDE_INT) ze_mask = -1; else - ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; + ze_mask = (HOST_WIDE_INT_1U << width) - 1; /* Complete overlap. We can remove the source AND. */ if ((and_mask & ze_mask) == ze_mask) diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 64702d9..7508d7a 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -280,7 +280,7 @@ (and (match_code "const_int") (ior (match_test "ival == 0xff") (match_test "ival == 0xffff") - (match_test "ival == (HOST_WIDE_INT) 0xffffffff")))) + (match_test "ival == HOST_WIDE_INT_C (0xffffffff)")))) (define_constraint "M" "0, 1, 2, or 3 (shifts for the @code{lea} instruction)." diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d5db538..6a26d96 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -2689,7 +2689,7 @@ && !x86_64_immediate_operand (operands[1], DImode) && !x86_64_zext_immediate_operand (operands[1], DImode) && !((UINTVAL (operands[1]) >> ctz_hwi (UINTVAL (operands[1]))) - & ~(HOST_WIDE_INT) 0xffffffff) + & ~HOST_WIDE_INT_C (0xffffffff)) && peep2_regno_dead_p (0, FLAGS_REG)" [(set (match_dup 0) (match_dup 1)) (parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2))) @@ -3542,7 +3542,7 @@ [(set (match_operand:SWI48 0 "general_reg_operand") (match_dup 4))] { - HOST_WIDE_INT tmp = INTVAL (operands[1]) & ~(HOST_WIDE_INT)0xff00; + HOST_WIDE_INT tmp = INTVAL (operands[1]) & ~HOST_WIDE_INT_C (0xff00); tmp |= (INTVAL (operands[3]) & 0xff) << 8; operands[4] = gen_int_mode (tmp, mode); }) diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 391f108..2a97776 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -309,7 +309,7 @@ switch (GET_CODE (op)) { case CONST_INT: - return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff); + return !(INTVAL (op) & ~HOST_WIDE_INT_C (0xffffffff)); case SYMBOL_REF: /* TLS symbols are not constant. */ @@ -839,7 +839,7 @@ (define_predicate "const_32bit_mask" (and (match_code "const_int") (match_test "trunc_int_for_mode (INTVAL (op), DImode) - == (HOST_WIDE_INT) 0xffffffff"))) + == HOST_WIDE_INT_C (0xffffffff)"))) ;; Match 2, 4, or 8. Used for leal multiplicands. (define_predicate "const248_operand" diff --git a/gcc/double-int.cc b/gcc/double-int.cc index 08b0f76..e5c442f 100644 --- a/gcc/double-int.cc +++ b/gcc/double-int.cc @@ -671,14 +671,14 @@ double_int::mask (unsigned prec) if (prec > HOST_BITS_PER_WIDE_INT) { prec -= HOST_BITS_PER_WIDE_INT; - m = ((unsigned HOST_WIDE_INT) 2 << (prec - 1)) - 1; + m = (HOST_WIDE_INT_UC (2) << (prec - 1)) - 1; mask.high = (HOST_WIDE_INT) m; mask.low = ALL_ONES; } else { mask.high = 0; - mask.low = prec ? ((unsigned HOST_WIDE_INT) 2 << (prec - 1)) - 1 : 0; + mask.low = prec ? (HOST_WIDE_INT_UC (2) << (prec - 1)) - 1 : 0; } return mask; diff --git a/gcc/genattrtab.cc b/gcc/genattrtab.cc index 12082c1..03c7d6c 100644 --- a/gcc/genattrtab.cc +++ b/gcc/genattrtab.cc @@ -2392,7 +2392,7 @@ static rtx attr_alt_complement (rtx s) { return attr_rtx (EQ_ATTR_ALT, XWINT (s, 0), - ((HOST_WIDE_INT) 1) - XWINT (s, 1)); + HOST_WIDE_INT_1 - XWINT (s, 1)); } /* Return EQ_ATTR_ALT expression representing set containing elements set @@ -2401,7 +2401,7 @@ attr_alt_complement (rtx s) static rtx mk_attr_alt (alternative_mask e) { - return attr_rtx (EQ_ATTR_ALT, (HOST_WIDE_INT) e, (HOST_WIDE_INT) 0); + return attr_rtx (EQ_ATTR_ALT, (HOST_WIDE_INT) e, HOST_WIDE_INT_0); } /* Given an expression, see if it can be simplified for a particular insn diff --git a/gcc/genautomata.cc b/gcc/genautomata.cc index c66298d..ec1e533 100644 --- a/gcc/genautomata.cc +++ b/gcc/genautomata.cc @@ -3416,13 +3416,13 @@ finish_alt_states (void) /* Set bit number bitno in the bit string. The macro is not side effect proof. */ -#define bitmap_set_bit(bitstring, bitno) \ +#define bitmap_set_bit(bitstring, bitno) \ ((bitstring)[(bitno) / (sizeof (*(bitstring)) * CHAR_BIT)] |= \ - (HOST_WIDE_INT)1 << (bitno) % (sizeof (*(bitstring)) * CHAR_BIT)) + HOST_WIDE_INT_1 << (bitno) % (sizeof (*(bitstring)) * CHAR_BIT)) #define CLEAR_BIT(bitstring, bitno) \ ((bitstring)[(bitno) / (sizeof (*(bitstring)) * CHAR_BIT)] &= \ - ~((HOST_WIDE_INT)1 << (bitno) % (sizeof (*(bitstring)) * CHAR_BIT))) + ~(HOST_WIDE_INT_1 << (bitno) % (sizeof (*(bitstring)) * CHAR_BIT))) /* Test if bit number bitno in the bitstring is set. The macro is not side effect proof. */ diff --git a/gcc/ipa-strub.cc b/gcc/ipa-strub.cc index 09db1e0..dff9422 100644 --- a/gcc/ipa-strub.cc +++ b/gcc/ipa-strub.cc @@ -940,7 +940,7 @@ can_strub_internally_p (cgraph_node *node, bool report = false) } if (list_length (TYPE_ARG_TYPES (TREE_TYPE (node->decl))) - >= (((HOST_WIDE_INT) 1 << IPA_PARAM_MAX_INDEX_BITS) + >= ((HOST_WIDE_INT_1 << IPA_PARAM_MAX_INDEX_BITS) - STRUB_INTERNAL_MAX_EXTRA_ARGS)) { result = false; diff --git a/gcc/loop-iv.cc b/gcc/loop-iv.cc index eb7e923..f56cc5e 100644 --- a/gcc/loop-iv.cc +++ b/gcc/loop-iv.cc @@ -1577,7 +1577,7 @@ implies_p (rtx a, rtx b) && CONST_INT_P (XEXP (opb0, 1)) /* Avoid overflows. */ && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1)) - != ((unsigned HOST_WIDE_INT)1 + != (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)) - 1) && INTVAL (XEXP (opb0, 1)) + 1 == -INTVAL (op1)) return rtx_equal_p (op0, XEXP (opb0, 0)); diff --git a/gcc/objc/objc-encoding.cc b/gcc/objc/objc-encoding.cc index 18a3ea6..7cb0e5a 100644 --- a/gcc/objc/objc-encoding.cc +++ b/gcc/objc/objc-encoding.cc @@ -391,10 +391,10 @@ encode_array (tree type, int curtype, int format) /* Else, we are in a struct, and we encode it as a zero-length array. */ - sprintf (buffer, "[" HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)0); + sprintf (buffer, "[" HOST_WIDE_INT_PRINT_DEC, HOST_WIDE_INT_0); } else if (TREE_INT_CST_LOW (TYPE_SIZE (array_of)) == 0) - sprintf (buffer, "[" HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)0); + sprintf (buffer, "[" HOST_WIDE_INT_PRINT_DEC, HOST_WIDE_INT_0); else sprintf (buffer, "[" HOST_WIDE_INT_PRINT_DEC, TREE_INT_CST_LOW (an_int_cst) diff --git a/gcc/pretty-print.cc b/gcc/pretty-print.cc index 67c213b..eb59bf4 100644 --- a/gcc/pretty-print.cc +++ b/gcc/pretty-print.cc @@ -2813,13 +2813,16 @@ test_pp_format () ASSERT_PP_FORMAT_2 ("17 12345678", "%llo %x", (long long)15, 0x12345678); ASSERT_PP_FORMAT_2 ("cafebabe 12345678", "%llx %x", (long long)0xcafebabe, 0x12345678); - ASSERT_PP_FORMAT_2 ("-27 12345678", "%wd %x", (HOST_WIDE_INT)-27, 0x12345678); - ASSERT_PP_FORMAT_2 ("-5 12345678", "%wi %x", (HOST_WIDE_INT)-5, 0x12345678); - ASSERT_PP_FORMAT_2 ("10 12345678", "%wu %x", (unsigned HOST_WIDE_INT)10, + ASSERT_PP_FORMAT_2 ("-27 12345678", "%wd %x", HOST_WIDE_INT_C (-27), 0x12345678); - ASSERT_PP_FORMAT_2 ("17 12345678", "%wo %x", (HOST_WIDE_INT)15, 0x12345678); - ASSERT_PP_FORMAT_2 ("0xcafebabe 12345678", "%wx %x", (HOST_WIDE_INT)0xcafebabe, + ASSERT_PP_FORMAT_2 ("-5 12345678", "%wi %x", HOST_WIDE_INT_C (-5), 0x12345678); + ASSERT_PP_FORMAT_2 ("10 12345678", "%wu %x", HOST_WIDE_INT_UC (10), + 0x12345678); + ASSERT_PP_FORMAT_2 ("17 12345678", "%wo %x", HOST_WIDE_INT_C (15), + 0x12345678); + ASSERT_PP_FORMAT_2 ("0xcafebabe 12345678", "%wx %x", + HOST_WIDE_INT_C (0xcafebabe), 0x12345678); ASSERT_PP_FORMAT_2 ("-27 12345678", "%zd %x", (ssize_t)-27, 0x12345678); ASSERT_PP_FORMAT_2 ("-5 12345678", "%zi %x", (ssize_t)-5, 0x12345678); ASSERT_PP_FORMAT_2 ("10 12345678", "%zu %x", (size_t)10, 0x12345678); diff --git a/gcc/rtlanal.cc b/gcc/rtlanal.cc index ec65cf1..d38455b 100644 --- a/gcc/rtlanal.cc +++ b/gcc/rtlanal.cc @@ -5184,7 +5184,7 @@ nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x, case FFS: case POPCOUNT: /* This is at most the number of bits in the mode. */ - nonzero = ((unsigned HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1; + nonzero = (HOST_WIDE_INT_UC (2) << (floor_log2 (mode_width))) - 1; break; case CLZ: diff --git a/gcc/tree-ssa-structalias.cc b/gcc/tree-ssa-structalias.cc index 0647152..9c63305 100644 --- a/gcc/tree-ssa-structalias.cc +++ b/gcc/tree-ssa-structalias.cc @@ -8179,10 +8179,9 @@ dump_varinfo (FILE *file, varinfo_t vi) fprintf (file, "%shead:%u", sep, vi->head); if (vi->offset) fprintf (file, "%soffset:" HOST_WIDE_INT_PRINT_DEC, sep, vi->offset); - if (vi->size != ~(unsigned HOST_WIDE_INT)0) + if (vi->size != ~HOST_WIDE_INT_0U) fprintf (file, "%ssize:" HOST_WIDE_INT_PRINT_DEC, sep, vi->size); - if (vi->fullsize != ~(unsigned HOST_WIDE_INT)0 - && vi->fullsize != vi->size) + if (vi->fullsize != ~HOST_WIDE_INT_0U && vi->fullsize != vi->size) fprintf (file, "%sfullsize:" HOST_WIDE_INT_PRINT_DEC, sep, vi->fullsize); fprintf (file, "\n"); diff --git a/gcc/tree.cc b/gcc/tree.cc index 046a558..f801712 100644 --- a/gcc/tree.cc +++ b/gcc/tree.cc @@ -2691,7 +2691,7 @@ build_replicated_int_cst (tree type, unsigned int width, HOST_WIDE_INT value) low = value; else { - mask = ((HOST_WIDE_INT)1 << width) - 1; + mask = (HOST_WIDE_INT_1U << width) - 1; low = (unsigned HOST_WIDE_INT) ~0 / mask * (value & mask); } diff --git a/gcc/tree.h b/gcc/tree.h index 972a067..e1fc6c2 100644 --- a/gcc/tree.h +++ b/gcc/tree.h @@ -3020,7 +3020,7 @@ extern void decl_value_expr_insert (tree, tree); DECL_OFFSET_ALIGN thus returns the alignment that DECL_FIELD_OFFSET has. */ #define DECL_OFFSET_ALIGN(NODE) \ - (((unsigned HOST_WIDE_INT)1) << FIELD_DECL_CHECK (NODE)->decl_common.off_align) + (HOST_WIDE_INT_1U << FIELD_DECL_CHECK (NODE)->decl_common.off_align) /* Specify that DECL_OFFSET_ALIGN(NODE) is X. */ #define SET_DECL_OFFSET_ALIGN(NODE, X) \ diff --git a/gcc/wide-int.cc b/gcc/wide-int.cc index a8a6443..9c6eba8 100644 --- a/gcc/wide-int.cc +++ b/gcc/wide-int.cc @@ -1713,8 +1713,7 @@ divmod_internal_2 (unsigned HOST_HALF_WIDE_INT *b_quotient, HOST_WIDE_INT and stored in the lower bits of each word. This algorithm should work properly on both 32 and 64 bit machines. */ - unsigned HOST_WIDE_INT b - = (unsigned HOST_WIDE_INT)1 << HOST_BITS_PER_HALF_WIDE_INT; + unsigned HOST_WIDE_INT b = HOST_WIDE_INT_1U << HOST_BITS_PER_HALF_WIDE_INT; unsigned HOST_WIDE_INT qhat; /* Estimate of quotient digit. */ unsigned HOST_WIDE_INT rhat; /* A remainder. */ unsigned HOST_WIDE_INT p; /* Product of two digits. */ -- cgit v1.1 From 0394ae31e832c5303f3b4aad9c66710a30c097f0 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Sat, 24 Feb 2024 11:58:22 +0000 Subject: vect: Tighten check for impossible SLP layouts [PR113205] During its forward pass, the SLP layout code tries to calculate the cost of a layout change on an incoming edge. This is taken as the minimum of two costs: one in which the source partition keeps its current layout (chosen earlier during the pass) and one in which the source partition switches to the new layout. The latter can sometimes be arranged by the backward pass. If only one of the costs is valid, the other cost was ignored. But the PR shows that this is not safe. If the source partition has layout 0 (the normal layout), we have to be prepared to handle the case in which that ends up being the only valid layout. Other code already accounts for this restriction, e.g. see the code starting with: /* Reject the layout if it would make layout 0 impossible for later partitions. This amounts to testing that the target supports reversing the layout change on edges to later partitions. gcc/ PR tree-optimization/113205 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject the proposed layout if it does not allow a source partition with layout 2 to keep that layout. gcc/testsuite/ PR tree-optimization/113205 * gcc.dg/torture/pr113205.c: New test. --- gcc/testsuite/gcc.dg/torture/pr113205.c | 19 +++++++++++++++++++ gcc/tree-vect-slp.cc | 4 ++++ 2 files changed, 23 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/torture/pr113205.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/torture/pr113205.c b/gcc/testsuite/gcc.dg/torture/pr113205.c new file mode 100644 index 0000000..edfba7f --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr113205.c @@ -0,0 +1,19 @@ +char a; +char *b, *c; +int d, e, f, g, h; +int *i; + +void +foo (void) +{ + unsigned p; + d = i[0]; + e = i[1]; + f = i[2]; + g = i[3]; + p = d * b[0]; + p += f * c[h]; + p += e * b[h]; + p += g * c[h]; + a = (p + 8000) >> (__SIZEOF_INT__ * __CHAR_BIT__ / 2); +} diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc index 7cf9504..895f4f7 100644 --- a/gcc/tree-vect-slp.cc +++ b/gcc/tree-vect-slp.cc @@ -5034,6 +5034,10 @@ vect_optimize_slp_pass::forward_cost (graph_edge *ud, unsigned int from_node_i, cost.split (from_partition.out_degree); cost.add_serial_cost (edge_cost); } + else if (from_partition.layout == 0) + /* We must allow the source partition to have layout 0 as a fallback, + in case all other options turn out to be impossible. */ + return cost; /* Take the minimum of that cost and the cost that applies if FROM_PARTITION instead switches to TO_LAYOUT_I. */ -- cgit v1.1 From 5c45dc1b97890afe7a977cea8069214ccdc42384 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sun, 25 Feb 2024 00:17:06 +0000 Subject: Daily bump. --- gcc/ChangeLog | 44 ++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/objc/ChangeLog | 4 ++++ gcc/testsuite/ChangeLog | 14 ++++++++++++++ 4 files changed, 63 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3af0b7e..fa9dd74 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,47 @@ +2024-02-24 Richard Sandiford + + PR tree-optimization/113205 + * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject + the proposed layout if it does not allow a source partition with + layout 2 to keep that layout. + +2024-02-24 Jakub Jelinek + + * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro. + * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro. + * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros. + * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro. + (mk_attr_alt): Use HOST_WIDE_INT_0 macro. + * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1 + macros. + * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro. + * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro. + * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and + HOST_WIDE_INT_UC macros. + * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro. + * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro. + * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro. + * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U + macros. + * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro. + * config/i386/constraints.md (define_constraint "L"): Use + HOST_WIDE_INT_C macro. + * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C + macro. + (movl + movb peephole2): Likewise. + * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise. + (const_32bit_mask): Likewise. + +2024-02-24 Jakub Jelinek + + PR middle-end/114073 + * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle + VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer + types like vector or complex types. + (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral + types. Fix up VIEW_CONVERT_EXPR handling. Allow merging + VIEW_CONVERT_EXPR from non-integral/pointer types with a store. + 2024-02-23 Robin Dapp PR target/114028 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 4e5d4ad..ff71cb4 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240224 +20240225 diff --git a/gcc/objc/ChangeLog b/gcc/objc/ChangeLog index 2a4231d..3cc5d60 100644 --- a/gcc/objc/ChangeLog +++ b/gcc/objc/ChangeLog @@ -1,3 +1,7 @@ +2024-02-24 Jakub Jelinek + + * objc-encoding.cc (encode_array): Use HOST_WIDE_INT_0 macros. + 2024-01-28 Iain Sandoe * objc-next-runtime-abi-02.cc (build_v2_address_table): Prevent diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 669978d..48e6fb6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,17 @@ +2024-02-24 Richard Sandiford + + PR tree-optimization/113205 + * gcc.dg/torture/pr113205.c: New test. + +2024-02-24 Jakub Jelinek + + PR middle-end/114073 + * gcc.dg/bitint-93.c: New test. + +2024-02-24 Richard Sandiford + + * gcc.dg/rtl/aarch64/pr113295-1.c: Restrict to aarc64*-*-*. + 2024-02-23 Steve Kargl Harald Anlauf -- cgit v1.1 From d1b241b9506cdc0ebd3f43d12cf77d7c33271342 Mon Sep 17 00:00:00 2001 From: Gaius Mulley Date: Sun, 25 Feb 2024 11:08:37 +0000 Subject: PR modula2/113749 m2 enabled build times out on i686-gnu-hurd The bug fix changes the FIO module to use the target O_RDONLY, O_WRONLY, SEEK_SET and SEEK_END (now available from the module wrapc). Also rebuilt are the bootstrap tools mc and pge as they have their own wrapc and C translations of FIO. gcc/m2/ChangeLog: PR modula2/113749 * Make-lang.in (BUILD-PGE-O): Add m2/pge-boot/Gwrapc.o. * gm2-libs-ch/wrapc.c (wrapc_SeekSet): New function. (wrapc_SeekEnd): Ditto. (wrapc_ReadOnly): Ditto. (wrapc_WriteOnly): Ditto. * gm2-libs/FIO.mod (SEEK_SET): Remove. (SEEK_END): Remove. (UNIXREADONLY): Remove. (UNIXWRITEONLY): Remove. (ConnectToUnix): Replace UNIXWRITEONLY with a call to WriteOnly. Replace UNIXREADONLY with a call to ReadOnly. (SetPositionFromBeginning): Replace SEEK_SET with a call to SeekSet. (SetPositionFromEnd): Replace SEEK_END with a call to SeekEnd. * gm2-libs/wrapc.def (SeekSet): New procedure function. (SeekEnd): New procedure function. (ReadOnly): New procedure function. (WriteOnly): New procedure function. * mc-boot-ch/Glibc.c (BUILD_MC_LIBC_TRACE): Undef. (check_init): New function. (tracedb): Ditto. (tracedb_open): Ditto. (tracedb_result): Ditto. (libc_read): Ditto. (libc_write): Ditto. (libc_close): Ditto. (libc_creat): Ditto. (libc_open): Ditto. (libc_lseek): Ditto. * mc-boot-ch/Gwrapc.c (wrapc_SeekSet): New function. (wrapc_SeekEnd): Ditto. (wrapc_ReadOnly): Ditto. (wrapc_WriteOnly): Ditto. * mc-boot/GDynamicStrings.cc: Rebuilt. * mc-boot/GFIO.cc: Ditto. * mc-boot/GIndexing.cc: Ditto. * mc-boot/GM2Dependent.cc: Ditto. * mc-boot/GM2EXCEPTION.cc: Ditto. * mc-boot/GPushBackInput.cc: Ditto. * mc-boot/GRTExceptions.cc: Ditto. * mc-boot/GRTint.cc: Ditto. * mc-boot/GSArgs.cc: Ditto. * mc-boot/GStdIO.cc: Ditto. * mc-boot/GStringConvert.cc: Ditto. * mc-boot/GSysStorage.cc: Ditto. * mc-boot/Gdecl.cc: Ditto. * mc-boot/Gkeyc.cc: Ditto. * mc-boot/Glibc.h: Ditto. * mc-boot/GmcComment.cc: Ditto. * mc-boot/GmcComp.cc: Ditto. * mc-boot/GmcDebug.cc: Ditto. * mc-boot/GmcMetaError.cc: Ditto. * mc-boot/GmcStack.cc: Ditto. * mc-boot/GmcStream.cc: Ditto. * mc-boot/GnameKey.cc: Ditto. * mc-boot/GsymbolKey.cc: Ditto. * mc-boot/Gvarargs.cc: Ditto. * mc-boot/Gwrapc.h: Ditto. * mc/decl.mod (getSymName): Add pointerref clause. * mc/mcStream.mod (copy): Check for an error after every read. * mc/varargs.mod (copy): Rewrite pointer arithmetic using INC to avoid type incompatibility. * pge-boot/GDynamicStrings.cc: Rebuilt. * pge-boot/GDynamicStrings.h: Ditto. * pge-boot/GFIO.cc: Ditto. * pge-boot/GFIO.h: Ditto. * pge-boot/GIO.cc: Ditto. * pge-boot/GIndexing.cc: Ditto. * pge-boot/GM2Dependent.cc: Ditto. * pge-boot/GM2EXCEPTION.cc: Ditto. * pge-boot/GNameKey.cc: Ditto. * pge-boot/GPushBackInput.cc: Ditto. * pge-boot/GRTExceptions.cc: Ditto. * pge-boot/GStdIO.cc: Ditto. * pge-boot/GSymbolKey.cc: Ditto. * pge-boot/GSysStorage.cc: Ditto. * pge-boot/Glibc.h: Ditto. * pge-boot/Gwrapc.cc: Ditto. * pge-boot/Gwrapc.h: Ditto. libgm2/ChangeLog: PR modula2/113749 * libm2pim/wrapc.cc: Include fcntl.h. (SeekSet): New function. (SeekEnd): Ditto. (ReadOnly): Ditto. (WriteOnly): Ditto. Signed-off-by: Gaius Mulley --- gcc/m2/Make-lang.in | 1 + gcc/m2/gm2-libs-ch/wrapc.c | 32 +++++++++ gcc/m2/gm2-libs/FIO.mod | 18 +++-- gcc/m2/gm2-libs/wrapc.def | 28 ++++++++ gcc/m2/mc-boot-ch/Glibc.c | 112 ++++++++++++++++++++++++++++-- gcc/m2/mc-boot-ch/Gwrapc.c | 32 +++++++++ gcc/m2/mc-boot/GDynamicStrings.cc | 32 ++++----- gcc/m2/mc-boot/GFIO.cc | 19 +++-- gcc/m2/mc-boot/GIndexing.cc | 6 +- gcc/m2/mc-boot/GM2Dependent.cc | 23 ++++++- gcc/m2/mc-boot/GM2EXCEPTION.cc | 4 +- gcc/m2/mc-boot/GPushBackInput.cc | 6 +- gcc/m2/mc-boot/GRTExceptions.cc | 34 ++++----- gcc/m2/mc-boot/GRTint.cc | 20 +++--- gcc/m2/mc-boot/GSArgs.cc | 6 +- gcc/m2/mc-boot/GStdIO.cc | 4 +- gcc/m2/mc-boot/GStringConvert.cc | 4 +- gcc/m2/mc-boot/GSysStorage.cc | 6 +- gcc/m2/mc-boot/Gdecl.cc | 138 +++++++++++++++++++------------------ gcc/m2/mc-boot/Gkeyc.cc | 2 +- gcc/m2/mc-boot/Glibc.h | 2 +- gcc/m2/mc-boot/GmcComment.cc | 2 +- gcc/m2/mc-boot/GmcComp.cc | 4 +- gcc/m2/mc-boot/GmcDebug.cc | 2 +- gcc/m2/mc-boot/GmcMetaError.cc | 8 +-- gcc/m2/mc-boot/GmcStack.cc | 4 +- gcc/m2/mc-boot/GmcStream.cc | 13 +++- gcc/m2/mc-boot/GnameKey.cc | 4 +- gcc/m2/mc-boot/GsymbolKey.cc | 6 +- gcc/m2/mc-boot/Gvarargs.cc | 3 +- gcc/m2/mc-boot/Gwrapc.h | 45 ++++++++++++ gcc/m2/mc/decl.mod | 1 + gcc/m2/mc/mcStream.mod | 16 +++-- gcc/m2/mc/varargs.mod | 3 +- gcc/m2/pge-boot/GDynamicStrings.cc | 67 +++++++++++++----- gcc/m2/pge-boot/GDynamicStrings.h | 7 ++ gcc/m2/pge-boot/GFIO.cc | 64 +++++++++-------- gcc/m2/pge-boot/GFIO.h | 4 +- gcc/m2/pge-boot/GIO.cc | 13 ++-- gcc/m2/pge-boot/GIndexing.cc | 6 +- gcc/m2/pge-boot/GM2Dependent.cc | 23 ++++++- gcc/m2/pge-boot/GM2EXCEPTION.cc | 4 +- gcc/m2/pge-boot/GNameKey.cc | 15 ++-- gcc/m2/pge-boot/GPushBackInput.cc | 6 +- gcc/m2/pge-boot/GRTExceptions.cc | 34 ++++----- gcc/m2/pge-boot/GStdIO.cc | 4 +- gcc/m2/pge-boot/GSymbolKey.cc | 6 +- gcc/m2/pge-boot/GSysStorage.cc | 6 +- gcc/m2/pge-boot/Glibc.h | 2 +- gcc/m2/pge-boot/Gwrapc.cc | 32 +++++++++ gcc/m2/pge-boot/Gwrapc.h | 45 ++++++++++++ 51 files changed, 698 insertions(+), 280 deletions(-) (limited to 'gcc') diff --git a/gcc/m2/Make-lang.in b/gcc/m2/Make-lang.in index 45bfa93..33b9ce8 100644 --- a/gcc/m2/Make-lang.in +++ b/gcc/m2/Make-lang.in @@ -1786,6 +1786,7 @@ BUILD-PGE-O = \ m2/pge-boot/GSymbolKey.o \ m2/pge-boot/GSysStorage.o \ m2/pge-boot/Glibc.o \ + m2/pge-boot/Gwrapc.o \ m2/pge-boot/Gerrno.o \ m2/pge-boot/GUnixArgs.o \ m2/pge-boot/Gtermios.o \ diff --git a/gcc/m2/gm2-libs-ch/wrapc.c b/gcc/m2/gm2-libs-ch/wrapc.c index ed80cbd..24b65a9 100644 --- a/gcc/m2/gm2-libs-ch/wrapc.c +++ b/gcc/m2/gm2-libs-ch/wrapc.c @@ -252,6 +252,38 @@ wrapc_isnanl (long double x) return isnan (x); } +/* SeekSet return the system libc SEEK_SET value. */ + +int +wrapc_SeekSet (void) +{ + return SEEK_SET; +} + +/* SeekEnd return the system libc SEEK_END value. */ + +int +wrapc_SeekEnd (void) +{ + return SEEK_END; +} + +/* ReadOnly return the system value of O_RDONLY. */ + +int +wrapc_ReadOnly (void) +{ + return O_RDONLY; +} + +/* WriteOnly return the system value of O_WRONLY. */ + +int +wrapc_WriteOnly (void) +{ + return O_WRONLY; +} + /* init - init/finish functions for the module */ void diff --git a/gcc/m2/gm2-libs/FIO.mod b/gcc/m2/gm2-libs/FIO.mod index 6755d3d..8347e82 100644 --- a/gcc/m2/gm2-libs/FIO.mod +++ b/gcc/m2/gm2-libs/FIO.mod @@ -41,18 +41,16 @@ FROM ASCII IMPORT nl, nul, tab ; FROM StrLib IMPORT StrLen, StrConCat, StrCopy ; FROM Storage IMPORT ALLOCATE, DEALLOCATE ; FROM NumberIO IMPORT CardToStr ; -FROM libc IMPORT exit, open, creat, read, write, close, lseek, strncpy, memcpy ; FROM Indexing IMPORT Index, InitIndex, InBounds, HighIndice, PutIndice, GetIndice ; FROM M2RTS IMPORT InstallTerminationProcedure ; +FROM libc IMPORT exit, open, creat, read, write, close, lseek, strncpy, memcpy ; +FROM wrapc IMPORT SeekSet, SeekEnd, ReadOnly, WriteOnly ; + CONST - SEEK_SET = 0 ; (* relative from beginning of the file *) - SEEK_END = 2 ; (* relative to the end of the file *) - UNIXREADONLY = 0 ; - UNIXWRITEONLY = 1 ; - CreatePermissions = 666B; MaxBufferLength = 1024*16 ; MaxErrorString = 1024* 8 ; + CreatePermissions = 666B; TYPE FileUsage = (unused, openedforread, openedforwrite, openedforrandom) ; @@ -428,10 +426,10 @@ BEGIN THEN unixfd := creat(name.address, CreatePermissions) ELSE - unixfd := open(name.address, UNIXWRITEONLY, 0) + unixfd := open(name.address, INTEGER (WriteOnly ()), 0) END ELSE - unixfd := open(name.address, UNIXREADONLY, 0) + unixfd := open(name.address, INTEGER (ReadOnly ()), 0) END ; IF unixfd<0 THEN @@ -1448,7 +1446,7 @@ BEGIN filled := 0 END END ; - offset := lseek (unixfd, VAL (CSSIZE_T, pos), SEEK_SET) ; + offset := lseek (unixfd, VAL (CSSIZE_T, pos), SeekSet ()) ; IF (offset>=0) AND (pos=offset) THEN abspos := pos @@ -1497,7 +1495,7 @@ BEGIN filled := 0 END END ; - offset := lseek (unixfd, VAL (CSSIZE_T, pos), SEEK_END) ; + offset := lseek (unixfd, VAL (CSSIZE_T, pos), SeekEnd ()) ; IF offset>=0 THEN abspos := offset ; diff --git a/gcc/m2/gm2-libs/wrapc.def b/gcc/m2/gm2-libs/wrapc.def index 0daf7c3..244baa3 100644 --- a/gcc/m2/gm2-libs/wrapc.def +++ b/gcc/m2/gm2-libs/wrapc.def @@ -140,4 +140,32 @@ PROCEDURE isnanf (x: SHORTREAL) : INTEGER ; PROCEDURE isnanl (x: LONGREAL) : INTEGER ; +(* + SeekSet - return the system libc SEEK_SET value. +*) + +PROCEDURE SeekSet () : INTEGER ; + + +(* + SeekEnd - return the system libc SEEK_END value. +*) + +PROCEDURE SeekEnd () : INTEGER ; + + +(* + ReadOnly - return the system value of O_RDONLY. +*) + +PROCEDURE ReadOnly () : BITSET ; + + +(* + WriteOnly - return the system value of O_WRONLY. +*) + +PROCEDURE WriteOnly () : BITSET ; + + END wrapc. diff --git a/gcc/m2/mc-boot-ch/Glibc.c b/gcc/m2/mc-boot-ch/Glibc.c index 6154934..23a4905 100644 --- a/gcc/m2/mc-boot-ch/Glibc.c +++ b/gcc/m2/mc-boot-ch/Glibc.c @@ -28,25 +28,116 @@ along with GNU Modula-2; see the file COPYING3. If not see #define EXTERN #endif +#undef BUILD_MC_LIBC_TRACE + +#if defined(BUILD_MC_LIBC_TRACE) +static bool initialzed_trace = false; +static bool trace_on = false; + +static +void +check_init (void) +{ + if (! initialzed_trace) + { + initialzed_trace = true; + trace_on = ((getenv ("MC_LIBC_TRACE") != NULL)); + } +} +#endif + +static +void +tracedb (const char *format, ...) +{ +#if defined(BUILD_MC_LIBC_TRACE) + check_init (); + if (trace_on) + { + va_list arg; + va_start (arg, format); + { + vfprintf (stdout, format, arg); + fflush (stdout); + } + va_end (arg); + } +#endif +} + +static +void +tracedb_open (const char *p, int flags, mode_t mode) +{ +#if defined(BUILD_MC_LIBC_TRACE) + bool item_written = false; + tracedb ("libc_open (%s, flags = 0x%x = ", p, flags); + + int bits = (flags & O_ACCMODE); + tracedb ("bits = 0x%x", bits); + if (bits == O_RDONLY) + { + tracedb ("O_RDONLY"); + item_written = true; + } + if ((flags & O_WRONLY) != 0) + { + if (item_written) + tracedb (" | "); + tracedb ("O_WRONLY"); + item_written = true; + } + if ((flags & O_RDWR) != 0) + { + if (item_written) + tracedb (" | "); + tracedb ("O_RDWR"); + item_written = true; + } + tracedb (", 0x%x)\n", mode); +#endif +} + +static +void +tracedb_result (int result) +{ +#if defined(BUILD_MC_LIBC_TRACE) + tracedb (" result = %d", result); + if (result == -1) + tracedb (", errno = %s", strerror (errno)); + tracedb ("\n"); +#endif +} + EXTERN int libc_read (int fd, void *a, int nbytes) { - return read (fd, a, nbytes); + tracedb ("libc_read (%d, %p, %d)\n", fd, a, nbytes); + int result = read (fd, a, nbytes); + tracedb_result (result); + return result; } EXTERN int libc_write (int fd, void *a, int nbytes) { - return write (fd, a, nbytes); + tracedb ("libc_write (%d, %p, %d)\n", fd, a, nbytes); + int result = write (fd, a, nbytes); + tracedb_result (result); + return result; } EXTERN int libc_close (int fd) { - return close (fd); + tracedb ("libc_close (%d)\n", fd); + int result = close (fd); + tracedb_result (result); + return result; } EXTERN @@ -232,21 +323,30 @@ EXTERN int libc_creat (char *p, mode_t mode) { - return creat (p, mode); + tracedb ("libc_creat (%s, 0x%x)\n", p, mode); + int result = creat (p, mode); + tracedb_result (result); + return result; } EXTERN int libc_open (char *p, int flags, mode_t mode) { - return open (p, flags, mode); + tracedb_open (p, flags, mode); + int result = open (p, flags, mode); + tracedb_result (result); + return result; } EXTERN off_t libc_lseek (int fd, off_t offset, int whence) { - return lseek (fd, offset, whence); + tracedb ("libc_lseek (%s, %p, %d)\n", fd, offset, whence); + int result = lseek (fd, offset, whence); + tracedb_result (result); + return result; } EXTERN diff --git a/gcc/m2/mc-boot-ch/Gwrapc.c b/gcc/m2/mc-boot-ch/Gwrapc.c index f9397eb..5e27e31 100644 --- a/gcc/m2/mc-boot-ch/Gwrapc.c +++ b/gcc/m2/mc-boot-ch/Gwrapc.c @@ -164,6 +164,38 @@ wrapc_signbitf (float r) #endif } +/* SeekSet return the system libc SEEK_SET value. */ + +int +wrapc_SeekSet (void) +{ + return SEEK_SET; +} + +/* SeekEnd return the system libc SEEK_END value. */ + +int +wrapc_SeekEnd (void) +{ + return SEEK_END; +} + +/* ReadOnly return the system value of O_RDONLY. */ + +int +wrapc_ReadOnly (void) +{ + return O_RDONLY; +} + +/* WriteOnly return the system value of O_WRONLY. */ + +int +wrapc_WriteOnly (void) +{ + return O_WRONLY; +} + /* init constructor for the module. */ void diff --git a/gcc/m2/mc-boot/GDynamicStrings.cc b/gcc/m2/mc-boot/GDynamicStrings.cc index e9d75ee..7f61778 100644 --- a/gcc/m2/mc-boot/GDynamicStrings.cc +++ b/gcc/m2/mc-boot/GDynamicStrings.cc @@ -1225,7 +1225,7 @@ static void ConcatContents (DynamicStrings_Contents *c, const char *a_, unsigned (*c).next->contents.next = NULL; ConcatContents (&(*c).next->contents, (const char *) a, _a_high, h, o); AddDebugInfo ((*c).next); - (*c).next = AssignDebug ((*c).next, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 722, (const char *) "ConcatContents", 14); + (*c).next = AssignDebug ((*c).next, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 722, (const char *) "ConcatContents", 14); } else { @@ -1323,7 +1323,7 @@ static void ConcatContentsAddress (DynamicStrings_Contents *c, void * a, unsigne AddDebugInfo ((*c).next); if (TraceOn) { - (*c).next = AssignDebug ((*c).next, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 917, (const char *) "ConcatContentsAddress", 21); + (*c).next = AssignDebug ((*c).next, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 917, (const char *) "ConcatContentsAddress", 21); } } else @@ -1548,7 +1548,7 @@ extern "C" DynamicStrings_String DynamicStrings_InitString (const char *a_, unsi AddDebugInfo (s); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 758, (const char *) "InitString", 10); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 758, (const char *) "InitString", 10); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -1651,7 +1651,7 @@ extern "C" DynamicStrings_String DynamicStrings_InitStringCharStar (void * a) AddDebugInfo (s); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 957, (const char *) "InitStringCharStar", 18); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 957, (const char *) "InitStringCharStar", 18); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -1676,7 +1676,7 @@ extern "C" DynamicStrings_String DynamicStrings_InitStringChar (char ch) s = DynamicStrings_InitString ((const char *) &a.array[0], 1); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 977, (const char *) "InitStringChar", 14); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 977, (const char *) "InitStringChar", 14); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -1863,7 +1863,7 @@ extern "C" DynamicStrings_String DynamicStrings_Dup (DynamicStrings_String s) s = DynamicStrings_Assign (DynamicStrings_InitString ((const char *) "", 0), s); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1198, (const char *) "Dup", 3); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1198, (const char *) "Dup", 3); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -1885,7 +1885,7 @@ extern "C" DynamicStrings_String DynamicStrings_Add (DynamicStrings_String a, Dy a = DynamicStrings_ConCat (DynamicStrings_ConCat (DynamicStrings_InitString ((const char *) "", 0), a), b); if (TraceOn) { - a = AssignDebug (a, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1218, (const char *) "Add", 3); + a = AssignDebug (a, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1218, (const char *) "Add", 3); } return a; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -1950,7 +1950,7 @@ extern "C" bool DynamicStrings_EqualCharStar (DynamicStrings_String s, void * a) t = DynamicStrings_InitStringCharStar (a); if (TraceOn) { - t = AssignDebug (t, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1275, (const char *) "EqualCharStar", 13); + t = AssignDebug (t, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1275, (const char *) "EqualCharStar", 13); } t = AddToGarbage (t, s); if (DynamicStrings_Equal (t, s)) @@ -1988,7 +1988,7 @@ extern "C" bool DynamicStrings_EqualArray (DynamicStrings_String s, const char * t = DynamicStrings_InitString ((const char *) a, _a_high); if (TraceOn) { - t = AssignDebug (t, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1305, (const char *) "EqualArray", 10); + t = AssignDebug (t, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1305, (const char *) "EqualArray", 10); } t = AddToGarbage (t, s); if (DynamicStrings_Equal (t, s)) @@ -2026,7 +2026,7 @@ extern "C" DynamicStrings_String DynamicStrings_Mult (DynamicStrings_String s, u } if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1337, (const char *) "Mult", 4); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1337, (const char *) "Mult", 4); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -2105,7 +2105,7 @@ extern "C" DynamicStrings_String DynamicStrings_Slice (DynamicStrings_String s, AddDebugInfo (t->contents.next); if (TraceOn) { - t->contents.next = AssignDebug (t->contents.next, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1405, (const char *) "Slice", 5); + t->contents.next = AssignDebug (t->contents.next, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1405, (const char *) "Slice", 5); } } t = t->contents.next; @@ -2123,7 +2123,7 @@ extern "C" DynamicStrings_String DynamicStrings_Slice (DynamicStrings_String s, } if (TraceOn) { - d = AssignDebug (d, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1422, (const char *) "Slice", 5); + d = AssignDebug (d, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1422, (const char *) "Slice", 5); } return d; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -2251,7 +2251,7 @@ extern "C" DynamicStrings_String DynamicStrings_RemoveComment (DynamicStrings_St } if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1534, (const char *) "RemoveComment", 13); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1534, (const char *) "RemoveComment", 13); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -2276,7 +2276,7 @@ extern "C" DynamicStrings_String DynamicStrings_RemoveWhitePrefix (DynamicString s = DynamicStrings_Slice (s, (int ) (i), 0); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1646, (const char *) "RemoveWhitePrefix", 17); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1646, (const char *) "RemoveWhitePrefix", 17); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -2301,7 +2301,7 @@ extern "C" DynamicStrings_String DynamicStrings_RemoveWhitePostfix (DynamicStrin s = DynamicStrings_Slice (s, 0, i+1); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1668, (const char *) "RemoveWhitePostfix", 18); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1668, (const char *) "RemoveWhitePostfix", 18); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -2668,7 +2668,7 @@ extern "C" DynamicStrings_String DynamicStrings_PopAllocationExemption (bool hal if (frameHead == NULL) { stop (); - M2RTS_Halt ((const char *) "mismatched number of PopAllocation's compared to PushAllocation's", 65, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, (const char *) "PopAllocationExemption", 22, 174); + M2RTS_Halt ((const char *) "mismatched number of PopAllocation's compared to PushAllocation's", 65, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, (const char *) "PopAllocationExemption", 22, 174); } else { diff --git a/gcc/m2/mc-boot/GFIO.cc b/gcc/m2/mc-boot/GFIO.cc index 8de4c4f..3f05b35 100644 --- a/gcc/m2/mc-boot/GFIO.cc +++ b/gcc/m2/mc-boot/GFIO.cc @@ -56,22 +56,19 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see # include "GStrLib.h" # include "GStorage.h" # include "GNumberIO.h" -# include "Glibc.h" # include "GIndexing.h" # include "GM2RTS.h" +# include "Glibc.h" +# include "Gwrapc.h" typedef unsigned int FIO_File; FIO_File FIO_StdErr; FIO_File FIO_StdOut; FIO_File FIO_StdIn; -# define SEEK_SET 0 -# define SEEK_END 2 -# define UNIXREADONLY 0 -# define UNIXWRITEONLY 1 -# define CreatePermissions 0666 # define MaxBufferLength (1024*16) # define MaxErrorString (1024*8) +# define CreatePermissions 0666 typedef struct FIO_NameInfo_r FIO_NameInfo; typedef struct FIO_buf_r FIO_buf; @@ -556,7 +553,7 @@ static FIO_File GetNextFreeDescriptor (void) return f; /* create new slot */ } } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/FIO.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/FIO.def", 25, 1); __builtin_unreachable (); } @@ -673,12 +670,12 @@ static void ConnectToUnix (FIO_File f, bool towrite, bool newfile) } else { - fd->unixfd = libc_open (fd->name.address, UNIXWRITEONLY, 0); + fd->unixfd = libc_open (fd->name.address, (int ) (wrapc_WriteOnly ()), 0); } } else { - fd->unixfd = libc_open (fd->name.address, UNIXREADONLY, 0); + fd->unixfd = libc_open (fd->name.address, (int ) (wrapc_ReadOnly ()), 0); } if (fd->unixfd < 0) { @@ -2093,7 +2090,7 @@ extern "C" void FIO_SetPositionFromBeginning (FIO_File f, long int pos) fd->buffer->position = 0; fd->buffer->filled = 0; } - offset = libc_lseek (fd->unixfd, pos, SEEK_SET); + offset = static_cast (libc_lseek (fd->unixfd, (ssize_t ) (pos), wrapc_SeekSet ())); if ((offset >= 0) && (pos == offset)) { fd->abspos = pos; @@ -2142,7 +2139,7 @@ extern "C" void FIO_SetPositionFromEnd (FIO_File f, long int pos) fd->buffer->position = 0; fd->buffer->filled = 0; } - offset = libc_lseek (fd->unixfd, pos, SEEK_END); + offset = static_cast (libc_lseek (fd->unixfd, (ssize_t ) (pos), wrapc_SeekEnd ())); if (offset >= 0) { fd->abspos = offset; diff --git a/gcc/m2/mc-boot/GIndexing.cc b/gcc/m2/mc-boot/GIndexing.cc index ac184be..894b8cb 100644 --- a/gcc/m2/mc-boot/GIndexing.cc +++ b/gcc/m2/mc-boot/GIndexing.cc @@ -223,7 +223,7 @@ extern "C" bool Indexing_InBounds (Indexing_Index i, unsigned int n) { return (n >= i->Low) && (n <= i->High); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/Indexing.def", 20, 1); + ReturnException ("../../gcc/m2/mc/Indexing.def", 20, 1); __builtin_unreachable (); } @@ -243,7 +243,7 @@ extern "C" unsigned int Indexing_HighIndice (Indexing_Index i) { return i->High; } - ReturnException ("../../gcc-read-write/gcc/m2/mc/Indexing.def", 20, 1); + ReturnException ("../../gcc/m2/mc/Indexing.def", 20, 1); __builtin_unreachable (); } @@ -263,7 +263,7 @@ extern "C" unsigned int Indexing_LowIndice (Indexing_Index i) { return i->Low; } - ReturnException ("../../gcc-read-write/gcc/m2/mc/Indexing.def", 20, 1); + ReturnException ("../../gcc/m2/mc/Indexing.def", 20, 1); __builtin_unreachable (); } diff --git a/gcc/m2/mc-boot/GM2Dependent.cc b/gcc/m2/mc-boot/GM2Dependent.cc index 198d2e8..cda07e8 100644 --- a/gcc/m2/mc-boot/GM2Dependent.cc +++ b/gcc/m2/mc-boot/GM2Dependent.cc @@ -135,6 +135,12 @@ extern "C" void M2Dependent_RegisterModule (void * modulename, void * libname, M extern "C" void M2Dependent_RequestDependant (void * modulename, void * libname, void * dependantmodule, void * dependantlibname); /* + InitDependencyList - initialize all fields of DependencyList. +*/ + +static void InitDependencyList (M2Dependent_DependencyList *depList, PROC proc, M2Dependent_DependencyState state); + +/* CreateModule - creates a new module entry and returns the ModuleChain. */ @@ -355,6 +361,20 @@ static void CheckInitialized (void); /* + InitDependencyList - initialize all fields of DependencyList. +*/ + +static void InitDependencyList (M2Dependent_DependencyList *depList, PROC proc, M2Dependent_DependencyState state) +{ + (*depList).proc = proc; + (*depList).forced = false; + (*depList).forc = false; + (*depList).appl = false; + (*depList).state = state; +} + + +/* CreateModule - creates a new module entry and returns the ModuleChain. */ @@ -368,8 +388,7 @@ static M2Dependent_ModuleChain CreateModule (void * name, void * libname, M2Depe mptr->libname = libname; mptr->init = init; mptr->fini = fini; - mptr->dependency.proc = dependencies; - mptr->dependency.state = M2Dependent_unregistered; + InitDependencyList (&mptr->dependency, dependencies, M2Dependent_unregistered); mptr->prev = NULL; mptr->next = NULL; if (HexTrace) diff --git a/gcc/m2/mc-boot/GM2EXCEPTION.cc b/gcc/m2/mc-boot/GM2EXCEPTION.cc index 2f9d61a..2e26831 100644 --- a/gcc/m2/mc-boot/GM2EXCEPTION.cc +++ b/gcc/m2/mc-boot/GM2EXCEPTION.cc @@ -58,13 +58,13 @@ extern "C" M2EXCEPTION_M2Exceptions M2EXCEPTION_M2Exception (void) n = RTExceptions_GetNumber (e); if (n == (UINT_MAX)) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_exException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/M2EXCEPTION.mod")), 47, 6, const_cast (reinterpret_cast("M2Exception")), const_cast (reinterpret_cast("current coroutine is not in the exceptional execution state"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_exException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/M2EXCEPTION.mod")), 47, 6, const_cast (reinterpret_cast("M2Exception")), const_cast (reinterpret_cast("current coroutine is not in the exceptional execution state"))); } else { return (M2EXCEPTION_M2Exceptions) (n); } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/M2EXCEPTION.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/M2EXCEPTION.def", 25, 1); __builtin_unreachable (); } diff --git a/gcc/m2/mc-boot/GPushBackInput.cc b/gcc/m2/mc-boot/GPushBackInput.cc index 715a7d4..4e0b41e 100644 --- a/gcc/m2/mc-boot/GPushBackInput.cc +++ b/gcc/m2/mc-boot/GPushBackInput.cc @@ -275,7 +275,7 @@ extern "C" char PushBackInput_PutCh (char ch) } else { - Debug_Halt ((const char *) "max push back stack exceeded, increase MaxPushBackStack", 55, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/PushBackInput.mod", 54, (const char *) "PutCh", 5, 151); + Debug_Halt ((const char *) "max push back stack exceeded, increase MaxPushBackStack", 55, (const char *) "../../gcc/m2/gm2-libs/PushBackInput.mod", 39, (const char *) "PutCh", 5, 151); } return ch; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -301,7 +301,7 @@ extern "C" void PushBackInput_PutString (const char *a_, unsigned int _a_high) l -= 1; if ((PushBackInput_PutCh (a[l])) != a[l]) { - Debug_Halt ((const char *) "assert failed", 13, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/PushBackInput.mod", 54, (const char *) "PutString", 9, 132); + Debug_Halt ((const char *) "assert failed", 13, (const char *) "../../gcc/m2/gm2-libs/PushBackInput.mod", 39, (const char *) "PutString", 9, 132); } } } @@ -322,7 +322,7 @@ extern "C" void PushBackInput_PutStr (DynamicStrings_String s) i -= 1; if ((PushBackInput_PutCh (DynamicStrings_char (s, static_cast (i)))) != (DynamicStrings_char (s, static_cast (i)))) { - Debug_Halt ((const char *) "assert failed", 13, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/PushBackInput.mod", 54, (const char *) "PutStr", 6, 113); + Debug_Halt ((const char *) "assert failed", 13, (const char *) "../../gcc/m2/gm2-libs/PushBackInput.mod", 39, (const char *) "PutStr", 6, 113); } } } diff --git a/gcc/m2/mc-boot/GRTExceptions.cc b/gcc/m2/mc-boot/GRTExceptions.cc index 99e364c..e7b35cf 100644 --- a/gcc/m2/mc-boot/GRTExceptions.cc +++ b/gcc/m2/mc-boot/GRTExceptions.cc @@ -722,7 +722,7 @@ static void AddHandler (RTExceptions_EHBlock e, RTExceptions_Handler h) static void indexf (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_indexException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 614, 9, const_cast (reinterpret_cast("indexf")), const_cast (reinterpret_cast("array index out of bounds"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_indexException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 614, 9, const_cast (reinterpret_cast("indexf")), const_cast (reinterpret_cast("array index out of bounds"))); } @@ -732,7 +732,7 @@ static void indexf (void * a) static void range (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_rangeException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 626, 9, const_cast (reinterpret_cast("range")), const_cast (reinterpret_cast("assignment out of range"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_rangeException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 626, 9, const_cast (reinterpret_cast("range")), const_cast (reinterpret_cast("assignment out of range"))); } @@ -742,7 +742,7 @@ static void range (void * a) static void casef (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_caseSelectException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 638, 9, const_cast (reinterpret_cast("casef")), const_cast (reinterpret_cast("case selector out of range"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_caseSelectException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 638, 9, const_cast (reinterpret_cast("casef")), const_cast (reinterpret_cast("case selector out of range"))); } @@ -752,7 +752,7 @@ static void casef (void * a) static void invalidloc (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_invalidLocation)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 650, 9, const_cast (reinterpret_cast("invalidloc")), const_cast (reinterpret_cast("invalid address referenced"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_invalidLocation)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 650, 9, const_cast (reinterpret_cast("invalidloc")), const_cast (reinterpret_cast("invalid address referenced"))); } @@ -762,7 +762,7 @@ static void invalidloc (void * a) static void function (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_functionException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 662, 9, const_cast (reinterpret_cast("function")), const_cast (reinterpret_cast("... function ... "))); /* --fixme-- what has happened ? */ + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_functionException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 662, 9, const_cast (reinterpret_cast("function")), const_cast (reinterpret_cast("... function ... "))); /* --fixme-- what has happened ? */ } @@ -772,7 +772,7 @@ static void function (void * a) static void wholevalue (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_wholeValueException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 674, 9, const_cast (reinterpret_cast("wholevalue")), const_cast (reinterpret_cast("illegal whole value exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_wholeValueException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 674, 9, const_cast (reinterpret_cast("wholevalue")), const_cast (reinterpret_cast("illegal whole value exception"))); } @@ -782,7 +782,7 @@ static void wholevalue (void * a) static void wholediv (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_wholeDivException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 686, 9, const_cast (reinterpret_cast("wholediv")), const_cast (reinterpret_cast("illegal whole value exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_wholeDivException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 686, 9, const_cast (reinterpret_cast("wholediv")), const_cast (reinterpret_cast("illegal whole value exception"))); } @@ -792,7 +792,7 @@ static void wholediv (void * a) static void realvalue (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_realValueException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 698, 9, const_cast (reinterpret_cast("realvalue")), const_cast (reinterpret_cast("illegal real value exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_realValueException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 698, 9, const_cast (reinterpret_cast("realvalue")), const_cast (reinterpret_cast("illegal real value exception"))); } @@ -802,7 +802,7 @@ static void realvalue (void * a) static void realdiv (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_realDivException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 710, 9, const_cast (reinterpret_cast("realdiv")), const_cast (reinterpret_cast("real number division by zero exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_realDivException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 710, 9, const_cast (reinterpret_cast("realdiv")), const_cast (reinterpret_cast("real number division by zero exception"))); } @@ -812,7 +812,7 @@ static void realdiv (void * a) static void complexvalue (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_complexValueException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 722, 9, const_cast (reinterpret_cast("complexvalue")), const_cast (reinterpret_cast("illegal complex value exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_complexValueException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 722, 9, const_cast (reinterpret_cast("complexvalue")), const_cast (reinterpret_cast("illegal complex value exception"))); } @@ -822,7 +822,7 @@ static void complexvalue (void * a) static void complexdiv (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_complexDivException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 734, 9, const_cast (reinterpret_cast("complexdiv")), const_cast (reinterpret_cast("complex number division by zero exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_complexDivException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 734, 9, const_cast (reinterpret_cast("complexdiv")), const_cast (reinterpret_cast("complex number division by zero exception"))); } @@ -832,7 +832,7 @@ static void complexdiv (void * a) static void protection (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_protException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 746, 9, const_cast (reinterpret_cast("protection")), const_cast (reinterpret_cast("protection exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_protException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 746, 9, const_cast (reinterpret_cast("protection")), const_cast (reinterpret_cast("protection exception"))); } @@ -842,7 +842,7 @@ static void protection (void * a) static void systemf (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_sysException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 758, 9, const_cast (reinterpret_cast("systemf")), const_cast (reinterpret_cast("system exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_sysException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 758, 9, const_cast (reinterpret_cast("systemf")), const_cast (reinterpret_cast("system exception"))); } @@ -852,7 +852,7 @@ static void systemf (void * a) static void coroutine (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_coException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 770, 9, const_cast (reinterpret_cast("coroutine")), const_cast (reinterpret_cast("coroutine exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_coException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 770, 9, const_cast (reinterpret_cast("coroutine")), const_cast (reinterpret_cast("coroutine exception"))); } @@ -862,7 +862,7 @@ static void coroutine (void * a) static void exception (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_exException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 782, 9, const_cast (reinterpret_cast("exception")), const_cast (reinterpret_cast("exception exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_exException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 782, 9, const_cast (reinterpret_cast("exception")), const_cast (reinterpret_cast("exception exception"))); } @@ -1180,13 +1180,13 @@ extern "C" RTExceptions_EHBlock RTExceptions_GetBaseExceptionBlock (void) { if (currentEHB == NULL) { - M2RTS_Halt ((const char *) "currentEHB has not been initialized yet", 39, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod", 53, (const char *) "GetBaseExceptionBlock", 21, 600); + M2RTS_Halt ((const char *) "currentEHB has not been initialized yet", 39, (const char *) "../../gcc/m2/gm2-libs/RTExceptions.mod", 38, (const char *) "GetBaseExceptionBlock", 21, 600); } else { return currentEHB; } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/RTExceptions.def", 25, 1); __builtin_unreachable (); } diff --git a/gcc/m2/mc-boot/GRTint.cc b/gcc/m2/mc-boot/GRTint.cc index 8e83b1f..236dbf4 100644 --- a/gcc/m2/mc-boot/GRTint.cc +++ b/gcc/m2/mc-boot/GRTint.cc @@ -585,7 +585,7 @@ static bool activatePending (bool untilInterrupt, RTint_DispatchVector call, uns default: - CaseException ("../../gcc-read-write/gcc/m2/gm2-libs/RTint.def", 25, 1); + CaseException ("../../gcc/m2/gm2-libs/RTint.def", 25, 1); __builtin_unreachable (); } vec = vec->pending; @@ -698,7 +698,7 @@ extern "C" unsigned int RTint_InitOutputVector (int fd, unsigned int pri) RTco_signal (lock); return vptr->no; } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/RTint.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/RTint.def", 25, 1); __builtin_unreachable (); } @@ -755,7 +755,7 @@ extern "C" void RTint_ReArmTimeVector (unsigned int vec, unsigned int micro, uns vptr = FindVectorNo (vec); if (vptr == NULL) { - M2RTS_Halt ((const char *) "cannot find vector supplied", 27, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/RTint.mod", 46, (const char *) "ReArmTimeVector", 15, 287); + M2RTS_Halt ((const char *) "cannot find vector supplied", 27, (const char *) "../../gcc/m2/gm2-libs/RTint.mod", 31, (const char *) "ReArmTimeVector", 15, 287); } else { @@ -780,7 +780,7 @@ extern "C" void RTint_GetTimeVector (unsigned int vec, unsigned int *micro, unsi vptr = FindVectorNo (vec); if (vptr == NULL) { - M2RTS_Halt ((const char *) "cannot find vector supplied", 27, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/RTint.mod", 46, (const char *) "GetTimeVector", 13, 313); + M2RTS_Halt ((const char *) "cannot find vector supplied", 27, (const char *) "../../gcc/m2/gm2-libs/RTint.mod", 31, (const char *) "GetTimeVector", 13, 313); } else { @@ -806,7 +806,7 @@ extern "C" void * RTint_AttachVector (unsigned int vec, void * ptr) vptr = FindVectorNo (vec); if (vptr == NULL) { - M2RTS_Halt ((const char *) "cannot find vector supplied", 27, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/RTint.mod", 46, (const char *) "AttachVector", 12, 340); + M2RTS_Halt ((const char *) "cannot find vector supplied", 27, (const char *) "../../gcc/m2/gm2-libs/RTint.mod", 31, (const char *) "AttachVector", 12, 340); } else { @@ -820,7 +820,7 @@ extern "C" void * RTint_AttachVector (unsigned int vec, void * ptr) RTco_signal (lock); return prevArg; } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/RTint.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/RTint.def", 25, 1); __builtin_unreachable (); } @@ -845,7 +845,7 @@ extern "C" void RTint_IncludeVector (unsigned int vec) vptr = FindVectorNo (vec); if (vptr == NULL) { - M2RTS_Halt ((const char *) "cannot find vector supplied", 27, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/RTint.mod", 46, (const char *) "IncludeVector", 13, 374); + M2RTS_Halt ((const char *) "cannot find vector supplied", 27, (const char *) "../../gcc/m2/gm2-libs/RTint.mod", 31, (const char *) "IncludeVector", 13, 374); } else { @@ -891,7 +891,7 @@ extern "C" void RTint_ExcludeVector (unsigned int vec) vptr = FindPendingVector (vec); if (vptr == NULL) { - M2RTS_Halt ((const char *) "cannot find pending vector supplied", 35, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/RTint.mod", 46, (const char *) "ExcludeVector", 13, 416); + M2RTS_Halt ((const char *) "cannot find pending vector supplied", 35, (const char *) "../../gcc/m2/gm2-libs/RTint.mod", 31, (const char *) "ExcludeVector", 13, 416); } else { @@ -989,7 +989,7 @@ extern "C" void RTint_Listen (bool untilInterrupt, RTint_DispatchVector call, un default: - CaseException ("../../gcc-read-write/gcc/m2/gm2-libs/RTint.def", 25, 1); + CaseException ("../../gcc/m2/gm2-libs/RTint.def", 25, 1); __builtin_unreachable (); } vec = vec->pending; @@ -1002,7 +1002,7 @@ extern "C" void RTint_Listen (bool untilInterrupt, RTint_DispatchVector call, un } if ((untilInterrupt && (((inSet == NULL) && (outSet == NULL)) || (maxFd == -1))) && ! found) { - M2RTS_Halt ((const char *) "deadlock found, no more processes to run and no interrupts active", 65, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/RTint.mod", 46, (const char *) "Listen", 6, 733); + M2RTS_Halt ((const char *) "deadlock found, no more processes to run and no interrupts active", 65, (const char *) "../../gcc/m2/gm2-libs/RTint.mod", 31, (const char *) "Listen", 6, 733); } /* printf('} ') ; */ diff --git a/gcc/m2/mc-boot/GSArgs.cc b/gcc/m2/mc-boot/GSArgs.cc index d69c47d..3424fbc 100644 --- a/gcc/m2/mc-boot/GSArgs.cc +++ b/gcc/m2/mc-boot/GSArgs.cc @@ -85,13 +85,15 @@ extern "C" unsigned int SArgs_Narg (void); extern "C" bool SArgs_GetArg (DynamicStrings_String *s, unsigned int n) { int i; + void * a; SArgs_PtrToPtrToChar ppc; i = (int ) (n); if (i < (UnixArgs_GetArgC ())) { - /* ppc := ADDRESS (VAL (PtrToPtrToChar, ArgV) + (i * CARDINAL (TSIZE(PtrToChar)))) ; */ - ppc = static_cast ((void *) (((SArgs_PtrToChar) (UnixArgs_GetArgV ()))+(n*sizeof (SArgs_PtrToChar)))); + a = (void *) (UnixArgs_GetArgV ()); + a = reinterpret_cast (reinterpret_cast (a)+n*sizeof (SArgs_PtrToChar)); + ppc = static_cast (a); (*s) = DynamicStrings_InitStringCharStar (reinterpret_cast ((*ppc))); return true; } diff --git a/gcc/m2/mc-boot/GStdIO.cc b/gcc/m2/mc-boot/GStdIO.cc index b3ab5c9..bf25ba2 100644 --- a/gcc/m2/mc-boot/GStdIO.cc +++ b/gcc/m2/mc-boot/GStdIO.cc @@ -194,7 +194,7 @@ extern "C" StdIO_ProcWrite StdIO_GetCurrentOutput (void) M2RTS_HALT (-1); __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/StdIO.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/StdIO.def", 25, 1); __builtin_unreachable (); } @@ -253,7 +253,7 @@ extern "C" StdIO_ProcRead StdIO_GetCurrentInput (void) M2RTS_HALT (-1); __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/StdIO.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/StdIO.def", 25, 1); __builtin_unreachable (); } diff --git a/gcc/m2/mc-boot/GStringConvert.cc b/gcc/m2/mc-boot/GStringConvert.cc index 4178d89..5d07bd1 100644 --- a/gcc/m2/mc-boot/GStringConvert.cc +++ b/gcc/m2/mc-boot/GStringConvert.cc @@ -1915,7 +1915,7 @@ extern "C" DynamicStrings_String StringConvert_ToSigFig (DynamicStrings_String s int point; unsigned int poTen; - Assert ((IsDigit (DynamicStrings_char (s, 0))) || ((DynamicStrings_char (s, 0)) == '.'), (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/StringConvert.mod", 54, 1220, (const char *) "ToSigFig", 8); + Assert ((IsDigit (DynamicStrings_char (s, 0))) || ((DynamicStrings_char (s, 0)) == '.'), (const char *) "../../gcc/m2/gm2-libs/StringConvert.mod", 39, 1220, (const char *) "ToSigFig", 8); point = DynamicStrings_Index (s, '.', 0); if (point < 0) { @@ -1967,7 +1967,7 @@ extern "C" DynamicStrings_String StringConvert_ToDecimalPlaces (DynamicStrings_S { int point; - Assert ((IsDigit (DynamicStrings_char (s, 0))) || ((DynamicStrings_char (s, 0)) == '.'), (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/StringConvert.mod", 54, 1069, (const char *) "ToDecimalPlaces", 15); + Assert ((IsDigit (DynamicStrings_char (s, 0))) || ((DynamicStrings_char (s, 0)) == '.'), (const char *) "../../gcc/m2/gm2-libs/StringConvert.mod", 39, 1069, (const char *) "ToDecimalPlaces", 15); point = DynamicStrings_Index (s, '.', 0); if (point < 0) { diff --git a/gcc/m2/mc-boot/GSysStorage.cc b/gcc/m2/mc-boot/GSysStorage.cc index b5c2275..d1d958d 100644 --- a/gcc/m2/mc-boot/GSysStorage.cc +++ b/gcc/m2/mc-boot/GSysStorage.cc @@ -94,7 +94,7 @@ extern "C" void SysStorage_ALLOCATE (void * *a, unsigned int size) (*a) = libc_malloc (static_cast (size)); if ((*a) == NULL) { - Debug_Halt ((const char *) "out of memory error", 19, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/SysStorage.mod", 51, (const char *) "ALLOCATE", 8, 51); + Debug_Halt ((const char *) "out of memory error", 19, (const char *) "../../gcc/m2/gm2-libs/SysStorage.mod", 36, (const char *) "ALLOCATE", 8, 51); } if (enableTrace && trace) { @@ -119,7 +119,7 @@ extern "C" void SysStorage_DEALLOCATE (void * *a, unsigned int size) } if ((libc_memset ((*a), 0, static_cast (size))) != (*a)) { - Debug_Halt ((const char *) "memset should have returned the first parameter", 47, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/SysStorage.mod", 51, (const char *) "DEALLOCATE", 10, 78); + Debug_Halt ((const char *) "memset should have returned the first parameter", 47, (const char *) "../../gcc/m2/gm2-libs/SysStorage.mod", 36, (const char *) "DEALLOCATE", 10, 78); } } if (enableDeallocation) @@ -164,7 +164,7 @@ extern "C" void SysStorage_REALLOCATE (void * *a, unsigned int size) (*a) = libc_realloc ((*a), static_cast (size)); if ((*a) == NULL) { - Debug_Halt ((const char *) "out of memory error", 19, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/SysStorage.mod", 51, (const char *) "REALLOCATE", 10, 122); + Debug_Halt ((const char *) "out of memory error", 19, (const char *) "../../gcc/m2/gm2-libs/SysStorage.mod", 36, (const char *) "REALLOCATE", 10, 122); } if (enableTrace && trace) { diff --git a/gcc/m2/mc-boot/Gdecl.cc b/gcc/m2/mc-boot/Gdecl.cc index f96d2f9..654cb0f 100644 --- a/gcc/m2/mc-boot/Gdecl.cc +++ b/gcc/m2/mc-boot/Gdecl.cc @@ -2781,7 +2781,7 @@ extern "C" int libc_dup (int d); extern "C" int libc_close (int d); extern "C" int libc_open (void * filename, int oflag, ...); extern "C" int libc_creat (void * filename, unsigned int mode); -extern "C" long int libc_lseek (int fd, long int offset, int whence); +extern "C" ssize_t libc_lseek (int fd, ssize_t offset, int whence); extern "C" void libc_perror (const char *string_, unsigned int _string_high); extern "C" int libc_readv (int fd, void * v, int n); extern "C" int libc_writev (int fd, void * v, int n); @@ -6705,7 +6705,7 @@ static decl_node newNode (decl_nodeT k) d->at.firstUsed = 0; return d; } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -7065,7 +7065,7 @@ static decl_node addToScope (decl_node n) } M2RTS_HALT (-1); __builtin_unreachable (); - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -7143,7 +7143,7 @@ static void setUnary (decl_node u, decl_nodeT k, decl_node a, decl_node t) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -7426,7 +7426,7 @@ static void putFieldVarient (decl_node f, decl_node v) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } switch (f->kind) @@ -7437,7 +7437,7 @@ static void putFieldVarient (decl_node f, decl_node v) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -7488,7 +7488,7 @@ static decl_node putFieldRecord (decl_node r, nameKey_Name tag, decl_node type, default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } /* fill in, n. */ @@ -7546,7 +7546,7 @@ static void putVarientTag (decl_node v, decl_node tag) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -7570,7 +7570,7 @@ static decl_node getParent (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } /* static analysis guarentees a RETURN statement will be used before here. */ @@ -7598,7 +7598,7 @@ static decl_node getRecord (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } /* static analysis guarentees a RETURN statement will be used before here. */ @@ -7778,7 +7778,7 @@ static bool getConstExpComplete (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } /* static analysis guarentees a RETURN statement will be used before here. */ @@ -7883,7 +7883,7 @@ static decl_node makeVal (decl_node params) M2RTS_HALT (-1); __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -7904,7 +7904,7 @@ static decl_node makeCast (decl_node c, decl_node p) M2RTS_HALT (-1); __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -8414,7 +8414,7 @@ static decl_node makeUnary (decl_nodeT k, decl_node e, decl_node res) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -8508,7 +8508,7 @@ static DynamicStrings_String getStringContents (decl_node n) } M2RTS_HALT (-1); __builtin_unreachable (); - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -8644,7 +8644,7 @@ static decl_node doMakeBinary (decl_nodeT k, decl_node l, decl_node r, decl_node default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } return n; @@ -9244,12 +9244,12 @@ static decl_node doGetExprType (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } M2RTS_HALT (-1); __builtin_unreachable (); - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -9388,12 +9388,12 @@ static decl_node getSymScope (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } M2RTS_HALT (-1); __builtin_unreachable (); - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -9705,7 +9705,7 @@ static bool needsParen (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } return true; @@ -9814,7 +9814,7 @@ static void doPolyBinary (mcPretty_pretty p, decl_nodeT op, decl_node left, decl default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -9840,7 +9840,7 @@ static void doPolyBinary (mcPretty_pretty p, decl_nodeT op, decl_node left, decl default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -10118,7 +10118,7 @@ static decl_node doGetLastOp (decl_node a, decl_node b) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } /* static analysis guarentees a RETURN statement will be used before here. */ @@ -10772,7 +10772,7 @@ static void doExprC (mcPretty_pretty p, decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -10977,7 +10977,7 @@ static void doExprM2 (mcPretty_pretty p, decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -11149,7 +11149,7 @@ static DynamicStrings_String replaceChar (DynamicStrings_String s, char ch, cons return s; } } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -11209,7 +11209,7 @@ static unsigned int countChar (DynamicStrings_String s, char ch) return c; } } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -12268,7 +12268,7 @@ static decl_node doMin (decl_node n) M2RTS_HALT (-1); /* finish the cacading elsif statement. */ __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -12349,7 +12349,7 @@ static decl_node doMax (decl_node n) M2RTS_HALT (-1); /* finish the cacading elsif statement. */ __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -12655,7 +12655,7 @@ static void doBaseC (mcPretty_pretty p, decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } mcPretty_setNeedSpace (p); @@ -12745,7 +12745,7 @@ static void doSystemC (mcPretty_pretty p, decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -16099,7 +16099,7 @@ static void doCreal (mcPretty_pretty p, decl_node t) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -16130,7 +16130,7 @@ static void doCimag (mcPretty_pretty p, decl_node t) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -16261,7 +16261,7 @@ static void doIntrinsicC (mcPretty_pretty p, decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } outText (p, (const char *) ";", 1); @@ -17437,7 +17437,7 @@ static void dbs (decl_dependentState s, decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } if (n != NULL) @@ -18330,10 +18330,10 @@ static decl_dependentState doDependants (alists_alist l, decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -18430,7 +18430,7 @@ static void visitIntrinsicFunction (alists_alist v, decl_node n, decl_nodeProced default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -19429,7 +19429,7 @@ static void visitDependants (alists_alist v, decl_node n, decl_nodeProcedure p) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -19776,12 +19776,12 @@ static DynamicStrings_String genKind (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } M2RTS_HALT (-1); __builtin_unreachable (); - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -20956,7 +20956,7 @@ static void doBaseM2 (mcPretty_pretty p, decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } mcPretty_setNeedSpace (p); @@ -20982,7 +20982,7 @@ static void doSystemM2 (mcPretty_pretty p, decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -22193,10 +22193,10 @@ static decl_node doDupExpr (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -22526,7 +22526,7 @@ extern "C" bool decl_isVisited (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } /* static analysis guarentees a RETURN statement will be used before here. */ @@ -22556,7 +22556,7 @@ extern "C" void decl_unsetVisited (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -22584,7 +22584,7 @@ extern "C" void decl_setVisited (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -22612,7 +22612,7 @@ extern "C" void decl_setEnumsComplete (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -22640,7 +22640,7 @@ extern "C" bool decl_getEnumsComplete (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } /* static analysis guarentees a RETURN statement will be used before here. */ @@ -22861,7 +22861,7 @@ extern "C" decl_node decl_lookupInScope (decl_node scope, nameKey_Name n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } /* static analysis guarentees a RETURN statement will be used before here. */ @@ -23236,12 +23236,12 @@ extern "C" decl_node decl_getType (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } M2RTS_HALT (-1); __builtin_unreachable (); - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -23635,7 +23635,7 @@ extern "C" decl_node decl_getScope (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } /* static analysis guarentees a RETURN statement will be used before here. */ @@ -24290,7 +24290,7 @@ extern "C" decl_node decl_makeVarient (decl_node r) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } return n; @@ -24743,6 +24743,10 @@ extern "C" nameKey_Name decl_getSymName (decl_node n) return nameKey_makeKey ((const char *) "MIN", 3); break; + case decl_pointerref: + return nameKey_NulName; + break; + case decl_funccall: return nameKey_NulName; break; @@ -24757,7 +24761,7 @@ extern "C" nameKey_Name decl_getSymName (decl_node n) __builtin_unreachable (); break; } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -24795,7 +24799,7 @@ extern "C" decl_node decl_import (decl_node m, decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } importEnumFields (m, n); @@ -24924,7 +24928,7 @@ extern "C" void decl_setSource (decl_node n, nameKey_Name s) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -24952,7 +24956,7 @@ extern "C" nameKey_Name decl_getSource (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } /* static analysis guarentees a RETURN statement will be used before here. */ @@ -25395,7 +25399,7 @@ extern "C" void decl_addParameter (decl_node proc, decl_node param) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -25488,7 +25492,7 @@ extern "C" decl_node decl_makeBinaryTok (mcReserved_toktype op, decl_node l, dec M2RTS_HALT (-1); /* most likely op needs a clause as above. */ __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -25520,7 +25524,7 @@ extern "C" decl_node decl_makeUnaryTok (mcReserved_toktype op, decl_node e) M2RTS_HALT (-1); /* most likely op needs a clause as above. */ __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + ReturnException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } @@ -25958,7 +25962,7 @@ extern "C" void decl_setConstExpComplete (decl_node n) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -26323,7 +26327,7 @@ extern "C" void decl_putBegin (decl_node b, decl_node s) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -26350,7 +26354,7 @@ extern "C" void decl_putFinally (decl_node b, decl_node s) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } } @@ -26978,7 +26982,7 @@ extern "C" void decl_out (void) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/decl.def", 20, 1); + CaseException ("../../gcc/m2/mc/decl.def", 20, 1); __builtin_unreachable (); } closeOutput (); diff --git a/gcc/m2/mc-boot/Gkeyc.cc b/gcc/m2/mc-boot/Gkeyc.cc index 24744ff..0deb633 100644 --- a/gcc/m2/mc-boot/Gkeyc.cc +++ b/gcc/m2/mc-boot/Gkeyc.cc @@ -928,7 +928,7 @@ static bool mangleN (nameKey_Name n, DynamicStrings_String *m, bool scopes) return true; } } - ReturnException ("../../gcc-read-write/gcc/m2/mc/keyc.def", 20, 1); + ReturnException ("../../gcc/m2/mc/keyc.def", 20, 1); __builtin_unreachable (); } diff --git a/gcc/m2/mc-boot/Glibc.h b/gcc/m2/mc-boot/Glibc.h index 9b3e005..382b737 100644 --- a/gcc/m2/mc-boot/Glibc.h +++ b/gcc/m2/mc-boot/Glibc.h @@ -192,7 +192,7 @@ EXTERN int libc_creat (void * filename, unsigned int mode); off_t lseek(int fildes, off_t offset, int whence); */ -EXTERN long int libc_lseek (int fd, long int offset, int whence); +EXTERN ssize_t libc_lseek (int fd, ssize_t offset, int whence); /* perror - writes errno and string. (ARRAY OF CHAR is translated onto ADDRESS). diff --git a/gcc/m2/mc-boot/GmcComment.cc b/gcc/m2/mc-boot/GmcComment.cc index c1a14c8..f17fb19 100644 --- a/gcc/m2/mc-boot/GmcComment.cc +++ b/gcc/m2/mc-boot/GmcComment.cc @@ -258,7 +258,7 @@ static void dumpComment (mcComment_commentDesc cd) default: - CaseException ("../../gcc-read-write/gcc/m2/mc/mcComment.def", 20, 1); + CaseException ("../../gcc/m2/mc/mcComment.def", 20, 1); __builtin_unreachable (); } if (cd->used) diff --git a/gcc/m2/mc-boot/GmcComp.cc b/gcc/m2/mc-boot/GmcComp.cc index 70b1a71..33c8201 100644 --- a/gcc/m2/mc-boot/GmcComp.cc +++ b/gcc/m2/mc-boot/GmcComp.cc @@ -295,7 +295,7 @@ static decl_node examineCompilationUnit (void) } mcflex_mcError (DynamicStrings_string (DynamicStrings_InitString ((const char *) "failed to find module name", 26))); libc_exit (1); - ReturnException ("../../gcc-read-write/gcc/m2/mc/mcComp.def", 20, 1); + ReturnException ("../../gcc/m2/mc/mcComp.def", 20, 1); __builtin_unreachable (); } @@ -325,7 +325,7 @@ static decl_node peepInto (DynamicStrings_String s) mcPrintf_fprintf1 (FIO_StdErr, (const char *) "failed to open %s\\n", 19, (const unsigned char *) &s, (sizeof (s)-1)); libc_exit (1); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/mcComp.def", 20, 1); + ReturnException ("../../gcc/m2/mc/mcComp.def", 20, 1); __builtin_unreachable (); } diff --git a/gcc/m2/mc-boot/GmcDebug.cc b/gcc/m2/mc-boot/GmcDebug.cc index 0d134b6..f891959 100644 --- a/gcc/m2/mc-boot/GmcDebug.cc +++ b/gcc/m2/mc-boot/GmcDebug.cc @@ -55,7 +55,7 @@ extern "C" void mcDebug_assert (bool q) { if (! q) { - mcError_internalError ((const char *) "assert failed", 13, (const char *) "../../gcc-read-write/gcc/m2/mc/mcDebug.mod", 42, 35); + mcError_internalError ((const char *) "assert failed", 13, (const char *) "../../gcc/m2/mc/mcDebug.mod", 27, 35); } } diff --git a/gcc/m2/mc-boot/GmcMetaError.cc b/gcc/m2/mc-boot/GmcMetaError.cc index 32f6efa..b4f483b 100644 --- a/gcc/m2/mc-boot/GmcMetaError.cc +++ b/gcc/m2/mc-boot/GmcMetaError.cc @@ -409,7 +409,7 @@ static void internalFormat (DynamicStrings_String s, int i, const char *m_, unsi s = DynamicStrings_ConCatChar (s, '^'); s = SFIO_WriteS (FIO_StdOut, s); FIO_WriteLine (FIO_StdOut); - mcError_internalError ((const char *) m, _m_high, (const char *) "../../gcc-read-write/gcc/m2/mc/mcMetaError.mod", 46, 97); + mcError_internalError ((const char *) m, _m_high, (const char *) "../../gcc/m2/mc/mcMetaError.mod", 31, 97); } @@ -421,7 +421,7 @@ static DynamicStrings_String x (DynamicStrings_String a, DynamicStrings_String b { if (a != b) { - mcError_internalError ((const char *) "different string returned", 25, (const char *) "../../gcc-read-write/gcc/m2/mc/mcMetaError.mod", 46, 109); + mcError_internalError ((const char *) "different string returned", 25, (const char *) "../../gcc/m2/mc/mcMetaError.mod", 31, 109); } return a; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -735,7 +735,7 @@ static mcError_error doError (mcError_error e, mcMetaError_errorType t, unsigned case mcMetaError_chained: if (e == NULL) { - mcError_internalError ((const char *) "should not be chaining an error onto an empty error note", 56, (const char *) "../../gcc-read-write/gcc/m2/mc/mcMetaError.mod", 46, 355); + mcError_internalError ((const char *) "should not be chaining an error onto an empty error note", 56, (const char *) "../../gcc/m2/mc/mcMetaError.mod", 31, 355); } else { @@ -759,7 +759,7 @@ static mcError_error doError (mcError_error e, mcMetaError_errorType t, unsigned default: - mcError_internalError ((const char *) "unexpected enumeration value", 28, (const char *) "../../gcc-read-write/gcc/m2/mc/mcMetaError.mod", 46, 369); + mcError_internalError ((const char *) "unexpected enumeration value", 28, (const char *) "../../gcc/m2/mc/mcMetaError.mod", 31, 369); break; } return e; diff --git a/gcc/m2/mc-boot/GmcStack.cc b/gcc/m2/mc-boot/GmcStack.cc index b08e918..c35fef3 100644 --- a/gcc/m2/mc-boot/GmcStack.cc +++ b/gcc/m2/mc-boot/GmcStack.cc @@ -166,7 +166,7 @@ extern "C" void * mcStack_pop (mcStack_stack s) Indexing_DeleteIndice (s->list, Indexing_HighIndice (s->list)); return a; } - ReturnException ("../../gcc-read-write/gcc/m2/mc/mcStack.def", 20, 1); + ReturnException ("../../gcc/m2/mc/mcStack.def", 20, 1); __builtin_unreachable (); } @@ -216,7 +216,7 @@ extern "C" void * mcStack_access (mcStack_stack s, unsigned int i) { return Indexing_GetIndice (s->list, i); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/mcStack.def", 20, 1); + ReturnException ("../../gcc/m2/mc/mcStack.def", 20, 1); __builtin_unreachable (); } diff --git a/gcc/m2/mc-boot/GmcStream.cc b/gcc/m2/mc-boot/GmcStream.cc index 81597b6..baf301a 100644 --- a/gcc/m2/mc-boot/GmcStream.cc +++ b/gcc/m2/mc-boot/GmcStream.cc @@ -181,10 +181,19 @@ static void copy (mcStream_ptrToFile p) s = DynamicStrings_InitStringCharStar (FIO_getFileName (f)); FIO_Close (f); f = SFIO_OpenToRead (s); - while (! (FIO_EOF (f))) + while ((! (FIO_EOF (f))) && (FIO_IsNoError (f))) { b = FIO_ReadNBytes (f, maxBuffer, &buffer); - b = FIO_WriteNBytes (destFile, b, &buffer); + if (FIO_IsNoError (f)) + { + b = FIO_WriteNBytes (destFile, b, &buffer); + } + else if (! (FIO_EOF (f))) + { + /* avoid dangling else. */ + libc_printf ((const char *) "mcStream.mod:copy: error seen when reading file fragment: %s\\n", 62, DynamicStrings_string (s)); + libc_exit (1); + } } FIO_Close (f); } diff --git a/gcc/m2/mc-boot/GnameKey.cc b/gcc/m2/mc-boot/GnameKey.cc index 322a6c4..2b23666 100644 --- a/gcc/m2/mc-boot/GnameKey.cc +++ b/gcc/m2/mc-boot/GnameKey.cc @@ -324,7 +324,7 @@ extern "C" nameKey_Name nameKey_makeKey (const char *a_, unsigned int _a_high) (*p) = ASCII_nul; return doMakeKey (n, higha); } - ReturnException ("../../gcc-read-write/gcc/m2/mc/nameKey.def", 20, 1); + ReturnException ("../../gcc/m2/mc/nameKey.def", 20, 1); __builtin_unreachable (); } @@ -374,7 +374,7 @@ extern "C" nameKey_Name nameKey_makekey (void * a) return doMakeKey (n, higha); } } - ReturnException ("../../gcc-read-write/gcc/m2/mc/nameKey.def", 20, 1); + ReturnException ("../../gcc/m2/mc/nameKey.def", 20, 1); __builtin_unreachable (); } diff --git a/gcc/m2/mc-boot/GsymbolKey.cc b/gcc/m2/mc-boot/GsymbolKey.cc index 8b01133..8a396ef 100644 --- a/gcc/m2/mc-boot/GsymbolKey.cc +++ b/gcc/m2/mc-boot/GsymbolKey.cc @@ -143,7 +143,7 @@ static void findNodeAndParentInTree (symbolKey_symbolTree t, nameKey_Name n, sym (*father) = t; if (t == NULL) { - Debug_Halt ((const char *) "parameter t should never be NIL", 31, (const char *) "../../gcc-read-write/gcc/m2/mc/symbolKey.mod", 44, (const char *) "findNodeAndParentInTree", 23, 203); + Debug_Halt ((const char *) "parameter t should never be NIL", 31, (const char *) "../../gcc/m2/mc/symbolKey.mod", 29, (const char *) "findNodeAndParentInTree", 23, 203); } (*child) = t->left; if ((*child) != NULL) @@ -286,7 +286,7 @@ extern "C" void symbolKey_putSymKey (symbolKey_symbolTree t, nameKey_Name name, } else { - Debug_Halt ((const char *) "symbol already stored", 21, (const char *) "../../gcc-read-write/gcc/m2/mc/symbolKey.mod", 44, (const char *) "putSymKey", 9, 119); + Debug_Halt ((const char *) "symbol already stored", 21, (const char *) "../../gcc/m2/mc/symbolKey.mod", 29, (const char *) "putSymKey", 9, 119); } } @@ -353,7 +353,7 @@ extern "C" void symbolKey_delSymKey (symbolKey_symbolTree t, nameKey_Name name) } else { - Debug_Halt ((const char *) "trying to delete a symbol that is not in the tree - the compiler never expects this to occur", 92, (const char *) "../../gcc-read-write/gcc/m2/mc/symbolKey.mod", 44, (const char *) "delSymKey", 9, 186); + Debug_Halt ((const char *) "trying to delete a symbol that is not in the tree - the compiler never expects this to occur", 92, (const char *) "../../gcc/m2/mc/symbolKey.mod", 29, (const char *) "delSymKey", 9, 186); } } diff --git a/gcc/m2/mc-boot/Gvarargs.cc b/gcc/m2/mc-boot/Gvarargs.cc index 22aef2b..23bd7cd 100644 --- a/gcc/m2/mc-boot/Gvarargs.cc +++ b/gcc/m2/mc-boot/Gvarargs.cc @@ -213,7 +213,8 @@ extern "C" varargs_vararg varargs_copy (varargs_vararg v) for (j=0; j<=c->nArgs; j++) { offset = (unsigned int ) (((varargs_ptrToByte) (v->contents))-((varargs_ptrToByte) (v->arg.array[j].ptr))); - c->arg.array[j].ptr = reinterpret_cast ((varargs_ptrToByte) (((varargs_ptrToByte) (c->contents))+offset)); + c->arg.array[j].ptr = reinterpret_cast ((varargs_ptrToByte) (c->contents)); + c->arg.array[j].ptr = reinterpret_cast (reinterpret_cast (c->arg.array[j].ptr)+offset); c->arg.array[j].len = v->arg.array[j].len; } return c; diff --git a/gcc/m2/mc-boot/Gwrapc.h b/gcc/m2/mc-boot/Gwrapc.h index 0ab5a1d..e4db1e2 100644 --- a/gcc/m2/mc-boot/Gwrapc.h +++ b/gcc/m2/mc-boot/Gwrapc.h @@ -118,6 +118,51 @@ EXTERN int wrapc_isfinitef (float x); */ EXTERN int wrapc_isfinitel (long double x); + +/* + isnan - provide non builtin alternative to the gcc builtin isnan. + Returns 1 if x is a NaN otherwise return 0. +*/ + +EXTERN int wrapc_isnan (double x); + +/* + isnanf - provide non builtin alternative to the gcc builtin isnanf. + Returns 1 if x is a NaN otherwise return 0. +*/ + +EXTERN int wrapc_isnanf (float x); + +/* + isnanl - provide non builtin alternative to the gcc builtin isnanl. + Returns 1 if x is a NaN otherwise return 0. +*/ + +EXTERN int wrapc_isnanl (long double x); + +/* + SeekSet - return the system libc SEEK_SET value. +*/ + +EXTERN int wrapc_SeekSet (void); + +/* + SeekEnd - return the system libc SEEK_END value. +*/ + +EXTERN int wrapc_SeekEnd (void); + +/* + ReadOnly - return the system value of O_RDONLY. +*/ + +EXTERN unsigned int wrapc_ReadOnly (void); + +/* + WriteOnly - return the system value of O_WRONLY. +*/ + +EXTERN unsigned int wrapc_WriteOnly (void); # ifdef __cplusplus } # endif diff --git a/gcc/m2/mc/decl.mod b/gcc/m2/mc/decl.mod index 084942f..3d1b57f 100644 --- a/gcc/m2/mc/decl.mod +++ b/gcc/m2/mc/decl.mod @@ -4243,6 +4243,7 @@ BEGIN im : RETURN makeKey ('IM') | max : RETURN makeKey ('MAX') | min : RETURN makeKey ('MIN') | + pointerref : RETURN NulName | funccall : RETURN NulName | identlist : RETURN NulName diff --git a/gcc/m2/mc/mcStream.mod b/gcc/m2/mc/mcStream.mod index 066d3ac..b29045e 100644 --- a/gcc/m2/mc/mcStream.mod +++ b/gcc/m2/mc/mcStream.mod @@ -22,8 +22,8 @@ along with GNU Modula-2; see the file COPYING3. If not see IMPLEMENTATION MODULE mcStream ; -FROM FIO IMPORT File, OpenToWrite, OpenToRead, EOF, ReadNBytes, WriteNBytes, Close, getFileName ; -FROM libc IMPORT unlink, printf, getpid ; +FROM FIO IMPORT File, OpenToWrite, OpenToRead, EOF, ReadNBytes, WriteNBytes, Close, getFileName, IsNoError ; +FROM libc IMPORT unlink, printf, getpid, exit ; FROM Indexing IMPORT InitIndex, InBounds, HighIndice, LowIndice, PutIndice, GetIndice, Index, ForeachIndiceInIndexDo ; FROM DynamicStrings IMPORT String, InitString, InitStringCharStar, string ; FROM FormatStrings IMPORT Sprintf2 ; @@ -134,9 +134,17 @@ BEGIN s := InitStringCharStar(getFileName (f)) ; Close (f) ; f := SFIO.OpenToRead (s) ; - WHILE NOT EOF (f) DO + WHILE (NOT EOF (f)) AND IsNoError (f) DO b := ReadNBytes (f, HIGH (buffer), ADR (buffer)) ; - b := WriteNBytes (destFile, b, ADR (buffer)) + IF IsNoError (f) + THEN + b := WriteNBytes (destFile, b, ADR (buffer)) + ELSIF NOT EOF (f) + THEN + printf ("mcStream.mod:copy: error seen when reading file fragment: %s\n", + string (s)) ; + exit (1) + END END ; Close (f) END diff --git a/gcc/m2/mc/varargs.mod b/gcc/m2/mc/varargs.mod index 7e4bcf3..1a99f70 100644 --- a/gcc/m2/mc/varargs.mod +++ b/gcc/m2/mc/varargs.mod @@ -108,7 +108,8 @@ BEGIN contents := memcpy (contents, v^.contents, size) ; FOR j := 0 TO nArgs DO offset := VAL (CARDINAL, VAL (ptrToByte, v^.contents) - VAL (ptrToByte, v^.arg[j].ptr)) ; - arg[j].ptr := VAL (ptrToByte, VAL (ptrToByte, contents) + offset) ; + arg[j].ptr := VAL (ptrToByte, contents) ; + INC (arg[j].ptr, offset) ; arg[j].len := v^.arg[j].len ; END END ; diff --git a/gcc/m2/pge-boot/GDynamicStrings.cc b/gcc/m2/pge-boot/GDynamicStrings.cc index 542c515..997802b 100644 --- a/gcc/m2/pge-boot/GDynamicStrings.cc +++ b/gcc/m2/pge-boot/GDynamicStrings.cc @@ -191,6 +191,12 @@ extern "C" DynamicStrings_String DynamicStrings_ConCatChar (DynamicStrings_Strin extern "C" DynamicStrings_String DynamicStrings_Assign (DynamicStrings_String a, DynamicStrings_String b); /* + ReplaceChar - returns string s after it has changed all occurances of from to to. +*/ + +extern "C" DynamicStrings_String DynamicStrings_ReplaceChar (DynamicStrings_String s, char from, char to); + +/* Dup - duplicate a String, s, returning the copy of s. */ @@ -1222,7 +1228,7 @@ static void ConcatContents (DynamicStrings_Contents *c, const char *a_, unsigned (*c).next->contents.next = NULL; ConcatContents (&(*c).next->contents, (const char *) a, _a_high, h, o); AddDebugInfo ((*c).next); - (*c).next = AssignDebug ((*c).next, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 722, (const char *) "ConcatContents", 14); + (*c).next = AssignDebug ((*c).next, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 722, (const char *) "ConcatContents", 14); } else { @@ -1320,7 +1326,7 @@ static void ConcatContentsAddress (DynamicStrings_Contents *c, void * a, unsigne AddDebugInfo ((*c).next); if (TraceOn) { - (*c).next = AssignDebug ((*c).next, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 917, (const char *) "ConcatContentsAddress", 21); + (*c).next = AssignDebug ((*c).next, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 917, (const char *) "ConcatContentsAddress", 21); } } else @@ -1545,7 +1551,7 @@ extern "C" DynamicStrings_String DynamicStrings_InitString (const char *a_, unsi AddDebugInfo (s); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 758, (const char *) "InitString", 10); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 758, (const char *) "InitString", 10); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -1648,7 +1654,7 @@ extern "C" DynamicStrings_String DynamicStrings_InitStringCharStar (void * a) AddDebugInfo (s); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 957, (const char *) "InitStringCharStar", 18); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 957, (const char *) "InitStringCharStar", 18); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -1673,7 +1679,7 @@ extern "C" DynamicStrings_String DynamicStrings_InitStringChar (char ch) s = DynamicStrings_InitString ((const char *) &a.array[0], 1); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 977, (const char *) "InitStringChar", 14); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 977, (const char *) "InitStringChar", 14); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -1819,6 +1825,35 @@ extern "C" DynamicStrings_String DynamicStrings_Assign (DynamicStrings_String a, /* + ReplaceChar - returns string s after it has changed all occurances of from to to. +*/ + +extern "C" DynamicStrings_String DynamicStrings_ReplaceChar (DynamicStrings_String s, char from, char to) +{ + DynamicStrings_String t; + unsigned int i; + + t = s; + while (t != NULL) + { + i = 0; + while (i < t->contents.len) + { + if (t->contents.buf.array[i] == from) + { + t->contents.buf.array[i] = to; + } + i += 1; + } + t = t->contents.next; + } + return s; + /* static analysis guarentees a RETURN statement will be used before here. */ + __builtin_unreachable (); +} + + +/* Dup - duplicate a String, s, returning the copy of s. */ @@ -1831,7 +1866,7 @@ extern "C" DynamicStrings_String DynamicStrings_Dup (DynamicStrings_String s) s = DynamicStrings_Assign (DynamicStrings_InitString ((const char *) "", 0), s); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1173, (const char *) "Dup", 3); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1198, (const char *) "Dup", 3); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -1853,7 +1888,7 @@ extern "C" DynamicStrings_String DynamicStrings_Add (DynamicStrings_String a, Dy a = DynamicStrings_ConCat (DynamicStrings_ConCat (DynamicStrings_InitString ((const char *) "", 0), a), b); if (TraceOn) { - a = AssignDebug (a, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1193, (const char *) "Add", 3); + a = AssignDebug (a, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1218, (const char *) "Add", 3); } return a; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -1918,7 +1953,7 @@ extern "C" bool DynamicStrings_EqualCharStar (DynamicStrings_String s, void * a) t = DynamicStrings_InitStringCharStar (a); if (TraceOn) { - t = AssignDebug (t, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1250, (const char *) "EqualCharStar", 13); + t = AssignDebug (t, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1275, (const char *) "EqualCharStar", 13); } t = AddToGarbage (t, s); if (DynamicStrings_Equal (t, s)) @@ -1956,7 +1991,7 @@ extern "C" bool DynamicStrings_EqualArray (DynamicStrings_String s, const char * t = DynamicStrings_InitString ((const char *) a, _a_high); if (TraceOn) { - t = AssignDebug (t, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1280, (const char *) "EqualArray", 10); + t = AssignDebug (t, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1305, (const char *) "EqualArray", 10); } t = AddToGarbage (t, s); if (DynamicStrings_Equal (t, s)) @@ -1994,7 +2029,7 @@ extern "C" DynamicStrings_String DynamicStrings_Mult (DynamicStrings_String s, u } if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1312, (const char *) "Mult", 4); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1337, (const char *) "Mult", 4); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -2073,7 +2108,7 @@ extern "C" DynamicStrings_String DynamicStrings_Slice (DynamicStrings_String s, AddDebugInfo (t->contents.next); if (TraceOn) { - t->contents.next = AssignDebug (t->contents.next, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1380, (const char *) "Slice", 5); + t->contents.next = AssignDebug (t->contents.next, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1405, (const char *) "Slice", 5); } } t = t->contents.next; @@ -2091,7 +2126,7 @@ extern "C" DynamicStrings_String DynamicStrings_Slice (DynamicStrings_String s, } if (TraceOn) { - d = AssignDebug (d, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1397, (const char *) "Slice", 5); + d = AssignDebug (d, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1422, (const char *) "Slice", 5); } return d; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -2219,7 +2254,7 @@ extern "C" DynamicStrings_String DynamicStrings_RemoveComment (DynamicStrings_St } if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1509, (const char *) "RemoveComment", 13); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1534, (const char *) "RemoveComment", 13); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -2244,7 +2279,7 @@ extern "C" DynamicStrings_String DynamicStrings_RemoveWhitePrefix (DynamicString s = DynamicStrings_Slice (s, (int ) (i), 0); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1621, (const char *) "RemoveWhitePrefix", 17); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1646, (const char *) "RemoveWhitePrefix", 17); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -2269,7 +2304,7 @@ extern "C" DynamicStrings_String DynamicStrings_RemoveWhitePostfix (DynamicStrin s = DynamicStrings_Slice (s, 0, i+1); if (TraceOn) { - s = AssignDebug (s, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, 1643, (const char *) "RemoveWhitePostfix", 18); + s = AssignDebug (s, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, 1668, (const char *) "RemoveWhitePostfix", 18); } return s; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -2636,7 +2671,7 @@ extern "C" DynamicStrings_String DynamicStrings_PopAllocationExemption (bool hal if (frameHead == NULL) { stop (); - M2RTS_Halt ((const char *) "mismatched number of PopAllocation's compared to PushAllocation's", 65, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/DynamicStrings.mod", 55, (const char *) "PopAllocationExemption", 22, 174); + M2RTS_Halt ((const char *) "mismatched number of PopAllocation's compared to PushAllocation's", 65, (const char *) "../../gcc/m2/gm2-libs/DynamicStrings.mod", 40, (const char *) "PopAllocationExemption", 22, 174); } else { diff --git a/gcc/m2/pge-boot/GDynamicStrings.h b/gcc/m2/pge-boot/GDynamicStrings.h index 4484df2..76f4cea 100644 --- a/gcc/m2/pge-boot/GDynamicStrings.h +++ b/gcc/m2/pge-boot/GDynamicStrings.h @@ -125,6 +125,13 @@ EXTERN DynamicStrings_String DynamicStrings_ConCatChar (DynamicStrings_String a, EXTERN DynamicStrings_String DynamicStrings_Assign (DynamicStrings_String a, DynamicStrings_String b); /* + ReplaceChar - returns string s after it has changed all + occurances of from to to. +*/ + +EXTERN DynamicStrings_String DynamicStrings_ReplaceChar (DynamicStrings_String s, char from, char to); + +/* Dup - duplicate a String, s, returning the copy of s. */ diff --git a/gcc/m2/pge-boot/GFIO.cc b/gcc/m2/pge-boot/GFIO.cc index e9fbc12..3e56792 100644 --- a/gcc/m2/pge-boot/GFIO.cc +++ b/gcc/m2/pge-boot/GFIO.cc @@ -47,6 +47,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see # include "GStorage.h" # include "Gmcrts.h" #include +# include #if defined(__cplusplus) # undef NULL # define NULL 0 @@ -59,22 +60,19 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see # include "GStrLib.h" # include "GStorage.h" # include "GNumberIO.h" -# include "Glibc.h" # include "GIndexing.h" # include "GM2RTS.h" +# include "Glibc.h" +# include "Gwrapc.h" typedef unsigned int FIO_File; FIO_File FIO_StdErr; FIO_File FIO_StdOut; FIO_File FIO_StdIn; -# define SEEK_SET 0 -# define SEEK_END 2 -# define UNIXREADONLY 0 -# define UNIXWRITEONLY 1 -# define CreatePermissions 0666 # define MaxBufferLength (1024*16) # define MaxErrorString (1024*8) +# define CreatePermissions 0666 typedef struct FIO_NameInfo_r FIO_NameInfo; typedef struct FIO_buf_r FIO_buf; @@ -198,7 +196,7 @@ extern "C" void FIO_FlushBuffer (FIO_File f); extern "C" unsigned int FIO_ReadNBytes (FIO_File f, unsigned int nBytes, void * dest); /* - ReadAny - reads HIGH(a) bytes into, a. All input + ReadAny - reads HIGH (a) + 1 bytes into, a. All input is fully buffered, unlike ReadNBytes and thus is more suited to small reads. */ @@ -216,7 +214,7 @@ extern "C" void FIO_ReadAny (FIO_File f, unsigned char *a, unsigned int _a_high) extern "C" unsigned int FIO_WriteNBytes (FIO_File f, unsigned int nBytes, void * src); /* - WriteAny - writes HIGH(a) bytes onto, file, f. All output + WriteAny - writes HIGH (a) + 1 bytes onto, file, f. All output is fully buffered, unlike WriteNBytes and thus is more suited to small writes. */ @@ -413,7 +411,7 @@ static int ReadFromBuffer (FIO_File f, void * a, unsigned int nBytes); Useful when performing small reads. */ -static int BufferedRead (FIO_File f, unsigned int nBytes, void * a); +static int BufferedRead (FIO_File f, unsigned int nBytes, void * dest); /* HandleEscape - translates @@ -476,7 +474,7 @@ static void SetEndOfLine (FIO_File f, char ch); Useful when performing small writes. */ -static int BufferedWrite (FIO_File f, unsigned int nBytes, void * a); +static int BufferedWrite (FIO_File f, unsigned int nBytes, void * src); /* PreInitialize - preinitialize the file descriptor. @@ -559,7 +557,7 @@ static FIO_File GetNextFreeDescriptor (void) return f; /* create new slot */ } } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/FIO.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/FIO.def", 25, 1); __builtin_unreachable (); } @@ -676,12 +674,12 @@ static void ConnectToUnix (FIO_File f, bool towrite, bool newfile) } else { - fd->unixfd = libc_open (fd->name.address, UNIXWRITEONLY, 0); + fd->unixfd = libc_open (fd->name.address, (int ) (wrapc_WriteOnly ()), 0); } } else { - fd->unixfd = libc_open (fd->name.address, UNIXREADONLY, 0); + fd->unixfd = libc_open (fd->name.address, (int ) (wrapc_ReadOnly ()), 0); } if (fd->unixfd < 0) { @@ -812,11 +810,11 @@ static int ReadFromBuffer (FIO_File f, void * a, unsigned int nBytes) Useful when performing small reads. */ -static int BufferedRead (FIO_File f, unsigned int nBytes, void * a) +static int BufferedRead (FIO_File f, unsigned int nBytes, void * dest) { typedef unsigned char *BufferedRead__T3; - void * t; + void * src; int total; int n; BufferedRead__T3 p; @@ -838,7 +836,7 @@ static int BufferedRead (FIO_File f, unsigned int nBytes, void * a) if (nBytes == 1) { /* too expensive to call memcpy for 1 character */ - p = static_cast (a); + p = static_cast (dest); (*p) = static_cast ((*fd->buffer->contents).array[fd->buffer->position]); fd->buffer->left -= 1; /* remove consumed byte */ fd->buffer->position += 1; /* move onwards n byte */ @@ -848,13 +846,13 @@ static int BufferedRead (FIO_File f, unsigned int nBytes, void * a) else { n = Min (fd->buffer->left, nBytes); - t = fd->buffer->address; - t = reinterpret_cast (reinterpret_cast (t)+fd->buffer->position); - p = static_cast (libc_memcpy (a, t, static_cast (n))); + src = fd->buffer->address; + src = reinterpret_cast (reinterpret_cast (src)+fd->buffer->position); + p = static_cast (libc_memcpy (dest, src, static_cast (n))); fd->buffer->left -= n; /* remove consumed bytes */ fd->buffer->position += n; /* move onwards n bytes */ /* move onwards ready for direct reads */ - a = reinterpret_cast (reinterpret_cast (a)+n); + dest = reinterpret_cast (reinterpret_cast (dest)+n); nBytes -= n; /* reduce the amount for future direct */ /* read */ total += n; @@ -1239,11 +1237,11 @@ static void SetEndOfLine (FIO_File f, char ch) Useful when performing small writes. */ -static int BufferedWrite (FIO_File f, unsigned int nBytes, void * a) +static int BufferedWrite (FIO_File f, unsigned int nBytes, void * src) { typedef unsigned char *BufferedWrite__T5; - void * t; + void * dest; int total; int n; BufferedWrite__T5 p; @@ -1265,7 +1263,7 @@ static int BufferedWrite (FIO_File f, unsigned int nBytes, void * a) if (nBytes == 1) { /* too expensive to call memcpy for 1 character */ - p = static_cast (a); + p = static_cast (src); (*fd->buffer->contents).array[fd->buffer->position] = static_cast ((*p)); fd->buffer->left -= 1; /* reduce space */ fd->buffer->position += 1; /* move onwards n byte */ @@ -1275,13 +1273,13 @@ static int BufferedWrite (FIO_File f, unsigned int nBytes, void * a) else { n = Min (fd->buffer->left, nBytes); - t = fd->buffer->address; - t = reinterpret_cast (reinterpret_cast (t)+fd->buffer->position); - p = static_cast (libc_memcpy (a, t, static_cast ((unsigned int ) (n)))); + dest = fd->buffer->address; + dest = reinterpret_cast (reinterpret_cast (dest)+fd->buffer->position); + p = static_cast (libc_memcpy (dest, src, static_cast ((unsigned int ) (n)))); fd->buffer->left -= n; /* remove consumed bytes */ fd->buffer->position += n; /* move onwards n bytes */ /* move ready for further writes */ - a = reinterpret_cast (reinterpret_cast (a)+n); + src = reinterpret_cast (reinterpret_cast (src)+n); nBytes -= n; /* reduce the amount for future writes */ total += n; /* reduce the amount for future writes */ } @@ -1689,7 +1687,7 @@ extern "C" unsigned int FIO_ReadNBytes (FIO_File f, unsigned int nBytes, void * /* - ReadAny - reads HIGH(a) bytes into, a. All input + ReadAny - reads HIGH (a) + 1 bytes into, a. All input is fully buffered, unlike ReadNBytes and thus is more suited to small reads. */ @@ -1697,7 +1695,7 @@ extern "C" unsigned int FIO_ReadNBytes (FIO_File f, unsigned int nBytes, void * extern "C" void FIO_ReadAny (FIO_File f, unsigned char *a, unsigned int _a_high) { CheckAccess (f, FIO_openedforread, false); - if ((BufferedRead (f, _a_high, a)) == ((int ) (_a_high))) + if ((BufferedRead (f, _a_high+1, a)) == ((int ) (_a_high+1))) { SetEndOfLine (f, static_cast (a[_a_high])); } @@ -1748,7 +1746,7 @@ extern "C" unsigned int FIO_WriteNBytes (FIO_File f, unsigned int nBytes, void * /* - WriteAny - writes HIGH(a) bytes onto, file, f. All output + WriteAny - writes HIGH (a) + 1 bytes onto, file, f. All output is fully buffered, unlike WriteNBytes and thus is more suited to small writes. */ @@ -1756,7 +1754,7 @@ extern "C" unsigned int FIO_WriteNBytes (FIO_File f, unsigned int nBytes, void * extern "C" void FIO_WriteAny (FIO_File f, unsigned char *a, unsigned int _a_high) { CheckAccess (f, FIO_openedforwrite, true); - if ((BufferedWrite (f, _a_high, a)) == ((int ) (_a_high))) + if ((BufferedWrite (f, _a_high+1, a)) == ((int ) (_a_high+1))) {} /* empty. */ } @@ -2096,7 +2094,7 @@ extern "C" void FIO_SetPositionFromBeginning (FIO_File f, long int pos) fd->buffer->position = 0; fd->buffer->filled = 0; } - offset = libc_lseek (fd->unixfd, pos, SEEK_SET); + offset = static_cast (libc_lseek (fd->unixfd, (ssize_t ) (pos), wrapc_SeekSet ())); if ((offset >= 0) && (pos == offset)) { fd->abspos = pos; @@ -2145,7 +2143,7 @@ extern "C" void FIO_SetPositionFromEnd (FIO_File f, long int pos) fd->buffer->position = 0; fd->buffer->filled = 0; } - offset = libc_lseek (fd->unixfd, pos, SEEK_END); + offset = static_cast (libc_lseek (fd->unixfd, (ssize_t ) (pos), wrapc_SeekEnd ())); if (offset >= 0) { fd->abspos = offset; diff --git a/gcc/m2/pge-boot/GFIO.h b/gcc/m2/pge-boot/GFIO.h index 8404d4b..d823964 100644 --- a/gcc/m2/pge-boot/GFIO.h +++ b/gcc/m2/pge-boot/GFIO.h @@ -135,7 +135,7 @@ EXTERN void FIO_FlushBuffer (FIO_File f); EXTERN unsigned int FIO_ReadNBytes (FIO_File f, unsigned int nBytes, void * dest); /* - ReadAny - reads HIGH(a) bytes into, a. All input + ReadAny - reads HIGH (a) + 1 bytes into, a. All input is fully buffered, unlike ReadNBytes and thus is more suited to small reads. */ @@ -153,7 +153,7 @@ EXTERN void FIO_ReadAny (FIO_File f, unsigned char *a, unsigned int _a_high); EXTERN unsigned int FIO_WriteNBytes (FIO_File f, unsigned int nBytes, void * src); /* - WriteAny - writes HIGH(a) bytes onto, file, f. All output + WriteAny - writes HIGH (a) + 1 bytes onto, file, f. All output is fully buffered, unlike WriteNBytes and thus is more suited to small writes. */ diff --git a/gcc/m2/pge-boot/GIO.cc b/gcc/m2/pge-boot/GIO.cc index 4e650c8..7d391bb 100644 --- a/gcc/m2/pge-boot/GIO.cc +++ b/gcc/m2/pge-boot/GIO.cc @@ -286,12 +286,13 @@ static void dononraw (termios_TERMIOS term) static void Init (void) { - fdState.array[0].IsEof = false; - fdState.array[0].IsRaw = false; - fdState.array[1].IsEof = false; - fdState.array[1].IsRaw = false; - fdState.array[2].IsEof = false; - fdState.array[2].IsRaw = false; + unsigned int fdi; + + for (fdi=0; fdi<=MaxDefaultFd; fdi++) + { + fdState.array[fdi].IsEof = false; + fdState.array[fdi].IsRaw = false; + } } diff --git a/gcc/m2/pge-boot/GIndexing.cc b/gcc/m2/pge-boot/GIndexing.cc index 6197310..c898a24 100644 --- a/gcc/m2/pge-boot/GIndexing.cc +++ b/gcc/m2/pge-boot/GIndexing.cc @@ -228,7 +228,7 @@ extern "C" bool Indexing_InBounds (Indexing_Index i, unsigned int n) { return (n >= i->Low) && (n <= i->High); } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/Indexing.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/Indexing.def", 25, 1); __builtin_unreachable (); } @@ -248,7 +248,7 @@ extern "C" unsigned int Indexing_HighIndice (Indexing_Index i) { return i->High; } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/Indexing.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/Indexing.def", 25, 1); __builtin_unreachable (); } @@ -268,7 +268,7 @@ extern "C" unsigned int Indexing_LowIndice (Indexing_Index i) { return i->Low; } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/Indexing.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/Indexing.def", 25, 1); __builtin_unreachable (); } diff --git a/gcc/m2/pge-boot/GM2Dependent.cc b/gcc/m2/pge-boot/GM2Dependent.cc index a623a04..4a4492a 100644 --- a/gcc/m2/pge-boot/GM2Dependent.cc +++ b/gcc/m2/pge-boot/GM2Dependent.cc @@ -138,6 +138,12 @@ extern "C" void M2Dependent_RegisterModule (void * modulename, void * libname, M extern "C" void M2Dependent_RequestDependant (void * modulename, void * libname, void * dependantmodule, void * dependantlibname); /* + InitDependencyList - initialize all fields of DependencyList. +*/ + +static void InitDependencyList (M2Dependent_DependencyList *depList, PROC proc, M2Dependent_DependencyState state); + +/* CreateModule - creates a new module entry and returns the ModuleChain. */ @@ -358,6 +364,20 @@ static void CheckInitialized (void); /* + InitDependencyList - initialize all fields of DependencyList. +*/ + +static void InitDependencyList (M2Dependent_DependencyList *depList, PROC proc, M2Dependent_DependencyState state) +{ + (*depList).proc = proc; + (*depList).forced = false; + (*depList).forc = false; + (*depList).appl = false; + (*depList).state = state; +} + + +/* CreateModule - creates a new module entry and returns the ModuleChain. */ @@ -371,8 +391,7 @@ static M2Dependent_ModuleChain CreateModule (void * name, void * libname, M2Depe mptr->libname = libname; mptr->init = init; mptr->fini = fini; - mptr->dependency.proc = dependencies; - mptr->dependency.state = M2Dependent_unregistered; + InitDependencyList (&mptr->dependency, dependencies, M2Dependent_unregistered); mptr->prev = NULL; mptr->next = NULL; if (HexTrace) diff --git a/gcc/m2/pge-boot/GM2EXCEPTION.cc b/gcc/m2/pge-boot/GM2EXCEPTION.cc index 43f1acb..274f29a 100644 --- a/gcc/m2/pge-boot/GM2EXCEPTION.cc +++ b/gcc/m2/pge-boot/GM2EXCEPTION.cc @@ -57,13 +57,13 @@ extern "C" M2EXCEPTION_M2Exceptions M2EXCEPTION_M2Exception (void) n = RTExceptions_GetNumber (e); if (n == (UINT_MAX)) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_exException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/M2EXCEPTION.mod")), 47, 6, const_cast (reinterpret_cast("M2Exception")), const_cast (reinterpret_cast("current coroutine is not in the exceptional execution state"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_exException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/M2EXCEPTION.mod")), 47, 6, const_cast (reinterpret_cast("M2Exception")), const_cast (reinterpret_cast("current coroutine is not in the exceptional execution state"))); } else { return (M2EXCEPTION_M2Exceptions) (n); } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/M2EXCEPTION.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/M2EXCEPTION.def", 25, 1); __builtin_unreachable (); } diff --git a/gcc/m2/pge-boot/GNameKey.cc b/gcc/m2/pge-boot/GNameKey.cc index 9adf984..52b90a0 100644 --- a/gcc/m2/pge-boot/GNameKey.cc +++ b/gcc/m2/pge-boot/GNameKey.cc @@ -331,7 +331,7 @@ extern "C" NameKey_Name NameKey_MakeKey (const char *a_, unsigned int _a_high) (*p) = ASCII_nul; return DoMakeKey (n, higha); } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-compiler/NameKey.def", 20, 1); + ReturnException ("../../gcc/m2/gm2-compiler/NameKey.def", 20, 1); __builtin_unreachable (); } @@ -381,7 +381,7 @@ extern "C" NameKey_Name NameKey_makekey (void * a) return DoMakeKey (n, higha); } } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-compiler/NameKey.def", 20, 1); + ReturnException ("../../gcc/m2/gm2-compiler/NameKey.def", 20, 1); __builtin_unreachable (); } @@ -421,12 +421,15 @@ extern "C" unsigned int NameKey_LengthKey (NameKey_Name Key) unsigned int i; NameKey_PtrToChar p; - p = static_cast (NameKey_KeyToCharStar (Key)); i = 0; - while ((*p) != ASCII_nul) + if (Key != NameKey_NulName) { - i += 1; - p += 1; + p = static_cast (NameKey_KeyToCharStar (Key)); + while ((*p) != ASCII_nul) + { + i += 1; + p += 1; + } } return i; /* static analysis guarentees a RETURN statement will be used before here. */ diff --git a/gcc/m2/pge-boot/GPushBackInput.cc b/gcc/m2/pge-boot/GPushBackInput.cc index e0da0cb..6fb0fbe 100644 --- a/gcc/m2/pge-boot/GPushBackInput.cc +++ b/gcc/m2/pge-boot/GPushBackInput.cc @@ -276,7 +276,7 @@ extern "C" char PushBackInput_PutCh (char ch) } else { - Debug_Halt ((const char *) "max push back stack exceeded, increase MaxPushBackStack", 55, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/PushBackInput.mod", 54, (const char *) "PutCh", 5, 151); + Debug_Halt ((const char *) "max push back stack exceeded, increase MaxPushBackStack", 55, (const char *) "../../gcc/m2/gm2-libs/PushBackInput.mod", 39, (const char *) "PutCh", 5, 151); } return ch; /* static analysis guarentees a RETURN statement will be used before here. */ @@ -302,7 +302,7 @@ extern "C" void PushBackInput_PutString (const char *a_, unsigned int _a_high) l -= 1; if ((PushBackInput_PutCh (a[l])) != a[l]) { - Debug_Halt ((const char *) "assert failed", 13, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/PushBackInput.mod", 54, (const char *) "PutString", 9, 132); + Debug_Halt ((const char *) "assert failed", 13, (const char *) "../../gcc/m2/gm2-libs/PushBackInput.mod", 39, (const char *) "PutString", 9, 132); } } } @@ -323,7 +323,7 @@ extern "C" void PushBackInput_PutStr (DynamicStrings_String s) i -= 1; if ((PushBackInput_PutCh (DynamicStrings_char (s, static_cast (i)))) != (DynamicStrings_char (s, static_cast (i)))) { - Debug_Halt ((const char *) "assert failed", 13, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/PushBackInput.mod", 54, (const char *) "PutStr", 6, 113); + Debug_Halt ((const char *) "assert failed", 13, (const char *) "../../gcc/m2/gm2-libs/PushBackInput.mod", 39, (const char *) "PutStr", 6, 113); } } } diff --git a/gcc/m2/pge-boot/GRTExceptions.cc b/gcc/m2/pge-boot/GRTExceptions.cc index d4d0b1c..2b6557e 100644 --- a/gcc/m2/pge-boot/GRTExceptions.cc +++ b/gcc/m2/pge-boot/GRTExceptions.cc @@ -725,7 +725,7 @@ static void AddHandler (RTExceptions_EHBlock e, RTExceptions_Handler h) static void indexf (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_indexException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 614, 9, const_cast (reinterpret_cast("indexf")), const_cast (reinterpret_cast("array index out of bounds"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_indexException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 614, 9, const_cast (reinterpret_cast("indexf")), const_cast (reinterpret_cast("array index out of bounds"))); } @@ -735,7 +735,7 @@ static void indexf (void * a) static void range (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_rangeException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 626, 9, const_cast (reinterpret_cast("range")), const_cast (reinterpret_cast("assignment out of range"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_rangeException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 626, 9, const_cast (reinterpret_cast("range")), const_cast (reinterpret_cast("assignment out of range"))); } @@ -745,7 +745,7 @@ static void range (void * a) static void casef (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_caseSelectException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 638, 9, const_cast (reinterpret_cast("casef")), const_cast (reinterpret_cast("case selector out of range"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_caseSelectException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 638, 9, const_cast (reinterpret_cast("casef")), const_cast (reinterpret_cast("case selector out of range"))); } @@ -755,7 +755,7 @@ static void casef (void * a) static void invalidloc (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_invalidLocation)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 650, 9, const_cast (reinterpret_cast("invalidloc")), const_cast (reinterpret_cast("invalid address referenced"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_invalidLocation)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 650, 9, const_cast (reinterpret_cast("invalidloc")), const_cast (reinterpret_cast("invalid address referenced"))); } @@ -765,7 +765,7 @@ static void invalidloc (void * a) static void function (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_functionException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 662, 9, const_cast (reinterpret_cast("function")), const_cast (reinterpret_cast("... function ... "))); /* --fixme-- what has happened ? */ + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_functionException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 662, 9, const_cast (reinterpret_cast("function")), const_cast (reinterpret_cast("... function ... "))); /* --fixme-- what has happened ? */ } @@ -775,7 +775,7 @@ static void function (void * a) static void wholevalue (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_wholeValueException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 674, 9, const_cast (reinterpret_cast("wholevalue")), const_cast (reinterpret_cast("illegal whole value exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_wholeValueException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 674, 9, const_cast (reinterpret_cast("wholevalue")), const_cast (reinterpret_cast("illegal whole value exception"))); } @@ -785,7 +785,7 @@ static void wholevalue (void * a) static void wholediv (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_wholeDivException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 686, 9, const_cast (reinterpret_cast("wholediv")), const_cast (reinterpret_cast("illegal whole value exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_wholeDivException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 686, 9, const_cast (reinterpret_cast("wholediv")), const_cast (reinterpret_cast("illegal whole value exception"))); } @@ -795,7 +795,7 @@ static void wholediv (void * a) static void realvalue (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_realValueException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 698, 9, const_cast (reinterpret_cast("realvalue")), const_cast (reinterpret_cast("illegal real value exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_realValueException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 698, 9, const_cast (reinterpret_cast("realvalue")), const_cast (reinterpret_cast("illegal real value exception"))); } @@ -805,7 +805,7 @@ static void realvalue (void * a) static void realdiv (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_realDivException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 710, 9, const_cast (reinterpret_cast("realdiv")), const_cast (reinterpret_cast("real number division by zero exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_realDivException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 710, 9, const_cast (reinterpret_cast("realdiv")), const_cast (reinterpret_cast("real number division by zero exception"))); } @@ -815,7 +815,7 @@ static void realdiv (void * a) static void complexvalue (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_complexValueException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 722, 9, const_cast (reinterpret_cast("complexvalue")), const_cast (reinterpret_cast("illegal complex value exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_complexValueException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 722, 9, const_cast (reinterpret_cast("complexvalue")), const_cast (reinterpret_cast("illegal complex value exception"))); } @@ -825,7 +825,7 @@ static void complexvalue (void * a) static void complexdiv (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_complexDivException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 734, 9, const_cast (reinterpret_cast("complexdiv")), const_cast (reinterpret_cast("complex number division by zero exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_complexDivException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 734, 9, const_cast (reinterpret_cast("complexdiv")), const_cast (reinterpret_cast("complex number division by zero exception"))); } @@ -835,7 +835,7 @@ static void complexdiv (void * a) static void protection (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_protException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 746, 9, const_cast (reinterpret_cast("protection")), const_cast (reinterpret_cast("protection exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_protException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 746, 9, const_cast (reinterpret_cast("protection")), const_cast (reinterpret_cast("protection exception"))); } @@ -845,7 +845,7 @@ static void protection (void * a) static void systemf (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_sysException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 758, 9, const_cast (reinterpret_cast("systemf")), const_cast (reinterpret_cast("system exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_sysException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 758, 9, const_cast (reinterpret_cast("systemf")), const_cast (reinterpret_cast("system exception"))); } @@ -855,7 +855,7 @@ static void systemf (void * a) static void coroutine (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_coException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 770, 9, const_cast (reinterpret_cast("coroutine")), const_cast (reinterpret_cast("coroutine exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_coException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 770, 9, const_cast (reinterpret_cast("coroutine")), const_cast (reinterpret_cast("coroutine exception"))); } @@ -865,7 +865,7 @@ static void coroutine (void * a) static void exception (void * a) { - RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_exException)), const_cast (reinterpret_cast("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod")), 782, 9, const_cast (reinterpret_cast("exception")), const_cast (reinterpret_cast("exception exception"))); + RTExceptions_Raise ( ((unsigned int) (M2EXCEPTION_exException)), const_cast (reinterpret_cast("../../gcc/m2/gm2-libs/RTExceptions.mod")), 782, 9, const_cast (reinterpret_cast("exception")), const_cast (reinterpret_cast("exception exception"))); } @@ -1183,13 +1183,13 @@ extern "C" RTExceptions_EHBlock RTExceptions_GetBaseExceptionBlock (void) { if (currentEHB == NULL) { - M2RTS_Halt ((const char *) "currentEHB has not been initialized yet", 39, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.mod", 53, (const char *) "GetBaseExceptionBlock", 21, 600); + M2RTS_Halt ((const char *) "currentEHB has not been initialized yet", 39, (const char *) "../../gcc/m2/gm2-libs/RTExceptions.mod", 38, (const char *) "GetBaseExceptionBlock", 21, 600); } else { return currentEHB; } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/RTExceptions.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/RTExceptions.def", 25, 1); __builtin_unreachable (); } diff --git a/gcc/m2/pge-boot/GStdIO.cc b/gcc/m2/pge-boot/GStdIO.cc index 24faf20..cf02566 100644 --- a/gcc/m2/pge-boot/GStdIO.cc +++ b/gcc/m2/pge-boot/GStdIO.cc @@ -192,7 +192,7 @@ extern "C" StdIO_ProcWrite StdIO_GetCurrentOutput (void) M2RTS_HALT (-1); __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/StdIO.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/StdIO.def", 25, 1); __builtin_unreachable (); } @@ -251,7 +251,7 @@ extern "C" StdIO_ProcRead StdIO_GetCurrentInput (void) M2RTS_HALT (-1); __builtin_unreachable (); } - ReturnException ("../../gcc-read-write/gcc/m2/gm2-libs/StdIO.def", 25, 1); + ReturnException ("../../gcc/m2/gm2-libs/StdIO.def", 25, 1); __builtin_unreachable (); } diff --git a/gcc/m2/pge-boot/GSymbolKey.cc b/gcc/m2/pge-boot/GSymbolKey.cc index d1495e4..5f22ae2 100644 --- a/gcc/m2/pge-boot/GSymbolKey.cc +++ b/gcc/m2/pge-boot/GSymbolKey.cc @@ -184,7 +184,7 @@ static void FindNodeParentInTree (SymbolKey_SymbolTree t, NameKey_Name n, Symbol (*parent) = t; if (t == NULL) { - Debug_Halt ((const char *) "parameter t should never be NIL", 31, (const char *) "../../gcc-read-write/gcc/m2/gm2-compiler/SymbolKey.mod", 54, (const char *) "FindNodeParentInTree", 20, 241); + Debug_Halt ((const char *) "parameter t should never be NIL", 31, (const char *) "../../gcc/m2/gm2-compiler/SymbolKey.mod", 39, (const char *) "FindNodeParentInTree", 20, 241); } Assertion_Assert (t->Right == NULL); (*child) = t->Left; @@ -393,7 +393,7 @@ extern "C" void SymbolKey_PutSymKey (SymbolKey_SymbolTree t, NameKey_Name NameKe } else { - Debug_Halt ((const char *) "symbol already stored", 21, (const char *) "../../gcc-read-write/gcc/m2/gm2-compiler/SymbolKey.mod", 54, (const char *) "PutSymKey", 9, 156); + Debug_Halt ((const char *) "symbol already stored", 21, (const char *) "../../gcc/m2/gm2-compiler/SymbolKey.mod", 39, (const char *) "PutSymKey", 9, 156); } } @@ -460,7 +460,7 @@ extern "C" void SymbolKey_DelSymKey (SymbolKey_SymbolTree t, NameKey_Name NameKe } else { - Debug_Halt ((const char *) "trying to delete a symbol that is not in the tree - the compiler never expects this to occur", 92, (const char *) "../../gcc-read-write/gcc/m2/gm2-compiler/SymbolKey.mod", 54, (const char *) "DelSymKey", 9, 223); + Debug_Halt ((const char *) "trying to delete a symbol that is not in the tree - the compiler never expects this to occur", 92, (const char *) "../../gcc/m2/gm2-compiler/SymbolKey.mod", 39, (const char *) "DelSymKey", 9, 223); } } diff --git a/gcc/m2/pge-boot/GSysStorage.cc b/gcc/m2/pge-boot/GSysStorage.cc index 8b7bc11..9449a3e 100644 --- a/gcc/m2/pge-boot/GSysStorage.cc +++ b/gcc/m2/pge-boot/GSysStorage.cc @@ -94,7 +94,7 @@ extern "C" void SysStorage_ALLOCATE (void * *a, unsigned int size) (*a) = libc_malloc (static_cast (size)); if ((*a) == NULL) { - Debug_Halt ((const char *) "out of memory error", 19, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/SysStorage.mod", 51, (const char *) "ALLOCATE", 8, 51); + Debug_Halt ((const char *) "out of memory error", 19, (const char *) "../../gcc/m2/gm2-libs/SysStorage.mod", 36, (const char *) "ALLOCATE", 8, 51); } if (enableTrace && trace) { @@ -119,7 +119,7 @@ extern "C" void SysStorage_DEALLOCATE (void * *a, unsigned int size) } if ((libc_memset ((*a), 0, static_cast (size))) != (*a)) { - Debug_Halt ((const char *) "memset should have returned the first parameter", 47, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/SysStorage.mod", 51, (const char *) "DEALLOCATE", 10, 78); + Debug_Halt ((const char *) "memset should have returned the first parameter", 47, (const char *) "../../gcc/m2/gm2-libs/SysStorage.mod", 36, (const char *) "DEALLOCATE", 10, 78); } } if (enableDeallocation) @@ -164,7 +164,7 @@ extern "C" void SysStorage_REALLOCATE (void * *a, unsigned int size) (*a) = libc_realloc ((*a), static_cast (size)); if ((*a) == NULL) { - Debug_Halt ((const char *) "out of memory error", 19, (const char *) "../../gcc-read-write/gcc/m2/gm2-libs/SysStorage.mod", 51, (const char *) "REALLOCATE", 10, 122); + Debug_Halt ((const char *) "out of memory error", 19, (const char *) "../../gcc/m2/gm2-libs/SysStorage.mod", 36, (const char *) "REALLOCATE", 10, 122); } if (enableTrace && trace) { diff --git a/gcc/m2/pge-boot/Glibc.h b/gcc/m2/pge-boot/Glibc.h index 9b3e005..382b737 100644 --- a/gcc/m2/pge-boot/Glibc.h +++ b/gcc/m2/pge-boot/Glibc.h @@ -192,7 +192,7 @@ EXTERN int libc_creat (void * filename, unsigned int mode); off_t lseek(int fildes, off_t offset, int whence); */ -EXTERN long int libc_lseek (int fd, long int offset, int whence); +EXTERN ssize_t libc_lseek (int fd, ssize_t offset, int whence); /* perror - writes errno and string. (ARRAY OF CHAR is translated onto ADDRESS). diff --git a/gcc/m2/pge-boot/Gwrapc.cc b/gcc/m2/pge-boot/Gwrapc.cc index 24a6f35..41ceac8 100644 --- a/gcc/m2/pge-boot/Gwrapc.cc +++ b/gcc/m2/pge-boot/Gwrapc.cc @@ -164,6 +164,38 @@ wrapc_signbitf (float r) #endif } +/* SeekSet return the system libc SEEK_SET value. */ + +int +wrapc_SeekSet (void) +{ + return SEEK_SET; +} + +/* SeekEnd return the system libc SEEK_END value. */ + +int +wrapc_SeekEnd (void) +{ + return SEEK_END; +} + +/* ReadOnly return the system value of O_RDONLY. */ + +int +wrapc_ReadOnly (void) +{ + return O_RDONLY; +} + +/* WriteOnly return the system value of O_WRONLY. */ + +int +wrapc_WriteOnly (void) +{ + return O_WRONLY; +} + /* init constructor for the module. */ void diff --git a/gcc/m2/pge-boot/Gwrapc.h b/gcc/m2/pge-boot/Gwrapc.h index 0ab5a1d..e4db1e2 100644 --- a/gcc/m2/pge-boot/Gwrapc.h +++ b/gcc/m2/pge-boot/Gwrapc.h @@ -118,6 +118,51 @@ EXTERN int wrapc_isfinitef (float x); */ EXTERN int wrapc_isfinitel (long double x); + +/* + isnan - provide non builtin alternative to the gcc builtin isnan. + Returns 1 if x is a NaN otherwise return 0. +*/ + +EXTERN int wrapc_isnan (double x); + +/* + isnanf - provide non builtin alternative to the gcc builtin isnanf. + Returns 1 if x is a NaN otherwise return 0. +*/ + +EXTERN int wrapc_isnanf (float x); + +/* + isnanl - provide non builtin alternative to the gcc builtin isnanl. + Returns 1 if x is a NaN otherwise return 0. +*/ + +EXTERN int wrapc_isnanl (long double x); + +/* + SeekSet - return the system libc SEEK_SET value. +*/ + +EXTERN int wrapc_SeekSet (void); + +/* + SeekEnd - return the system libc SEEK_END value. +*/ + +EXTERN int wrapc_SeekEnd (void); + +/* + ReadOnly - return the system value of O_RDONLY. +*/ + +EXTERN unsigned int wrapc_ReadOnly (void); + +/* + WriteOnly - return the system value of O_WRONLY. +*/ + +EXTERN unsigned int wrapc_WriteOnly (void); # ifdef __cplusplus } # endif -- cgit v1.1 From 3f58f96a4e8255e222953f9856bcd6c25f7b33cd Mon Sep 17 00:00:00 2001 From: Jerry DeLisle Date: Sun, 25 Feb 2024 14:50:07 -0800 Subject: libgfortran: Propagate user defined iostat and iomsg. PR libfortran/105456 libgfortran/ChangeLog: * io/list_read.c (list_formatted_read_scalar): Add checks for the case where a user defines their own error codes and error messages and generate the runtime error. * io/transfer.c (st_read_done): Whitespace. gcc/testsuite/ChangeLog: * gfortran.dg/pr105456.f90: New test. --- gcc/testsuite/gfortran.dg/pr105456.f90 | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/pr105456.f90 (limited to 'gcc') diff --git a/gcc/testsuite/gfortran.dg/pr105456.f90 b/gcc/testsuite/gfortran.dg/pr105456.f90 new file mode 100644 index 0000000..1883238 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr105456.f90 @@ -0,0 +1,38 @@ +! { dg-do run } +! { dg-shouldfail "The users message" } +module sk1 + implicit none + type char + character :: ch + end type char + interface read (formatted) + module procedure read_formatted + end interface read (formatted) +contains + subroutine read_formatted (dtv, unit, iotype, vlist, piostat, piomsg) + class (char), intent(inout) :: dtv + integer, intent(in) :: unit + character (len=*), intent(in) :: iotype + integer, intent(in) :: vlist(:) + integer, intent(out) :: piostat + character (len=*), intent(inout) :: piomsg + character :: ch + read (unit,fmt='(A1)', advance="no", iostat=piostat, iomsg=piomsg) ch + piostat = 42 + piomsg="The users message" + dtv%ch = ch + end subroutine read_formatted +end module sk1 + +program skip1 + use sk1 + implicit none + type (char) :: x + open (10,status="scratch") + write (10,'(A)') '', 'a' + rewind (10) + read (10,*) x + write (*,'(10(A))') "Read: '",x%ch,"'" +end program skip1 +! { dg-output ".*(unit = 10, file = .*)" } +! { dg-output "Fortran runtime error: The users message" } -- cgit v1.1 From 94687d17ba79cdb9fd01c87b2b40b63512471569 Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Sat, 24 Feb 2024 10:26:09 +0100 Subject: Merge dmd, druntime ceff48bf7d, phobos dcbfbd43a D front-end changes: - Import latest fixes from dmd v2.107.1-rc.1. D runtime changes: - Import latest fixes from druntime v2.107.1-rc.1. Phobos changes: - Import latest fixes from phobos v2.107.1-rc.1. gcc/d/ChangeLog: * dmd/MERGE: Merge upstream dmd ceff48bf7d. libphobos/ChangeLog: * libdruntime/MERGE: Merge upstream druntime ceff48bf7d. * libdruntime/Makefile.am (DRUNTIME_DSOURCES_FREEBSD): Add core/sys/freebsd/net/if_.d. * libdruntime/Makefile.in: Regenerate. * src/MERGE: Merge upstream phobos dcbfbd43a. --- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/arrayop.d | 2 +- gcc/d/dmd/ast_node.h | 2 +- gcc/d/dmd/common/file.d | 89 +++-- gcc/d/dmd/common/smallbuffer.d | 30 +- gcc/d/dmd/cparse.d | 150 ++++++-- gcc/d/dmd/dimport.d | 109 +----- gcc/d/dmd/dmodule.d | 32 +- gcc/d/dmd/dsymbolsem.d | 97 +++++ gcc/d/dmd/expression.d | 4 +- gcc/d/dmd/expression.h | 2 +- gcc/d/dmd/expressionsem.d | 97 +++++ gcc/d/dmd/func.d | 394 +-------------------- gcc/d/dmd/funcsem.d | 390 ++++++++++++++++++++ gcc/d/dmd/identifier.h | 2 +- gcc/d/dmd/importc.d | 7 +- gcc/d/dmd/mtype.d | 1 - gcc/d/dmd/parse.d | 48 +-- gcc/d/dmd/root/array.h | 3 +- gcc/d/dmd/root/bitarray.h | 1 - gcc/d/dmd/root/object.h | 57 --- gcc/d/dmd/rootobject.h | 57 +++ gcc/d/dmd/statementsem.d | 2 +- gcc/d/dmd/staticcond.d | 107 ------ gcc/d/dmd/template.h | 2 +- .../gdc.test/compilable/imports/defines.c | 25 ++ gcc/testsuite/gdc.test/compilable/testdefines.d | 10 + .../gdc.test/fail_compilation/warn13679.d | 4 +- 28 files changed, 912 insertions(+), 814 deletions(-) delete mode 100644 gcc/d/dmd/root/object.h create mode 100644 gcc/d/dmd/rootobject.h (limited to 'gcc') diff --git a/gcc/d/dmd/MERGE b/gcc/d/dmd/MERGE index 021149a..f11c5fb 100644 --- a/gcc/d/dmd/MERGE +++ b/gcc/d/dmd/MERGE @@ -1,4 +1,4 @@ -9471b25db9ed44d71e0e27956430c0c6a09c16db +ceff48bf7db05503117f54fdc0cefcb89b711136 The first line of this file holds the git revision number of the last merge done from the dlang/dmd repository. diff --git a/gcc/d/dmd/arrayop.d b/gcc/d/dmd/arrayop.d index afe6054..af3875e 100644 --- a/gcc/d/dmd/arrayop.d +++ b/gcc/d/dmd/arrayop.d @@ -22,7 +22,7 @@ import dmd.dsymbol; import dmd.errors; import dmd.expression; import dmd.expressionsem; -import dmd.func; +import dmd.funcsem; import dmd.hdrgen; import dmd.id; import dmd.identifier; diff --git a/gcc/d/dmd/ast_node.h b/gcc/d/dmd/ast_node.h index a24218a..db8608e 100644 --- a/gcc/d/dmd/ast_node.h +++ b/gcc/d/dmd/ast_node.h @@ -10,7 +10,7 @@ #pragma once -#include "root/object.h" +#include "rootobject.h" class Visitor; diff --git a/gcc/d/dmd/common/file.d b/gcc/d/dmd/common/file.d index 8a28424..80677f6 100644 --- a/gcc/d/dmd/common/file.d +++ b/gcc/d/dmd/common/file.d @@ -16,24 +16,37 @@ module dmd.common.file; import core.stdc.errno : errno; import core.stdc.stdio : fprintf, remove, rename, stderr; -import core.stdc.stdlib : exit; -import core.stdc.string : strerror, strlen; -import core.sys.windows.winbase; -import core.sys.windows.winnt; -import core.sys.posix.fcntl; -import core.sys.posix.unistd; +import core.stdc.stdlib; +import core.stdc.string : strerror, strlen, memcpy; import dmd.common.smallbuffer; -nothrow: - version (Windows) { + import core.sys.windows.winbase; import core.sys.windows.winnls : CP_ACP; + import core.sys.windows.winnt; + + enum CodePage = CP_ACP; // assume filenames encoded in system default Windows ANSI code page + enum invalidHandle = INVALID_HANDLE_VALUE; +} +else version (Posix) +{ + import core.sys.posix.fcntl; + import core.sys.posix.sys.mman; + import core.sys.posix.sys.stat; + import core.sys.posix.unistd; + import core.sys.posix.utime; - // assume filenames encoded in system default Windows ANSI code page - enum CodePage = CP_ACP; + enum invalidHandle = -1; } +else + static assert(0); + + + + +nothrow: /** Encapsulated management of a memory-mapped file. @@ -48,9 +61,6 @@ struct FileMapping(Datum) static assert(__traits(isPOD, Datum) && Datum.sizeof == 1, "Not tested with other data types yet. Add new types with care."); - version(Posix) enum invalidHandle = -1; - else version(Windows) enum invalidHandle = INVALID_HANDLE_VALUE; - // state { /// Handle of underlying file private auto handle = invalidHandle; @@ -82,9 +92,6 @@ struct FileMapping(Datum) { version (Posix) { - import core.sys.posix.sys.mman; - import core.sys.posix.fcntl : open, O_CREAT, O_RDONLY, O_RDWR, S_IRGRP, S_IROTH, S_IRUSR, S_IWUSR; - handle = open(filename, is(Datum == const) ? O_RDONLY : (O_CREAT | O_RDWR), S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); @@ -150,9 +157,6 @@ struct FileMapping(Datum) // Save the name for later. Technically there's no need: on Linux one can use readlink on /proc/self/fd/NNN. // On BSD and OSX one can use fcntl with F_GETPATH. On Windows one can use GetFileInformationByHandleEx. // But just saving the name is simplest, fastest, and most portable... - import core.stdc.string : strlen; - import core.stdc.stdlib : malloc; - import core.stdc.string : memcpy; const totalNameLength = filename.strlen() + 1; auto namex = cast(char*) malloc(totalNameLength); if (!namex) @@ -224,9 +228,6 @@ struct FileMapping(Datum) fakePure({ version (Posix) { - import core.sys.posix.sys.mman : munmap; - import core.sys.posix.unistd : close; - // Cannot call fprintf from inside a destructor, so exiting silently. if (data.ptr && munmap(cast(void*) data.ptr, data.length) != 0) @@ -234,7 +235,7 @@ struct FileMapping(Datum) exit(1); } data = null; - if (handle != invalidHandle && close(handle) != 0) + if (handle != invalidHandle && .close(handle) != 0) { exit(1); } @@ -303,7 +304,6 @@ struct FileMapping(Datum) // In-memory resource freed, now get rid of the underlying temp file. version(Posix) { - import core.sys.posix.unistd : unlink; if (unlink(deleteme) != 0) { fprintf(stderr, "unlink(\"%s\") failed: %s\n", filename, strerror(errno)); @@ -312,7 +312,6 @@ struct FileMapping(Datum) } else version(Windows) { - import core.sys.windows.winbase; if (deleteme[0 .. strlen(deleteme)].extendedPathThen!(p => DeleteFileW(p.ptr)) == 0) { fprintf(stderr, "DeleteFileW error %d\n", GetLastError()); @@ -361,9 +360,6 @@ struct FileMapping(Datum) fakePure({ version(Posix) { - import core.sys.posix.unistd : ftruncate; - import core.sys.posix.sys.mman; - if (data.length) { assert(data.ptr, "Corrupt memory mapping"); @@ -431,7 +427,6 @@ struct FileMapping(Datum) // Fetch the name and then set it to `null` so it doesn't get deallocated auto oldname = name; - import core.stdc.stdlib; scope(exit) free(cast(void*) oldname); name = null; close(); @@ -447,7 +442,6 @@ struct FileMapping(Datum) } else version(Windows) { - import core.sys.windows.winbase; auto r = oldname[0 .. strlen(oldname)].extendedPathThen!( p1 => filename[0 .. strlen(filename)].extendedPathThen!(p2 => MoveFileExW(p1.ptr, p2.ptr, MOVEFILE_REPLACE_EXISTING)) ); @@ -527,8 +521,6 @@ bool touchFile(const char* namez) GetSystemTime(&st); SystemTimeToFileTime(&st, &ft); - import core.stdc.string : strlen; - // get handle to file HANDLE h = namez[0 .. namez.strlen()].extendedPathThen!(p => CreateFile(p.ptr, FILE_WRITE_ATTRIBUTES, FILE_SHARE_READ | FILE_SHARE_WRITE, @@ -546,7 +538,6 @@ bool touchFile(const char* namez) } else version (Posix) { - import core.sys.posix.utime; return utime(namez, null) == 0; } else @@ -560,24 +551,28 @@ Params: fd = file handle Returns: file size in bytes, or `ulong.max` on any error. */ version (Posix) -private ulong fileSize(int fd) { - import core.sys.posix.sys.stat; - stat_t buf; - if (fstat(fd, &buf) == 0) - return buf.st_size; - return ulong.max; + private ulong fileSize(int fd) + { + stat_t buf; + if (fstat(fd, &buf) == 0) + return buf.st_size; + return ulong.max; + } } - -/// Ditto -version (Windows) -private ulong fileSize(HANDLE fd) +else version (Windows) { - ulong result; - if (GetFileSizeEx(fd, cast(LARGE_INTEGER*) &result) == 0) - return result; - return ulong.max; + /// Ditto + private ulong fileSize(HANDLE fd) + { + ulong result; + if (GetFileSizeEx(fd, cast(LARGE_INTEGER*) &result) == 0) + return result; + return ulong.max; + } } +else + static assert(0); /** Runs a non-pure function or delegate as pure code. Use with caution. diff --git a/gcc/d/dmd/common/smallbuffer.d b/gcc/d/dmd/common/smallbuffer.d index c6aa7ab..608ecc8 100644 --- a/gcc/d/dmd/common/smallbuffer.d +++ b/gcc/d/dmd/common/smallbuffer.d @@ -107,28 +107,30 @@ unittest } /** -(Windows only) Converts a narrow string to a wide string using `buffer` as strorage. Returns a slice managed by -`buffer` containing the converted string. The terminating zero is not part of the returned slice, -but is guaranteed to follow it. + * (Windows only) Converts a narrow string to a wide string using `buffer` as strorage. + * Params: + * narrow = string to be converted + * buffer = where to place the converted string + * Returns: a slice of `buffer` containing the converted string. A zero follows the slice. */ version(Windows) wchar[] toWStringz(scope const(char)[] narrow, ref SmallBuffer!wchar buffer) nothrow { - import core.sys.windows.winnls : MultiByteToWideChar; - import dmd.common.file : CodePage; - if (narrow is null) return null; - size_t length; - int i; - while (1) + size_t charsToWchars(scope const(char)[] narrow, scope wchar[] buffer) { // https://learn.microsoft.com/en-us/windows/win32/api/stringapiset/nf-stringapiset-multibytetowidechar - length = MultiByteToWideChar(CodePage, 0, narrow.ptr, cast(int) narrow.length, buffer.ptr, cast(int) buffer.length); - if (length < buffer.length) - break; - buffer.create(length + 1); - assert(++i == 1); // ensure loop should only execute once or twice + import core.sys.windows.winnls : MultiByteToWideChar, CP_ACP; + return MultiByteToWideChar(CP_ACP, 0, narrow.ptr, cast(int) narrow.length, buffer.ptr, cast(int) buffer.length); + } + + size_t length = charsToWchars(narrow, buffer[]); + if (length >= buffer.length) // not enough room in buffer[] + { + buffer.create(length + 1); // extend buffer length + length = charsToWchars(narrow, buffer[]); // try again + assert(length < buffer.length); } buffer[length] = 0; return buffer[0 .. length]; diff --git a/gcc/d/dmd/cparse.d b/gcc/d/dmd/cparse.d index 536a212..e917d2c 100644 --- a/gcc/d/dmd/cparse.d +++ b/gcc/d/dmd/cparse.d @@ -1682,9 +1682,12 @@ final class CParser(AST) : Parser!AST AST.ParameterList parameterList; StorageClass stc = 0; const loc = token.loc; + auto symbolsSave = symbols; + symbols = new AST.Dsymbols(); typedefTab.push(null); auto fbody = cparseStatement(ParseStatementFlags.scope_); typedefTab.pop(); // end of function scope + symbols = symbolsSave; // Rewrite last ExpStatement (if there is one) as a ReturnStatement auto ss = fbody.isScopeStatement(); @@ -1693,8 +1696,11 @@ final class CParser(AST) : Parser!AST if (const len = (*cs.statements).length) { auto s = (*cs.statements)[len - 1]; - if (auto es = s.isExpStatement()) - (*cs.statements)[len - 1] = new AST.ReturnStatement(es.loc, es.exp); + if (s) // error recovery should be with ErrorStatement, not null + { + if (auto es = s.isExpStatement()) + (*cs.statements)[len - 1] = new AST.ReturnStatement(es.loc, es.exp); + } } auto tf = new AST.TypeFunction(parameterList, null, LINK.d, stc); @@ -5520,7 +5526,7 @@ final class CParser(AST) : Parser!AST defines.writeByte('#'); defines.writestring(n.ident.toString()); skipToNextLine(defines); - defines.writeByte('\n'); + defines.writeByte(0); // each #define line is 0 terminated return true; } else if (n.ident == Id.__pragma) @@ -5840,7 +5846,8 @@ final class CParser(AST) : Parser!AST const length = buf.length; buf.writeByte(0); auto slice = buf.peekChars()[0 .. length]; - resetDefineLines(slice); // reset lexer + auto scanlocSave = scanloc; + resetDefineLines(slice); // reset lexer auto save = eSink; auto eLatch = new ErrorSinkLatch(); eSink = eLatch; @@ -5865,12 +5872,14 @@ final class CParser(AST) : Parser!AST (*symbols)[*pd] = s; return; } + assert(symbols, "symbols is null"); defineTab[cast(void*)s.ident] = symbols.length; symbols.push(s); } while (p < endp) { + //printf("|%s|\n", p); if (p[0 .. 7] == "#define") { p += 7; @@ -5884,10 +5893,11 @@ final class CParser(AST) : Parser!AST AST.Type t; + Lswitch: switch (token.value) { - case TOK.endOfLine: // #define identifier - nextDefineLine(); + case TOK.endOfFile: // #define identifier + ++p; continue; case TOK.int32Literal: @@ -5901,7 +5911,7 @@ final class CParser(AST) : Parser!AST Linteger: const intvalue = token.intvalue; nextToken(); - if (token.value == TOK.endOfLine) + if (token.value == TOK.endOfFile) { /* Declare manifest constant: * enum id = intvalue; @@ -5909,7 +5919,7 @@ final class CParser(AST) : Parser!AST AST.Expression e = new AST.IntegerExp(scanloc, intvalue, t); auto v = new AST.VarDeclaration(scanloc, t, id, new AST.ExpInitializer(scanloc, e), STC.manifest); addVar(v); - nextDefineLine(); + ++p; continue; } break; @@ -5924,7 +5934,7 @@ final class CParser(AST) : Parser!AST Lfloat: const floatvalue = token.floatvalue; nextToken(); - if (token.value == TOK.endOfLine) + if (token.value == TOK.endOfFile) { /* Declare manifest constant: * enum id = floatvalue; @@ -5932,7 +5942,7 @@ final class CParser(AST) : Parser!AST AST.Expression e = new AST.RealExp(scanloc, floatvalue, t); auto v = new AST.VarDeclaration(scanloc, t, id, new AST.ExpInitializer(scanloc, e), STC.manifest); addVar(v); - nextDefineLine(); + ++p; continue; } break; @@ -5942,7 +5952,7 @@ final class CParser(AST) : Parser!AST const len = token.len; const postfix = token.postfix; nextToken(); - if (token.value == TOK.endOfLine) + if (token.value == TOK.endOfFile) { /* Declare manifest constant: * enum id = "string"; @@ -5950,19 +5960,20 @@ final class CParser(AST) : Parser!AST AST.Expression e = new AST.StringExp(scanloc, str[0 .. len], len, 1, postfix); auto v = new AST.VarDeclaration(scanloc, null, id, new AST.ExpInitializer(scanloc, e), STC.manifest); addVar(v); - nextDefineLine(); + ++p; continue; } break; case TOK.leftParenthesis: + { /* Look for: * #define ID ( expression ) * and rewrite it to a template function: * auto ID()() { return expression; } */ if (params) - break; // no parameters + goto caseFunctionLike; // version with parameters nextToken(); eLatch.sawErrors = false; auto exp = cparseExpression(); @@ -5971,7 +5982,7 @@ final class CParser(AST) : Parser!AST if (token.value != TOK.rightParenthesis) break; nextToken(); - if (token.value != TOK.endOfLine) + if (token.value != TOK.endOfFile) break; auto ret = new AST.ReturnStatement(exp.loc, exp); auto parameterList = AST.ParameterList(new AST.Parameters(), VarArg.none, 0); @@ -5985,26 +5996,115 @@ final class CParser(AST) : Parser!AST AST.Expression constraint = null; auto tempdecl = new AST.TemplateDeclaration(exp.loc, id, tpl, constraint, decldefs, false); addVar(tempdecl); - nextDefineLine(); + ++p; continue; + } + + caseFunctionLike: + { + /* Parse `( a, b ) expression` + * Create template function: + * auto id(__MP1, __MP2)(__MP1 a, __MP1 b) { return expression; } + */ + //printf("functionlike %s\n", id.toChars()); + + // Capture the parameter list + VarArg varargs = VarArg.none; + auto parameters = new AST.Parameters(); + nextToken(); // skip past `(` + Lwhile: + while (1) + { + if (token.value == TOK.rightParenthesis) + break; + if (token.value == TOK.dotDotDot) + { + static if (0) // variadic macros not supported yet + { + varargs = AST.VarArg.variadic; // C-style variadics + nextToken(); + if (token.value == TOK.rightParenthesis) + break Lwhile; + } + break Lswitch; + } + + if (token.value != TOK.identifier) + break Lswitch; + auto param = new AST.Parameter(token.loc, 0, null, token.ident, null, null); + parameters.push(param); + nextToken(); + if (token.value == TOK.comma) + { + nextToken(); + continue; + } + break; + } + if (token.value != TOK.rightParenthesis) + break; + + //auto pstart = p; + nextToken(); + auto parameterList = AST.ParameterList(parameters, varargs, 0); + /* Create a type for each parameter. Add it to the template parameter list, + * and the parameter list. + */ + auto tpl = new AST.TemplateParameters(); + foreach (param; (*parameters)[]) + { + auto idtype = Identifier.generateId("__MP"); + auto loc = param.loc; + auto tp = new AST.TemplateTypeParameter(loc, idtype, null, null); + tpl.push(tp); + + auto at = new AST.TypeIdentifier(loc, idtype); + param.type = at; + } + + eLatch.sawErrors = false; + auto exp = cparseExpression(); + + //printf("exp: %s tok: %s\n", exp.toChars(), Token.toChars(token.value)); + //printf("parsed: '%.*s'\n", cast(int)(p - pstart), pstart); + assert(symbols); + + if (eLatch.sawErrors) // parsing errors + break; // abandon this #define + + if (token.value != TOK.endOfFile) // did not consume the entire line + break; + + // Generate function + auto ret = new AST.ReturnStatement(exp.loc, exp); + StorageClass stc = STC.auto_; + auto tf = new AST.TypeFunction(parameterList, null, LINK.d, stc); + auto fd = new AST.FuncDeclaration(exp.loc, exp.loc, id, stc, tf, 0); + fd.fbody = ret; + + // Wrap it in an eponymous template + AST.Dsymbols* decldefs = new AST.Dsymbols(); + decldefs.push(fd); + auto tempdecl = new AST.TemplateDeclaration(exp.loc, id, tpl, null, decldefs, false); + addVar(tempdecl); + + ++p; + continue; + } default: break; } } - skipToNextLine(); - } - else - { - scan(&token); - if (token.value != TOK.endOfLine) - { - skipToNextLine(); - } } - nextDefineLine(); + // scan to end of line + while (*p) + ++p; + ++p; // advance to start of next line + scanloc.linnum = scanloc.linnum + 1; } + scanloc = scanlocSave; eSink = save; defines = buf; } diff --git a/gcc/d/dmd/dimport.d b/gcc/d/dmd/dimport.d index b083c03..2efdd31 100644 --- a/gcc/d/dmd/dimport.d +++ b/gcc/d/dmd/dimport.d @@ -12,21 +12,13 @@ module dmd.dimport; import dmd.arraytypes; -import dmd.astenums; -import dmd.declaration; import dmd.dmodule; -import dmd.dscope; import dmd.dsymbol; -import dmd.dsymbolsem; import dmd.errors; -import dmd.expression; -import dmd.globals; import dmd.identifier; import dmd.location; -import dmd.mtype; import dmd.visitor; -import core.stdc.stdio; /*********************************************************** */ extern (C++) final class Import : Dsymbol @@ -76,6 +68,8 @@ extern (C++) final class Import : Dsymbol assert(id); version (none) { + import core.stdc.stdio; + printf("Import::Import("); foreach (id; packages) { @@ -124,105 +118,6 @@ extern (C++) final class Import : Dsymbol } /******************************* - * Load this module. - * Returns: - * true for errors, false for success - */ - extern (D) bool load(Scope* sc) - { - //printf("Import::load('%s') %p\n", toPrettyChars(), this); - // See if existing module - const errors = global.errors; - DsymbolTable dst = Package.resolve(packages, null, &pkg); - version (none) - { - if (pkg && pkg.isModule()) - { - .error(loc, "can only import from a module, not from a member of module `%s`. Did you mean `import %s : %s`?", pkg.toChars(), pkg.toPrettyChars(), id.toChars()); - mod = pkg.isModule(); // Error recovery - treat as import of that module - return true; - } - } - Dsymbol s = dst.lookup(id); - if (s) - { - if (s.isModule()) - mod = cast(Module)s; - else - { - if (s.isAliasDeclaration()) - { - .error(loc, "%s `%s` conflicts with `%s`", s.kind(), s.toPrettyChars(), id.toChars()); - } - else if (Package p = s.isPackage()) - { - if (p.isPkgMod == PKG.unknown) - { - uint preverrors = global.errors; - mod = Module.load(loc, packages, id); - if (!mod) - p.isPkgMod = PKG.package_; - else - { - // mod is a package.d, or a normal module which conflicts with the package name. - if (mod.isPackageFile) - mod.tag = p.tag; // reuse the same package tag - else - { - // show error if Module.load does not - if (preverrors == global.errors) - .error(loc, "%s `%s` from file %s conflicts with %s `%s`", mod.kind(), mod.toPrettyChars(), mod.srcfile.toChars, p.kind(), p.toPrettyChars()); - return true; - } - } - } - else - { - mod = p.isPackageMod(); - } - if (!mod) - { - .error(loc, "can only import from a module, not from package `%s.%s`", p.toPrettyChars(), id.toChars()); - } - } - else if (pkg) - { - .error(loc, "can only import from a module, not from package `%s.%s`", pkg.toPrettyChars(), id.toChars()); - } - else - { - .error(loc, "can only import from a module, not from package `%s`", id.toChars()); - } - } - } - if (!mod) - { - // Load module - mod = Module.load(loc, packages, id); - if (mod) - { - // id may be different from mod.ident, if so then insert alias - dst.insert(id, mod); - } - } - if (mod && !mod.importedFrom) - mod.importedFrom = sc ? sc._module.importedFrom : Module.rootModule; - if (!pkg) - { - if (mod && mod.isPackageFile) - { - // one level depth package.d file (import pkg; ./pkg/package.d) - // it's necessary to use the wrapping Package already created - pkg = mod.pkg; - } - else - pkg = mod; - } - //printf("-Import::load('%s'), pkg = %p\n", toChars(), pkg); - return global.errors != errors; - } - - /******************************* * Mark the imported packages as accessible from the current * scope. This access check is necessary when using FQN b/c * we're using a single global package tree. diff --git a/gcc/d/dmd/dmodule.d b/gcc/d/dmd/dmodule.d index 07d5077..a77e4f3 100644 --- a/gcc/d/dmd/dmodule.d +++ b/gcc/d/dmd/dmodule.d @@ -16,12 +16,14 @@ module dmd.dmodule; import core.stdc.stdio; import core.stdc.stdlib; import core.stdc.string; + import dmd.aggregate; import dmd.arraytypes; import dmd.astcodegen; import dmd.astenums; +import dmd.common.outbuffer; import dmd.compiler; -import dmd.gluelayer; +import dmd.cparse; import dmd.dimport; import dmd.dmacro; import dmd.doc; @@ -35,25 +37,37 @@ import dmd.expressionsem; import dmd.file_manager; import dmd.func; import dmd.globals; +import dmd.gluelayer; import dmd.id; import dmd.identifier; import dmd.location; import dmd.parse; -import dmd.cparse; import dmd.root.array; import dmd.root.file; import dmd.root.filename; -import dmd.common.outbuffer; import dmd.root.port; import dmd.root.rmem; -import dmd.rootobject; import dmd.root.string; +import dmd.rootobject; import dmd.semantic2; import dmd.semantic3; import dmd.target; import dmd.utils; import dmd.visitor; +version (Windows) +{ + import core.sys.windows.winbase : getpid = GetCurrentProcessId; + enum PathSeparator = '\\'; +} +else version (Posix) +{ + import core.sys.posix.unistd : getpid; + enum PathSeparator = '/'; +} +else + static assert(0); + version (IN_GCC) {} else version (IN_LLVM) {} else version = MARS; @@ -141,11 +155,7 @@ private const(char)[] getFilename(Identifier[] packages, Identifier ident) nothr buf.writestring(p); if (modAliases.length) checkModFileAlias(p); - version (Windows) - enum FileSeparator = '\\'; - else - enum FileSeparator = '/'; - buf.writeByte(FileSeparator); + buf.writeByte(PathSeparator); } buf.writestring(filename); if (modAliases.length) @@ -558,10 +568,6 @@ extern (C++) final class Module : Package OutBuffer buf; if (arg == "__stdin.d") { - version (Posix) - import core.sys.posix.unistd : getpid; - else version (Windows) - import core.sys.windows.winbase : getpid = GetCurrentProcessId; buf.printf("__stdin_%d.d", getpid()); arg = buf[]; } diff --git a/gcc/d/dmd/dsymbolsem.d b/gcc/d/dmd/dsymbolsem.d index c15d925..bb0a1d6 100644 --- a/gcc/d/dmd/dsymbolsem.d +++ b/gcc/d/dmd/dsymbolsem.d @@ -6916,6 +6916,103 @@ extern(C++) class ImportAllVisitor : Visitor override void visit(StaticForeachDeclaration _) {} } +/******************************* + * Load module. + * Returns: + * true for errors, false for success + */ +extern (D) bool load(Import imp, Scope* sc) +{ + // See if existing module + const errors = global.errors; + DsymbolTable dst = Package.resolve(imp.packages, null, &imp.pkg); + version (none) + { + if (pkg && pkg.isModule()) + { + .error(loc, "can only import from a module, not from a member of module `%s`. Did you mean `import %s : %s`?", pkg.toChars(), pkg.toPrettyChars(), id.toChars()); + mod = pkg.isModule(); // Error recovery - treat as import of that module + return true; + } + } + Dsymbol s = dst.lookup(imp.id); + if (s) + { + if (s.isModule()) + imp.mod = cast(Module)s; + else + { + if (s.isAliasDeclaration()) + { + .error(imp.loc, "%s `%s` conflicts with `%s`", s.kind(), s.toPrettyChars(), imp.id.toChars()); + } + else if (Package p = s.isPackage()) + { + if (p.isPkgMod == PKG.unknown) + { + uint preverrors = global.errors; + imp.mod = Module.load(imp.loc, imp.packages, imp.id); + if (!imp.mod) + p.isPkgMod = PKG.package_; + else + { + // imp.mod is a package.d, or a normal module which conflicts with the package name. + if (imp.mod.isPackageFile) + imp.mod.tag = p.tag; // reuse the same package tag + else + { + // show error if Module.load does not + if (preverrors == global.errors) + .error(imp.loc, "%s `%s` from file %s conflicts with %s `%s`", imp.mod.kind(), imp.mod.toPrettyChars(), imp.mod.srcfile.toChars, p.kind(), p.toPrettyChars()); + return true; + } + } + } + else + { + imp.mod = p.isPackageMod(); + } + if (!imp.mod) + { + .error(imp.loc, "can only import from a module, not from package `%s.%s`", p.toPrettyChars(), imp.id.toChars()); + } + } + else if (imp.pkg) + { + .error(imp.loc, "can only import from a module, not from package `%s.%s`", imp.pkg.toPrettyChars(), imp.id.toChars()); + } + else + { + .error(imp.loc, "can only import from a module, not from package `%s`", imp.id.toChars()); + } + } + } + if (!imp.mod) + { + // Load module + imp.mod = Module.load(imp.loc, imp.packages, imp.id); + if (imp.mod) + { + // imp.id may be different from mod.ident, if so then insert alias + dst.insert(imp.id, imp.mod); + } + } + if (imp.mod && !imp.mod.importedFrom) + imp.mod.importedFrom = sc ? sc._module.importedFrom : Module.rootModule; + if (!imp.pkg) + { + if (imp.mod && imp.mod.isPackageFile) + { + // one level depth package.d file (import pkg; ./pkg/package.d) + // it's necessary to use the wrapping Package already created + imp.pkg = imp.mod.pkg; + } + else + imp.pkg = imp.mod; + } + return global.errors != errors; +} + void setFieldOffset(Dsymbol d, AggregateDeclaration ad, FieldState* fieldState, bool isunion) { scope v = new SetFieldOffsetVisitor(ad, fieldState, isunion); diff --git a/gcc/d/dmd/expression.d b/gcc/d/dmd/expression.d index bc907cf..479ad3a 100644 --- a/gcc/d/dmd/expression.d +++ b/gcc/d/dmd/expression.d @@ -314,6 +314,7 @@ extern (C++) abstract class Expression : ASTNode Type type; // !=null means that semantic() has been run Loc loc; // file location const EXP op; // to minimize use of dynamic_cast + bool parens; // if this is a parenthesized expression extern (D) this(const ref Loc loc, EXP op) scope @safe { @@ -1310,7 +1311,6 @@ extern (C++) final class ComplexExp : Expression extern (C++) class IdentifierExp : Expression { Identifier ident; - bool parens; // if it appears as (identifier) extern (D) this(const ref Loc loc, Identifier ident) scope @safe { @@ -2432,8 +2432,6 @@ extern (C++) final class CompoundLiteralExp : Expression */ extern (C++) final class TypeExp : Expression { - bool parens; // if this is a parenthesized expression - extern (D) this(const ref Loc loc, Type type) @safe { super(loc, EXP.type); diff --git a/gcc/d/dmd/expression.h b/gcc/d/dmd/expression.h index 3bd8ca7..9cd73a9 100644 --- a/gcc/d/dmd/expression.h +++ b/gcc/d/dmd/expression.h @@ -90,6 +90,7 @@ public: Type *type; // !=NULL means that semantic() has been run Loc loc; // file location EXP op; // to minimize use of dynamic_cast + d_bool parens; // if this is a parenthesized expression size_t size() const; static void _init(); @@ -300,7 +301,6 @@ class IdentifierExp : public Expression { public: Identifier *ident; - d_bool parens; static IdentifierExp *create(const Loc &loc, Identifier *ident); bool isLvalue() override final; diff --git a/gcc/d/dmd/expressionsem.d b/gcc/d/dmd/expressionsem.d index cc589b9..b4d5274 100644 --- a/gcc/d/dmd/expressionsem.d +++ b/gcc/d/dmd/expressionsem.d @@ -16628,3 +16628,100 @@ Expression toBoolean(Expression exp, Scope* sc) return e; } } + +/******************************************** + * Semantically analyze and then evaluate a static condition at compile time. + * This is special because short circuit operators &&, || and ?: at the top + * level are not semantically analyzed if the result of the expression is not + * necessary. + * Params: + * sc = instantiating scope + * original = original expression, for error messages + * e = resulting expression + * errors = set to `true` if errors occurred + * negatives = array to store negative clauses + * Returns: + * true if evaluates to true + */ +bool evalStaticCondition(Scope* sc, Expression original, Expression e, out bool errors, Expressions* negatives = null) +{ + if (negatives) + negatives.setDim(0); + + bool impl(Expression e) + { + if (e.isNotExp()) + { + NotExp ne = cast(NotExp)e; + return !impl(ne.e1); + } + + if (e.op == EXP.andAnd || e.op == EXP.orOr) + { + LogicalExp aae = cast(LogicalExp)e; + bool result = impl(aae.e1); + if (errors) + return false; + if (e.op == EXP.andAnd) + { + if (!result) + return false; + } + else + { + if (result) + return true; + } + result = impl(aae.e2); + return !errors && result; + } + + if (e.op == EXP.question) + { + CondExp ce = cast(CondExp)e; + bool result = impl(ce.econd); + if (errors) + return false; + Expression leg = result ? ce.e1 : ce.e2; + result = impl(leg); + return !errors && result; + } + + Expression before = e; + const uint nerrors = global.errors; + + sc = sc.startCTFE(); + sc.flags |= SCOPE.condition; + + e = e.expressionSemantic(sc); + e = resolveProperties(sc, e); + e = e.toBoolean(sc); + + sc = sc.endCTFE(); + e = e.optimize(WANTvalue); + + if (nerrors != global.errors || + e.isErrorExp() || + e.type.toBasetype() == Type.terror) + { + errors = true; + return false; + } + + e = e.ctfeInterpret(); + + const opt = e.toBool(); + if (opt.isEmpty()) + { + if (!e.type.isTypeError()) + error(e.loc, "expression `%s` is not constant", e.toChars()); + errors = true; + return false; + } + + if (negatives && !opt.get()) + negatives.push(before); + return opt.get(); + } + return impl(e); +} diff --git a/gcc/d/dmd/func.d b/gcc/d/dmd/func.d index 4881ad6..d890811 100644 --- a/gcc/d/dmd/func.d +++ b/gcc/d/dmd/func.d @@ -58,7 +58,6 @@ import dmd.semantic3; import dmd.statement_rewrite_walker; import dmd.statement; import dmd.statementsem; -import dmd.templatesem; import dmd.tokens; import dmd.typesem; import dmd.visitor; @@ -2925,395 +2924,6 @@ unittest assert(mismatches.isMutable); } -/// Flag used by $(LREF resolveFuncCall). -enum FuncResolveFlag : ubyte -{ - standard = 0, /// issue error messages, solve the call. - quiet = 1, /// do not issue error message on no match, just return `null`. - overloadOnly = 2, /// only resolve overloads, i.e. do not issue error on ambiguous - /// matches and need explicit this. - ufcs = 4, /// trying to resolve UFCS call -} - -/******************************************* - * Given a symbol that could be either a FuncDeclaration or - * a function template, resolve it to a function symbol. - * Params: - * loc = instantiation location - * sc = instantiation scope - * s = instantiation symbol - * tiargs = initial list of template arguments - * tthis = if !NULL, the `this` argument type - * argumentList = arguments to function - * flags = see $(LREF FuncResolveFlag). - * Returns: - * if match is found, then function symbol, else null - */ -FuncDeclaration resolveFuncCall(const ref Loc loc, Scope* sc, Dsymbol s, - Objects* tiargs, Type tthis, ArgumentList argumentList, FuncResolveFlag flags) -{ - auto fargs = argumentList.arguments; - if (!s) - return null; // no match - - version (none) - { - printf("resolveFuncCall('%s')\n", s.toChars()); - if (tthis) - printf("\tthis: %s\n", tthis.toChars()); - if (fargs) - { - for (size_t i = 0; i < fargs.length; i++) - { - Expression arg = (*fargs)[i]; - assert(arg.type); - printf("\t%s: %s\n", arg.toChars(), arg.type.toChars()); - } - } - printf("\tfnames: %s\n", fnames ? fnames.toChars() : "null"); - } - - if (tiargs && arrayObjectIsError(*tiargs)) - return null; - if (fargs !is null) - foreach (arg; *fargs) - if (isError(arg)) - return null; - - MatchAccumulator m; - functionResolve(m, s, loc, sc, tiargs, tthis, argumentList); - auto orig_s = s; - - if (m.last > MATCH.nomatch && m.lastf) - { - if (m.count == 1) // exactly one match - { - if (!(flags & FuncResolveFlag.quiet)) - functionSemantic(m.lastf); - return m.lastf; - } - if ((flags & FuncResolveFlag.overloadOnly) && !tthis && m.lastf.needThis()) - { - return m.lastf; - } - } - - /* Failed to find a best match. - * Do nothing or print error. - */ - if (m.last == MATCH.nomatch) - { - // error was caused on matched function, not on the matching itself, - // so return the function to produce a better diagnostic - if (m.count == 1) - return m.lastf; - } - - // We are done at this point, as the rest of this function generate - // a diagnostic on invalid match - if (flags & FuncResolveFlag.quiet) - return null; - - auto fd = s.isFuncDeclaration(); - auto od = s.isOverDeclaration(); - auto td = s.isTemplateDeclaration(); - if (td && td.funcroot) - s = fd = td.funcroot; - - OutBuffer tiargsBuf; - arrayObjectsToBuffer(tiargsBuf, tiargs); - - OutBuffer fargsBuf; - fargsBuf.writeByte('('); - argExpTypesToCBuffer(fargsBuf, fargs); - fargsBuf.writeByte(')'); - if (tthis) - tthis.modToBuffer(fargsBuf); - - // The call is ambiguous - if (m.lastf && m.nextf) - { - TypeFunction tf1 = m.lastf.type.toTypeFunction(); - TypeFunction tf2 = m.nextf.type.toTypeFunction(); - const(char)* lastprms = parametersTypeToChars(tf1.parameterList); - const(char)* nextprms = parametersTypeToChars(tf2.parameterList); - - .error(loc, "`%s.%s` called with argument types `%s` matches both:\n%s: `%s%s%s`\nand:\n%s: `%s%s%s`", - s.parent.toPrettyChars(), s.ident.toChars(), - fargsBuf.peekChars(), - m.lastf.loc.toChars(), m.lastf.toPrettyChars(), lastprms, tf1.modToChars(), - m.nextf.loc.toChars(), m.nextf.toPrettyChars(), nextprms, tf2.modToChars()); - return null; - } - - // no match, generate an error messages - if (flags & FuncResolveFlag.ufcs) - { - auto arg = (*fargs)[0]; - .error(loc, "no property `%s` for `%s` of type `%s`", s.ident.toChars(), arg.toChars(), arg.type.toChars()); - .errorSupplemental(loc, "the following error occured while looking for a UFCS match"); - } - - if (!fd) - { - // all of overloads are templates - if (td) - { - if (!od && !td.overnext) - { - .error(loc, "%s `%s` is not callable using argument types `!(%s)%s`", - td.kind(), td.ident.toChars(), tiargsBuf.peekChars(), fargsBuf.peekChars()); - } - else - { - .error(loc, "none of the overloads of %s `%s.%s` are callable using argument types `!(%s)%s`", - td.kind(), td.parent.toPrettyChars(), td.ident.toChars(), - tiargsBuf.peekChars(), fargsBuf.peekChars()); - } - - - if (!global.gag || global.params.v.showGaggedErrors) - printCandidates(loc, td, sc.isDeprecated()); - return null; - } - /* This case used to happen when several ctors are mixed in an agregate. - A (bad) error message is already generated in overloadApply(). - see https://issues.dlang.org/show_bug.cgi?id=19729 - and https://issues.dlang.org/show_bug.cgi?id=17259 - */ - if (!od) - return null; - } - - if (od) - { - .error(loc, "none of the overloads of `%s` are callable using argument types `!(%s)%s`", - od.ident.toChars(), tiargsBuf.peekChars(), fargsBuf.peekChars()); - return null; - } - - // remove when deprecation period of class allocators and deallocators is over - if (fd.isNewDeclaration() && fd.checkDisabled(loc, sc)) - return null; - - bool hasOverloads = fd.overnext !is null; - auto tf = fd.type.isTypeFunction(); - // if type is an error, the original type should be there for better diagnostics - if (!tf) - tf = fd.originalType.toTypeFunction(); - - // modifier mismatch - if (tthis && (fd.isCtorDeclaration() ? - !MODimplicitConv(tf.mod, tthis.mod) : - !MODimplicitConv(tthis.mod, tf.mod))) - { - OutBuffer thisBuf, funcBuf; - MODMatchToBuffer(&thisBuf, tthis.mod, tf.mod); - auto mismatches = MODMatchToBuffer(&funcBuf, tf.mod, tthis.mod); - if (hasOverloads) - { - OutBuffer buf; - buf.argExpTypesToCBuffer(fargs); - if (fd.isCtorDeclaration()) - .error(loc, "none of the overloads of `%s` can construct a %sobject with argument types `(%s)`", - fd.toChars(), thisBuf.peekChars(), buf.peekChars()); - else - .error(loc, "none of the overloads of `%s` are callable using a %sobject with argument types `(%s)`", - fd.toChars(), thisBuf.peekChars(), buf.peekChars()); - - if (!global.gag || global.params.v.showGaggedErrors) - printCandidates(loc, fd, sc.isDeprecated()); - return null; - } - - bool calledHelper; - void errorHelper(const(char)* failMessage) scope - { - .error(loc, "%s `%s%s%s` is not callable using argument types `%s`", - fd.kind(), fd.toPrettyChars(), parametersTypeToChars(tf.parameterList), - tf.modToChars(), fargsBuf.peekChars()); - errorSupplemental(loc, failMessage); - calledHelper = true; - } - - functionResolve(m, orig_s, loc, sc, tiargs, tthis, argumentList, &errorHelper); - if (calledHelper) - return null; - - if (fd.isCtorDeclaration()) - .error(loc, "%s%s `%s` cannot construct a %sobject", - funcBuf.peekChars(), fd.kind(), fd.toPrettyChars(), thisBuf.peekChars()); - else - .error(loc, "%smethod `%s` is not callable using a %sobject", - funcBuf.peekChars(), fd.toPrettyChars(), thisBuf.peekChars()); - - if (mismatches.isNotShared) - .errorSupplemental(fd.loc, "Consider adding `shared` here"); - else if (mismatches.isMutable) - .errorSupplemental(fd.loc, "Consider adding `const` or `inout` here"); - return null; - } - - //printf("tf = %s, args = %s\n", tf.deco, (*fargs)[0].type.deco); - if (hasOverloads) - { - .error(loc, "none of the overloads of `%s` are callable using argument types `%s`", - fd.toChars(), fargsBuf.peekChars()); - if (!global.gag || global.params.v.showGaggedErrors) - printCandidates(loc, fd, sc.isDeprecated()); - return null; - } - - .error(loc, "%s `%s%s%s` is not callable using argument types `%s`", - fd.kind(), fd.toPrettyChars(), parametersTypeToChars(tf.parameterList), - tf.modToChars(), fargsBuf.peekChars()); - - // re-resolve to check for supplemental message - if (!global.gag || global.params.v.showGaggedErrors) - { - if (tthis) - { - if (auto classType = tthis.isTypeClass()) - { - if (auto baseClass = classType.sym.baseClass) - { - if (auto baseFunction = baseClass.search(baseClass.loc, fd.ident)) - { - MatchAccumulator mErr; - functionResolve(mErr, baseFunction, loc, sc, tiargs, baseClass.type, argumentList); - if (mErr.last > MATCH.nomatch && mErr.lastf) - { - errorSupplemental(loc, "%s `%s` hides base class function `%s`", - fd.kind, fd.toPrettyChars(), mErr.lastf.toPrettyChars()); - errorSupplemental(loc, "add `alias %s = %s` to `%s`'s body to merge the overload sets", - fd.toChars(), mErr.lastf.toPrettyChars(), tthis.toChars()); - return null; - } - } - } - } - } - - void errorHelper2(const(char)* failMessage) scope - { - errorSupplemental(loc, failMessage); - } - - functionResolve(m, orig_s, loc, sc, tiargs, tthis, argumentList, &errorHelper2); - } - return null; -} - -/******************************************* - * Prints template and function overload candidates as supplemental errors. - * Params: - * loc = instantiation location - * declaration = the declaration to print overload candidates for - * showDeprecated = If `false`, `deprecated` function won't be shown - */ -private void printCandidates(Decl)(const ref Loc loc, Decl declaration, bool showDeprecated) -if (is(Decl == TemplateDeclaration) || is(Decl == FuncDeclaration)) -{ - // max num of overloads to print (-v or -verror-supplements overrides this). - const uint DisplayLimit = global.params.v.errorSupplementCount(); - const(char)* constraintsTip; - // determine if the first candidate was printed - int printed; - - bool matchSymbol(Dsymbol s, bool print, bool single_candidate = false) - { - if (auto fd = s.isFuncDeclaration()) - { - // Don't print overloads which have errors. - // Not that if the whole overload set has errors, we'll never reach - // this point so there's no risk of printing no candidate - if (fd.errors || fd.type.ty == Terror) - return false; - // Don't print disabled functions, or `deprecated` outside of deprecated scope - if (fd.storage_class & STC.disable || (fd.isDeprecated() && !showDeprecated)) - return false; - if (!print) - return true; - auto tf = cast(TypeFunction) fd.type; - OutBuffer buf; - buf.writestring(fd.toPrettyChars()); - buf.writestring(parametersTypeToChars(tf.parameterList)); - if (tf.mod) - { - buf.writeByte(' '); - buf.MODtoBuffer(tf.mod); - } - .errorSupplemental(fd.loc, - printed ? " `%s`" : - single_candidate ? "Candidate is: `%s`" : "Candidates are: `%s`", buf.peekChars()); - } - else if (auto td = s.isTemplateDeclaration()) - { - import dmd.staticcond; - - if (!print) - return true; - OutBuffer buf; - HdrGenState hgs; - hgs.skipConstraints = true; - toCharsMaybeConstraints(td, buf, hgs); - const tmsg = buf.peekChars(); - const cmsg = td.getConstraintEvalError(constraintsTip); - - // add blank space if there are multiple candidates - // the length of the blank space is `strlen("Candidates are: ")` - - if (cmsg) - { - .errorSupplemental(td.loc, - printed ? " `%s`\n%s" : - single_candidate ? "Candidate is: `%s`\n%s" : "Candidates are: `%s`\n%s", - tmsg, cmsg); - } - else - { - .errorSupplemental(td.loc, - printed ? " `%s`" : - single_candidate ? "Candidate is: `%s`" : "Candidates are: `%s`", - tmsg); - } - } - return true; - } - // determine if there's > 1 candidate - int count = 0; - overloadApply(declaration, (s) { - if (matchSymbol(s, false)) - count++; - return count > 1; - }); - int skipped = 0; - overloadApply(declaration, (s) { - if (global.params.v.verbose || printed < DisplayLimit) - { - if (matchSymbol(s, true, count == 1)) - printed++; - } - else - { - // Too many overloads to sensibly display. - // Just show count of remaining overloads. - if (matchSymbol(s, false)) - skipped++; - } - return 0; - }); - if (skipped > 0) - .errorSupplemental(loc, "... (%d more, -v to show) ...", skipped); - - // Nothing was displayed, all overloads are either disabled or deprecated - if (!printed) - .errorSupplemental(loc, "All possible candidates are marked as `deprecated` or `@disable`"); - // should be only in verbose mode - if (constraintsTip) - .tip(constraintsTip); -} - /************************************** * Returns an indirect type one step from t. */ @@ -4336,9 +3946,9 @@ bool setUnsafePreview(Scope* sc, FeatureState fs, bool gag, Loc loc, const(char) return false; if (sc.func.isSafeBypassingInference()) { - if (!gag) + if (!gag && !sc.isDeprecated()) { - warning(loc, msg, arg0 ? arg0.toChars() : "", arg1 ? arg1.toChars() : "", arg2 ? arg2.toChars() : ""); + deprecation(loc, msg, arg0 ? arg0.toChars() : "", arg1 ? arg1.toChars() : "", arg2 ? arg2.toChars() : ""); } } else if (!sc.func.safetyViolation) diff --git a/gcc/d/dmd/funcsem.d b/gcc/d/dmd/funcsem.d index 49da6b2..b8b185c 100644 --- a/gcc/d/dmd/funcsem.d +++ b/gcc/d/dmd/funcsem.d @@ -60,6 +60,7 @@ import dmd.statement_rewrite_walker; import dmd.statement; import dmd.statementsem; import dmd.target; +import dmd.templatesem; import dmd.tokens; import dmd.typesem; import dmd.visitor; @@ -1365,3 +1366,392 @@ BaseClass* overrideInterface(FuncDeclaration fd) } return null; } + +/// Flag used by $(LREF resolveFuncCall). +enum FuncResolveFlag : ubyte +{ + standard = 0, /// issue error messages, solve the call. + quiet = 1, /// do not issue error message on no match, just return `null`. + overloadOnly = 2, /// only resolve overloads, i.e. do not issue error on ambiguous + /// matches and need explicit this. + ufcs = 4, /// trying to resolve UFCS call +} + +/******************************************* + * Given a symbol that could be either a FuncDeclaration or + * a function template, resolve it to a function symbol. + * Params: + * loc = instantiation location + * sc = instantiation scope + * s = instantiation symbol + * tiargs = initial list of template arguments + * tthis = if !NULL, the `this` argument type + * argumentList = arguments to function + * flags = see $(LREF FuncResolveFlag). + * Returns: + * if match is found, then function symbol, else null + */ +FuncDeclaration resolveFuncCall(const ref Loc loc, Scope* sc, Dsymbol s, + Objects* tiargs, Type tthis, ArgumentList argumentList, FuncResolveFlag flags) +{ + auto fargs = argumentList.arguments; + if (!s) + return null; // no match + + version (none) + { + printf("resolveFuncCall('%s')\n", s.toChars()); + if (tthis) + printf("\tthis: %s\n", tthis.toChars()); + if (fargs) + { + for (size_t i = 0; i < fargs.length; i++) + { + Expression arg = (*fargs)[i]; + assert(arg.type); + printf("\t%s: %s\n", arg.toChars(), arg.type.toChars()); + } + } + printf("\tfnames: %s\n", fnames ? fnames.toChars() : "null"); + } + + if (tiargs && arrayObjectIsError(*tiargs)) + return null; + if (fargs !is null) + foreach (arg; *fargs) + if (isError(arg)) + return null; + + MatchAccumulator m; + functionResolve(m, s, loc, sc, tiargs, tthis, argumentList); + auto orig_s = s; + + if (m.last > MATCH.nomatch && m.lastf) + { + if (m.count == 1) // exactly one match + { + if (!(flags & FuncResolveFlag.quiet)) + functionSemantic(m.lastf); + return m.lastf; + } + if ((flags & FuncResolveFlag.overloadOnly) && !tthis && m.lastf.needThis()) + { + return m.lastf; + } + } + + /* Failed to find a best match. + * Do nothing or print error. + */ + if (m.last == MATCH.nomatch) + { + // error was caused on matched function, not on the matching itself, + // so return the function to produce a better diagnostic + if (m.count == 1) + return m.lastf; + } + + // We are done at this point, as the rest of this function generate + // a diagnostic on invalid match + if (flags & FuncResolveFlag.quiet) + return null; + + auto fd = s.isFuncDeclaration(); + auto od = s.isOverDeclaration(); + auto td = s.isTemplateDeclaration(); + if (td && td.funcroot) + s = fd = td.funcroot; + + OutBuffer tiargsBuf; + arrayObjectsToBuffer(tiargsBuf, tiargs); + + OutBuffer fargsBuf; + fargsBuf.writeByte('('); + argExpTypesToCBuffer(fargsBuf, fargs); + fargsBuf.writeByte(')'); + if (tthis) + tthis.modToBuffer(fargsBuf); + + // The call is ambiguous + if (m.lastf && m.nextf) + { + TypeFunction tf1 = m.lastf.type.toTypeFunction(); + TypeFunction tf2 = m.nextf.type.toTypeFunction(); + const(char)* lastprms = parametersTypeToChars(tf1.parameterList); + const(char)* nextprms = parametersTypeToChars(tf2.parameterList); + + .error(loc, "`%s.%s` called with argument types `%s` matches both:\n%s: `%s%s%s`\nand:\n%s: `%s%s%s`", + s.parent.toPrettyChars(), s.ident.toChars(), + fargsBuf.peekChars(), + m.lastf.loc.toChars(), m.lastf.toPrettyChars(), lastprms, tf1.modToChars(), + m.nextf.loc.toChars(), m.nextf.toPrettyChars(), nextprms, tf2.modToChars()); + return null; + } + + // no match, generate an error messages + if (flags & FuncResolveFlag.ufcs) + { + auto arg = (*fargs)[0]; + .error(loc, "no property `%s` for `%s` of type `%s`", s.ident.toChars(), arg.toChars(), arg.type.toChars()); + .errorSupplemental(loc, "the following error occured while looking for a UFCS match"); + } + + if (!fd) + { + // all of overloads are templates + if (td) + { + if (!od && !td.overnext) + { + .error(loc, "%s `%s` is not callable using argument types `!(%s)%s`", + td.kind(), td.ident.toChars(), tiargsBuf.peekChars(), fargsBuf.peekChars()); + } + else + { + .error(loc, "none of the overloads of %s `%s.%s` are callable using argument types `!(%s)%s`", + td.kind(), td.parent.toPrettyChars(), td.ident.toChars(), + tiargsBuf.peekChars(), fargsBuf.peekChars()); + } + + + if (!global.gag || global.params.v.showGaggedErrors) + printCandidates(loc, td, sc.isDeprecated()); + return null; + } + /* This case used to happen when several ctors are mixed in an agregate. + A (bad) error message is already generated in overloadApply(). + see https://issues.dlang.org/show_bug.cgi?id=19729 + and https://issues.dlang.org/show_bug.cgi?id=17259 + */ + if (!od) + return null; + } + + if (od) + { + .error(loc, "none of the overloads of `%s` are callable using argument types `!(%s)%s`", + od.ident.toChars(), tiargsBuf.peekChars(), fargsBuf.peekChars()); + return null; + } + + // remove when deprecation period of class allocators and deallocators is over + if (fd.isNewDeclaration() && fd.checkDisabled(loc, sc)) + return null; + + bool hasOverloads = fd.overnext !is null; + auto tf = fd.type.isTypeFunction(); + // if type is an error, the original type should be there for better diagnostics + if (!tf) + tf = fd.originalType.toTypeFunction(); + + // modifier mismatch + if (tthis && (fd.isCtorDeclaration() ? + !MODimplicitConv(tf.mod, tthis.mod) : + !MODimplicitConv(tthis.mod, tf.mod))) + { + OutBuffer thisBuf, funcBuf; + MODMatchToBuffer(&thisBuf, tthis.mod, tf.mod); + auto mismatches = MODMatchToBuffer(&funcBuf, tf.mod, tthis.mod); + if (hasOverloads) + { + OutBuffer buf; + buf.argExpTypesToCBuffer(fargs); + if (fd.isCtorDeclaration()) + .error(loc, "none of the overloads of `%s` can construct a %sobject with argument types `(%s)`", + fd.toChars(), thisBuf.peekChars(), buf.peekChars()); + else + .error(loc, "none of the overloads of `%s` are callable using a %sobject with argument types `(%s)`", + fd.toChars(), thisBuf.peekChars(), buf.peekChars()); + + if (!global.gag || global.params.v.showGaggedErrors) + printCandidates(loc, fd, sc.isDeprecated()); + return null; + } + + bool calledHelper; + void errorHelper(const(char)* failMessage) scope + { + .error(loc, "%s `%s%s%s` is not callable using argument types `%s`", + fd.kind(), fd.toPrettyChars(), parametersTypeToChars(tf.parameterList), + tf.modToChars(), fargsBuf.peekChars()); + errorSupplemental(loc, failMessage); + calledHelper = true; + } + + functionResolve(m, orig_s, loc, sc, tiargs, tthis, argumentList, &errorHelper); + if (calledHelper) + return null; + + if (fd.isCtorDeclaration()) + .error(loc, "%s%s `%s` cannot construct a %sobject", + funcBuf.peekChars(), fd.kind(), fd.toPrettyChars(), thisBuf.peekChars()); + else + .error(loc, "%smethod `%s` is not callable using a %sobject", + funcBuf.peekChars(), fd.toPrettyChars(), thisBuf.peekChars()); + + if (mismatches.isNotShared) + .errorSupplemental(fd.loc, "Consider adding `shared` here"); + else if (mismatches.isMutable) + .errorSupplemental(fd.loc, "Consider adding `const` or `inout` here"); + return null; + } + + //printf("tf = %s, args = %s\n", tf.deco, (*fargs)[0].type.deco); + if (hasOverloads) + { + .error(loc, "none of the overloads of `%s` are callable using argument types `%s`", + fd.toChars(), fargsBuf.peekChars()); + if (!global.gag || global.params.v.showGaggedErrors) + printCandidates(loc, fd, sc.isDeprecated()); + return null; + } + + .error(loc, "%s `%s%s%s` is not callable using argument types `%s`", + fd.kind(), fd.toPrettyChars(), parametersTypeToChars(tf.parameterList), + tf.modToChars(), fargsBuf.peekChars()); + + // re-resolve to check for supplemental message + if (!global.gag || global.params.v.showGaggedErrors) + { + if (tthis) + { + if (auto classType = tthis.isTypeClass()) + { + if (auto baseClass = classType.sym.baseClass) + { + if (auto baseFunction = baseClass.search(baseClass.loc, fd.ident)) + { + MatchAccumulator mErr; + functionResolve(mErr, baseFunction, loc, sc, tiargs, baseClass.type, argumentList); + if (mErr.last > MATCH.nomatch && mErr.lastf) + { + errorSupplemental(loc, "%s `%s` hides base class function `%s`", + fd.kind, fd.toPrettyChars(), mErr.lastf.toPrettyChars()); + errorSupplemental(loc, "add `alias %s = %s` to `%s`'s body to merge the overload sets", + fd.toChars(), mErr.lastf.toPrettyChars(), tthis.toChars()); + return null; + } + } + } + } + } + + void errorHelper2(const(char)* failMessage) scope + { + errorSupplemental(loc, failMessage); + } + + functionResolve(m, orig_s, loc, sc, tiargs, tthis, argumentList, &errorHelper2); + } + return null; +} + +/******************************************* + * Prints template and function overload candidates as supplemental errors. + * Params: + * loc = instantiation location + * declaration = the declaration to print overload candidates for + * showDeprecated = If `false`, `deprecated` function won't be shown + */ +private void printCandidates(Decl)(const ref Loc loc, Decl declaration, bool showDeprecated) +if (is(Decl == TemplateDeclaration) || is(Decl == FuncDeclaration)) +{ + // max num of overloads to print (-v or -verror-supplements overrides this). + const uint DisplayLimit = global.params.v.errorSupplementCount(); + const(char)* constraintsTip; + // determine if the first candidate was printed + int printed; + + bool matchSymbol(Dsymbol s, bool print, bool single_candidate = false) + { + if (auto fd = s.isFuncDeclaration()) + { + // Don't print overloads which have errors. + // Not that if the whole overload set has errors, we'll never reach + // this point so there's no risk of printing no candidate + if (fd.errors || fd.type.ty == Terror) + return false; + // Don't print disabled functions, or `deprecated` outside of deprecated scope + if (fd.storage_class & STC.disable || (fd.isDeprecated() && !showDeprecated)) + return false; + if (!print) + return true; + auto tf = cast(TypeFunction) fd.type; + OutBuffer buf; + buf.writestring(fd.toPrettyChars()); + buf.writestring(parametersTypeToChars(tf.parameterList)); + if (tf.mod) + { + buf.writeByte(' '); + buf.MODtoBuffer(tf.mod); + } + .errorSupplemental(fd.loc, + printed ? " `%s`" : + single_candidate ? "Candidate is: `%s`" : "Candidates are: `%s`", buf.peekChars()); + } + else if (auto td = s.isTemplateDeclaration()) + { + import dmd.staticcond; + + if (!print) + return true; + OutBuffer buf; + HdrGenState hgs; + hgs.skipConstraints = true; + toCharsMaybeConstraints(td, buf, hgs); + const tmsg = buf.peekChars(); + const cmsg = td.getConstraintEvalError(constraintsTip); + + // add blank space if there are multiple candidates + // the length of the blank space is `strlen("Candidates are: ")` + + if (cmsg) + { + .errorSupplemental(td.loc, + printed ? " `%s`\n%s" : + single_candidate ? "Candidate is: `%s`\n%s" : "Candidates are: `%s`\n%s", + tmsg, cmsg); + } + else + { + .errorSupplemental(td.loc, + printed ? " `%s`" : + single_candidate ? "Candidate is: `%s`" : "Candidates are: `%s`", + tmsg); + } + } + return true; + } + // determine if there's > 1 candidate + int count = 0; + overloadApply(declaration, (s) { + if (matchSymbol(s, false)) + count++; + return count > 1; + }); + int skipped = 0; + overloadApply(declaration, (s) { + if (global.params.v.verbose || printed < DisplayLimit) + { + if (matchSymbol(s, true, count == 1)) + printed++; + } + else + { + // Too many overloads to sensibly display. + // Just show count of remaining overloads. + if (matchSymbol(s, false)) + skipped++; + } + return 0; + }); + if (skipped > 0) + .errorSupplemental(loc, "... (%d more, -v to show) ...", skipped); + + // Nothing was displayed, all overloads are either disabled or deprecated + if (!printed) + .errorSupplemental(loc, "All possible candidates are marked as `deprecated` or `@disable`"); + // should be only in verbose mode + if (constraintsTip) + .tip(constraintsTip); +} diff --git a/gcc/d/dmd/identifier.h b/gcc/d/dmd/identifier.h index afd3664..4f26801 100644 --- a/gcc/d/dmd/identifier.h +++ b/gcc/d/dmd/identifier.h @@ -11,7 +11,7 @@ #pragma once #include "root/dcompat.h" -#include "root/object.h" +#include "rootobject.h" class Identifier final : public RootObject { diff --git a/gcc/d/dmd/importc.d b/gcc/d/dmd/importc.d index e4d5aa2..ece56c8 100644 --- a/gcc/d/dmd/importc.d +++ b/gcc/d/dmd/importc.d @@ -243,16 +243,15 @@ Expression castCallAmbiguity(Expression e, Scope* sc) case EXP.call: auto ce = (*pe).isCallExp(); - auto ie = ce.e1.isIdentifierExp(); - if (ie && ie.parens) + if (ce.e1.parens) { - ce.e1 = expressionSemantic(ie, sc); + ce.e1 = expressionSemantic(ce.e1, sc); if (ce.e1.op == EXP.type) { const numArgs = ce.arguments ? ce.arguments.length : 0; if (numArgs >= 1) { - ie.parens = false; + ce.e1.parens = false; Expression arg; foreach (a; (*ce.arguments)[]) { diff --git a/gcc/d/dmd/mtype.d b/gcc/d/dmd/mtype.d index 09ed630..843c402 100644 --- a/gcc/d/dmd/mtype.d +++ b/gcc/d/dmd/mtype.d @@ -30,7 +30,6 @@ import dmd.dtemplate; import dmd.enumsem; import dmd.errors; import dmd.expression; -import dmd.func; import dmd.funcsem; import dmd.globals; import dmd.hdrgen; diff --git a/gcc/d/dmd/parse.d b/gcc/d/dmd/parse.d index 9c446eb..646c4b7 100644 --- a/gcc/d/dmd/parse.d +++ b/gcc/d/dmd/parse.d @@ -7130,7 +7130,7 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer private void checkParens(TOK value, AST.Expression e) { - if (precedence[e.op] == PREC.rel) + if (precedence[e.op] == PREC.rel && !e.parens) error(e.loc, "`%s` must be surrounded by parentheses when next to operator `%s`", e.toChars(), Token.toChars(value)); } @@ -8550,6 +8550,7 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer // ( expression ) nextToken(); e = parseExpression(); + e.parens = true; check(loc, TOK.rightParenthesis); break; } @@ -8874,9 +8875,9 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer nextToken(); return AST.ErrorExp.get(); } - auto te = new AST.TypeExp(loc, t); - te.parens = true; - e = parsePostExp(te); + e = new AST.TypeExp(loc, t); + e.parens = true; + e = parsePostExp(e); } else if (token.value == TOK.leftParenthesis || token.value == TOK.plusPlus || token.value == TOK.minusMinus) @@ -9193,18 +9194,14 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer private AST.Expression parseAndExp() { Loc loc = token.loc; - bool parens = token.value == TOK.leftParenthesis; auto e = parseCmpExp(); while (token.value == TOK.and) { - if (!parens) - checkParens(TOK.and, e); - parens = nextToken() == TOK.leftParenthesis; + checkParens(TOK.and, e); + nextToken(); auto e2 = parseCmpExp(); - if (!parens) - checkParens(TOK.and, e2); + checkParens(TOK.and, e2); e = new AST.AndExp(loc, e, e2); - parens = true; // don't call checkParens() for And loc = token.loc; } return e; @@ -9212,42 +9209,32 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer private AST.Expression parseXorExp() { - Loc loc = token.loc; + const loc = token.loc; - bool parens = token.value == TOK.leftParenthesis; auto e = parseAndExp(); while (token.value == TOK.xor) { - if (!parens) - checkParens(TOK.xor, e); - parens = nextToken() == TOK.leftParenthesis; + checkParens(TOK.xor, e); + nextToken(); auto e2 = parseAndExp(); - if (!parens) - checkParens(TOK.xor, e2); + checkParens(TOK.xor, e2); e = new AST.XorExp(loc, e, e2); - parens = true; - loc = token.loc; } return e; } private AST.Expression parseOrExp() { - Loc loc = token.loc; + const loc = token.loc; - bool parens = token.value == TOK.leftParenthesis; auto e = parseXorExp(); while (token.value == TOK.or) { - if (!parens) - checkParens(TOK.or, e); - parens = nextToken() == TOK.leftParenthesis; + checkParens(TOK.or, e); + nextToken(); auto e2 = parseXorExp(); - if (!parens) - checkParens(TOK.or, e2); + checkParens(TOK.or, e2); e = new AST.OrExp(loc, e, e2); - parens = true; - loc = token.loc; } return e; } @@ -9298,7 +9285,6 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer AST.Expression parseAssignExp() { - bool parens = token.value == TOK.leftParenthesis; AST.Expression e; e = parseCondExp(); if (e is null) @@ -9307,7 +9293,7 @@ class Parser(AST, Lexer = dmd.lexer.Lexer) : Lexer // require parens for e.g. `t ? a = 1 : b = 2` void checkRequiredParens() { - if (e.op == EXP.question && !parens) + if (e.op == EXP.question && !e.parens) eSink.error(e.loc, "`%s` must be surrounded by parentheses when next to operator `%s`", e.toChars(), Token.toChars(token.value)); } diff --git a/gcc/d/dmd/root/array.h b/gcc/d/dmd/root/array.h index 1033b22..3e28804 100644 --- a/gcc/d/dmd/root/array.h +++ b/gcc/d/dmd/root/array.h @@ -9,7 +9,6 @@ #pragma once #include "dsystem.h" -#include "object.h" #include "rmem.h" template @@ -44,7 +43,7 @@ struct Array d_size_t len = 2; for (d_size_t u = 0; u < length; u++) { - buf[u] = ((RootObject *)data.ptr[u])->toChars(); + buf[u] = ((TYPE)data.ptr[u])->toChars(); len += strlen(buf[u]) + 1; } char *str = (char *)mem.xmalloc(len); diff --git a/gcc/d/dmd/root/bitarray.h b/gcc/d/dmd/root/bitarray.h index 2cd7152..2a82703 100644 --- a/gcc/d/dmd/root/bitarray.h +++ b/gcc/d/dmd/root/bitarray.h @@ -9,7 +9,6 @@ #pragma once #include "dsystem.h" -#include "object.h" #include "rmem.h" struct BitArray diff --git a/gcc/d/dmd/root/object.h b/gcc/d/dmd/root/object.h deleted file mode 100644 index f56cb17..0000000 --- a/gcc/d/dmd/root/object.h +++ /dev/null @@ -1,57 +0,0 @@ - -/* Copyright (C) 1999-2024 by The D Language Foundation, All Rights Reserved - * written by Walter Bright - * https://www.digitalmars.com - * Distributed under the Boost Software License, Version 1.0. - * https://www.boost.org/LICENSE_1_0.txt - * https://github.com/dlang/dmd/blob/master/src/dmd/root/object.h - */ - -#pragma once - -#include "dsystem.h" -#include "dcompat.h" - -typedef size_t hash_t; - -struct OutBuffer; - -enum DYNCAST -{ - DYNCAST_OBJECT, - DYNCAST_EXPRESSION, - DYNCAST_DSYMBOL, - DYNCAST_TYPE, - DYNCAST_IDENTIFIER, - DYNCAST_TUPLE, - DYNCAST_PARAMETER, - DYNCAST_STATEMENT, - DYNCAST_CONDITION, - DYNCAST_TEMPLATEPARAMETER, - DYNCAST_INITIALIZER -}; - -/* - * Root of our class library. - */ -class RootObject -{ -public: - RootObject() { } - - virtual bool equals(const RootObject * const o) const; - - /** - * Pretty-print an Object. Useful for debugging the old-fashioned way. - */ - virtual const char *toChars() const; - /// This function is `extern(D)` and should not be called from C++, - /// as the ABI does not match on some platforms - virtual DString toString(); - - /** - * Used as a replacement for dynamic_cast. Returns a unique number - * defined by the library user. For Object, the return value is 0. - */ - virtual DYNCAST dyncast() const; -}; diff --git a/gcc/d/dmd/rootobject.h b/gcc/d/dmd/rootobject.h new file mode 100644 index 0000000..718a54f --- /dev/null +++ b/gcc/d/dmd/rootobject.h @@ -0,0 +1,57 @@ + +/* Copyright (C) 1999-2024 by The D Language Foundation, All Rights Reserved + * written by Walter Bright + * https://www.digitalmars.com + * Distributed under the Boost Software License, Version 1.0. + * https://www.boost.org/LICENSE_1_0.txt + * https://github.com/dlang/dmd/blob/master/src/dmd/rootobject.h + */ + +#pragma once + +#include "root/dsystem.h" +#include "root/dcompat.h" + +typedef size_t hash_t; + +struct OutBuffer; + +enum DYNCAST +{ + DYNCAST_OBJECT, + DYNCAST_EXPRESSION, + DYNCAST_DSYMBOL, + DYNCAST_TYPE, + DYNCAST_IDENTIFIER, + DYNCAST_TUPLE, + DYNCAST_PARAMETER, + DYNCAST_STATEMENT, + DYNCAST_CONDITION, + DYNCAST_TEMPLATEPARAMETER, + DYNCAST_INITIALIZER +}; + +/* + * Root of our class library. + */ +class RootObject +{ +public: + RootObject() { } + + virtual bool equals(const RootObject * const o) const; + + /** + * Pretty-print an Object. Useful for debugging the old-fashioned way. + */ + virtual const char *toChars() const; + /// This function is `extern(D)` and should not be called from C++, + /// as the ABI does not match on some platforms + virtual DString toString(); + + /** + * Used as a replacement for dynamic_cast. Returns a unique number + * defined by the library user. For Object, the return value is 0. + */ + virtual DYNCAST dyncast() const; +}; diff --git a/gcc/d/dmd/statementsem.d b/gcc/d/dmd/statementsem.d index 5013c56..1bf36e3 100644 --- a/gcc/d/dmd/statementsem.d +++ b/gcc/d/dmd/statementsem.d @@ -1196,7 +1196,7 @@ Statement statementSemanticVisit(Statement s, Scope* sc) } case Taarray: if (fs.op == TOK.foreach_reverse_) - warning(fs.loc, "cannot use `foreach_reverse` with an associative array"); + error(fs.loc, "cannot use `foreach_reverse` with an associative array"); if (checkForArgTypes(fs)) return retError(); diff --git a/gcc/d/dmd/staticcond.d b/gcc/d/dmd/staticcond.d index 72afe02..3ab6885 100644 --- a/gcc/d/dmd/staticcond.d +++ b/gcc/d/dmd/staticcond.d @@ -11,120 +11,13 @@ module dmd.staticcond; -import dmd.arraytypes; -import dmd.dinterpret; -import dmd.dmodule; -import dmd.dscope; -import dmd.dsymbol; -import dmd.errors; import dmd.expression; -import dmd.expressionsem; -import dmd.globals; -import dmd.identifier; -import dmd.mtype; -import dmd.optimize; import dmd.root.array; import dmd.common.outbuffer; import dmd.tokens; -/******************************************** - * Semantically analyze and then evaluate a static condition at compile time. - * This is special because short circuit operators &&, || and ?: at the top - * level are not semantically analyzed if the result of the expression is not - * necessary. - * Params: - * sc = instantiating scope - * original = original expression, for error messages - * e = resulting expression - * errors = set to `true` if errors occurred - * negatives = array to store negative clauses - * Returns: - * true if evaluates to true - */ -bool evalStaticCondition(Scope* sc, Expression original, Expression e, out bool errors, Expressions* negatives = null) -{ - if (negatives) - negatives.setDim(0); - - bool impl(Expression e) - { - if (e.isNotExp()) - { - NotExp ne = cast(NotExp)e; - return !impl(ne.e1); - } - - if (e.op == EXP.andAnd || e.op == EXP.orOr) - { - LogicalExp aae = cast(LogicalExp)e; - bool result = impl(aae.e1); - if (errors) - return false; - if (e.op == EXP.andAnd) - { - if (!result) - return false; - } - else - { - if (result) - return true; - } - result = impl(aae.e2); - return !errors && result; - } - - if (e.op == EXP.question) - { - CondExp ce = cast(CondExp)e; - bool result = impl(ce.econd); - if (errors) - return false; - Expression leg = result ? ce.e1 : ce.e2; - result = impl(leg); - return !errors && result; - } - - Expression before = e; - const uint nerrors = global.errors; - - sc = sc.startCTFE(); - sc.flags |= SCOPE.condition; - - e = e.expressionSemantic(sc); - e = resolveProperties(sc, e); - e = e.toBoolean(sc); - - sc = sc.endCTFE(); - e = e.optimize(WANTvalue); - - if (nerrors != global.errors || - e.isErrorExp() || - e.type.toBasetype() == Type.terror) - { - errors = true; - return false; - } - - e = e.ctfeInterpret(); - - const opt = e.toBool(); - if (opt.isEmpty()) - { - if (!e.type.isTypeError()) - error(e.loc, "expression `%s` is not constant", e.toChars()); - errors = true; - return false; - } - - if (negatives && !opt.get()) - negatives.push(before); - return opt.get(); - } - return impl(e); -} /******************************************** * Format a static condition as a tree-like structure, marking failed and diff --git a/gcc/d/dmd/template.h b/gcc/d/dmd/template.h index 6f12ac3..0f96a1b 100644 --- a/gcc/d/dmd/template.h +++ b/gcc/d/dmd/template.h @@ -36,7 +36,7 @@ public: // kludge for template.isType() DYNCAST dyncast() const override { return DYNCAST_TUPLE; } - const char *toChars() const override { return objects.toChars(); } + const char *toChars() const override; }; struct TemplatePrevious diff --git a/gcc/testsuite/gdc.test/compilable/imports/defines.c b/gcc/testsuite/gdc.test/compilable/imports/defines.c index 8a5601a..6b0746f 100644 --- a/gcc/testsuite/gdc.test/compilable/imports/defines.c +++ b/gcc/testsuite/gdc.test/compilable/imports/defines.c @@ -30,3 +30,28 @@ _Static_assert(SSS[0] == 'h', "10"); #define ABC 12 #define GHI (size) abbadabba #define DEF (ABC + 5) + +#define ADD(a, b) a + b +#define SUB() 3 - 2 + +#define NO_BODY() +#define NO_BODY_PARAMS(a, b) +#define DO_WHILE() do { } while(0) + +#define pr16199_trigger(cond,func,args) _Generic (cond, default: func args) +#define pr16199_skipped1(a) (1) +#define pr16199_skipped2(b) (2) +#define pr16199_ice 0x3 + +#define M16199Ea(TYPE) (TYPE __x;) +#define M16199E(X,S,M) ({ M16199Ea(S *); }) + +#define M16199Da(TYPE,VAR) ((TYPE)(VAR)) +#define M16199D(X,S,M) ({ int *__x = (X); M16199Da(S *, __x); }) +int pr16199d() { return 7; } + +#define M16199C(X,S,M) ({ int __x; }) +int pr16199c() +{ + return 8; +} diff --git a/gcc/testsuite/gdc.test/compilable/testdefines.d b/gcc/testsuite/gdc.test/compilable/testdefines.d index 9dd8cf2..060e962 100644 --- a/gcc/testsuite/gdc.test/compilable/testdefines.d +++ b/gcc/testsuite/gdc.test/compilable/testdefines.d @@ -15,3 +15,13 @@ static assert(SSS == "hello"); static assert(ABC == 12); static assert(DEF == 17); + +static assert(ADD(3, 4) == 7); +static assert(SUB() == 1); + +static assert(pr16199_skipped1(5) == 1); +static assert(pr16199_skipped2(6) == 2); +static assert(pr16199_ice == 3); + +static assert(pr16199d() == 7); +static assert(pr16199c() == 8); diff --git a/gcc/testsuite/gdc.test/fail_compilation/warn13679.d b/gcc/testsuite/gdc.test/fail_compilation/warn13679.d index 74d4564..2291039 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/warn13679.d +++ b/gcc/testsuite/gdc.test/fail_compilation/warn13679.d @@ -3,9 +3,7 @@ /* TEST_OUTPUT: --- -fail_compilation/warn13679.d(15): Warning: cannot use `foreach_reverse` with an associative array -Error: warnings are treated as errors - Use -wi if you wish to treat warnings only as informational. +fail_compilation/warn13679.d(13): Error: cannot use `foreach_reverse` with an associative array --- */ -- cgit v1.1 From ad178a2be7ea099d0dfc1452186035748c0828dd Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Mon, 26 Feb 2024 00:16:54 +0000 Subject: Daily bump. --- gcc/DATESTAMP | 2 +- gcc/d/ChangeLog | 4 +++ gcc/m2/ChangeLog | 84 +++++++++++++++++++++++++++++++++++++++++++++++++ gcc/testsuite/ChangeLog | 5 +++ 4 files changed, 94 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index ff71cb4..47afea3 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240225 +20240226 diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog index 06cc557..696fb584 100644 --- a/gcc/d/ChangeLog +++ b/gcc/d/ChangeLog @@ -1,3 +1,7 @@ +2024-02-25 Iain Buclaw + + * dmd/MERGE: Merge upstream dmd ceff48bf7d. + 2024-02-17 Iain Buclaw * dmd/MERGE: Merge upstream dmd 9471b25db9. diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog index 6e9c770..3adc420 100644 --- a/gcc/m2/ChangeLog +++ b/gcc/m2/ChangeLog @@ -1,3 +1,87 @@ +2024-02-25 Gaius Mulley + + PR modula2/113749 + * Make-lang.in (BUILD-PGE-O): Add m2/pge-boot/Gwrapc.o. + * gm2-libs-ch/wrapc.c (wrapc_SeekSet): New function. + (wrapc_SeekEnd): Ditto. + (wrapc_ReadOnly): Ditto. + (wrapc_WriteOnly): Ditto. + * gm2-libs/FIO.mod (SEEK_SET): Remove. + (SEEK_END): Remove. + (UNIXREADONLY): Remove. + (UNIXWRITEONLY): Remove. + (ConnectToUnix): Replace UNIXWRITEONLY with a call to WriteOnly. + Replace UNIXREADONLY with a call to ReadOnly. + (SetPositionFromBeginning): Replace SEEK_SET with a call to + SeekSet. + (SetPositionFromEnd): Replace SEEK_END with a call to + SeekEnd. + * gm2-libs/wrapc.def (SeekSet): New procedure function. + (SeekEnd): New procedure function. + (ReadOnly): New procedure function. + (WriteOnly): New procedure function. + * mc-boot-ch/Glibc.c (BUILD_MC_LIBC_TRACE): Undef. + (check_init): New function. + (tracedb): Ditto. + (tracedb_open): Ditto. + (tracedb_result): Ditto. + (libc_read): Ditto. + (libc_write): Ditto. + (libc_close): Ditto. + (libc_creat): Ditto. + (libc_open): Ditto. + (libc_lseek): Ditto. + * mc-boot-ch/Gwrapc.c (wrapc_SeekSet): New function. + (wrapc_SeekEnd): Ditto. + (wrapc_ReadOnly): Ditto. + (wrapc_WriteOnly): Ditto. + * mc-boot/GDynamicStrings.cc: Rebuilt. + * mc-boot/GFIO.cc: Ditto. + * mc-boot/GIndexing.cc: Ditto. + * mc-boot/GM2Dependent.cc: Ditto. + * mc-boot/GM2EXCEPTION.cc: Ditto. + * mc-boot/GPushBackInput.cc: Ditto. + * mc-boot/GRTExceptions.cc: Ditto. + * mc-boot/GRTint.cc: Ditto. + * mc-boot/GSArgs.cc: Ditto. + * mc-boot/GStdIO.cc: Ditto. + * mc-boot/GStringConvert.cc: Ditto. + * mc-boot/GSysStorage.cc: Ditto. + * mc-boot/Gdecl.cc: Ditto. + * mc-boot/Gkeyc.cc: Ditto. + * mc-boot/Glibc.h: Ditto. + * mc-boot/GmcComment.cc: Ditto. + * mc-boot/GmcComp.cc: Ditto. + * mc-boot/GmcDebug.cc: Ditto. + * mc-boot/GmcMetaError.cc: Ditto. + * mc-boot/GmcStack.cc: Ditto. + * mc-boot/GmcStream.cc: Ditto. + * mc-boot/GnameKey.cc: Ditto. + * mc-boot/GsymbolKey.cc: Ditto. + * mc-boot/Gvarargs.cc: Ditto. + * mc-boot/Gwrapc.h: Ditto. + * mc/decl.mod (getSymName): Add pointerref clause. + * mc/mcStream.mod (copy): Check for an error after every read. + * mc/varargs.mod (copy): Rewrite pointer arithmetic using INC to + avoid type incompatibility. + * pge-boot/GDynamicStrings.cc: Rebuilt. + * pge-boot/GDynamicStrings.h: Ditto. + * pge-boot/GFIO.cc: Ditto. + * pge-boot/GFIO.h: Ditto. + * pge-boot/GIO.cc: Ditto. + * pge-boot/GIndexing.cc: Ditto. + * pge-boot/GM2Dependent.cc: Ditto. + * pge-boot/GM2EXCEPTION.cc: Ditto. + * pge-boot/GNameKey.cc: Ditto. + * pge-boot/GPushBackInput.cc: Ditto. + * pge-boot/GRTExceptions.cc: Ditto. + * pge-boot/GStdIO.cc: Ditto. + * pge-boot/GSymbolKey.cc: Ditto. + * pge-boot/GSysStorage.cc: Ditto. + * pge-boot/Glibc.h: Ditto. + * pge-boot/Gwrapc.cc: Ditto. + * pge-boot/Gwrapc.h: Ditto. + 2024-02-22 Gaius Mulley PR modula2/114055 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 48e6fb6..a101c52 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2024-02-25 Jerry DeLisle + + PR libfortran/105456 + * gfortran.dg/pr105456.f90: New test. + 2024-02-24 Richard Sandiford PR tree-optimization/113205 -- cgit v1.1 From 4972f97a265c574d51e20373ddefd66576051e5c Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sun, 25 Feb 2024 10:21:04 -0800 Subject: x86: Properly implement AMX-TILE load/store intrinsics ldtilecfg and sttilecfg take a 512-byte memory block. With _tile_loadconfig implemented as extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _tile_loadconfig (const void *__config) { __asm__ volatile ("ldtilecfg\t%X0" :: "m" (*((const void **)__config))); } GCC sees: (parallel [ (asm_operands/v ("ldtilecfg %X0") ("") 0 [(mem/f/c:DI (plus:DI (reg/f:DI 77 virtual-stack-vars) (const_int -64 [0xffffffffffffffc0])) [1 MEM[(const void * *)&tile_data]+0 S8 A128])] [(asm_input:DI ("m"))] (clobber (reg:CC 17 flags))]) and the memory operand size is 1 byte. As the result, the rest of 511 bytes is ignored by GCC. Implement ldtilecfg and sttilecfg intrinsics with a pointer to XImode to honor the 512-byte memory block. gcc/ChangeLog: PR target/114098 * config/i386/amxtileintrin.h (_tile_loadconfig): Use __builtin_ia32_ldtilecfg. (_tile_storeconfig): Use __builtin_ia32_sttilecfg. * config/i386/i386-builtin.def (BDESC): Add __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg. * config/i386/i386-expand.cc (ix86_expand_builtin): Handle IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG. * config/i386/i386.md (ldtilecfg): New pattern. (sttilecfg): Likewise. gcc/testsuite/ChangeLog: PR target/114098 * gcc.target/i386/amxtile-4.c: New test. --- gcc/config/i386/amxtileintrin.h | 4 +-- gcc/config/i386/i386-builtin.def | 4 +++ gcc/config/i386/i386-expand.cc | 19 +++++++++++ gcc/config/i386/i386.md | 24 ++++++++++++++ gcc/testsuite/gcc.target/i386/amxtile-4.c | 52 +++++++++++++++++++++++++++++++ 5 files changed, 101 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/amxtile-4.c (limited to 'gcc') diff --git a/gcc/config/i386/amxtileintrin.h b/gcc/config/i386/amxtileintrin.h index d1a26e0..5081b32 100644 --- a/gcc/config/i386/amxtileintrin.h +++ b/gcc/config/i386/amxtileintrin.h @@ -39,14 +39,14 @@ extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _tile_loadconfig (const void *__config) { - __asm__ volatile ("ldtilecfg\t%X0" :: "m" (*((const void **)__config))); + __builtin_ia32_ldtilecfg (__config); } extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _tile_storeconfig (void *__config) { - __asm__ volatile ("sttilecfg\t%X0" : "=m" (*((void **)__config))); + __builtin_ia32_sttilecfg (__config); } extern __inline void diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 7293552..ab73e20 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -126,6 +126,10 @@ BDESC (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_nothing, "__b BDESC (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64) BDESC (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64) +/* LDFILECFG and STFILECFG. */ +BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_AMX_TILE, CODE_FOR_nothing, "__builtin_ia32_ldtilecfg", IX86_BUILTIN_LDTILECFG, UNKNOWN, (int) VOID_FTYPE_PCVOID) +BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_AMX_TILE, CODE_FOR_nothing, "__builtin_ia32_sttilecfg", IX86_BUILTIN_STTILECFG, UNKNOWN, (int) VOID_FTYPE_PVOID) + /* SSE */ BDESC (OPTION_MASK_ISA_SSE, 0, CODE_FOR_movv4sf_internal, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF) BDESC (OPTION_MASK_ISA_SSE, 0, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index a4d3369..c98e0f8 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -14152,6 +14152,25 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, emit_insn (pat); return 0; + case IX86_BUILTIN_LDTILECFG: + case IX86_BUILTIN_STTILECFG: + arg0 = CALL_EXPR_ARG (exp, 0); + op0 = expand_normal (arg0); + + if (!address_operand (op0, VOIDmode)) + { + op0 = convert_memory_address (Pmode, op0); + op0 = copy_addr_to_reg (op0); + } + op0 = gen_rtx_MEM (XImode, op0); + if (fcode == IX86_BUILTIN_LDTILECFG) + icode = CODE_FOR_ldtilecfg; + else + icode = CODE_FOR_sttilecfg; + pat = GEN_FCN (icode) (op0); + emit_insn (pat); + return 0; + case IX86_BUILTIN_LLWPCB: arg0 = CALL_EXPR_ARG (exp, 0); op0 = expand_normal (arg0); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 6a26d96..df97a2d6 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -353,6 +353,10 @@ ;; For USER_MSR support UNSPECV_URDMSR UNSPECV_UWRMSR + + ;; For AMX-TILE + UNSPECV_LDTILECFG + UNSPECV_STTILECFG ]) ;; Constants to represent rounding modes in the ROUND instruction @@ -28152,6 +28156,26 @@ [(set_attr "prefix" "vex") (set_attr "type" "other")]) +(define_insn "ldtilecfg" + [(unspec_volatile [(match_operand:XI 0 "memory_operand" "m")] + UNSPECV_LDTILECFG)] + "TARGET_AMX_TILE" + "ldtilecfg\t%0" + [(set_attr "type" "other") + (set_attr "prefix" "maybe_evex") + (set_attr "memory" "load") + (set_attr "mode" "XI")]) + +(define_insn "sttilecfg" + [(set (match_operand:XI 0 "memory_operand" "=m") + (unspec_volatile:XI [(const_int 0)] UNSPECV_STTILECFG))] + "TARGET_AMX_TILE" + "sttilecfg\t%0" + [(set_attr "type" "other") + (set_attr "prefix" "maybe_evex") + (set_attr "memory" "store") + (set_attr "mode" "XI")]) + (include "mmx.md") (include "sse.md") (include "sync.md") diff --git a/gcc/testsuite/gcc.target/i386/amxtile-4.c b/gcc/testsuite/gcc.target/i386/amxtile-4.c new file mode 100644 index 0000000..6b49cde --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/amxtile-4.c @@ -0,0 +1,52 @@ +/* PR target/114098 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mamx-tile" } */ + +#include +#include + +#define MAX_ROWS 16 +#define MAX_COLS 64 +#define MAX 1024 +#define STRIDE 64 + +typedef struct __tile_config +{ + uint8_t palette_id; + uint8_t start_row; + uint8_t reserved_0[14]; + uint16_t colsb[16]; + uint8_t rows[16]; +} __tilecfg __attribute__ ((aligned (64))); + +/* Initialize tile config */ +static void +init_tile_config (__tilecfg *tileinfo) +{ + int i; + tileinfo->palette_id = 1; + tileinfo->start_row = 0; + + for (i = 0; i < 1; ++i) + { + tileinfo->colsb[i] = MAX_ROWS; + tileinfo->rows[i] = MAX_ROWS; + } + + for (i = 1; i < 4; ++i) + { + tileinfo->colsb[i] = MAX_COLS; + tileinfo->rows[i] = MAX_ROWS; + } + + _tile_loadconfig (tileinfo); +} + +void +enable_amx (void) +{ + __tilecfg tile_data = {0}; + init_tile_config (&tile_data); +} + +/* { dg-final { scan-assembler-times "pxor\[^\n\]*%xmm" 1 } } */ -- cgit v1.1 From 6987f16742bd4fc6bb8118b9efde52fb9169b327 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 26 Feb 2024 07:30:05 +0100 Subject: i386: Fix up x86_function_profiler -masm=intel support [PR114094] In my r14-8214 changes I apparently forgot one \n at the end of an instruction. The corresponding AT&T line looks like: "1:\tcall\t*%s@GOTPCREL(%%rip)\n" but the Intel variant was "1:\tcall\t[QWORD PTR %s@GOTPCREL[rip]]" Fixed thusly. 2024-02-26 Jakub Jelinek PR target/114094 * config/i386/i386.cc (x86_function_profiler): Add missing new-line to printed instruction. * gcc.target/i386/pr114094.c: New test. --- gcc/config/i386/i386.cc | 2 +- gcc/testsuite/gcc.target/i386/pr114094.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr114094.c (limited to 'gcc') diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 4fdab34..86381b0 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -22909,7 +22909,7 @@ x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED) if (!ix86_direct_extern_access) { if (ASSEMBLER_DIALECT == ASM_INTEL) - fprintf (file, "1:\tcall\t[QWORD PTR %s@GOTPCREL[rip]]", + fprintf (file, "1:\tcall\t[QWORD PTR %s@GOTPCREL[rip]]\n", mcount_name); else fprintf (file, "1:\tcall\t*%s@GOTPCREL(%%rip)\n", diff --git a/gcc/testsuite/gcc.target/i386/pr114094.c b/gcc/testsuite/gcc.target/i386/pr114094.c new file mode 100644 index 0000000..64fe509 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr114094.c @@ -0,0 +1,10 @@ +/* PR target/114094 */ +/* { dg-do assemble { target *-*-linux* } } */ +/* { dg-require-effective-target masm_intel } */ +/* { dg-require-effective-target pie } */ +/* { dg-options "-fpie -fprofile -mno-direct-extern-access -masm=intel" } */ + +void +foo (void) +{ +} -- cgit v1.1 From af66ad89e8169f44db723813662917cf4cbb78fc Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Fri, 23 Feb 2024 16:06:05 +0100 Subject: middle-end/114070 - folding breaking VEC_COND expansion The following properly guards the simplifications that move operations into VEC_CONDs, in particular when that changes the type constraints on this operation. This needed a genmatch fix which was recording spurious implicit fors when tcc_comparison is used in a C expression. PR middle-end/114070 * genmatch.cc (parser::parse_c_expr): Do not record operand lists but only mark operators used. * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)): Properly guard the case of tcc_comparison changing the VEC_COND value operand type. * gcc.dg/torture/pr114070.c: New testcase. --- gcc/genmatch.cc | 6 ++---- gcc/match.pd | 15 ++++++++++++--- gcc/testsuite/gcc.dg/torture/pr114070.c | 12 ++++++++++++ 3 files changed, 26 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/torture/pr114070.c (limited to 'gcc') diff --git a/gcc/genmatch.cc b/gcc/genmatch.cc index 5e92d0b..61c4c8c 100644 --- a/gcc/genmatch.cc +++ b/gcc/genmatch.cc @@ -4749,10 +4749,8 @@ parser::parse_c_expr (cpp_ttype start) = (const char *)CPP_HASHNODE (token->val.node.node)->ident.str; if (strcmp (str, "return") == 0) fatal_at (token, "return statement not allowed in C expression"); - id_base *idb = get_operator (str); - user_id *p; - if (idb && (p = dyn_cast (idb)) && p->is_oper_list) - record_operlist (token->src_loc, p); + /* Mark user operators corresponding to 'str' as used. */ + get_operator (str); } /* Record the token. */ diff --git a/gcc/match.pd b/gcc/match.pd index c5b6540..67007fc 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -5149,15 +5149,24 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) /* (c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e) */ (simplify (op (vec_cond:s @0 @1 @2) (vec_cond:s @0 @3 @4)) - (vec_cond @0 (op! @1 @3) (op! @2 @4))) + (if (TREE_CODE_CLASS (op) != tcc_comparison + || types_match (type, TREE_TYPE (@1)) + || expand_vec_cond_expr_p (type, TREE_TYPE (@0), ERROR_MARK)) + (vec_cond @0 (op! @1 @3) (op! @2 @4)))) /* (c ? a : b) op d --> c ? (a op d) : (b op d) */ (simplify (op (vec_cond:s @0 @1 @2) @3) - (vec_cond @0 (op! @1 @3) (op! @2 @3))) + (if (TREE_CODE_CLASS (op) != tcc_comparison + || types_match (type, TREE_TYPE (@1)) + || expand_vec_cond_expr_p (type, TREE_TYPE (@0), ERROR_MARK)) + (vec_cond @0 (op! @1 @3) (op! @2 @3)))) (simplify (op @3 (vec_cond:s @0 @1 @2)) - (vec_cond @0 (op! @3 @1) (op! @3 @2)))) + (if (TREE_CODE_CLASS (op) != tcc_comparison + || types_match (type, TREE_TYPE (@1)) + || expand_vec_cond_expr_p (type, TREE_TYPE (@0), ERROR_MARK)) + (vec_cond @0 (op! @3 @1) (op! @3 @2))))) #if GIMPLE (match (nop_atomic_bit_test_and_p @0 @1 @4) diff --git a/gcc/testsuite/gcc.dg/torture/pr114070.c b/gcc/testsuite/gcc.dg/torture/pr114070.c new file mode 100644 index 0000000..cf46ec4 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr114070.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-fno-vect-cost-model" } */ + +int unresolved(unsigned dirmask, unsigned mask, int *unresolved_n) +{ + for (int i = 0; i < 1024; i++) { + mask |= 1; + if (!unresolved_n[i] || unresolved_n[i] & 70000) + dirmask |= 1; + } + return (dirmask == mask); +} -- cgit v1.1 From f9d2a95be5680e04f53141c2675798b06d23f409 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 26 Feb 2024 10:07:39 +0100 Subject: fold-const: Avoid infinite recursion in +-*&|^minmax reassociation [PR114084] In the following testcase we infinitely recurse during BIT_IOR_EXPR reassociation. One operand is (unsigned _BitInt(31)) a << 4 and another operand 2147483647 >> 1 | 80 where both the right shift and the | 80 trees have TREE_CONSTANT set, but weren't folded because of delayed folding, where some foldings are apparently done even in that case unfortunately. Now, the fold_binary_loc reassocation code splits both operands into variable part, minus variable part, constant part, minus constant part, literal part and minus literal parts, to prevent infinite recursion punts if there are just 2 parts altogether from the 2 operands and then goes on with reassociation, merges first the corresponding parts from both operands and then some further merges. The problem with the above expressions is that we get 3 different objects, var0 (the left shift), con1 (the right shift) and lit1 (80), so the infinite recursion prevention doesn't trigger, and we eventually merge con1 with lit1, which effectively reconstructs the original op1 and then associate that with var0 which is original op0, and associate_trees for that case calls fold_binary. There are some casts involved there too (the T typedef type and the underlying _BitInt type which are stripped with STRIP_NOPS). The following patch attempts to prevent this infinite recursion by tracking the origin (if certain var comes from nothing - 0, op0 - 1, op1 - 2 or both - 3) and propagates it through all the associate_tree calls which merge the vars. If near the end we'd try to merge what comes solely from op0 with what comes solely from op1 (or vice versa), the patch punts, because then it isn't any kind of reassociation between the two operands, if anything it should be handled when folding the suboperands. 2024-02-26 Jakub Jelinek PR middle-end/114084 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees if all subtrees of var0 come from one of the op0 or op1 operands and all subtrees of con0 come from the other one. Don't clear variables which are never used afterwards. * gcc.dg/bitint-94.c: New test. --- gcc/fold-const.cc | 51 ++++++++++++++++++++++++++++++++-------- gcc/testsuite/gcc.dg/bitint-94.c | 12 ++++++++++ 2 files changed, 53 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/bitint-94.c (limited to 'gcc') diff --git a/gcc/fold-const.cc b/gcc/fold-const.cc index 80e211e..43105d2 100644 --- a/gcc/fold-const.cc +++ b/gcc/fold-const.cc @@ -11779,6 +11779,15 @@ fold_binary_loc (location_t loc, enum tree_code code, tree type, + (lit0 != 0) + (lit1 != 0) + (minus_lit0 != 0) + (minus_lit1 != 0)) > 2) { + int var0_origin = (var0 != 0) + 2 * (var1 != 0); + int minus_var0_origin + = (minus_var0 != 0) + 2 * (minus_var1 != 0); + int con0_origin = (con0 != 0) + 2 * (con1 != 0); + int minus_con0_origin + = (minus_con0 != 0) + 2 * (minus_con1 != 0); + int lit0_origin = (lit0 != 0) + 2 * (lit1 != 0); + int minus_lit0_origin + = (minus_lit0 != 0) + 2 * (minus_lit1 != 0); var0 = associate_trees (loc, var0, var1, code, atype); minus_var0 = associate_trees (loc, minus_var0, minus_var1, code, atype); @@ -11791,15 +11800,19 @@ fold_binary_loc (location_t loc, enum tree_code code, tree type, if (minus_var0 && var0) { + var0_origin |= minus_var0_origin; var0 = associate_trees (loc, var0, minus_var0, MINUS_EXPR, atype); minus_var0 = 0; + minus_var0_origin = 0; } if (minus_con0 && con0) { + con0_origin |= minus_con0_origin; con0 = associate_trees (loc, con0, minus_con0, MINUS_EXPR, atype); minus_con0 = 0; + minus_con0_origin = 0; } /* Preserve the MINUS_EXPR if the negative part of the literal is @@ -11815,15 +11828,19 @@ fold_binary_loc (location_t loc, enum tree_code code, tree type, /* But avoid ending up with only negated parts. */ && (var0 || con0)) { + minus_lit0_origin |= lit0_origin; minus_lit0 = associate_trees (loc, minus_lit0, lit0, MINUS_EXPR, atype); lit0 = 0; + lit0_origin = 0; } else { + lit0_origin |= minus_lit0_origin; lit0 = associate_trees (loc, lit0, minus_lit0, MINUS_EXPR, atype); minus_lit0 = 0; + minus_lit0_origin = 0; } } @@ -11833,37 +11850,51 @@ fold_binary_loc (location_t loc, enum tree_code code, tree type, return NULL_TREE; /* Eliminate lit0 and minus_lit0 to con0 and minus_con0. */ + con0_origin |= lit0_origin; con0 = associate_trees (loc, con0, lit0, code, atype); - lit0 = 0; + minus_con0_origin |= minus_lit0_origin; minus_con0 = associate_trees (loc, minus_con0, minus_lit0, code, atype); - minus_lit0 = 0; /* Eliminate minus_con0. */ if (minus_con0) { if (con0) - con0 = associate_trees (loc, con0, minus_con0, - MINUS_EXPR, atype); + { + con0_origin |= minus_con0_origin; + con0 = associate_trees (loc, con0, minus_con0, + MINUS_EXPR, atype); + } else if (var0) - var0 = associate_trees (loc, var0, minus_con0, - MINUS_EXPR, atype); + { + var0_origin |= minus_con0_origin; + var0 = associate_trees (loc, var0, minus_con0, + MINUS_EXPR, atype); + } else gcc_unreachable (); - minus_con0 = 0; } /* Eliminate minus_var0. */ if (minus_var0) { if (con0) - con0 = associate_trees (loc, con0, minus_var0, - MINUS_EXPR, atype); + { + con0_origin |= minus_var0_origin; + con0 = associate_trees (loc, con0, minus_var0, + MINUS_EXPR, atype); + } else gcc_unreachable (); - minus_var0 = 0; } + /* Reassociate only if there has been any actual association + between subtrees from op0 and subtrees from op1 in at + least one of the operands, otherwise we risk infinite + recursion. See PR114084. */ + if (var0_origin != 3 && con0_origin != 3) + return NULL_TREE; + return fold_convert_loc (loc, type, associate_trees (loc, var0, con0, code, atype)); diff --git a/gcc/testsuite/gcc.dg/bitint-94.c b/gcc/testsuite/gcc.dg/bitint-94.c new file mode 100644 index 0000000..ca32043 --- /dev/null +++ b/gcc/testsuite/gcc.dg/bitint-94.c @@ -0,0 +1,12 @@ +/* PR middle-end/114084 */ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-std=c23 -pedantic-errors" } */ + +typedef unsigned _BitInt(31) T; +T a, b; + +void +foo (void) +{ + b = (T) ((a | (-1U >> 1)) >> 1 | (a | 5) << 4); +} -- cgit v1.1 From 24aa051af7c59f37ec45aea754b48b97d210ea6d Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 26 Feb 2024 10:08:45 +0100 Subject: match.pd: Guard 2 simplifications on integral TYPE_OVERFLOW_UNDEFINED [PR114090] These 2 patterns are incorrect on floating point, or for -fwrapv, or for -ftrapv, or the first one for unsigned types (the second one is mathematically correct, but we ought to just fold that to 0 instead). So, the following patch properly guards this. I think we don't need && !TYPE_OVERFLOW_SANITIZED (type) because in both simplifications there would be UB before and after on signed integer minimum. 2024-02-26 Jakub Jelinek PR tree-optimization/114090 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x): Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED types. ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise. * gcc.dg/pr114090.c: New test. --- gcc/match.pd | 10 ++++++---- gcc/testsuite/gcc.dg/pr114090.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr114090.c (limited to 'gcc') diff --git a/gcc/match.pd b/gcc/match.pd index 67007fc..f3fffd8 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -453,8 +453,9 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) /* (x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x. */ (simplify - (plus:c (max @0 integer_zerop) (max (negate @0) integer_zerop)) - (abs @0)) + (plus:c (max @0 integer_zerop) (max (negate @0) integer_zerop)) + (if (ANY_INTEGRAL_TYPE_P (type) && TYPE_OVERFLOW_UNDEFINED (type)) + (abs @0))) /* X * 1, X / 1 -> X. */ (for op (mult trunc_div ceil_div floor_div round_div exact_div) @@ -4218,8 +4219,9 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) /* (x <= 0 ? -x : 0) -> max(-x, 0). */ (simplify - (cond (le @0 integer_zerop@1) (negate@2 @0) integer_zerop@1) - (max @2 @1)) + (cond (le @0 integer_zerop@1) (negate@2 @0) integer_zerop@1) + (if (ANY_INTEGRAL_TYPE_P (type) && TYPE_OVERFLOW_UNDEFINED (type)) + (max @2 @1))) /* (zero_one == 0) ? y : z y -> ((typeof(y))zero_one * z) y */ (for op (bit_xor bit_ior plus) diff --git a/gcc/testsuite/gcc.dg/pr114090.c b/gcc/testsuite/gcc.dg/pr114090.c new file mode 100644 index 0000000..dcc2f8b --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr114090.c @@ -0,0 +1,38 @@ +/* PR tree-optimization/114090 */ +/* { dg-do run } */ +/* { dg-options "-O2 -fwrapv" } */ + +__attribute__((noipa)) int +foo (int x) +{ + int w = (x >= 0 ? x : 0); + int y = -x; + int z = (y >= 0 ? y : 0); + return w + z; +} + +__attribute__((noipa)) int +bar (int x) +{ + int w = (x >= 0 ? x : 0); + int z = (x <= 0 ? -x : 0); + return w + z; +} + +__attribute__((noipa)) int +baz (int x) +{ + return x <= 0 ? -x : 0; +} + +int +main () +{ + int v = -__INT_MAX__ - 1; + if (foo (v) != 0) + __builtin_abort (); + if (bar (v) != v) + __builtin_abort (); + if (baz (v) != v) + __builtin_abort (); +} -- cgit v1.1 From a25d7d1385087e0f43574064db45f1bc7d52f400 Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Mon, 26 Feb 2024 10:42:04 +0100 Subject: testsuite: xfail gcc.c-torture/compile/pr61159.c on Solaris/x86 with as [PR61159] gcc.c-torture/compile/pr61159.c currently FAILs on 32 and 64-bit Solaris/x86 with the native assembler: FAIL: gcc.c-torture/compile/pr61159.c -O0 (test for excess errors) FAIL: gcc.c-torture/compile/pr61159.c -O1 (test for excess errors) FAIL: gcc.c-torture/compile/pr61159.c -O2 (test for excess errors) FAIL: gcc.c-torture/compile/pr61159.c -O2 -flto (test for excess errors) FAIL: gcc.c-torture/compile/pr61159.c -O2 -flto -flto-partition=none (test for excess errors) FAIL: gcc.c-torture/compile/pr61159.c -O3 -g (test for excess errors) FAIL: gcc.c-torture/compile/pr61159.c -Os (test for excess errors) Excess errors: Assembler: pr61159.c "/var/tmp//ccRtFPva.s", line 5 : Cannot set a weak symbol to a common symbol This is a bug/limitation in the native assembler. Given that this hasn't seen fixes for a long time, this patch xfails the test. Tested on i386-pc-solaris2.11 (as and gas) and x86_64-pc-linux-gnu. 2024-02-24 Rainer Orth gcc/testsuite: PR ipa/61159 * gcc.c-torture/compile/pr61159.c: xfail on Solaris/x86 with as. --- gcc/testsuite/gcc.c-torture/compile/pr61159.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.c-torture/compile/pr61159.c b/gcc/testsuite/gcc.c-torture/compile/pr61159.c index dadd9c0..d2986d4 100644 --- a/gcc/testsuite/gcc.c-torture/compile/pr61159.c +++ b/gcc/testsuite/gcc.c-torture/compile/pr61159.c @@ -1,6 +1,6 @@ /* { dg-require-alias "" } */ /* { dg-require-weak "" } */ -/* { dg-xfail-if "weak alias" { powerpc-ibm-aix* } } */ +/* { dg-xfail-if "weak alias" { powerpc-ibm-aix* || { *86*-*-solaris* && { ! gas } } } } */ static int dummy = 0; extern int foo __attribute__((__weak__, __alias__("dummy"))); -- cgit v1.1 From f12697f3298566412386e5d70dc48a431e09b75f Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 26 Feb 2024 11:12:39 +0100 Subject: i386: Enable _BitInt support on ia32 Given the https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113837#c9 comment, the following patch just attempts to implement what I think is best for ia32. Compared to https://gitlab.com/x86-psABIs/i386-ABI/-/issues/5 , like that patch for _BitInt(64) or smaller it uses the smallest containing {,un}signed {char,short,int,long long} for passing/returning and layout of variables including in structures for alignment/size, with any extra bits unspecified. Unlike the above proposal, for larger _BitInt (i.e. _BitInt(65)+), it uses passing/returning/layout/alignment of structure containing minimum needed number of 32-bit limbs, again with the extra bits unspecified. This is because most operations (except copy or bitwise ops) on _BitInts aren't really vectorizable and will be under the hood implemented in loops over 32-bit limbs anyway (using 64-bit limbs under the hood would mean often using library implementation for the basic operations) and because ia32 doesn't align even long long/double in structures to 64-bit I think it is better to just use 32-bit alignment for that. And I don't see a reason to waste 32-bit bits say for _BitInt(224) or _BitInt(288) on ia32. So, effectively it is like the x86-64 _BitInt ABI with everything divided by 2, the only exception is that in x86-64 psABI _BitInt(128) is said to be already a structure of 2 limbs, which happens to be passed mostly the same as __int128 (except for alignment). 2024-02-26 Jakub Jelinek * config/i386/i386.cc (ix86_bitint_type_info): Add support for !TARGET_64BIT. --- gcc/config/i386/i386.cc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 86381b0..fc50685 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -25777,13 +25777,11 @@ ix86_get_excess_precision (enum excess_precision_type type) bool ix86_bitint_type_info (int n, struct bitint_info *info) { - if (!TARGET_64BIT) - return false; if (n <= 8) info->limb_mode = QImode; else if (n <= 16) info->limb_mode = HImode; - else if (n <= 32) + else if (n <= 32 || (!TARGET_64BIT && n > 64)) info->limb_mode = SImode; else info->limb_mode = DImode; -- cgit v1.1 From bb98f71bac8aace4e685e648a81dfaf365123833 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Sun, 25 Feb 2024 13:14:39 -0800 Subject: x86: Check interrupt instead of noreturn attribute ix86_set_func_type checks noreturn attribute to avoid incompatible attribute error in LTO1 on interrupt functions. Since TREE_THIS_VOLATILE is set also for _Noreturn without noreturn attribute, check interrupt attribute for interrupt functions instead. gcc/ PR target/114097 * config/i386/i386-options.cc (ix86_set_func_type): Check interrupt instead of noreturn attribute. gcc/testsuite/ PR target/114097 * gcc.target/i386/pr114097-1.c: New test. --- gcc/config/i386/i386-options.cc | 8 +++++--- gcc/testsuite/gcc.target/i386/pr114097-1.c | 26 ++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr114097-1.c (limited to 'gcc') diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 93a0114..1301f6b 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -3391,11 +3391,13 @@ ix86_set_func_type (tree fndecl) into a noreturn function by setting TREE_THIS_VOLATILE. Normally the local-pure-const pass is run after ix86_set_func_type is called. When the local-pure-const pass is enabled for LTO, the interrupt - function is marked as noreturn in the IR output, which leads the - incompatible attribute error in LTO1. */ + function is marked with TREE_THIS_VOLATILE in the IR output, which + leads to the incompatible attribute error in LTO1. Ignore the + interrupt function in this case. */ bool has_no_callee_saved_registers = ((TREE_THIS_VOLATILE (fndecl) - && lookup_attribute ("noreturn", DECL_ATTRIBUTES (fndecl)) + && !lookup_attribute ("interrupt", + TYPE_ATTRIBUTES (TREE_TYPE (fndecl))) && optimize && !optimize_debug && (TREE_NOTHROW (fndecl) || !flag_exceptions)) diff --git a/gcc/testsuite/gcc.target/i386/pr114097-1.c b/gcc/testsuite/gcc.target/i386/pr114097-1.c new file mode 100644 index 0000000..b14c7b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr114097-1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mtune-ctrl=^prologue_using_move,^epilogue_using_move -fomit-frame-pointer" } */ + +#define ARRAY_SIZE 256 + +extern int array[ARRAY_SIZE][ARRAY_SIZE][ARRAY_SIZE]; +extern int value (int, int, int) +#ifndef __x86_64__ +__attribute__ ((regparm(3))) +#endif +; + +void +_Noreturn +no_return_to_caller (void) +{ + unsigned i, j, k; + for (i = ARRAY_SIZE; i > 0; --i) + for (j = ARRAY_SIZE; j > 0; --j) + for (k = ARRAY_SIZE; k > 0; --k) + array[i - 1][j - 1][k - 1] = value (i, j, k); + while (1); +} + +/* { dg-final { scan-assembler-not "push" } } */ +/* { dg-final { scan-assembler-not "pop" } } */ -- cgit v1.1 From 39c07c5a3bf4a865175727bf60d5758372543b87 Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Mon, 26 Feb 2024 13:13:34 +0100 Subject: Finalization of object allocated by anonymous access designating local type The finalization of objects dynamically allocated through an anonymous access type is deferred to the enclosing library unit in the current implementation and a warning is given on each of them. However this cannot be done if the designated type is local, because this would generate dangling references to the local finalization routine, so the finalization needs to be dropped in this case and the warning adjusted. gcc/ada/ PR ada/113893 * exp_ch7.adb (Build_Anonymous_Master): Do not build the master for a local designated type. * exp_util.adb (Build_Allocate_Deallocate_Proc): Force Needs_Fin to false if no finalization master is attached to an access type and assert that it is anonymous in this case. * sem_res.adb (Resolve_Allocator): Mention that the object might not be finalized at all in the warning given when the type is an anonymous access-to-controlled type. gcc/testsuite/ * gnat.dg/access10.adb: New test. --- gcc/ada/exp_ch7.adb | 13 +++++++++ gcc/ada/exp_util.adb | 15 ++++++---- gcc/ada/sem_res.adb | 14 ++++----- gcc/testsuite/gnat.dg/access10.adb | 58 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 88 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gnat.dg/access10.adb (limited to 'gcc') diff --git a/gcc/ada/exp_ch7.adb b/gcc/ada/exp_ch7.adb index 2ac7310..e594a53 100644 --- a/gcc/ada/exp_ch7.adb +++ b/gcc/ada/exp_ch7.adb @@ -749,6 +749,7 @@ package body Exp_Ch7 is Desig_Typ : Entity_Id; FM_Id : Entity_Id; Priv_View : Entity_Id; + Scop : Entity_Id; Unit_Decl : Node_Id; Unit_Id : Entity_Id; @@ -787,6 +788,18 @@ package body Exp_Ch7 is Desig_Typ := Priv_View; end if; + -- For a designated type not declared at library level, we cannot create + -- a finalization collection attached to an outer unit since this would + -- generate dangling references to the dynamic scope through access-to- + -- procedure values designating the local Finalize_Address primitive. + + Scop := Enclosing_Dynamic_Scope (Desig_Typ); + if Scop /= Standard_Standard + and then Scope_Depth (Scop) > Scope_Depth (Unit_Id) + then + return; + end if; + -- Determine whether the current semantic unit already has an anonymous -- master which services the designated type. diff --git a/gcc/ada/exp_util.adb b/gcc/ada/exp_util.adb index 31cd47d..04d1146 100644 --- a/gcc/ada/exp_util.adb +++ b/gcc/ada/exp_util.adb @@ -936,6 +936,16 @@ package body Exp_Util is Needs_Finalization (Desig_Typ) and then not No_Heap_Finalization (Ptr_Typ); + -- The allocation/deallocation of a controlled object must be associated + -- with an attachment to/detachment from a finalization master, but the + -- implementation cannot guarantee this property for every anonymous + -- access tyoe, see Build_Anonymous_Collection. + + if Needs_Fin and then No (Finalization_Master (Ptr_Typ)) then + pragma Assert (Ekind (Ptr_Typ) = E_Anonymous_Access_Type); + Needs_Fin := False; + end if; + if Needs_Fin then -- Do nothing if the access type may never allocate / deallocate @@ -945,11 +955,6 @@ package body Exp_Util is return; end if; - -- The allocation / deallocation of a controlled object must be - -- chained on / detached from a finalization master. - - pragma Assert (Present (Finalization_Master (Ptr_Typ))); - -- The only other kind of allocation / deallocation supported by this -- routine is on / from a subpool. diff --git a/gcc/ada/sem_res.adb b/gcc/ada/sem_res.adb index 8e9714c..075c0d8 100644 --- a/gcc/ada/sem_res.adb +++ b/gcc/ada/sem_res.adb @@ -5679,19 +5679,19 @@ package body Sem_Res is Set_Is_Dynamic_Coextension (N, False); Set_Is_Static_Coextension (N, False); - -- Anonymous access-to-controlled objects are not finalized on - -- time because this involves run-time ownership and currently - -- this property is not available. In rare cases the object may - -- not be finalized at all. Warn on potential issues involving - -- anonymous access-to-controlled objects. + -- Objects allocated through anonymous access types are not + -- finalized on time because this involves run-time ownership + -- and currently this property is not available. In rare cases + -- the object might not be finalized at all. Warn on potential + -- issues involving anonymous access-to-controlled types. if Ekind (Typ) = E_Anonymous_Access_Type and then Is_Controlled_Active (Desig_T) then Error_Msg_N - ("??object designated by anonymous access object might " + ("??object designated by anonymous access value might " & "not be finalized until its enclosing library unit " - & "goes out of scope", N); + & "goes out of scope, or not be finalized at all", N); Error_Msg_N ("\use named access type instead", N); end if; end if; diff --git a/gcc/testsuite/gnat.dg/access10.adb b/gcc/testsuite/gnat.dg/access10.adb new file mode 100644 index 0000000..189df46 --- /dev/null +++ b/gcc/testsuite/gnat.dg/access10.adb @@ -0,0 +1,58 @@ +-- PR ada/113893 +-- Testcase by Pascal Pignard + +-- { dg-do run } + +with Ada.Text_IO; +with Ada.Finalization; + +procedure Access10 is + + generic + type Element_Type is private; + with function Image (Item : Element_Type) return String is <>; + package Sanitize is + type Container is new Ada.Finalization.Controlled with record + Data : Element_Type; + end record; + overriding procedure Finalize (Object : in out Container); + end Sanitize; + + package body Sanitize is + overriding procedure Finalize (Object : in out Container) is + begin + Ada.Text_IO.Put_Line ("Current:" & Image (Object.Data)); + end Finalize; + end Sanitize; + + procedure Test01 is + package Float_Sanitized is new Sanitize (Float, Float'Image); + V : Float_Sanitized.Container; + C : constant Float_Sanitized.Container := + (Ada.Finalization.Controlled with 8.8); + A : access Float_Sanitized.Container := + new Float_Sanitized.Container'(Ada.Finalization.Controlled with 7.7); -- { dg-warning "not be finalized|named" } + AC : access constant Float_Sanitized.Container := + new Float_Sanitized.Container'(Ada.Finalization.Controlled with 6.6); -- { dg-warning "not be finalized|named" } + begin + V.Data := 9.9 + C.Data + A.Data; + Ada.Text_IO.Put_Line ("Value:" & Float'Image (V.Data)); + end Test01; + + procedure Test02 is + type Float_Sanitized is new Float; + V : Float_Sanitized; + C : constant Float_Sanitized := (8.8); + A : access Float_Sanitized := new Float_Sanitized'(7.7); + AC : access constant Float_Sanitized := new Float_Sanitized'(6.6); + begin + V := 9.9 + C + A.all; + Ada.Text_IO.Put_Line ("Value:" & Float_Sanitized'Image (V)); + end Test02; + +begin + Ada.Text_IO.Put_Line ("Test01:"); + Test01; + Ada.Text_IO.Put_Line ("Test02:"); + Test02; +end; -- cgit v1.1 From 8293df8019adfffae3384cb6fb9cb6f496fe8608 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 26 Feb 2024 11:25:50 +0100 Subject: tree-optimization/114068 - missed virtual LC PHI after vect peeling When we choose the IV exit to be one leading to no virtual use we fail to have a virtual LC PHI even though we need it for the epilog entry. The following makes sure to create it so that later updating works. PR tree-optimization/114068 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge): New function. (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI on the main exit if needed. Remove band-aid for the case it was missing. * gcc.dg/vect/vect-early-break_118-pr114068.c: New testcase. * gcc.dg/vect/vect-early-break_119-pr114068.c: Likewise. --- .../gcc.dg/vect/vect-early-break_118-pr114068.c | 23 ++++++++++ .../gcc.dg/vect/vect-early-break_119-pr114068.c | 25 +++++++++++ gcc/tree-vect-loop-manip.cc | 52 ++++++++++++++++------ 3 files changed, 87 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/vect-early-break_118-pr114068.c create mode 100644 gcc/testsuite/gcc.dg/vect/vect-early-break_119-pr114068.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_118-pr114068.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_118-pr114068.c new file mode 100644 index 0000000..b462a46 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_118-pr114068.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-add-options vect_early_break } */ +/* { dg-require-effective-target vect_early_break } */ +/* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-O3" } */ + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ + +struct h { + int b; + int f; +} k; + +void n(int m) { + struct h a = k; + for (int o = m; o; ++o) { + if (a.f) + __builtin_unreachable(); + if (o > 1) + __builtin_unreachable(); + *(&k.b + o) = 1; + } +} diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_119-pr114068.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_119-pr114068.c new file mode 100644 index 0000000..a65ef7b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_119-pr114068.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-add-options vect_early_break } */ +/* { dg-require-effective-target vect_early_break } */ +/* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-O3" } */ + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ + +struct h { + int b; + int c; + int f; +} k; + +void n(int m) { + struct h a = k; + for (int o = m; o; ++o) { + if (a.f) + __builtin_unreachable(); + if (o > 1) + __builtin_unreachable(); + *(&k.b + o) = 1; + *(&k.c + o*m) = 2; + } +} diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc index 3f974d6..39bac1e 100644 --- a/gcc/tree-vect-loop-manip.cc +++ b/gcc/tree-vect-loop-manip.cc @@ -1429,6 +1429,32 @@ vect_set_loop_condition (class loop *loop, edge loop_e, loop_vec_info loop_vinfo (gimple *) cond_stmt); } +/* Get the virtual operand live on E. The precondition on this is valid + immediate dominators and an actual virtual definition dominating E. */ +/* ??? Costly band-aid. For the use in question we can populate a + live-on-exit/end-of-BB virtual operand when copying stmts. */ + +static tree +get_live_virtual_operand_on_edge (edge e) +{ + basic_block bb = e->src; + do + { + for (auto gsi = gsi_last_bb (bb); !gsi_end_p (gsi); gsi_prev (&gsi)) + { + gimple *stmt = gsi_stmt (gsi); + if (gimple_vdef (stmt)) + return gimple_vdef (stmt); + if (gimple_vuse (stmt)) + return gimple_vuse (stmt); + } + if (gphi *vphi = get_virtual_phi (bb)) + return gimple_phi_result (vphi); + bb = get_immediate_dominator (CDI_DOMINATORS, bb); + } + while (1); +} + /* Given LOOP this function generates a new copy of it and puts it on E which is either the entry or exit of LOOP. If SCALAR_LOOP is non-NULL, assume LOOP and SCALAR_LOOP are equivalent and copy the @@ -1595,6 +1621,18 @@ slpeel_tree_duplicate_loop_to_edge_cfg (class loop *loop, edge loop_exit, flush_pending_stmts (loop_exit); set_immediate_dominator (CDI_DOMINATORS, new_preheader, loop_exit->src); + /* If we ended up choosing an exit leading to a path not using memory + we can end up without a virtual LC PHI. Create it when it is + needed because of the epilog loop continuation. */ + if (need_virtual_phi && !get_virtual_phi (loop_exit->dest)) + { + tree header_def = gimple_phi_result (get_virtual_phi (loop->header)); + gphi *vphi = create_phi_node (copy_ssa_name (header_def), + new_preheader); + add_phi_arg (vphi, get_live_virtual_operand_on_edge (loop_exit), + loop_exit, UNKNOWN_LOCATION); + } + bool multiple_exits_p = loop_exits.length () > 1; basic_block main_loop_exit_block = new_preheader; basic_block alt_loop_exit_block = NULL; @@ -1711,19 +1749,7 @@ slpeel_tree_duplicate_loop_to_edge_cfg (class loop *loop, edge loop_exit, { /* Use the existing virtual LC SSA from exit block. */ gphi *vphi = get_virtual_phi (main_loop_exit_block); - /* ??? When the exit yields to a path without - any virtual use we can miss a LC PHI for the - live virtual operand. Simply choosing the - one live at the start of the loop header isn't - correct, but we should get here only with - early-exit vectorization which will move all - defs after the main exit, so leave a temporarily - wrong virtual operand in place. This happens - for gcc.dg/pr113659.c. */ - if (vphi) - new_arg = gimple_phi_result (vphi); - else - new_arg = gimple_phi_result (from_phi); + new_arg = gimple_phi_result (vphi); } else if ((res = new_phi_args.get (new_arg))) new_arg = *res; -- cgit v1.1 From fb68e2cac1283f731a3a979cb714621afb1ddfcc Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 26 Feb 2024 12:27:42 +0100 Subject: tree-optimization/114099 - virtual LC PHIs and early exit vect In some cases exits can lack LC PHI nodes for the virtual operand. We have to create them when the epilog loop requires them which also allows us to remove some only halfway correct fixups. This is the variant triggering for alternate exits. PR tree-optimization/114099 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Create and fill in a needed virtual LC PHI for the alternate exits. Remove code dealing with that missing. * gcc.dg/vect/vect-early-break_120-pr114099.c: New testcase. --- .../gcc.dg/vect/vect-early-break_120-pr114099.c | 20 +++++++++++++ gcc/tree-vect-loop-manip.cc | 35 ++++++++-------------- 2 files changed, 33 insertions(+), 22 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/vect-early-break_120-pr114099.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_120-pr114099.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_120-pr114099.c new file mode 100644 index 0000000..77e47e3 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_120-pr114099.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-add-options vect_early_break } */ +/* { dg-require-effective-target vect_early_break } */ +/* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-O3" } */ + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ + +int m; +void __attribute__((noreturn)) n(); +void t1(int jj, int l) { + for (int i = 1; i < l; i++) + { + int p = m++; + if (p) + n(); + if(jj <= i) + __builtin_unreachable(); + } +} diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc index 39bac1e..137b053 100644 --- a/gcc/tree-vect-loop-manip.cc +++ b/gcc/tree-vect-loop-manip.cc @@ -1667,17 +1667,18 @@ slpeel_tree_duplicate_loop_to_edge_cfg (class loop *loop, edge loop_exit, alt_loop_exit_block = split_edge (exit); if (!need_virtual_phi) continue; - if (vphi_def) - { - if (!vphi) - vphi = create_phi_node (copy_ssa_name (vphi_def), - alt_loop_exit_block); - else - /* Edge redirection might re-allocate the PHI node - so we have to rediscover it. */ - vphi = get_virtual_phi (alt_loop_exit_block); - add_phi_arg (vphi, vphi_def, exit, UNKNOWN_LOCATION); - } + /* When the edge has no virtual LC PHI get at the live + virtual operand by other means. */ + if (!vphi_def) + vphi_def = get_live_virtual_operand_on_edge (exit); + if (!vphi) + vphi = create_phi_node (copy_ssa_name (vphi_def), + alt_loop_exit_block); + else + /* Edge redirection might re-allocate the PHI node + so we have to rediscover it. */ + vphi = get_virtual_phi (alt_loop_exit_block); + add_phi_arg (vphi, vphi_def, exit, UNKNOWN_LOCATION); } set_immediate_dominator (CDI_DOMINATORS, new_preheader, @@ -1789,17 +1790,7 @@ slpeel_tree_duplicate_loop_to_edge_cfg (class loop *loop, edge loop_exit, if (virtual_operand_p (alt_arg)) { gphi *vphi = get_virtual_phi (alt_loop_exit_block); - /* ??? When the exit yields to a path without - any virtual use we can miss a LC PHI for the - live virtual operand. Simply choosing the - one live at the start of the loop header isn't - correct, but we should get here only with - early-exit vectorization which will move all - defs after the main exit, so leave a temporarily - wrong virtual operand in place. This happens - for gcc.c-torture/execute/20150611-1.c */ - if (vphi) - alt_arg = gimple_phi_result (vphi); + alt_arg = gimple_phi_result (vphi); } /* For other live args we didn't create LC PHI nodes. Do so here. */ -- cgit v1.1 From 10c73c111652208c5f9dc63a52933f4d6550cadd Mon Sep 17 00:00:00 2001 From: Joseph Myers Date: Mon, 26 Feb 2024 15:20:19 +0000 Subject: Update gcc sv.po, zh_CN.po * sv.po, zh_CN.po: Update. --- gcc/po/sv.po | 250 +++++++++++++++++++++++++++----------------------------- gcc/po/zh_CN.po | 224 +++++++++++++++++++++----------------------------- 2 files changed, 211 insertions(+), 263 deletions(-) (limited to 'gcc') diff --git a/gcc/po/sv.po b/gcc/po/sv.po index 5c182c3..ff07a75 100644 --- a/gcc/po/sv.po +++ b/gcc/po/sv.po @@ -1,8 +1,8 @@ # Swedish messages for gcc. -# Copyright © 2000, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023 Free Software Foundation, Inc. +# Copyright © 2000, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023, 2024 Free Software Foundation, Inc. # This file is distributed under the same license as the gcc package. # Dennis Björklund , 2000, 2001, 2002. -# Göran Uddeborg , 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023. +# Göran Uddeborg , 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023, 2024. # # Reminder to translator: GCC team does not want RCS keywords in the header! # @@ -11,26 +11,28 @@ # bb (basic block) gb (grundblock) # bundle bunt # cast typkonvertering -# crate back +# crate lår # chunk stycke # clique klick # harden härda # kind sort # load ladda +# map avbildning # offset avstånd # overload överlagra # rank ordning # scope räckvidd # store lagra # stride steg +# struct post # tile bricka # thunk snutt msgid "" msgstr "" -"Project-Id-Version: gcc 13.2.0\n" +"Project-Id-Version: gcc 14.1-b20240218\n" "Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n" "POT-Creation-Date: 2024-02-16 21:35+0000\n" -"PO-Revision-Date: 2023-07-29 18:00+0200\n" +"PO-Revision-Date: 2024-02-25 10:21+0100\n" "Last-Translator: Göran Uddeborg \n" "Language-Team: Swedish \n" "Language: sv\n" @@ -338,10 +340,8 @@ msgid "-install_name only allowed with -dynamiclib" msgstr "-install_name är bara tillåten med -dynamiclib" #: config/darwin.h:191 -#, fuzzy -#| msgid "-bundle not allowed with -dynamiclib" msgid "-bundle not allowed with -shared" -msgstr "-bundle är inte tillåten med -dynamiclib" +msgstr "-bundle är inte tillåten med -shared" #: config/darwin.h:192 msgid "-bundle not allowed with -dynamiclib" @@ -1045,7 +1045,7 @@ msgstr "Sätt modulentiteternas standardtillgänglighet till PRIVATE." #: fortran/lang.opt:721 #, no-c-format msgid "Handle OpenMP allocators for allocatables and pointers." -msgstr "" +msgstr "Hantera OpenMP-allokerare för allokerbara och pekare." #: fortran/lang.opt:725 #, no-c-format @@ -1200,10 +1200,9 @@ msgid "Conform to the ISO Fortran 2018 standard." msgstr "Följ standarden ISO Fortran 2018." #: fortran/lang.opt:896 -#, fuzzy, no-c-format -#| msgid "Conform to the ISO Fortran 2003 standard." +#, no-c-format msgid "Conform to the ISO Fortran 2023 standard." -msgstr "Följ standarden ISO Fortran 2003." +msgstr "Följ standarden ISO Fortran 2023." #: fortran/lang.opt:900 #, no-c-format @@ -1238,12 +1237,12 @@ msgstr "Varna för oändligt rekursiva anrop." #: rust/lang.opt:63 #, no-c-format msgid "-frust-crate= Set the crate name for the compilation" -msgstr "-frust-crate= Sätt backnamn för kompileringen" +msgstr "-frust-crate= Sätt lårnamn (crate) för kompileringen" #: rust/lang.opt:67 #, no-c-format msgid "-frust-extern= Specify where an external library is located" -msgstr "" +msgstr "-frust-extern= Ange var ett externt bibliotek är placerat" #: rust/lang.opt:71 #, no-c-format @@ -1251,10 +1250,9 @@ msgid "Dump various Rust front end internals." msgstr "Skriv ut diverse intern information från Rust-framänden." #: rust/lang.opt:75 -#, fuzzy, no-c-format -#| msgid "-frust-dump-\tDump Rust frontend internal information." +#, no-c-format msgid "-frust-dump- Dump Rust frontend internal information." -msgstr "-frust-dump-\tSkriv ut Rust-framändens interna information." +msgstr "-frust-dump- Skriv ut Rust-framändens interna information." #: rust/lang.opt:79 #, no-c-format @@ -1262,21 +1260,19 @@ msgid "Enable experimental compilation of Rust files at your own risk" msgstr "Aktivera experimentell kompilering av Rust-filer på egen risk" #: rust/lang.opt:83 -#, fuzzy, no-c-format -#| msgid "-frust-max-recursion-depth=integer" +#, no-c-format msgid "-frust-max-recursion-depth=" -msgstr "-frust-max-recursion-depth=heltal" +msgstr "-frust-max-recursion-depth=" #: rust/lang.opt:87 #, no-c-format msgid "-frust-crate-type=[bin|lib|rlib|dylib|cdylib|staticlib|proc-macro] Crate type to emit" -msgstr "" +msgstr "-frust-crate-type=[bin|lib|rlib|dylib|cdylib|staticlib|proc-macro] Lår (crate) att skapa" #: rust/lang.opt:115 -#, fuzzy, no-c-format -#| msgid "-frust-mangling=[legacy|v0] Choose which version to use for name mangling" +#, no-c-format msgid "-frust-mangling=[legacy|v0] Version to use for name mangling" -msgstr "-frust-mangling=[legacy|v0] Välj vilken version som skall användas för namnmangling" +msgstr "-frust-mangling=[legacy|v0] Version att använda för namnmangling" #: rust/lang.opt:128 #, no-c-format @@ -1284,37 +1280,34 @@ msgid "-frust-cfg= Set a config expansion option" msgstr "-frust-cfg= Ange ett konfigurationsutökningsalternativ" #: rust/lang.opt:132 -#, fuzzy, no-c-format -#| msgid "-frust-edition=[2015|2018|2021] Choose which edition to use when compiling rust code" +#, no-c-format msgid "-frust-edition=[2015|2018|2021] Edition to use when compiling rust code" -msgstr "-frust-edition=[2015|2018|2021] Välj vilken utgåva som skall användas vid kompilering av rust-kod" +msgstr "-frust-edition=[2015|2018|2021] Utgåva att använda vid kompilering av rust-kod" #: rust/lang.opt:148 -#, fuzzy, no-c-format -#| msgid "Flag to enable embeding metadata directly into object files" +#, no-c-format msgid "Enable embedding metadata directly into object files" -msgstr "Flagga för att akvivera inbäddad metadata direkt i objektfiler" +msgstr "Aktivera inbäddad metadata direkt i objektfiler" #: rust/lang.opt:152 #, no-c-format msgid "-frust-metadata-output= Path to output crate metadata" -msgstr "-frust-metadata-output= Sökväg till utdatabackens metadata" +msgstr "-frust-metadata-output= Sökväg till utdatalårens (crate) metadata" #: rust/lang.opt:160 -#, fuzzy, no-c-format -#| msgid "-frust-compile-until=[ast|attributecheck|expansion|nameresolution|lowering|typecheck|privacy|unsafety|const|copimlation|end] When to stop in the pipeline when compiling Rust code" +#, no-c-format msgid "-frust-compile-until=[ast|attributecheck|expansion|astvalidation|featuregating|nameresolution|lowering|typecheck|privacy|unsafety|const|borrowcheck|compilation|end] The pipeline will run up until this stage when compiling Rust code" -msgstr "-frust-compile-until=[ast|attributecheck|expansion|nameresolution|lowering|typecheck|privacy|unsafety|const|copimlation|end] När pipelinen skall stoppas vid kompilering av Rust-kod" +msgstr "-frust-compile-until=[ast|attributecheck|expansion|astvalidation|featuregating|nameresolution|lowering|typecheck|privacy|unsafety|const|borrowcheck|compilation|end] Pipelinen kommer köra fram till detta steg vid kompilering av Rust-kod" #: rust/lang.opt:209 #, no-c-format msgid "Use the temporary and experimental name resolution pipeline instead of the stable one" -msgstr "" +msgstr "Använd den temporära och experimentella namnuppslagningspipelinen istället för den stabila" #: rust/lang.opt:213 #, no-c-format msgid "Use the WIP borrow checker." -msgstr "" +msgstr "Använd WIP-lånekontrolleraren." #: c-family/c.opt:182 #, no-c-format @@ -1409,18 +1402,17 @@ msgstr "-MT \tLägg till ett mål som inte kräver citationstecken." #: c-family/c.opt:261 #, no-c-format msgid "Structured format for output dependency information. Supported (\"p1689r5\")." -msgstr "" +msgstr "Strukturerat format för utmatning av beroendeinformation. Stödjs (”p1689r5”)." #: c-family/c.opt:265 -#, fuzzy, no-c-format -#| msgid "Generate C++ Module dependency information." +#, no-c-format msgid "File for output dependency information." -msgstr "Generera C++ modulberoendeinformation." +msgstr "Fil för utdataberoendeinformation." #: c-family/c.opt:269 #, no-c-format msgid "-fdeps-target=obj.o Output file for the compile step." -msgstr "" +msgstr "-fdeps-target=obj.o Utmatningsfil för kompileringssteget." #: c-family/c.opt:273 #, no-c-format @@ -1490,7 +1482,7 @@ msgstr "Varna vid all användning av alloca." #: c-family/c.opt:340 #, no-c-format msgid "Warn when allocating insufficient storage for the target type of the assigned pointer." -msgstr "" +msgstr "Varna när otillräckligt med lagring allokeras för måltypen för den tilldelade pekaren." #: c-family/c.opt:344 #, no-c-format @@ -1568,16 +1560,14 @@ msgid "Warn when a built-in preprocessor macro is undefined or redefined." msgstr "Varna när ett inbyggt preprocessormakro avdefinieras eller omdefinieras." #: c-family/c.opt:438 -#, fuzzy, no-c-format -#| msgid "Warn about features not present in ISO C11, but present in ISO C2X." +#, no-c-format msgid "Warn about features not present in ISO C11, but present in ISO C23." -msgstr "Varna för funktioner som inte finns i ISO C11, men finns i ISO C2X." +msgstr "Varna för funktioner som inte finns i ISO C11, men finns i ISO C23." #: c-family/c.opt:442 -#, fuzzy, no-c-format -#| msgid "Deprecated in favor of -std=c11." +#, no-c-format msgid "Deprecated in favor of -Wc11-c23-compat." -msgstr "Undanbedes till förmån för -std=c11." +msgstr "Undanbedes till förmån för -Wc11-c23-compat." #: c-family/c.opt:446 #, no-c-format @@ -1640,10 +1630,9 @@ msgid "Warn about C++23 constructs in code compiled with an older standard." msgstr "Varna för C++23-konstruktioner i kod kompilerad med en äldre standard." #: c-family/c.opt:503 -#, fuzzy, no-c-format -#| msgid "Warn about C++20 constructs in code compiled with an older standard." +#, no-c-format msgid "Warn about C++26 constructs in code compiled with an older standard." -msgstr "Varna för C++20-konstruktioner i kod kompilerad med en äldre standard." +msgstr "Varna för C++26-konstruktioner i kod kompilerad med en äldre standard." #: c-family/c.opt:507 #, fuzzy, no-c-format @@ -1852,7 +1841,7 @@ msgstr "Varna för brott mot stilreglerna i Effective C++." #: c-family/c.opt:683 #, no-c-format msgid "Warn if an additional enum-base is used in an elaborated-type-specifier." -msgstr "" +msgstr "Varna om en ytterligare enum-bas används i en elaborated-type-specifier." #: c-family/c.opt:687 #, no-c-format @@ -1902,7 +1891,7 @@ msgstr "Varna för semikolon efter funktionsdefinitioner i klassen." #: c-family/c.opt:731 #, no-c-format msgid "Warn when a structure containing a C99 flexible array member as the last field is not at the end of another structure." -msgstr "" +msgstr "Varna när en post som innehåller en flexibel vektormedlem enligt C99 som sista fält inte är vid slutet av en annan post." #: c-family/c.opt:736 #, no-c-format @@ -2309,7 +2298,7 @@ msgstr "Varna för åsidosättande initierare utan sidoeffekter." #: c-family/c.opt:1129 #, no-c-format msgid "Warn if the named return value optimization is not performed although it is allowed." -msgstr "" +msgstr "Varna om optimeringen av ett namngivet returvärde inte utförs trots att det är tillåtet." #: c-family/c.opt:1133 #, no-c-format @@ -2419,7 +2408,7 @@ msgstr "Varna när ett argument skickas till restrict-kvalificerade parameterali #: c-family/c.opt:1226 #, no-c-format msgid "Warn whenever void-returning functions return a non-void expressions, or a return expression is missing in a function not returning void." -msgstr "" +msgstr "Varna närhelst void-returnerande funktioner returnerar ett yttryck som inte äv void, eller ett returuttryck saknas i en funktion som inte returnerar void." #: c-family/c.opt:1230 #, no-c-format @@ -3022,7 +3011,7 @@ msgstr "Anta normal C-körmiljö." #: c-family/c.opt:1915 #, no-c-format msgid "Implement P2564 for consteval propagation." -msgstr "" +msgstr "Implementera P2564 för consteval-propagering." #: c-family/c.opt:1919 #, no-c-format @@ -4081,7 +4070,7 @@ msgstr "Länka standard D-biblioteket dynamiskt i kompileringen." #: m2/lang.opt:35 #, no-c-format msgid "turns on case statement label compile time checking when using an expression of an enum type." -msgstr "" +msgstr "slår på kontroller av etiketter i case-satser vid kompileringstillfället när ett uttryck av en enum-typ används." #: m2/lang.opt:39 #, no-c-format @@ -4106,12 +4095,12 @@ msgstr "extra semantiska kontroller vid kompileringstillfället, typiskt försö #: m2/lang.opt:55 #, no-c-format msgid "turns on compile time analysis in the first basic block of a procedure detecting access to uninitialized data." -msgstr "" +msgstr "slår på analys vid kompileringstillfället i det första grundblocket i en procedurdetekterad åtkomst av oinitierade data." #: m2/lang.opt:59 #, no-c-format msgid "turns on compile time analysis to detect access to uninitialized variables, the checking can be specified by: known,cond,all." -msgstr "" +msgstr "slår på analys vid kompileringstillfället för att upptäcka åtkomst av oinitierade variabler, kontrollerandet kan anges med :known,cond,all." #: m2/lang.opt:63 #, no-c-format @@ -4411,7 +4400,7 @@ msgstr "-fgo-embedcfg=\tLista inbäddade filer via go:embed." #: go/lang.opt:66 #, no-c-format msgid "-fgo-importcfg=\tProvide file that tells where to find imports." -msgstr "" +msgstr "-fgo-importcfg=\tGe fil som säger var importer finns." #: go/lang.opt:70 #, no-c-format @@ -4496,22 +4485,22 @@ msgstr "Det maximala djupet av exploderade noder som skall förekomma i en dot-d #: analyzer/analyzer.opt:59 #, no-c-format msgid "The number of bytes at which to ellipsize string literals in analyzer text art diagrams." -msgstr "" +msgstr "Antalet byte vid vilket strängliteraler i textkonstdiagram från analyseraren skall ha ellips." #: analyzer/analyzer.opt:63 #, no-c-format msgid "The number of literal bytes to show at the head of a string literal in text art when ellipsizing it." -msgstr "" +msgstr "Antalet literala byte att visa vid huvudet av en strängliteral i textkonst när den har ellips." #: analyzer/analyzer.opt:67 #, no-c-format msgid "The number of literal bytes to show at the tail of a string literal in text art when ellipsizing it." -msgstr "" +msgstr "Antalet literala byt att visa vid slutet av en strängliteral i textkonst när den har ellips." #: analyzer/analyzer.opt:71 #, no-c-format msgid "The ideal width in characters of text art diagrams generated by the analyzer." -msgstr "" +msgstr "Den ideala bredden i tecken för textkonstdiagram som genereras ava analysatorn." #: analyzer/analyzer.opt:75 #, no-c-format @@ -4775,7 +4764,7 @@ msgstr "Begränsa analyseraren till att köra just den namngivna kontrollen." #: analyzer/analyzer.opt:279 #, no-c-format msgid "Add extra annotations to diagrams." -msgstr "" +msgstr "Lägg till extra annotationer till diagram." #: analyzer/analyzer.opt:283 #, no-c-format @@ -4815,7 +4804,7 @@ msgstr "Aktivera transitivitet av begränsningar under analysen." #: analyzer/analyzer.opt:311 #, no-c-format msgid "Show events within system headers in analyzer execution paths." -msgstr "" +msgstr "Visa händelser inom systemhuvuden i analyserarens körvägar." #: analyzer/analyzer.opt:315 #, no-c-format @@ -5880,7 +5869,7 @@ msgstr "-march=\tGenerera kod för angiven RISC-V ISA (t.ex. RV64IM). ISA-strä #: config/riscv/riscv.opt:91 #, no-c-format msgid "-march=help\tPrint supported -march extensions." -msgstr "" +msgstr "-march=help\tSkriv ut de utökningar av -march som stödjs." #: config/riscv/riscv.opt:103 config/mips/mips.opt:430 #, no-c-format @@ -6027,7 +6016,7 @@ msgstr "Reducera stackjusteringen vid anropsplatsen om möjligt." #: config/riscv/riscv.opt:529 #, no-c-format msgid "Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64)." -msgstr "" +msgstr "Max antal byte att jämföra som en del av inline:ade strcmp/strncmp-rutiner (standard: 64)." #: config/riscv/riscv.opt:533 #, fuzzy, no-c-format @@ -6038,17 +6027,17 @@ msgstr "Giltiga argument till -mcode-readable=:" #: config/riscv/riscv.opt:546 #, no-c-format msgid "-param=riscv-autovec-preference=\tSet the preference of auto-vectorization in the RISC-V port." -msgstr "" +msgstr "-param=riscv-autovec-preference=\tSätt preferensen för autovektorisering i RISC-V-porteringen." #: config/riscv/riscv.opt:550 #, no-c-format msgid "The RVV possible LMUL (-param=riscv-autovec-lmul=):" -msgstr "" +msgstr "De RVV-möjliga LMUL (-param=riscv-autovec-lmul=):" #: config/riscv/riscv.opt:569 #, no-c-format msgid "-param=riscv-autovec-lmul=\tSet the RVV LMUL of auto-vectorization in the RISC-V port." -msgstr "" +msgstr "-param=riscv-autovec-lmul=\tSätt RVV LMUL:en för autovektorisering i RISC-V-porteringen." #: config/riscv/riscv.opt:576 #, fuzzy, no-c-format @@ -6059,7 +6048,7 @@ msgstr "Giltiga argument till -mstringop-strategy=:" #: config/riscv/riscv.opt:589 #, no-c-format msgid "-param=vsetvl-strategy=\tSet the optimization level of VSETVL insert pass." -msgstr "" +msgstr "-param=vsetvl-strategy=\tSätt optimeringsnivån för VSETVL-infogningspasset." #: config/riscv/riscv.opt:593 config/i386/i386.opt:496 #, no-c-format @@ -6317,7 +6306,7 @@ msgstr "Aktivera approximationen av division. Att aktivera detta reducerar prec #: config/aarch64/aarch64.opt:254 #, no-c-format msgid "Specify when to enable an early register allocation pass. The possibilities are: all functions, functions that have access to strided multi-register instructions, and no functions." -msgstr "" +msgstr "Ange när ett tidigt registerallokeringspass skall aktiveras. Möjligheterna är: alla funktioner, funktioner som har tillgång till stegvisa multiregisterinstruktioner och inga funktioner." #: config/aarch64/aarch64.opt:260 #, no-c-format @@ -6342,12 +6331,12 @@ msgstr "Generera kod för att spåra när CPU:n kan spekulera felaktigt." #: config/aarch64/aarch64.opt:294 #, no-c-format msgid "Enable the copy of the AArch64 load/store pair fusion pass that runs before register allocation." -msgstr "" +msgstr "Aktivera kopieringen av sammanslagningspasset av load/store-par för AArch64 som köre före registerallokering." #: config/aarch64/aarch64.opt:299 #, no-c-format msgid "Enable the copy of the AArch64 load/store pair fusion pass that runs after register allocation." -msgstr "" +msgstr "Aktivera kopieringen av sammanslagningspasset av load/store-par för AArch64 som köre efter registerallokering." #: config/aarch64/aarch64.opt:318 #, no-c-format @@ -6367,7 +6356,7 @@ msgstr "Generera lokala anrop till atomära operationer utanför linjen." #: config/aarch64/aarch64.opt:337 #, no-c-format msgid "When vectorizing, consider using multiple different approaches and use the cost model to choose the cheapest one." -msgstr "" +msgstr "Överväg vid vektorisering att använda flera olika tillvägagångssätt och använd kostnadsmodellen för att välja den billigaste." #: config/aarch64/aarch64.opt:342 #, no-c-format @@ -6402,22 +6391,22 @@ msgstr "Begränsa hur mycket autovektoriseraren får rulla ut en slinga." #: config/aarch64/aarch64.opt:372 #, no-c-format msgid "--param=aarch64-ldp-policy=[default|always|never|aligned] Fine-grained policy for load pairs." -msgstr "" +msgstr "--param=aarch64-ldp-policy=[default|always|never|aligned] Finkorning policy för laddningspar." #: config/aarch64/aarch64.opt:376 #, no-c-format msgid "--param=aarch64-stp-policy=[default|always|never|aligned] Fine-grained policy for store pairs." -msgstr "" +msgstr "--param=aarch64-stp-policy=[default|always|never|aligned] Finkorning policy för lagringspar." #: config/aarch64/aarch64.opt:395 #, no-c-format msgid "Limit on number of alias checks performed when attempting to form an ldp/stp." -msgstr "" +msgstr "Gräns på antal aliaskontroller som utförs vid försök att forma en ldp/stp." #: config/aarch64/aarch64.opt:399 #, no-c-format msgid "Param to control which writeback opportunities we try to handle in the load/store pair fusion pass. A value of zero disables writeback handling. One means we try to form pairs involving one or more existing individual writeback accesses where possible. A value of two means we also try to opportunistically form writeback opportunities by folding in trailing destructive updates of the base register used by a pair." -msgstr "" +msgstr "Parameter för att styra vilka återskrivningsmöjligheter vi försöker hantera i sammanslagningspasset av load/store-par. Värdet noll avaktiverar återskrivningshantering. Ett betyder att vi försöker forma par som inbegriper en eller flera återskrivningsåtkomster när möjligt. Ett värde på två betyder att vi även försöker att opportunistiskt forma återskrivningsmöjligheter genom vikning i avslutande destruktiva uppdateringar av basregistret som används av ett par." #: config/linux.opt:24 #, no-c-format @@ -7020,7 +7009,7 @@ msgstr "Placera relokerad endast läsbar data i .data-sektionen." #: config/i386/mingw.opt:23 #, no-c-format msgid "Preprocess, compile or link with specified C RunTime DLL library." -msgstr "" +msgstr "Preprocessa, kompilera eller länka med det angivna C körtids-DLL-biblioteket." #: config/i386/mingw.opt:33 #, no-c-format @@ -7374,7 +7363,7 @@ msgstr "Känd föredragen registervektorlängd (att användas med flaggan -mpref #: config/i386/i386.opt:652 #, no-c-format msgid "Enable floating-point status flags setting SSE vector operations on partial vectors." -msgstr "" +msgstr "Aktivera SSE-vektoroperationer för flyttal som sätter statusflaggor på partiella vektorer." #: config/i386/i386.opt:656 #, no-c-format @@ -8090,12 +8079,12 @@ msgstr "Aktivera vektorisering av träd." #: config/i386/i386.opt:1331 #, no-c-format msgid "Support code generation for APX features, including EGPR, PUSH2POP2, NDD and PPX." -msgstr "" +msgstr "Stöd kodgenerering för APX-funktioner, inklusive EGPR, PUSH2POP2, NDD och PPX." #: config/i386/i386.opt:1360 #, no-c-format msgid "Enable GPR32 in inline asm when APX_F enabled." -msgstr "" +msgstr "Aktivera GPR32 i inline:ad asm när APX_F är aktiverat." #: config/i386/i386.opt:1364 #, fuzzy, no-c-format @@ -8570,12 +8559,12 @@ msgstr "När RAM skall nås, använd X som hårdvaran framtvingar, d.v.s. använ #: config/avr/avr.opt:99 #, no-c-format msgid "The device has the bitfield NVMCTRL_CTRLB.FLMAP. This option is used internally." -msgstr "" +msgstr "Enheten har bitfältet NVMCTRL_CTRLB.FLMAP. Denna flagga används internt." #: config/avr/avr.opt:103 #, no-c-format msgid "The device has the .rodata section located in the RAM area." -msgstr "" +msgstr "Enheten har sektionen .rodata placerad i RAM-området." #: config/avr/avr.opt:108 #, no-c-format @@ -8915,7 +8904,7 @@ msgstr "Slagra alla argumentregister på stacken." #: config/s390/s390.opt:335 #, no-c-format msgid "Assume external symbols to be potentially unaligned. By default all symbols without explicit alignment are assumed to reside on a 2 byte boundary as mandated by the IBM Z ABI." -msgstr "" +msgstr "Anta att externa symboler potentiellt är ojusterade. Som standard antas alla symboler utan en explicit justering att ligga på en 2-bytegräns så som IBM Z ABI:et kräver." #: config/rl78/rl78.opt:27 config/rx/elf.opt:26 config/csky/csky.opt:198 #, no-c-format @@ -10235,12 +10224,12 @@ msgstr "-march=ISA\tGenerera kod för den angivna ISA:n." #: config/loongarch/loongarch.opt:98 #, no-c-format msgid "Enable LoongArch SIMD Extension (LSX, 128-bit)." -msgstr "" +msgstr "Aktivera LoongArch SIMD-utvidgningen (LSX, 128-bitar)." #: config/loongarch/loongarch.opt:102 #, no-c-format msgid "Enable LoongArch Advanced SIMD Extension (LASX, 256-bit)." -msgstr "" +msgstr "Aktivera LoongArch Advanced SIMD-utvidgningen (LASX, 256-bit)." #: config/loongarch/loongarch.opt:107 #, no-c-format @@ -10346,7 +10335,7 @@ msgstr "Stöd flaggbevarande add-carry-instruktioner." #: config/loongarch/loongarch.opt:280 #, no-c-format msgid "Support div.w[u] and mod.w[u] instructions with inputs not sign-extended." -msgstr "" +msgstr "Stöd instruktionerna div.w[u] och mod.w[u] med indata som inte är teckenutvidgat." #: config/loongarch/loongarch.opt:284 #, fuzzy, no-c-format @@ -10363,7 +10352,7 @@ msgstr "Stöd instruktionerna XSAVEC." #: config/loongarch/loongarch.opt:292 #, no-c-format msgid "Do not need load-load barriers (dbar 0x700)." -msgstr "" +msgstr "Behöver inte load-load-barriärer (dbar 0x700)." #: config/or1k/elf.opt:28 #, no-c-format @@ -13457,7 +13446,7 @@ msgstr "Aktivera operationskoderna ENTER_S och LEAVE_S för ARCv2." #: config/vxworks-smp.opt:25 #, no-c-format msgid "Select VxWorks SMP C runtimes for linking." -msgstr "" +msgstr "Välj körtids VxWorks SMP C till länkning." #: lto/lang.opt:50 #, no-c-format @@ -13717,7 +13706,7 @@ msgstr "Varna vid försök att frigöra ett icke-heap-objekt." #: common.opt:639 #, no-c-format msgid "Warn when -fhardened did not enable an option from its set." -msgstr "" +msgstr "Varna när -fardened inte aktiverade någon flagga från sin uppsättning." #: common.opt:650 #, no-c-format @@ -14203,7 +14192,7 @@ msgstr "Utför ett optimeringspass för kopieringspropagering av register." #: common.opt:1263 #, no-c-format msgid "Fold instructions calculating memory offsets to the memory access instruction if possible." -msgstr "" +msgstr "Vik instruktioner som beräknar minnesavstånd till minnesåtkomstinstruktionen om möjligt." #: common.opt:1267 #, no-c-format @@ -14394,7 +14383,7 @@ msgstr "Visa stackdjup för händelser i vägar." #: common.opt:1525 #, no-c-format msgid "-fdiagnostics-text-art-charset=[none|ascii|unicode|emoji]\tDetermine which characters to use in text arg diagrams." -msgstr "" +msgstr "-fdiagnostics-text-art-charset=[none|ascii|unicode|emoji]\tBestäm vilka tecken som används i textargumentdiagram." #: common.opt:1544 #, no-c-format @@ -14659,7 +14648,7 @@ msgstr "Aktivera att grensannolikheter gissas." #: common.opt:1834 #, no-c-format msgid "Enable various security-relevant flags." -msgstr "" +msgstr "Aktivera olika säkerhetsrelevanta flaggor." #: common.opt:1838 #, no-c-format @@ -14686,17 +14675,17 @@ msgstr "avaktivera pass %s för funktionen %s" #: common.opt:1854 #, no-c-format msgid "Check CFR execution paths also before calls followed by returns of their results." -msgstr "" +msgstr "Kontrollera CFR-körvägen även före anrop som följs av returer av deras resultat." #: common.opt:1858 #, no-c-format msgid "Check CFR execution paths also when exiting a function through an exception." -msgstr "" +msgstr "Kontrollera CFR-körvägen även vid avslut av en funktion genom ett undantag." #: common.opt:1862 #, no-c-format msgid "-fhardcfr-check-noreturn-calls=[always|no-xthrow|nothrow|never]\tCheck CFR execution paths also before calling noreturn functions." -msgstr "" +msgstr "-fhardcfr-check-noreturn-calls=[always|no-xthrow|nothrow|never]\tKontrollera CFR-körvägar även före anrop av noreturn-funktioner." #: common.opt:1885 #, no-c-format @@ -14766,7 +14755,7 @@ msgstr "Inline:a __atomic-operationer när en låsningsfri instruktionssekvens #: common.opt:1968 #, no-c-format msgid "-finline-stringops[=memcmp|memcpy|memmove|memset] Expand supported mem/str operations inline, even if against optimization." -msgstr "" +msgstr "-finline-stringops[=memcmp|memcpy|memmove|memset] Expandera de stödda mem/str operationerna inline, även om det är emot optimeringen." #: common.opt:1999 #, no-c-format @@ -15652,17 +15641,17 @@ msgstr "Behandla spill med tecken som odefinierat. Negeras som -fwrapv -fwrapv- #: common.opt:2931 #, no-c-format msgid "Disable stack scrub entirely, disregarding strub attributes." -msgstr "" +msgstr "Avaktivera helt stackskrubbning, bortse från strub-attribut." #: common.opt:2935 #, no-c-format msgid "Enable stack scrub as per attributes, with strict call checking." -msgstr "" +msgstr "Aktivera stackskrubbning enligt attribut, med strikt anropskontroll." #: common.opt:2944 #, no-c-format msgid "Restore default strub mode: as per attributes, with relaxed checking." -msgstr "" +msgstr "Återställ strub-läget: enligt attribut, med lättare kontroller." #: common.opt:2948 #, fuzzy, no-c-format @@ -15673,7 +15662,7 @@ msgstr "Aktivera hwasan-instrumentering av inbyggda funktioner." #: common.opt:2952 #, no-c-format msgid "Enable at-calls stack scrubbing for all viable functions." -msgstr "" +msgstr "Aktivera stackskrubbning vid anrop för alla möjliga funktioner." #: common.opt:2956 #, fuzzy, no-c-format @@ -15734,7 +15723,7 @@ msgstr "För mål som normalt använder trampoliner för nästade funktioner, ge #: common.opt:3016 #, no-c-format msgid "Whether trampolines are generated in executable memory rather than executable stack." -msgstr "" +msgstr "Huruvida trampoliner genereras i körbart minne snarare än på körbar stack." #: common.opt:3034 #, no-c-format @@ -16470,7 +16459,7 @@ msgstr "Skalfaktor att använda på antalet satser i en trådningsväg som korsa #: params.opt:139 #, no-c-format msgid "Whether the target fully pipelines FMA instructions. If non-zero, reassociation considers the benefit of parallelizing FMA's multiplication part and addition part, assuming FMUL and FMA use the same units that can also do FADD." -msgstr "" +msgstr "Huruvida målet fullt ut använder pipeline för FMA-instruktioner. Om skilt från noll bedömer reassocieringar fördelen av att parallellisera FMA:ers multiplikationsdel och additionsdel, under antagandet att FMUL och FMA använder samma enheter som även kan göra FADD." # Undrar om jag fattat syftningen i "critical edges execution count" rätt! #: params.opt:146 @@ -16526,12 +16515,12 @@ msgstr "Maximalt antal parameter i en SCoP." #: params.opt:186 #, no-c-format msgid "Maximum number of blocks for -fharden-control-flow-redundancy." -msgstr "" +msgstr "Maximalt antal block för -fharden-control-flow-redundancy." #: params.opt:190 #, no-c-format msgid "Maximum number of blocks for in-line -fharden-control-flow-redundancy." -msgstr "" +msgstr "Maximalt antal block för inline -fharden-control-flow-redundancy." #: params.opt:194 #, no-c-format @@ -17592,7 +17581,7 @@ msgstr "Det maximala antalet nästade anrop att söka i efter styrberoenden unde #: params.opt:1126 #, no-c-format msgid "Maximum number of predicates anded for each predicate ored in the normalized predicate chain." -msgstr "" +msgstr "Maximalt antal predikat med \"and\" för varje predikat med \"or\" i den normaliserade predikatkedjan." #: params.opt:1131 #, fuzzy, no-c-format @@ -22429,15 +22418,15 @@ msgstr "antalet resultat stämmer inte med antalet värden" #: go/gofrontend/expressions.cc:14671 msgid "invalid 3-index slice of object that is not a slice" -msgstr "" +msgstr "ogiltig 3-indexskiva av objekt som inte är en skiva" #: go/gofrontend/expressions.cc:14674 msgid "attempt to slice object that is not array, slice, or string" -msgstr "" +msgstr "försök att skiva objekt som inte är en vektor, skiva eller sträng" #: go/gofrontend/expressions.cc:14677 msgid "attempt to index object that is not array, slice, string, or map" -msgstr "" +msgstr "försök att indexera objekt som inte är en vektor, skiva, sträng eller avbildning" #: go/gofrontend/expressions.cc:14730 #, fuzzy @@ -22467,15 +22456,15 @@ msgstr "gränssnitt eller pekare till gränssnitt förväntades" #: go/gofrontend/expressions.cc:18212 msgid "may only omit types within composite literals of slice, array, or map type" -msgstr "" +msgstr "kan endast utelämna typer med sammanstatta litteraler av typen skiva, vektor eller avbildning" #: go/gofrontend/expressions.cc:18306 go/gofrontend/expressions.cc:18618 msgid "map composite literal must have keys" -msgstr "" +msgstr "avbildning av sammansatta litteraler måste ha nycklar" #: go/gofrontend/expressions.cc:18651 msgid "expected struct, slice, array, or map type for composite literal" -msgstr "" +msgstr "en av typerna post, skiva, vektor eller avbildning förväntades för en sammanstatt litteral" #: go/gofrontend/expressions.cc:19266 go/gofrontend/statements.cc:2121 msgid "type assertion only valid for interface types" @@ -22699,7 +22688,7 @@ msgstr "metoden %s%s%s är märkt go:nointerface" #: rust/resolve/rust-ast-resolve-expr.cc:140 #, c-format msgid "You have broken GCC Rust. This is a feature.\n" -msgstr "" +msgstr "Du har haft sönder GCC Rust. Detta är en finess.\n" #: lto-streamer.h:1033 #, gcc-internal-format, gfc-internal-format @@ -23012,10 +23001,9 @@ msgid "Unrecognized option: %qs" msgstr "Okänd flagga: %qs" #: rust/lang.opt:90 -#, fuzzy, gcc-internal-format -#| msgid "unknown lam type %qs" +#, gcc-internal-format msgid "unknown crate type: '%qs'" -msgstr "okänd lam-typ %qs" +msgstr "okänd lårtyp (crate): ”%qs”" #: rust/lang.opt:118 #, gcc-internal-format @@ -23174,27 +23162,27 @@ msgstr "%<-msse5%> togs bort" #: config/i386/i386.opt:741 #, gcc-internal-format msgid "AVX512PF support will be removed in GCC 15" -msgstr "" +msgstr "stöd för AVX512PF kommer tas bort i GCC 15" #: config/i386/i386.opt:745 #, gcc-internal-format msgid "AVX512ER support will be removed in GCC 15" -msgstr "" +msgstr "stöd för AVX512ER kommer tas bort i GCC 15" #: config/i386/i386.opt:773 #, gcc-internal-format msgid "AVX5124FMAPS support will be removed in GCC 15" -msgstr "" +msgstr "stöd för AVX5124FMAPS kommer tas bort i GCC 15" #: config/i386/i386.opt:777 #, gcc-internal-format msgid "AVX5124VNNIW support will be removed in GCC 15" -msgstr "" +msgstr "stöd för AVX5124VNNIW kommer tas bort i GCC 15" #: config/i386/i386.opt:972 #, gcc-internal-format msgid "PREFETCHWT1 support will be removed in GCC 15" -msgstr "" +msgstr "stöd för PREFETCHWT1 kommer tas bort i GCC 15" #: config/i386/i386.opt:1286 #, gcc-internal-format @@ -23283,7 +23271,7 @@ msgstr "okänd stackåteranvändningsmodell %qs" #: common.opt:1972 #, gcc-internal-format msgid "unavailable stringop for inlining %qs" -msgstr "" +msgstr "oåtkomlig strängoperation för inlining %qs" #: common.opt:2003 #, gcc-internal-format @@ -25685,7 +25673,7 @@ msgstr "%qs är en okänd flagga till %<-save-temps%>" #: gcc.cc:5024 #, gcc-internal-format msgid "linker hardening options not enabled by %<-fhardened%> because other link options were specified on the command line" -msgstr "" +msgstr "flaggor för länkarhärdning aktiveras inte av %<-fhardened%> för att andra länkflaggor angavs på kommandoraden" #: gcc.cc:5048 toplev.cc:712 #, gcc-internal-format @@ -26236,17 +26224,17 @@ msgstr "%s stödjs inte på denna målarkitektur" #: gimple-harden-control-flow.cc:97 #, gcc-internal-format msgid "%qD calls % or similar, %<-fharden-control-flow-redundancy%> is not supported" -msgstr "" +msgstr "%qD anropar % eller liknande, %<-fharden-control-flow-redundancy%> stödjs inte" #: gimple-harden-control-flow.cc:110 #, gcc-internal-format msgid "%qD receives nonlocal gotos, %<-fharden-control-flow-redundancy%> is not supported" -msgstr "" +msgstr "%qD tar emot ickelokala goto, %<-fharden-control-flow-redundancy%> stödjs inte" #: gimple-harden-control-flow.cc:121 #, gcc-internal-format msgid "%qD has more than %u blocks, the requested maximum for %<-fharden-control-flow-redundancy%>" -msgstr "" +msgstr "%qD har fler än %u block, det begärda maximumet för %<-fharden-control-flow-redundancy%>" #: gimple-ssa-isolate-paths.cc:290 #, gcc-internal-format @@ -28579,7 +28567,7 @@ msgstr "pass %s stödjer inte kloning" #: ipa-strub.cc:654 #, gcc-internal-format msgid "%qD is not eligible for % on the target system" -msgstr "" +msgstr "%qD är inte berättigat till % på målsystemet" #: ipa-strub.cc:658 #, fuzzy, gcc-internal-format @@ -28590,7 +28578,7 @@ msgstr "ej stödd konstant adress:" #: ipa-strub.cc:684 #, gcc-internal-format msgid "%qD is not eligible for % because %<-fsplit-stack%> is enabled" -msgstr "" +msgstr "%qD är inte berättigat till % för att %<-fsplit-stack%> är aktiverat" #: ipa-strub.cc:697 #, gcc-internal-format diff --git a/gcc/po/zh_CN.po b/gcc/po/zh_CN.po index 185ead3..3f83462 100644 --- a/gcc/po/zh_CN.po +++ b/gcc/po/zh_CN.po @@ -32,10 +32,10 @@ # msgid "" msgstr "" -"Project-Id-Version: gcc 13.2.0\n" +"Project-Id-Version: gcc 14.1-b20240218\n" "Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n" "POT-Creation-Date: 2024-02-16 21:35+0000\n" -"PO-Revision-Date: 2024-02-17 18:57-0500\n" +"PO-Revision-Date: 2024-02-24 14:20-0500\n" "Last-Translator: Boyuan Yang <073plan@gmail.com>\n" "Language-Team: Chinese (simplified) \n" "Language: zh_CN\n" @@ -44,7 +44,7 @@ msgstr "" "Content-Transfer-Encoding: 8bit\n" "Plural-Forms: nplurals=1; plural=0;\n" "X-Bugs: Report translation errors to the Language-Team address.\n" -"X-Generator: Poedit 2.4.3\n" +"X-Generator: Poedit 3.4.2\n" #: cif-code.def:39 msgid "function not considered for inlining" @@ -1737,10 +1737,9 @@ msgid "Warn about C++23 constructs in code compiled with an older standard." msgstr "对使用较旧标准编译的代码给出 C++23 构造的警告。" #: c-family/c.opt:503 -#, fuzzy, no-c-format -#| msgid "Warn about C++20 constructs in code compiled with an older standard." +#, no-c-format msgid "Warn about C++26 constructs in code compiled with an older standard." -msgstr "对使用较旧标准编译的代码给出 C++20 构造的警告。" +msgstr "对使用较旧标准编译的代码给出 C++26 构造的警告。" #: c-family/c.opt:507 #, no-c-format @@ -1850,10 +1849,9 @@ msgid "Warn when all constructors and destructors are private." msgstr "当所有构造函数和析构函数都是私有时给出警告" #: c-family/c.opt:588 -#, fuzzy, no-c-format -#| msgid "Warn about implicit declarations" +#, no-c-format msgid "Warn about dangling else." -msgstr "对隐式函数声明给出警告" +msgstr "对悬空的 else 给出警告。" #: c-family/c.opt:592 c-family/c.opt:596 #, no-c-format @@ -1868,24 +1866,22 @@ msgstr "" #: c-family/c.opt:604 #, no-c-format msgid "Warn about __TIME__, __DATE__ and __TIMESTAMP__ usage." -msgstr "" +msgstr "当 __TIME__、__DATE__ 和 __TIMESTAMP__ 被使用时给出警告。" #: c-family/c.opt:608 -#, fuzzy, no-c-format -#| msgid "Warn when a declaration is found after a statement" +#, no-c-format msgid "Warn when a declaration is found after a statement." -msgstr "当声明出现在语句后时给出警告" +msgstr "当声明出现在语句后时给出警告。" #: c-family/c.opt:612 -#, fuzzy, no-c-format -#| msgid "Warn about unprototyped function declarations" +#, no-c-format msgid "Warn for missing parameter types in function declarations." -msgstr "使用了非原型的函数声明时给出警告" +msgstr "当函数生命中缺失参数类型时给出警告。" #: c-family/c.opt:616 -#, fuzzy, no-c-format +#, no-c-format msgid "Warn when deleting a pointer to incomplete type." -msgstr "提领指向不完全类型的指针" +msgstr "在删除不兼容类型的指针时给出警告。" #: c-family/c.opt:620 #, fuzzy, no-c-format @@ -2013,10 +2009,9 @@ msgid "Warn if \"defined\" is used outside #if." msgstr "当 \"defined\" 在 #if 之外使用时给出警告。" #: c-family/c.opt:727 -#, fuzzy, no-c-format -#| msgid "Warn about implicit function declarations" +#, no-c-format msgid "Warn about semicolon after in-class function definition." -msgstr "对隐式函数声明给出警告" +msgstr "" #: c-family/c.opt:731 #, no-c-format @@ -2059,10 +2054,9 @@ msgid "Warn if passing too many arguments to a function for its format string." msgstr "当传递给格式字符串的参数太多时给出警告" #: c-family/c.opt:760 -#, fuzzy, no-c-format -#| msgid "Warn about format strings that are not literals" +#, no-c-format msgid "Warn about format strings that are not literals." -msgstr "当格式字符串不是字面量时给出警告" +msgstr "当格式字符串不是字面量时给出警告。" #: c-family/c.opt:764 #, no-c-format @@ -2430,10 +2424,9 @@ msgid "Warn about potentially suboptimal choices related to OpenACC parallelism. msgstr "" #: c-family/c.opt:1101 -#, fuzzy, no-c-format -#| msgid "Warn about \"suspicious\" constructs" +#, no-c-format msgid "Warn about suspicious OpenMP code." -msgstr "对“可疑”的构造给出警告" +msgstr "对可疑的 OpenMP 代码给出警告。" #: c-family/c.opt:1105 #, no-c-format @@ -2503,10 +2496,9 @@ msgid "Warn when converting the type of pointers to member functions." msgstr "当改变成员函数指针的类型时给出警告" #: c-family/c.opt:1165 -#, fuzzy, no-c-format -#| msgid "Warn about function pointer arithmetic" +#, no-c-format msgid "Warn about function pointer arithmetic." -msgstr "当在算术表达式中使用函数指针时给出警告" +msgstr "当在算术表达式中使用函数指针时给出警告。" #: c-family/c.opt:1169 #, fuzzy, no-c-format @@ -2521,16 +2513,14 @@ msgid "Warn when a pointer is compared with a zero character constant." msgstr "使用多字节字符集的字符常量时给出警告" #: c-family/c.opt:1177 -#, fuzzy, no-c-format -#| msgid "Warn when a pointer is cast to an integer of a different size" +#, no-c-format msgid "Warn when a pointer is cast to an integer of a different size." -msgstr "将一个指针转换为大小不同的整数时给出警告" +msgstr "将一个指针转换为大小不同的整数时给出警告。" #: c-family/c.opt:1181 -#, fuzzy, no-c-format -#| msgid "Warn about misuses of pragmas" +#, no-c-format msgid "Warn about misuses of pragmas." -msgstr "对错误使用的 pragma 加以警告" +msgstr "对错误使用的 pragma 给出警告。" #: c-family/c.opt:1185 #, no-c-format @@ -2554,15 +2544,14 @@ msgid "Warn when a range-based for-loop is creating unnecessary copies." msgstr "" #: c-family/c.opt:1201 -#, fuzzy, no-c-format -#| msgid "Warn about multiple declarations of the same object" +#, no-c-format msgid "Warn about multiple declarations of the same object." -msgstr "对同一个对象多次声明时给出警告" +msgstr "对同一个对象多次声明时给出警告。" #: c-family/c.opt:1205 #, no-c-format msgid "Warn about redundant calls to std::move." -msgstr "" +msgstr "对多余的 std::move 调用给出警告。" #: c-family/c.opt:1209 #, no-c-format @@ -2852,10 +2841,9 @@ msgid "Warn about invalid forms of delimited or named escape sequences." msgstr "" #: c-family/c.opt:1449 -#, fuzzy, no-c-format -#| msgid "Warn about unrecognized pragmas" +#, no-c-format msgid "Warn about unrecognized pragmas." -msgstr "对无法识别的 pragma 加以警告" +msgstr "对无法识别的 pragma 加以警告。" #: c-family/c.opt:1453 #, fuzzy, no-c-format @@ -3231,10 +3219,9 @@ msgid "Use traditional GNU semantics for inline functions." msgstr "为内联函数使用传统的 GNU 语义。" #: c-family/c.opt:1907 -#, fuzzy, no-c-format -#| msgid "Assume normal C execution environment" +#, no-c-format msgid "Assume normal C execution environment." -msgstr "假定一般的 C 执行环境" +msgstr "假定一般的 C 执行环境。" #: c-family/c.opt:1915 #, no-c-format @@ -3803,10 +3790,9 @@ msgid "Conform to the ISO 2023 C++ draft standard (experimental and incomplete s msgstr "遵循 ISO 2023 C++ 标准草案（试验性质的不完全支持）。" #: c-family/c.opt:2480 c-family/c.opt:2484 -#, fuzzy, no-c-format -#| msgid "Conform to the ISO 2023 C++ draft standard (experimental and incomplete support)." +#, no-c-format msgid "Conform to the ISO 2026 C++ draft standard (experimental and incomplete support)." -msgstr "遵循 ISO 2023 C++ 标准草案（试验性质的不完全支持）。" +msgstr "遵循 ISO 2026 C++ 标准草案（试验性质的不完全支持）。" #: c-family/c.opt:2488 c-family/c.opt:2642 #, no-c-format @@ -3825,16 +3811,14 @@ msgid "Conform to the ISO 2017 C standard (published in 2018)." msgstr "遵循 ISO 2017 C 标准（于2018年发布）。" #: c-family/c.opt:2504 c-family/c.opt:2654 -#, fuzzy, no-c-format -#| msgid "Conform to the ISO 202X C standard draft (experimental and incomplete support)." +#, no-c-format msgid "Conform to the ISO 2023 C standard draft (expected to be published in 2024) (experimental and incomplete support)." -msgstr "遵循 ISO 202X C++ 标准草案（试验性质的不完全支持）。" +msgstr "遵循 ISO 2023 C++ 标准草案（预计于2024年发布）（试验性质的不完全支持）。" #: c-family/c.opt:2508 -#, fuzzy, no-c-format -#| msgid "Deprecated in favor of -std=c11." +#, no-c-format msgid "Deprecated in favor of -std=c23." -msgstr "已弃用，请改用 -std=c11。" +msgstr "已弃用，请改用 -std=c23。" #: c-family/c.opt:2512 c-family/c.opt:2516 c-family/c.opt:2626 #, no-c-format @@ -3887,10 +3871,9 @@ msgid "Conform to the ISO 2017 C++ standard with GNU extensions." msgstr "遵循 ISO 2017 C++ 标准，也支持 GNU 扩展。" #: c-family/c.opt:2562 c-family/c.opt:2566 -#, fuzzy, no-c-format -#| msgid "Conform to the ISO 201z(7?) C++ draft standard with GNU extensions (experimental and incomplete support)" +#, no-c-format msgid "Conform to the ISO 2020 C++ standard with GNU extensions (experimental and incomplete support)." -msgstr "遵循 ISO 201z(7?) C++ 标准草案和 GNU 扩展(试验性质的不完全支持)" +msgstr "遵循 ISO 2020 C++ 标准和 GNU 扩展（试验性质的不完全支持）" #: c-family/c.opt:2570 c-family/c.opt:2574 #, fuzzy, no-c-format @@ -3915,10 +3898,9 @@ msgid "Deprecated in favor of -std=gnu11." msgstr "已弃用，请改用 -std=gnu11。" #: c-family/c.opt:2594 c-family/c.opt:2598 -#, fuzzy, no-c-format -#| msgid "Conform to the ISO 1990 C standard with GNU extensions" +#, no-c-format msgid "Conform to the ISO 2017 C standard (published in 2018) with GNU extensions." -msgstr "遵循 ISO 1990 C 标准，也支持 GNU 扩展" +msgstr "遵循 ISO 2017 C 标准（发布于2018年），也支持 GNU 扩展" #: c-family/c.opt:2602 #, fuzzy, no-c-format @@ -3927,10 +3909,9 @@ msgid "Conform to the ISO 2023 C standard draft (expected to be published in 202 msgstr "遵循 ISO 201z(7?) C++ 标准草案和 GNU 扩展(试验性质的不完全支持)" #: c-family/c.opt:2606 -#, fuzzy, no-c-format -#| msgid "Deprecated in favor of -std=gnu11." +#, no-c-format msgid "Deprecated in favor of -std=gnu23." -msgstr "已弃用，请改用 -std=gnu11。" +msgstr "已弃用，请改用 -std=gnu23。" #: c-family/c.opt:2610 c-family/c.opt:2614 #, no-c-format @@ -4112,13 +4093,12 @@ msgstr "生成文档。" #: d/lang.opt:268 #, no-c-format msgid "-fdoc-dir=\tWrite documentation file to directory ." -msgstr "" +msgstr "-fdoc-dir=\t将文档写入指定目录 中。" #: d/lang.opt:272 -#, fuzzy, no-c-format -#| msgid "-o \tPlace output into " +#, no-c-format msgid "-fdoc-file=\tWrite documentation to ." -msgstr "-o <文件>\t将输出写入文件" +msgstr "-o <文件>\t将文档写入指定 <文件>。" #: d/lang.opt:276 #, no-c-format @@ -5432,16 +5412,14 @@ msgid "Do not generate a single exit point for each function." msgstr "不为每个函数生成单一的退出点" #: config/mmix/mmix.opt:95 -#, fuzzy, no-c-format -#| msgid "Set start-address of the program" +#, no-c-format msgid "Set start-address of the program." -msgstr "设定程序的起始地址" +msgstr "设定程序的起始地址。" #: config/mmix/mmix.opt:99 -#, fuzzy, no-c-format -#| msgid "Set start-address of data" +#, no-c-format msgid "Set start-address of data." -msgstr "设定数据的起始地址" +msgstr "设定数据的起始地址。" #: config/darwin.opt:34 #, fuzzy, no-c-format @@ -5491,10 +5469,9 @@ msgid "Generate code for the kernel or loadable kernel extensions." msgstr "为内核或可加载内核扩展生成代码" #: config/darwin.opt:75 -#, fuzzy, no-c-format -#| msgid "The earliest MacOS X version on which this program will run" +#, no-c-format msgid "The earliest macOS version on which this program will run." -msgstr "这个程序可能在其上运行的最早的 MacOS X 版本" +msgstr "这个程序可能在其上运行的最早的 macOS 版本。" #: config/darwin.opt:80 #, no-c-format @@ -5638,12 +5615,12 @@ msgstr "" #: config/darwin.opt:198 #, no-c-format msgid "Abbreviation for \"-g -fno-eliminate-unused-debug-symbols\"." -msgstr "" +msgstr "\"-g -fno-eliminate-unused-debug-symbols\" 的缩写。" #: config/darwin.opt:202 #, no-c-format msgid "Abbreviation for \"-g -feliminate-unused-debug-symbols\"." -msgstr "" +msgstr "\"-g -feliminate-unused-debug-symbols\" 的缩写。" #: config/darwin.opt:206 #, no-c-format @@ -5876,16 +5853,14 @@ msgid "(Obsolete and unhandled by ld64, ignored)\tld should produce an executabl msgstr "" #: config/bfin/bfin.opt:40 config/msp430/msp430.opt:3 config/c6x/c6x.opt:38 -#, fuzzy, no-c-format -#| msgid "Use simulator runtime" +#, no-c-format msgid "Use simulator runtime." -msgstr "使用仿真器运行时" +msgstr "使用仿真器运行时。" #: config/bfin/bfin.opt:44 config/arm/arm.opt:120 -#, fuzzy, no-c-format -#| msgid "Specify the name of the target CPU" +#, no-c-format msgid "Specify the name of the target CPU." -msgstr "指定目标 CPU 的名称" +msgstr "指定目标 CPU 的名称。" #: config/bfin/bfin.opt:48 #, fuzzy, no-c-format @@ -5894,10 +5869,9 @@ msgid "Omit frame pointer for leaf functions." msgstr "为叶函数(不调用其他函数的函数)忽略框架指针" #: config/bfin/bfin.opt:52 -#, fuzzy, no-c-format -#| msgid "Program is entirely located in low 64k of memory" +#, no-c-format msgid "Program is entirely located in low 64k of memory." -msgstr "程序完全位于内存的低 64K" +msgstr "程序完全位于内存的低 64K。" #: config/bfin/bfin.opt:56 #, fuzzy, no-c-format @@ -6007,10 +5981,9 @@ msgid "Known M68K ISAs (for use with the -march= option):" msgstr "已知 M68K ISA (用于 -march= 选项)：" #: config/m68k/ieee.opt:24 config/i386/i386.opt:389 -#, fuzzy, no-c-format -#| msgid "Use IEEE math for fp comparisons" +#, no-c-format msgid "Use IEEE math for fp comparisons." -msgstr "浮点数间的比较严格遵循 IEEE 标准" +msgstr "浮点数间的比较严格遵循 IEEE 标准。" #: config/m68k/m68k.opt:30 #, no-c-format @@ -6488,10 +6461,9 @@ msgid "Specify stringop expansion strategy." msgstr "" #: config/m32c/m32c.opt:23 -#, fuzzy, no-c-format -#| msgid "-msim\tUse simulator runtime" +#, no-c-format msgid "-msim\tUse simulator runtime." -msgstr "-msim\t使用仿真器运行时" +msgstr "-msim\t使用仿真器运行时。" #: config/m32c/m32c.opt:27 #, fuzzy, no-c-format @@ -6963,16 +6935,14 @@ msgid "Do not inline integer division." msgstr "不内联整数除法。" #: config/ia64/ia64.opt:94 -#, fuzzy, no-c-format -#| msgid "Generate inline square root, optimize for latency" +#, no-c-format msgid "Generate inline square root, optimize for latency." -msgstr "生成内联的平方根，为最小延迟优化" +msgstr "生成内联的平方根，为最小延迟优化。" #: config/ia64/ia64.opt:98 -#, fuzzy, no-c-format -#| msgid "Generate inline square root, optimize for throughput" +#, no-c-format msgid "Generate inline square root, optimize for throughput." -msgstr "生成内联的平方根，为最大吞吐量优化" +msgstr "生成内联的平方根，为最大吞吐量优化。" #: config/ia64/ia64.opt:102 #, no-c-format @@ -7221,10 +7191,9 @@ msgid "Target the FT32B architecture." msgstr "目标为 AM33 处理器" #: config/ft32/ft32.opt:39 -#, fuzzy, no-c-format -#| msgid "Enable MeP Coprocessor" +#, no-c-format msgid "Enable FT32B code compression." -msgstr "启用 MeP 协处理器" +msgstr "启用 FT32B 代码压缩。" #: config/ft32/ft32.opt:43 #, no-c-format @@ -7454,40 +7423,34 @@ msgid "Use windowed registers ABI." msgstr "使用浮点寄存器" #: config/i386/cygming.opt:23 -#, fuzzy, no-c-format -#| msgid "Create console application" +#, no-c-format msgid "Create console application." -msgstr "创建命令行程序" +msgstr "创建控制台程序。" #: config/i386/cygming.opt:27 -#, fuzzy, no-c-format -#| msgid "Generate code for a DLL" +#, no-c-format msgid "Generate code for a DLL." -msgstr "生成动态链接库的代码" +msgstr "生成动态链接库的代码。" #: config/i386/cygming.opt:31 -#, fuzzy, no-c-format -#| msgid "Ignore dllimport for functions" +#, no-c-format msgid "Ignore dllimport for functions." -msgstr "忽略函数的 dllimport 属性" +msgstr "忽略函数的 dllimport 属性。" #: config/i386/cygming.opt:35 -#, fuzzy, no-c-format -#| msgid "Use Mingw-specific thread support" +#, no-c-format msgid "Use Mingw-specific thread support." -msgstr "使用 Mingw 特定的线程支持" +msgstr "使用 Mingw 特定的线程支持。" #: config/i386/cygming.opt:39 -#, fuzzy, no-c-format -#| msgid "Set Windows defines" +#, no-c-format msgid "Set Windows defines." -msgstr "设定 Windows 定义" +msgstr "设定 Windows 定义。" #: config/i386/cygming.opt:43 -#, fuzzy, no-c-format -#| msgid "Create GUI application" +#, no-c-format msgid "Create GUI application." -msgstr "创建图形界面程序" +msgstr "创建图形界面应用程序。" #: config/i386/cygming.opt:47 #, fuzzy, no-c-format @@ -7602,10 +7565,9 @@ msgid "Generate code for given CPU." msgstr "为给定的 CPU 生成代码。" #: config/i386/i386.opt:282 config/bpf/bpf.opt:98 -#, fuzzy, no-c-format -#| msgid "Use given assembler dialect" +#, no-c-format msgid "Use given assembler dialect." -msgstr "使用给定的汇编风格" +msgstr "使用给定的汇编风格。" #: config/i386/i386.opt:286 #, fuzzy, no-c-format @@ -7626,15 +7588,14 @@ msgid "-mlarge-data-threshold=\tData greater than given threshold will g msgstr "在 x86-64 中等模式下大于指定阈值的数据将被存放在 .ldata 节中" #: config/i386/i386.opt:304 -#, fuzzy, no-c-format -#| msgid "Use given x86-64 code model" +#, no-c-format msgid "Use given x86-64 code model." -msgstr "使用给定的 x86-64 代码模式" +msgstr "使用给定的 x86-64 代码模式。" #: config/i386/i386.opt:327 -#, fuzzy, no-c-format +#, no-c-format msgid "Use given address mode." -msgstr "使用 UTF-8 模式" +msgstr "使用给定的地址模式。" #: config/i386/i386.opt:331 #, no-c-format @@ -7642,10 +7603,9 @@ msgid "Known address mode (for use with the -maddress-mode= option):" msgstr "已知寻址模式 (用于 -mcmodel= 选项)：" #: config/i386/i386.opt:344 -#, fuzzy, no-c-format -#| msgid "Generate sin, cos, sqrt for FPU" +#, no-c-format msgid "Generate sin, cos, sqrt for FPU." -msgstr "为 FPU 生成 sin、cos 和 sqrt 指令" +msgstr "为 FPU 生成 sin、cos 和 sqrt 指令。" #: config/i386/i386.opt:348 #, fuzzy, no-c-format -- cgit v1.1 From 77576915cfd26e603aba5295dfdac54a5545f5f2 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 26 Feb 2024 16:30:16 +0100 Subject: c: Improve some diagnostics for __builtin_stdc_bit_* [PR114042] The PR complains that for the __builtin_stdc_bit_* "builtins" the diagnostics doesn't mention the name of the builtin the user used, but instead __builtin_{clz,ctz,popcount}g instead (which is what the FE immediately lowers it to). The following patch repeats the checks from check_builtin_function_arguments which are there done on BUILT_IN_{CLZ,CTZ,POPCOUNT}G, such that they diagnose it with the name of the "builtin" user actually used before it is gone. 2024-02-26 Jakub Jelinek PR c/114042 * c-parser.cc (c_parser_postfix_expression): Diagnose __builtin_stdc_bit_* argument with ENUMERAL_TYPE or BOOLEAN_TYPE type or if signed here rather than on the replacement builtins in check_builtin_function_arguments. * gcc.dg/builtin-stdc-bit-2.c: Adjust testcase for actual builtin names rather than names of builtin replacements. --- gcc/c/c-parser.cc | 21 ++++++++ gcc/testsuite/gcc.dg/builtin-stdc-bit-2.c | 84 +++++++++++++++---------------- 2 files changed, 63 insertions(+), 42 deletions(-) (limited to 'gcc') diff --git a/gcc/c/c-parser.cc b/gcc/c/c-parser.cc index 8019e60..53e99aa 100644 --- a/gcc/c/c-parser.cc +++ b/gcc/c/c-parser.cc @@ -11859,6 +11859,27 @@ c_parser_postfix_expression (c_parser *parser) expr.set_error (); break; } + if (TREE_CODE (TREE_TYPE (arg_p->value)) == ENUMERAL_TYPE) + { + error_at (loc, "argument %u in call to function " + "%qs has enumerated type", 1, name); + expr.set_error (); + break; + } + if (TREE_CODE (TREE_TYPE (arg_p->value)) == BOOLEAN_TYPE) + { + error_at (loc, "argument %u in call to function " + "%qs has boolean type", 1, name); + expr.set_error (); + break; + } + if (!TYPE_UNSIGNED (TREE_TYPE (arg_p->value))) + { + error_at (loc, "argument 1 in call to function " + "%qs has signed type", name); + expr.set_error (); + break; + } tree arg = arg_p->value; tree type = TYPE_MAIN_VARIANT (TREE_TYPE (arg)); /* Expand: diff --git a/gcc/testsuite/gcc.dg/builtin-stdc-bit-2.c b/gcc/testsuite/gcc.dg/builtin-stdc-bit-2.c index 1997753..c7430c5 100644 --- a/gcc/testsuite/gcc.dg/builtin-stdc-bit-2.c +++ b/gcc/testsuite/gcc.dg/builtin-stdc-bit-2.c @@ -14,9 +14,9 @@ foo (void) __builtin_stdc_leading_zeros ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_leading_zeros' operand not an integral type" } */ __builtin_stdc_leading_zeros (); /* { dg-error "wrong number of arguments to '__builtin_stdc_leading_zeros'" } */ __builtin_stdc_leading_zeros (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_leading_zeros'" } */ - __builtin_stdc_leading_zeros ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has boolean type" } */ - __builtin_stdc_leading_zeros ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has enumerated type" } */ - __builtin_stdc_leading_zeros (0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has signed type" } */ + __builtin_stdc_leading_zeros ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_leading_zeros' has boolean type" } */ + __builtin_stdc_leading_zeros ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_leading_zeros' has enumerated type" } */ + __builtin_stdc_leading_zeros (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_leading_zeros' has signed type" } */ __builtin_stdc_leading_ones (0.0f); /* { dg-error "'__builtin_stdc_leading_ones' operand not an integral type" } */ __builtin_stdc_leading_ones (0.0); /* { dg-error "'__builtin_stdc_leading_ones' operand not an integral type" } */ __builtin_stdc_leading_ones (0.0L); /* { dg-error "'__builtin_stdc_leading_ones' operand not an integral type" } */ @@ -24,9 +24,9 @@ foo (void) __builtin_stdc_leading_ones ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_leading_ones' operand not an integral type" } */ __builtin_stdc_leading_ones (); /* { dg-error "wrong number of arguments to '__builtin_stdc_leading_ones'" } */ __builtin_stdc_leading_ones (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_leading_ones'" } */ - __builtin_stdc_leading_ones ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has boolean type" } */ - __builtin_stdc_leading_ones ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has enumerated type" } */ - __builtin_stdc_leading_ones (0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has signed type" } */ + __builtin_stdc_leading_ones ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_leading_ones' has boolean type" } */ + __builtin_stdc_leading_ones ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_leading_ones' has enumerated type" } */ + __builtin_stdc_leading_ones (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_leading_ones' has signed type" } */ __builtin_stdc_trailing_zeros (0.0f); /* { dg-error "'__builtin_stdc_trailing_zeros' operand not an integral type" } */ __builtin_stdc_trailing_zeros (0.0); /* { dg-error "'__builtin_stdc_trailing_zeros' operand not an integral type" } */ __builtin_stdc_trailing_zeros (0.0L); /* { dg-error "'__builtin_stdc_trailing_zeros' operand not an integral type" } */ @@ -34,9 +34,9 @@ foo (void) __builtin_stdc_trailing_zeros ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_trailing_zeros' operand not an integral type" } */ __builtin_stdc_trailing_zeros (); /* { dg-error "wrong number of arguments to '__builtin_stdc_trailing_zeros'" } */ __builtin_stdc_trailing_zeros (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_trailing_zeros'" } */ - __builtin_stdc_trailing_zeros ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has boolean type" } */ - __builtin_stdc_trailing_zeros ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has enumerated type" } */ - __builtin_stdc_trailing_zeros (0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has signed type" } */ + __builtin_stdc_trailing_zeros ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_trailing_zeros' has boolean type" } */ + __builtin_stdc_trailing_zeros ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_trailing_zeros' has enumerated type" } */ + __builtin_stdc_trailing_zeros (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_trailing_zeros' has signed type" } */ __builtin_stdc_trailing_ones (0.0f); /* { dg-error "'__builtin_stdc_trailing_ones' operand not an integral type" } */ __builtin_stdc_trailing_ones (0.0); /* { dg-error "'__builtin_stdc_trailing_ones' operand not an integral type" } */ __builtin_stdc_trailing_ones (0.0L); /* { dg-error "'__builtin_stdc_trailing_ones' operand not an integral type" } */ @@ -44,9 +44,9 @@ foo (void) __builtin_stdc_trailing_ones ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_trailing_ones' operand not an integral type" } */ __builtin_stdc_trailing_ones (); /* { dg-error "wrong number of arguments to '__builtin_stdc_trailing_ones'" } */ __builtin_stdc_trailing_ones (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_trailing_ones'" } */ - __builtin_stdc_trailing_ones ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has boolean type" } */ - __builtin_stdc_trailing_ones ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has enumerated type" } */ - __builtin_stdc_trailing_ones (0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has signed type" } */ + __builtin_stdc_trailing_ones ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_trailing_ones' has boolean type" } */ + __builtin_stdc_trailing_ones ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_trailing_ones' has enumerated type" } */ + __builtin_stdc_trailing_ones (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_trailing_ones' has signed type" } */ __builtin_stdc_first_leading_zero (0.0f); /* { dg-error "'__builtin_stdc_first_leading_zero' operand not an integral type" } */ __builtin_stdc_first_leading_zero (0.0); /* { dg-error "'__builtin_stdc_first_leading_zero' operand not an integral type" } */ __builtin_stdc_first_leading_zero (0.0L); /* { dg-error "'__builtin_stdc_first_leading_zero' operand not an integral type" } */ @@ -54,9 +54,9 @@ foo (void) __builtin_stdc_first_leading_zero ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_first_leading_zero' operand not an integral type" } */ __builtin_stdc_first_leading_zero (); /* { dg-error "wrong number of arguments to '__builtin_stdc_first_leading_zero'" } */ __builtin_stdc_first_leading_zero (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_first_leading_zero'" } */ - __builtin_stdc_first_leading_zero ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has boolean type" } */ - __builtin_stdc_first_leading_zero ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has enumerated type" } */ - __builtin_stdc_first_leading_zero (0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has signed type" } */ + __builtin_stdc_first_leading_zero ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_leading_zero' has boolean type" } */ + __builtin_stdc_first_leading_zero ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_leading_zero' has enumerated type" } */ + __builtin_stdc_first_leading_zero (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_leading_zero' has signed type" } */ __builtin_stdc_first_leading_one (0.0f); /* { dg-error "'__builtin_stdc_first_leading_one' operand not an integral type" } */ __builtin_stdc_first_leading_one (0.0); /* { dg-error "'__builtin_stdc_first_leading_one' operand not an integral type" } */ __builtin_stdc_first_leading_one (0.0L); /* { dg-error "'__builtin_stdc_first_leading_one' operand not an integral type" } */ @@ -64,9 +64,9 @@ foo (void) __builtin_stdc_first_leading_one ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_first_leading_one' operand not an integral type" } */ __builtin_stdc_first_leading_one (); /* { dg-error "wrong number of arguments to '__builtin_stdc_first_leading_one'" } */ __builtin_stdc_first_leading_one (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_first_leading_one'" } */ - __builtin_stdc_first_leading_one ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has boolean type" } */ - __builtin_stdc_first_leading_one ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has enumerated type" } */ - __builtin_stdc_first_leading_one (0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has signed type" } */ + __builtin_stdc_first_leading_one ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_leading_one' has boolean type" } */ + __builtin_stdc_first_leading_one ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_leading_one' has enumerated type" } */ + __builtin_stdc_first_leading_one (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_leading_one' has signed type" } */ __builtin_stdc_first_trailing_zero (0.0f); /* { dg-error "'__builtin_stdc_first_trailing_zero' operand not an integral type" } */ __builtin_stdc_first_trailing_zero (0.0); /* { dg-error "'__builtin_stdc_first_trailing_zero' operand not an integral type" } */ __builtin_stdc_first_trailing_zero (0.0L); /* { dg-error "'__builtin_stdc_first_trailing_zero' operand not an integral type" } */ @@ -74,9 +74,9 @@ foo (void) __builtin_stdc_first_trailing_zero ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_first_trailing_zero' operand not an integral type" } */ __builtin_stdc_first_trailing_zero (); /* { dg-error "wrong number of arguments to '__builtin_stdc_first_trailing_zero'" } */ __builtin_stdc_first_trailing_zero (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_first_trailing_zero'" } */ - __builtin_stdc_first_trailing_zero ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has boolean type" } */ - __builtin_stdc_first_trailing_zero ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has enumerated type" } */ - __builtin_stdc_first_trailing_zero (0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has signed type" } */ + __builtin_stdc_first_trailing_zero ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_trailing_zero' has boolean type" } */ + __builtin_stdc_first_trailing_zero ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_trailing_zero' has enumerated type" } */ + __builtin_stdc_first_trailing_zero (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_trailing_zero' has signed type" } */ __builtin_stdc_first_trailing_one (0.0f); /* { dg-error "'__builtin_stdc_first_trailing_one' operand not an integral type" } */ __builtin_stdc_first_trailing_one (0.0); /* { dg-error "'__builtin_stdc_first_trailing_one' operand not an integral type" } */ __builtin_stdc_first_trailing_one (0.0L); /* { dg-error "'__builtin_stdc_first_trailing_one' operand not an integral type" } */ @@ -84,9 +84,9 @@ foo (void) __builtin_stdc_first_trailing_one ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_first_trailing_one' operand not an integral type" } */ __builtin_stdc_first_trailing_one (); /* { dg-error "wrong number of arguments to '__builtin_stdc_first_trailing_one'" } */ __builtin_stdc_first_trailing_one (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_first_trailing_one'" } */ - __builtin_stdc_first_trailing_one ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has boolean type" } */ - __builtin_stdc_first_trailing_one ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has enumerated type" } */ - __builtin_stdc_first_trailing_one (0); /* { dg-error "argument 1 in call to function '__builtin_ctzg' has signed type" } */ + __builtin_stdc_first_trailing_one ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_trailing_one' has boolean type" } */ + __builtin_stdc_first_trailing_one ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_trailing_one' has enumerated type" } */ + __builtin_stdc_first_trailing_one (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_first_trailing_one' has signed type" } */ __builtin_stdc_count_zeros (0.0f); /* { dg-error "'__builtin_stdc_count_zeros' operand not an integral type" } */ __builtin_stdc_count_zeros (0.0); /* { dg-error "'__builtin_stdc_count_zeros' operand not an integral type" } */ __builtin_stdc_count_zeros (0.0L); /* { dg-error "'__builtin_stdc_count_zeros' operand not an integral type" } */ @@ -94,9 +94,9 @@ foo (void) __builtin_stdc_count_zeros ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_count_zeros' operand not an integral type" } */ __builtin_stdc_count_zeros (); /* { dg-error "wrong number of arguments to '__builtin_stdc_count_zeros'" } */ __builtin_stdc_count_zeros (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_count_zeros'" } */ - __builtin_stdc_count_zeros ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_popcountg' has boolean type" } */ - __builtin_stdc_count_zeros ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_popcountg' has enumerated type" } */ - __builtin_stdc_count_zeros (0); /* { dg-error "argument 1 in call to function '__builtin_popcountg' has signed type" } */ + __builtin_stdc_count_zeros ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_count_zeros' has boolean type" } */ + __builtin_stdc_count_zeros ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_count_zeros' has enumerated type" } */ + __builtin_stdc_count_zeros (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_count_zeros' has signed type" } */ __builtin_stdc_count_ones (0.0f); /* { dg-error "'__builtin_stdc_count_ones' operand not an integral type" } */ __builtin_stdc_count_ones (0.0); /* { dg-error "'__builtin_stdc_count_ones' operand not an integral type" } */ __builtin_stdc_count_ones (0.0L); /* { dg-error "'__builtin_stdc_count_ones' operand not an integral type" } */ @@ -104,9 +104,9 @@ foo (void) __builtin_stdc_count_ones ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_count_ones' operand not an integral type" } */ __builtin_stdc_count_ones (); /* { dg-error "wrong number of arguments to '__builtin_stdc_count_ones'" } */ __builtin_stdc_count_ones (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_count_ones'" } */ - __builtin_stdc_count_ones ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_popcountg' has boolean type" } */ - __builtin_stdc_count_ones ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_popcountg' has enumerated type" } */ - __builtin_stdc_count_ones (0); /* { dg-error "argument 1 in call to function '__builtin_popcountg' has signed type" } */ + __builtin_stdc_count_ones ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_count_ones' has boolean type" } */ + __builtin_stdc_count_ones ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_count_ones' has enumerated type" } */ + __builtin_stdc_count_ones (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_count_ones' has signed type" } */ __builtin_stdc_has_single_bit (0.0f); /* { dg-error "'__builtin_stdc_has_single_bit' operand not an integral type" } */ __builtin_stdc_has_single_bit (0.0); /* { dg-error "'__builtin_stdc_has_single_bit' operand not an integral type" } */ __builtin_stdc_has_single_bit (0.0L); /* { dg-error "'__builtin_stdc_has_single_bit' operand not an integral type" } */ @@ -114,9 +114,9 @@ foo (void) __builtin_stdc_has_single_bit ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_has_single_bit' operand not an integral type" } */ __builtin_stdc_has_single_bit (); /* { dg-error "wrong number of arguments to '__builtin_stdc_has_single_bit'" } */ __builtin_stdc_has_single_bit (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_has_single_bit'" } */ - __builtin_stdc_has_single_bit ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_popcountg' has boolean type" } */ - __builtin_stdc_has_single_bit ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_popcountg' has enumerated type" } */ - __builtin_stdc_has_single_bit (0); /* { dg-error "argument 1 in call to function '__builtin_popcountg' has signed type" } */ + __builtin_stdc_has_single_bit ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_has_single_bit' has boolean type" } */ + __builtin_stdc_has_single_bit ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_has_single_bit' has enumerated type" } */ + __builtin_stdc_has_single_bit (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_has_single_bit' has signed type" } */ __builtin_stdc_bit_width (0.0f); /* { dg-error "'__builtin_stdc_bit_width' operand not an integral type" } */ __builtin_stdc_bit_width (0.0); /* { dg-error "'__builtin_stdc_bit_width' operand not an integral type" } */ __builtin_stdc_bit_width (0.0L); /* { dg-error "'__builtin_stdc_bit_width' operand not an integral type" } */ @@ -124,9 +124,9 @@ foo (void) __builtin_stdc_bit_width ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_bit_width' operand not an integral type" } */ __builtin_stdc_bit_width (); /* { dg-error "wrong number of arguments to '__builtin_stdc_bit_width'" } */ __builtin_stdc_bit_width (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_bit_width'" } */ - __builtin_stdc_bit_width ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has boolean type" } */ - __builtin_stdc_bit_width ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has enumerated type" } */ - __builtin_stdc_bit_width (0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has signed type" } */ + __builtin_stdc_bit_width ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_bit_width' has boolean type" } */ + __builtin_stdc_bit_width ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_bit_width' has enumerated type" } */ + __builtin_stdc_bit_width (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_bit_width' has signed type" } */ __builtin_stdc_bit_floor (0.0f); /* { dg-error "'__builtin_stdc_bit_floor' operand not an integral type" } */ __builtin_stdc_bit_floor (0.0); /* { dg-error "'__builtin_stdc_bit_floor' operand not an integral type" } */ __builtin_stdc_bit_floor (0.0L); /* { dg-error "'__builtin_stdc_bit_floor' operand not an integral type" } */ @@ -134,9 +134,9 @@ foo (void) __builtin_stdc_bit_floor ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_bit_floor' operand not an integral type" } */ __builtin_stdc_bit_floor (); /* { dg-error "wrong number of arguments to '__builtin_stdc_bit_floor'" } */ __builtin_stdc_bit_floor (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_bit_floor'" } */ - __builtin_stdc_bit_floor ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has boolean type" } */ - __builtin_stdc_bit_floor ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has enumerated type" } */ - __builtin_stdc_bit_floor (0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has signed type" } */ + __builtin_stdc_bit_floor ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_bit_floor' has boolean type" } */ + __builtin_stdc_bit_floor ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_bit_floor' has enumerated type" } */ + __builtin_stdc_bit_floor (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_bit_floor' has signed type" } */ __builtin_stdc_bit_ceil (0.0f); /* { dg-error "'__builtin_stdc_bit_ceil' operand not an integral type" } */ __builtin_stdc_bit_ceil (0.0); /* { dg-error "'__builtin_stdc_bit_ceil' operand not an integral type" } */ __builtin_stdc_bit_ceil (0.0L); /* { dg-error "'__builtin_stdc_bit_ceil' operand not an integral type" } */ @@ -144,7 +144,7 @@ foo (void) __builtin_stdc_bit_ceil ((struct S) { 0 }); /* { dg-error "'__builtin_stdc_bit_ceil' operand not an integral type" } */ __builtin_stdc_bit_ceil (); /* { dg-error "wrong number of arguments to '__builtin_stdc_bit_ceil'" } */ __builtin_stdc_bit_ceil (0U, 0U); /* { dg-error "wrong number of arguments to '__builtin_stdc_bit_ceil'" } */ - __builtin_stdc_bit_ceil ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has boolean type" } */ - __builtin_stdc_bit_ceil ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has enumerated type" } */ - __builtin_stdc_bit_ceil (0); /* { dg-error "argument 1 in call to function '__builtin_clzg' has signed type" } */ + __builtin_stdc_bit_ceil ((_Bool) 0); /* { dg-error "argument 1 in call to function '__builtin_stdc_bit_ceil' has boolean type" } */ + __builtin_stdc_bit_ceil ((enum E) E0); /* { dg-error "argument 1 in call to function '__builtin_stdc_bit_ceil' has enumerated type" } */ + __builtin_stdc_bit_ceil (0); /* { dg-error "argument 1 in call to function '__builtin_stdc_bit_ceil' has signed type" } */ } -- cgit v1.1 From 1931c40364bb9fb0a7c4b650917e3ac0e88bf6f4 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 26 Feb 2024 17:55:07 +0100 Subject: varasm: Handle private COMDAT function symbol reference in readonly data section [PR113617] If default_elf_select_rtx_section is called to put a reference to some local symbol defined in a comdat section into memory, which happens more often since the r14-4944 RA change, linking might fail. default_elf_select_rtx_section puts such constants into .data.rel.ro.local etc. sections and if linker chooses comdat sections from some other TU and discards the one to which a relocation in .data.rel.ro.local remains, linker diagnoses error. References to private comdat symbols can only appear from functions or data objects in the same comdat group, so the following patch arranges using .data.rel.ro.local.pool. and similar sections. 2024-02-26 Jakub Jelinek H.J. Lu PR rtl-optimization/113617 * varasm.cc (default_elf_select_rtx_section): For references to private symbols in comdat sections use .data.relro.local.pool., .data.relro.pool. or .rodata. comdat sections. * g++.dg/other/pr113617.C: New test. * g++.dg/other/pr113617.h: New test. * g++.dg/other/pr113617-aux.cc: New test. --- gcc/testsuite/g++.dg/other/pr113617-aux.cc | 9 ++ gcc/testsuite/g++.dg/other/pr113617.C | 27 ++++++ gcc/testsuite/g++.dg/other/pr113617.h | 132 +++++++++++++++++++++++++++++ gcc/varasm.cc | 48 ++++++++++- 4 files changed, 215 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/other/pr113617-aux.cc create mode 100644 gcc/testsuite/g++.dg/other/pr113617.C create mode 100644 gcc/testsuite/g++.dg/other/pr113617.h (limited to 'gcc') diff --git a/gcc/testsuite/g++.dg/other/pr113617-aux.cc b/gcc/testsuite/g++.dg/other/pr113617-aux.cc new file mode 100644 index 0000000..e6900e0 --- /dev/null +++ b/gcc/testsuite/g++.dg/other/pr113617-aux.cc @@ -0,0 +1,9 @@ +// PR rtl-optimization/113617 +// { dg-do link { target { c++17 && c++14_down } } } + +#include "pr113617.h" + +void qux() { + A a; + a.foo(0, 0); +} diff --git a/gcc/testsuite/g++.dg/other/pr113617.C b/gcc/testsuite/g++.dg/other/pr113617.C new file mode 100644 index 0000000..a02dda1 --- /dev/null +++ b/gcc/testsuite/g++.dg/other/pr113617.C @@ -0,0 +1,27 @@ +// PR rtl-optimization/113617 +// { dg-do link { target c++11 } } +// { dg-options "-O2" } +// { dg-additional-options "-fPIC" { target fpic } } */ +// { dg-additional-options "-shared" { target shared } } */ +// { dg-additional-sources pr113617-aux.cc } + +#include "pr113617.h" + +int z; +long xx1; +void corge() { + A a; + a.foo(xx1, 0); +} + +typedef unsigned long int VV __attribute__((vector_size (2 * sizeof (long)))); +VV vv; +__attribute__((noipa)) static void fn1 (void) {} +__attribute__((noipa)) static void fn2 (void) {} + +void +fn3 () +{ + VV a = { (unsigned long) &fn1, (unsigned long) &fn2 }; + vv = a; +} diff --git a/gcc/testsuite/g++.dg/other/pr113617.h b/gcc/testsuite/g++.dg/other/pr113617.h new file mode 100644 index 0000000..4d30edd --- /dev/null +++ b/gcc/testsuite/g++.dg/other/pr113617.h @@ -0,0 +1,132 @@ +namespace { +template struct J { static constexpr int value = V; }; +template using K = J; +using M = K; +template struct L { template using type = _Tp; }; +template using N = typename L<_Cond>::type<_If, _Else>; +M k; +template struct O { using type = _Tp; }; +template +struct P : N, _Up> {}; +template struct Q { using type = typename P<_Tp>::type; }; +} +namespace R { +struct H; +enum G {}; +template class S; +struct T { using U = bool (*) (H &, const H &, G); U F; }; +template class B; +template +struct B<_R(_A...), _F> { + static bool F(H &, const H &, G) { return false; } + __attribute__((noipa)) static _R bar(const H &) {} +}; +template +struct S<_R(_A...)> : T { + template using AH = B<_R(), _F>; + template S(_F) { + using AG = AH<_F>; + barr = AG::bar; + F = AG::F; + } + using AF = _R (*)(const H &); + AF barr; +}; +template class I; +template +struct I<_F(_B...)> {}; +template using W = decltype(k); +template struct V { + typedef I::type(typename Q<_B>::type...)> type; +}; +template +__attribute__((noipa)) typename V::value, _F, _B...>::type +baz(_F, _B...) { return typename V::value, _F, _B...>::type (); } +template struct AJ { + template struct _Ptr { using type = _Up *; }; + using AI = typename _Ptr<_Tp>::type; +}; +template struct Y { + using AI = typename AJ<_Tp>::AI; + AI operator->(); +}; +} +extern int z; +namespace N1 { +namespace N2 { +namespace N3 { +enum Z { Z1, Z2 }; +template struct X { + template + __attribute__((noipa)) void boo(long long, long long, long long, _F &) {} +}; +struct AC { + AC(int); + void m1(R::S); +}; +template +__attribute__((noipa)) void garply(void *, long long, long long, long long) {} +template <> +template +void X::boo(long long, long long x, long long y, _F &fi) { + AC pool(z); + for (;;) { + auto job = R::baz(garply<_F>, &fi, y, y, x); + pool.m1(job); + } +} +struct AB { + static AB &bleh(); + template + void boo(long first, long x, long y, _F fi) { + switch (ab1) { + case Z1: + ab2->boo(first, x, y, fi); + case Z2: + ab3->boo(first, x, y, fi); + } + } + Z ab1; + R::Y> ab2; + R::Y> ab3; +}; +template struct C; +template struct C<_F, false> { + __attribute__((noipa)) C(_F) {} + void boo(long first, long x, long y) { + auto u = AB::bleh(); + u.boo(first, x, y, *this); + } +}; +template struct AA { typedef C<_F, 0> type; }; +} +} +} +struct AD { + template + static void boo(long first, long x, long y, _F f) { + typename N1::N2::N3::AA<_F>::type fi(f); + fi.boo(first, x, y); + } + template + static void boo(long first, long x, _F f) { + boo(first, x, 0, f); + } +}; +template struct A { + void foo(long long, long long); + int *c; +}; +namespace { +template struct D { __attribute__((noipa)) D(int *) {} }; +} +template +void A::foo(long long x, long long y) +{ + int e; + D d(&e); + AD::boo(0, y, d); + long p; + for (p = 0; p < x; p++) + c[p] = c[p - 1]; +} diff --git a/gcc/varasm.cc b/gcc/varasm.cc index 008d9b1..747f74b 100644 --- a/gcc/varasm.cc +++ b/gcc/varasm.cc @@ -7458,17 +7458,63 @@ default_elf_select_rtx_section (machine_mode mode, rtx x, unsigned HOST_WIDE_INT align) { int reloc = compute_reloc_for_rtx (x); + tree decl = nullptr; + const char *prefix = nullptr; + int flags = 0; + + /* If it is a private COMDAT function symbol reference, call + function_rodata_section for the read-only or relocated read-only + data section associated with function DECL so that the COMDAT + section will be used for the private COMDAT function symbol. */ + if (HAVE_COMDAT_GROUP) + { + if (GET_CODE (x) == CONST + && GET_CODE (XEXP (x, 0)) == PLUS + && CONST_INT_P (XEXP (XEXP (x, 0), 1))) + x = XEXP (XEXP (x, 0), 0); + + if (GET_CODE (x) == SYMBOL_REF) + { + decl = SYMBOL_REF_DECL (x); + if (decl + && (TREE_CODE (decl) != FUNCTION_DECL + || !DECL_COMDAT_GROUP (decl) + || TREE_PUBLIC (decl))) + decl = nullptr; + } + } /* ??? Handle small data here somehow. */ if (reloc & targetm.asm_out.reloc_rw_mask ()) { - if (reloc == 1) + if (decl) + { + prefix = reloc == 1 ? ".data.rel.ro.local" : ".data.rel.ro"; + flags = SECTION_WRITE | SECTION_RELRO; + } + else if (reloc == 1) return get_named_section (NULL, ".data.rel.ro.local", 1); else return get_named_section (NULL, ".data.rel.ro", 3); } + if (decl) + { + const char *comdat = IDENTIFIER_POINTER (DECL_COMDAT_GROUP (decl)); + if (!prefix) + prefix = ".rodata"; + size_t prefix_len = strlen (prefix); + size_t comdat_len = strlen (comdat); + size_t len = prefix_len + sizeof (".pool.") + comdat_len; + char *name = XALLOCAVEC (char, len); + memcpy (name, prefix, prefix_len); + memcpy (name + prefix_len, ".pool.", sizeof (".pool.") - 1); + memcpy (name + prefix_len + sizeof (".pool.") - 1, comdat, + comdat_len + 1); + return get_section (name, flags | SECTION_LINKONCE, decl); + } + return mergeable_constant_section (mode, align, 0); } -- cgit v1.1 From 2f71e801ad0bb1f620334aadbd7c99cc4efe6309 Mon Sep 17 00:00:00 2001 From: Harald Anlauf Date: Sun, 25 Feb 2024 21:18:23 +0100 Subject: Fortran: do not evaluate polymorphic functions twice in assignment [PR114012] PR fortran/114012 gcc/fortran/ChangeLog: * trans-expr.cc (gfc_conv_procedure_call): Evaluate non-trivial arguments just once before assigning to an unlimited polymorphic dummy variable. gcc/testsuite/ChangeLog: * gfortran.dg/pr114012.f90: New test. --- gcc/fortran/trans-expr.cc | 4 ++ gcc/testsuite/gfortran.dg/pr114012.f90 | 81 ++++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/pr114012.f90 (limited to 'gcc') diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc index 118dfd7..d63c304 100644 --- a/gcc/fortran/trans-expr.cc +++ b/gcc/fortran/trans-expr.cc @@ -6691,6 +6691,10 @@ gfc_conv_procedure_call (gfc_se * se, gfc_symbol * sym, { tree efield; + /* Evaluate arguments just once. */ + if (e->expr_type != EXPR_VARIABLE) + parmse.expr = save_expr (parmse.expr); + /* Set the _data field. */ tmp = gfc_class_data_get (var); efield = fold_convert (TREE_TYPE (tmp), diff --git a/gcc/testsuite/gfortran.dg/pr114012.f90 b/gcc/testsuite/gfortran.dg/pr114012.f90 new file mode 100644 index 0000000..9dbb031 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr114012.f90 @@ -0,0 +1,81 @@ +! { dg-do run } +! PR fortran/114012 +! +! Polymorphic functions were evaluated twice in assignment + +program test + implicit none + + type :: custom_int + integer :: val = 2 + end type + + interface assignment(=) + procedure assign + end interface + interface operator(-) + procedure neg + end interface + + type(custom_int) :: i + integer :: count_assign, count_neg + + count_assign = 0 + count_neg = 0 + + i = 1 + if (count_assign /= 1 .or. count_neg /= 0) stop 1 + + i = -i + if (count_assign /= 2 .or. count_neg /= 1) stop 2 + if (i% val /= -1) stop 3 + + i = neg(i) + if (count_assign /= 3 .or. count_neg /= 2) stop 4 + if (i% val /= 1) stop 5 + + i = (neg(i)) + if (count_assign /= 4 .or. count_neg /= 3) stop 6 + if (i% val /= -1) stop 7 + + i = - neg(i) + if (count_assign /= 5 .or. count_neg /= 5) stop 8 + if (i% val /= -1) stop 9 + +contains + + subroutine assign (field, val) + type(custom_int), intent(out) :: field + class(*), intent(in) :: val + + count_assign = count_assign + 1 + + select type (val) + type is (integer) +! print *, " in assign(integer)", field%val, val + field%val = val + type is (custom_int) +! print *, " in assign(custom)", field%val, val%val + field%val = val%val + class default + error stop + end select + + end subroutine assign + + function neg (input_field) result(output_field) + type(custom_int), intent(in), target :: input_field + class(custom_int), allocatable :: output_field + allocate (custom_int :: output_field) + + count_neg = count_neg + 1 + + select type (output_field) + type is (custom_int) +! print *, " in neg", output_field%val, input_field%val + output_field%val = -input_field%val + class default + error stop + end select + end function neg +end program test -- cgit v1.1 From 9b0f7ef8bcf3b837365a2cf0af6b3ddbcdfdeb4f Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Mon, 26 Feb 2024 19:47:33 +0100 Subject: AVR: Dead code removal. gcc/ * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in an "if avr_adiw_reg_p()" block that's dead for AVR_TINY. --- gcc/config/avr/avr.cc | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index d3756a2..655a8e8 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -6291,10 +6291,7 @@ avr_out_compare (rtx_insn *insn, rtx *xop, int *plen) && (val8 == 0 || reg_unused_after (insn, xreg))) { - if (AVR_TINY) - avr_asm_len (TINY_SBIW (%A0, %B0, %1), xop, plen, 2); - else - avr_asm_len ("sbiw %0,%1", xop, plen, 1); + avr_asm_len ("sbiw %0,%1", xop, plen, 1); i++; continue; @@ -6305,9 +6302,7 @@ avr_out_compare (rtx_insn *insn, rtx *xop, int *plen) && compare_eq_p (insn) && reg_unused_after (insn, xreg)) { - return AVR_TINY - ? avr_asm_len (TINY_ADIW (%A0, %B0, %n1), xop, plen, 2) - : avr_asm_len ("adiw %0,%n1", xop, plen, 1); + return avr_asm_len ("adiw %0,%n1", xop, plen, 1); } } -- cgit v1.1 From 96773ce7d667452a50b0456681f415b47c22960a Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Mon, 26 Feb 2024 21:20:41 +0100 Subject: AVR: Tag optimization options as "Optimization". Some options that are pure optimizations where not tagged as such. gcc/ * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args) (mstrict-X): Tag as "Optimization". --- gcc/config/avr/avr.opt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/avr.opt index c9f2b4d..76530fd 100644 --- a/gcc/config/avr/avr.opt +++ b/gcc/config/avr/avr.opt @@ -19,7 +19,7 @@ ; . mcall-prologues -Target Mask(CALL_PROLOGUES) +Target Mask(CALL_PROLOGUES) Optimization Use subroutines for function prologues and epilogues. mmcu= @@ -79,7 +79,7 @@ Target Mask(TINY_STACK) Change only the low 8 bits of the stack pointer. mrelax -Target +Target Optimization Relax branches. mpmem-wrap-around @@ -87,11 +87,11 @@ Target Make the linker relaxation machine assume that a program counter wrap-around occurs. maccumulate-args -Target Mask(ACCUMULATE_OUTGOING_ARGS) +Target Mask(ACCUMULATE_OUTGOING_ARGS) Optimization Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards. This option can lead to reduced code size for functions that call many functions that get their arguments on the stack like, for example printf. mstrict-X -Target Var(avr_strict_X) Init(0) +Target Var(avr_strict_X) Init(0) Optimization When accessing RAM, use X as imposed by the hardware, i.e. just use pre-decrement, post-increment and indirect addressing with the X register. Without this option, the compiler may assume that there is an addressing mode X+const similar to Y+const and Z+const and emit instructions to emulate such an addressing mode for X. mflmap -- cgit v1.1 From 1e2a3b278d7770db6b5ca869756b1375fc3a77d6 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Tue, 27 Feb 2024 00:17:46 +0000 Subject: Daily bump. --- gcc/ChangeLog | 90 +++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 12 +++++++ gcc/c/ChangeLog | 8 +++++ gcc/fortran/ChangeLog | 7 ++++ gcc/po/ChangeLog | 4 +++ gcc/testsuite/ChangeLog | 69 +++++++++++++++++++++++++++++++++++++ 7 files changed, 191 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fa9dd74..f2c21f3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,93 @@ +2024-02-26 Georg-Johann Lay + + * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args) + (mstrict-X): Tag as "Optimization". + +2024-02-26 Georg-Johann Lay + + * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in + an "if avr_adiw_reg_p()" block that's dead for AVR_TINY. + +2024-02-26 Jakub Jelinek + H.J. Lu + + PR rtl-optimization/113617 + * varasm.cc (default_elf_select_rtx_section): For + references to private symbols in comdat sections + use .data.relro.local.pool., .data.relro.pool. + or .rodata. comdat sections. + +2024-02-26 Richard Biener + + PR tree-optimization/114099 + * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): + Create and fill in a needed virtual LC PHI for the alternate + exits. Remove code dealing with that missing. + +2024-02-26 Richard Biener + + PR tree-optimization/114068 + * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge): + New function. + (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI + on the main exit if needed. Remove band-aid for the case + it was missing. + +2024-02-26 H.J. Lu + + PR target/114097 + * config/i386/i386-options.cc (ix86_set_func_type): Check + interrupt instead of noreturn attribute. + +2024-02-26 Jakub Jelinek + + * config/i386/i386.cc (ix86_bitint_type_info): Add support for + !TARGET_64BIT. + +2024-02-26 Jakub Jelinek + + PR tree-optimization/114090 + * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x): + Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED + types. + ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise. + +2024-02-26 Jakub Jelinek + + PR middle-end/114084 + * fold-const.cc (fold_binary_loc): Avoid the final associate_trees + if all subtrees of var0 come from one of the op0 or op1 operands + and all subtrees of con0 come from the other one. Don't clear + variables which are never used afterwards. + +2024-02-26 Richard Biener + + PR middle-end/114070 + * genmatch.cc (parser::parse_c_expr): Do not record operand + lists but only mark operators used. + * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)): + Properly guard the case of tcc_comparison changing the VEC_COND + value operand type. + +2024-02-26 Jakub Jelinek + + PR target/114094 + * config/i386/i386.cc (x86_function_profiler): Add missing new-line + to printed instruction. + +2024-02-26 H.J. Lu + + PR target/114098 + * config/i386/amxtileintrin.h (_tile_loadconfig): Use + __builtin_ia32_ldtilecfg. + (_tile_storeconfig): Use __builtin_ia32_sttilecfg. + * config/i386/i386-builtin.def (BDESC): Add + __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg. + * config/i386/i386-expand.cc (ix86_expand_builtin): Handle + IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG. + * config/i386/i386.md (ldtilecfg): New pattern. + (sttilecfg): Likewise. + 2024-02-24 Richard Sandiford PR tree-optimization/113205 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 47afea3..abc12bc 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240226 +20240227 diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 694b255..dd8a85d 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,15 @@ +2024-02-26 Eric Botcazou + + PR ada/113893 + * exp_ch7.adb (Build_Anonymous_Master): Do not build the master + for a local designated type. + * exp_util.adb (Build_Allocate_Deallocate_Proc): Force Needs_Fin + to false if no finalization master is attached to an access type + and assert that it is anonymous in this case. + * sem_res.adb (Resolve_Allocator): Mention that the object might + not be finalized at all in the warning given when the type is an + anonymous access-to-controlled type. + 2024-01-23 Ronan Desplanques * gnatvsn.ads: Update year. diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index b8c3eb1..69495af 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,11 @@ +2024-02-26 Jakub Jelinek + + PR c/114042 + * c-parser.cc (c_parser_postfix_expression): Diagnose + __builtin_stdc_bit_* argument with ENUMERAL_TYPE or BOOLEAN_TYPE + type or if signed here rather than on the replacement builtins + in check_builtin_function_arguments. + 2024-02-22 Jakub Jelinek PR c/114007 diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 2a21185..644d9ec 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,10 @@ +2024-02-26 Harald Anlauf + + PR fortran/114012 + * trans-expr.cc (gfc_conv_procedure_call): Evaluate non-trivial + arguments just once before assigning to an unlimited polymorphic + dummy variable. + 2024-02-23 Steve Kargl Harald Anlauf diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index c6225cb..c6cda1e 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2024-02-26 Joseph Myers + + * sv.po, zh_CN.po: Update. + 2024-02-19 Joseph Myers * be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a101c52..025027d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,72 @@ +2024-02-26 Harald Anlauf + + PR fortran/114012 + * gfortran.dg/pr114012.f90: New test. + +2024-02-26 Jakub Jelinek + H.J. Lu + + PR rtl-optimization/113617 + * g++.dg/other/pr113617.C: New test. + * g++.dg/other/pr113617.h: New test. + * g++.dg/other/pr113617-aux.cc: New test. + +2024-02-26 Jakub Jelinek + + PR c/114042 + * gcc.dg/builtin-stdc-bit-2.c: Adjust testcase for actual builtin + names rather than names of builtin replacements. + +2024-02-26 Richard Biener + + PR tree-optimization/114099 + * gcc.dg/vect/vect-early-break_120-pr114099.c: New testcase. + +2024-02-26 Richard Biener + + PR tree-optimization/114068 + * gcc.dg/vect/vect-early-break_118-pr114068.c: New testcase. + * gcc.dg/vect/vect-early-break_119-pr114068.c: Likewise. + +2024-02-26 Eric Botcazou + + * gnat.dg/access10.adb: New test. + +2024-02-26 H.J. Lu + + PR target/114097 + * gcc.target/i386/pr114097-1.c: New test. + +2024-02-26 Rainer Orth + + PR ipa/61159 + * gcc.c-torture/compile/pr61159.c: xfail on Solaris/x86 with as. + +2024-02-26 Jakub Jelinek + + PR tree-optimization/114090 + * gcc.dg/pr114090.c: New test. + +2024-02-26 Jakub Jelinek + + PR middle-end/114084 + * gcc.dg/bitint-94.c: New test. + +2024-02-26 Richard Biener + + PR middle-end/114070 + * gcc.dg/torture/pr114070.c: New testcase. + +2024-02-26 Jakub Jelinek + + PR target/114094 + * gcc.target/i386/pr114094.c: New test. + +2024-02-26 H.J. Lu + + PR target/114098 + * gcc.target/i386/amxtile-4.c: New test. + 2024-02-25 Jerry DeLisle PR libfortran/105456 -- cgit v1.1 From 8e8eac3dea017eae739eb79d540887bb2cf1dc9f Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Tue, 27 Feb 2024 08:20:25 +0100 Subject: testsuite: Fix gcc.dg/attr-weakref-1.c on Solaris/x86 with as [PR70582] gcc.dg/attr-weakref-1.c FAILs on 32 and 64-bit Solaris/x86 with the native assembler: FAIL: gcc.dg/attr-weakref-1.c (test for excess errors) UNRESOLVED: gcc.dg/attr-weakref-1.c compilation failed to produce executable Excess errors: Assembler: attr-weakref-1.c "/var/tmp//ccUSaysF.s", line 171 : Multiply defined symbol: "Wv3a" This is a bug in the native as, which isn't seeing fixes recently. Since only a single subtest is affected, this patch omits that one. Tested on i386-pc-solaris2.11 (as and gas) and x86_64-pc-linux-gnu. 2024-02-24 Rainer Orth gcc/testsuite: PR ipa/70582 * gcc.dg/attr-weakref-1.c (dg-additional-options): Define SOLARIS_X86_AS as appropriate. (lv3, Wv3a, pv3a): Wrap in !SOLARIS_X86_AS. (main): Likewise for chk (pv3a). --- gcc/testsuite/gcc.dg/attr-weakref-1.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/attr-weakref-1.c b/gcc/testsuite/gcc.dg/attr-weakref-1.c index 9e14b60..f13aee4 100644 --- a/gcc/testsuite/gcc.dg/attr-weakref-1.c +++ b/gcc/testsuite/gcc.dg/attr-weakref-1.c @@ -14,6 +14,8 @@ // { dg-options "-O2" } // { dg-additional-options "-Wl,-undefined,dynamic_lookup" { target *-*-darwin* } } // { dg-additional-options "-Wl,-flat_namespace" { target *-*-darwin[89]* } } +// One subtest doesn't assemble with the Solaris/x86 as (PR ipa/70582) +// { dg-additional-options "-DSOLARIS_X86_AS" { target { *86*-*-solaris2* && { ! gas } } } } // { dg-additional-sources "attr-weakref-1a.c" } // Copyright 2005 Free Software Foundation, Inc. @@ -46,9 +48,11 @@ vtype gv2; static vtype Wv2a __attribute__((weakref ("gv2"))); static vtype *pv2a USED = &Wv2a; +#if !defined SOLARIS_X86_AS static vtype lv3; static vtype Wv3a __attribute__((weakref ("lv3"))); static vtype *pv3a USED = &Wv3a; +#endif extern vtype uv4; static vtype Wv4a __attribute__((weakref ("uv4"))); @@ -192,7 +196,9 @@ extern ftype wf14 __attribute__((weak)); int main () { chk (!pv1a); chk (pv2a); +#if !defined(SOLARIS_X86_AS) chk (pv3a); +#endif chk (pv4a); chk (pv4); chk (pv5a); -- cgit v1.1 From 8a5d9409584aeb777b06f9c19c7d1a3552d496ad Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 26 Feb 2024 15:17:43 +0100 Subject: tree-optimization/114081 - dominator update for prologue peeling The following implements manual update for multi-exit loop prologue peeling during vectorization. PR tree-optimization/114081 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Perform manual dominator update for prologue peeling. (vect_do_peeling): Properly update dominators after adding the prologue-around guard. * gcc.dg/vect/vect-early-break_121-pr114081.c: New testcase. --- .../gcc.dg/vect/vect-early-break_121-pr114081.c | 39 +++++++++++ gcc/tree-vect-loop-manip.cc | 78 ++++++++++++++++------ 2 files changed, 95 insertions(+), 22 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/vect-early-break_121-pr114081.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_121-pr114081.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_121-pr114081.c new file mode 100644 index 0000000..423ff0b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_121-pr114081.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-add-options vect_early_break } */ +/* { dg-require-effective-target vect_early_break } */ +/* { dg-require-effective-target vect_int } */ +/* { dg-additional-options "-O3" } */ +/* { dg-additional-options "-mavx2" { target { x86_64-*-* i?86-*-* } } } */ + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ + +typedef struct filter_list_entry { + const char *name; + int id; + void (*function)(); +} filter_list_entry; + +static const filter_list_entry filter_list[9] = {0}; + +void php_zval_filter(int filter, int id1) { + filter_list_entry filter_func; + + int size = 9; + for (int i = 0; i < size; ++i) { + if (filter_list[i].id == filter) { + filter_func = filter_list[i]; + goto done; + } + } + +#pragma GCC novector + for (int i = 0; i < size; ++i) { + if (filter_list[i].id == 0x0204) { + filter_func = filter_list[i]; + goto done; + } + } +done: + if (!filter_func.id) + filter_func.function(); +} diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc index 137b053..f72da91 100644 --- a/gcc/tree-vect-loop-manip.cc +++ b/gcc/tree-vect-loop-manip.cc @@ -1594,7 +1594,6 @@ slpeel_tree_duplicate_loop_to_edge_cfg (class loop *loop, edge loop_exit, auto loop_exits = get_loop_exit_edges (loop); bool multiple_exits_p = loop_exits.length () > 1; auto_vec doms; - class loop *update_loop = NULL; if (at_exit) /* Add the loop copy at exit. */ { @@ -1856,11 +1855,33 @@ slpeel_tree_duplicate_loop_to_edge_cfg (class loop *loop, edge loop_exit, correct. */ if (multiple_exits_p) { - update_loop = new_loop; + class loop *update_loop = new_loop; doms = get_all_dominated_blocks (CDI_DOMINATORS, loop->header); for (unsigned i = 0; i < doms.length (); ++i) if (flow_bb_inside_loop_p (loop, doms[i])) doms.unordered_remove (i); + + for (edge e : get_loop_exit_edges (update_loop)) + { + edge ex; + edge_iterator ei; + FOR_EACH_EDGE (ex, ei, e->dest->succs) + { + /* Find the first non-fallthrough block as fall-throughs can't + dominate other blocks. */ + if (single_succ_p (ex->dest)) + { + doms.safe_push (ex->dest); + ex = single_succ_edge (ex->dest); + } + doms.safe_push (ex->dest); + } + doms.safe_push (e->dest); + } + + iterate_fix_dominators (CDI_DOMINATORS, doms, false); + if (updated_doms) + updated_doms->safe_splice (doms); } } else /* Add the copy at entry. */ @@ -1910,33 +1931,28 @@ slpeel_tree_duplicate_loop_to_edge_cfg (class loop *loop, edge loop_exit, set_immediate_dominator (CDI_DOMINATORS, new_loop->header, loop_preheader_edge (new_loop)->src); + /* Update dominators for multiple exits. */ if (multiple_exits_p) - update_loop = loop; - } - - if (multiple_exits_p) - { - for (edge e : get_loop_exit_edges (update_loop)) { - edge ex; - edge_iterator ei; - FOR_EACH_EDGE (ex, ei, e->dest->succs) + for (edge alt_e : loop_exits) { - /* Find the first non-fallthrough block as fall-throughs can't - dominate other blocks. */ - if (single_succ_p (ex->dest)) + if (alt_e == loop_exit) + continue; + basic_block old_dom + = get_immediate_dominator (CDI_DOMINATORS, alt_e->dest); + if (flow_bb_inside_loop_p (loop, old_dom)) { - doms.safe_push (ex->dest); - ex = single_succ_edge (ex->dest); + auto_vec queue; + for (auto son = first_dom_son (CDI_DOMINATORS, old_dom); + son; son = next_dom_son (CDI_DOMINATORS, son)) + if (!flow_bb_inside_loop_p (loop, son)) + queue.safe_push (son); + for (auto son : queue) + set_immediate_dominator (CDI_DOMINATORS, + son, get_bb_copy (old_dom)); } - doms.safe_push (ex->dest); } - doms.safe_push (e->dest); } - - iterate_fix_dominators (CDI_DOMINATORS, doms, false); - if (updated_doms) - updated_doms->safe_splice (doms); } free (new_bbs); @@ -3368,6 +3384,24 @@ vect_do_peeling (loop_vec_info loop_vinfo, tree niters, tree nitersm1, guard_to, guard_bb, prob_prolog.invert (), irred_flag); + for (edge alt_e : get_loop_exit_edges (prolog)) + { + if (alt_e == prolog_e) + continue; + basic_block old_dom + = get_immediate_dominator (CDI_DOMINATORS, alt_e->dest); + if (flow_bb_inside_loop_p (prolog, old_dom)) + { + auto_vec queue; + for (auto son = first_dom_son (CDI_DOMINATORS, old_dom); + son; son = next_dom_son (CDI_DOMINATORS, son)) + if (!flow_bb_inside_loop_p (prolog, son)) + queue.safe_push (son); + for (auto son : queue) + set_immediate_dominator (CDI_DOMINATORS, son, guard_bb); + } + } + e = EDGE_PRED (guard_to, 0); e = (e != guard_e ? e : EDGE_PRED (guard_to, 1)); slpeel_update_phi_nodes_for_guard1 (prolog, loop, guard_e, e); -- cgit v1.1 From c3c44c01d20b00ab5228f32596153b7f4cbc6036 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 27 Feb 2024 09:52:07 +0100 Subject: expand: Add trivial folding for bit query builtins at expansion time [PR114044] While it seems a lot of places in various optimization passes fold bit query internal functions with INTEGER_CST arguments to INTEGER_CST when there is a lhs, when lhs is missing, all the removals of such dead stmts are guarded with -ftree-dce, so with -fno-tree-dce those unfolded ifn calls remain in the IL until expansion. If they have large/huge BITINT_TYPE arguments, there is no BLKmode optab and so expansion ICEs, and bitint lowering doesn't touch such calls because it doesn't know they need touching, functions only containing those will not even be further processed by the pass because there are no non-small BITINT_TYPE SSA_NAMEs + the 2 exceptions (stores of BITINT_TYPE INTEGER_CSTs and conversions from BITINT_TYPE INTEGER_CSTs to floating point SSA_NAMEs) and when walking there is no special case for calls with BITINT_TYPE INTEGER_CSTs either, those are for normal calls normally handled at expansion time. So, the following patch adjust the expansion of these 6 ifns, by doing nothing if there is no lhs, and also just in case and user disabled all possible passes that would fold this handles the case of setting lhs to ifn call with INTEGER_CST argument. 2024-02-27 Jakub Jelinek PR rtl-optimization/114044 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN. * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS, expand_PARITY): Declare. * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS, expand_PARITY): New functions. (expand_POPCOUNT): Use expand_bitquery. * gcc.dg/bitint-95.c: New test. --- gcc/internal-fn.cc | 55 ++++++++++++++++++++++++++++++++++++++++ gcc/internal-fn.def | 10 ++++---- gcc/internal-fn.h | 5 ++++ gcc/testsuite/gcc.dg/bitint-95.c | 45 ++++++++++++++++++++++++++++++++ 4 files changed, 110 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/bitint-95.c (limited to 'gcc') diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc index a07f25f..fcf47c7 100644 --- a/gcc/internal-fn.cc +++ b/gcc/internal-fn.cc @@ -52,6 +52,7 @@ along with GCC; see the file COPYING3. If not see #include "explow.h" #include "rtl-iter.h" #include "gimple-range.h" +#include "fold-const-call.h" /* For lang_hooks.types.type_for_mode. */ #include "langhooks.h" @@ -5107,9 +5108,63 @@ expand_BITINTTOFLOAT (internal_fn, gcall *stmt) emit_move_insn (target, val); } +static bool +expand_bitquery (internal_fn fn, gcall *stmt) +{ + tree lhs = gimple_call_lhs (stmt); + if (lhs == NULL_TREE) + return false; + tree arg = gimple_call_arg (stmt, 0); + if (TREE_CODE (arg) == INTEGER_CST) + { + tree ret = fold_const_call (as_combined_fn (fn), TREE_TYPE (arg), arg); + gcc_checking_assert (ret && TREE_CODE (ret) == INTEGER_CST); + expand_assignment (lhs, ret, false); + return false; + } + return true; +} + +void +expand_CLRSB (internal_fn fn, gcall *stmt) +{ + if (expand_bitquery (fn, stmt)) + expand_unary_optab_fn (fn, stmt, clrsb_optab); +} + +void +expand_CLZ (internal_fn fn, gcall *stmt) +{ + if (expand_bitquery (fn, stmt)) + expand_unary_optab_fn (fn, stmt, clz_optab); +} + +void +expand_CTZ (internal_fn fn, gcall *stmt) +{ + if (expand_bitquery (fn, stmt)) + expand_unary_optab_fn (fn, stmt, ctz_optab); +} + +void +expand_FFS (internal_fn fn, gcall *stmt) +{ + if (expand_bitquery (fn, stmt)) + expand_unary_optab_fn (fn, stmt, ffs_optab); +} + +void +expand_PARITY (internal_fn fn, gcall *stmt) +{ + if (expand_bitquery (fn, stmt)) + expand_unary_optab_fn (fn, stmt, parity_optab); +} + void expand_POPCOUNT (internal_fn fn, gcall *stmt) { + if (!expand_bitquery (fn, stmt)) + return; if (gimple_call_num_args (stmt) == 1) { expand_unary_optab_fn (fn, stmt, popcount_optab); diff --git a/gcc/internal-fn.def b/gcc/internal-fn.def index c14d303..848bb9d 100644 --- a/gcc/internal-fn.def +++ b/gcc/internal-fn.def @@ -440,11 +440,11 @@ DEF_INTERNAL_OPTAB_FN (COMPLEX_FMS, ECF_CONST, cmls, ternary) DEF_INTERNAL_OPTAB_FN (COMPLEX_FMS_CONJ, ECF_CONST, cmls_conj, ternary) /* Unary integer ops. */ -DEF_INTERNAL_INT_FN (CLRSB, ECF_CONST | ECF_NOTHROW, clrsb, unary) -DEF_INTERNAL_INT_FN (CLZ, ECF_CONST | ECF_NOTHROW, clz, unary) -DEF_INTERNAL_INT_FN (CTZ, ECF_CONST | ECF_NOTHROW, ctz, unary) -DEF_INTERNAL_INT_FN (FFS, ECF_CONST | ECF_NOTHROW, ffs, unary) -DEF_INTERNAL_INT_FN (PARITY, ECF_CONST | ECF_NOTHROW, parity, unary) +DEF_INTERNAL_INT_EXT_FN (CLRSB, ECF_CONST | ECF_NOTHROW, clrsb, unary) +DEF_INTERNAL_INT_EXT_FN (CLZ, ECF_CONST | ECF_NOTHROW, clz, unary) +DEF_INTERNAL_INT_EXT_FN (CTZ, ECF_CONST | ECF_NOTHROW, ctz, unary) +DEF_INTERNAL_INT_EXT_FN (FFS, ECF_CONST | ECF_NOTHROW, ffs, unary) +DEF_INTERNAL_INT_EXT_FN (PARITY, ECF_CONST | ECF_NOTHROW, parity, unary) DEF_INTERNAL_INT_EXT_FN (POPCOUNT, ECF_CONST | ECF_NOTHROW, popcount, unary) DEF_INTERNAL_FN (GOMP_TARGET_REV, ECF_NOVOPS | ECF_LEAF | ECF_NOTHROW, NULL) diff --git a/gcc/internal-fn.h b/gcc/internal-fn.h index bccee1c..2785a5a 100644 --- a/gcc/internal-fn.h +++ b/gcc/internal-fn.h @@ -262,6 +262,11 @@ extern void expand_MULBITINT (internal_fn, gcall *); extern void expand_DIVMODBITINT (internal_fn, gcall *); extern void expand_FLOATTOBITINT (internal_fn, gcall *); extern void expand_BITINTTOFLOAT (internal_fn, gcall *); +extern void expand_CLRSB (internal_fn, gcall *); +extern void expand_CLZ (internal_fn, gcall *); +extern void expand_CTZ (internal_fn, gcall *); +extern void expand_FFS (internal_fn, gcall *); +extern void expand_PARITY (internal_fn, gcall *); extern void expand_POPCOUNT (internal_fn, gcall *); extern bool vectorized_internal_fn_supported_p (internal_fn, tree); diff --git a/gcc/testsuite/gcc.dg/bitint-95.c b/gcc/testsuite/gcc.dg/bitint-95.c new file mode 100644 index 0000000..9794652 --- /dev/null +++ b/gcc/testsuite/gcc.dg/bitint-95.c @@ -0,0 +1,45 @@ +/* PR rtl-optimization/114044 */ +/* { dg-do compile { target bitint575 } } */ +/* { dg-options "-O -fno-tree-dce" } */ + +void +foo (void) +{ + unsigned _BitInt (575) a = 3; + __builtin_clzg (a); +} + +void +bar (void) +{ + unsigned _BitInt (575) a = 3; + __builtin_ctzg (a); +} + +void +baz (void) +{ + signed _BitInt (575) a = 3; + __builtin_clrsbg (a); +} + +void +qux (void) +{ + signed _BitInt (575) a = 3; + __builtin_ffsg (a); +} + +void +garply (void) +{ + unsigned _BitInt (575) a = 3; + __builtin_parityg (a); +} + +void +corge (void) +{ + unsigned _BitInt (575) a = 3; + __builtin_popcountg (a); +} -- cgit v1.1 From a0b1798042d033fd2cc2c806afbb77875dd2909b Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 26 Feb 2024 13:33:21 +0100 Subject: tree-optimization/114074 - CHREC multiplication and undefined overflow When folding a multiply CHRECs are handled like {a, +, b} * c is {a*c, +, b*c} but that isn't generally correct when overflow invokes undefined behavior. The following uses unsigned arithmetic unless either a is zero or a and b have the same sign. I've used simple early outs for INTEGER_CSTs and otherwise use a range-query since we lack a tree_expr_nonpositive_p and get_range_pos_neg isn't a good fit. PR tree-optimization/114074 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL. * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs. Handle poly vs. non-poly multiplication correctly with respect to undefined behavior on overflow. * gcc.dg/torture/pr114074.c: New testcase. * gcc.dg/pr68317.c: Adjust expected location of diagnostic. * gcc.dg/vect/vect-early-break_119-pr114068.c: Do not expect loop to be vectorized. --- gcc/testsuite/gcc.dg/pr68317.c | 4 +- gcc/testsuite/gcc.dg/torture/pr114074.c | 27 +++++++++++ .../gcc.dg/vect/vect-early-break_119-pr114068.c | 2 - gcc/tree-chrec.cc | 55 +++++++++++++++++----- gcc/tree-chrec.h | 2 +- 5 files changed, 74 insertions(+), 16 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/torture/pr114074.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/pr68317.c b/gcc/testsuite/gcc.dg/pr68317.c index bd053a7..06cd2e1 100644 --- a/gcc/testsuite/gcc.dg/pr68317.c +++ b/gcc/testsuite/gcc.dg/pr68317.c @@ -12,8 +12,8 @@ foo () { int32_t index = 0; - for (index; index <= 10; index--) // expected warning here + for (index; index <= 10; index--) /* { dg-warning "iteration \[0-9\]+ invokes undefined behavior" } */ /* Result of the following multiply will overflow when converted to signed int32_t. */ - bar ((0xcafe + index) * 0xdead); /* { dg-warning "iteration \[0-9\]+ invokes undefined behavior" } */ + bar ((0xcafe + index) * 0xdead); } diff --git a/gcc/testsuite/gcc.dg/torture/pr114074.c b/gcc/testsuite/gcc.dg/torture/pr114074.c new file mode 100644 index 0000000..336e976 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr114074.c @@ -0,0 +1,27 @@ +/* { dg-do run } */ + +int a, b, d; + +__attribute__((noipa)) void +foo (void) +{ + ++d; +} + +int +main () +{ + for (a = 0; a > -3; a -= 2) + { + int c = a; + b = __INT_MAX__ - 3000; + a = ~c * b; + foo (); + if (!a) + break; + a = c; + } + if (d != 2) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_119-pr114068.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_119-pr114068.c index a65ef7b..2063979 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-early-break_119-pr114068.c +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_119-pr114068.c @@ -4,8 +4,6 @@ /* { dg-require-effective-target vect_int } */ /* { dg-additional-options "-O3" } */ -/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ - struct h { int b; int c; diff --git a/gcc/tree-chrec.cc b/gcc/tree-chrec.cc index 61456fe..2e6c735 100644 --- a/gcc/tree-chrec.cc +++ b/gcc/tree-chrec.cc @@ -38,6 +38,8 @@ along with GCC; see the file COPYING3. If not see #include "gimple.h" #include "tree-ssa-loop.h" #include "dumpfile.h" +#include "value-range.h" +#include "value-query.h" #include "tree-scalar-evolution.h" /* Extended folder for chrecs. */ @@ -404,6 +406,10 @@ chrec_fold_multiply (tree type, || automatically_generated_chrec_p (op1)) return chrec_fold_automatically_generated_operands (op0, op1); + if (TREE_CODE (op0) != POLYNOMIAL_CHREC + && TREE_CODE (op1) == POLYNOMIAL_CHREC) + std::swap (op0, op1); + switch (TREE_CODE (op0)) { case POLYNOMIAL_CHREC: @@ -428,10 +434,43 @@ chrec_fold_multiply (tree type, if (integer_zerop (op1)) return build_int_cst (type, 0); - return build_polynomial_chrec - (CHREC_VARIABLE (op0), - chrec_fold_multiply (type, CHREC_LEFT (op0), op1), - chrec_fold_multiply (type, CHREC_RIGHT (op0), op1)); + /* When overflow is undefined and CHREC_LEFT/RIGHT do not have the + same sign or CHREC_LEFT is zero then folding the multiply into + the addition does not have the same behavior on overflow. Use + unsigned arithmetic in that case. */ + value_range rl, rr; + if (!ANY_INTEGRAL_TYPE_P (type) + || TYPE_OVERFLOW_WRAPS (type) + || integer_zerop (CHREC_LEFT (op0)) + || (TREE_CODE (CHREC_LEFT (op0)) == INTEGER_CST + && TREE_CODE (CHREC_RIGHT (op0)) == INTEGER_CST + && (tree_int_cst_sgn (CHREC_LEFT (op0)) + == tree_int_cst_sgn (CHREC_RIGHT (op0)))) + || (get_range_query (cfun)->range_of_expr (rl, CHREC_LEFT (op0)) + && !rl.undefined_p () + && (rl.nonpositive_p () || rl.nonnegative_p ()) + && get_range_query (cfun)->range_of_expr (rr, + CHREC_RIGHT (op0)) + && !rr.undefined_p () + && ((rl.nonpositive_p () && rr.nonpositive_p ()) + || (rl.nonnegative_p () && rr.nonnegative_p ())))) + { + tree left = chrec_fold_multiply (type, CHREC_LEFT (op0), op1); + tree right = chrec_fold_multiply (type, CHREC_RIGHT (op0), op1); + return build_polynomial_chrec (CHREC_VARIABLE (op0), left, right); + } + else + { + tree utype = unsigned_type_for (type); + tree uop1 = chrec_convert_rhs (utype, op1); + tree uleft0 = chrec_convert_rhs (utype, CHREC_LEFT (op0)); + tree uright0 = chrec_convert_rhs (utype, CHREC_RIGHT (op0)); + tree left = chrec_fold_multiply (utype, uleft0, uop1); + tree right = chrec_fold_multiply (utype, uright0, uop1); + tree tem = build_polynomial_chrec (CHREC_VARIABLE (op0), + left, right); + return chrec_convert_rhs (type, tem); + } } CASE_CONVERT: @@ -449,13 +488,7 @@ chrec_fold_multiply (tree type, switch (TREE_CODE (op1)) { case POLYNOMIAL_CHREC: - gcc_checking_assert - (!chrec_contains_symbols_defined_in_loop (op1, - CHREC_VARIABLE (op1))); - return build_polynomial_chrec - (CHREC_VARIABLE (op1), - chrec_fold_multiply (type, CHREC_LEFT (op1), op0), - chrec_fold_multiply (type, CHREC_RIGHT (op1), op0)); + gcc_unreachable (); CASE_CONVERT: if (tree_contains_chrecs (op1, NULL)) diff --git a/gcc/tree-chrec.h b/gcc/tree-chrec.h index e3a5ba5..8003eb5 100644 --- a/gcc/tree-chrec.h +++ b/gcc/tree-chrec.h @@ -63,7 +63,7 @@ extern tree chrec_fold_plus (tree, tree, tree); extern tree chrec_fold_minus (tree, tree, tree); extern tree chrec_fold_multiply (tree, tree, tree); extern tree chrec_convert (tree, tree, gimple *, bool = true, tree = NULL); -extern tree chrec_convert_rhs (tree, tree, gimple *); +extern tree chrec_convert_rhs (tree, tree, gimple * = NULL); extern tree chrec_convert_aggressive (tree, tree, bool *); /* Operations. */ -- cgit v1.1 From a82ecdeacf83996321de5312522b0cc961e02a95 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Mon, 26 Feb 2024 17:20:58 +0000 Subject: arm: warn about deprecation of iwmmx in mmintrin.h GCC 13's changes file documents that iwmmx is deprecated. Raise the bar by warning when the mmintrin.h header is included by users, but provide a way to suppress the warning. gcc: * config/arm/mmintrin.h: Warn if this header is included without defining __ENABLE_DEPRECATED_IWMMXT. --- gcc/config/arm/mmintrin.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'gcc') diff --git a/gcc/config/arm/mmintrin.h b/gcc/config/arm/mmintrin.h index 0765950..e9cc3dd 100644 --- a/gcc/config/arm/mmintrin.h +++ b/gcc/config/arm/mmintrin.h @@ -28,6 +28,9 @@ #error mmintrin.h included without enabling WMMX/WMMX2 instructions (e.g. -march=iwmmxt or -march=iwmmxt2) #endif +#ifndef __ENABLE_DEPRECATED_IWMMXT +#warning support for WMMX/WMMX2 is deprecated and will be removed in GCC 15. Define __ENABLE_DEPRECATED_IWMMXT to suppress this warning +#endif #if defined __cplusplus extern "C" { -- cgit v1.1 From 43ad6ce60108acc822efcd394b75e270c1996cb5 Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Tue, 27 Feb 2024 08:36:58 -0500 Subject: analyzer: fix ICE on floating-point bounds [PR111881] gcc/analyzer/ChangeLog: PR analyzer/111881 * constraint-manager.cc (bound::ensure_closed): Assert that m_constant has integral type. (range::add_bound): Bail out on floating point constants. gcc/testsuite/ChangeLog: PR analyzer/111881 * c-c++-common/analyzer/conditionals-pr111881.c: New test. Signed-off-by: David Malcolm --- gcc/analyzer/constraint-manager.cc | 6 ++++++ gcc/testsuite/c-c++-common/analyzer/conditionals-pr111881.c | 8 ++++++++ 2 files changed, 14 insertions(+) create mode 100644 gcc/testsuite/c-c++-common/analyzer/conditionals-pr111881.c (limited to 'gcc') diff --git a/gcc/analyzer/constraint-manager.cc b/gcc/analyzer/constraint-manager.cc index e8bcabe..a380b95 100644 --- a/gcc/analyzer/constraint-manager.cc +++ b/gcc/analyzer/constraint-manager.cc @@ -124,10 +124,12 @@ bound::ensure_closed (enum bound_kind bound_kind) For example, convert 3 < x into 4 <= x, and convert x < 5 into x <= 4. */ gcc_assert (CONSTANT_CLASS_P (m_constant)); + gcc_assert (INTEGRAL_TYPE_P (TREE_TYPE (m_constant))); m_constant = fold_build2 (bound_kind == BK_UPPER ? MINUS_EXPR : PLUS_EXPR, TREE_TYPE (m_constant), m_constant, integer_one_node); gcc_assert (CONSTANT_CLASS_P (m_constant)); + gcc_assert (INTEGRAL_TYPE_P (TREE_TYPE (m_constant))); m_closed = true; } } @@ -306,6 +308,10 @@ range::above_upper_bound (tree rhs_const) const bool range::add_bound (bound b, enum bound_kind bound_kind) { + /* Bail out on floating point constants. */ + if (!INTEGRAL_TYPE_P (TREE_TYPE (b.m_constant))) + return true; + b.ensure_closed (bound_kind); switch (bound_kind) diff --git a/gcc/testsuite/c-c++-common/analyzer/conditionals-pr111881.c b/gcc/testsuite/c-c++-common/analyzer/conditionals-pr111881.c new file mode 100644 index 0000000..ecf165f --- /dev/null +++ b/gcc/testsuite/c-c++-common/analyzer/conditionals-pr111881.c @@ -0,0 +1,8 @@ +/* Verify we don't ICE on certain float conditionals. */ + +/* { dg-additional-options "-Ofast" } */ + +int test_pr111881 (float sf1) +{ + return sf1 <= 0 || sf1 >= 7 ? 0 : sf1; +} -- cgit v1.1 From 27534e793e51560213cef999df66a7214ee7502a Mon Sep 17 00:00:00 2001 From: Eric Botcazou Date: Tue, 27 Feb 2024 18:01:00 +0100 Subject: Fix internal error on non-byte-aligned reference in GIMPLE DSE This is a regression present on the mainline, 13 and 12 branches. For the attached Ada case, it's a tree checking failure on the mainline at -O: +===========================GNAT BUG DETECTED==============================+ | 14.0.1 20240226 (experimental) [master r14-9171-g4972f97a265] GCC error:| | tree check: expected tree that contains 'decl common' structure, | | have 'component_ref' in tree_could_trap_p, at tree-eh.cc:2733 | | Error detected around /home/eric/cvs/gcc/gcc/testsuite/gnat.dg/opt104.adb: Time is a 10-byte record and Packed_Rec.T is placed at bit-offset 65 because of the packing. so tree-ssa-dse.cc:setup_live_bytes_from_ref has computed a const_size of 88 from ref->offset of 65 and ref->max_size of 80. Then in tree-ssa-dse.cc:compute_trims: 411 int last_live = bitmap_last_set_bit (live); (gdb) next 412 if (ref->size.is_constant (&const_size)) (gdb) 414 int last_orig = (const_size / BITS_PER_UNIT) - 1; (gdb) 418 *trim_tail = last_orig - last_live; (gdb) call debug_bitmap (live) n_bits = 256, set = {0 1 2 3 4 5 6 7 8 9 10 } (gdb) p last_live $33 = 10 (gdb) p const_size $34 = 80 (gdb) p last_orig $35 = 9 (gdb) p *trim_tail $36 = -1 In other words, compute_trims is overlooking the alignment adjustments that setup_live_bytes_from_ref applied earlier. Moveover it reads: /* We use sbitmaps biased such that ref->offset is bit zero and the bitmap extends through ref->size. So we know that in the original bitmap bits 0..ref->size were true. We don't actually need the bitmap, just the REF to compute the trims. */ but setup_live_bytes_from_ref used ref->max_size instead of ref->size. It appears that all the callers of compute_trims assume that ref->offset is byte aligned and that the trimmed bytes are relative to ref->size, so the patch simply adds an early return if either condition is not fulfilled. gcc/ * tree-ssa-dse.cc (compute_trims): Fix description. Return early if either ref->offset is not byte aligned or ref->size is not known to be equal to ref->max_size. (maybe_trim_complex_store): Fix description. (maybe_trim_constructor_store): Likewise. (maybe_trim_partially_dead_store): Likewise. gcc/testsuite/ * gnat.dg/opt104.ads, gnat.dg/opt104.adb: New test. --- gcc/testsuite/gnat.dg/opt104.adb | 22 +++++++++++++++++ gcc/testsuite/gnat.dg/opt104.ads | 40 +++++++++++++++++++++++++++++++ gcc/tree-ssa-dse.cc | 51 +++++++++++++++++++++------------------- 3 files changed, 89 insertions(+), 24 deletions(-) create mode 100644 gcc/testsuite/gnat.dg/opt104.adb create mode 100644 gcc/testsuite/gnat.dg/opt104.ads (limited to 'gcc') diff --git a/gcc/testsuite/gnat.dg/opt104.adb b/gcc/testsuite/gnat.dg/opt104.adb new file mode 100644 index 0000000..1548c3e --- /dev/null +++ b/gcc/testsuite/gnat.dg/opt104.adb @@ -0,0 +1,22 @@ +-- { dg-do compile } +-- { dg-options "-O -gnatws" } + +package body Opt104 is + + procedure Proc (R : Rec) is + Data : Packed_Rec; + + begin + case R.D is + when True => + for I in 1 .. R.Len loop + exit; + end loop; + + when False => + null; + end case; + end; + +end Opt104; + diff --git a/gcc/testsuite/gnat.dg/opt104.ads b/gcc/testsuite/gnat.dg/opt104.ads new file mode 100644 index 0000000..a177ed0 --- /dev/null +++ b/gcc/testsuite/gnat.dg/opt104.ads @@ -0,0 +1,40 @@ +package Opt104 is + + type Time is record + S : Integer; + B1 : Boolean; + B2 : Boolean; + B3 : Boolean; + B4 : Boolean; + B5 : Boolean; + B6 : Boolean; + end record; + + Zero_Time : constant Time := + (S => 0, + B1 => False, + B2 => False, + B3 => False, + B4 => False, + B5 => False, + B6 => False); + + type Root is tagged null record; + + type Packed_Rec is record + R : Root; + B : Boolean; + T : Time := Zero_Time; + end record; + pragma Pack (Packed_Rec); + + type Rec (D : Boolean) is record + case D is + when True => Len : Integer; + when False => null; + end case; + end record; + + procedure Proc (R : Rec); + +end Opt104; diff --git a/gcc/tree-ssa-dse.cc b/gcc/tree-ssa-dse.cc index 81b6512..7c34851 100644 --- a/gcc/tree-ssa-dse.cc +++ b/gcc/tree-ssa-dse.cc @@ -403,11 +403,11 @@ setup_live_bytes_from_ref (ao_ref *ref, sbitmap live_bytes) return false; } -/* Compute the number of elements that we can trim from the head and - tail of ORIG resulting in a bitmap that is a superset of LIVE. +/* Compute the number of stored bytes that we can trim from the head and + tail of REF. LIVE is the bitmap of stores to REF that are still live. - Store the number of elements trimmed from the head and tail in - TRIM_HEAD and TRIM_TAIL. + Store the number of bytes trimmed from the head and tail in TRIM_HEAD + and TRIM_TAIL respectively. STMT is the statement being trimmed and is used for debugging dump output only. */ @@ -416,10 +416,17 @@ static void compute_trims (ao_ref *ref, sbitmap live, int *trim_head, int *trim_tail, gimple *stmt) { - /* We use sbitmaps biased such that ref->offset is bit zero and the bitmap - extends through ref->size. So we know that in the original bitmap - bits 0..ref->size were true. We don't actually need the bitmap, just - the REF to compute the trims. */ + *trim_head = 0; + *trim_tail = 0; + + /* We use bitmaps biased such that ref->offset is contained in bit zero and + the bitmap extends through ref->max_size, so we know that in the original + bitmap bits 0 .. ref->max_size were true. But we need to check that this + covers the bytes of REF exactly. */ + const unsigned int align = known_alignment (ref->offset); + if ((align > 0 && align < BITS_PER_UNIT) + || !known_eq (ref->size, ref->max_size)) + return; /* Now identify how much, if any of the tail we can chop off. */ HOST_WIDE_INT const_size; @@ -444,8 +451,6 @@ compute_trims (ao_ref *ref, sbitmap live, int *trim_head, int *trim_tail, last_orig) <= 0) *trim_tail = 0; } - else - *trim_tail = 0; /* Identify how much, if any of the head we can chop off. */ int first_orig = 0; @@ -503,8 +508,7 @@ compute_trims (ao_ref *ref, sbitmap live, int *trim_head, int *trim_tail, } } - if ((*trim_head || *trim_tail) - && dump_file && (dump_flags & TDF_DETAILS)) + if ((*trim_head || *trim_tail) && dump_file && (dump_flags & TDF_DETAILS)) { fprintf (dump_file, " Trimming statement (head = %d, tail = %d): ", *trim_head, *trim_tail); @@ -513,12 +517,12 @@ compute_trims (ao_ref *ref, sbitmap live, int *trim_head, int *trim_tail, } } -/* STMT initializes an object from COMPLEX_CST where one or more of the - bytes written may be dead stores. REF is a representation of the - memory written. LIVE is the bitmap of stores that are actually live. +/* STMT initializes an object from COMPLEX_CST where one or more of the bytes + written may be dead stores. REF is a representation of the memory written. + LIVE is the bitmap of stores to REF that are still live. - Attempt to rewrite STMT so that only the real or imaginary part of - the object is actually stored. */ + Attempt to rewrite STMT so that only the real or the imaginary part of the + object is actually stored. */ static void maybe_trim_complex_store (ao_ref *ref, sbitmap live, gimple *stmt) @@ -554,11 +558,10 @@ maybe_trim_complex_store (ao_ref *ref, sbitmap live, gimple *stmt) } /* STMT initializes an object using a CONSTRUCTOR where one or more of the - bytes written are dead stores. ORIG is the bitmap of bytes stored by - STMT. LIVE is the bitmap of stores that are actually live. + bytes written are dead stores. REF is a representation of the memory + written. LIVE is the bitmap of stores to REF that are still live. - Attempt to rewrite STMT so that only the real or imaginary part of - the object is actually stored. + Attempt to rewrite STMT so that it writes fewer memory locations. The most common case for getting here is a CONSTRUCTOR with no elements being used to zero initialize an object. We do not try to handle other @@ -780,9 +783,9 @@ maybe_trim_memstar_call (ao_ref *ref, sbitmap live, gimple *stmt) } } -/* STMT is a memory write where one or more bytes written are dead - stores. ORIG is the bitmap of bytes stored by STMT. LIVE is the - bitmap of stores that are actually live. +/* STMT is a memory write where one or more bytes written are dead stores. + REF is a representation of the memory written. LIVE is the bitmap of + stores to REF that are still live. Attempt to rewrite STMT so that it writes fewer memory locations. Right now we only support trimming at the start or end of the memory region. -- cgit v1.1 From 15d1dae0d4d1be88d28ad7578a60fd3e36de36d8 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Tue, 27 Feb 2024 18:41:24 +0100 Subject: i386: psrlq is not used for PERM [PR113871] Also handle V2BF mode. PR target/113871 gcc/ChangeLog: * config/i386/mmx.md (V248FI): Add V2BF mode. (V24FI_32): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr113871-5a.c: New test. * gcc.target/i386/pr113871-5b.c: New test. --- gcc/config/i386/mmx.md | 4 ++-- gcc/testsuite/gcc.target/i386/pr113871-5a.c | 19 +++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr113871-5b.c | 19 +++++++++++++++++++ 3 files changed, 40 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr113871-5a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr113871-5b.c (limited to 'gcc') diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 075309c..2856ae6 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -85,9 +85,9 @@ (define_mode_iterator V24FI [V2SF V2SI V4HF V4HI]) -(define_mode_iterator V248FI [V2SF V2SI V4HF V4HI V8QI]) +(define_mode_iterator V248FI [V2SF V2SI V4HF V4BF V4HI V8QI]) -(define_mode_iterator V24FI_32 [V2HF V2HI V4QI]) +(define_mode_iterator V24FI_32 [V2HF V2BF V2HI V4QI]) ;; Mapping from integer vector mode to mnemonic suffix (define_mode_attr mmxvecsize diff --git a/gcc/testsuite/gcc.target/i386/pr113871-5a.c b/gcc/testsuite/gcc.target/i386/pr113871-5a.c new file mode 100644 index 0000000..25ab82a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113871-5a.c @@ -0,0 +1,19 @@ +/* PR target/113871 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +typedef __bf16 vect64 __attribute__((vector_size(8))); + +void f (vect64 *a) +{ + *a = __builtin_shufflevector(*a, (vect64){0}, 1, 2, 3, 4); +} + +/* { dg-final { scan-assembler "psrlq" } } */ + +void g(vect64 *a) +{ + *a = __builtin_shufflevector((vect64){0}, *a, 3, 4, 5, 6); +} + +/* { dg-final { scan-assembler "psllq" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr113871-5b.c b/gcc/testsuite/gcc.target/i386/pr113871-5b.c new file mode 100644 index 0000000..363a0f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113871-5b.c @@ -0,0 +1,19 @@ +/* PR target/113871 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef __bf16 vect32 __attribute__((vector_size(4))); + +void f (vect32 *a) +{ + *a = __builtin_shufflevector(*a, (vect32){0}, 1, 2); +} + +/* { dg-final { scan-assembler "psrld" } } */ + +void g(vect32 *a) +{ + *a = __builtin_shufflevector((vect32){0}, *a, 1, 2); +} + +/* { dg-final { scan-assembler "pslld" } } */ -- cgit v1.1 From 939439a90f234f9e70d30240bf5c227eebe2b43f Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Tue, 27 Feb 2024 14:49:42 -0500 Subject: analyzer: use correct format code for string literal indices [PR110483,PR111802] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On e.g. gcc211 the use of "%li" with unsigned HOST_WIDE_INT led to this warning: ../../src/gcc/analyzer/access-diagram.cc: In member function ‘void ana::string_literal_spatial_item::add_column_for_byte(text_art::table&, const ana::bit_to_table_map&, text_art::style_manager&, ana::byte_offset_t, ana::byte_offset_t, int, int) const’: ../../src/gcc/analyzer/access-diagram.cc:1909:40: warning: format ‘%li’ expects argument of type ‘long int’, but argument 3 has type ‘long long unsigned int’ [-Wformat=] byte_idx_within_string.ulow ())); ^ and to all values being erroneously printed as "0". Fixed thusly. gcc/analyzer/ChangeLog: PR analyzer/110483 PR analyzer/111802 * access-diagram.cc (string_literal_spatial_item::add_column_for_byte): Use %wu for printing unsigned HOST_WIDE_INT. Signed-off-by: David Malcolm --- gcc/analyzer/access-diagram.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/analyzer/access-diagram.cc b/gcc/analyzer/access-diagram.cc index 9555ee8..24d203f 100644 --- a/gcc/analyzer/access-diagram.cc +++ b/gcc/analyzer/access-diagram.cc @@ -1905,7 +1905,7 @@ private: const table::rect_t idx_table_rect = btm.get_table_rect (&m_string_reg, bytes, byte_idx_table_y, 1); t.set_cell_span (idx_table_rect, - fmt_styled_string (sm, "[%li]", + fmt_styled_string (sm, "[%wu]", byte_idx_within_string.ulow ())); } -- cgit v1.1 From 6309ad25c6dc22bf1d47990eedb8a5bec5d7315a Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Wed, 28 Feb 2024 00:16:42 +0000 Subject: Daily bump. --- gcc/ChangeLog | 47 +++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 15 +++++++++++++++ gcc/testsuite/ChangeLog | 41 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 104 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f2c21f3..3fde83d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,50 @@ +2024-02-27 Uros Bizjak + + PR target/113871 + * config/i386/mmx.md (V248FI): Add V2BF mode. + (V24FI_32): Ditto. + +2024-02-27 Eric Botcazou + + * tree-ssa-dse.cc (compute_trims): Fix description. Return early + if either ref->offset is not byte aligned or ref->size is not known + to be equal to ref->max_size. + (maybe_trim_complex_store): Fix description. + (maybe_trim_constructor_store): Likewise. + (maybe_trim_partially_dead_store): Likewise. + +2024-02-27 Richard Earnshaw + + * config/arm/mmintrin.h: Warn if this header is included without + defining __ENABLE_DEPRECATED_IWMMXT. + +2024-02-27 Richard Biener + + PR tree-optimization/114074 + * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL. + * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs. + Handle poly vs. non-poly multiplication correctly with respect + to undefined behavior on overflow. + +2024-02-27 Jakub Jelinek + + PR rtl-optimization/114044 + * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use + DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN. + * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS, + expand_PARITY): Declare. + * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ, + expand_CTZ, expand_FFS, expand_PARITY): New functions. + (expand_POPCOUNT): Use expand_bitquery. + +2024-02-27 Richard Biener + + PR tree-optimization/114081 + * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): + Perform manual dominator update for prologue peeling. + (vect_do_peeling): Properly update dominators after adding the + prologue-around guard. + 2024-02-26 Georg-Johann Lay * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args) diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index abc12bc..4b3cebb 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240227 +20240228 diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index 61b7aa1..98fa45c 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,18 @@ +2024-02-27 David Malcolm + + PR analyzer/110483 + PR analyzer/111802 + * access-diagram.cc + (string_literal_spatial_item::add_column_for_byte): Use %wu for + printing unsigned HOST_WIDE_INT. + +2024-02-27 David Malcolm + + PR analyzer/111881 + * constraint-manager.cc (bound::ensure_closed): Assert that + m_constant has integral type. + (range::add_bound): Bail out on floating point constants. + 2024-02-21 David Malcolm PR analyzer/113999 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 025027d..5b73bbb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,44 @@ +2024-02-27 Uros Bizjak + + PR target/113871 + * gcc.target/i386/pr113871-5a.c: New test. + * gcc.target/i386/pr113871-5b.c: New test. + +2024-02-27 Eric Botcazou + + * gnat.dg/opt104.ads, gnat.dg/opt104.adb: New test. + +2024-02-27 David Malcolm + + PR analyzer/111881 + * c-c++-common/analyzer/conditionals-pr111881.c: New test. + +2024-02-27 Richard Biener + + PR tree-optimization/114074 + * gcc.dg/torture/pr114074.c: New testcase. + * gcc.dg/pr68317.c: Adjust expected location of diagnostic. + * gcc.dg/vect/vect-early-break_119-pr114068.c: Do not expect + loop to be vectorized. + +2024-02-27 Jakub Jelinek + + PR rtl-optimization/114044 + * gcc.dg/bitint-95.c: New test. + +2024-02-27 Richard Biener + + PR tree-optimization/114081 + * gcc.dg/vect/vect-early-break_121-pr114081.c: New testcase. + +2024-02-27 Rainer Orth + + PR ipa/70582 + * gcc.dg/attr-weakref-1.c (dg-additional-options): Define + SOLARIS_X86_AS as appropriate. + (lv3, Wv3a, pv3a): Wrap in !SOLARIS_X86_AS. + (main): Likewise for chk (pv3a). + 2024-02-26 Harald Anlauf PR fortran/114012 -- cgit v1.1 From 615b62aada6cc42759e5c43e196dab6c524925d6 Mon Sep 17 00:00:00 2001 From: Nathaniel Shead Date: Wed, 28 Feb 2024 11:20:53 +1100 Subject: c++: Revert deferring emission of inline variables [PR114013] This is a (partial) reversion of r14-8987-gdd9d14f7d53 to return to eagerly emitting inline variables to the middle-end when they are declared. 'import_export_decl' will still continue to accept them, as allowing this is a pure extension and doesn't seem to cause issues with modules, but otherwise deferring the emission of inline variables appears to cause issues on some targets and prevents some code using inline variable templates from correctly linking. There might be a more targetted way to support this, but due to the complexity of handling linkage and emission I'd prefer to wait till GCC 15 to explore our options. PR c++/113970 PR c++/114013 gcc/cp/ChangeLog: * decl.cc (make_rtl_for_nonlocal_decl): Don't defer inline variables. gcc/testsuite/ChangeLog: * g++.dg/cpp1z/inline-var10.C: New test. Signed-off-by: Nathaniel Shead --- gcc/cp/decl.cc | 4 ---- gcc/testsuite/g++.dg/cpp1z/inline-var10.C | 33 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp1z/inline-var10.C (limited to 'gcc') diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc index e47f694..d19d09a 100644 --- a/gcc/cp/decl.cc +++ b/gcc/cp/decl.cc @@ -7954,10 +7954,6 @@ make_rtl_for_nonlocal_decl (tree decl, tree init, const char* asmspec) && DECL_IMPLICIT_INSTANTIATION (decl)) defer_p = 1; - /* Defer vague-linkage variables. */ - if (DECL_INLINE_VAR_P (decl)) - defer_p = 1; - /* If we're not deferring, go ahead and assemble the variable. */ if (!defer_p) rest_of_decl_compilation (decl, toplev, at_eof); diff --git a/gcc/testsuite/g++.dg/cpp1z/inline-var10.C b/gcc/testsuite/g++.dg/cpp1z/inline-var10.C new file mode 100644 index 0000000..8a19855 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1z/inline-var10.C @@ -0,0 +1,33 @@ +// PR c++/114013 +// { dg-do link { target c++17 } } + +struct S { int a, b; }; + +template +constexpr struct S var[8] = {}; + +template <> +constexpr inline struct S var<6>[8] = { + { 1, 1 }, { 2, 0 }, { 3, 1 }, { 4, 0 }, + { 5, 1 }, { 6, 0 }, { 7, 1 }, { 8, 0 } +}; + +[[gnu::noipa]] void +foo (S) +{ +} + +template +void +bar (int x) +{ + foo (var[x]); +} + +volatile int x; + +int +main () +{ + bar <6> (x); +} -- cgit v1.1 From dc30e24b76d570e13a71567a38f7594b104736bf Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 28 Feb 2024 09:26:51 +0100 Subject: testsuite: Add c23-stdarg-4.c test variant where all functions return large struct I think we have no coverage for the case where structure_value_addr_parm and TYPE_NO_NAMED_ARGS_STDARG_P are both true. The if (type_arg_types != 0) n_named_args = (list_length (type_arg_types) /* Count the struct value address, if it is passed as a parm. */ + structure_value_addr_parm); else if (TYPE_NO_NAMED_ARGS_STDARG_P (funtype)) n_named_args = 0; else /* If we know nothing, treat all args as named. */ n_named_args = num_actuals; code should probably have n_named_args = structure_value_addr_parm; instead of n_named_args = 0;, this testcase is an attempt to see if it is broken on any target. 2024-02-28 Jakub Jelinek * gcc.dg/c23-stdarg-6.c: New test. --- gcc/testsuite/gcc.dg/c23-stdarg-6.c | 217 ++++++++++++++++++++++++++++++++++++ 1 file changed, 217 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/c23-stdarg-6.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/c23-stdarg-6.c b/gcc/testsuite/gcc.dg/c23-stdarg-6.c new file mode 100644 index 0000000..d5f08d0 --- /dev/null +++ b/gcc/testsuite/gcc.dg/c23-stdarg-6.c @@ -0,0 +1,217 @@ +/* Test C23 variadic functions with no named parameters, or last named + parameter with a declaration not allowed in C17. Execution tests. */ +/* { dg-do run } */ +/* { dg-options "-std=c23 -pedantic-errors" } */ + +#include + +extern void abort (void); +extern void exit (int); +struct s { char c[1000]; }; + +struct s +f (...) +{ + va_list ap; + va_start (ap); + double r = va_arg (ap, int); + r += va_arg (ap, double); + r += va_arg (ap, int); + r += va_arg (ap, double); + va_end (ap); + struct s ret = {}; + ret.c[0] = r; + ret.c[999] = 42; + return ret; +} + +struct s +g (...) +{ + va_list ap; + va_start (ap, random ! ignored, ignored ** text); + for (int i = 0; i < 10; i++) + if (va_arg (ap, double) != i) + abort (); + va_end (ap); + struct s ret = {}; + ret.c[0] = 17; + ret.c[999] = 58; + return ret; +} + +struct s +h1 (register int x, ...) +{ + va_list ap; + va_start (ap); + for (int i = 0; i < 10; i++) + { + if (va_arg (ap, double) != i) + abort (); + i++; + if (va_arg (ap, int) != i) + abort (); + } + va_end (ap); + struct s ret = {}; + ret.c[0] = 32; + ret.c[999] = 95; + return ret; +} + +struct s +h2 (int x(), ...) +{ + va_list ap; + va_start (ap); + for (int i = 0; i < 10; i++) + { + if (va_arg (ap, double) != i) + abort (); + i++; + if (va_arg (ap, int) != i) + abort (); + } + va_end (ap); + struct s ret = {}; + ret.c[0] = 5; + ret.c[999] = 125; + return ret; +} + +struct s +h3 (int x[10], ...) +{ + va_list ap; + va_start (ap); + for (int i = 0; i < 10; i++) + { + if (va_arg (ap, double) != i) + abort (); + i++; + if (va_arg (ap, int) != i) + abort (); + } + va_end (ap); + struct s ret = {}; + ret.c[0] = 8; + ret.c[999] = 12; + return ret; +} + +struct s +h4 (char x, ...) +{ + va_list ap; + va_start (ap); + for (int i = 0; i < 10; i++) + { + if (va_arg (ap, double) != i) + abort (); + i++; + if (va_arg (ap, int) != i) + abort (); + } + va_end (ap); + struct s ret = {}; + ret.c[0] = 18; + ret.c[999] = 28; + return ret; +} + +struct s +h5 (float x, ...) +{ + va_list ap; + va_start (ap); + for (int i = 0; i < 10; i++) + { + if (va_arg (ap, double) != i) + abort (); + i++; + if (va_arg (ap, int) != i) + abort (); + } + va_end (ap); + struct s ret = {}; + ret.c[0] = 38; + ret.c[999] = 48; + return ret; +} + +struct s +h6 (volatile long x, ...) +{ + va_list ap; + va_start (ap); + for (int i = 0; i < 10; i++) + { + if (va_arg (ap, double) != i) + abort (); + i++; + if (va_arg (ap, int) != i) + abort (); + } + va_end (ap); + struct s ret = {}; + ret.c[0] = 58; + ret.c[999] = 68; + return ret; +} + +struct s +h7 (volatile struct s x, ...) +{ + va_list ap; + va_start (ap); + for (int i = 0; i < 10; i++) + { + if (va_arg (ap, double) != i) + abort (); + i++; + if (va_arg (ap, int) != i) + abort (); + } + va_end (ap); + struct s ret = {}; + ret.c[0] = 78; + ret.c[999] = 88; + return ret; +} + +int +main () +{ + struct s x = f (1, 2.0, 3, 4.0); + if (x.c[0] != 10 || x.c[999] != 42) + abort (); + x = g (0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0); + if (x.c[0] != 17 || x.c[999] != 58) + abort (); + x = g (0.0f, 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f); + if (x.c[0] != 17 || x.c[999] != 58) + abort (); + x = h1 (0, 0.0, 1, 2.0, 3, 4.0, 5, 6.0, 7, 8.0, 9); + if (x.c[0] != 32 || x.c[999] != 95) + abort (); + x = h2 (0, 0.0, 1, 2.0, 3, 4.0, 5, 6.0, 7, 8.0, 9); + if (x.c[0] != 5 || x.c[999] != 125) + abort (); + x = h3 (0, 0.0, 1, 2.0, 3, 4.0, 5, 6.0, 7, 8.0, 9); + if (x.c[0] != 8 || x.c[999] != 12) + abort (); + x = h4 (0, 0.0, 1, 2.0, 3, 4.0, 5, 6.0, 7, 8.0, 9); + if (x.c[0] != 18 || x.c[999] != 28) + abort (); + x = h5 (0, 0.0, 1, 2.0, 3, 4.0, 5, 6.0, 7, 8.0, 9); + if (x.c[0] != 38 || x.c[999] != 48) + abort (); + x = h6 (0, 0.0, 1, 2.0, 3, 4.0, 5, 6.0, 7, 8.0, 9); + if (x.c[0] != 58 || x.c[999] != 68) + abort (); + x = h7 ((struct s) {}, 0.0, 1, 2.0, 3, 4.0, 5, 6.0, 7, 8.0, 9); + if (x.c[0] != 78 || x.c[999] != 88) + abort (); + exit (0); +} -- cgit v1.1 From cc383e9702897dd783657ea3dce4aecf48318441 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 28 Feb 2024 09:40:15 +0100 Subject: gimple-fold: Use bitwise vector types rather than barely supported huge integral types in memcpy etc. folding [PR113988] The following patch changes the memcpy etc. folding to use bitwise vector types rather than huge INTEGER_TYPEs for copying of > MAX_FIXED_MODE_SIZE lengths. The problem with the huge INTEGER_TYPEs is that they aren't supported very much, usually there are just optabs to handle moves of them, perhaps misaligned moves and that is it, so they pose problems e.g. to BITINT_TYPE lowering. 2024-02-28 Jakub Jelinek PR tree-optimization/113988 * stor-layout.h (bitwise_mode_for_size): Declare. * stor-layout.cc (bitwise_mode_for_size): New function. * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it. Use bitwise_type_for_mode instead of build_nonstandard_integer_type. Use BITS_PER_UNIT instead of 8. * gcc.dg/bitint-91.c: New test. --- gcc/gimple-fold.cc | 11 +++++++---- gcc/stor-layout.cc | 26 ++++++++++++++++++++++++++ gcc/stor-layout.h | 2 ++ gcc/testsuite/gcc.dg/bitint-91.c | 38 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/bitint-91.c (limited to 'gcc') diff --git a/gcc/gimple-fold.cc b/gcc/gimple-fold.cc index 5191102..d2a0f6d 100644 --- a/gcc/gimple-fold.cc +++ b/gcc/gimple-fold.cc @@ -995,9 +995,12 @@ gimple_fold_builtin_memory_op (gimple_stmt_iterator *gsi, if (warning != OPT_Wrestrict) return false; - scalar_int_mode mode; - if (int_mode_for_size (ilen * 8, 0).exists (&mode) - && GET_MODE_SIZE (mode) * BITS_PER_UNIT == ilen * 8 + scalar_int_mode imode; + machine_mode mode; + if (int_mode_for_size (ilen * BITS_PER_UNIT, 0).exists (&imode) + && bitwise_mode_for_size (ilen + * BITS_PER_UNIT).exists (&mode) + && known_eq (GET_MODE_BITSIZE (mode), ilen * BITS_PER_UNIT) /* If the destination pointer is not aligned we must be able to emit an unaligned store. */ && (dest_align >= GET_MODE_ALIGNMENT (mode) @@ -1005,7 +1008,7 @@ gimple_fold_builtin_memory_op (gimple_stmt_iterator *gsi, || (optab_handler (movmisalign_optab, mode) != CODE_FOR_nothing))) { - tree type = build_nonstandard_integer_type (ilen * 8, 1); + tree type = bitwise_type_for_mode (mode); tree srctype = type; tree desttype = type; if (src_align < GET_MODE_ALIGNMENT (mode)) diff --git a/gcc/stor-layout.cc b/gcc/stor-layout.cc index 4cf2491..e34be19 100644 --- a/gcc/stor-layout.cc +++ b/gcc/stor-layout.cc @@ -476,6 +476,32 @@ bitwise_type_for_mode (machine_mode mode) return inner_type; } +/* Find a mode that can be used for efficient bitwise operations on SIZE + bits, if one exists. */ + +opt_machine_mode +bitwise_mode_for_size (poly_uint64 size) +{ + if (known_le (size, (unsigned int) MAX_FIXED_MODE_SIZE)) + return mode_for_size (size, MODE_INT, true); + + machine_mode mode, ret = VOIDmode; + FOR_EACH_MODE_FROM (mode, MIN_MODE_VECTOR_INT) + if (known_eq (GET_MODE_BITSIZE (mode), size) + && (ret == VOIDmode || GET_MODE_INNER (mode) == QImode) + && have_regs_of_mode[mode] + && targetm.vector_mode_supported_p (mode)) + { + if (GET_MODE_INNER (mode) == QImode) + return mode; + else if (ret == VOIDmode) + ret = mode; + } + if (ret != VOIDmode) + return ret; + return opt_machine_mode (); +} + /* Find a mode that is suitable for representing a vector with NUNITS elements of mode INNERMODE, if one exists. The returned mode can be either an integer mode or a vector mode. */ diff --git a/gcc/stor-layout.h b/gcc/stor-layout.h index 7fbc312..096ca81 100644 --- a/gcc/stor-layout.h +++ b/gcc/stor-layout.h @@ -102,6 +102,8 @@ extern opt_machine_mode mode_for_size_tree (const_tree, enum mode_class, int); extern tree bitwise_type_for_mode (machine_mode); +extern opt_machine_mode bitwise_mode_for_size (poly_uint64); + /* Given a VAR_DECL, PARM_DECL or RESULT_DECL, clears the results of a previous call to layout_decl and calls it again. */ extern void relayout_decl (tree); diff --git a/gcc/testsuite/gcc.dg/bitint-91.c b/gcc/testsuite/gcc.dg/bitint-91.c new file mode 100644 index 0000000..ede6f68 --- /dev/null +++ b/gcc/testsuite/gcc.dg/bitint-91.c @@ -0,0 +1,38 @@ +/* PR tree-optimization/113988 */ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-mavx512f" { target i?86-*-* x86_64-*-* } } */ + +int i; + +#if __BITINT_MAXWIDTH__ >= 256 +void +foo (void *p, _BitInt(256) x) +{ + __builtin_memcpy (p, &x, sizeof x); +} + +_BitInt(256) +bar (void *p, _BitInt(256) x) +{ + _BitInt(246) y = x + 1; + __builtin_memcpy (p, &y, sizeof y); + return x; +} +#endif + +#if __BITINT_MAXWIDTH__ >= 512 +void +baz (void *p, _BitInt(512) x) +{ + __builtin_memcpy (p, &x, sizeof x); +} + +_BitInt(512) +qux (void *p, _BitInt(512) x) +{ + _BitInt(512) y = x + 1; + __builtin_memcpy (p, &y, sizeof y); + return x; +} +#endif -- cgit v1.1 From d6479050ecef10fd5e67b4da989229e4cfac53ee Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 28 Feb 2024 09:59:45 +0100 Subject: graphite: Fix non-INTEGER_TYPE integral comparison handling [PR114041] The following testcases are miscompiled, because graphite ignores boolean, enumerated or _BitInt comparisons, rewrites the code as if the comparisons were always true or always false. The INTEGER_TYPE checks were initially added in r6-2239 but at that point it was both in add_conditions_to_domain and in parameter_index_in_region. Later on the check was also added to stmt_simple_for_scop_p, and finally r8-3931 changed the stmt_simple_for_scop_p check to INTEGRAL_TYPE_P and turned the parameter_index_in_region -> assign_parameter_index_in_region into INTEGRAL_TYPE_P assertion, but the add_conditions_to_domain check for INTEGER_TYPE remained. The following patch uses INTEGRAL_TYPE_P to complete the change. 2024-02-28 Jakub Jelinek PR tree-optimization/114041 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for INTEGRAL_TYPE_P check rather than INTEGER_TYPE. * gcc.dg/graphite/run-id-pr114041-1.c: New test. * gcc.dg/graphite/run-id-pr114041-2.c: New test. --- gcc/graphite-sese-to-poly.cc | 5 +++-- gcc/testsuite/gcc.dg/graphite/run-id-pr114041-1.c | 23 +++++++++++++++++++ gcc/testsuite/gcc.dg/graphite/run-id-pr114041-2.c | 27 +++++++++++++++++++++++ 3 files changed, 53 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/graphite/run-id-pr114041-1.c create mode 100644 gcc/testsuite/gcc.dg/graphite/run-id-pr114041-2.c (limited to 'gcc') diff --git a/gcc/graphite-sese-to-poly.cc b/gcc/graphite-sese-to-poly.cc index 547d661..4f614a3 100644 --- a/gcc/graphite-sese-to-poly.cc +++ b/gcc/graphite-sese-to-poly.cc @@ -391,8 +391,9 @@ add_conditions_to_domain (poly_bb_p pbb) { case GIMPLE_COND: { - /* Don't constrain on anything else than INTEGER_TYPE. */ - if (TREE_CODE (TREE_TYPE (gimple_cond_lhs (stmt))) != INTEGER_TYPE) + /* Don't constrain on anything else than INTEGRAL_TYPE_P. */ + tree cmp_type = TREE_TYPE (gimple_cond_lhs (stmt)); + if (!INTEGRAL_TYPE_P (cmp_type)) break; gcond *cond_stmt = as_a (stmt); diff --git a/gcc/testsuite/gcc.dg/graphite/run-id-pr114041-1.c b/gcc/testsuite/gcc.dg/graphite/run-id-pr114041-1.c new file mode 100644 index 0000000..1ffdd74 --- /dev/null +++ b/gcc/testsuite/gcc.dg/graphite/run-id-pr114041-1.c @@ -0,0 +1,23 @@ +/* PR tree-optimization/114041 */ +/* { dg-require-effective-target bitint } */ +/* { dg-options "-O -fgraphite-identity" } */ + +unsigned a[24], b[24]; + +__attribute__((noipa)) unsigned +foo (unsigned _BitInt(8) x) +{ + for (int i = 0; i < 24; ++i) + a[i] = i; + unsigned e = __builtin_stdc_bit_ceil (x); + for (int i = 0; i < 24; ++i) + b[i] = i; + return e; +} + +int +main () +{ + if (foo (0) != 1) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.dg/graphite/run-id-pr114041-2.c b/gcc/testsuite/gcc.dg/graphite/run-id-pr114041-2.c new file mode 100644 index 0000000..c935255 --- /dev/null +++ b/gcc/testsuite/gcc.dg/graphite/run-id-pr114041-2.c @@ -0,0 +1,27 @@ +/* PR tree-optimization/114041 */ +/* { dg-options "-O -fgraphite-identity" } */ + +unsigned a[24], b[24]; +enum E { E0 = 0, E1 = 1, E42 = 42, E56 = 56 }; + +__attribute__((noipa)) unsigned +foo (enum E x) +{ + for (int i = 0; i < 24; ++i) + a[i] = i; + unsigned e; + if (x >= E42) + e = __builtin_clz ((unsigned) x); + else + e = 42; + for (int i = 0; i < 24; ++i) + b[i] = i; + return e; +} + +int +main () +{ + if (foo (E1) != 42 || foo (E56) != __SIZEOF_INT__ * __CHAR_BIT__ - 6) + __builtin_abort (); +} -- cgit v1.1 From 82ebfd35da49e5df87da132a7b8c41baeebc57b4 Mon Sep 17 00:00:00 2001 From: Juergen Christ Date: Mon, 19 Feb 2024 10:10:35 +0100 Subject: Only emulate integral vectors. The emulation via word mode tries to perform integer arithmetic on floating point values instead of floating point arithmetic. This leads to mis-compilations. Failure occured on s390x on these existing test cases: gcc.dg/vect/tsvc/vect-tsvc-s112.c gcc.dg/vect/tsvc/vect-tsvc-s113.c gcc.dg/vect/tsvc/vect-tsvc-s119.c gcc.dg/vect/tsvc/vect-tsvc-s121.c gcc.dg/vect/tsvc/vect-tsvc-s131.c gcc.dg/vect/tsvc/vect-tsvc-s132.c gcc.dg/vect/tsvc/vect-tsvc-s2233.c gcc.dg/vect/tsvc/vect-tsvc-s421.c gcc.dg/vect/vect-alias-check-14.c gcc.target/s390/vector/partial/s390-vec-length-epil-run-1.c gcc.target/s390/vector/partial/s390-vec-length-epil-run-3.c gcc.target/s390/vector/partial/s390-vec-length-full-run-3.c gcc/ChangeLog: PR tree-optimization/114075 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating point vectors Signed-off-by: Juergen Christ --- gcc/tree-vect-stmts.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc index 1dbe111..be0e1a9 100644 --- a/gcc/tree-vect-stmts.cc +++ b/gcc/tree-vect-stmts.cc @@ -6756,7 +6756,8 @@ vectorizable_operation (vec_info *vinfo, those through even when the mode isn't word_mode. For ops we have to lower the lowering code assumes we are dealing with word_mode. */ - if ((((code == PLUS_EXPR || code == MINUS_EXPR || code == NEGATE_EXPR) + if (!INTEGRAL_TYPE_P (TREE_TYPE (vectype)) + || (((code == PLUS_EXPR || code == MINUS_EXPR || code == NEGATE_EXPR) || !target_support_p) && maybe_ne (GET_MODE_SIZE (vec_mode), UNITS_PER_WORD)) /* Check only during analysis. */ -- cgit v1.1 From db465230cccf0844e803dd6701756054fe97244a Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 28 Feb 2024 11:49:29 +0100 Subject: testsuite: Add testcase for recently fixed PR [PR114075] This adds testcase from PR114075 which has been fixed by the r14-9205 change on s390x-linux with -march=z13. 2024-02-28 Jakub Jelinek PR tree-optimization/114075 * gcc.dg/gomp/pr114075.c: New test. --- gcc/testsuite/gcc.dg/gomp/pr114075.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/gomp/pr114075.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/gomp/pr114075.c b/gcc/testsuite/gcc.dg/gomp/pr114075.c new file mode 100644 index 0000000..c5c9cda --- /dev/null +++ b/gcc/testsuite/gcc.dg/gomp/pr114075.c @@ -0,0 +1,31 @@ +/* PR tree-optimization/114075 */ +/* { dg-do run } */ +/* { dg-options "-O2 -fopenmp-simd -Wno-psabi" } */ + +typedef float V __attribute__((__vector_size__ (16))); + +__attribute__((__always_inline__)) inline static float +foo (V a) +{ + float r = 0; +#pragma omp simd reduction(+:r) + for (unsigned long i = 0; i < (sizeof (a) / sizeof (float)); i++) + r += a[i]; + return r; +} + +int +main () +{ + static const struct { V a; float r; } t[] = { + { (V) { -17.0f, -18.0f, -19.0f, 20.0f }, -34.0f }, + { (V) { 18.5f, 19.125f, 20.5f, -38.25f }, 19.875f }, + { (V) { -8.25f, 16.75f, -42.5f, -18.75f }, -52.75f } + }; + for (unsigned long i = 0; i < (sizeof (t) / sizeof (t[0])); i++) + { + float r = foo (t[i].a); + if (r != t[i].r) + __builtin_abort (); + } +} -- cgit v1.1 From 6864a2aa78a893afea26eb8fc1aa4b7ade3e940f Mon Sep 17 00:00:00 2001 From: Rainer Orth Date: Wed, 28 Feb 2024 11:55:47 +0100 Subject: testsuite: Fix gcc.dg/tree-ssa/builtin-snprintf-6.c XPASS on i?86 -m64 [PR91567] gcc.dg/tree-ssa/builtin-snprintf-6.c currently XPASSes on i?86-*-* configurations with -m64: XPASS: gcc.dg/tree-ssa/builtin-snprintf-6.c scan-tree-dump-times optimized "Function test_assign_aggregate" 1 (seen e.g. on i386-pc-solaris2.11, i686-pc-linux-gnu, or i386-apple-darwin*). The problem is that the xfail only handles x86_64, ignoring that i?86 configurations can also be multilibbed. This patch fixes the by handling both forms alike. Tested on i386-pc-solaris2.11, amd64-pc-solaris2.11, sparc-sun-solaris2.11, and sparcv9-sun-solaris2.11. 2024-02-28 Rainer Orth gcc/testsuite: PR tree-optimization/91567 * gcc.dg/tree-ssa/builtin-snprintf-6.c (scan-tree-dump-times): Treat i?86-*-* like x86_64-*-*. --- gcc/testsuite/gcc.dg/tree-ssa/builtin-snprintf-6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/tree-ssa/builtin-snprintf-6.c b/gcc/testsuite/gcc.dg/tree-ssa/builtin-snprintf-6.c index df0e6b7..df09c81 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/builtin-snprintf-6.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/builtin-snprintf-6.c @@ -91,7 +91,7 @@ void test_assign_aggregate (void) T (5, "123456", "s=%.*s", 3, &s.a[2]); } -/* { dg-final { scan-tree-dump-times "Function test_assign_aggregate" 1 "optimized" { xfail { { ! x86_64-*-* } || { ilp32 } } } } } */ +/* { dg-final { scan-tree-dump-times "Function test_assign_aggregate" 1 "optimized" { xfail { { ! { i?86-*-* x86_64-*-* } } || { ilp32 } } } } } */ #endif /* x86_64 */ -- cgit v1.1 From 92f07eb406612fa341dc33d9d6e4f3781dc09452 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 28 Feb 2024 12:09:04 +0100 Subject: testsuite: XFAIL ssa-sink-18.c also on powerpc64 [PR111462] powerpc64-linux apparently (not very surprisingly) behaves the same way as powerpc64le-linux and has 4 sunk statements rather than 5, so we should xfail it on powerpc64*-*-* rather than just powerpc64le-*-*. powerpc-linux has 3 sunk statements, but the scan pattern is done for lp64 only as the comment explains. 2024-02-28 Jakub Jelinek PR testsuite/111462 * gcc.dg/tree-ssa/ssa-sink-18.c: XFAIL also on powerpc64. --- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c index b199df2..3615cec 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c @@ -213,6 +213,6 @@ compute_on_bytes (uint8_t *in_data, int in_len, uint8_t *out_data, int out_len) expected, so this case is restricted to lp64 only so far. This different ivopts choice affects riscv64 as well, probably because it also lacks base+index addressing modes, so the ip[len] address computation can't be - made from the IV computation above. powerpc64le similarly is affected. */ + made from the IV computation above. powerpc64{,le} similarly is affected. */ - /* { dg-final { scan-tree-dump-times "Sunk statements: 5" 1 "sink2" { target lp64 xfail { riscv64-*-* powerpc64le-*-* hppa*64*-*-* } } } } */ + /* { dg-final { scan-tree-dump-times "Sunk statements: 5" 1 "sink2" { target lp64 xfail { riscv64-*-* powerpc64*-*-* hppa*64*-*-* } } } } */ -- cgit v1.1 From c841144a94363ff26e40ab3f26b14702c32987a8 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 28 Feb 2024 12:37:07 +0100 Subject: tree-optimization/114121 - wrong VN with context sensitive range info When VN ends up exploiting range-info specifying the ao_ref offset and max_size we have to make sure to reflect this in the hashtable entry for the recorded expression. The PR113831 fix handled the case where we can encode this in the operands themselves but this bug shows the issue is more widespread. So instead of altering the operands the following instead records this extra info that's possibly used, only throwing it away when the value-numbering didn't come up with a non-VARYING value which is an important detail to preserve CSE as opposed to constant folding which is where all cases currently known popped up. With this the original PR113831 fix can be reverted. PR tree-optimization/114121 * tree-ssa-sccvn.h (vn_reference_s::offset, vn_reference_s::max_size): New fields. (vn_reference_insert_pieces): Adjust prototype. * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size. * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and size, allow using "don't know" state. (vn_walk_cb_data::finish): Pass along offset/max_size. (vn_reference_lookup_or_insert_for_pieces): Take offset and max_size as argument and use it. (vn_reference_lookup_3): Properly adjust offset and max_size according to the adjusted ao_ref. (vn_reference_lookup_pieces): Initialize offset and max_size. (vn_reference_lookup): Likewise. (vn_reference_lookup_call): Likewise. (vn_reference_insert): Likewise. (visit_reference_op_call): Likewise. (vn_reference_insert_pieces): Take offset and max_size as argument and use it. * gcc.dg/torture/pr114121.c: New testcase. --- gcc/testsuite/gcc.dg/torture/pr114121.c | 35 +++++++++++++++++++++ gcc/tree-ssa-pre.cc | 5 +-- gcc/tree-ssa-sccvn.cc | 55 ++++++++++++++++++++++++++++++--- gcc/tree-ssa-sccvn.h | 3 ++ 4 files changed, 91 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/torture/pr114121.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/torture/pr114121.c b/gcc/testsuite/gcc.dg/torture/pr114121.c new file mode 100644 index 0000000..9a6ddf2 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr114121.c @@ -0,0 +1,35 @@ +/* { dg-do run { target bitint } } */ + +#if __BITINT_MAXWIDTH__ >= 256 +unsigned a, b, c, d, e; +unsigned _BitInt(256) f; + +__attribute__((noipa)) unsigned short +bswap16 (int t) +{ + return __builtin_bswap16 (t); +} + +void +foo (unsigned z, unsigned _BitInt(512) y, unsigned *r) +{ + unsigned t = __builtin_sub_overflow_p (0, y << 509, f); + z *= bswap16 (t); + d = __builtin_sub_overflow_p (c, 3, (unsigned _BitInt(512)) 0); + unsigned q = z + c + b; + unsigned short n = q >> (8 + a); + *r = b + e + n; +} +#endif + +int +main () +{ +#if __BITINT_MAXWIDTH__ >= 256 + unsigned x; + foo (8, 2, &x); + if (x != 8) + __builtin_abort (); +#endif + return 0; +} diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc index d29214d..75217f5 100644 --- a/gcc/tree-ssa-pre.cc +++ b/gcc/tree-ssa-pre.cc @@ -1666,8 +1666,9 @@ phi_translate_1 (bitmap_set_t dest, if (!newoperands.exists ()) newoperands = operands.copy (); newref = vn_reference_insert_pieces (newvuse, ref->set, - ref->base_set, ref->type, - newoperands, + ref->base_set, + ref->offset, ref->max_size, + ref->type, newoperands, result, new_val_id); newoperands = vNULL; } diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index 2587eb1..a10c00b 100644 --- a/gcc/tree-ssa-sccvn.cc +++ b/gcc/tree-ssa-sccvn.cc @@ -438,7 +438,7 @@ static void init_vn_nary_op_from_pieces (vn_nary_op_t, unsigned int, enum tree_code, tree, tree *); static tree vn_lookup_simplify_result (gimple_match_op *); static vn_reference_t vn_reference_lookup_or_insert_for_pieces - (tree, alias_set_type, alias_set_type, tree, + (tree, alias_set_type, alias_set_type, poly_int64, poly_int64, tree, vec, tree); /* Return whether there is value numbering information for a given SSA name. */ @@ -748,6 +748,8 @@ vn_reference_compute_hash (const vn_reference_t vr1) vn_reference_op_compute_hash (vro, hstate); } } + /* Do not hash vr1->offset or vr1->max_size, we want to get collisions + to be able to identify compatible results. */ result = hstate.end (); /* ??? We would ICE later if we hash instead of adding that in. */ if (vr1->vuse) @@ -772,6 +774,16 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2) if (vr1->vuse != vr2->vuse) return false; + /* The offset/max_size used for the ao_ref during lookup has to be + the same. */ + if (maybe_ne (vr1->offset, vr2->offset) + || maybe_ne (vr1->max_size, vr2->max_size)) + { + /* But nothing known in the prevailing entry is OK to be used. */ + if (maybe_ne (vr1->offset, 0) || known_size_p (vr1->max_size)) + return false; + } + /* If the operands are the same we are done. */ if (vr1->operands == vr2->operands) return true; @@ -2061,6 +2073,7 @@ vn_walk_cb_data::finish (alias_set_type set, alias_set_type base_set, tree val) vec &operands = saved_operands.exists () ? saved_operands : vr->operands; return vn_reference_lookup_or_insert_for_pieces (last_vuse, set, base_set, + vr->offset, vr->max_size, vr->type, operands, val); } @@ -2537,6 +2550,8 @@ static vn_reference_t vn_reference_lookup_or_insert_for_pieces (tree vuse, alias_set_type set, alias_set_type base_set, + poly_int64 offset, + poly_int64 max_size, tree type, vec operands, @@ -2550,15 +2565,18 @@ vn_reference_lookup_or_insert_for_pieces (tree vuse, vr1.type = type; vr1.set = set; vr1.base_set = base_set; + vr1.offset = offset; + vr1.max_size = max_size; vr1.hashcode = vn_reference_compute_hash (&vr1); if (vn_reference_lookup_1 (&vr1, &result)) return result; + if (TREE_CODE (value) == SSA_NAME) value_id = VN_INFO (value)->value_id; else value_id = get_or_alloc_constant_value_id (value); - return vn_reference_insert_pieces (vuse, set, base_set, type, - operands.copy (), value, value_id); + return vn_reference_insert_pieces (vuse, set, base_set, offset, max_size, + type, operands.copy (), value, value_id); } /* Return a value-number for RCODE OPS... either by looking up an existing @@ -3756,6 +3774,8 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void *data_, return (void *)-1; } *ref = r; + vr->offset = r.offset; + vr->max_size = r.max_size; /* Do not update last seen VUSE after translating. */ data->last_vuse_ptr = NULL; @@ -3944,6 +3964,8 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void *data_, if (maybe_ne (ref->size, r.size)) return (void *)-1; *ref = r; + vr->offset = r.offset; + vr->max_size = r.max_size; /* Do not update last seen VUSE after translating. */ data->last_vuse_ptr = NULL; @@ -4008,6 +4030,10 @@ vn_reference_lookup_pieces (tree vuse, alias_set_type set, vr1.type = type; vr1.set = set; vr1.base_set = base_set; + /* We can pretend there's no extra info fed in since the ao_refs offset + and max_size are computed only from the VN reference ops. */ + vr1.offset = 0; + vr1.max_size = -1; vr1.hashcode = vn_reference_compute_hash (&vr1); if ((cst = fully_constant_vn_reference_p (&vr1))) return cst; @@ -4134,6 +4160,8 @@ vn_reference_lookup (tree op, tree vuse, vn_lookup_kind kind, ao_ref_init (&op_ref, op); vr1.set = ao_ref_alias_set (&op_ref); vr1.base_set = ao_ref_base_alias_set (&op_ref); + vr1.offset = 0; + vr1.max_size = -1; vr1.hashcode = vn_reference_compute_hash (&vr1); if (mask == NULL_TREE) if (tree cst = fully_constant_vn_reference_p (&vr1)) @@ -4156,7 +4184,13 @@ vn_reference_lookup (tree op, tree vuse, vn_lookup_kind kind, if (!valueized_anything || !ao_ref_init_from_vn_reference (&r, vr1.set, vr1.base_set, vr1.type, ops_for_ref)) - ao_ref_init (&r, op); + { + ao_ref_init (&r, op); + /* Record the extra info we're getting from the full ref. */ + ao_ref_base (&r); + vr1.offset = r.offset; + vr1.max_size = r.max_size; + } vn_walk_cb_data data (&vr1, r.ref ? NULL_TREE : op, last_vuse_ptr, kind, tbaa_p, mask, redundant_store_removal_p); @@ -4212,6 +4246,8 @@ vn_reference_lookup_call (gcall *call, vn_reference_t *vnresult, vr->punned = false; vr->set = 0; vr->base_set = 0; + vr->offset = 0; + vr->max_size = -1; vr->hashcode = vn_reference_compute_hash (vr); vn_reference_lookup_1 (vr, vnresult); } @@ -4275,6 +4311,10 @@ vn_reference_insert (tree op, tree result, tree vuse, tree vdef) ao_ref_init (&op_ref, op); vr1->set = ao_ref_alias_set (&op_ref); vr1->base_set = ao_ref_base_alias_set (&op_ref); + /* Specifically use an unknown extent here, we're not doing any lookup + and assume the caller didn't either (or it went VARYING). */ + vr1->offset = 0; + vr1->max_size = -1; vr1->hashcode = vn_reference_compute_hash (vr1); vr1->result = TREE_CODE (result) == SSA_NAME ? SSA_VAL (result) : result; vr1->result_vdef = vdef; @@ -4317,7 +4357,8 @@ vn_reference_insert (tree op, tree result, tree vuse, tree vdef) vn_reference_t vn_reference_insert_pieces (tree vuse, alias_set_type set, - alias_set_type base_set, tree type, + alias_set_type base_set, + poly_int64 offset, poly_int64 max_size, tree type, vec operands, tree result, unsigned int value_id) @@ -4334,6 +4375,8 @@ vn_reference_insert_pieces (tree vuse, alias_set_type set, vr1->punned = false; vr1->set = set; vr1->base_set = base_set; + vr1->offset = offset; + vr1->max_size = max_size; vr1->hashcode = vn_reference_compute_hash (vr1); if (result && TREE_CODE (result) == SSA_NAME) result = SSA_VAL (result); @@ -5852,6 +5895,8 @@ visit_reference_op_call (tree lhs, gcall *stmt) vr2->type = vr1.type; vr2->punned = vr1.punned; vr2->set = vr1.set; + vr2->offset = vr1.offset; + vr2->max_size = vr1.max_size; vr2->base_set = vr1.base_set; vr2->hashcode = vr1.hashcode; vr2->result = lhs; diff --git a/gcc/tree-ssa-sccvn.h b/gcc/tree-ssa-sccvn.h index 8ec1de0..82f6f73 100644 --- a/gcc/tree-ssa-sccvn.h +++ b/gcc/tree-ssa-sccvn.h @@ -145,6 +145,8 @@ typedef struct vn_reference_s tree vuse; alias_set_type set; alias_set_type base_set; + poly_int64 offset; + poly_int64 max_size; tree type; unsigned punned : 1; vec operands; @@ -268,6 +270,7 @@ tree vn_reference_lookup (tree, tree, vn_lookup_kind, vn_reference_t *, bool, tree * = NULL, tree = NULL_TREE, bool = false); void vn_reference_lookup_call (gcall *, vn_reference_t *, vn_reference_t); vn_reference_t vn_reference_insert_pieces (tree, alias_set_type, alias_set_type, + poly_int64, poly_int64, tree, vec, tree, unsigned int); void print_vn_reference_ops (FILE *, const vec); -- cgit v1.1 From 5c01ede02a1f9ba1a58ab8d96a73e46e0484d820 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 28 Feb 2024 13:45:57 +0100 Subject: tree-optimization/113831 - revert original fix This reverts the original fix for PR113831 which is better fixed by the PR114121 fix. I've XFAILed instead of removing the PR108355 testcase again. PR tree-optimization/113831 PR tree-optimization/108355 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert PR113831 fix. * gcc.dg/tree-ssa/ssa-fre-104.c: XFAIL. --- gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-104.c | 2 +- gcc/tree-ssa-sccvn.cc | 134 ---------------------------- 2 files changed, 1 insertion(+), 135 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-104.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-104.c index f0f12ef..425c32d 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-104.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-104.c @@ -21,4 +21,4 @@ int main() { *c = &d; } -/* { dg-final { scan-tree-dump-not "foo" "fre1" } } */ +/* { dg-final { scan-tree-dump-not "foo" "fre1" { xfail *-*-* } } } */ diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index a10c00b..88d3b24 100644 --- a/gcc/tree-ssa-sccvn.cc +++ b/gcc/tree-ssa-sccvn.cc @@ -912,8 +912,6 @@ copy_reference_ops_from_ref (tree ref, vec *result) { /* For non-calls, store the information that makes up the address. */ tree orig = ref; - unsigned start = result->length (); - bool seen_variable_array_ref = false; while (ref) { vn_reference_op_s temp; @@ -1000,12 +998,6 @@ copy_reference_ops_from_ref (tree ref, vec *result) tree eltype = TREE_TYPE (TREE_TYPE (TREE_OPERAND (ref, 0))); /* Record index as operand. */ temp.op0 = TREE_OPERAND (ref, 1); - /* When the index is not constant we have to apply the same - logic as get_ref_base_and_extent which eventually uses - global ranges to refine the overall ref extent. Record - we've seen such a case, fixup below. */ - if (TREE_CODE (temp.op0) == SSA_NAME) - seen_variable_array_ref = true; /* Always record lower bounds and element size. */ temp.op1 = array_ref_low_bound (ref); /* But record element size in units of the type alignment. */ @@ -1098,132 +1090,6 @@ copy_reference_ops_from_ref (tree ref, vec *result) else ref = NULL_TREE; } - poly_int64 offset, size, max_size; - tree base; - bool rev; - if (seen_variable_array_ref - && handled_component_p (orig) - && (base = get_ref_base_and_extent (orig, - &offset, &size, &max_size, &rev)) - && known_size_p (max_size) - && known_eq (size, max_size)) - { - poly_int64 orig_offset = offset; - poly_int64 tem; - if (TREE_CODE (base) == MEM_REF - && mem_ref_offset (base).to_shwi (&tem)) - offset += tem * BITS_PER_UNIT; - HOST_WIDE_INT coffset = offset.to_constant (); - /* When get_ref_base_and_extent computes an offset constrained to - a constant position we have to fixup variable array indexes in - the ref to avoid the situation where based on context we'd have - to value-number the same vn_reference ops differently. Make - the vn_reference ops differ by adjusting those indexes to - appropriate constants. */ - poly_int64 off = 0; - bool oob_index = false; - for (unsigned i = result->length (); i > start; --i) - { - auto &op = (*result)[i-1]; - if (flag_checking - && op.opcode == ARRAY_REF - && TREE_CODE (op.op0) == INTEGER_CST) - { - /* The verifier below chokes on inconsistencies of handling - out-of-bound accesses so disable it in that case. */ - tree atype = (*result)[i].type; - if (TREE_CODE (atype) == ARRAY_TYPE) - if (tree dom = TYPE_DOMAIN (atype)) - if ((TYPE_MIN_VALUE (dom) - && TREE_CODE (TYPE_MIN_VALUE (dom)) == INTEGER_CST - && (wi::to_widest (op.op0) - < wi::to_widest (TYPE_MIN_VALUE (dom)))) - || (TYPE_MAX_VALUE (dom) - && TREE_CODE (TYPE_MAX_VALUE (dom)) == INTEGER_CST - && (wi::to_widest (op.op0) - > wi::to_widest (TYPE_MAX_VALUE (dom))))) - oob_index = true; - } - if ((op.opcode == ARRAY_REF - || op.opcode == ARRAY_RANGE_REF) - && TREE_CODE (op.op0) == SSA_NAME) - { - /* There's a single constant index that get's 'off' closer - to 'offset'. */ - unsigned HOST_WIDE_INT elsz - = tree_to_uhwi (op.op2) * vn_ref_op_align_unit (&op); - unsigned HOST_WIDE_INT idx - = (coffset - off.to_constant ()) / BITS_PER_UNIT / elsz; - if (idx == 0) - op.op0 = op.op1; - else - op.op0 = wide_int_to_tree (TREE_TYPE (op.op0), - wi::to_poly_wide (op.op1) + idx); - op.off = idx * elsz; - off += op.off * BITS_PER_UNIT; - } - else - { - if (op.opcode == ERROR_MARK) - /* two-ops codes have the offset in the first op. */ - ; - else if (op.opcode == ADDR_EXPR - || op.opcode == SSA_NAME - || op.opcode == CONSTRUCTOR - || TREE_CODE_CLASS (op.opcode) == tcc_declaration - || TREE_CODE_CLASS (op.opcode) == tcc_constant) - /* end-of ref. */ - gcc_assert (i == result->length ()); - else if (op.opcode == COMPONENT_REF) - { - /* op.off is tracked in bytes, re-do it manually - because of bitfields. */ - tree field = op.op0; - /* We do not have a complete COMPONENT_REF tree here so we - cannot use component_ref_field_offset. Do the interesting - parts manually. */ - tree this_offset = DECL_FIELD_OFFSET (field); - if (op.op1 || !poly_int_tree_p (this_offset)) - gcc_unreachable (); - else - { - poly_offset_int woffset - = (wi::to_poly_offset (this_offset) - << LOG2_BITS_PER_UNIT); - woffset += wi::to_offset (DECL_FIELD_BIT_OFFSET (field)); - off += woffset.force_shwi (); - } - } - else - { - gcc_assert (known_ne (op.off, -1) - /* The constant offset can be -1. */ - || op.opcode == MEM_REF - /* Out-of-bound indices can compute to - a known -1 offset. */ - || ((op.opcode == ARRAY_REF - || op.opcode == ARRAY_RANGE_REF) - && poly_int_tree_p (op.op0) - && poly_int_tree_p (op.op1) - && TREE_CODE (op.op2) == INTEGER_CST)); - off += op.off * BITS_PER_UNIT; - } - } - } - if (flag_checking && !oob_index) - { - ao_ref r; - if (start != 0) - ; - else if (ao_ref_init_from_vn_reference (&r, 0, 0, TREE_TYPE (orig), - *result)) - gcc_assert (known_eq (r.offset, orig_offset) - && known_eq (r.size, size) - && known_eq (r.max_size, max_size)); - else - gcc_unreachable (); - } - } } /* Build a alias-oracle reference abstraction in *REF from the vn_reference -- cgit v1.1 From 95f012ef4a72eb50f05ad909fa10655f4cb8cbd3 Mon Sep 17 00:00:00 2001 From: Harald Anlauf Date: Tue, 27 Feb 2024 21:51:53 +0100 Subject: Fortran testsuite: fix invalid Fortran in testcase gcc/testsuite/ChangeLog: * gfortran.dg/pr101026.f: Let variables used in specification expression be passed as dummy arguments --- gcc/testsuite/gfortran.dg/pr101026.f | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/gfortran.dg/pr101026.f b/gcc/testsuite/gfortran.dg/pr101026.f index 9576d88..e05e21c 100644 --- a/gcc/testsuite/gfortran.dg/pr101026.f +++ b/gcc/testsuite/gfortran.dg/pr101026.f @@ -1,6 +1,6 @@ ! { dg-do compile } ! { dg-options "-Ofast -frounding-math" } - SUBROUTINE PASSB4 (CC,CH) + SUBROUTINE PASSB4 (CC,CH,IDO,L1) DIMENSION CC(IDO,4,L1), CH(IDO,L1,*) DO 103 I=2,IDO,2 TI4 = CC0-CC(I,4,K) -- cgit v1.1 From 0198cade5ac15c35ed3f5af54060d7bc6a39f326 Mon Sep 17 00:00:00 2001 From: Cupertino Miranda Date: Tue, 30 Jan 2024 19:01:12 +0000 Subject: btf: fix type id in BTF_KIND_FUNC struct data. This patch corrects the addition of +1 on the type id, which originally was done in the wrong location and led to func_dtd->dtd_type for BTF_KIND_FUNC struct data to contain the type id of the previous entry. gcc/ChangeLog: * btfout.cc (btf_collect_dataset): Corrects BTF type id. --- gcc/btfout.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/btfout.cc b/gcc/btfout.cc index dcf751f..7e114e2 100644 --- a/gcc/btfout.cc +++ b/gcc/btfout.cc @@ -457,7 +457,8 @@ btf_collect_datasec (ctf_container_ref ctfc) func_dtd->dtd_data.ctti_type = dtd->dtd_type; func_dtd->linkage = dtd->linkage; func_dtd->dtd_name = dtd->dtd_name; - func_dtd->dtd_type = num_types_added + num_types_created; + /* +1 for the sentinel type not in the types map. */ + func_dtd->dtd_type = num_types_added + num_types_created + 1; /* Only the BTF_KIND_FUNC type actually references the name. The BTF_KIND_FUNC_PROTO is always anonymous. */ @@ -480,8 +481,7 @@ btf_collect_datasec (ctf_container_ref ctfc) struct btf_var_secinfo info; - /* +1 for the sentinel type not in the types map. */ - info.type = func_dtd->dtd_type + 1; + info.type = func_dtd->dtd_type; /* Both zero at compile time. */ info.size = 0; -- cgit v1.1 From 69a3ce49bda929e1ffbc1fc1123f5f2485ec944d Mon Sep 17 00:00:00 2001 From: Cupertino Miranda Date: Mon, 12 Feb 2024 17:36:21 +0000 Subject: btf: add BTF_KIND_FUNC traversal function. The patch adds a traversal function to traverse all BTF_KIND_FUNC nodes with a callback function. Used for .BTF.ext section content creation. gcc/ChangeLog: * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT. (traverse_btf_func_types): Define function. * ctfc.h (funcs_traverse_callback): Typedef for function prototype. (traverse_btf_func_types): Add prototype. --- gcc/btfout.cc | 22 ++++++++++++++++++++-- gcc/ctfc.h | 3 +++ 2 files changed, 23 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/btfout.cc b/gcc/btfout.cc index 7e114e2..7aabd99 100644 --- a/gcc/btfout.cc +++ b/gcc/btfout.cc @@ -1276,8 +1276,10 @@ output_btf_types (ctf_container_ref ctfc) static void output_btf_func_types (ctf_container_ref ctfc) { - for (size_t i = 0; i < vec_safe_length (funcs); i++) - btf_asm_func_type (ctfc, (*funcs)[i], i); + ctf_dtdef_ref ref; + unsigned i; + FOR_EACH_VEC_ELT (*funcs, i, ref) + btf_asm_func_type (ctfc, ref, i); } /* Output all BTF_KIND_DATASEC records. */ @@ -1452,4 +1454,20 @@ btf_finalize (void) tu_ctfc = NULL; } +/* Traversal function for all BTF_KIND_FUNC type records. */ + +bool +traverse_btf_func_types (funcs_traverse_callback callback, void *data) +{ + ctf_dtdef_ref ref; + unsigned i; + FOR_EACH_VEC_ELT (*funcs, i, ref) + { + bool stop = callback (ref, data); + if (stop == true) + return true; + } + return false; +} + #include "gt-btfout.h" diff --git a/gcc/ctfc.h b/gcc/ctfc.h index 7aac57e..fa188bf 100644 --- a/gcc/ctfc.h +++ b/gcc/ctfc.h @@ -441,6 +441,9 @@ extern int ctf_add_variable (ctf_container_ref, const char *, ctf_id_t, extern ctf_id_t ctf_lookup_tree_type (ctf_container_ref, const tree); extern ctf_id_t get_btf_id (ctf_id_t); +typedef bool (*funcs_traverse_callback) (ctf_dtdef_ref, void *); +bool traverse_btf_func_types (funcs_traverse_callback, void *); + /* CTF section does not emit location information; at this time, location information is needed for BTF CO-RE use-cases. */ -- cgit v1.1 From 38d2eb337b41e9cdc5eb89ab865d74ef5304bc03 Mon Sep 17 00:00:00 2001 From: Cupertino Miranda Date: Mon, 12 Feb 2024 17:37:37 +0000 Subject: bpf: Always emit .BTF.ext section if generating BTF BPF applications, when generating BTF information should always create a .BTF.ext section. Current implementation was only creating it when -mco-re option was used. This patch makes .BTF.ext always be generated for BPF target objects. The patch also adds conditions around btf_finalize function call such that BTF deallocation happens later for BPF target. For BPF, btf_finalize is only called after .BTF.ext is generated. gcc/ChangeLog: * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext enabled by default for BPF. (bpf_file_end): Call BTF deallocation. (bpf_asm_init_sections): Correct condition. * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF deallocation. (ctf_debuf_finish): Correct condition for calling ctf_debug_finalize. --- gcc/config/bpf/bpf.cc | 20 +++++++++----------- gcc/dwarf2ctf.cc | 12 ++++++------ 2 files changed, 15 insertions(+), 17 deletions(-) (limited to 'gcc') diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc index f9ac263..71f643e 100644 --- a/gcc/config/bpf/bpf.cc +++ b/gcc/config/bpf/bpf.cc @@ -195,10 +195,8 @@ bpf_option_override (void) if (TARGET_BPF_CORE && !btf_debuginfo_p ()) error ("BPF CO-RE requires BTF debugging information, use %<-gbtf%>"); - /* To support the portability needs of BPF CO-RE approach, BTF debug - information includes the BPF CO-RE relocations. */ - if (TARGET_BPF_CORE) - write_symbols |= BTF_WITH_CORE_DEBUG; + /* BPF applications always generate .BTF.ext. */ + write_symbols |= BTF_WITH_CORE_DEBUG; /* Unlike much of the other BTF debug information, the information necessary for CO-RE relocations is added to the CTF container by the BPF backend. @@ -218,10 +216,7 @@ bpf_option_override (void) /* -gbtf implies -mcore when using the BPF backend, unless -mno-co-re is specified. */ if (btf_debuginfo_p () && !(target_flags_explicit & MASK_BPF_CORE)) - { - target_flags |= MASK_BPF_CORE; - write_symbols |= BTF_WITH_CORE_DEBUG; - } + target_flags |= MASK_BPF_CORE; /* Determine available features from ISA setting (-mcpu=). */ if (bpf_has_jmpext == -1) @@ -267,7 +262,7 @@ bpf_option_override (void) static void bpf_asm_init_sections (void) { - if (TARGET_BPF_CORE) + if (btf_debuginfo_p () && btf_with_core_debuginfo_p ()) btf_ext_init (); } @@ -279,8 +274,11 @@ bpf_asm_init_sections (void) static void bpf_file_end (void) { - if (TARGET_BPF_CORE) - btf_ext_output (); + if (btf_debuginfo_p () && btf_with_core_debuginfo_p ()) + { + btf_ext_output (); + btf_finalize (); + } } #undef TARGET_ASM_FILE_END diff --git a/gcc/dwarf2ctf.cc b/gcc/dwarf2ctf.cc index 93e5619..dca86ed 100644 --- a/gcc/dwarf2ctf.cc +++ b/gcc/dwarf2ctf.cc @@ -944,7 +944,10 @@ ctf_debug_finalize (const char *filename, bool btf) if (btf) { btf_output (filename); - btf_finalize (); + /* btf_finalize when compiling BPF applciations gets deallocated by the + BPF target in bpf_file_end. */ + if (btf_debuginfo_p () && !btf_with_core_debuginfo_p ()) + btf_finalize (); } else @@ -1027,11 +1030,8 @@ ctf_debug_finish (const char * filename) /* Emit BTF debug info here when CO-RE relocations need to be generated. BTF with CO-RE relocations needs to be generated when CO-RE is in effect for the BPF target. */ - if (btf_with_core_debuginfo_p ()) - { - gcc_assert (btf_debuginfo_p ()); - ctf_debug_finalize (filename, btf_debuginfo_p ()); - } + if (btf_debuginfo_p () && btf_with_core_debuginfo_p ()) + ctf_debug_finalize (filename, btf_debuginfo_p ()); } #include "gt-dwarf2ctf.h" -- cgit v1.1 From 77142bdba485057550c5d849864948b0d20be8af Mon Sep 17 00:00:00 2001 From: Cupertino Miranda Date: Mon, 12 Feb 2024 17:46:03 +0000 Subject: bpf: implementation of func_info in .BTF.ext. Kernel verifier complains in some particular cases for missing func_info implementation in .BTF.ext. This patch implements it. Strings are cached locally in coreout.cc to avoid adding duplicated strings in the string list. This string deduplication should eventually be moved to the CTFC functions such that this happens widely. With this implementation, the CO-RE relocations information was also simplified and integrated with the FuncInfo structures. gcc/Changelog: PR target/113453 * config/bpf/bpf.cc (bpf_function_prologue): Define target hook. * config/bpf/coreout.cc (brf_ext_info_section) (btf_ext_info): Move from coreout.h (btf_ext_funcinfo, btf_ext_lineinfo): Add struct. (bpf_core_reloc): Rename to btf_ext_core_reloc. (btf_ext): Add static variable. (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN) (bpf_create_or_find_funcinfo, bpt_create_core_reloc) (btf_ext_add_string, btf_funcinfo_type_callback) (btf_add_func_info_for, btf_validate_funcinfo) (btf_ext_info_len, output_btfext_func_info): Add function. (output_btfext_header, bpf_core_reloc_add) (output_btfext_core_relocs, btf_ext_init, btf_ext_output): Change to support new structs. * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo): Move and change in coreout.cc. (btf_add_func_info_for, btf_ext_add_string): Add prototypes. gcc/testsuite/ChangeLog: PR target/113453 * gcc.target/bpf/btfext-funcinfo-nocore.c: Add. * gcc.target/bpf/btfext-funcinfo.c: Add. * gcc.target/bpf/core-attr-5.c: Fix regexp. * gcc.target/bpf/core-attr-6.c: Fix regexp. * gcc.target/bpf/core-builtin-fieldinfo-offset-1.c: Fix regexp. * gcc.target/bpf/core-section-1.c: Fix regexp. --- gcc/config/bpf/bpf.cc | 12 + gcc/config/bpf/coreout.cc | 514 +++++++++++++++------ gcc/config/bpf/coreout.h | 20 +- .../gcc.target/bpf/btfext-funcinfo-nocore.c | 42 ++ gcc/testsuite/gcc.target/bpf/btfext-funcinfo.c | 46 ++ gcc/testsuite/gcc.target/bpf/core-attr-5.c | 9 +- gcc/testsuite/gcc.target/bpf/core-attr-6.c | 6 +- .../bpf/core-builtin-fieldinfo-offset-1.c | 13 +- gcc/testsuite/gcc.target/bpf/core-section-1.c | 2 +- 9 files changed, 502 insertions(+), 162 deletions(-) create mode 100644 gcc/testsuite/gcc.target/bpf/btfext-funcinfo-nocore.c create mode 100644 gcc/testsuite/gcc.target/bpf/btfext-funcinfo.c (limited to 'gcc') diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc index 71f643e..22b0cf2 100644 --- a/gcc/config/bpf/bpf.cc +++ b/gcc/config/bpf/bpf.cc @@ -385,6 +385,18 @@ bpf_compute_frame_layout (void) #undef TARGET_COMPUTE_FRAME_LAYOUT #define TARGET_COMPUTE_FRAME_LAYOUT bpf_compute_frame_layout +/* Defined to initialize data for func_info region in .BTF.ext section. */ + +static void +bpf_function_prologue (FILE *f ATTRIBUTE_UNUSED) +{ + if (btf_debuginfo_p ()) + btf_add_func_info_for (cfun->decl, current_function_func_begin_label); +} + +#undef TARGET_ASM_FUNCTION_PROLOGUE +#define TARGET_ASM_FUNCTION_PROLOGUE bpf_function_prologue + /* Expand to the instructions in a function prologue. This function is called when expanding the 'prologue' pattern in bpf.md. */ diff --git a/gcc/config/bpf/coreout.cc b/gcc/config/bpf/coreout.cc index 2f06ec2..1406652 100644 --- a/gcc/config/bpf/coreout.cc +++ b/gcc/config/bpf/coreout.cc @@ -31,6 +31,7 @@ #include "btf.h" #include "rtl.h" #include "tree-pretty-print.h" +#include "cgraph.h" #include "coreout.h" @@ -95,64 +96,193 @@ result, a single .BTF.ext section can contain CO-RE relocations for multiple programs in distinct sections. */ -/* Internal representation of a BPF CO-RE relocation record. */ +/* BTF.ext debug info section. */ +static GTY (()) section * btf_ext_info_section; + +#ifndef BTF_EXT_INFO_SECTION_NAME +#define BTF_EXT_INFO_SECTION_NAME ".BTF.ext" +#endif +#define BTF_EXT_INFO_SECTION_FLAGS (SECTION_DEBUG) + +#ifndef BTF_EXT_INFO_SECTION_LABEL +#define BTF_EXT_INFO_SECTION_LABEL "Lbtfext" +#endif + +#define MAX_BTF_EXT_LABEL_BYTES 40 +static char btf_ext_info_section_label[MAX_BTF_EXT_LABEL_BYTES]; + +/* A funcinfo record, in the .BTF.ext funcinfo section. */ +struct GTY ((chain_next ("%h.next"))) btf_ext_funcinfo +{ + uint32_t type; /* Type ID of a BTF_KIND_FUNC type. */ + const char *fnname; + const char *label; + + struct btf_ext_funcinfo *next; /* Linked list to collect func_info elems. */ +}; + +/* A lineinfo record, in the .BTF.ext lineinfo section. */ +struct GTY ((chain_next ("%h.next"))) btf_ext_lineinfo +{ + uint32_t insn_off; /* Offset of the instruction. */ + uint32_t file_name_off; /* Offset of file name in BTF string table. */ + uint32_t line_off; /* Offset of source line in BTF string table. */ + uint32_t line_col; /* Line number (bits 31-11) and column (11-0). */ -typedef struct GTY (()) bpf_core_reloc { + struct btf_ext_lineinfo *next; /* Linked list to collect line_info elems. */ +}; + +/* Internal representation of a BPF CO-RE relocation record. */ +struct GTY ((chain_next ("%h.next"))) btf_ext_core_reloc { unsigned int bpfcr_type; /* BTF type ID of container. */ unsigned int bpfcr_astr_off; /* Offset of access string in .BTF string table. */ rtx_code_label * bpfcr_insn_label; /* RTX label attached to instruction to patch. */ enum btf_core_reloc_kind bpfcr_kind; /* Kind of relocation to perform. */ -} bpf_core_reloc_t; -typedef bpf_core_reloc_t * bpf_core_reloc_ref; + struct { + const char *accessor_str; + tree type; + } info; -/* Internal representation of a CO-RE relocation (sub)section of the - .BTF.ext information. One such section is generated for each ELF section - in the output object having relocations that a BPF loader must resolve. */ + struct btf_ext_core_reloc *next; +}; -typedef struct GTY (()) bpf_core_section { - /* Name of ELF section to which these CO-RE relocations apply. */ - const char * name; +/* Main data structure to keep .BTF.ext section data. */ +struct GTY ((chain_next ("%h.next"))) btf_ext_info_sec { + const char *sec_name; + uint32_t sec_name_off; /* offset to section name. */ + + struct { + uint32_t num_info; + struct btf_ext_funcinfo *head; + } func_info; + struct { + uint32_t num_info; + struct btf_ext_lineinfo *head; + } line_info; + struct { + uint32_t num_info; + struct btf_ext_core_reloc *head; + } core_info; + + struct btf_ext_info_sec *next; +}; - /* Offset of section name in .BTF string table. */ - uint32_t name_offset; +static GTY (()) struct btf_ext_info_sec *btf_ext = NULL; - /* Relocations in the section. */ - vec * GTY (()) relocs; -} bpf_core_section_t; +/* Helper function to add a section structure to the linked list with entry + point in info static variable. */ -typedef bpf_core_section_t * bpf_core_section_ref; +static struct btf_ext_info_sec * +btfext_info_sec_find_or_add (const char *sec_name, bool add) +{ + struct btf_ext_info_sec **tmp = &btf_ext; -/* BTF.ext debug info section. */ + while (*tmp != NULL) + { + if (strcmp ((*tmp)->sec_name, sec_name) == 0) + return *tmp; + tmp = &((*tmp)->next); + } -static GTY (()) section * btf_ext_info_section; + if (add == false) + return NULL; -static int btf_ext_label_num; + struct btf_ext_info_sec *ret = ggc_cleared_alloc (); + *tmp = ret; -#ifndef BTF_EXT_INFO_SECTION_NAME -#define BTF_EXT_INFO_SECTION_NAME ".BTF.ext" -#endif + /* Set data for section info. */ + ret->sec_name = sec_name; + ret->sec_name_off = btf_ext_add_string (sec_name); -#define BTF_EXT_INFO_SECTION_FLAGS (SECTION_DEBUG) + return ret; +} -#define MAX_BTF_EXT_LABEL_BYTES 40 +#define SEARCH_NODE_AND_RETURN(TYPE, FIELD, CONDITION) __extension__ ({ \ + TYPE **head = &(FIELD); \ + while (*head != NULL) \ + { \ + if (CONDITION) \ + return (*head); \ + head = &((*head)->next); \ + } \ + head; \ +}) + +/* Function to create or find a funcinfo node in info. */ + +static struct btf_ext_funcinfo * +bpf_create_or_find_funcinfo (const char *fnname, const char *sec_name, + btf_ext_info_sec **in_sec = NULL) +{ + struct btf_ext_info_sec *sec_elem = + btfext_info_sec_find_or_add (sec_name, true); -static char btf_ext_info_section_label[MAX_BTF_EXT_LABEL_BYTES]; + if (in_sec != NULL) + *in_sec = sec_elem; -#ifndef BTF_EXT_INFO_SECTION_LABEL -#define BTF_EXT_INFO_SECTION_LABEL "Lbtfext" -#endif + struct btf_ext_funcinfo **head = + SEARCH_NODE_AND_RETURN(struct btf_ext_funcinfo, + sec_elem->func_info.head, + strcmp ((*head)->fnname, fnname) == 0); -static GTY (()) vec *bpf_core_sections; + *head = ggc_cleared_alloc (); + (*head)->fnname = fnname; + (*head)->label = NULL; -struct GTY(()) bpf_core_extra { - const char *accessor_str; - tree type; + return *head; +} + +/* Function to create a core_reloc node in info. */ + +static struct btf_ext_core_reloc * +bpf_create_core_reloc (const char *sec_name, + struct btf_ext_info_sec **in_sec = NULL) +{ + struct btf_ext_info_sec *sec_elem = + btfext_info_sec_find_or_add (sec_name, true); + + if (in_sec != NULL) + *in_sec = sec_elem; + + struct btf_ext_core_reloc **head = + SEARCH_NODE_AND_RETURN(struct btf_ext_core_reloc, + sec_elem->core_info.head, + false); + + *head = ggc_cleared_alloc (); + + return *head; +} + +/* String caching to avoid repeated strings added to BTF string table. */ +struct GTY((chain_next ("%h.next"))) string_cache { + const char *str; + unsigned int offset; + struct string_cache *next; }; -typedef struct bpf_core_extra *bpf_core_extra_ref; -static GTY(()) hash_map *bpf_comment_info; +static GTY(()) struct string_cache *btf_ext_strings = NULL; + +unsigned int +btf_ext_add_string (const char *str) +{ + ctf_container_ref ctfc = ctf_get_tu_ctfc (); + struct string_cache **tmp = &btf_ext_strings; + while (*tmp != NULL) + { + if (strcmp ((*tmp)->str, str) == 0) + return (*tmp)->offset; + tmp = &((*tmp)->next); + } + + *tmp = ggc_cleared_alloc (); + (*tmp)->str = ggc_strdup (str); + ctf_add_string (ctfc, (*tmp)->str, &((*tmp)->offset), CTF_AUX_STRTAB); + + return (*tmp)->offset; +} /* Create a new BPF CO-RE relocation record, and add it to the appropriate CO-RE section. */ @@ -162,42 +292,23 @@ bpf_core_reloc_add (const tree type, const char * section_name, rtx_code_label *label, enum btf_core_reloc_kind kind) { - bpf_core_reloc_ref bpfcr = ggc_cleared_alloc (); - bpf_core_extra_ref info = ggc_cleared_alloc (); + struct btf_ext_info_sec *sec = NULL; + struct btf_ext_core_reloc *bpfcr = bpf_create_core_reloc (section_name, &sec); + ctf_container_ref ctfc = ctf_get_tu_ctfc (); /* Buffer the access string in the auxiliary strtab. */ - ctf_add_string (ctfc, accessor, &(bpfcr->bpfcr_astr_off), CTF_AUX_STRTAB); + bpfcr->bpfcr_astr_off = 0; + if (accessor != NULL) + bpfcr->bpfcr_astr_off = btf_ext_add_string (accessor); bpfcr->bpfcr_type = get_btf_id (ctf_lookup_tree_type (ctfc, type)); bpfcr->bpfcr_insn_label = label; bpfcr->bpfcr_kind = kind; - info->accessor_str = accessor; - info->type = type; - bpf_comment_info->put (bpfcr, info); - - /* Add the CO-RE reloc to the appropriate section. */ - bpf_core_section_ref sec; - int i; - FOR_EACH_VEC_ELT (*bpf_core_sections, i, sec) - if (strcmp (sec->name, section_name) == 0) - { - vec_safe_push (sec->relocs, bpfcr); - return; - } + bpfcr->info.accessor_str = accessor; + bpfcr->info.type = type; - /* If the CO-RE section does not yet exist, create it. */ - sec = ggc_cleared_alloc (); - - ctf_add_string (ctfc, section_name, &sec->name_offset, CTF_AUX_STRTAB); - if (strcmp (section_name, "")) - ctfc->ctfc_aux_strlen += strlen (section_name) + 1; - - sec->name = section_name; - vec_alloc (sec->relocs, 1); - vec_safe_push (sec->relocs, bpfcr); - - vec_safe_push (bpf_core_sections, sec); + sec->core_info.num_info += 1; } /* Return the 0-based index of the field NODE in its containing struct or union @@ -243,6 +354,111 @@ bpf_core_get_sou_member_index (ctf_container_ref ctfc, const tree node) return -1; } +/* Helper function to check if a particular named function exists as a + BTF_KIND_FUNC type record. */ + +static bool +btf_funcinfo_type_callback (ctf_dtdef_ref func, void *data) +{ + struct btf_ext_funcinfo *info = (struct btf_ext_funcinfo *) data; + if (strcmp (func->dtd_name, info->fnname) == 0) + { + uint32_t type = func->dtd_type; + info->type = type; + return true; + } + return false; +} + +/* Entry point function to add a func_info in local data structures + represented by info static variable. + This function is used in bpf.cc. */ + +struct btf_ext_funcinfo * +btf_add_func_info_for (tree decl, const char *label) +{ + const char *fnname = IDENTIFIER_POINTER (DECL_NAME (decl)); + const char *sec_name = decl_section_name (decl); + + /* Recover the original function name, which may have been mangled by + optimizations. */ + const char *cp_ptr = strstr (fnname, "."); + if (cp_ptr != NULL) + { + char new_name[100]; + strcpy (new_name, fnname); + int pos = cp_ptr - fnname; + new_name[pos] = 0; + fnname = ggc_strdup (new_name); + } + + if (sec_name == NULL) + sec_name = ".text"; + + struct btf_ext_info_sec *sec = NULL; + struct btf_ext_funcinfo *info = + bpf_create_or_find_funcinfo (fnname, sec_name, &sec); + + info->label = label; + return info; +} + +/* This function traverses all func_info entries and verified they do have a + BTF_KIND_FUNC type record associated. If they do not it is marked as + invalided by clearing the associated label. */ + +static void +btf_validate_funcinfo (btf_ext_info_sec *sec) +{ + while (sec != NULL) + { + struct btf_ext_funcinfo *funcinfo = sec->func_info.head; + while (funcinfo != NULL) + { + bool found = traverse_btf_func_types (btf_funcinfo_type_callback, + funcinfo); + if (found == true) + sec->func_info.num_info += 1; + else + funcinfo->label = NULL; + + funcinfo = funcinfo->next; + } + sec = sec->next; + } +} + +/* Compute the section size in section for func_info, line_info and core_info + regions of .BTF.ext. */ + +static void +btf_ext_info_len (uint32_t *fi_len, uint32_t *li_len, uint32_t *cr_len) +{ + *fi_len = *li_len = *cr_len = 0; + struct btf_ext_info_sec *tmp = btf_ext; + if (tmp != NULL) + while (tmp != NULL) + { + /* Size computation does 8 bytes per section entry plus num_info of the + * respective structure size: + - 8 bytes for func_info, + - 16 bytes for both line_info and core_info. */ + if (tmp->func_info.num_info > 0) + *fi_len += 8 + (8 * tmp->func_info.num_info); + if (tmp->line_info.num_info > 0) + *li_len += 8 + (16 * tmp->line_info.num_info); + if (tmp->core_info.num_info > 0) + *cr_len += 8 + (16 * tmp->core_info.num_info); + tmp = tmp->next; + } + + /* If there are entries within the regions, add 4 bytes to set the header of + the respective sections that contains the size for each of the entry. */ + *fi_len += *fi_len != 0 ? 4 : 0; + *li_len += *li_len != 0 ? 4 : 0; + *cr_len += *cr_len != 0 ? 4 : 0; +} + /* Compute and output the header of a .BTF.ext debug info section. */ static void @@ -256,23 +472,19 @@ output_btfext_header (void) dw2_asm_output_data (1, 0, "btfext_flags"); dw2_asm_output_data (4, sizeof (struct btf_ext_header), "btfext_hdr_len"); - uint32_t func_info_off = 0, func_info_len = 0; - uint32_t line_info_off = 0, line_info_len = 0; - uint32_t core_relo_off = 0, core_relo_len = 0; + btf_validate_funcinfo (btf_ext); - /* Header core_relo_len is the sum total length in bytes of all CO-RE - relocation sections, plus the 4 byte record size. */ - size_t i; - bpf_core_section_ref sec; - core_relo_len += vec_safe_length (bpf_core_sections) - * sizeof (struct btf_ext_section_header); + uint32_t func_info_len = 0; + uint32_t line_info_len = 0; + uint32_t core_info_len = 0; + btf_ext_info_len (&func_info_len, &line_info_len, &core_info_len); - FOR_EACH_VEC_ELT (*bpf_core_sections, i, sec) - core_relo_len += - vec_safe_length (sec->relocs) * sizeof (struct btf_ext_reloc); + if (!TARGET_BPF_CORE) + core_info_len = 0; - if (core_relo_len) - core_relo_len += sizeof (uint32_t); + uint32_t func_info_off = 0; + uint32_t line_info_off = func_info_len; + uint32_t core_info_off = line_info_off + line_info_len; dw2_asm_output_data (4, func_info_off, "func_info_offset"); dw2_asm_output_data (4, func_info_len, "func_info_len"); @@ -280,47 +492,47 @@ output_btfext_header (void) dw2_asm_output_data (4, line_info_off, "line_info_offset"); dw2_asm_output_data (4, line_info_len, "line_info_len"); - dw2_asm_output_data (4, core_relo_off, "core_relo_offset"); - dw2_asm_output_data (4, core_relo_len, "core_relo_len"); + dw2_asm_output_data (4, core_info_off, "core_relo_offset"); + dw2_asm_output_data (4, core_info_len, "core_relo_len"); } -/* Output a single CO-RE relocation record. */ +/* Outputs func_info region on .BTF.ext. */ static void -output_asm_btfext_core_reloc (bpf_core_reloc_ref bpfcr) +output_btfext_func_info (struct btf_ext_info_sec *sec) { - bpf_core_extra_ref *info = bpf_comment_info->get (bpfcr); - gcc_assert (info != NULL); - - bpfcr->bpfcr_astr_off += ctfc_get_strtab_len (ctf_get_tu_ctfc (), - CTF_STRTAB); - - dw2_assemble_integer (4, gen_rtx_LABEL_REF (Pmode, bpfcr->bpfcr_insn_label)); - fprintf (asm_out_file, "\t%s%s\n", - flag_debug_asm ? ASM_COMMENT_START : "", - (flag_debug_asm ? " bpfcr_insn" : "")); - - /* Extract the pretty print for the type expression. */ - pretty_printer pp; - dump_generic_node (&pp, (*info)->type, 0, TDF_VOPS|TDF_MEMSYMS|TDF_SLIM, - false); - char *str = xstrdup (pp_formatted_text (&pp)); - - dw2_asm_output_data (4, bpfcr->bpfcr_type, "bpfcr_type (%s)", str); - dw2_asm_output_data (4, bpfcr->bpfcr_astr_off, "bpfcr_astr_off (\"%s\")", - (*info)->accessor_str); - dw2_asm_output_data (4, bpfcr->bpfcr_kind, "bpfcr_kind"); -} - -/* Output all CO-RE relocation records for a section. */ - -static void -output_btfext_core_relocs (bpf_core_section_ref sec) -{ - size_t i; - bpf_core_reloc_ref bpfcr; - FOR_EACH_VEC_ELT (*(sec->relocs), i, bpfcr) - output_asm_btfext_core_reloc (bpfcr); + unsigned int str_aux_off = ctfc_get_strtab_len (ctf_get_tu_ctfc (), + CTF_STRTAB); + bool executed = false; + while (sec != NULL) + { + uint32_t count = 0; + if (sec->func_info.num_info > 0) + { + if (executed == false && (executed = true)) + dw2_asm_output_data (4, 8, "FuncInfo entry size"); + dw2_asm_output_data (4, sec->sec_name_off + str_aux_off, + "FuncInfo section string for %s", + sec->sec_name); + dw2_asm_output_data (4, sec->func_info.num_info, "Number of entries"); + + struct btf_ext_funcinfo *elem = sec->func_info.head; + while (elem != NULL) + { + if (elem->label != NULL) + { + count += 1; + dw2_asm_output_offset (4, elem->label, + NULL, "label for function %s", elem->fnname); + dw2_asm_output_data (4, elem->type, "btf_type_id"); + } + elem = elem->next; + } + } + + gcc_assert (count == sec->func_info.num_info); + sec = sec->next; + } } /* Output all CO-RE relocation sections. */ @@ -328,28 +540,51 @@ output_btfext_core_relocs (bpf_core_section_ref sec) static void output_btfext_core_sections (void) { - size_t i; - bpf_core_section_ref sec; - - /* BTF Ext section info. */ - dw2_asm_output_data (4, sizeof (struct btf_ext_reloc), - "btfext_core_info_rec_size"); - - FOR_EACH_VEC_ELT (*bpf_core_sections, i, sec) + struct btf_ext_info_sec *sec = btf_ext; + unsigned int str_aux_off = ctfc_get_strtab_len (ctf_get_tu_ctfc (), + CTF_STRTAB); + bool executed = false; + while (sec != NULL) { - /* Section name offset, refers to the offset of a string with the name of - the section to which these CORE relocations refer, e.g. '.text'. - The string is buffered in the BTF strings table. */ - - /* BTF specific strings are in CTF_AUX_STRTAB, which is concatenated - after CTF_STRTAB. Add the length of STRTAB to the final offset. */ - sec->name_offset += ctfc_get_strtab_len (ctf_get_tu_ctfc (), CTF_STRTAB); - - dw2_asm_output_data (4, sec->name_offset, "btfext_secinfo_sec_name_off"); - dw2_asm_output_data (4, vec_safe_length (sec->relocs), - "btfext_secinfo_num_recs"); - - output_btfext_core_relocs (sec); + uint32_t count = 0; + if (sec->core_info.num_info > 0) + { + if (executed == false && (executed = true)) + dw2_asm_output_data (4, 16, "CoreInfo entry size"); + dw2_asm_output_data (4, sec->sec_name_off + str_aux_off, + "CoreInfo section string for %s", + sec->sec_name); + dw2_asm_output_data (4, sec->core_info.num_info, "Number of entries"); + + struct btf_ext_core_reloc *bpfcr = sec->core_info.head; + while (bpfcr != NULL) + { + count += 1; + dw2_assemble_integer (4, + gen_rtx_LABEL_REF (Pmode, bpfcr->bpfcr_insn_label)); + fprintf (asm_out_file, "\t%s%s\n", + flag_debug_asm ? ASM_COMMENT_START : "", + (flag_debug_asm ? " bpfcr_insn" : "")); + + /* Extract the pretty print for the type expression. */ + pretty_printer pp; + dump_generic_node (&pp, bpfcr->info.type, 0, + TDF_VOPS|TDF_MEMSYMS|TDF_SLIM, + false); + char *str = xstrdup (pp_formatted_text (&pp)); + + dw2_asm_output_data (4, bpfcr->bpfcr_type, "bpfcr_type (%s)", + str); + dw2_asm_output_data (4, bpfcr->bpfcr_astr_off + str_aux_off, + "bpfcr_astr_off (\"%s\")", + bpfcr->info.accessor_str); + dw2_asm_output_data (4, bpfcr->bpfcr_kind, "bpfcr_kind"); + bpfcr = bpfcr->next; + } + } + + gcc_assert (count == sec->core_info.num_info); + sec = sec->next; } } @@ -362,11 +597,7 @@ btf_ext_init (void) BTF_EXT_INFO_SECTION_FLAGS, NULL); ASM_GENERATE_INTERNAL_LABEL (btf_ext_info_section_label, - BTF_EXT_INFO_SECTION_LABEL, - btf_ext_label_num++); - - vec_alloc (bpf_core_sections, 1); - bpf_comment_info = hash_map::create_ggc (); + "Lbtfext", 0); } /* Output the entire .BTF.ext section. */ @@ -375,9 +606,12 @@ void btf_ext_output (void) { output_btfext_header (); - output_btfext_core_sections (); + output_btfext_func_info (btf_ext); + if (TARGET_BPF_CORE) + output_btfext_core_sections (); - bpf_core_sections = NULL; + /* Extra padding required by BPF code, in case all structures are empty. */ + dw2_asm_output_data (4, 0, "Required padding by libbpf structs"); } #include "gt-coreout.h" diff --git a/gcc/config/bpf/coreout.h b/gcc/config/bpf/coreout.h index 8a209f2..1c26b92 100644 --- a/gcc/config/bpf/coreout.h +++ b/gcc/config/bpf/coreout.h @@ -38,22 +38,6 @@ struct btf_ext_section_header uint32_t num_records; }; -/* A funcinfo record, in the .BTF.ext funcinfo section. */ -struct btf_ext_funcinfo -{ - uint32_t insn_off; /* Offset of the first instruction of the function. */ - uint32_t type; /* Type ID of a BTF_KIND_FUNC type. */ -}; - -/* A lineinfo record, in the .BTF.ext lineinfo section. */ -struct btf_ext_lineinfo -{ - uint32_t insn_off; /* Offset of the instruction. */ - uint32_t file_name_off; /* Offset of file name in BTF string table. */ - uint32_t line_off; /* Offset of source line in BTF string table. */ - uint32_t line_col; /* Line number (bits 31-11) and column (11-0). */ -}; - enum btf_core_reloc_kind { BPF_RELO_INVALID = -1, @@ -113,6 +97,10 @@ bpf_core_reloc_add (const tree type, const char * section_name, extern int bpf_core_get_sou_member_index (ctf_container_ref, const tree); +struct btf_ext_funcinfo *btf_add_func_info_for (tree decl, + const char *label); +unsigned int btf_ext_add_string (const char *str); + #ifdef __cplusplus } #endif diff --git a/gcc/testsuite/gcc.target/bpf/btfext-funcinfo-nocore.c b/gcc/testsuite/gcc.target/bpf/btfext-funcinfo-nocore.c new file mode 100644 index 0000000..09d3acc --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/btfext-funcinfo-nocore.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -dA -gbtf -mno-co-re" } */ + +struct T { + int a; + int b; + struct U { + int c; + struct V { + int d; + int e[4]; + int f; + } v; + } u; +} __attribute__((preserve_access_index)); + +__attribute__((section("foo_sec"), used)) +int foo_func (struct T *t) +{ + t->u.c = 5; + return t->u.v.e[3]; +} + +__attribute__((section("bar_sec"), used)) +int bar_func (struct T *t) +{ + int *x = &(t->u.v.f); + int old = *x; + *x = 4; + return old; +} + +/* { dg-final { scan-assembler-times "FuncInfo section string for foo_sec" 1 } } */ +/* { dg-final { scan-assembler-times "FuncInfo section string for bar_sec" 1 } } */ +/* { dg-final { scan-assembler-times "label for function foo_func" 1 } } */ +/* { dg-final { scan-assembler-times "label for function bar_func" 1 } } */ +/* { dg-final { scan-assembler-times ".4byte\t0x1\t# Number of entries" 2 } } */ +/* { dg-final { scan-assembler-times "Required padding" 1 } } */ + +/* { dg-final { scan-assembler-times "ascii \"foo_sec.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ +/* { dg-final { scan-assembler-times "ascii \"bar_sec.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/bpf/btfext-funcinfo.c b/gcc/testsuite/gcc.target/bpf/btfext-funcinfo.c new file mode 100644 index 0000000..a59c5bd --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/btfext-funcinfo.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -dA -gbtf" } */ + +struct T { + int a; + int b; + struct U { + int c; + struct V { + int d; + int e[4]; + int f; + } v; + } u; +} __attribute__((preserve_access_index)); + +__attribute__((section("foo_sec"), used)) +int foo_func (struct T *t) +{ + t->u.c = 5; + return t->u.v.e[3]; +} + +__attribute__((section("bar_sec"), used)) +int bar_func (struct T *t) +{ + int *x = &(t->u.v.f); + int old = *x; + *x = 4; + return old; +} + +/* { dg-final { scan-assembler-times "FuncInfo section string for foo_sec" 1 } } */ +/* { dg-final { scan-assembler-times "FuncInfo section string for bar_sec" 1 } } */ +/* { dg-final { scan-assembler-times "label for function foo_func" 1 } } */ +/* { dg-final { scan-assembler-times "label for function bar_func" 1 } } */ + +/* { dg-final { scan-assembler-times "ascii \"0:2:1:1:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ +/* { dg-final { scan-assembler-times "ascii \"0:2:1:2.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ +/* { dg-final { scan-assembler-times "ascii \"foo_sec.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ +/* { dg-final { scan-assembler-times "ascii \"bar_sec.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ +/* { dg-final { scan-assembler-times "FuncInfo entry size" 1 } } */ + +/* { dg-final { scan-assembler-times ".4byte\t0x1\t# Number of entries" 3 } } */ +/* { dg-final { scan-assembler-times ".4byte\t0x2\t# Number of entries" 1 } } */ +/* { dg-final { scan-assembler-times "Required padding" 1 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-attr-5.c b/gcc/testsuite/gcc.target/bpf/core-attr-5.c index c0dc15f..e71901d 100644 --- a/gcc/testsuite/gcc.target/bpf/core-attr-5.c +++ b/gcc/testsuite/gcc.target/bpf/core-attr-5.c @@ -55,8 +55,13 @@ func (struct T *t, int i) /* { dg-final { scan-assembler-times "ascii \"0:4.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:1:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:1:1.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ -/* { dg-final { scan-assembler-times "ascii \"0:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 2 } } */ +/* { dg-final { scan-assembler-times "ascii \"0:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:1:3\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:4\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:3\"\\)" 2 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:2\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:1:1\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:0\"\\)" 1 } } */ /* { dg-final { scan-assembler-times "bpfcr_type \\(struct T \\*\\)" 4 } } */ /* { dg-final { scan-assembler-times "bpfcr_type \\(struct U \\*\\)" 4 { xfail *-*-* } } } */ - diff --git a/gcc/testsuite/gcc.target/bpf/core-attr-6.c b/gcc/testsuite/gcc.target/bpf/core-attr-6.c index 858ae62..34a4c36 100644 --- a/gcc/testsuite/gcc.target/bpf/core-attr-6.c +++ b/gcc/testsuite/gcc.target/bpf/core-attr-6.c @@ -37,10 +37,14 @@ func (struct T *t, int i) mset (&t->a); } -/* { dg-final { scan-assembler-times "ascii \"0:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 2 } } */ +/* { dg-final { scan-assembler-times "ascii \"0:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:1:1.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:2.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:1:1\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:3\"\\)" 2 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:2\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:0\"\\)" 1 } } */ /* { dg-final { scan-assembler-times "bpfcr_type \\(struct T \\*\\)" 3 } } */ /* { dg-final { scan-assembler-times "bpfcr_type \\(struct U \\*\\)" 2 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-offset-1.c b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-offset-1.c index a4af9a5..2765420 100644 --- a/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-offset-1.c +++ b/gcc/testsuite/gcc.target/bpf/core-builtin-fieldinfo-offset-1.c @@ -52,9 +52,18 @@ unsigned int foo (struct T *t) /* { dg-final { scan-assembler-times "ascii \"0:1:0:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:0:4.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:1:0.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ -/* { dg-final { scan-assembler-times "ascii \"0:1:1:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 2 } } */ +/* { dg-final { scan-assembler-times "ascii \"0:1:1:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:1:1:4.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"0:2.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ -/* { dg-final { scan-assembler-times "ascii \"0:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 2 } } */ +/* { dg-final { scan-assembler-times "ascii \"0:3.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ + +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:0:0\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:0:3\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:0:4\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:1:0\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:1:3\"\\)" 2 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:1:1:4\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:2\"\\)" 1 } } */ +/* { dg-final { scan-assembler-times "bpfcr_astr_off \\(\"0:3\"\\)" 2 } } */ /* { dg-final { scan-assembler-times "0\[\t \]+\[^\n\]*bpfcr_kind" 10 } } */ diff --git a/gcc/testsuite/gcc.target/bpf/core-section-1.c b/gcc/testsuite/gcc.target/bpf/core-section-1.c index 4f16b08..c2bac46 100644 --- a/gcc/testsuite/gcc.target/bpf/core-section-1.c +++ b/gcc/testsuite/gcc.target/bpf/core-section-1.c @@ -35,4 +35,4 @@ int bar_func (struct T *t) /* { dg-final { scan-assembler-times "ascii \"foo_sec.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "ascii \"bar_sec.0\"\[\t \]+\[^\n\]*btf_aux_string" 1 } } */ /* { dg-final { scan-assembler-times "bpfcr_type" 2 } } */ -/* { dg-final { scan-assembler-times "btfext_core_info_rec_size" 1 } } */ +/* { dg-final { scan-assembler-times "CoreInfo entry size" 1 } } */ -- cgit v1.1 From 13914f4be9d7d4ac075e780b7a4bd8bac2ca1f15 Mon Sep 17 00:00:00 2001 From: Cupertino Miranda Date: Mon, 12 Feb 2024 17:56:04 +0000 Subject: bpf: renames coreout.* files to btfext-out.*. gcc/ChangeLog: * config.gcc (target_gtfiles): Change coreout to btfext-out. (extra_objs): Change coreout to btfext-out. * config/bpf/coreout.cc: Rename to btfext-out.cc. * config/bpf/btfext-out.cc: Add. * config/bpf/coreout.h: Rename to btfext-out.h. * config/bpf/btfext-out.h: Add. * config/bpf/core-builtins.cc: Change include. * config/bpf/core-builtins.h: Change include. * config/bpf/t-bpf: Accomodate renamed files. --- gcc/config.gcc | 4 +- gcc/config/bpf/btfext-out.cc | 617 ++++++++++++++++++++++++++++++++++++++++ gcc/config/bpf/btfext-out.h | 108 +++++++ gcc/config/bpf/core-builtins.cc | 2 +- gcc/config/bpf/core-builtins.h | 2 +- gcc/config/bpf/coreout.cc | 617 ---------------------------------------- gcc/config/bpf/coreout.h | 108 ------- gcc/config/bpf/t-bpf | 4 +- 8 files changed, 731 insertions(+), 731 deletions(-) create mode 100644 gcc/config/bpf/btfext-out.cc create mode 100644 gcc/config/bpf/btfext-out.h delete mode 100644 gcc/config/bpf/coreout.cc delete mode 100644 gcc/config/bpf/coreout.h (limited to 'gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index 2e35a11..a1480b7 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1654,8 +1654,8 @@ bpf-*-*) tmake_file="${tmake_file} bpf/t-bpf" use_collect2=no use_gcc_stdint=provide - extra_objs="coreout.o core-builtins.o" - target_gtfiles="$target_gtfiles \$(srcdir)/config/bpf/coreout.cc \$(srcdir)/config/bpf/core-builtins.cc" + extra_objs="btfext-out.o core-builtins.o" + target_gtfiles="$target_gtfiles \$(srcdir)/config/bpf/btfext-out.cc \$(srcdir)/config/bpf/core-builtins.cc" ;; cris-*-elf | cris-*-none) tm_file="elfos.h newlib-stdint.h ${tm_file}" diff --git a/gcc/config/bpf/btfext-out.cc b/gcc/config/bpf/btfext-out.cc new file mode 100644 index 0000000..00d2501 --- /dev/null +++ b/gcc/config/bpf/btfext-out.cc @@ -0,0 +1,617 @@ +/* BPF Compile Once - Run Everywhere (CO-RE) support. + Copyright (C) 2021-2024 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#define IN_TARGET_CODE 1 + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "target.h" +#include "memmodel.h" +#include "tm_p.h" +#include "output.h" +#include "dwarf2asm.h" +#include "ctfc.h" +#include "btf.h" +#include "rtl.h" +#include "tree-pretty-print.h" +#include "cgraph.h" + +#include "btfext-out.h" + +/* This file contains data structures and routines for construction and output + of BPF Compile Once - Run Everywhere (BPF CO-RE) information. + + eBPF programs written in C usually include Linux kernel headers, so that + they may interact with kernel data structures in a useful way. This + intrudces two major portability issues: + + 1. Kernel data structures regularly change, with fields added, moved or + deleted between versions. An eBPF program cannot in general be expected + to run on any systems which does not share an identical kernel version to + the system on which it was compiled. + + 2. Included kernel headers (and used data structures) may be internal, not + exposed in an userspace API, and therefore target-specific. An eBPF + program compiled on an x86_64 machine will include x86_64 kernel headers. + The resulting program may not run well (or at all) in machines of + another architecture. + + BPF CO-RE is designed to solve the first issue by leveraging the BPF loader + to adjust references to kernel data structures made by the program as-needed + according to versions of structures actually present on the host kernel. + + To achieve this, additional information is placed in a ".BTF.ext" section. + This information tells the loader which references will require adjusting, + and how to perform each necessary adjustment. + + For any access to a data structure which may require load-time adjustment, + the following information is recorded (making up a CO-RE relocation record): + - The BTF type ID of the outermost structure which is accessed. + - An access string encoding the accessed member via a series of member and + array indexes. These indexes are used to look up detailed BTF information + about the member. + - The offset of the appropriate instruction to patch in the BPF program. + - An integer specifying what kind of relocation to perform. + + A CO-RE-capable BPF loader reads this information together with the BTF + information of the program, compares it against BTF information of the host + kernel, and determines the appropriate way to patch the specified + instruction. + + Once all CO-RE relocations are resolved, the program is loaded and verified + as usual. The process can be summarized with the following diagram: + + +------------+ + | C compiler | + +-----+------+ + | BPF + BTF + CO-RE relocations + v + +------------+ + +--->| BPF loader | + | +-----+------+ + | | BPF (adapted) + BTF | v + | +------------+ + +----+ Kernel | + +------------+ + + Note that a single ELF object may contain multiple eBPF programs. As a + result, a single .BTF.ext section can contain CO-RE relocations for multiple + programs in distinct sections. */ + +/* BTF.ext debug info section. */ +static GTY (()) section * btf_ext_info_section; + +#ifndef BTF_EXT_INFO_SECTION_NAME +#define BTF_EXT_INFO_SECTION_NAME ".BTF.ext" +#endif +#define BTF_EXT_INFO_SECTION_FLAGS (SECTION_DEBUG) + +#ifndef BTF_EXT_INFO_SECTION_LABEL +#define BTF_EXT_INFO_SECTION_LABEL "Lbtfext" +#endif + +#define MAX_BTF_EXT_LABEL_BYTES 40 +static char btf_ext_info_section_label[MAX_BTF_EXT_LABEL_BYTES]; + +/* A funcinfo record, in the .BTF.ext funcinfo section. */ +struct GTY ((chain_next ("%h.next"))) btf_ext_funcinfo +{ + uint32_t type; /* Type ID of a BTF_KIND_FUNC type. */ + const char *fnname; + const char *label; + + struct btf_ext_funcinfo *next; /* Linked list to collect func_info elems. */ +}; + +/* A lineinfo record, in the .BTF.ext lineinfo section. */ +struct GTY ((chain_next ("%h.next"))) btf_ext_lineinfo +{ + uint32_t insn_off; /* Offset of the instruction. */ + uint32_t file_name_off; /* Offset of file name in BTF string table. */ + uint32_t line_off; /* Offset of source line in BTF string table. */ + uint32_t line_col; /* Line number (bits 31-11) and column (11-0). */ + + struct btf_ext_lineinfo *next; /* Linked list to collect line_info elems. */ +}; + +/* Internal representation of a BPF CO-RE relocation record. */ +struct GTY ((chain_next ("%h.next"))) btf_ext_core_reloc { + unsigned int bpfcr_type; /* BTF type ID of container. */ + unsigned int bpfcr_astr_off; /* Offset of access string in .BTF + string table. */ + rtx_code_label * bpfcr_insn_label; /* RTX label attached to instruction + to patch. */ + enum btf_core_reloc_kind bpfcr_kind; /* Kind of relocation to perform. */ + + struct { + const char *accessor_str; + tree type; + } info; + + struct btf_ext_core_reloc *next; +}; + +/* Main data structure to keep .BTF.ext section data. */ +struct GTY ((chain_next ("%h.next"))) btf_ext_info_sec { + const char *sec_name; + uint32_t sec_name_off; /* offset to section name. */ + + struct { + uint32_t num_info; + struct btf_ext_funcinfo *head; + } func_info; + struct { + uint32_t num_info; + struct btf_ext_lineinfo *head; + } line_info; + struct { + uint32_t num_info; + struct btf_ext_core_reloc *head; + } core_info; + + struct btf_ext_info_sec *next; +}; + +static GTY (()) struct btf_ext_info_sec *btf_ext = NULL; + +/* Helper function to add a section structure to the linked list with entry + point in info static variable. */ + +static struct btf_ext_info_sec * +btfext_info_sec_find_or_add (const char *sec_name, bool add) +{ + struct btf_ext_info_sec **tmp = &btf_ext; + + while (*tmp != NULL) + { + if (strcmp ((*tmp)->sec_name, sec_name) == 0) + return *tmp; + tmp = &((*tmp)->next); + } + + if (add == false) + return NULL; + + struct btf_ext_info_sec *ret = ggc_cleared_alloc (); + *tmp = ret; + + /* Set data for section info. */ + ret->sec_name = sec_name; + ret->sec_name_off = btf_ext_add_string (sec_name); + + return ret; +} + +#define SEARCH_NODE_AND_RETURN(TYPE, FIELD, CONDITION) __extension__ ({ \ + TYPE **head = &(FIELD); \ + while (*head != NULL) \ + { \ + if (CONDITION) \ + return (*head); \ + head = &((*head)->next); \ + } \ + head; \ +}) + +/* Function to create or find a funcinfo node in info. */ + +static struct btf_ext_funcinfo * +bpf_create_or_find_funcinfo (const char *fnname, const char *sec_name, + btf_ext_info_sec **in_sec = NULL) +{ + struct btf_ext_info_sec *sec_elem = + btfext_info_sec_find_or_add (sec_name, true); + + if (in_sec != NULL) + *in_sec = sec_elem; + + struct btf_ext_funcinfo **head = + SEARCH_NODE_AND_RETURN(struct btf_ext_funcinfo, + sec_elem->func_info.head, + strcmp ((*head)->fnname, fnname) == 0); + + *head = ggc_cleared_alloc (); + (*head)->fnname = fnname; + (*head)->label = NULL; + + return *head; +} + +/* Function to create a core_reloc node in info. */ + +static struct btf_ext_core_reloc * +bpf_create_core_reloc (const char *sec_name, + struct btf_ext_info_sec **in_sec = NULL) +{ + struct btf_ext_info_sec *sec_elem = + btfext_info_sec_find_or_add (sec_name, true); + + if (in_sec != NULL) + *in_sec = sec_elem; + + struct btf_ext_core_reloc **head = + SEARCH_NODE_AND_RETURN(struct btf_ext_core_reloc, + sec_elem->core_info.head, + false); + + *head = ggc_cleared_alloc (); + + return *head; +} + +/* String caching to avoid repeated strings added to BTF string table. */ +struct GTY((chain_next ("%h.next"))) string_cache { + const char *str; + unsigned int offset; + struct string_cache *next; +}; +static GTY(()) struct string_cache *btf_ext_strings = NULL; + +unsigned int +btf_ext_add_string (const char *str) +{ + ctf_container_ref ctfc = ctf_get_tu_ctfc (); + struct string_cache **tmp = &btf_ext_strings; + while (*tmp != NULL) + { + if (strcmp ((*tmp)->str, str) == 0) + return (*tmp)->offset; + tmp = &((*tmp)->next); + } + + *tmp = ggc_cleared_alloc (); + (*tmp)->str = ggc_strdup (str); + ctf_add_string (ctfc, (*tmp)->str, &((*tmp)->offset), CTF_AUX_STRTAB); + + return (*tmp)->offset; +} + +/* Create a new BPF CO-RE relocation record, and add it to the appropriate + CO-RE section. */ +void +bpf_core_reloc_add (const tree type, const char * section_name, + const char *accessor, + rtx_code_label *label, + enum btf_core_reloc_kind kind) +{ + struct btf_ext_info_sec *sec = NULL; + struct btf_ext_core_reloc *bpfcr = bpf_create_core_reloc (section_name, &sec); + + ctf_container_ref ctfc = ctf_get_tu_ctfc (); + + /* Buffer the access string in the auxiliary strtab. */ + bpfcr->bpfcr_astr_off = 0; + if (accessor != NULL) + bpfcr->bpfcr_astr_off = btf_ext_add_string (accessor); + bpfcr->bpfcr_type = get_btf_id (ctf_lookup_tree_type (ctfc, type)); + bpfcr->bpfcr_insn_label = label; + bpfcr->bpfcr_kind = kind; + + bpfcr->info.accessor_str = accessor; + bpfcr->info.type = type; + + sec->core_info.num_info += 1; +} + +/* Return the 0-based index of the field NODE in its containing struct or union + type. */ + +int +bpf_core_get_sou_member_index (ctf_container_ref ctfc, const tree node) +{ + if (TREE_CODE (node) == FIELD_DECL) + { + const tree container = DECL_CONTEXT (node); + + /* Lookup the CTF type info for the containing type. */ + dw_die_ref die = lookup_type_die (container); + if (die == NULL) + return -1; + + ctf_dtdef_ref dtd = ctf_dtd_lookup (ctfc, die); + if (dtd == NULL) + return -1; + + unsigned int kind = CTF_V2_INFO_KIND (dtd->dtd_data.ctti_info); + if (kind != CTF_K_STRUCT && kind != CTF_K_UNION) + return -1; + + tree field = TYPE_FIELDS (container); + int i = 0; + ctf_dmdef_t * dmd; + for (dmd = dtd->dtd_u.dtu_members; + dmd != NULL; dmd = (ctf_dmdef_t *) ctf_dmd_list_next (dmd)) + { + bool field_has_btf = get_btf_id (dmd->dmd_type) <= BTF_MAX_TYPE; + + if (field == node) + return field_has_btf ? i : -1; + + if (field_has_btf) + i++; + + field = DECL_CHAIN (field); + } + } + return -1; +} + +/* Helper function to check if a particular named function exists as a + BTF_KIND_FUNC type record. */ + +static bool +btf_funcinfo_type_callback (ctf_dtdef_ref func, void *data) +{ + struct btf_ext_funcinfo *info = (struct btf_ext_funcinfo *) data; + if (strcmp (func->dtd_name, info->fnname) == 0) + { + uint32_t type = func->dtd_type; + info->type = type; + return true; + } + return false; +} + +/* Entry point function to add a func_info in local data structures + represented by info static variable. + This function is used in bpf.cc. */ + +struct btf_ext_funcinfo * +btf_add_func_info_for (tree decl, const char *label) +{ + const char *fnname = IDENTIFIER_POINTER (DECL_NAME (decl)); + const char *sec_name = decl_section_name (decl); + + /* Recover the original function name, which may have been mangled by + optimizations. */ + const char *cp_ptr = strstr (fnname, "."); + if (cp_ptr != NULL) + { + char new_name[100]; + strcpy (new_name, fnname); + int pos = cp_ptr - fnname; + new_name[pos] = 0; + fnname = ggc_strdup (new_name); + } + + if (sec_name == NULL) + sec_name = ".text"; + + struct btf_ext_info_sec *sec = NULL; + struct btf_ext_funcinfo *info = + bpf_create_or_find_funcinfo (fnname, sec_name, &sec); + + info->label = label; + return info; +} + +/* This function traverses all func_info entries and verified they do have a + BTF_KIND_FUNC type record associated. If they do not it is marked as + invalided by clearing the associated label. */ + +static void +btf_validate_funcinfo (btf_ext_info_sec *sec) +{ + while (sec != NULL) + { + struct btf_ext_funcinfo *funcinfo = sec->func_info.head; + while (funcinfo != NULL) + { + bool found = traverse_btf_func_types (btf_funcinfo_type_callback, + funcinfo); + if (found == true) + sec->func_info.num_info += 1; + else + funcinfo->label = NULL; + + funcinfo = funcinfo->next; + } + sec = sec->next; + } +} + +/* Compute the section size in section for func_info, line_info and core_info + regions of .BTF.ext. */ + +static void +btf_ext_info_len (uint32_t *fi_len, uint32_t *li_len, uint32_t *cr_len) +{ + *fi_len = *li_len = *cr_len = 0; + struct btf_ext_info_sec *tmp = btf_ext; + if (tmp != NULL) + while (tmp != NULL) + { + /* Size computation does 8 bytes per section entry plus num_info of the + * respective structure size: + - 8 bytes for func_info, + - 16 bytes for both line_info and core_info. */ + if (tmp->func_info.num_info > 0) + *fi_len += 8 + (8 * tmp->func_info.num_info); + if (tmp->line_info.num_info > 0) + *li_len += 8 + (16 * tmp->line_info.num_info); + if (tmp->core_info.num_info > 0) + *cr_len += 8 + (16 * tmp->core_info.num_info); + tmp = tmp->next; + } + + /* If there are entries within the regions, add 4 bytes to set the header of + the respective sections that contains the size for each of the entry. */ + *fi_len += *fi_len != 0 ? 4 : 0; + *li_len += *li_len != 0 ? 4 : 0; + *cr_len += *cr_len != 0 ? 4 : 0; +} + +/* Compute and output the header of a .BTF.ext debug info section. */ + +static void +output_btfext_header (void) +{ + switch_to_section (btf_ext_info_section); + ASM_OUTPUT_LABEL (asm_out_file, btf_ext_info_section_label); + + dw2_asm_output_data (2, BTF_MAGIC, "btf_magic"); + dw2_asm_output_data (1, BTF_VERSION, "btfext_version"); + dw2_asm_output_data (1, 0, "btfext_flags"); + dw2_asm_output_data (4, sizeof (struct btf_ext_header), "btfext_hdr_len"); + + btf_validate_funcinfo (btf_ext); + + uint32_t func_info_len = 0; + uint32_t line_info_len = 0; + uint32_t core_info_len = 0; + btf_ext_info_len (&func_info_len, &line_info_len, &core_info_len); + + if (!TARGET_BPF_CORE) + core_info_len = 0; + + uint32_t func_info_off = 0; + uint32_t line_info_off = func_info_len; + uint32_t core_info_off = line_info_off + line_info_len; + + dw2_asm_output_data (4, func_info_off, "func_info_offset"); + dw2_asm_output_data (4, func_info_len, "func_info_len"); + + dw2_asm_output_data (4, line_info_off, "line_info_offset"); + dw2_asm_output_data (4, line_info_len, "line_info_len"); + + dw2_asm_output_data (4, core_info_off, "core_relo_offset"); + dw2_asm_output_data (4, core_info_len, "core_relo_len"); +} + +/* Outputs func_info region on .BTF.ext. */ + +static void +output_btfext_func_info (struct btf_ext_info_sec *sec) +{ + unsigned int str_aux_off = ctfc_get_strtab_len (ctf_get_tu_ctfc (), + CTF_STRTAB); + bool executed = false; + while (sec != NULL) + { + uint32_t count = 0; + if (sec->func_info.num_info > 0) + { + if (executed == false && (executed = true)) + dw2_asm_output_data (4, 8, "FuncInfo entry size"); + dw2_asm_output_data (4, sec->sec_name_off + str_aux_off, + "FuncInfo section string for %s", + sec->sec_name); + dw2_asm_output_data (4, sec->func_info.num_info, "Number of entries"); + + struct btf_ext_funcinfo *elem = sec->func_info.head; + while (elem != NULL) + { + if (elem->label != NULL) + { + count += 1; + dw2_asm_output_offset (4, elem->label, + NULL, "label for function %s", elem->fnname); + dw2_asm_output_data (4, elem->type, "btf_type_id"); + } + elem = elem->next; + } + } + + gcc_assert (count == sec->func_info.num_info); + sec = sec->next; + } +} + +/* Output all CO-RE relocation sections. */ + +static void +output_btfext_core_sections (void) +{ + struct btf_ext_info_sec *sec = btf_ext; + unsigned int str_aux_off = ctfc_get_strtab_len (ctf_get_tu_ctfc (), + CTF_STRTAB); + bool executed = false; + while (sec != NULL) + { + uint32_t count = 0; + if (sec->core_info.num_info > 0) + { + if (executed == false && (executed = true)) + dw2_asm_output_data (4, 16, "CoreInfo entry size"); + dw2_asm_output_data (4, sec->sec_name_off + str_aux_off, + "CoreInfo section string for %s", + sec->sec_name); + dw2_asm_output_data (4, sec->core_info.num_info, "Number of entries"); + + struct btf_ext_core_reloc *bpfcr = sec->core_info.head; + while (bpfcr != NULL) + { + count += 1; + dw2_assemble_integer (4, + gen_rtx_LABEL_REF (Pmode, bpfcr->bpfcr_insn_label)); + fprintf (asm_out_file, "\t%s%s\n", + flag_debug_asm ? ASM_COMMENT_START : "", + (flag_debug_asm ? " bpfcr_insn" : "")); + + /* Extract the pretty print for the type expression. */ + pretty_printer pp; + dump_generic_node (&pp, bpfcr->info.type, 0, + TDF_VOPS|TDF_MEMSYMS|TDF_SLIM, + false); + char *str = xstrdup (pp_formatted_text (&pp)); + + dw2_asm_output_data (4, bpfcr->bpfcr_type, "bpfcr_type (%s)", + str); + dw2_asm_output_data (4, bpfcr->bpfcr_astr_off + str_aux_off, + "bpfcr_astr_off (\"%s\")", + bpfcr->info.accessor_str); + dw2_asm_output_data (4, bpfcr->bpfcr_kind, "bpfcr_kind"); + bpfcr = bpfcr->next; + } + } + + gcc_assert (count == sec->core_info.num_info); + sec = sec->next; + } +} + +/* Initialize sections, labels, and data structures for BTF.ext output. */ + +void +btf_ext_init (void) +{ + btf_ext_info_section = get_section (BTF_EXT_INFO_SECTION_NAME, + BTF_EXT_INFO_SECTION_FLAGS, NULL); + + ASM_GENERATE_INTERNAL_LABEL (btf_ext_info_section_label, + "Lbtfext", 0); +} + +/* Output the entire .BTF.ext section. */ + +void +btf_ext_output (void) +{ + output_btfext_header (); + output_btfext_func_info (btf_ext); + if (TARGET_BPF_CORE) + output_btfext_core_sections (); + + /* Extra padding required by BPF code, in case all structures are empty. */ + dw2_asm_output_data (4, 0, "Required padding by libbpf structs"); +} + +#include "gt-btfext-out.h" diff --git a/gcc/config/bpf/btfext-out.h b/gcc/config/bpf/btfext-out.h new file mode 100644 index 0000000..b363094 --- /dev/null +++ b/gcc/config/bpf/btfext-out.h @@ -0,0 +1,108 @@ +/* btfext-out.h - Declarations and definitions related to + BPF Compile Once - Run Everywhere (CO-RE) support. + Copyright (C) 2021-2024 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + + +#ifndef __COREOUT_H +#define __COREOUT_H + +#include +#include "ctfc.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* .BTF.ext information. */ + +struct btf_ext_section_header +{ + uint32_t sec_name_off; + uint32_t num_records; +}; + +enum btf_core_reloc_kind +{ + BPF_RELO_INVALID = -1, + BPF_RELO_FIELD_BYTE_OFFSET = 0, + BPF_RELO_FIELD_BYTE_SIZE = 1, + BPF_RELO_FIELD_EXISTS = 2, + BPF_RELO_FIELD_SIGNED = 3, + BPF_RELO_FIELD_LSHIFT_U64 = 4, + BPF_RELO_FIELD_RSHIFT_U64 = 5, + BPF_RELO_TYPE_ID_LOCAL = 6, + BPF_RELO_TYPE_ID_TARGET = 7, + BPF_RELO_TYPE_EXISTS = 8, + BPF_RELO_TYPE_SIZE = 9, + BPF_RELO_ENUMVAL_EXISTS = 10, + BPF_RELO_ENUMVAL_VALUE = 11, + BPF_RELO_TYPE_MATCHES = 12 +}; + +struct btf_ext_reloc +{ + uint32_t insn_off; /* Offset of instruction to be patched. A + section-relative label at compile time. */ + uint32_t type_id; /* Type ID of the outermost containing entity, e.g. + the containing structure. */ + uint32_t access_str_off; /* Offset of CO-RE accessor string in .BTF strings + section. */ + uint32_t kind; /* An enum btf_core_reloc_kind. Note that it always + takes 32 bits. */ +}; + +struct btf_ext_header +{ + uint16_t magic; /* Magic number (BTF_MAGIC). */ + uint8_t version; /* Data format version (BTF_VERSION). */ + uint8_t flags; /* Flags. Currently unused. */ + uint32_t hdr_len; /* Length of this header in bytes. */ + + /* Following offsets are relative to the end of this header, in bytes. + Following lengths are in bytes. */ + uint32_t func_info_off; /* Offset of funcinfo section. */ + uint32_t func_info_len; /* Length of funcinfo section. */ + uint32_t line_info_off; /* Offset of lineinfo section. */ + uint32_t line_info_len; /* Length of lineinfo section. */ + + uint32_t core_relo_off; /* Offset of CO-RE relocation section. */ + uint32_t core_relo_len; /* Length of CO-RE relocation section. */ +}; + +extern void btf_ext_init (void); +extern void btf_ext_output (void); + +void +bpf_core_reloc_add (const tree type, const char * section_name, + const char *accessor, + rtx_code_label *label, + enum btf_core_reloc_kind kind); + +extern int bpf_core_get_sou_member_index (ctf_container_ref, const tree); + +struct btf_ext_funcinfo *btf_add_func_info_for (tree decl, + const char *label); +unsigned int btf_ext_add_string (const char *str); + +#ifdef __cplusplus +} +#endif + +#endif /* __COREOUT_H */ diff --git a/gcc/config/bpf/core-builtins.cc b/gcc/config/bpf/core-builtins.cc index aa75fd6..8d8c54c 100644 --- a/gcc/config/bpf/core-builtins.cc +++ b/gcc/config/bpf/core-builtins.cc @@ -45,7 +45,7 @@ along with GCC; see the file COPYING3. If not see #include "ctfc.h" #include "btf.h" -#include "coreout.h" +#include "btfext-out.h" #include "core-builtins.h" /* BPF CO-RE builtins definition. diff --git a/gcc/config/bpf/core-builtins.h b/gcc/config/bpf/core-builtins.h index c54f6dd..e56b55b 100644 --- a/gcc/config/bpf/core-builtins.h +++ b/gcc/config/bpf/core-builtins.h @@ -1,7 +1,7 @@ #ifndef BPF_CORE_BUILTINS_H #define BPF_CORE_BUILTINS_H -#include "coreout.h" +#include "btfext-out.h" enum bpf_builtins { diff --git a/gcc/config/bpf/coreout.cc b/gcc/config/bpf/coreout.cc deleted file mode 100644 index 1406652..0000000 --- a/gcc/config/bpf/coreout.cc +++ /dev/null @@ -1,617 +0,0 @@ -/* BPF Compile Once - Run Everywhere (CO-RE) support. - Copyright (C) 2021-2024 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - . */ - -#define IN_TARGET_CODE 1 - -#include "config.h" -#include "system.h" -#include "coretypes.h" -#include "target.h" -#include "memmodel.h" -#include "tm_p.h" -#include "output.h" -#include "dwarf2asm.h" -#include "ctfc.h" -#include "btf.h" -#include "rtl.h" -#include "tree-pretty-print.h" -#include "cgraph.h" - -#include "coreout.h" - -/* This file contains data structures and routines for construction and output - of BPF Compile Once - Run Everywhere (BPF CO-RE) information. - - eBPF programs written in C usually include Linux kernel headers, so that - they may interact with kernel data structures in a useful way. This - intrudces two major portability issues: - - 1. Kernel data structures regularly change, with fields added, moved or - deleted between versions. An eBPF program cannot in general be expected - to run on any systems which does not share an identical kernel version to - the system on which it was compiled. - - 2. Included kernel headers (and used data structures) may be internal, not - exposed in an userspace API, and therefore target-specific. An eBPF - program compiled on an x86_64 machine will include x86_64 kernel headers. - The resulting program may not run well (or at all) in machines of - another architecture. - - BPF CO-RE is designed to solve the first issue by leveraging the BPF loader - to adjust references to kernel data structures made by the program as-needed - according to versions of structures actually present on the host kernel. - - To achieve this, additional information is placed in a ".BTF.ext" section. - This information tells the loader which references will require adjusting, - and how to perform each necessary adjustment. - - For any access to a data structure which may require load-time adjustment, - the following information is recorded (making up a CO-RE relocation record): - - The BTF type ID of the outermost structure which is accessed. - - An access string encoding the accessed member via a series of member and - array indexes. These indexes are used to look up detailed BTF information - about the member. - - The offset of the appropriate instruction to patch in the BPF program. - - An integer specifying what kind of relocation to perform. - - A CO-RE-capable BPF loader reads this information together with the BTF - information of the program, compares it against BTF information of the host - kernel, and determines the appropriate way to patch the specified - instruction. - - Once all CO-RE relocations are resolved, the program is loaded and verified - as usual. The process can be summarized with the following diagram: - - +------------+ - | C compiler | - +-----+------+ - | BPF + BTF + CO-RE relocations - v - +------------+ - +--->| BPF loader | - | +-----+------+ - | | BPF (adapted) - BTF | v - | +------------+ - +----+ Kernel | - +------------+ - - Note that a single ELF object may contain multiple eBPF programs. As a - result, a single .BTF.ext section can contain CO-RE relocations for multiple - programs in distinct sections. */ - -/* BTF.ext debug info section. */ -static GTY (()) section * btf_ext_info_section; - -#ifndef BTF_EXT_INFO_SECTION_NAME -#define BTF_EXT_INFO_SECTION_NAME ".BTF.ext" -#endif -#define BTF_EXT_INFO_SECTION_FLAGS (SECTION_DEBUG) - -#ifndef BTF_EXT_INFO_SECTION_LABEL -#define BTF_EXT_INFO_SECTION_LABEL "Lbtfext" -#endif - -#define MAX_BTF_EXT_LABEL_BYTES 40 -static char btf_ext_info_section_label[MAX_BTF_EXT_LABEL_BYTES]; - -/* A funcinfo record, in the .BTF.ext funcinfo section. */ -struct GTY ((chain_next ("%h.next"))) btf_ext_funcinfo -{ - uint32_t type; /* Type ID of a BTF_KIND_FUNC type. */ - const char *fnname; - const char *label; - - struct btf_ext_funcinfo *next; /* Linked list to collect func_info elems. */ -}; - -/* A lineinfo record, in the .BTF.ext lineinfo section. */ -struct GTY ((chain_next ("%h.next"))) btf_ext_lineinfo -{ - uint32_t insn_off; /* Offset of the instruction. */ - uint32_t file_name_off; /* Offset of file name in BTF string table. */ - uint32_t line_off; /* Offset of source line in BTF string table. */ - uint32_t line_col; /* Line number (bits 31-11) and column (11-0). */ - - struct btf_ext_lineinfo *next; /* Linked list to collect line_info elems. */ -}; - -/* Internal representation of a BPF CO-RE relocation record. */ -struct GTY ((chain_next ("%h.next"))) btf_ext_core_reloc { - unsigned int bpfcr_type; /* BTF type ID of container. */ - unsigned int bpfcr_astr_off; /* Offset of access string in .BTF - string table. */ - rtx_code_label * bpfcr_insn_label; /* RTX label attached to instruction - to patch. */ - enum btf_core_reloc_kind bpfcr_kind; /* Kind of relocation to perform. */ - - struct { - const char *accessor_str; - tree type; - } info; - - struct btf_ext_core_reloc *next; -}; - -/* Main data structure to keep .BTF.ext section data. */ -struct GTY ((chain_next ("%h.next"))) btf_ext_info_sec { - const char *sec_name; - uint32_t sec_name_off; /* offset to section name. */ - - struct { - uint32_t num_info; - struct btf_ext_funcinfo *head; - } func_info; - struct { - uint32_t num_info; - struct btf_ext_lineinfo *head; - } line_info; - struct { - uint32_t num_info; - struct btf_ext_core_reloc *head; - } core_info; - - struct btf_ext_info_sec *next; -}; - -static GTY (()) struct btf_ext_info_sec *btf_ext = NULL; - -/* Helper function to add a section structure to the linked list with entry - point in info static variable. */ - -static struct btf_ext_info_sec * -btfext_info_sec_find_or_add (const char *sec_name, bool add) -{ - struct btf_ext_info_sec **tmp = &btf_ext; - - while (*tmp != NULL) - { - if (strcmp ((*tmp)->sec_name, sec_name) == 0) - return *tmp; - tmp = &((*tmp)->next); - } - - if (add == false) - return NULL; - - struct btf_ext_info_sec *ret = ggc_cleared_alloc (); - *tmp = ret; - - /* Set data for section info. */ - ret->sec_name = sec_name; - ret->sec_name_off = btf_ext_add_string (sec_name); - - return ret; -} - -#define SEARCH_NODE_AND_RETURN(TYPE, FIELD, CONDITION) __extension__ ({ \ - TYPE **head = &(FIELD); \ - while (*head != NULL) \ - { \ - if (CONDITION) \ - return (*head); \ - head = &((*head)->next); \ - } \ - head; \ -}) - -/* Function to create or find a funcinfo node in info. */ - -static struct btf_ext_funcinfo * -bpf_create_or_find_funcinfo (const char *fnname, const char *sec_name, - btf_ext_info_sec **in_sec = NULL) -{ - struct btf_ext_info_sec *sec_elem = - btfext_info_sec_find_or_add (sec_name, true); - - if (in_sec != NULL) - *in_sec = sec_elem; - - struct btf_ext_funcinfo **head = - SEARCH_NODE_AND_RETURN(struct btf_ext_funcinfo, - sec_elem->func_info.head, - strcmp ((*head)->fnname, fnname) == 0); - - *head = ggc_cleared_alloc (); - (*head)->fnname = fnname; - (*head)->label = NULL; - - return *head; -} - -/* Function to create a core_reloc node in info. */ - -static struct btf_ext_core_reloc * -bpf_create_core_reloc (const char *sec_name, - struct btf_ext_info_sec **in_sec = NULL) -{ - struct btf_ext_info_sec *sec_elem = - btfext_info_sec_find_or_add (sec_name, true); - - if (in_sec != NULL) - *in_sec = sec_elem; - - struct btf_ext_core_reloc **head = - SEARCH_NODE_AND_RETURN(struct btf_ext_core_reloc, - sec_elem->core_info.head, - false); - - *head = ggc_cleared_alloc (); - - return *head; -} - -/* String caching to avoid repeated strings added to BTF string table. */ -struct GTY((chain_next ("%h.next"))) string_cache { - const char *str; - unsigned int offset; - struct string_cache *next; -}; -static GTY(()) struct string_cache *btf_ext_strings = NULL; - -unsigned int -btf_ext_add_string (const char *str) -{ - ctf_container_ref ctfc = ctf_get_tu_ctfc (); - struct string_cache **tmp = &btf_ext_strings; - while (*tmp != NULL) - { - if (strcmp ((*tmp)->str, str) == 0) - return (*tmp)->offset; - tmp = &((*tmp)->next); - } - - *tmp = ggc_cleared_alloc (); - (*tmp)->str = ggc_strdup (str); - ctf_add_string (ctfc, (*tmp)->str, &((*tmp)->offset), CTF_AUX_STRTAB); - - return (*tmp)->offset; -} - -/* Create a new BPF CO-RE relocation record, and add it to the appropriate - CO-RE section. */ -void -bpf_core_reloc_add (const tree type, const char * section_name, - const char *accessor, - rtx_code_label *label, - enum btf_core_reloc_kind kind) -{ - struct btf_ext_info_sec *sec = NULL; - struct btf_ext_core_reloc *bpfcr = bpf_create_core_reloc (section_name, &sec); - - ctf_container_ref ctfc = ctf_get_tu_ctfc (); - - /* Buffer the access string in the auxiliary strtab. */ - bpfcr->bpfcr_astr_off = 0; - if (accessor != NULL) - bpfcr->bpfcr_astr_off = btf_ext_add_string (accessor); - bpfcr->bpfcr_type = get_btf_id (ctf_lookup_tree_type (ctfc, type)); - bpfcr->bpfcr_insn_label = label; - bpfcr->bpfcr_kind = kind; - - bpfcr->info.accessor_str = accessor; - bpfcr->info.type = type; - - sec->core_info.num_info += 1; -} - -/* Return the 0-based index of the field NODE in its containing struct or union - type. */ - -int -bpf_core_get_sou_member_index (ctf_container_ref ctfc, const tree node) -{ - if (TREE_CODE (node) == FIELD_DECL) - { - const tree container = DECL_CONTEXT (node); - - /* Lookup the CTF type info for the containing type. */ - dw_die_ref die = lookup_type_die (container); - if (die == NULL) - return -1; - - ctf_dtdef_ref dtd = ctf_dtd_lookup (ctfc, die); - if (dtd == NULL) - return -1; - - unsigned int kind = CTF_V2_INFO_KIND (dtd->dtd_data.ctti_info); - if (kind != CTF_K_STRUCT && kind != CTF_K_UNION) - return -1; - - tree field = TYPE_FIELDS (container); - int i = 0; - ctf_dmdef_t * dmd; - for (dmd = dtd->dtd_u.dtu_members; - dmd != NULL; dmd = (ctf_dmdef_t *) ctf_dmd_list_next (dmd)) - { - bool field_has_btf = get_btf_id (dmd->dmd_type) <= BTF_MAX_TYPE; - - if (field == node) - return field_has_btf ? i : -1; - - if (field_has_btf) - i++; - - field = DECL_CHAIN (field); - } - } - return -1; -} - -/* Helper function to check if a particular named function exists as a - BTF_KIND_FUNC type record. */ - -static bool -btf_funcinfo_type_callback (ctf_dtdef_ref func, void *data) -{ - struct btf_ext_funcinfo *info = (struct btf_ext_funcinfo *) data; - if (strcmp (func->dtd_name, info->fnname) == 0) - { - uint32_t type = func->dtd_type; - info->type = type; - return true; - } - return false; -} - -/* Entry point function to add a func_info in local data structures - represented by info static variable. - This function is used in bpf.cc. */ - -struct btf_ext_funcinfo * -btf_add_func_info_for (tree decl, const char *label) -{ - const char *fnname = IDENTIFIER_POINTER (DECL_NAME (decl)); - const char *sec_name = decl_section_name (decl); - - /* Recover the original function name, which may have been mangled by - optimizations. */ - const char *cp_ptr = strstr (fnname, "."); - if (cp_ptr != NULL) - { - char new_name[100]; - strcpy (new_name, fnname); - int pos = cp_ptr - fnname; - new_name[pos] = 0; - fnname = ggc_strdup (new_name); - } - - if (sec_name == NULL) - sec_name = ".text"; - - struct btf_ext_info_sec *sec = NULL; - struct btf_ext_funcinfo *info = - bpf_create_or_find_funcinfo (fnname, sec_name, &sec); - - info->label = label; - return info; -} - -/* This function traverses all func_info entries and verified they do have a - BTF_KIND_FUNC type record associated. If they do not it is marked as - invalided by clearing the associated label. */ - -static void -btf_validate_funcinfo (btf_ext_info_sec *sec) -{ - while (sec != NULL) - { - struct btf_ext_funcinfo *funcinfo = sec->func_info.head; - while (funcinfo != NULL) - { - bool found = traverse_btf_func_types (btf_funcinfo_type_callback, - funcinfo); - if (found == true) - sec->func_info.num_info += 1; - else - funcinfo->label = NULL; - - funcinfo = funcinfo->next; - } - sec = sec->next; - } -} - -/* Compute the section size in section for func_info, line_info and core_info - regions of .BTF.ext. */ - -static void -btf_ext_info_len (uint32_t *fi_len, uint32_t *li_len, uint32_t *cr_len) -{ - *fi_len = *li_len = *cr_len = 0; - struct btf_ext_info_sec *tmp = btf_ext; - if (tmp != NULL) - while (tmp != NULL) - { - /* Size computation does 8 bytes per section entry plus num_info of the - * respective structure size: - - 8 bytes for func_info, - - 16 bytes for both line_info and core_info. */ - if (tmp->func_info.num_info > 0) - *fi_len += 8 + (8 * tmp->func_info.num_info); - if (tmp->line_info.num_info > 0) - *li_len += 8 + (16 * tmp->line_info.num_info); - if (tmp->core_info.num_info > 0) - *cr_len += 8 + (16 * tmp->core_info.num_info); - tmp = tmp->next; - } - - /* If there are entries within the regions, add 4 bytes to set the header of - the respective sections that contains the size for each of the entry. */ - *fi_len += *fi_len != 0 ? 4 : 0; - *li_len += *li_len != 0 ? 4 : 0; - *cr_len += *cr_len != 0 ? 4 : 0; -} - -/* Compute and output the header of a .BTF.ext debug info section. */ - -static void -output_btfext_header (void) -{ - switch_to_section (btf_ext_info_section); - ASM_OUTPUT_LABEL (asm_out_file, btf_ext_info_section_label); - - dw2_asm_output_data (2, BTF_MAGIC, "btf_magic"); - dw2_asm_output_data (1, BTF_VERSION, "btfext_version"); - dw2_asm_output_data (1, 0, "btfext_flags"); - dw2_asm_output_data (4, sizeof (struct btf_ext_header), "btfext_hdr_len"); - - btf_validate_funcinfo (btf_ext); - - uint32_t func_info_len = 0; - uint32_t line_info_len = 0; - uint32_t core_info_len = 0; - btf_ext_info_len (&func_info_len, &line_info_len, &core_info_len); - - if (!TARGET_BPF_CORE) - core_info_len = 0; - - uint32_t func_info_off = 0; - uint32_t line_info_off = func_info_len; - uint32_t core_info_off = line_info_off + line_info_len; - - dw2_asm_output_data (4, func_info_off, "func_info_offset"); - dw2_asm_output_data (4, func_info_len, "func_info_len"); - - dw2_asm_output_data (4, line_info_off, "line_info_offset"); - dw2_asm_output_data (4, line_info_len, "line_info_len"); - - dw2_asm_output_data (4, core_info_off, "core_relo_offset"); - dw2_asm_output_data (4, core_info_len, "core_relo_len"); -} - -/* Outputs func_info region on .BTF.ext. */ - -static void -output_btfext_func_info (struct btf_ext_info_sec *sec) -{ - unsigned int str_aux_off = ctfc_get_strtab_len (ctf_get_tu_ctfc (), - CTF_STRTAB); - bool executed = false; - while (sec != NULL) - { - uint32_t count = 0; - if (sec->func_info.num_info > 0) - { - if (executed == false && (executed = true)) - dw2_asm_output_data (4, 8, "FuncInfo entry size"); - dw2_asm_output_data (4, sec->sec_name_off + str_aux_off, - "FuncInfo section string for %s", - sec->sec_name); - dw2_asm_output_data (4, sec->func_info.num_info, "Number of entries"); - - struct btf_ext_funcinfo *elem = sec->func_info.head; - while (elem != NULL) - { - if (elem->label != NULL) - { - count += 1; - dw2_asm_output_offset (4, elem->label, - NULL, "label for function %s", elem->fnname); - dw2_asm_output_data (4, elem->type, "btf_type_id"); - } - elem = elem->next; - } - } - - gcc_assert (count == sec->func_info.num_info); - sec = sec->next; - } -} - -/* Output all CO-RE relocation sections. */ - -static void -output_btfext_core_sections (void) -{ - struct btf_ext_info_sec *sec = btf_ext; - unsigned int str_aux_off = ctfc_get_strtab_len (ctf_get_tu_ctfc (), - CTF_STRTAB); - bool executed = false; - while (sec != NULL) - { - uint32_t count = 0; - if (sec->core_info.num_info > 0) - { - if (executed == false && (executed = true)) - dw2_asm_output_data (4, 16, "CoreInfo entry size"); - dw2_asm_output_data (4, sec->sec_name_off + str_aux_off, - "CoreInfo section string for %s", - sec->sec_name); - dw2_asm_output_data (4, sec->core_info.num_info, "Number of entries"); - - struct btf_ext_core_reloc *bpfcr = sec->core_info.head; - while (bpfcr != NULL) - { - count += 1; - dw2_assemble_integer (4, - gen_rtx_LABEL_REF (Pmode, bpfcr->bpfcr_insn_label)); - fprintf (asm_out_file, "\t%s%s\n", - flag_debug_asm ? ASM_COMMENT_START : "", - (flag_debug_asm ? " bpfcr_insn" : "")); - - /* Extract the pretty print for the type expression. */ - pretty_printer pp; - dump_generic_node (&pp, bpfcr->info.type, 0, - TDF_VOPS|TDF_MEMSYMS|TDF_SLIM, - false); - char *str = xstrdup (pp_formatted_text (&pp)); - - dw2_asm_output_data (4, bpfcr->bpfcr_type, "bpfcr_type (%s)", - str); - dw2_asm_output_data (4, bpfcr->bpfcr_astr_off + str_aux_off, - "bpfcr_astr_off (\"%s\")", - bpfcr->info.accessor_str); - dw2_asm_output_data (4, bpfcr->bpfcr_kind, "bpfcr_kind"); - bpfcr = bpfcr->next; - } - } - - gcc_assert (count == sec->core_info.num_info); - sec = sec->next; - } -} - -/* Initialize sections, labels, and data structures for BTF.ext output. */ - -void -btf_ext_init (void) -{ - btf_ext_info_section = get_section (BTF_EXT_INFO_SECTION_NAME, - BTF_EXT_INFO_SECTION_FLAGS, NULL); - - ASM_GENERATE_INTERNAL_LABEL (btf_ext_info_section_label, - "Lbtfext", 0); -} - -/* Output the entire .BTF.ext section. */ - -void -btf_ext_output (void) -{ - output_btfext_header (); - output_btfext_func_info (btf_ext); - if (TARGET_BPF_CORE) - output_btfext_core_sections (); - - /* Extra padding required by BPF code, in case all structures are empty. */ - dw2_asm_output_data (4, 0, "Required padding by libbpf structs"); -} - -#include "gt-coreout.h" diff --git a/gcc/config/bpf/coreout.h b/gcc/config/bpf/coreout.h deleted file mode 100644 index 1c26b92..0000000 --- a/gcc/config/bpf/coreout.h +++ /dev/null @@ -1,108 +0,0 @@ -/* coreout.h - Declarations and definitions related to - BPF Compile Once - Run Everywhere (CO-RE) support. - Copyright (C) 2021-2024 Free Software Foundation, Inc. - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GCC is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - . */ - - -#ifndef __COREOUT_H -#define __COREOUT_H - -#include -#include "ctfc.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/* .BTF.ext information. */ - -struct btf_ext_section_header -{ - uint32_t sec_name_off; - uint32_t num_records; -}; - -enum btf_core_reloc_kind -{ - BPF_RELO_INVALID = -1, - BPF_RELO_FIELD_BYTE_OFFSET = 0, - BPF_RELO_FIELD_BYTE_SIZE = 1, - BPF_RELO_FIELD_EXISTS = 2, - BPF_RELO_FIELD_SIGNED = 3, - BPF_RELO_FIELD_LSHIFT_U64 = 4, - BPF_RELO_FIELD_RSHIFT_U64 = 5, - BPF_RELO_TYPE_ID_LOCAL = 6, - BPF_RELO_TYPE_ID_TARGET = 7, - BPF_RELO_TYPE_EXISTS = 8, - BPF_RELO_TYPE_SIZE = 9, - BPF_RELO_ENUMVAL_EXISTS = 10, - BPF_RELO_ENUMVAL_VALUE = 11, - BPF_RELO_TYPE_MATCHES = 12 -}; - -struct btf_ext_reloc -{ - uint32_t insn_off; /* Offset of instruction to be patched. A - section-relative label at compile time. */ - uint32_t type_id; /* Type ID of the outermost containing entity, e.g. - the containing structure. */ - uint32_t access_str_off; /* Offset of CO-RE accessor string in .BTF strings - section. */ - uint32_t kind; /* An enum btf_core_reloc_kind. Note that it always - takes 32 bits. */ -}; - -struct btf_ext_header -{ - uint16_t magic; /* Magic number (BTF_MAGIC). */ - uint8_t version; /* Data format version (BTF_VERSION). */ - uint8_t flags; /* Flags. Currently unused. */ - uint32_t hdr_len; /* Length of this header in bytes. */ - - /* Following offsets are relative to the end of this header, in bytes. - Following lengths are in bytes. */ - uint32_t func_info_off; /* Offset of funcinfo section. */ - uint32_t func_info_len; /* Length of funcinfo section. */ - uint32_t line_info_off; /* Offset of lineinfo section. */ - uint32_t line_info_len; /* Length of lineinfo section. */ - - uint32_t core_relo_off; /* Offset of CO-RE relocation section. */ - uint32_t core_relo_len; /* Length of CO-RE relocation section. */ -}; - -extern void btf_ext_init (void); -extern void btf_ext_output (void); - -void -bpf_core_reloc_add (const tree type, const char * section_name, - const char *accessor, - rtx_code_label *label, - enum btf_core_reloc_kind kind); - -extern int bpf_core_get_sou_member_index (ctf_container_ref, const tree); - -struct btf_ext_funcinfo *btf_add_func_info_for (tree decl, - const char *label); -unsigned int btf_ext_add_string (const char *str); - -#ifdef __cplusplus -} -#endif - -#endif /* __COREOUT_H */ diff --git a/gcc/config/bpf/t-bpf b/gcc/config/bpf/t-bpf index 18f1fa6..dc50332 100644 --- a/gcc/config/bpf/t-bpf +++ b/gcc/config/bpf/t-bpf @@ -1,7 +1,7 @@ -TM_H += $(srcdir)/config/bpf/coreout.h $(srcdir)/config/bpf/core-builtins.h +TM_H += $(srcdir)/config/bpf/btfext-out.h $(srcdir)/config/bpf/core-builtins.h -coreout.o: $(srcdir)/config/bpf/coreout.cc +btfext-out.o: $(srcdir)/config/bpf/btfext-out.cc $(COMPILE) $< $(POSTCOMPILE) -- cgit v1.1 From 29ac92436aa5c702e9e02c206e7590ebd806398e Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 28 Feb 2024 23:20:13 +0100 Subject: c++: Fix explicit instantiation of const variable templates after earlier implicit instantation [PR113976] Already previously instantiated const variable templates had cp_apply_type_quals_to_decl called when they were instantiated, but if they need runtime initialization, their TREE_READONLY flag has been subsequently cleared. Explicit variable template instantiation calls grokdeclarator which calls cp_apply_type_quals_to_decl on them again, setting TREE_READONLY flag again, but nothing clears it afterwards, so we emit such instantiations into rodata sections and segfault when the dynamic initialization attempts to initialize them. The following patch fixes that by not calling cp_apply_type_quals_to_decl on already instantiated variable declarations. 2024-02-28 Jakub Jelinek Patrick Palka PR c++/113976 * decl.cc (grokdeclarator): Don't call cp_apply_type_quals_to_decl on DECL_TEMPLATE_INSTANTIATED VAR_DECLs. * g++.dg/cpp1y/var-templ87.C: New test. --- gcc/cp/decl.cc | 7 +++++- gcc/testsuite/g++.dg/cpp1y/var-templ87.C | 43 ++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/cpp1y/var-templ87.C (limited to 'gcc') diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc index d19d09a..05e4600 100644 --- a/gcc/cp/decl.cc +++ b/gcc/cp/decl.cc @@ -15259,7 +15259,12 @@ grokdeclarator (const cp_declarator *declarator, /* Record constancy and volatility on the DECL itself . There's no need to do this when processing a template; we'll do this for the instantiated declaration based on the type of DECL. */ - if (!processing_template_decl) + if (!processing_template_decl + /* Don't do it for instantiated variable templates either, + cp_apply_type_quals_to_decl should have been called on it + already and might have been overridden in cp_finish_decl + if initializer needs runtime initialization. */ + && (!VAR_P (decl) || !DECL_TEMPLATE_INSTANTIATED (decl))) cp_apply_type_quals_to_decl (type_quals, decl); return decl; diff --git a/gcc/testsuite/g++.dg/cpp1y/var-templ87.C b/gcc/testsuite/g++.dg/cpp1y/var-templ87.C new file mode 100644 index 0000000..e62d06d --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/var-templ87.C @@ -0,0 +1,43 @@ +// PR c++/113976 +// { dg-do run { target c++14 } } + +int +foo () +{ + return 42; +} + +template +const int a = foo (); +const int *b = &a <0>; +template +const int c = foo (); +template const int c <0>; +template +const int d = foo (); +const int *e = &d <0>; +template const int d <0>; +template +const int f = foo (); +template const int f <0>; +const int *g = &f <0>; +struct S { int a, b; }; +template +const S h = { 42, foo () }; +const S *i = &h <0>; +template +const S j = { 42, foo () }; +template const S j <0>; +template +const S k = { 42, foo () }; +const S *l = &k <0>; +template const S k <0>; +template +const S m = { 42, foo () }; +template const S m <0>; +const S *n = &m <0>; + +int +main () +{ +} -- cgit v1.1 From fd52355aa5796746b2d515223e466ce13b8acff5 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Thu, 29 Feb 2024 00:16:43 +0000 Subject: Daily bump. --- gcc/ChangeLog | 107 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog | 14 +++++++ gcc/testsuite/ChangeLog | 70 +++++++++++++++++++++++++++++++ 4 files changed, 192 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3fde83d..10fa428 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,110 @@ +2024-02-28 Cupertino Miranda + + * config.gcc (target_gtfiles): Change coreout to btfext-out. + (extra_objs): Change coreout to btfext-out. + * config/bpf/coreout.cc: Rename to btfext-out.cc. + * config/bpf/btfext-out.cc: Add. + * config/bpf/coreout.h: Rename to btfext-out.h. + * config/bpf/btfext-out.h: Add. + * config/bpf/core-builtins.cc: Change include. + * config/bpf/core-builtins.h: Change include. + * config/bpf/t-bpf: Accomodate renamed files. + +2024-02-28 Cupertino Miranda + + PR target/113453 + * config/bpf/bpf.cc (bpf_function_prologue): Define target + hook. + * config/bpf/coreout.cc (brf_ext_info_section) + (btf_ext_info): Move from coreout.h + (btf_ext_funcinfo, btf_ext_lineinfo): Add struct. + (bpf_core_reloc): Rename to btf_ext_core_reloc. + (btf_ext): Add static variable. + (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN) + (bpf_create_or_find_funcinfo, bpt_create_core_reloc) + (btf_ext_add_string, btf_funcinfo_type_callback) + (btf_add_func_info_for, btf_validate_funcinfo) + (btf_ext_info_len, output_btfext_func_info): Add function. + (output_btfext_header, bpf_core_reloc_add) + (output_btfext_core_relocs, btf_ext_init, btf_ext_output): + Change to support new structs. + * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo): + Move and change in coreout.cc. + (btf_add_func_info_for, btf_ext_add_string): Add prototypes. + +2024-02-28 Cupertino Miranda + + * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext + enabled by default for BPF. + (bpf_file_end): Call BTF deallocation. + (bpf_asm_init_sections): Correct condition. + * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF + deallocation. + (ctf_debuf_finish): Correct condition for calling + ctf_debug_finalize. + +2024-02-28 Cupertino Miranda + + * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT. + (traverse_btf_func_types): Define function. + * ctfc.h (funcs_traverse_callback): Typedef for function + prototype. + (traverse_btf_func_types): Add prototype. + +2024-02-28 Cupertino Miranda + + * btfout.cc (btf_collect_dataset): Corrects BTF type id. + +2024-02-28 Richard Biener + + PR tree-optimization/113831 + PR tree-optimization/108355 + * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert + PR113831 fix. + +2024-02-28 Richard Biener + + PR tree-optimization/114121 + * tree-ssa-sccvn.h (vn_reference_s::offset, + vn_reference_s::max_size): New fields. + (vn_reference_insert_pieces): Adjust prototype. + * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size. + * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and + size, allow using "don't know" state. + (vn_walk_cb_data::finish): Pass along offset/max_size. + (vn_reference_lookup_or_insert_for_pieces): Take offset and + max_size as argument and use it. + (vn_reference_lookup_3): Properly adjust offset and max_size + according to the adjusted ao_ref. + (vn_reference_lookup_pieces): Initialize offset and max_size. + (vn_reference_lookup): Likewise. + (vn_reference_lookup_call): Likewise. + (vn_reference_insert): Likewise. + (visit_reference_op_call): Likewise. + (vn_reference_insert_pieces): Take offset and max_size + as argument and use it. + +2024-02-28 Juergen Christ + + PR tree-optimization/114075 + * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating + point vectors + +2024-02-28 Jakub Jelinek + + PR tree-optimization/114041 + * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for + INTEGRAL_TYPE_P check rather than INTEGER_TYPE. + +2024-02-28 Jakub Jelinek + + PR tree-optimization/113988 + * stor-layout.h (bitwise_mode_for_size): Declare. + * stor-layout.cc (bitwise_mode_for_size): New function. + * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it. + Use bitwise_type_for_mode instead of build_nonstandard_integer_type. + Use BITS_PER_UNIT instead of 8. + 2024-02-27 Uros Bizjak PR target/113871 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 4b3cebb..4c39afe 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240228 +20240229 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index e1a4084..1ff86c8 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,17 @@ +2024-02-28 Jakub Jelinek + Patrick Palka + + PR c++/113976 + * decl.cc (grokdeclarator): Don't call cp_apply_type_quals_to_decl + on DECL_TEMPLATE_INSTANTIATED VAR_DECLs. + +2024-02-28 Nathaniel Shead + + PR c++/113970 + PR c++/114013 + * decl.cc (make_rtl_for_nonlocal_decl): Don't defer inline + variables. + 2024-02-23 Jakub Jelinek PR c++/113083 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5b73bbb..1cb1870 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,73 @@ +2024-02-28 Jakub Jelinek + Patrick Palka + + PR c++/113976 + * g++.dg/cpp1y/var-templ87.C: New test. + +2024-02-28 Cupertino Miranda + + PR target/113453 + PR target/113453 + * gcc.target/bpf/btfext-funcinfo-nocore.c: Add. + * gcc.target/bpf/btfext-funcinfo.c: Add. + * gcc.target/bpf/core-attr-5.c: Fix regexp. + * gcc.target/bpf/core-attr-6.c: Fix regexp. + * gcc.target/bpf/core-builtin-fieldinfo-offset-1.c: Fix regexp. + * gcc.target/bpf/core-section-1.c: Fix regexp. + +2024-02-28 Harald Anlauf + + * gfortran.dg/pr101026.f: Let variables used in specification + expression be passed as dummy arguments + +2024-02-28 Richard Biener + + PR tree-optimization/113831 + PR tree-optimization/108355 + * gcc.dg/tree-ssa/ssa-fre-104.c: XFAIL. + +2024-02-28 Richard Biener + + PR tree-optimization/114121 + * gcc.dg/torture/pr114121.c: New testcase. + +2024-02-28 Jakub Jelinek + + PR testsuite/111462 + * gcc.dg/tree-ssa/ssa-sink-18.c: XFAIL also on powerpc64. + +2024-02-28 Rainer Orth + + PR tree-optimization/91567 + * gcc.dg/tree-ssa/builtin-snprintf-6.c (scan-tree-dump-times): + Treat i?86-*-* like x86_64-*-*. + +2024-02-28 Jakub Jelinek + + PR tree-optimization/114075 + * gcc.dg/gomp/pr114075.c: New test. + +2024-02-28 Jakub Jelinek + + PR tree-optimization/114041 + * gcc.dg/graphite/run-id-pr114041-1.c: New test. + * gcc.dg/graphite/run-id-pr114041-2.c: New test. + +2024-02-28 Jakub Jelinek + + PR tree-optimization/113988 + * gcc.dg/bitint-91.c: New test. + +2024-02-28 Jakub Jelinek + + * gcc.dg/c23-stdarg-6.c: New test. + +2024-02-28 Nathaniel Shead + + PR c++/113970 + PR c++/114013 + * g++.dg/cpp1z/inline-var10.C: New test. + 2024-02-27 Uros Bizjak PR target/113871 -- cgit v1.1 From edfe198084338691d0facc86bf8dfa6ede3ca676 Mon Sep 17 00:00:00 2001 From: Alexander Westbrooks Date: Wed, 28 Feb 2024 20:03:46 -0600 Subject: Fortran - Error compiling PDT Type-bound Procedures [PR82943/86148/86268] This patch allows parameterized derived types to compile successfully when typebound procedures are specified in the type specification. Furthermore, it allows function calls for PDTs by setting the f2k_derived space of PDT instances to reference their original template, thereby giving it referential access to the typebound procedures of the template. Lastly, it adds a check for deferred length parameters of PDTs in CLASS declaration statements, and correctly throws an error if such declarations are missing POINTER or ALLOCATABLE attributes. 2024-02-25 Alexander Westbrooks gcc/fortran/ChangeLog: PR fortran/82943 PR fortran/86148 PR fortran/86268 * decl.cc (gfc_get_pdt_instance): Set the PDT instance field 'f2k_derived', if not set already, to point to the given PDT template 'f2k_derived' namespace in order to give the PDT instance referential access to the typebound procedures of the template. * gfortran.h (gfc_pdt_is_instance_of): Add prototype. * resolve.cc (resolve_typebound_procedure): If the derived type does not have the attribute 'pdt_template' set, compare the dummy argument to the 'resolve_bindings_derived' type like usual. If the derived type is a 'pdt_template', then check if the dummy argument is an instance of the PDT template. If the derived type is a PDT template, and the dummy argument is an instance of that template, but the dummy argument 'param_list' is not SPEC_ASSUMED, check if there are any LEN parameters in the dummy argument. If there are no LEN parameters, then this implies that there are only KIND parameters in the dummy argument. If there are LEN parameters, this would be an error, for all LEN parameters for the dummy argument MUST be assumed for typebound procedures of PDTs. (resolve_pdt): Add a check for ALLOCATABLE and POINTER attributes for SPEC_DEFERRED parameters of PDT class symbols. ALLOCATABLE and POINTER attributes for a PDT class symbol are stored in the 'class_pointer' and 'allocatable' attributes of the '_data' component respectively. * symbol.cc (gfc_pdt_is_instance_of): New function. gcc/testsuite/ChangeLog: PR fortran/82943 PR fortran/86148 PR fortran/86268 * gfortran.dg/pdt_4.f03: Update modified error message. * gfortran.dg/pdt_34.f03: New test. * gfortran.dg/pdt_35.f03: New test. * gfortran.dg/pdt_36.f03: New test. * gfortran.dg/pdt_37.f03: New test. Signed-off-by: Alexander Westbrooks --- gcc/fortran/decl.cc | 15 ++++++++ gcc/fortran/gfortran.h | 1 + gcc/fortran/resolve.cc | 74 +++++++++++++++++++++++++++++++----- gcc/fortran/symbol.cc | 27 +++++++++++++ gcc/testsuite/gfortran.dg/pdt_34.f03 | 42 ++++++++++++++++++++ gcc/testsuite/gfortran.dg/pdt_35.f03 | 45 ++++++++++++++++++++++ gcc/testsuite/gfortran.dg/pdt_36.f03 | 65 +++++++++++++++++++++++++++++++ gcc/testsuite/gfortran.dg/pdt_37.f03 | 74 ++++++++++++++++++++++++++++++++++++ gcc/testsuite/gfortran.dg/pdt_4.f03 | 2 +- 9 files changed, 335 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/pdt_34.f03 create mode 100644 gcc/testsuite/gfortran.dg/pdt_35.f03 create mode 100644 gcc/testsuite/gfortran.dg/pdt_36.f03 create mode 100644 gcc/testsuite/gfortran.dg/pdt_37.f03 (limited to 'gcc') diff --git a/gcc/fortran/decl.cc b/gcc/fortran/decl.cc index 503ecb8..a7576f4 100644 --- a/gcc/fortran/decl.cc +++ b/gcc/fortran/decl.cc @@ -4083,6 +4083,21 @@ gfc_get_pdt_instance (gfc_actual_arglist *param_list, gfc_symbol **sym, continue; } + /* Addressing PR82943, this will fix the issue where a function or + subroutine is declared as not a member of the PDT instance. + The reason for this is because the PDT instance did not have access + to its template's f2k_derived namespace in order to find the + typebound procedures. + + The number of references to the PDT template's f2k_derived will + ensure that f2k_derived is properly freed later on. */ + + if (!instance->f2k_derived && pdt->f2k_derived) + { + instance->f2k_derived = pdt->f2k_derived; + instance->f2k_derived->refs++; + } + /* Set the component kind using the parameterized expression. */ if ((c1->ts.kind == 0 || c1->ts.type == BT_CHARACTER) && c1->kind_expr != NULL) diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h index fd843a3..ebba233 100644 --- a/gcc/fortran/gfortran.h +++ b/gcc/fortran/gfortran.h @@ -3586,6 +3586,7 @@ void gfc_traverse_gsymbol (gfc_gsymbol *, void (*)(gfc_gsymbol *, void *), void gfc_typebound_proc* gfc_get_typebound_proc (gfc_typebound_proc*); gfc_symbol* gfc_get_derived_super_type (gfc_symbol*); bool gfc_type_is_extension_of (gfc_symbol *, gfc_symbol *); +bool gfc_pdt_is_instance_of (gfc_symbol *, gfc_symbol *); bool gfc_type_compatible (gfc_typespec *, gfc_typespec *); void gfc_copy_formal_args_intr (gfc_symbol *, gfc_intrinsic_sym *, diff --git a/gcc/fortran/resolve.cc b/gcc/fortran/resolve.cc index 44f89f6..02acc4a 100644 --- a/gcc/fortran/resolve.cc +++ b/gcc/fortran/resolve.cc @@ -14760,15 +14760,69 @@ resolve_typebound_procedure (gfc_symtree* stree) goto error; } - if (CLASS_DATA (me_arg)->ts.u.derived - != resolve_bindings_derived) + /* The derived type is not a PDT template. Resolve as usual. */ + if (!resolve_bindings_derived->attr.pdt_template + && (CLASS_DATA (me_arg)->ts.u.derived != resolve_bindings_derived)) { - gfc_error ("Argument %qs of %qs with PASS(%s) at %L must be of" - " the derived-type %qs", me_arg->name, proc->name, + gfc_error ("Argument %qs of %qs with PASS(%s) at %L must be of " + "the derived-type %qs", me_arg->name, proc->name, me_arg->name, &where, resolve_bindings_derived->name); goto error; } + if (resolve_bindings_derived->attr.pdt_template + && !gfc_pdt_is_instance_of (resolve_bindings_derived, + CLASS_DATA (me_arg)->ts.u.derived)) + { + gfc_error ("Argument %qs of %qs with PASS(%s) at %L must be of " + "the parametric derived-type %qs", me_arg->name, + proc->name, me_arg->name, &where, + resolve_bindings_derived->name); + goto error; + } + + if (resolve_bindings_derived->attr.pdt_template + && gfc_pdt_is_instance_of (resolve_bindings_derived, + CLASS_DATA (me_arg)->ts.u.derived) + && (me_arg->param_list != NULL) + && (gfc_spec_list_type (me_arg->param_list, + CLASS_DATA(me_arg)->ts.u.derived) + != SPEC_ASSUMED)) + { + + /* Add a check to verify if there are any LEN parameters in the + first place. If there are LEN parameters, throw this error. + If there are only KIND parameters, then don't trigger + this error. */ + gfc_component *c; + bool seen_len_param = false; + gfc_actual_arglist *me_arg_param = me_arg->param_list; + + for (; me_arg_param; me_arg_param = me_arg_param->next) + { + c = gfc_find_component (CLASS_DATA(me_arg)->ts.u.derived, + me_arg_param->name, true, true, NULL); + + gcc_assert (c != NULL); + + if (c->attr.pdt_kind) + continue; + + /* Getting here implies that there is a pdt_len parameter + in the list. */ + seen_len_param = true; + break; + } + + if (seen_len_param) + { + gfc_error ("All LEN type parameters of the passed dummy " + "argument %qs of %qs at %L must be ASSUMED.", + me_arg->name, proc->name, &where); + goto error; + } + } + gcc_assert (me_arg->ts.type == BT_CLASS); if (CLASS_DATA (me_arg)->as && CLASS_DATA (me_arg)->as->rank != 0) { @@ -15886,11 +15940,13 @@ resolve_pdt (gfc_symbol* sym) else if (param->spec_type == SPEC_ASSUMED) assumed_len_exprs = true; - if (param->spec_type == SPEC_DEFERRED - && !attr->allocatable && !attr->pointer) - gfc_error ("The object %qs at %L has a deferred LEN " - "parameter %qs and is neither allocatable " - "nor a pointer", sym->name, &sym->declared_at, + if (param->spec_type == SPEC_DEFERRED && !attr->allocatable + && ((sym->ts.type == BT_DERIVED && !attr->pointer) + || (sym->ts.type == BT_CLASS && !attr->class_pointer))) + gfc_error ("Entity %qs at %L has a deferred LEN " + "parameter %qs and requires either the POINTER " + "or ALLOCATABLE attribute", + sym->name, &sym->declared_at, param->name); } diff --git a/gcc/fortran/symbol.cc b/gcc/fortran/symbol.cc index fddf68f..5d9852c 100644 --- a/gcc/fortran/symbol.cc +++ b/gcc/fortran/symbol.cc @@ -5172,6 +5172,33 @@ gfc_type_is_extension_of (gfc_symbol *t1, gfc_symbol *t2) return gfc_compare_derived_types (t1, t2); } +/* Check if parameterized derived type t2 is an instance of pdt template t1 + + gfc_symbol *t1 -> pdt template to verify t2 against. + gfc_symbol *t2 -> pdt instance to be verified. + + In decl.cc, gfc_get_pdt_instance, a pdt instance is given a 3 character + prefix "Pdt", followed by an underscore list of the kind parameters, + up to a maximum of 8 kind parameters. To verify if a PDT Type corresponds + to the template, this functions extracts t2's derive_type name, + and compares it to the derive_type name of t1 for compatibility. + + For example: + + t2->name = Pdtf_2_2; extract out the 'f' and compare with t1->name. */ + +bool +gfc_pdt_is_instance_of (gfc_symbol *t1, gfc_symbol *t2) +{ + if ( !t1->attr.pdt_template || !t2->attr.pdt_type ) + return false; + + /* Limit comparison to length of t1->name to ignore new kind params. */ + if ( !(strncmp (&(t2->name[3]), t1->name, strlen (t1->name)) == 0) ) + return false; + + return true; +} /* Check if two typespecs are type compatible (F03:5.1.1.2): If ts1 is nonpolymorphic, ts2 must be the same type. diff --git a/gcc/testsuite/gfortran.dg/pdt_34.f03 b/gcc/testsuite/gfortran.dg/pdt_34.f03 new file mode 100644 index 0000000..c601071 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pdt_34.f03 @@ -0,0 +1,42 @@ +! { dg-do compile } +! +! Tests the fixes for PR82943. +! +! Contributed by Alexander Westbrooks +! +module m + public :: foo, bar, foobar + + type, public :: good_type(n) + integer, len :: n = 1 + contains + procedure :: foo + end type + + type, public :: good_type2(k) + integer, kind :: k = 1 + contains + procedure :: bar + end type + + type, public :: good_type3(n, k) + integer, len :: n = 1 + integer, kind :: k = 1 + contains + procedure :: foobar + end type + + contains + subroutine foo(this) + class(good_type(*)), intent(inout) :: this + end subroutine + + subroutine bar(this) + class(good_type2(2)), intent(inout) :: this + end subroutine + + subroutine foobar(this) + class(good_type3(*,2)), intent(inout) :: this + end subroutine + + end module \ No newline at end of file diff --git a/gcc/testsuite/gfortran.dg/pdt_35.f03 b/gcc/testsuite/gfortran.dg/pdt_35.f03 new file mode 100644 index 0000000..8b99948 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pdt_35.f03 @@ -0,0 +1,45 @@ +! { dg-do compile } +! +! Tests the fixes for PR82943. +! +! This test focuses on inheritance for the type bound procedures. +! +! Contributed by Alexander Westbrooks +! +module m + + public :: foo, bar, foobar + + type, public :: goodpdt_lvl_0(a, b) + integer, kind :: a = 1 + integer, len :: b + contains + procedure :: foo + end type + + type, public, EXTENDS(goodpdt_lvl_0) :: goodpdt_lvl_1 (c) + integer, len :: c + contains + procedure :: bar + end type + + type, public, EXTENDS(goodpdt_lvl_1) :: goodpdt_lvl_2 (d) + integer, len :: d + contains + procedure :: foobar + end type + +contains + subroutine foo(this) + class(goodpdt_lvl_0(1,*)), intent(inout) :: this + end subroutine + + subroutine bar(this) + class(goodpdt_lvl_1(1,*,*)), intent(inout) :: this + end subroutine + + subroutine foobar(this) + class(goodpdt_lvl_2(1,*,*,*)), intent(inout) :: this + end subroutine + +end module \ No newline at end of file diff --git a/gcc/testsuite/gfortran.dg/pdt_36.f03 b/gcc/testsuite/gfortran.dg/pdt_36.f03 new file mode 100644 index 0000000..a351c0e --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pdt_36.f03 @@ -0,0 +1,65 @@ +! { dg-do run } +! +! Tests the fixes for PR82943. +! +! This test focuses on calling the type bound procedures in a program. +! +! Contributed by Alexander Westbrooks +! +module testmod + + public :: foo + + type, public :: tough_lvl_0(a, b) + integer, kind :: a = 1 + integer, len :: b + contains + procedure :: foo + end type + + type, public, EXTENDS(tough_lvl_0) :: tough_lvl_1 (c) + integer, len :: c + contains + procedure :: bar + end type + + type, public, EXTENDS(tough_lvl_1) :: tough_lvl_2 (d) + integer, len :: d + contains + procedure :: foobar + end type + +contains + subroutine foo(this) + class(tough_lvl_0(1,*)), intent(inout) :: this + end subroutine + + subroutine bar(this) + class(tough_lvl_1(1,*,*)), intent(inout) :: this + end subroutine + + subroutine foobar(this) + class(tough_lvl_2(1,*,*,*)), intent(inout) :: this + end subroutine + +end module + +PROGRAM testprogram + USE testmod + + TYPE(tough_lvl_0(1,5)) :: test_pdt_0 + TYPE(tough_lvl_1(1,5,6)) :: test_pdt_1 + TYPE(tough_lvl_2(1,5,6,7)) :: test_pdt_2 + + CALL test_pdt_0%foo() + + CALL test_pdt_1%foo() + CALL test_pdt_1%bar() + + CALL test_pdt_2%foo() + CALL test_pdt_2%bar() + CALL test_pdt_2%foobar() + + +END PROGRAM testprogram + \ No newline at end of file diff --git a/gcc/testsuite/gfortran.dg/pdt_37.f03 b/gcc/testsuite/gfortran.dg/pdt_37.f03 new file mode 100644 index 0000000..6753a9b --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pdt_37.f03 @@ -0,0 +1,74 @@ +! { dg-do compile } +! +! Tests the fixes for PR82943. +! +! This test focuses on the errors produced by incorrect LEN parameters for dummy +! arguments of PDT Typebound Procedures. +! +! Contributed by Alexander Westbrooks +! +module test_len_param + implicit none + type :: param_deriv_type(a) + integer, len :: a + contains + procedure :: assumed_len_param ! Good. No error expected. + procedure :: assumed_len_param_ptr ! { dg-error "must not be POINTER" } + procedure :: assumed_len_param_alloc ! { dg-error "must not be ALLOCATABLE" } + procedure :: deferred_len_param ! { dg-error "must be ASSUMED" } + procedure :: deferred_len_param_ptr ! { dg-error "must be ASSUMED" } + procedure :: deferred_len_param_alloc ! { dg-error "must be ASSUMED" } + procedure :: fixed_len_param ! { dg-error "must be ASSUMED" } + procedure :: fixed_len_param_ptr ! { dg-error "must be ASSUMED" } + procedure :: fixed_len_param_alloc ! { dg-error "must be ASSUMED" } + + end type + +contains + subroutine assumed_len_param(this) + class(param_deriv_type(*)), intent(inout) :: this ! Good. No error expected. + ! TYPE(param_deriv_type(*)), intent(inout) :: that ! Good. No error expected. + end subroutine + + subroutine assumed_len_param_ptr(this, that) + class(param_deriv_type(*)), intent(inout), pointer :: this ! Good. No error expected. + TYPE(param_deriv_type(*)), intent(inout), allocatable :: that ! Good. No error expected. + end subroutine + + subroutine assumed_len_param_alloc(this, that) + class(param_deriv_type(*)), intent(inout), allocatable :: this ! Good. No error expected. + TYPE(param_deriv_type(*)), intent(inout), allocatable :: that ! Good. No error expected. + end subroutine + + subroutine deferred_len_param(this, that) ! { dg-error "requires either the POINTER or ALLOCATABLE attribute" } + class(param_deriv_type(:)), intent(inout) :: this + TYPE(param_deriv_type(:)), intent(inout) :: that ! Good. No error expected. + end subroutine + + subroutine deferred_len_param_ptr(this, that) + class(param_deriv_type(:)), intent(inout), pointer :: this ! Good. No error expected. + TYPE(param_deriv_type(:)), intent(inout), pointer :: that ! Good. No error expected. + end subroutine + + subroutine deferred_len_param_alloc(this, that) + class(param_deriv_type(:)), intent(inout), allocatable :: this ! Good. No error expected. + TYPE(param_deriv_type(:)), intent(inout), allocatable :: that ! Good. No error expected. + end subroutine + + subroutine fixed_len_param(this, that) + class(param_deriv_type(10)), intent(inout) :: this ! Good. No error expected. + TYPE(param_deriv_type(10)), intent(inout) :: that ! Good. No error expected. + end subroutine + + subroutine fixed_len_param_ptr(this, that) + class(param_deriv_type(10)), intent(inout), pointer :: this ! Good. No error expected. + TYPE(param_deriv_type(10)), intent(inout), pointer :: that ! Good. No error expected. + end subroutine + + subroutine fixed_len_param_alloc(this, that) + class(param_deriv_type(10)), intent(inout), allocatable :: this ! Good. No error expected. + TYPE(param_deriv_type(10)), intent(inout), allocatable :: that ! Good. No error expected. + end subroutine + +end module + diff --git a/gcc/testsuite/gfortran.dg/pdt_4.f03 b/gcc/testsuite/gfortran.dg/pdt_4.f03 index 37412e4..f74ac89 100644 --- a/gcc/testsuite/gfortran.dg/pdt_4.f03 +++ b/gcc/testsuite/gfortran.dg/pdt_4.f03 @@ -96,7 +96,7 @@ contains subroutine foo(arg) type (mytype(4, *)) :: arg ! OK end subroutine - subroutine bar(arg) ! { dg-error "is neither allocatable nor a pointer" } + subroutine bar(arg) ! { dg-error "requires either the POINTER or ALLOCATABLE attribute" } type (thytype(8, :, 4)) :: arg end subroutine subroutine foobar(arg) ! OK -- cgit v1.1 From fd07a29e39f5347d6cef3e7042a32306f97a1719 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Wed, 28 Feb 2024 16:01:52 +0800 Subject: RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64 atomic_compare_and_swapsi will use lr.w to do obtain the original value, which sign extends to DI. RV64 only has DI comparisons, so we also need to sign extend the expected value to DI as otherwise the comparison will fail when the expected value has the 32nd bit set. gcc/ChangeLog: PR target/114130 * config/riscv/sync.md (atomic_compare_and_swap): Sign extend the expected value if needed. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr114130.c: New. Reviewed-by: Palmer Dabbelt --- gcc/config/riscv/sync.md | 9 +++++++++ gcc/testsuite/gcc.target/riscv/pr114130.c | 12 ++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/pr114130.c (limited to 'gcc') diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 54bb0a6..6f0b5aa 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -353,6 +353,15 @@ (match_operand:SI 7 "const_int_operand" "")] ;; mod_f "TARGET_ATOMIC" { + if (word_mode != mode && operands[3] != const0_rtx) + { + /* We don't have SI mode compare on RV64, so we need to make sure expected + value is sign-extended. */ + rtx tmp0 = gen_reg_rtx (word_mode); + emit_insn (gen_extend_insn (tmp0, operands[3], word_mode, mode, 0)); + operands[3] = simplify_gen_subreg (mode, tmp0, word_mode, 0); + } + emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2], operands[3], operands[4], operands[6], operands[7])); diff --git a/gcc/testsuite/gcc.target/riscv/pr114130.c b/gcc/testsuite/gcc.target/riscv/pr114130.c new file mode 100644 index 0000000..647e27d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114130.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64" } */ +#include + +void foo(uint32_t *p) { + uintptr_t x = *(uintptr_t *)p; + uint32_t e = !p ? 0 : (uintptr_t)p >> 1; + uint32_t d = (uintptr_t)x; + __atomic_compare_exchange(p, &e, &d, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); +} + +/* { dg-final { scan-assembler-bound {sext.w\t} >= 1 } } */ -- cgit v1.1 From 3685fae23bb00898749dfc155212c9c5cd3a0980 Mon Sep 17 00:00:00 2001 From: Nathaniel Shead Date: Fri, 16 Feb 2024 15:52:48 +1100 Subject: c++: Support lambdas attached to more places in modules [PR111710] The fix for PR107398 weakened the restrictions that lambdas must belong to namespace scope. However this was not sufficient: we also need to allow lambdas attached to FIELD_DECLs, PARM_DECLs, and TYPE_DECLs. For field decls we key the lambda to its class rather than the field itself. Otherwise we can run into issues when deduplicating the lambda's TYPE_DECL, because when loading its context we load the containing field before we've deduplicated the keyed lambda, causing mismatches; by keying to the class instead we defer checking keyed declarations until deduplication has completed. Additionally, by [basic.link] p15.2 a lambda defined anywhere in a class-specifier should not be TU-local, which includes base-class declarations, so ensure that lambdas declared there are keyed appropriately as well. Because this now requires 'DECL_MODULE_KEYED_DECLS_P' to be checked on a fairly large number of different kinds of DECLs, and that in general it's safe to just get 'false' as a result of a check on an unexpected DECL type, this patch also removes the tree checking from the accessor. Finally, to handle deduplicating templated lambda fields, we need to ensure that we can determine that two lambdas from different field decls match, so we ensure that we also deduplicate LAMBDA_EXPRs on stream in. PR c++/111710 gcc/cp/ChangeLog: * cp-tree.h (DECL_MODULE_KEYED_DECLS_P): Remove tree checking. (struct lang_decl_base): Update comments and fix whitespace. * module.cc (trees_out::lang_decl_bools): Always write module_keyed_decls_p flag... (trees_in::lang_decl_bools): ...and always read it. (trees_out::decl_value): Handle all kinds of keyed decls. (trees_in::decl_value): Likewise. (trees_in::tree_value): Deduplicate LAMBDA_EXPRs. (maybe_key_decl): Also support lambdas attached to fields, parameters, and types. Key lambdas attached to fields to their class. (trees_out::get_merge_kind): Likewise. (trees_out::key_mergeable): Likewise. (trees_in::key_mergeable): Support keyed decls in a TYPE_DECL container. * parser.cc (cp_parser_class_head): Start a lambda scope when parsing base classes. gcc/testsuite/ChangeLog: * g++.dg/modules/lambda-7.h: New test. * g++.dg/modules/lambda-7_a.H: New test. * g++.dg/modules/lambda-7_b.C: New test. * g++.dg/modules/lambda-7_c.C: New test. Signed-off-by: Nathaniel Shead Reviewed-by: Patrick Palka Reviewed-by: Jason Merrill --- gcc/cp/cp-tree.h | 26 ++++---- gcc/cp/module.cc | 101 ++++++++++++++++++------------ gcc/cp/parser.cc | 10 ++- gcc/testsuite/g++.dg/modules/lambda-7.h | 42 +++++++++++++ gcc/testsuite/g++.dg/modules/lambda-7_a.H | 4 ++ gcc/testsuite/g++.dg/modules/lambda-7_b.C | 5 ++ gcc/testsuite/g++.dg/modules/lambda-7_c.C | 41 ++++++++++++ 7 files changed, 174 insertions(+), 55 deletions(-) create mode 100644 gcc/testsuite/g++.dg/modules/lambda-7.h create mode 100644 gcc/testsuite/g++.dg/modules/lambda-7_a.H create mode 100644 gcc/testsuite/g++.dg/modules/lambda-7_b.C create mode 100644 gcc/testsuite/g++.dg/modules/lambda-7_c.C (limited to 'gcc') diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 334c113..04c3aa6 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -1773,9 +1773,8 @@ check_constraint_info (tree t) (DECL_LANG_SPECIFIC (DECL_MODULE_CHECK (NODE))->u.base.module_entity_p) /* DECL that has attached decls for ODR-relatedness. */ -#define DECL_MODULE_KEYED_DECLS_P(NODE) \ - (DECL_LANG_SPECIFIC (TREE_CHECK2(NODE,FUNCTION_DECL,VAR_DECL))\ - ->u.base.module_keyed_decls_p) +#define DECL_MODULE_KEYED_DECLS_P(NODE) \ + (DECL_LANG_SPECIFIC (DECL_MODULE_CHECK (NODE))->u.base.module_keyed_decls_p) /* Whether this is an exported DECL. Held on any decl that can appear at namespace scope (function, var, type, template, const or @@ -2887,21 +2886,20 @@ struct GTY(()) lang_decl_base { unsigned friend_or_tls : 1; /* var, fn, type or template */ unsigned unknown_bound_p : 1; /* var */ unsigned odr_used : 1; /* var or fn */ - unsigned concept_p : 1; /* applies to vars and functions */ + unsigned concept_p : 1; /* applies to vars and functions */ unsigned var_declared_inline_p : 1; /* var */ unsigned dependent_init_p : 1; /* var */ - /* The following apply to VAR, FUNCTION, TYPE, CONCEPT, & NAMESPACE + /* The following four apply to VAR, FUNCTION, TYPE, CONCEPT, & NAMESPACE decls. */ - unsigned module_purview_p : 1; // in named-module purview - unsigned module_attach_p : 1; // attached to named module - unsigned module_import_p : 1; /* from an import */ - unsigned module_entity_p : 1; /* is in the entitity ary & - hash. */ - /* VAR_DECL or FUNCTION_DECL has keyed decls. */ - unsigned module_keyed_decls_p : 1; - - /* 12 spare bits. */ + unsigned module_purview_p : 1; /* in named-module purview */ + unsigned module_attach_p : 1; /* attached to named module */ + unsigned module_import_p : 1; /* from an import */ + unsigned module_entity_p : 1; /* is in the entitity ary & hash */ + + unsigned module_keyed_decls_p : 1; /* has keys, applies to all decls */ + + /* 11 spare bits. */ }; /* True for DECL codes which have template info and access. */ diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc index 106af7b..1b2ba2e 100644 --- a/gcc/cp/module.cc +++ b/gcc/cp/module.cc @@ -5664,8 +5664,7 @@ trees_out::lang_decl_bools (tree t) want to mark them as in module purview. */ WB (lang->u.base.module_purview_p && !header_module_p ()); WB (lang->u.base.module_attach_p); - if (VAR_OR_FUNCTION_DECL_P (t)) - WB (lang->u.base.module_keyed_decls_p); + WB (lang->u.base.module_keyed_decls_p); switch (lang->u.base.selector) { default: @@ -5738,8 +5737,7 @@ trees_in::lang_decl_bools (tree t) RB (lang->u.base.dependent_init_p); RB (lang->u.base.module_purview_p); RB (lang->u.base.module_attach_p); - if (VAR_OR_FUNCTION_DECL_P (t)) - RB (lang->u.base.module_keyed_decls_p); + RB (lang->u.base.module_keyed_decls_p); switch (lang->u.base.selector) { default: @@ -7871,8 +7869,7 @@ trees_out::decl_value (tree decl, depset *dep) install_entity (decl, dep); } - if (VAR_OR_FUNCTION_DECL_P (inner) - && DECL_LANG_SPECIFIC (inner) + if (DECL_LANG_SPECIFIC (inner) && DECL_MODULE_KEYED_DECLS_P (inner) && !is_key_order ()) { @@ -8172,8 +8169,7 @@ trees_in::decl_value () bool installed = install_entity (existing); bool is_new = existing == decl; - if (VAR_OR_FUNCTION_DECL_P (inner) - && DECL_LANG_SPECIFIC (inner) + if (DECL_LANG_SPECIFIC (inner) && DECL_MODULE_KEYED_DECLS_P (inner)) { /* Read and maybe install the attached entities. */ @@ -9187,6 +9183,13 @@ trees_in::tree_value () return NULL_TREE; } + if (TREE_CODE (t) == LAMBDA_EXPR + && CLASSTYPE_LAMBDA_EXPR (TREE_TYPE (t))) + { + existing = CLASSTYPE_LAMBDA_EXPR (TREE_TYPE (t)); + back_refs[~tag] = existing; + } + dump (dumper::TREE) && dump ("Read tree:%d %C:%N", tag, TREE_CODE (t), t); if (TREE_CODE (existing) == INTEGER_CST && !TREE_OVERFLOW (existing)) @@ -10484,12 +10487,17 @@ trees_out::get_merge_kind (tree decl, depset *dep) if (tree scope = LAMBDA_EXPR_EXTRA_SCOPE (CLASSTYPE_LAMBDA_EXPR (TREE_TYPE (decl)))) - if (TREE_CODE (scope) == VAR_DECL - && DECL_MODULE_KEYED_DECLS_P (scope)) - { - mk = MK_keyed; - break; - } + { + /* Lambdas attached to fields are keyed to its class. */ + if (TREE_CODE (scope) == FIELD_DECL) + scope = TYPE_NAME (DECL_CONTEXT (scope)); + if (DECL_LANG_SPECIFIC (scope) + && DECL_MODULE_KEYED_DECLS_P (scope)) + { + mk = MK_keyed; + break; + } + } if (RECORD_OR_UNION_TYPE_P (ctx)) { @@ -10789,7 +10797,13 @@ trees_out::key_mergeable (int tag, merge_kind mk, tree decl, tree inner, gcc_checking_assert (LAMBDA_TYPE_P (TREE_TYPE (inner))); tree scope = LAMBDA_EXPR_EXTRA_SCOPE (CLASSTYPE_LAMBDA_EXPR (TREE_TYPE (inner))); - gcc_checking_assert (TREE_CODE (scope) == VAR_DECL); + gcc_checking_assert (TREE_CODE (scope) == VAR_DECL + || TREE_CODE (scope) == FIELD_DECL + || TREE_CODE (scope) == PARM_DECL + || TREE_CODE (scope) == TYPE_DECL); + /* Lambdas attached to fields are keyed to the class. */ + if (TREE_CODE (scope) == FIELD_DECL) + scope = TYPE_NAME (DECL_CONTEXT (scope)); auto *root = keyed_table->get (scope); unsigned ix = root->length (); /* If we don't find it, we'll write a really big number @@ -11067,6 +11081,26 @@ trees_in::key_mergeable (int tag, merge_kind mk, tree decl, tree inner, } } } + else if (mk == MK_keyed + && DECL_LANG_SPECIFIC (name) + && DECL_MODULE_KEYED_DECLS_P (name)) + { + gcc_checking_assert (TREE_CODE (container) == NAMESPACE_DECL + || TREE_CODE (container) == TYPE_DECL); + if (auto *set = keyed_table->get (name)) + if (key.index < set->length ()) + { + existing = (*set)[key.index]; + if (existing) + { + gcc_checking_assert + (DECL_IMPLICIT_TYPEDEF_P (existing)); + if (inner != decl) + existing + = CLASSTYPE_TI_TEMPLATE (TREE_TYPE (existing)); + } + } + } else switch (TREE_CODE (container)) { @@ -11074,27 +11108,8 @@ trees_in::key_mergeable (int tag, merge_kind mk, tree decl, tree inner, gcc_unreachable (); case NAMESPACE_DECL: - if (mk == MK_keyed) - { - if (DECL_LANG_SPECIFIC (name) - && VAR_OR_FUNCTION_DECL_P (name) - && DECL_MODULE_KEYED_DECLS_P (name)) - if (auto *set = keyed_table->get (name)) - if (key.index < set->length ()) - { - existing = (*set)[key.index]; - if (existing) - { - gcc_checking_assert - (DECL_IMPLICIT_TYPEDEF_P (existing)); - if (inner != decl) - existing - = CLASSTYPE_TI_TEMPLATE (TREE_TYPE (existing)); - } - } - } - else if (is_attached - && !(state->is_module () || state->is_partition ())) + if (is_attached + && !(state->is_module () || state->is_partition ())) kind = "unique"; else { @@ -18984,11 +18999,19 @@ maybe_key_decl (tree ctx, tree decl) if (!modules_p ()) return; - // FIXME: For now just deal with lambdas attached to var decls. - // This might be sufficient? - if (TREE_CODE (ctx) != VAR_DECL) + /* We only need to deal with lambdas attached to var, field, + parm, or type decls. */ + if (TREE_CODE (ctx) != VAR_DECL + && TREE_CODE (ctx) != FIELD_DECL + && TREE_CODE (ctx) != PARM_DECL + && TREE_CODE (ctx) != TYPE_DECL) return; + /* For fields, key it to the containing type to handle deduplication + correctly. */ + if (TREE_CODE (ctx) == FIELD_DECL) + ctx = TYPE_NAME (DECL_CONTEXT (ctx)); + if (!keyed_table) keyed_table = new keyed_map_t (EXPERIMENT (1, 400)); diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc index b2ed2ba..3ee9d49 100644 --- a/gcc/cp/parser.cc +++ b/gcc/cp/parser.cc @@ -27678,10 +27678,16 @@ cp_parser_class_head (cp_parser* parser, if (cp_lexer_next_token_is (parser->lexer, CPP_COLON)) { if (type) - pushclass (type); + { + pushclass (type); + start_lambda_scope (TYPE_NAME (type)); + } bases = cp_parser_base_clause (parser); if (type) - popclass (); + { + finish_lambda_scope (); + popclass (); + } } else bases = NULL_TREE; diff --git a/gcc/testsuite/g++.dg/modules/lambda-7.h b/gcc/testsuite/g++.dg/modules/lambda-7.h new file mode 100644 index 0000000..6f6080c --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/lambda-7.h @@ -0,0 +1,42 @@ +struct S { + int (*a)(int) = [](int x) { return x * 2; }; + + int b(int x, int (*f)(int) = [](int x) { return x * 3; }) { + return f(x); + } + + static int c(int x, int (*f)(int) = [](int x) { return x * 4; }) { + return f(x); + } +}; + +inline int d(int x, int (*f)(int) = [](int x) { return x * 5; }) { + return f(x); +} + +// unevaluated lambdas +#if __cplusplus >= 202002L +struct E : decltype([](int x) { return x * 6; }) { + decltype([](int x) { return x * 7; }) f; +}; + +template +struct G : decltype([](int x) { return x * 8; }) { + decltype([](int x) { return x * 9; }) h; +}; + +template <> +struct G : decltype([](int x) { return x * 10; }) { + decltype([](int x) { return x * 11; }) i; +}; +#endif + +// concepts +#if __cpp_concepts >= 201907L +template +concept J = requires { []{ T(); }; }; + +template +concept K = []{ return sizeof(T) == 1; }(); +#endif + diff --git a/gcc/testsuite/g++.dg/modules/lambda-7_a.H b/gcc/testsuite/g++.dg/modules/lambda-7_a.H new file mode 100644 index 0000000..5197114 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/lambda-7_a.H @@ -0,0 +1,4 @@ +// { dg-additional-options "-fmodule-header -Wno-subobject-linkage" } +// { dg-module-cmi {} } + +#include "lambda-7.h" diff --git a/gcc/testsuite/g++.dg/modules/lambda-7_b.C b/gcc/testsuite/g++.dg/modules/lambda-7_b.C new file mode 100644 index 0000000..2d781e9 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/lambda-7_b.C @@ -0,0 +1,5 @@ +// { dg-additional-options "-fmodules-ts -fno-module-lazy -Wno-subobject-linkage" } +// Test for ODR deduplication + +#include "lambda-7.h" +import "lambda-7_a.H"; diff --git a/gcc/testsuite/g++.dg/modules/lambda-7_c.C b/gcc/testsuite/g++.dg/modules/lambda-7_c.C new file mode 100644 index 0000000..f283681 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/lambda-7_c.C @@ -0,0 +1,41 @@ +// { dg-module-do run } +// { dg-additional-options "-fmodules-ts -fno-module-lazy -Wno-subobject-linkage" } + +import "lambda-7_a.H"; + +int main() { + S s; + if (s.a(10) != 20) + __builtin_abort(); + if (s.b(10) != 30) + __builtin_abort(); + if (s.c(10) != 40) + __builtin_abort(); + if (d(10) != 50) + __builtin_abort(); + +#if __cplusplus >= 202002L + E e; + if (e(10) != 60) + __builtin_abort(); + if (e.f(10) != 70) + __builtin_abort(); + + G g1; + if (g1(10) != 80) + __builtin_abort(); + if (g1.h(10) != 90) + __builtin_abort(); + + G g2; + if (g2(10) != 100) + __builtin_abort(); + if (g2.i(10) != 110) + __builtin_abort(); +#endif + +#if __cpp_concepts >= 201907L + static_assert(J); + static_assert(K); +#endif +} -- cgit v1.1 From c556ea076dcbfe2a3059dd0ad2e06a0b1d1fa89b Mon Sep 17 00:00:00 2001 From: Xi Ruoyao Date: Sun, 25 Feb 2024 20:40:41 +0800 Subject: LoongArch: NFC: Deduplicate crc instruction defines Introduce an iterator for UNSPEC_CRC and UNSPEC_CRCC to make the next change easier. gcc/ChangeLog: * config/loongarch/loongarch.md (CRC): New define_int_iterator. (crc): New define_int_attr. (loongarch_crc_w__w, loongarch_crcc_w__w): Unify into ... (loongarch__w__w): ... here. --- gcc/config/loongarch/loongarch.md | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) (limited to 'gcc') diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index dffa41b..9646fa90 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -4251,24 +4251,16 @@ (define_mode_iterator QHSD [QI HI SI DI]) +(define_int_iterator CRC [UNSPEC_CRC UNSPEC_CRCC]) +(define_int_attr crc [(UNSPEC_CRC "crc") (UNSPEC_CRCC "crcc")]) -(define_insn "loongarch_crc_w__w" +(define_insn "loongarch__w__w" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:QHSD 1 "register_operand" "r") (match_operand:SI 2 "register_operand" "r")] - UNSPEC_CRC))] + CRC))] "" - "crc.w..w\t%0,%1,%2" - [(set_attr "type" "unknown") - (set_attr "mode" "")]) - -(define_insn "loongarch_crcc_w__w" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:QHSD 1 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r")] - UNSPEC_CRCC))] - "" - "crcc.w..w\t%0,%1,%2" + ".w..w\t%0,%1,%2" [(set_attr "type" "unknown") (set_attr "mode" "")]) -- cgit v1.1 From aab1c5dcd23f014f39b127f74aecd04913945a7f Mon Sep 17 00:00:00 2001 From: Xi Ruoyao Date: Sun, 25 Feb 2024 20:44:34 +0800 Subject: LoongArch: Remove unneeded sign extension after crc/crcc instructions The specification of crc/crcc instructions is clear that the output is sign-extended to GRLEN. Add a define_insn to tell the compiler this fact and allow it to remove the unneeded sign extension on crc/crcc output. As crc/crcc instructions are usually used in a tight loop, this should produce a significant performance gain. gcc/ChangeLog: * config/loongarch/loongarch.md (loongarch__w__w_extended): New define_insn. gcc/testsuite/ChangeLog: * gcc.target/loongarch/crc-sext.c: New test; --- gcc/config/loongarch/loongarch.md | 11 +++++++++++ gcc/testsuite/gcc.target/loongarch/crc-sext.c | 13 +++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/crc-sext.c (limited to 'gcc') diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 9646fa90..f3b5c64 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -4264,6 +4264,17 @@ [(set_attr "type" "unknown") (set_attr "mode" "")]) +(define_insn "loongarch__w__w_extended" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (unspec:SI [(match_operand:QHSD 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + CRC)))] + "TARGET_64BIT" + ".w..w\t%0,%1,%2" + [(set_attr "type" "unknown") + (set_attr "mode" "")]) + ;; With normal or medium code models, if the only use of a pc-relative ;; address is for loading or storing a value, then relying on linker ;; relaxation is not better than emitting the machine instruction directly. diff --git a/gcc/testsuite/gcc.target/loongarch/crc-sext.c b/gcc/testsuite/gcc.target/loongarch/crc-sext.c new file mode 100644 index 0000000..9ade5a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/crc-sext.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=loongarch64" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +**my_crc: +** crc.w.d.w \$r4,\$r4,\$r5 +** jr \$r1 +*/ +int my_crc(long long dword, int crc) +{ + return __builtin_loongarch_crc_w_d_w(dword, crc); +} -- cgit v1.1 From 5ec7740496a6908b32cd058c0520a2bd5a689bb5 Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Wed, 28 Feb 2024 22:39:32 -0800 Subject: aarch64: Fix memtag builtins vs GC [PR108174] The memtag builtins were being GC'ed away so we end up with a crash sometimes (maybe even wrong code). This fixes that issue by adding GTY on the variable/struct aarch64_memtag_builtin_data. Committed as obvious after a build/test for aarch64-linux-gnu. PR target/108174 gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make static and mark with GTY. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/memtag_4.c: New test. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64-builtins.cc | 2 +- gcc/testsuite/gcc.target/aarch64/acle/memtag_4.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/memtag_4.c (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 277904f..75d21de 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -1840,7 +1840,7 @@ aarch64_init_prefetch_builtin (void) } /* Initialize the memory tagging extension (MTE) builtins. */ -struct +static GTY(()) struct GTY(()) { tree ftype; enum insn_code icode; diff --git a/gcc/testsuite/gcc.target/aarch64/acle/memtag_4.c b/gcc/testsuite/gcc.target/aarch64/acle/memtag_4.c new file mode 100644 index 0000000..1e209ff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/memtag_4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv9-a+memtag --param ggc-min-expand=0 --param ggc-min-heapsize=0" } */ +/* PR target/108174 */ +/* Check to make sure that the builtin functions are not GC'ed away. */ +#include "arm_acle.h" + +void g(void) +{ + const char *c; + __arm_mte_increment_tag(c , 0 ); +} +void h(void) +{ + const char *c; + __arm_mte_increment_tag( c,0); +} -- cgit v1.1 From 46666b9bde5903d80ad8a30f5e7ecb6fc4208290 Mon Sep 17 00:00:00 2001 From: Gaius Mulley Date: Thu, 29 Feb 2024 13:42:30 +0000 Subject: PR modula2/102344 TestLong4.mod FAILs This is a testsuite fix for TestLong4.mod so that it succeeds on 32 bit systems. The original TestLong4.mod has been rewritten as testing MAX(LONGCARD) into the variable l. The new testlong4.mod has been added to cpp/pass. The new testcode uses the C preprocessor to select the appropriate constant literal depending upon __SIZEOF_LONG__. gcc/testsuite/ChangeLog: PR modula2/102344 * gm2/pim/pass/TestLong4.mod: Rewrite. * gm2/cpp/pass/testlong4.mod: New test. Signed-off-by: Gaius Mulley --- gcc/testsuite/gm2/cpp/pass/testlong4.mod | 33 ++++++++++++++++++++++++++++++++ gcc/testsuite/gm2/pim/pass/TestLong4.mod | 3 +-- 2 files changed, 34 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gm2/cpp/pass/testlong4.mod (limited to 'gcc') diff --git a/gcc/testsuite/gm2/cpp/pass/testlong4.mod b/gcc/testsuite/gm2/cpp/pass/testlong4.mod new file mode 100644 index 0000000..97dd4b2 --- /dev/null +++ b/gcc/testsuite/gm2/cpp/pass/testlong4.mod @@ -0,0 +1,33 @@ +(* Copyright (C) 2024 Free Software Foundation, Inc. *) +(* This file is part of GNU Modula-2. + +GNU Modula-2 is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2, or (at your option) any later +version. + +GNU Modula-2 is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with gm2; see the file COPYING. If not, write to the Free Software +Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *) + +MODULE testlong4 ; + +FROM libc IMPORT exit ; + +VAR + l: LONGCARD ; +BEGIN + (* test for assignment of MAX(LONGINT)+1 *) +#if __SIZEOF_LONG__ == 4 + l := 2147483648 +#elif __SIZEOF_LONG__ == 8 + l := 9223372036854775808 +#else +# error "add the clause for the size of long here" +#endif +END testlong4. diff --git a/gcc/testsuite/gm2/pim/pass/TestLong4.mod b/gcc/testsuite/gm2/pim/pass/TestLong4.mod index 514deb9..f2de941 100644 --- a/gcc/testsuite/gm2/pim/pass/TestLong4.mod +++ b/gcc/testsuite/gm2/pim/pass/TestLong4.mod @@ -22,6 +22,5 @@ FROM libc IMPORT exit ; VAR l: LONGCARD ; BEGIN - (* test for assignment of MAX(LONGINT)+1 *) - l := 9223372036854775808 + l := MAX (LONGCARD) END TestLong4. -- cgit v1.1 From b83f3cd3ff765fb82344b848b8a128763b7a4233 Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Tue, 20 Feb 2024 15:55:55 -0500 Subject: c++: -Wuninitialized when binding a ref to uninit DM [PR113987] This PR asks that our -Wuninitialized for mem-initializers does not warn when binding a reference to an uninitialized data member. We already check !INDIRECT_TYPE_P in find_uninit_fields_r, but that won't catch binding a parameter of a reference type to an uninitialized field, as in: struct S { S (int&); }; struct T { T() : s(i) {} S s; int i; }; This patch adds a new function to handle this case. PR c++/113987 gcc/cp/ChangeLog: * call.cc (conv_binds_to_reference_parm_p): New. * cp-tree.h (conv_binds_to_reference_parm_p): Declare. * init.cc (find_uninit_fields_r): Call it. gcc/testsuite/ChangeLog: * g++.dg/warn/Wuninitialized-15.C: Turn dg-warning into dg-bogus. * g++.dg/warn/Wuninitialized-34.C: New test. --- gcc/cp/call.cc | 24 ++++++++++++++++++++ gcc/cp/cp-tree.h | 1 + gcc/cp/init.cc | 3 ++- gcc/testsuite/g++.dg/warn/Wuninitialized-15.C | 3 +-- gcc/testsuite/g++.dg/warn/Wuninitialized-34.C | 32 +++++++++++++++++++++++++++ 5 files changed, 60 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/g++.dg/warn/Wuninitialized-34.C (limited to 'gcc') diff --git a/gcc/cp/call.cc b/gcc/cp/call.cc index 1dac147..c40ef2e 100644 --- a/gcc/cp/call.cc +++ b/gcc/cp/call.cc @@ -14551,4 +14551,28 @@ maybe_show_nonconverting_candidate (tree to, tree from, tree arg, int flags) "function was not considered"); } +/* We're converting EXPR to TYPE. If that conversion involves a conversion + function and we're binding EXPR to a reference parameter of that function, + return true. */ + +bool +conv_binds_to_reference_parm_p (tree type, tree expr) +{ + conversion_obstack_sentinel cos; + conversion *c = implicit_conversion (type, TREE_TYPE (expr), expr, + /*c_cast_p=*/false, LOOKUP_NORMAL, + tf_none); + if (c && !c->bad_p && c->user_conv_p) + for (; c; c = next_conversion (c)) + if (c->kind == ck_user) + for (z_candidate *cand = c->cand; cand; cand = cand->next) + if (cand->viable == 1) + for (size_t i = 0; i < cand->num_convs; ++i) + if (cand->convs[i]->kind == ck_ref_bind + && conv_get_original_expr (cand->convs[i]) == expr) + return true; + + return false; +} + #include "gt-cp-call.h" diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 04c3aa6..06c2637 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -6843,6 +6843,7 @@ extern void cp_warn_deprecated_use_scopes (tree); extern tree get_function_version_dispatcher (tree); extern bool any_template_arguments_need_structural_equality_p (tree); extern void maybe_show_nonconverting_candidate (tree, tree, tree, int); +extern bool conv_binds_to_reference_parm_p (tree, tree); /* in class.cc */ extern tree build_vfield_ref (tree, tree); diff --git a/gcc/cp/init.cc b/gcc/cp/init.cc index ac37330..1a341f7 100644 --- a/gcc/cp/init.cc +++ b/gcc/cp/init.cc @@ -906,7 +906,8 @@ find_uninit_fields_r (tree *tp, int *walk_subtrees, void *data) warning_at (EXPR_LOCATION (init), OPT_Wuninitialized, "reference %qD is not yet bound to a value when used " "here", field); - else if (!INDIRECT_TYPE_P (type) || is_this_parameter (d->member)) + else if ((!INDIRECT_TYPE_P (type) || is_this_parameter (d->member)) + && !conv_binds_to_reference_parm_p (type, init)) warning_at (EXPR_LOCATION (init), OPT_Wuninitialized, "member %qD is used uninitialized", field); *walk_subtrees = false; diff --git a/gcc/testsuite/g++.dg/warn/Wuninitialized-15.C b/gcc/testsuite/g++.dg/warn/Wuninitialized-15.C index 89e9066..2fd3303 100644 --- a/gcc/testsuite/g++.dg/warn/Wuninitialized-15.C +++ b/gcc/testsuite/g++.dg/warn/Wuninitialized-15.C @@ -65,8 +65,7 @@ struct H { G g; A a2; H() : g(a1) { } - // ??? clang++ doesn't warn here - H(int) : g(a2) { } // { dg-warning "member .H::a2. is used uninitialized" } + H(int) : g(a2) { } // { dg-bogus "member .H::a2. is used uninitialized" } }; struct I { diff --git a/gcc/testsuite/g++.dg/warn/Wuninitialized-34.C b/gcc/testsuite/g++.dg/warn/Wuninitialized-34.C new file mode 100644 index 0000000..28226d8 --- /dev/null +++ b/gcc/testsuite/g++.dg/warn/Wuninitialized-34.C @@ -0,0 +1,32 @@ +// PR c++/113987 +// { dg-do compile } +// { dg-options "-Wuninitialized" } + +struct t1 { + t1(int); +}; +struct t2 { + t2(int&, int = 0); + t2(double&, int = 0); +}; +struct t3 { + t3(int&); +}; +struct t4 {}; +void f1(int&); +struct t { + t() : + v1(i), // { dg-warning "is used uninitialized" } + v2(i), + v3(i), + v4((f1(i), t4())), + v5(i) {} + t1 v1; + t2 v2; + t3 v3; + t4 v4; + t1 v5; + int i; + int j; +}; +int main() { t v1; } -- cgit v1.1 From 2f43ad6a60adb8dd4af9a3c78dfe78597e891c9e Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Thu, 29 Feb 2024 18:08:45 +0100 Subject: AVR: target/114132 - Code sets up a frame pointer without need. The condition CUMULATIVE_ARGS.nregs == 0 in avr_frame_pointer_required_p() means that no more argument registers are left, but that's not the same condition that tells whether an argument pointer is required. PR target/114132 gcc/ * config/avr/avr.h (CUMULATIVE_ARGS) : New field. * config/avr/avr.cc (avr_init_cumulative_args): Initialize it. (avr_function_arg): Set it. (avr_frame_pointer_required_p): Use it instead of .nregs. gcc/testsuite/ * gcc.target/avr/pr114132-1.c: New test. * gcc.target/avr/torture/pr114132-2.c: New test. --- gcc/config/avr/avr.cc | 7 ++++++- gcc/config/avr/avr.h | 4 ++++ gcc/testsuite/gcc.target/avr/pr114132-1.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/avr/torture/pr114132-2.c | 22 ++++++++++++++++++++++ 4 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/avr/pr114132-1.c create mode 100644 gcc/testsuite/gcc.target/avr/torture/pr114132-2.c (limited to 'gcc') diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 655a8e8..478463b 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -3565,6 +3565,7 @@ avr_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, { cum->nregs = AVR_TINY ? 6 : 18; cum->regno = FIRST_CUM_REG; + cum->has_stack_args = 0; if (!libname && stdarg_p (fntype)) cum->nregs = 0; @@ -3605,6 +3606,8 @@ avr_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) if (cum->nregs && bytes <= cum->nregs) return gen_rtx_REG (arg.mode, cum->regno - bytes); + cum->has_stack_args = 1; + return NULL_RTX; } @@ -6014,6 +6017,8 @@ out_movhi_mr_r (rtx_insn *insn, rtx op[], int *plen) return ""; } + +/* Implement `TARGET_FRAME_POINTER_REQUIRED'. */ /* Return 1 if frame pointer for current function required. */ static bool @@ -6022,7 +6027,7 @@ avr_frame_pointer_required_p (void) return (cfun->calls_alloca || cfun->calls_setjmp || cfun->has_nonlocal_label - || crtl->args.info.nregs == 0 + || crtl->args.info.has_stack_args || get_frame_size () > 0); } diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index ff2738d..56211fa 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -333,6 +333,10 @@ typedef struct avr_args /* Next available register number */ int regno; + + /* Whether some of the arguments are passed on the stack, + and hence an arg pointer is needed. */ + int has_stack_args; } CUMULATIVE_ARGS; #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ diff --git a/gcc/testsuite/gcc.target/avr/pr114132-1.c b/gcc/testsuite/gcc.target/avr/pr114132-1.c new file mode 100644 index 0000000..209eca8 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr114132-1.c @@ -0,0 +1,15 @@ +/* { dg-additional-options "-Os -std=c99" } */ + +#ifdef __AVR_TINY__ +int func (int a, int b, char c) +#else +int func (long long a, long long b, char c) +#endif +{ + (void) a; + (void) b; + + return c; +} + +/* { dg-final { scan-assembler-not "push r28" } } */ diff --git a/gcc/testsuite/gcc.target/avr/torture/pr114132-2.c b/gcc/testsuite/gcc.target/avr/torture/pr114132-2.c new file mode 100644 index 0000000..c2bcbac --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/pr114132-2.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +__attribute__((noinline,noclone)) +#ifdef __AVR_TINY__ +int func (int a, int b, char c) +#else +int func (long long a, long long b, char c) +#endif +{ + (void) a; + (void) b; + return 10 + c; +} + +int main (void) +{ + if (func (0, 0, 91) != 101) + __builtin_abort(); + return 0; +} + -- cgit v1.1 From cda3836161834c5f21f264885891fe4d0ce90da1 Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Thu, 29 Feb 2024 17:19:27 +0100 Subject: AVR: target/114100 - Better indirect accesses for reduced Tiny The Reduced Tiny core does not support indirect addressing with offset, which basically means that every indirect memory access with a size of more than one byte is effectively POST_INC or PRE_DEC. The lack of that addressing mode is currently handled by pretending to support it, and then let the insn printers add and subtract again offsets as needed. For example, the following C code int vars[10]; void inc_var2 (void) { ++vars[2]; } is compiled to: ldi r30,lo8(vars) ; 14 [c=4 l=2] *movhi/4 ldi r31,hi8(vars) subi r30,lo8(-(4)) ; 15 [c=8 l=6] *movhi/2 sbci r31,hi8(-(4)) ld r20,Z+ ld r21,Z subi r30,lo8((4+1)) sbci r31,hi8((4+1)) subi r20,-1 ; 16 [c=4 l=2] *addhi3_clobber/1 sbci r21,-1 subi r30,lo8(-(4+1)) ; 17 [c=4 l=4] *movhi/3 sbci r31,hi8(-(4+1)) st Z,r21 st -Z,r20 where the code could be -- and with this patch actually is -- like ldi r30,lo8(vars+4) ; 28 [c=4 l=2] *movhi/4 ldi r31,hi8(vars+4) ld r20,Z+ ; 17 [c=8 l=2] *movhi/2 ld r21,Z+ subi r20,-1 ; 19 [c=4 l=2] *addhi3_clobber/1 sbci r21,-1 st -Z,r21 ; 30 [c=4 l=2] *movhi/3 st -Z,r20 This is achieved in two steps: - A post-reload split into "real" instructions during .split2. - A new avr-specific mini pass .avr-fuse-add that runs before RTL peephole and that tries to combine the generated pointer additions into memory accesses to form POST_INC or PRE_DEC. gcc/ PR target/114100 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document. * config/avr/avr.opt (-mfuse-add=): New target option. * common/config/avr/avr-common.cc (avr_option_optimization_table) [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1. [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2. * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass. * config/avr/avr-protos.h (avr_split_tiny_move) (make_avr_pass_fuse_add): New protos. * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses avr_split_tiny_move to split indirect memory accesses. (gen_move_clobbercc): New define_expand helper. * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data. (avr_pass_fuse_add): New class from rtl_opt_pass. (make_avr_pass_fuse_add, avr_split_tiny_move): New functions. (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions. (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets of PLUS addressing for AVR_TINY. (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X. (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y. (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS. --- gcc/common/config/avr/avr-common.cc | 2 + gcc/config/avr/avr-passes.def | 9 + gcc/config/avr/avr-protos.h | 2 + gcc/config/avr/avr.cc | 785 +++++++++++++++++++++++++++++++++++- gcc/config/avr/avr.md | 29 ++ gcc/config/avr/avr.opt | 8 + gcc/doc/invoke.texi | 10 +- 7 files changed, 843 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/common/config/avr/avr-common.cc b/gcc/common/config/avr/avr-common.cc index 7867483..fdf130f 100644 --- a/gcc/common/config/avr/avr-common.cc +++ b/gcc/common/config/avr/avr-common.cc @@ -34,6 +34,8 @@ static const struct default_options avr_option_optimization_table[] = { OPT_LEVELS_ALL, OPT_fcaller_saves, NULL, 0 }, { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_mgas_isr_prologues, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_mmain_is_OS_task, NULL, 1 }, + { OPT_LEVELS_1_PLUS, OPT_mfuse_add_, NULL, 1 }, + { OPT_LEVELS_2_PLUS, OPT_mfuse_add_, NULL, 2 }, // Stick to the "old" placement of the subreg lowering pass. { OPT_LEVELS_1_PLUS, OPT_fsplit_wide_types_early, NULL, 1 }, /* Allow optimizer to introduce store data races. This used to be the diff --git a/gcc/config/avr/avr-passes.def b/gcc/config/avr/avr-passes.def index 34e5b95..748260e 100644 --- a/gcc/config/avr/avr-passes.def +++ b/gcc/config/avr/avr-passes.def @@ -17,6 +17,15 @@ along with GCC; see the file COPYING3. If not see . */ +/* A post reload optimization pass that fuses PLUS insns with CONST_INT + addend with a load or store insn to get POST_INC or PRE_DEC addressing. + It can also fuse two PLUSes to a single one, which may occur due to + splits from `avr_split_tiny_move'. We do this in an own pass because + it can find more cases than peephole2, for example when there are + unrelated insns between the interesting ones. */ + +INSERT_PASS_BEFORE (pass_peephole2, 1, avr_pass_fuse_add); + /* An analysis pass that runs prior to prologue / epilogue generation. Computes cfun->machine->gasisr.maybe which is used in prologue and epilogue generation provided -mgas-isr-prologues is on. */ diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h index 7d1f815..064a3d2 100644 --- a/gcc/config/avr/avr-protos.h +++ b/gcc/config/avr/avr-protos.h @@ -88,6 +88,7 @@ extern void avr_expand_prologue (void); extern void avr_expand_epilogue (bool); extern bool avr_emit_cpymemhi (rtx*); extern int avr_epilogue_uses (int regno); +extern bool avr_split_tiny_move (rtx_insn *insn, rtx *operands); extern void avr_output_addr_vec (rtx_insn*, rtx); extern const char *avr_out_sbxx_branch (rtx_insn *insn, rtx operands[]); @@ -161,6 +162,7 @@ extern bool avr_have_dimode; namespace gcc { class context; } class rtl_opt_pass; +extern rtl_opt_pass *make_avr_pass_fuse_add (gcc::context *); extern rtl_opt_pass *make_avr_pass_pre_proep (gcc::context *); extern rtl_opt_pass *make_avr_pass_recompute_notes (gcc::context *); extern rtl_opt_pass *make_avr_pass_casesi (gcc::context *); diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 478463b..94ef7c5 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -1779,6 +1779,585 @@ sequent_regs_live (void) return (cur_seq == live_seq) ? live_seq : 0; } + +namespace { +static const pass_data avr_pass_data_fuse_add = +{ + RTL_PASS, // type + "", // name (will be patched) + OPTGROUP_NONE, // optinfo_flags + TV_DF_SCAN, // tv_id + 0, // properties_required + 0, // properties_provided + 0, // properties_destroyed + 0, // todo_flags_start + TODO_df_finish // todo_flags_finish +}; + + +class avr_pass_fuse_add : public rtl_opt_pass +{ +public: + avr_pass_fuse_add (gcc::context *ctxt, const char *name) + : rtl_opt_pass (avr_pass_data_fuse_add, ctxt) + { + this->name = name; + } + + virtual bool gate (function *) { return optimize && avr_fuse_add > 0; } + + virtual unsigned int execute (function *); + + struct Some_Insn + { + rtx_insn *insn = nullptr; + rtx dest, src; + bool valid () const { return insn != nullptr; } + void set_deleted () + { + gcc_assert (insn); + SET_INSN_DELETED (insn); + insn = nullptr; + } + }; + + // If .insn is not NULL, then this is a reg:HI += const_int + // of an address register. + struct Add_Insn : Some_Insn + { + rtx addend; + int regno; + Add_Insn () {} + Add_Insn (rtx_insn *insn); + }; + + // If .insn is not NULL, then this sets an address register + // to a constant value. + struct Ldi_Insn : Some_Insn + { + int regno; + Ldi_Insn () {} + Ldi_Insn (rtx_insn *insn); + }; + + // If .insn is not NULL, then this is a load or store insn where the + // address is REG or POST_INC with an address register. + struct Mem_Insn : Some_Insn + { + rtx reg_or_0, mem, addr, addr_reg; + int addr_regno; + enum rtx_code addr_code; + machine_mode mode; + addr_space_t addr_space; + bool store_p, volatile_p; + Mem_Insn () {} + Mem_Insn (rtx_insn *insn); + }; + + rtx_insn *fuse_ldi_add (Ldi_Insn &prev_ldi, Add_Insn &add); + rtx_insn *fuse_add_add (Add_Insn &prev_add, Add_Insn &add); + rtx_insn *fuse_add_mem (Add_Insn &prev_add, Mem_Insn &mem); + rtx_insn *fuse_mem_add (Mem_Insn &prev_mem, Add_Insn &add); +}; // avr_pass_fuse_add + +} // anon namespace + +rtl_opt_pass * +make_avr_pass_fuse_add (gcc::context *ctxt) +{ + return new avr_pass_fuse_add (ctxt, "avr-fuse-add"); +} + +/* Describe properties of AVR's indirect load and store instructions + LD, LDD, ST, STD, LPM, ELPM depending on register number, volatility etc. + Rules for "volatile" accesses are: + + | Xmega | non-Xmega + ------+-----------------+---------------- + load | read LSB first | read LSB first + store | write LSB first | write MSB first +*/ + +struct AVR_LdSt_Props +{ + bool has_postinc, has_predec, has_ldd; + // The insn printers will use POST_INC or PRE_DEC addressing, no matter + // what adressing modes we are feeding into them. + bool want_postinc, want_predec; + + AVR_LdSt_Props (int regno, bool store_p, bool volatile_p, addr_space_t as) + { + bool generic_p = ADDR_SPACE_GENERIC_P (as); + bool flashx_p = ! generic_p && as != ADDR_SPACE_MEMX; + has_postinc = generic_p || (flashx_p && regno == REG_Z); + has_predec = generic_p; + has_ldd = ! AVR_TINY && generic_p && (regno == REG_Y || regno == REG_Z); + want_predec = volatile_p && generic_p && ! AVR_XMEGA && store_p; + want_postinc = volatile_p && generic_p && (AVR_XMEGA || ! store_p); + want_postinc |= flashx_p && regno == REG_Z; + } + + AVR_LdSt_Props (const avr_pass_fuse_add::Mem_Insn &m) + : AVR_LdSt_Props (m.addr_regno, m.store_p, m.volatile_p, m.addr_space) + { + gcc_assert (m.valid ()); + } +}; + +/* Emit a single_set that clobbers REG_CC. */ + +static rtx_insn * +emit_move_ccc (rtx dest, rtx src) +{ + return emit_insn (gen_gen_move_clobbercc (dest, src)); +} + +/* Emit a single_set that clobbers REG_CC after insn AFTER. */ + +static rtx_insn * +emit_move_ccc_after (rtx dest, rtx src, rtx_insn *after) +{ + return emit_insn_after (gen_gen_move_clobbercc (dest, src), after); +} + +static bool +reg_seen_between_p (const_rtx reg, const rtx_insn *from, const rtx_insn *to) +{ + return (reg_used_between_p (reg, from, to) + || reg_set_between_p (reg, from, to)); +} + + +static void +avr_maybe_adjust_cfa (rtx_insn *insn, rtx reg, int addend) +{ + if (addend + && frame_pointer_needed + && REGNO (reg) == FRAME_POINTER_REGNUM + && avr_fuse_add == 3) + { + rtx plus = plus_constant (Pmode, reg, addend); + RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_CFA_ADJUST_CFA, gen_rtx_SET (reg, plus)); + } +} + + +// If successful, this represents a SET of a pointer register to a constant. +avr_pass_fuse_add::Ldi_Insn::Ldi_Insn (rtx_insn *insn) +{ + rtx set = single_set (insn); + if (!set) + return; + + src = SET_SRC (set); + dest = SET_DEST (set); + + if (REG_P (dest) + && GET_MODE (dest) == Pmode + && IN_RANGE (regno = REGNO (dest), REG_X, REG_Z) + && CONSTANT_P (src)) + { + this->insn = insn; + } +} + +// If successful, this represents a PLUS with CONST_INT of a pointer +// register X, Y or Z. Otherwise, the object is not valid(). +avr_pass_fuse_add::Add_Insn::Add_Insn (rtx_insn *insn) +{ + rtx set = single_set (insn); + if (!set) + return; + + src = SET_SRC (set); + dest = SET_DEST (set); + if (REG_P (dest) + // We are only interested in PLUSes that change address regs. + && GET_MODE (dest) == Pmode + && IN_RANGE (regno = REGNO (dest), REG_X, REG_Z) + && PLUS == GET_CODE (src) + && rtx_equal_p (XEXP (src, 0), dest) + && CONST_INT_P (XEXP (src, 1))) + { + // This is reg:HI += const_int. + addend = XEXP (src, 1); + this->insn = insn; + } +} + +// If successful, this represents a load or store insn where the addressing +// mode uses pointer register X, Y or Z. Otherwise, the object is not valid(). +avr_pass_fuse_add::Mem_Insn::Mem_Insn (rtx_insn *insn) +{ + rtx set = single_set (insn); + if (!set) + return; + + src = SET_SRC (set); + dest = SET_DEST (set); + mode = GET_MODE (dest); + + if (MEM_P (dest) + && (REG_P (src) || src == CONST0_RTX (mode))) + { + reg_or_0 = src; + mem = dest; + } + else if (REG_P (dest) && MEM_P (src)) + { + reg_or_0 = dest; + mem = src; + } + else + return; + + addr = XEXP (mem, 0); + addr_code = GET_CODE (addr); + + if (addr_code == REG) + addr_reg = addr; + else if (addr_code == POST_INC || addr_code == PRE_DEC) + addr_reg = XEXP (addr, 0); + else + return; + + addr_regno = REGNO (addr_reg); + + if (avr_fuse_add == 2 + && frame_pointer_needed + && addr_regno == FRAME_POINTER_REGNUM) + MEM_VOLATILE_P (mem) = 0; + + if (reg_overlap_mentioned_p (reg_or_0, addr) // Can handle CONSTANT_P. + || addr_regno > REG_Z + || avr_mem_memx_p (mem) + // The following optimizations only handle REG and POST_INC, + // so that's all what we allow here. + || (addr_code != REG && addr_code != POST_INC)) + return; + + addr_space = MEM_ADDR_SPACE (mem); + volatile_p = MEM_VOLATILE_P (mem); + store_p = MEM_P (dest); + + // Turn this "valid". + this->insn = insn; +} + +/* Try to combine a Ldi insn with a PLUS CONST_INT addend to one Ldi insn. + If LDI is valid, then it precedes ADD in the same block. + When a replacement is found, a new insn is emitted and the old insns + are pseudo-deleted. The returned insn is the point where the calling + scanner should continue. When no replacement is found, nullptr is + returned and nothing changed. */ + +rtx_insn * +avr_pass_fuse_add::fuse_ldi_add (Ldi_Insn &ldi, Add_Insn &add) +{ + if (! ldi.valid () + || reg_seen_between_p (ldi.dest, ldi.insn, add.insn)) + { + // If something is between the Ldi and the current insn, we can + // set the Ldi invalid to speed future scans. + return ldi.insn = nullptr; + } + + // Found a Ldi with const and a PLUS insns in the same BB, + // and with no interfering insns between them. + + // Emit new Ldi with the sum of the original offsets after the old Ldi. + rtx xval = plus_constant (Pmode, ldi.src, INTVAL (add.addend)); + + rtx_insn *insn = emit_move_ccc_after (ldi.dest, xval, ldi.insn); + avr_dump (";; new Ldi[%d] insn %d after %d: R%d = %r\n\n", ldi.regno, + INSN_UID (insn), INSN_UID (ldi.insn), ldi.regno, xval); + + rtx_insn *next = NEXT_INSN (add.insn); + ldi.set_deleted (); + add.set_deleted (); + + return next; +} + +/* Try to combine two PLUS insns with CONST_INT addend to one such insn. + If PREV_ADD is valid, then it precedes ADD in the same basic block. + When a replacement is found, a new insn is emitted and the old insns + are pseudo-deleted. The returned insn is the point where the calling + scanner should continue. When no replacement is found, nullptr is + returned and nothing changed. */ + +rtx_insn * +avr_pass_fuse_add::fuse_add_add (Add_Insn &prev_add, Add_Insn &add) +{ + if (! prev_add.valid () + || reg_seen_between_p (add.dest, prev_add.insn, add.insn)) + { + // If something is between the previous Add and the current insn, + // we can set the previous Add invalid to speed future scans. + return prev_add.insn = nullptr; + } + + // Found two PLUS insns in the same BB, and with no interfering + // insns between them. + rtx plus = plus_constant (Pmode, add.src, INTVAL (prev_add.addend)); + + rtx_insn *next; + if (REG_P (plus)) + { + avr_dump (";; Add[%d] from %d annihilates %d\n\n", add.regno, + INSN_UID (prev_add.insn), INSN_UID (add.insn)); + next = NEXT_INSN (add.insn); + } + else + { + // Emit after the current insn, so that it will be picked + // up as next valid Add insn. + next = emit_move_ccc_after (add.dest, plus, add.insn); + avr_dump (";; #1 new Add[%d] insn %d after %d: R%d += %d\n\n", + add.regno, INSN_UID (next), INSN_UID (add.insn), + add.regno, (int) INTVAL (XEXP (plus, 1))); + gcc_assert (GET_CODE (plus) == PLUS); + } + + add.set_deleted (); + prev_add.set_deleted (); + + return next; +} + +/* Try to combine a PLUS of the address register with a load or store insn. + If ADD is valid, then it precedes MEM in the same basic block. + When a replacement is found, a new insn is emitted and the old insns + are pseudo-deleted. The returned insn is the point where the calling + scanner should continue. When no replacement is found, nullptr is + returned and nothing changed. */ + +rtx_insn * +avr_pass_fuse_add::fuse_add_mem (Add_Insn &add, Mem_Insn &mem) +{ + if (! add.valid () + || reg_seen_between_p (add.dest, add.insn, mem.insn)) + { + // If something is between the Add and the current insn, we can + // set the Add invalid to speed future scans. + return add.insn = nullptr; + } + + AVR_LdSt_Props ap { mem }; + + int msize = GET_MODE_SIZE (mem.mode); + + // The mem insn really wants PRE_DEC. + bool case1 = ((mem.addr_code == REG || mem.addr_code == POST_INC) + && msize > 1 && ap.want_predec && ! ap.has_ldd); + + // The offset can be consumed by a PRE_DEC. + bool case2 = (- INTVAL (add.addend) == msize + && (mem.addr_code == REG || mem.addr_code == POST_INC) + && ap.has_predec && ! ap.want_postinc); + + if (! case1 && ! case2) + return nullptr; + + // Change from REG or POST_INC to PRE_DEC. + rtx xmem = change_address (mem.mem, mem.mode, + gen_rtx_PRE_DEC (Pmode, mem.addr_reg)); + rtx dest = mem.store_p ? xmem : mem.reg_or_0; + rtx src = mem.store_p ? mem.reg_or_0 : xmem; + + rtx_insn *next = emit_move_ccc_after (dest, src, mem.insn); + add_reg_note (next, REG_INC, mem.addr_reg); + avr_dump (";; new Mem[%d] insn %d after %d: %r = %r\n\n", mem.addr_regno, + INSN_UID (next), INSN_UID (mem.insn), dest, src); + + // Changing REG or POST_INC -> PRE_DEC means that the addend before + // the memory access must be increased by the size of the access, + rtx plus = plus_constant (Pmode, add.src, msize); + if (! REG_P (plus)) + { + rtx_insn *insn = emit_move_ccc_after (add.dest, plus, add.insn); + avr_dump (";; #2 new Add[%d] insn %d after %d: R%d += %d\n\n", + add.regno, INSN_UID (insn), INSN_UID (add.insn), + add.regno, (int) INTVAL (XEXP (plus, 1))); + gcc_assert (GET_CODE (plus) == PLUS); + } + else + avr_dump (";; Add[%d] insn %d consumed into %d\n\n", + add.regno, INSN_UID (add.insn), INSN_UID (next)); + + // Changing POST_INC -> PRE_DEC means that the addend after the mem has to be + // the size of the access. The hope is that this new add insn may be unused. + if (mem.addr_code == POST_INC) + { + plus = plus_constant (Pmode, add.dest, msize); + rtx_insn *next2 = emit_move_ccc_after (add.dest, plus, next); + avr_dump (";; #3 new Add[%d] insn %d after %d: R%d += %d\n\n", add.regno, + INSN_UID (next2), INSN_UID (next), add.regno, msize); + next = next2; + } + + add.set_deleted (); + mem.set_deleted (); + + return next; +} + +/* Try to combine a load or store insn with a PLUS of the address register. + If MEM is valid, then it precedes ADD in the same basic block. + When a replacement is found, a new insn is emitted and the old insns + are pseudo-deleted. The returned insn is the point where the calling + scanner should continue. When no replacement is found, nullptr is + returned and nothing changed. */ + +rtx_insn * +avr_pass_fuse_add::fuse_mem_add (Mem_Insn &mem, Add_Insn &add) +{ + if (! mem.valid () + || reg_seen_between_p (add.dest, mem.insn, add.insn)) + { + // If something is between the Mem and the current insn, we can + // set the Mem invalid to speed future scans. + return mem.insn = nullptr; + } + + AVR_LdSt_Props ap { mem }; + + int msize = GET_MODE_SIZE (mem.mode); + + // The add insn can be consumed by a POST_INC. + bool case1 = (mem.addr_code == REG + && INTVAL (add.addend) == msize + && ap.has_postinc && ! ap.want_predec); + + // There are cases where even a partial consumption of the offset is better. + // This are the cases where no LD+offset addressing is available, because + // the address register is obviously used after the mem insn, and a mem insn + // with REG addressing mode will have to restore the address. + bool case2 = (mem.addr_code == REG + && msize > 1 && ap.want_postinc && ! ap.has_ldd); + + if (! case1 && ! case2) + return nullptr; + + // Change addressing mode from REG to POST_INC. + rtx xmem = change_address (mem.mem, mem.mode, + gen_rtx_POST_INC (Pmode, mem.addr_reg)); + rtx dest = mem.store_p ? xmem : mem.reg_or_0; + rtx src = mem.store_p ? mem.reg_or_0 : xmem; + + rtx_insn *insn = emit_move_ccc_after (dest, src, mem.insn); + add_reg_note (insn, REG_INC, mem.addr_reg); + avr_dump (";; new Mem[%d] insn %d after %d: %r = %r\n\n", add.regno, + INSN_UID (insn), INSN_UID (mem.insn), dest, src); + + rtx_insn *next = NEXT_INSN (add.insn); + + // Changing REG -> POST_INC means that the post addend must be + // decreased by the size of the access. + rtx plus = plus_constant (Pmode, add.src, -msize); + if (! REG_P (plus)) + { + next = emit_move_ccc_after (mem.addr_reg, plus, add.insn); + avr_dump (";; #4 new Add[%d] insn %d after %d: R%d += %d\n\n", + add.regno, INSN_UID (next), INSN_UID (add.insn), + add.regno, (int) INTVAL (XEXP (plus, 1))); + gcc_assert (GET_CODE (plus) == PLUS); + } + else + avr_dump (";; Add[%d] insn %d consumed into %d\n\n", + add.regno, INSN_UID (add.insn), INSN_UID (insn)); + + add.set_deleted (); + mem.set_deleted (); + + return next; +} + +/* Try to post-reload combine PLUS with CONST_INt of pointer registers with: + - Sets to a constant address. + - PLUS insn of that kind. + - Indirect loads and stores. + In almost all cases, combine opportunities arise from the preparation + done by `avr_split_tiny_move', but in some rare cases combinations are + found for the ordinary cores, too. + As we consider at most one Mem insn per try, there may still be missed + optimizations like POST_INC + PLUS + POST_INC might be performed + as PRE_DEC + PRE_DEC for two adjacent locations. */ + +unsigned int +avr_pass_fuse_add::execute (function *func) +{ + df_note_add_problem (); + df_analyze (); + + int n_add = 0, n_mem = 0, n_ldi = 0; + basic_block bb; + + FOR_EACH_BB_FN (bb, func) + { + Ldi_Insn prev_ldi_insns[32]; + Add_Insn prev_add_insns[32]; + Mem_Insn prev_mem_insns[32]; + rtx_insn *insn, *curr; + + avr_dump ("\n;; basic block %d\n\n", bb->index); + + FOR_BB_INSNS_SAFE (bb, insn, curr) + { + rtx_insn *next = nullptr; + Ldi_Insn ldi_insn { insn }; + Add_Insn add_insn { insn }; + Mem_Insn mem_insn { insn }; + + if (add_insn.valid ()) + { + // Found reg:HI += const_int + avr_dump (";; insn %d: Add[%d]: R%d += %d\n\n", + INSN_UID (add_insn.insn), add_insn.regno, + add_insn.regno, (int) INTVAL (add_insn.addend)); + Ldi_Insn &prev_ldi_insn = prev_ldi_insns[add_insn.regno]; + Add_Insn &prev_add_insn = prev_add_insns[add_insn.regno]; + Mem_Insn &prev_mem_insn = prev_mem_insns[add_insn.regno]; + if ((next = fuse_ldi_add (prev_ldi_insn, add_insn))) + curr = next, n_ldi += 1; + else if ((next = fuse_add_add (prev_add_insn, add_insn))) + curr = next, n_add += 1; + else if ((next = fuse_mem_add (prev_mem_insn, add_insn))) + curr = next, n_mem += 1; + else + prev_add_insn = add_insn; + } + else if (mem_insn.valid ()) + { + int addr_regno = REGNO (mem_insn.addr_reg); + avr_dump (";; insn %d: Mem[%d]: %r = %r\n\n", + INSN_UID (mem_insn.insn), addr_regno, + mem_insn.dest, mem_insn.src); + Add_Insn &prev_add_insn = prev_add_insns[addr_regno]; + if ((next = fuse_add_mem (prev_add_insn, mem_insn))) + curr = next, n_mem += 1; + else + prev_mem_insns[addr_regno] = mem_insn; + } + else if (ldi_insn.valid ()) + { + if (! CONST_INT_P (ldi_insn.src)) + avr_dump (";; insn %d: Ldi[%d]: R%d = %r\n\n", + INSN_UID (ldi_insn.insn), ldi_insn.regno, + ldi_insn.regno, ldi_insn.src); + prev_ldi_insns[ldi_insn.regno] = ldi_insn; + } + } // for insns + } // for BBs + + avr_dump (";; Function %f: Found %d changes: %d ldi, %d add, %d mem.\n", + n_ldi + n_add + n_mem, n_ldi, n_add, n_mem); + + return 0; +} + + namespace { static const pass_data avr_pass_data_pre_proep = { @@ -2776,7 +3355,10 @@ avr_legitimate_address_p (machine_mode mode, rtx x, bool strict) && CONST_INT_P (op1) && INTVAL (op1) >= 0) { - bool fit = IN_RANGE (INTVAL (op1), 0, MAX_LD_OFFSET (mode)); + bool fit = (IN_RANGE (INTVAL (op1), 0, MAX_LD_OFFSET (mode)) + // Reduced Tiny does not support PLUS addressing + // anyway, so we are not restricted to LD offset. + || AVR_TINY); if (fit) { @@ -6018,6 +6600,174 @@ out_movhi_mr_r (rtx_insn *insn, rtx op[], int *plen) } +/* During reload, we allow much more addresses than Reduced Tiny actually + supports. Split them after reload in order to get closer to the + core's capabilities. This sets the stage for pass .avr-fuse-add. */ + +bool +avr_split_tiny_move (rtx_insn * /*insn*/, rtx *xop) +{ + bool store_p = false; + rtx mem, reg_or_0; + + if (REG_P (xop[0]) && MEM_P (xop[1])) + { + reg_or_0 = xop[0]; + mem = xop[1]; + } + else if (MEM_P (xop[0]) + && (REG_P (xop[1]) + || xop[1] == CONST0_RTX (GET_MODE (xop[0])))) + { + mem = xop[0]; + reg_or_0 = xop[1]; + store_p = true; + } + else + return false; + + machine_mode mode = GET_MODE (mem); + rtx base, addr = XEXP (mem, 0); + enum rtx_code addr_code = GET_CODE (addr); + + if (REG_P (reg_or_0) + && reg_overlap_mentioned_p (reg_or_0, addr)) + return false; + else if (addr_code == PLUS || addr_code == PRE_DEC || addr_code == POST_INC) + base = XEXP (addr, 0); + else if (addr_code == REG) + base = addr; + else + return false; + + if (REGNO (base) > REG_Z) + return false; + + bool volatile_p = MEM_VOLATILE_P (mem); + bool mem_volatile_p = false; + if (frame_pointer_needed + && REGNO (base) == FRAME_POINTER_REGNUM) + { + if (avr_fuse_add < 2 + // Be a projection (we always split PLUS). + || (avr_fuse_add == 2 && volatile_p && addr_code != PLUS)) + return false; + + // Changing the frame pointer locally may confuse later passes + // like .dse2 which don't track changes of FP, not even when + // respective CFA notes are present. An example is pr22141-1.c. + if (avr_fuse_add == 2) + mem_volatile_p = true; + } + + enum rtx_code new_code = UNKNOWN; + HOST_WIDE_INT add = 0, sub = 0; + int msize = GET_MODE_SIZE (mode); + + AVR_LdSt_Props ap { REGNO (base), store_p, volatile_p, ADDR_SPACE_GENERIC }; + + switch (addr_code) + { + default: + return false; + + case PLUS: + add = INTVAL (XEXP (addr, 1)); + if (msize == 1) + { + new_code = REG; + sub = -add; + } + else if (ap.want_predec) + { + // volatile stores prefer PRE_DEC (MSB first) + sub = -add; + add += msize; + new_code = PRE_DEC; + } + else + { + new_code = POST_INC; + sub = -add - msize; + } + break; + + case POST_INC: + // volatile stores prefer PRE_DEC (MSB first) + if (msize > 1 && ap.want_predec) + { + add = msize; + new_code = PRE_DEC; + sub = msize; + break; + } + return false; + + case PRE_DEC: + // volatile loads prefer POST_INC (LSB first) + if (msize > 1 && ap.want_postinc) + { + add = -msize; + new_code = POST_INC; + sub = -msize; + break; + } + return false; + + case REG: + if (msize == 1) + return false; + + if (ap.want_predec) + { + add = msize; + new_code = PRE_DEC; + sub = 0; + } + else + { + add = 0; + new_code = POST_INC; + sub = -msize; + } + break; + } // switch addr_code + + rtx_insn *insn; + + if (add) + { + insn = emit_move_ccc (base, plus_constant (Pmode, base, add)); + avr_maybe_adjust_cfa (insn, base, add); + } + + rtx new_addr = new_code == REG + ? base + : gen_rtx_fmt_e (new_code, Pmode, base); + + rtx new_mem = change_address (mem, mode, new_addr); + if (mem_volatile_p) + MEM_VOLATILE_P (new_mem) = 1; + + insn = emit_move_ccc (store_p ? new_mem : reg_or_0, + store_p ? reg_or_0 : new_mem); + if (auto_inc_p (new_addr)) + { + add_reg_note (insn, REG_INC, base); + int off = new_code == POST_INC ? msize : -msize; + avr_maybe_adjust_cfa (insn, base, off); + } + + if (sub) + { + insn = emit_move_ccc (base, plus_constant (Pmode, base, sub)); + avr_maybe_adjust_cfa (insn, base, sub); + } + + return true; +} + + /* Implement `TARGET_FRAME_POINTER_REQUIRED'. */ /* Return 1 if frame pointer for current function required. */ @@ -8222,6 +8972,28 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, } } + if (AVR_TINY + && optimize + && i == 0 + && n_bytes == 2 + // When that pass adjusts the frame pointer, then we know that + // reg Y points to ordinary memory, and the only side-effect + // of -Y and Y+ is the side effect on Y. + && avr_fuse_add >= 2 + && frame_pointer_needed + && REGNO (xop[0]) == FRAME_POINTER_REGNUM) + { + rtx xval16 = simplify_gen_subreg (HImode, xval, imode, i); + if (xval16 == const1_rtx || xval16 == constm1_rtx) + { + avr_asm_len ((code == PLUS) == (xval16 == const1_rtx) + ? "ld __tmp_reg__,%a0+" + : "ld __tmp_reg__,-%a0", xop, plen, 1); + i++; + continue; + } + } + if (val8 == 0) { if (started) @@ -12812,6 +13584,11 @@ avr_mode_code_base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, return POINTER_Z_REGS; } + if (AVR_TINY) + // We allow all offsets for all pointer regs. Pass .avr-fuse-add + // will rectify it (register allocation cannot do it). + return POINTER_REGS; + if (!avr_strict_X) return reload_completed ? BASE_POINTER_REGS : POINTER_REGS; @@ -12873,6 +13650,12 @@ avr_regno_mode_code_ok_for_base_p (int regno, } if (avr_strict_X + // On Reduced Tiny, all registers are equal in that they do not + // support PLUS addressing; respective addresses will be fake, + // even for the frame pointer. They must be handled in the + // printers by add-store-sub sequences -- or may be split after + // reload by `avr_split_tiny_move'. + && ! AVR_TINY && PLUS == outer_code && regno == REG_X) { diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 49e5867..8f6bc28 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -956,6 +956,30 @@ operands[4] = gen_int_mode (-GET_MODE_SIZE (mode), HImode); }) + +;; Legitimate address and stuff allows way more addressing modes than +;; Reduced Tiny actually supports. Split them now so that we get +;; closer to real instructions which may result in some optimization +;; opportunities. +(define_split + [(parallel [(set (match_operand:MOVMODE 0 "nonimmediate_operand") + (match_operand:MOVMODE 1 "general_operand")) + (clobber (reg:CC REG_CC))])] + "AVR_TINY + && reload_completed + && avr_fuse_add > 0 + // Only split this for .split2 when we are before + // pass .avr-fuse-add (which runs after proep). + && ! epilogue_completed + && (MEM_P (operands[0]) || MEM_P (operands[1]))" + [(scratch)] + { + if (avr_split_tiny_move (curr_insn, operands)) + DONE; + FAIL; + }) + + ;;========================================================================== ;; xpointer move (24 bit) @@ -6704,6 +6728,11 @@ (match_operand:HISI 1 "const_int_operand"))) (clobber (match_operand:QI 2 "scratch_operand"))])]) +(define_expand "gen_move_clobbercc" + [(parallel [(set (match_operand 0) + (match_operand 1)) + (clobber (reg:CC REG_CC))])]) + ;; ---------------------------------------------------------------------- ;; JUMP INSTRUCTIONS ;; ---------------------------------------------------------------------- diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/avr.opt index 76530fd..ea35b7d 100644 --- a/gcc/config/avr/avr.opt +++ b/gcc/config/avr/avr.opt @@ -107,6 +107,14 @@ msp8 Target RejectNegative Var(avr_sp8) Init(0) The device has no SPH special function register. This option will be overridden by the compiler driver with the correct setting if presence/absence of SPH can be deduced from -mmcu=MCU. +mfuse-add +Target Alias(mfuse-add=, 1, 0) Optimization +Split register additions from load/store instructions. Most useful on Reduced Tiny. + +mfuse-add= +Target Joined RejectNegative UInteger Var(avr_fuse_add) Init(0) Optimization IntegerRange(0, 3) +Split register additions from load/store instructions. Most useful on Reduced Tiny. + Waddr-space-convert Warning C Var(avr_warn_addr_space_convert) Init(0) Warn if the address space of an address is changed. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 4f4ca2b..7862c75 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -884,7 +884,7 @@ Objective-C and Objective-C++ Dialects}. @emph{AVR Options} @gccoptlist{-mmcu=@var{mcu} -mabsdata -maccumulate-args --mbranch-cost=@var{cost} +-mbranch-cost=@var{cost} -mfuse-add=@var{level} -mcall-prologues -mgas-isr-prologues -mint8 -mflmap -mdouble=@var{bits} -mlong-double=@var{bits} -mn_flash=@var{size} -mno-interrupts @@ -23785,6 +23785,14 @@ integers. The default branch cost is 0. Functions prologues/epilogues are expanded as calls to appropriate subroutines. Code size is smaller. +@opindex mfuse-add +@item -mfuse-add +@itemx -mno-fuse-add +@itemx -mfuse-add=@var{level} +Optimize indirect memory accesses on reduced Tiny devices. +The default uses @code{@var{level}=1} for optimizations @option{-Og} +and @option{-O1}, and @code{@var{level}=2} for higher optimizations. + @opindex mdouble @opindex mlong-double @item -mdouble=@var{bits} -- cgit v1.1 From c0d8a64e72324d1c2981da21a66394bf8f7a2889 Mon Sep 17 00:00:00 2001 From: David Malcolm Date: Thu, 29 Feb 2024 17:57:08 -0500 Subject: analyzer: fix ICE in call summarization [PR114159] PR analyzer/114159 reports an ICE inside playback of call summaries for very low values of --param=analyzer-max-svalue-depth=VAL. Root cause is that call_summary_edge_info's ctor tries to evaluate the function ptr of a gimple call stmt and assumes it gets a function *, but with low values of --param=analyzer-max-svalue-depth=VAL we get back an UNKNOWN svalue, rather than a pointer to a specific function. Fix by adding a new call_info ctor that passes a specific const function & from the call_summary_edge_info, rather than trying to compute the function. In doing so, I noticed that the analyzer was using "function *" despite not modifying functions, and was sloppy about can-be-null versus must-be-non-null function pointers, so I "constified" the function, and converted the many places where the function must be non-null to be "const function &". gcc/analyzer/ChangeLog: PR analyzer/114159 * analyzer.cc: Include "tree-dfa.h". (get_ssa_default_def): New decl. * analyzer.h (get_ssa_default_def): New. * call-info.cc (call_info::call_info): New ctor taking an explicit called_fn. * call-info.h (call_info::call_info): Likewise. * call-summary.cc (call_summary_replay::call_summary_replay): Convert param from function * to const function &. * call-summary.h (call_summary_replay::call_summary_replay): Likewise. * checker-event.h (state_change_event::get_dest_function): Constify return value. * engine.cc (point_and_state::validate): Update for conversion to const function &. (exploded_node::on_stmt): Likewise. (call_summary_edge_info::call_summary_edge_info): Likewise. Pass in called_fn to call_info ctor. (exploded_node::replay_call_summaries): Update for conversion to const function &. Convert per_function_data from * to &. (exploded_node::replay_call_summary): Update for conversion to const function &. (exploded_graph::add_function_entry): Likewise. (toplevel_function_p): Likewise. (add_tainted_args_callback): Likewise. (exploded_graph::build_initial_worklist): Likewise. (exploded_graph::maybe_create_dynamic_call): Likewise. (maybe_update_for_edge): Likewise. (exploded_graph::on_escaped_function): Likewise. * exploded-graph.h (exploded_node::replay_call_summaries): Likewise. (exploded_node::replay_call_summary): Likewise. (exploded_graph::add_function_entry): Likewise. * program-point.cc (function_point::from_function_entry): Likewise. (program_point::from_function_entry): Likewise. * program-point.h (function_point::from_function_entry): Likewise. (program_point::from_function_entry): Likewise. * program-state.cc (program_state::push_frame): Likewise. (program_state::get_current_function): Constify return type. * program-state.h (program_state::push_frame): Update for conversion to const function &. (program_state::get_current_function): Likewise. * region-model-manager.cc (region_model_manager::get_frame_region): Likewise. * region-model-manager.h (region_model_manager::get_frame_region): Likewise. * region-model.cc (region_model::called_from_main_p): Likewise. (region_model::update_for_gcall): Likewise. (region_model::push_frame): Likewise. (region_model::get_current_function): Constify return type. (region_model::pop_frame): Update for conversion to const function &. (selftest::test_stack_frames): Likewise. (selftest::test_get_representative_path_var): Likewise. (selftest::test_state_merging): Likewise. (selftest::test_alloca): Likewise. * region-model.h (region_model::push_frame): Likewise. (region_model::get_current_function): Likewise. * region.cc (frame_region::dump_to_pp): Likewise. (frame_region::get_region_for_local): Likewise. * region.h (class frame_region): Likewise. * sm-signal.cc (signal_unsafe_call::describe_state_change): Likewise. (update_model_for_signal_handler): Likewise. (signal_delivery_edge_info_t::update_model): Likewise. (register_signal_handler::impl_transition): Likewise. * state-purge.cc (class gimple_op_visitor): Likewise. (state_purge_map::state_purge_map): Likewise. (state_purge_map::get_or_create_data_for_decl): Likewise. (state_purge_per_ssa_name::state_purge_per_ssa_name): Likewise. (state_purge_per_ssa_name::add_to_worklist): Likewise. (state_purge_per_ssa_name::process_point): Likewise. (state_purge_per_decl::add_to_worklist): Likewise. (state_purge_annotator::print_needed): Likewise. * state-purge.h (state_purge_map::get_or_create_data_for_decl): Likewise. (class state_purge_per_tree): Likewise. (class state_purge_per_ssa_name): Likewise. (class state_purge_per_decl): Likewise. * supergraph.cc (supergraph::dump_dot_to_pp): Likewise. * supergraph.h (supergraph::get_node_for_function_entry): Likewise. (supergraph::get_node_for_function_exit): Likewise. gcc/ChangeLog: PR analyzer/114159 * function.cc (function_name): Make param const. * function.h (function_name): Likewise. gcc/testsuite/ChangeLog: PR analyzer/114159 * c-c++-common/analyzer/call-summaries-pr114159.c: New test. Signed-off-by: David Malcolm --- gcc/analyzer/analyzer.cc | 9 +++ gcc/analyzer/analyzer.h | 3 + gcc/analyzer/call-info.cc | 8 +++ gcc/analyzer/call-info.h | 1 + gcc/analyzer/call-summary.cc | 6 +- gcc/analyzer/call-summary.h | 2 +- gcc/analyzer/checker-event.h | 2 +- gcc/analyzer/engine.cc | 83 +++++++++++----------- gcc/analyzer/exploded-graph.h | 8 +-- gcc/analyzer/program-point.cc | 4 +- gcc/analyzer/program-point.h | 4 +- gcc/analyzer/program-state.cc | 4 +- gcc/analyzer/program-state.h | 4 +- gcc/analyzer/region-model-manager.cc | 2 +- gcc/analyzer/region-model-manager.h | 2 +- gcc/analyzer/region-model.cc | 42 +++++------ gcc/analyzer/region-model.h | 4 +- gcc/analyzer/region.cc | 10 +-- gcc/analyzer/region.h | 18 ++--- gcc/analyzer/sm-signal.cc | 13 ++-- gcc/analyzer/state-purge.cc | 29 ++++---- gcc/analyzer/state-purge.h | 15 ++-- gcc/analyzer/supergraph.cc | 5 +- gcc/analyzer/supergraph.h | 8 +-- gcc/function.cc | 2 +- gcc/function.h | 2 +- .../analyzer/call-summaries-pr114159.c | 20 ++++++ 27 files changed, 181 insertions(+), 129 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/analyzer/call-summaries-pr114159.c (limited to 'gcc') diff --git a/gcc/analyzer/analyzer.cc b/gcc/analyzer/analyzer.cc index 389496c..7f5d3d5 100644 --- a/gcc/analyzer/analyzer.cc +++ b/gcc/analyzer/analyzer.cc @@ -31,6 +31,7 @@ along with GCC; see the file COPYING3. If not see #include "analyzer/analyzer.h" #include "tree-pretty-print.h" #include "diagnostic-event-id.h" +#include "tree-dfa.h" #if ENABLE_ANALYZER @@ -275,6 +276,14 @@ byte_offset_to_json (const byte_offset_t &offset) return new json::string (pp_formatted_text (&pp)); } +/* Workaround for lack of const-correctness of ssa_default_def. */ + +tree +get_ssa_default_def (const function &fun, tree var) +{ + return ssa_default_def (const_cast (&fun), var); +} + } // namespace ana /* Helper function for checkers. Is the CALL to the given function name, diff --git a/gcc/analyzer/analyzer.h b/gcc/analyzer/analyzer.h index 20a8e3f..1d792ed 100644 --- a/gcc/analyzer/analyzer.h +++ b/gcc/analyzer/analyzer.h @@ -433,6 +433,9 @@ compare_constants (tree lhs_const, enum tree_code op, tree rhs_const); extern tree get_string_cst_size (const_tree string_cst); +extern tree +get_ssa_default_def (const function &fun, tree var); + } // namespace ana extern bool is_special_named_call_p (const gcall *call, const char *funcname, diff --git a/gcc/analyzer/call-info.cc b/gcc/analyzer/call-info.cc index 7ec8212..4c965b2 100644 --- a/gcc/analyzer/call-info.cc +++ b/gcc/analyzer/call-info.cc @@ -143,6 +143,14 @@ call_info::call_info (const call_details &cd) gcc_assert (m_fndecl); } +call_info::call_info (const call_details &cd, + const function &called_fn) +: m_call_stmt (cd.get_call_stmt ()), + m_fndecl (called_fn.decl) +{ + gcc_assert (m_fndecl); +} + /* class succeed_or_fail_call_info : public call_info. */ label_text diff --git a/gcc/analyzer/call-info.h b/gcc/analyzer/call-info.h index 9815b41..17d5fdf 100644 --- a/gcc/analyzer/call-info.h +++ b/gcc/analyzer/call-info.h @@ -44,6 +44,7 @@ public: protected: call_info (const call_details &cd); + call_info (const call_details &cd, const function &called_fn); private: const gcall *m_call_stmt; diff --git a/gcc/analyzer/call-summary.cc b/gcc/analyzer/call-summary.cc index ecb6fb1..8b8567a 100644 --- a/gcc/analyzer/call-summary.cc +++ b/gcc/analyzer/call-summary.cc @@ -167,7 +167,7 @@ call_summary::dump (const extrinsic_state &ext_state, bool simple) const arguments at the caller. */ call_summary_replay::call_summary_replay (const call_details &cd, - function *called_fn, + const function &called_fn, call_summary *summary, const extrinsic_state &ext_state) : m_cd (cd), @@ -177,7 +177,7 @@ call_summary_replay::call_summary_replay (const call_details &cd, region_model_manager *mgr = cd.get_manager (); // populate params based on args - tree fndecl = called_fn->decl; + tree fndecl = called_fn.decl; /* Get a frame_region for use with respect to the summary. This will be a top-level frame, since that's what's in @@ -196,7 +196,7 @@ call_summary_replay::call_summary_replay (const call_details &cd, break; const svalue *caller_arg_sval = cd.get_arg_svalue (idx); tree parm_lval = iter_parm; - if (tree parm_default_ssa = ssa_default_def (called_fn, iter_parm)) + if (tree parm_default_ssa = get_ssa_default_def (called_fn, iter_parm)) parm_lval = parm_default_ssa; const region *summary_parm_reg = summary_frame->get_region_for_local (mgr, parm_lval, cd.get_ctxt ()); diff --git a/gcc/analyzer/call-summary.h b/gcc/analyzer/call-summary.h index 73f21ac..220dd083 100644 --- a/gcc/analyzer/call-summary.h +++ b/gcc/analyzer/call-summary.h @@ -68,7 +68,7 @@ class call_summary_replay { public: call_summary_replay (const call_details &cd, - function *called_fn, + const function &called_fn, call_summary *m_summary, const extrinsic_state &ext_state); diff --git a/gcc/analyzer/checker-event.h b/gcc/analyzer/checker-event.h index 7d8915c..d2fb87f 100644 --- a/gcc/analyzer/checker-event.h +++ b/gcc/analyzer/checker-event.h @@ -370,7 +370,7 @@ public: label_text get_desc (bool can_colorize) const final override; meaning get_meaning () const override; - function *get_dest_function () const + const function *get_dest_function () const { return m_dst_state.get_current_function (); } diff --git a/gcc/analyzer/engine.cc b/gcc/analyzer/engine.cc index 44ff20c..ad310b4 100644 --- a/gcc/analyzer/engine.cc +++ b/gcc/analyzer/engine.cc @@ -1072,7 +1072,7 @@ point_and_state::validate (const extrinsic_state &ext_state) const { int index = iter_frame->get_index (); gcc_assert (m_point.get_function_at_depth (index) - == iter_frame->get_function ()); + == &iter_frame->get_function ()); } } @@ -1496,14 +1496,17 @@ exploded_node::on_stmt (exploded_graph &eg, per_function_data *called_fn_data = eg.get_per_function_data (called_fn); if (called_fn_data) - return replay_call_summaries (eg, - snode, - as_a (stmt), - state, - path_ctxt, - called_fn, - called_fn_data, - &ctxt); + { + gcc_assert (called_fn); + return replay_call_summaries (eg, + snode, + as_a (stmt), + state, + path_ctxt, + *called_fn, + *called_fn_data, + &ctxt); + } } bool unknown_side_effects = false; @@ -1610,10 +1613,10 @@ class call_summary_edge_info : public call_info { public: call_summary_edge_info (const call_details &cd, - function *called_fn, + const function &called_fn, call_summary *summary, const extrinsic_state &ext_state) - : call_info (cd), + : call_info (cd, called_fn), m_called_fn (called_fn), m_summary (summary), m_ext_state (ext_state) @@ -1648,7 +1651,7 @@ public: } private: - function *m_called_fn; + const function &m_called_fn; call_summary *m_summary; const extrinsic_state &m_ext_state; }; @@ -1662,18 +1665,15 @@ exploded_node::replay_call_summaries (exploded_graph &eg, const gcall *call_stmt, program_state *state, path_context *path_ctxt, - function *called_fn, - per_function_data *called_fn_data, + const function &called_fn, + per_function_data &called_fn_data, region_model_context *ctxt) { logger *logger = eg.get_logger (); LOG_SCOPE (logger); - gcc_assert (called_fn); - gcc_assert (called_fn_data); - /* Each summary will call bifurcate on the PATH_CTXT. */ - for (auto summary : called_fn_data->m_summaries) + for (auto summary : called_fn_data.m_summaries) replay_call_summary (eg, snode, call_stmt, state, path_ctxt, called_fn, summary, ctxt); path_ctxt->terminate_path (); @@ -1691,7 +1691,7 @@ exploded_node::replay_call_summary (exploded_graph &eg, const gcall *call_stmt, program_state *old_state, path_context *path_ctxt, - function *called_fn, + const function &called_fn, call_summary *summary, region_model_context *ctxt) { @@ -1700,13 +1700,12 @@ exploded_node::replay_call_summary (exploded_graph &eg, gcc_assert (snode); gcc_assert (call_stmt); gcc_assert (old_state); - gcc_assert (called_fn); gcc_assert (summary); if (logger) logger->log ("using %s as summary for call to %qE from %qE", summary->get_desc ().get (), - called_fn->decl, + called_fn.decl, snode->get_function ()->decl); const extrinsic_state &ext_state = eg.get_ext_state (); const program_state &summary_end_state = summary->get_state (); @@ -2784,16 +2783,17 @@ private: Return the exploded_node for the entrypoint to the function. */ exploded_node * -exploded_graph::add_function_entry (function *fun) +exploded_graph::add_function_entry (const function &fun) { - gcc_assert (gimple_has_body_p (fun->decl)); + gcc_assert (gimple_has_body_p (fun.decl)); /* Be idempotent. */ - if (m_functions_with_enodes.contains (fun)) + function *key = const_cast (&fun); + if (m_functions_with_enodes.contains (key)) { logger * const logger = get_logger (); if (logger) - logger->log ("entrypoint for %qE already exists", fun->decl); + logger->log ("entrypoint for %qE already exists", fun.decl); return NULL; } @@ -2805,10 +2805,10 @@ exploded_graph::add_function_entry (function *fun) std::unique_ptr edge_info = NULL; - if (lookup_attribute ("tainted_args", DECL_ATTRIBUTES (fun->decl))) + if (lookup_attribute ("tainted_args", DECL_ATTRIBUTES (fun.decl))) { - if (mark_params_as_tainted (&state, fun->decl, m_ext_state)) - edge_info = make_unique (fun->decl); + if (mark_params_as_tainted (&state, fun.decl, m_ext_state)) + edge_info = make_unique (fun.decl); } if (!state.m_valid) @@ -2820,7 +2820,7 @@ exploded_graph::add_function_entry (function *fun) add_edge (m_origin, enode, NULL, false, std::move (edge_info)); - m_functions_with_enodes.add (fun); + m_functions_with_enodes.add (key); return enode; } @@ -3108,7 +3108,7 @@ exploded_graph::get_per_function_data (function *fun) const called via other functions. */ static bool -toplevel_function_p (function *fun, logger *logger) +toplevel_function_p (const function &fun, logger *logger) { /* Don't directly traverse into functions that have an "__analyzer_" prefix. Doing so is useful for the analyzer test suite, allowing @@ -3119,17 +3119,17 @@ toplevel_function_p (function *fun, logger *logger) excess messages from the case of the first function being traversed directly. */ #define ANALYZER_PREFIX "__analyzer_" - if (!strncmp (IDENTIFIER_POINTER (DECL_NAME (fun->decl)), ANALYZER_PREFIX, + if (!strncmp (IDENTIFIER_POINTER (DECL_NAME (fun.decl)), ANALYZER_PREFIX, strlen (ANALYZER_PREFIX))) { if (logger) logger->log ("not traversing %qE (starts with %qs)", - fun->decl, ANALYZER_PREFIX); + fun.decl, ANALYZER_PREFIX); return false; } if (logger) - logger->log ("traversing %qE (all checks passed)", fun->decl); + logger->log ("traversing %qE (all checks passed)", fun.decl); return true; } @@ -3254,9 +3254,9 @@ add_tainted_args_callback (exploded_graph *eg, tree field, tree fndecl, program_point point = program_point::from_function_entry (*ext_state.get_model_manager (), - eg->get_supergraph (), fun); + eg->get_supergraph (), *fun); program_state state (ext_state); - state.push_frame (ext_state, fun); + state.push_frame (ext_state, *fun); if (!mark_params_as_tainted (&state, fndecl, ext_state)) return; @@ -3330,9 +3330,10 @@ exploded_graph::build_initial_worklist () FOR_EACH_FUNCTION_WITH_GIMPLE_BODY (node) { function *fun = node->get_fun (); - if (!toplevel_function_p (fun, logger)) + gcc_assert (fun); + if (!toplevel_function_p (*fun, logger)) continue; - exploded_node *enode = add_function_entry (fun); + exploded_node *enode = add_function_entry (*fun); if (logger) { if (enode) @@ -3838,8 +3839,8 @@ exploded_graph::maybe_create_dynamic_call (const gcall *call, if (fun) { const supergraph &sg = this->get_supergraph (); - supernode *sn_entry = sg.get_node_for_function_entry (fun); - supernode *sn_exit = sg.get_node_for_function_exit (fun); + supernode *sn_entry = sg.get_node_for_function_entry (*fun); + supernode *sn_exit = sg.get_node_for_function_exit (*fun); program_point new_point = program_point::before_supernode (sn_entry, @@ -4962,7 +4963,7 @@ maybe_update_for_edge (logger *logger, == PK_BEFORE_SUPERNODE); function *fun = eedge->m_dest->get_function (); gcc_assert (fun); - m_model.push_frame (fun, NULL, ctxt); + m_model.push_frame (*fun, NULL, ctxt); if (logger) logger->log (" pushing frame for %qD", fun->decl); } @@ -5582,7 +5583,7 @@ exploded_graph::on_escaped_function (tree fndecl) if (!gimple_has_body_p (fndecl)) return; - exploded_node *enode = add_function_entry (fun); + exploded_node *enode = add_function_entry (*fun); if (logger) { if (enode) diff --git a/gcc/analyzer/exploded-graph.h b/gcc/analyzer/exploded-graph.h index 387ae3a..642d69b 100644 --- a/gcc/analyzer/exploded-graph.h +++ b/gcc/analyzer/exploded-graph.h @@ -285,15 +285,15 @@ class exploded_node : public dnode const gcall *call_stmt, program_state *state, path_context *path_ctxt, - function *called_fn, - per_function_data *called_fn_data, + const function &called_fn, + per_function_data &called_fn_data, region_model_context *ctxt); void replay_call_summary (exploded_graph &eg, const supernode *snode, const gcall *call_stmt, program_state *state, path_context *path_ctxt, - function *called_fn, + const function &called_fn, call_summary *summary, region_model_context *ctxt); @@ -810,7 +810,7 @@ public: exploded_node *get_origin () const { return m_origin; } - exploded_node *add_function_entry (function *fun); + exploded_node *add_function_entry (const function &fun); void build_initial_worklist (); void process_worklist (); diff --git a/gcc/analyzer/program-point.cc b/gcc/analyzer/program-point.cc index 5e98b52..6e225cf 100644 --- a/gcc/analyzer/program-point.cc +++ b/gcc/analyzer/program-point.cc @@ -230,7 +230,7 @@ function_point::final_stmt_p () const /* Create a function_point representing the entrypoint of function FUN. */ function_point -function_point::from_function_entry (const supergraph &sg, function *fun) +function_point::from_function_entry (const supergraph &sg, const function &fun) { return before_supernode (sg.get_node_for_function_entry (fun), NULL); } @@ -698,7 +698,7 @@ program_point::origin (const region_model_manager &mgr) program_point program_point::from_function_entry (const region_model_manager &mgr, const supergraph &sg, - function *fun) + const function &fun) { return program_point (function_point::from_function_entry (sg, fun), mgr.get_empty_call_string ()); diff --git a/gcc/analyzer/program-point.h b/gcc/analyzer/program-point.h index 62c2c94..61b895f 100644 --- a/gcc/analyzer/program-point.h +++ b/gcc/analyzer/program-point.h @@ -112,7 +112,7 @@ public: /* Factory functions for making various kinds of program_point. */ static function_point from_function_entry (const supergraph &sg, - function *fun); + const function &fun); static function_point before_supernode (const supernode *supernode, const superedge *from_edge); @@ -252,7 +252,7 @@ public: static program_point origin (const region_model_manager &mgr); static program_point from_function_entry (const region_model_manager &mgr, const supergraph &sg, - function *fun); + const function &fun); static program_point before_supernode (const supernode *supernode, const superedge *from_edge, diff --git a/gcc/analyzer/program-state.cc b/gcc/analyzer/program-state.cc index 55dd6ca..c88652b 100644 --- a/gcc/analyzer/program-state.cc +++ b/gcc/analyzer/program-state.cc @@ -1143,14 +1143,14 @@ program_state::to_json (const extrinsic_state &ext_state) const void program_state::push_frame (const extrinsic_state &ext_state ATTRIBUTE_UNUSED, - function *fun) + const function &fun) { m_region_model->push_frame (fun, NULL, NULL); } /* Get the current function of this state. */ -function * +const function * program_state::get_current_function () const { return m_region_model->get_current_function (); diff --git a/gcc/analyzer/program-state.h b/gcc/analyzer/program-state.h index 69bf931..3ba6a93 100644 --- a/gcc/analyzer/program-state.h +++ b/gcc/analyzer/program-state.h @@ -226,8 +226,8 @@ public: json::object *to_json (const extrinsic_state &ext_state) const; - void push_frame (const extrinsic_state &ext_state, function *fun); - function * get_current_function () const; + void push_frame (const extrinsic_state &ext_state, const function &fun); + const function * get_current_function () const; void push_call (exploded_graph &eg, exploded_node *enode, diff --git a/gcc/analyzer/region-model-manager.cc b/gcc/analyzer/region-model-manager.cc index 93e72ec..8530f49 100644 --- a/gcc/analyzer/region-model-manager.cc +++ b/gcc/analyzer/region-model-manager.cc @@ -1676,7 +1676,7 @@ region_model_manager::get_cast_region (const region *original_region, const frame_region * region_model_manager::get_frame_region (const frame_region *calling_frame, - function *fun) + const function &fun) { int index = calling_frame ? calling_frame->get_index () + 1 : 0; diff --git a/gcc/analyzer/region-model-manager.h b/gcc/analyzer/region-model-manager.h index 5c89de1..7d1208c 100644 --- a/gcc/analyzer/region-model-manager.h +++ b/gcc/analyzer/region-model-manager.h @@ -131,7 +131,7 @@ public: const region *get_cast_region (const region *original_region, tree type); const frame_region *get_frame_region (const frame_region *calling_frame, - function *fun); + const function &fun); const region *get_symbolic_region (const svalue *sval); const string_region *get_region_for_string (tree string_cst); const region *get_bit_range (const region *parent, tree type, diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc index 6ab9174..33a4584 100644 --- a/gcc/analyzer/region-model.cc +++ b/gcc/analyzer/region-model.cc @@ -2619,7 +2619,7 @@ region_model::called_from_main_p () const /* Determine if the oldest stack frame in this model is for "main". */ const frame_region *frame0 = get_frame_at_index (0); gcc_assert (frame0); - return id_equal (DECL_NAME (frame0->get_function ()->decl), "main"); + return id_equal (DECL_NAME (frame0->get_function ().decl), "main"); } /* Subroutine of region_model::get_store_value for when REG is (or is within) @@ -5552,7 +5552,8 @@ region_model::update_for_gcall (const gcall *call_stmt, callee = DECL_STRUCT_FUNCTION (fn_decl); } - push_frame (callee, &arg_svals, ctxt); + gcc_assert (callee); + push_frame (*callee, &arg_svals, ctxt); } /* Pop the top-most frame_region from the stack, and copy the return @@ -5896,14 +5897,15 @@ region_model::on_top_level_param (tree param, Return the frame_region for the new frame. */ const region * -region_model::push_frame (function *fun, const vec *arg_svals, +region_model::push_frame (const function &fun, + const vec *arg_svals, region_model_context *ctxt) { m_current_frame = m_mgr->get_frame_region (m_current_frame, fun); if (arg_svals) { /* Arguments supplied from a caller frame. */ - tree fndecl = fun->decl; + tree fndecl = fun.decl; unsigned idx = 0; for (tree iter_parm = DECL_ARGUMENTS (fndecl); iter_parm; iter_parm = DECL_CHAIN (iter_parm), ++idx) @@ -5914,7 +5916,7 @@ region_model::push_frame (function *fun, const vec *arg_svals, if (idx >= arg_svals->length ()) break; tree parm_lval = iter_parm; - if (tree parm_default_ssa = ssa_default_def (fun, iter_parm)) + if (tree parm_default_ssa = get_ssa_default_def (fun, iter_parm)) parm_lval = parm_default_ssa; const region *parm_reg = get_lvalue (parm_lval, ctxt); const svalue *arg_sval = (*arg_svals)[idx]; @@ -5937,7 +5939,7 @@ region_model::push_frame (function *fun, const vec *arg_svals, /* Otherwise we have a top-level call within the analysis. The params have defined but unknown initial values. Anything they point to has escaped. */ - tree fndecl = fun->decl; + tree fndecl = fun.decl; /* Handle "__attribute__((nonnull))". */ tree fntype = TREE_TYPE (fndecl); @@ -5951,7 +5953,7 @@ region_model::push_frame (function *fun, const vec *arg_svals, ? (bitmap_empty_p (nonnull_args) || bitmap_bit_p (nonnull_args, parm_idx)) : false); - if (tree parm_default_ssa = ssa_default_def (fun, iter_parm)) + if (tree parm_default_ssa = get_ssa_default_def (fun, iter_parm)) on_top_level_param (parm_default_ssa, non_null, ctxt); else on_top_level_param (iter_parm, non_null, ctxt); @@ -5967,12 +5969,12 @@ region_model::push_frame (function *fun, const vec *arg_svals, /* Get the function of the top-most frame in this region_model's stack. There must be such a frame. */ -function * +const function * region_model::get_current_function () const { const frame_region *frame = get_current_frame (); gcc_assert (frame); - return frame->get_function (); + return &frame->get_function (); } /* Pop the topmost frame_region from this region_model's stack; @@ -6007,7 +6009,7 @@ region_model::pop_frame (tree result_lvalue, ctxt->on_pop_frame (frame_reg); /* Evaluate the result, within the callee frame. */ - tree fndecl = m_current_frame->get_function ()->decl; + tree fndecl = m_current_frame->get_function ().decl; tree result = DECL_RESULT (fndecl); const svalue *retval = NULL; if (result @@ -7966,7 +7968,7 @@ test_stack_frames () /* Push stack frame for "parent_fn". */ const region *parent_frame_reg - = model.push_frame (DECL_STRUCT_FUNCTION (parent_fndecl), + = model.push_frame (*DECL_STRUCT_FUNCTION (parent_fndecl), NULL, &ctxt); ASSERT_EQ (model.get_current_frame (), parent_frame_reg); ASSERT_TRUE (model.region_exists_p (parent_frame_reg)); @@ -7982,7 +7984,7 @@ test_stack_frames () /* Push stack frame for "child_fn". */ const region *child_frame_reg - = model.push_frame (DECL_STRUCT_FUNCTION (child_fndecl), NULL, &ctxt); + = model.push_frame (*DECL_STRUCT_FUNCTION (child_fndecl), NULL, &ctxt); ASSERT_EQ (model.get_current_frame (), child_frame_reg); ASSERT_TRUE (model.region_exists_p (child_frame_reg)); const region *x_in_child_reg = model.get_lvalue (x, &ctxt); @@ -8075,7 +8077,7 @@ test_get_representative_path_var () for (int depth = 0; depth < 5; depth++) { const region *frame_n_reg - = model.push_frame (DECL_STRUCT_FUNCTION (fndecl), NULL, &ctxt); + = model.push_frame (*DECL_STRUCT_FUNCTION (fndecl), NULL, &ctxt); const region *parm_n_reg = model.get_lvalue (path_var (n, depth), &ctxt); parm_regs.safe_push (parm_n_reg); @@ -8319,9 +8321,9 @@ test_state_merging () region_model model0 (&mgr); region_model model1 (&mgr); ASSERT_EQ (model0.get_stack_depth (), 0); - model0.push_frame (DECL_STRUCT_FUNCTION (test_fndecl), NULL, &ctxt); + model0.push_frame (*DECL_STRUCT_FUNCTION (test_fndecl), NULL, &ctxt); ASSERT_EQ (model0.get_stack_depth (), 1); - model1.push_frame (DECL_STRUCT_FUNCTION (test_fndecl), NULL, &ctxt); + model1.push_frame (*DECL_STRUCT_FUNCTION (test_fndecl), NULL, &ctxt); placeholder_svalue test_sval (mgr.alloc_symbol_id (), integer_type_node, "test sval"); @@ -8413,7 +8415,7 @@ test_state_merging () /* Pointers: non-NULL and non-NULL: ptr to a local. */ { region_model model0 (&mgr); - model0.push_frame (DECL_STRUCT_FUNCTION (test_fndecl), NULL, NULL); + model0.push_frame (*DECL_STRUCT_FUNCTION (test_fndecl), NULL, NULL); model0.set_value (model0.get_lvalue (p, NULL), model0.get_rvalue (addr_of_a, NULL), NULL); @@ -8552,12 +8554,12 @@ test_state_merging () frame points to a local in a more recent stack frame. */ { region_model model0 (&mgr); - model0.push_frame (DECL_STRUCT_FUNCTION (test_fndecl), NULL, NULL); + model0.push_frame (*DECL_STRUCT_FUNCTION (test_fndecl), NULL, NULL); const region *q_in_first_frame = model0.get_lvalue (q, NULL); /* Push a second frame. */ const region *reg_2nd_frame - = model0.push_frame (DECL_STRUCT_FUNCTION (test_fndecl), NULL, NULL); + = model0.push_frame (*DECL_STRUCT_FUNCTION (test_fndecl), NULL, NULL); /* Have a pointer in the older frame point to a local in the more recent frame. */ @@ -8584,7 +8586,7 @@ test_state_merging () /* Verify that we can merge a model in which a local points to a global. */ { region_model model0 (&mgr); - model0.push_frame (DECL_STRUCT_FUNCTION (test_fndecl), NULL, NULL); + model0.push_frame (*DECL_STRUCT_FUNCTION (test_fndecl), NULL, NULL); model0.set_value (model0.get_lvalue (q, NULL), model0.get_rvalue (addr_of_y, NULL), NULL); @@ -9110,7 +9112,7 @@ test_alloca () /* Push stack frame. */ const region *frame_reg - = model.push_frame (DECL_STRUCT_FUNCTION (fndecl), + = model.push_frame (*DECL_STRUCT_FUNCTION (fndecl), NULL, &ctxt); /* "p = alloca (n * 4);". */ const svalue *size_sval = model.get_rvalue (n_times_4, &ctxt); diff --git a/gcc/analyzer/region-model.h b/gcc/analyzer/region-model.h index d4ef101..118e0f2 100644 --- a/gcc/analyzer/region-model.h +++ b/gcc/analyzer/region-model.h @@ -347,10 +347,10 @@ class region_model void update_for_return_gcall (const gcall *call_stmt, region_model_context *ctxt); - const region *push_frame (function *fun, const vec *arg_sids, + const region *push_frame (const function &fun, const vec *arg_sids, region_model_context *ctxt); const frame_region *get_current_frame () const { return m_current_frame; } - function * get_current_function () const; + const function *get_current_function () const; void pop_frame (tree result_lvalue, const svalue **out_result, region_model_context *ctxt, diff --git a/gcc/analyzer/region.cc b/gcc/analyzer/region.cc index 50821a5..d457061 100644 --- a/gcc/analyzer/region.cc +++ b/gcc/analyzer/region.cc @@ -1306,10 +1306,10 @@ void frame_region::dump_to_pp (pretty_printer *pp, bool simple) const { if (simple) - pp_printf (pp, "frame: %qs@%i", function_name (m_fun), get_stack_depth ()); + pp_printf (pp, "frame: %qs@%i", function_name (&m_fun), get_stack_depth ()); else pp_printf (pp, "frame_region(%qs, index: %i, depth: %i)", - function_name (m_fun), m_index, get_stack_depth ()); + function_name (&m_fun), m_index, get_stack_depth ()); } const decl_region * @@ -1334,14 +1334,14 @@ frame_region::get_region_for_local (region_model_manager *mgr, /* Fall through. */ case PARM_DECL: case RESULT_DECL: - gcc_assert (DECL_CONTEXT (expr) == m_fun->decl); + gcc_assert (DECL_CONTEXT (expr) == m_fun.decl); break; case SSA_NAME: { if (tree var = SSA_NAME_VAR (expr)) { if (DECL_P (var)) - gcc_assert (DECL_CONTEXT (var) == m_fun->decl); + gcc_assert (DECL_CONTEXT (var) == m_fun.decl); } else if (ctxt) if (const extrinsic_state *ext_state = ctxt->get_ext_state ()) @@ -1351,7 +1351,7 @@ frame_region::get_region_for_local (region_model_manager *mgr, const gimple *def_stmt = SSA_NAME_DEF_STMT (expr); const supernode *snode = sg->get_supernode_for_stmt (def_stmt); - gcc_assert (snode->get_function () == m_fun); + gcc_assert (snode->get_function () == &m_fun); } } break; diff --git a/gcc/analyzer/region.h b/gcc/analyzer/region.h index 70557ba..73f35f5 100644 --- a/gcc/analyzer/region.h +++ b/gcc/analyzer/region.h @@ -305,11 +305,10 @@ public: /* A support class for uniquifying instances of frame_region. */ struct key_t { - key_t (const frame_region *calling_frame, function *fun) - : m_calling_frame (calling_frame), m_fun (fun) + key_t (const frame_region *calling_frame, const function &fun) + : m_calling_frame (calling_frame), m_fun (&fun) { /* calling_frame can be NULL. */ - gcc_assert (fun); } hashval_t hash () const @@ -322,7 +321,8 @@ public: bool operator== (const key_t &other) const { - return (m_calling_frame == other.m_calling_frame && m_fun == other.m_fun); + return (m_calling_frame == other.m_calling_frame + && m_fun == other.m_fun); } void mark_deleted () { m_fun = reinterpret_cast (1); } @@ -334,12 +334,12 @@ public: bool is_empty () const { return m_fun == NULL; } const frame_region *m_calling_frame; - function *m_fun; + const function *m_fun; }; frame_region (symbol::id_t id, const region *parent, const frame_region *calling_frame, - function *fun, int index) + const function &fun, int index) : space_region (id, parent), m_calling_frame (calling_frame), m_fun (fun), m_index (index) {} @@ -356,8 +356,8 @@ public: /* Accessors. */ const frame_region *get_calling_frame () const { return m_calling_frame; } - function *get_function () const { return m_fun; } - tree get_fndecl () const { return get_function ()->decl; } + const function &get_function () const { return m_fun; } + tree get_fndecl () const { return get_function ().decl; } int get_index () const { return m_index; } int get_stack_depth () const { return m_index + 1; } @@ -373,7 +373,7 @@ public: private: const frame_region *m_calling_frame; - function *m_fun; + const function &m_fun; int m_index; /* The regions for the decls within this frame are managed by this diff --git a/gcc/analyzer/sm-signal.cc b/gcc/analyzer/sm-signal.cc index 5be857a..93269ca 100644 --- a/gcc/analyzer/sm-signal.cc +++ b/gcc/analyzer/sm-signal.cc @@ -146,7 +146,8 @@ public: if (change.is_global_p () && change.m_new_state == m_sm.m_in_signal_handler) { - function *handler = change.m_event.get_dest_function (); + const function *handler = change.m_event.get_dest_function (); + gcc_assert (handler); return change.formatted_print ("registering %qD as signal handler", handler->decl); } @@ -193,7 +194,7 @@ signal_state_machine::signal_state_machine (logger *logger) static void update_model_for_signal_handler (region_model *model, - function *handler_fun) + const function &handler_fun) { gcc_assert (model); /* Purge all state within MODEL. */ @@ -222,7 +223,9 @@ public: region_model_context *) const final override { gcc_assert (eedge); - update_model_for_signal_handler (model, eedge->m_dest->get_function ()); + gcc_assert (eedge->m_dest->get_function ()); + update_model_for_signal_handler (model, + *eedge->m_dest->get_function ()); return true; } @@ -263,11 +266,11 @@ public: program_point entering_handler = program_point::from_function_entry (*ext_state.get_model_manager (), eg->get_supergraph (), - handler_fun); + *handler_fun); program_state state_entering_handler (ext_state); update_model_for_signal_handler (state_entering_handler.m_region_model, - handler_fun); + *handler_fun); state_entering_handler.m_checker_states[sm_idx]->set_global_state (m_sm.m_in_signal_handler); diff --git a/gcc/analyzer/state-purge.cc b/gcc/analyzer/state-purge.cc index 93959fb..324b548 100644 --- a/gcc/analyzer/state-purge.cc +++ b/gcc/analyzer/state-purge.cc @@ -89,7 +89,7 @@ class gimple_op_visitor : public log_user public: gimple_op_visitor (state_purge_map *map, const function_point &point, - function *fun) + const function &fun) : log_user (map->get_logger ()), m_map (map), m_point (point), @@ -172,7 +172,7 @@ private: state_purge_map *m_map; const function_point &m_point; - function *m_fun; + const function &m_fun; }; static bool @@ -214,6 +214,7 @@ state_purge_map::state_purge_map (const supergraph &sg, FOR_EACH_FUNCTION_WITH_GIMPLE_BODY (node) { function *fun = node->get_fun (); + gcc_assert (fun); if (logger) log ("function: %s", function_name (fun)); tree name; @@ -225,7 +226,7 @@ state_purge_map::state_purge_map (const supergraph &sg, if (TREE_CODE (var) == VAR_DECL) if (VAR_DECL_IS_VIRTUAL_OPERAND (var)) continue; - m_ssa_map.put (name, new state_purge_per_ssa_name (*this, name, fun)); + m_ssa_map.put (name, new state_purge_per_ssa_name (*this, name, *fun)); } } @@ -241,8 +242,10 @@ state_purge_map::state_purge_map (const supergraph &sg, unsigned i; FOR_EACH_VEC_ELT (snode->m_stmts, i, stmt) { + function *fun = snode->get_function (); + gcc_assert (fun); function_point point (function_point::before_stmt (snode, i)); - gimple_op_visitor v (this, point, snode->get_function ()); + gimple_op_visitor v (this, point, *fun); walk_stmt_load_store_addr_ops (stmt, &v, my_load_cb, my_store_cb, my_addr_cb); } @@ -272,7 +275,7 @@ state_purge_map::~state_purge_map () if necessary. */ state_purge_per_decl & -state_purge_map::get_or_create_data_for_decl (function *fun, tree decl) +state_purge_map::get_or_create_data_for_decl (const function &fun, tree decl) { if (state_purge_per_decl **slot = const_cast (m_decl_map).get (decl)) @@ -295,14 +298,14 @@ state_purge_map::get_or_create_data_for_decl (function *fun, tree decl) state_purge_per_ssa_name::state_purge_per_ssa_name (const state_purge_map &map, tree name, - function *fun) + const function &fun) : state_purge_per_tree (fun), m_points_needing_name (), m_name (name) { LOG_FUNC (map.get_logger ()); if (map.get_logger ()) { - map.log ("SSA name: %qE within %qD", name, fun->decl); + map.log ("SSA name: %qE within %qD", name, fun.decl); /* Show def stmt. */ const gimple *def_stmt = SSA_NAME_DEF_STMT (name); @@ -410,7 +413,7 @@ state_purge_per_ssa_name::state_purge_per_ssa_name (const state_purge_map &map, if (map.get_logger ()) { - map.log ("%qE in %qD is needed to process:", name, fun->decl); + map.log ("%qE in %qD is needed to process:", name, fun.decl); /* Log m_points_needing_name, sorting it to avoid churn when comparing dumps. */ auto_vec points; @@ -472,7 +475,7 @@ state_purge_per_ssa_name::add_to_worklist (const function_point &point, logger->end_log_line (); } - gcc_assert (point.get_function () == get_function ()); + gcc_assert (point.get_function () == &get_function ()); if (point.get_from_edge ()) gcc_assert (point.get_from_edge ()->get_kind () == SUPEREDGE_CFG_EDGE); @@ -678,7 +681,7 @@ state_purge_per_ssa_name::process_point (const function_point &point, state_purge_per_decl::state_purge_per_decl (const state_purge_map &map, tree decl, - function *fun) + const function &fun) : state_purge_per_tree (fun), m_decl (decl) { @@ -794,7 +797,7 @@ state_purge_per_decl::add_to_worklist (const function_point &point, logger->end_log_line (); } - gcc_assert (point.get_function () == get_function ()); + gcc_assert (point.get_function () == &get_function ()); if (point.get_from_edge ()) gcc_assert (point.get_from_edge ()->get_kind () == SUPEREDGE_CFG_EDGE); @@ -1192,7 +1195,7 @@ state_purge_annotator::print_needed (graphviz_out *gv, { tree name = (*iter).first; state_purge_per_ssa_name *per_name_data = (*iter).second; - if (per_name_data->get_function () == point.get_function ()) + if (&per_name_data->get_function () == point.get_function ()) { if (per_name_data->needed_at_point_p (point)) needed.safe_push (name); @@ -1206,7 +1209,7 @@ state_purge_annotator::print_needed (graphviz_out *gv, { tree decl = (*iter).first; state_purge_per_decl *per_decl_data = (*iter).second; - if (per_decl_data->get_function () == point.get_function ()) + if (&per_decl_data->get_function () == point.get_function ()) { if (per_decl_data->needed_at_point_p (point)) needed.safe_push (decl); diff --git a/gcc/analyzer/state-purge.h b/gcc/analyzer/state-purge.h index c6d64b4..4eb2ba0 100644 --- a/gcc/analyzer/state-purge.h +++ b/gcc/analyzer/state-purge.h @@ -112,7 +112,8 @@ public: return NULL; } - state_purge_per_decl &get_or_create_data_for_decl (function *fun, tree decl); + state_purge_per_decl & + get_or_create_data_for_decl (const function &fun, tree decl); const supergraph &get_sg () const { return m_sg; } @@ -135,19 +136,19 @@ private: class state_purge_per_tree { public: - function *get_function () const { return m_fun; } - tree get_fndecl () const { return m_fun->decl; } + const function &get_function () const { return m_fun; } + tree get_fndecl () const { return m_fun.decl; } protected: typedef hash_set point_set_t; - state_purge_per_tree (function *fun) + state_purge_per_tree (const function &fun) : m_fun (fun) { } private: - function *m_fun; + const function &m_fun; }; /* The part of a state_purge_map relating to a specific SSA name. @@ -162,7 +163,7 @@ class state_purge_per_ssa_name : public state_purge_per_tree public: state_purge_per_ssa_name (const state_purge_map &map, tree name, - function *fun); + const function &fun); bool needed_at_point_p (const function_point &point) const; @@ -194,7 +195,7 @@ class state_purge_per_decl : public state_purge_per_tree public: state_purge_per_decl (const state_purge_map &map, tree decl, - function *fun); + const function &fun); bool needed_at_point_p (const function_point &point) const; diff --git a/gcc/analyzer/supergraph.cc b/gcc/analyzer/supergraph.cc index b822752..adbf90f 100644 --- a/gcc/analyzer/supergraph.cc +++ b/gcc/analyzer/supergraph.cc @@ -364,6 +364,7 @@ supergraph::dump_dot_to_pp (pretty_printer *pp, FOR_EACH_FUNCTION_WITH_GIMPLE_BODY (node) { function *fun = node->get_fun (); + gcc_assert (fun); const char *funcname = function_name (fun); gv.println ("subgraph \"cluster_%s\" {", funcname); @@ -409,9 +410,9 @@ supergraph::dump_dot_to_pp (pretty_printer *pp, /* Add an invisible edge from ENTRY to EXIT, to improve the graph layout. */ pp_string (pp, "\t"); - get_node_for_function_entry (fun)->dump_dot_id (pp); + get_node_for_function_entry (*fun)->dump_dot_id (pp); pp_string (pp, ":s -> "); - get_node_for_function_exit (fun)->dump_dot_id (pp); + get_node_for_function_exit (*fun)->dump_dot_id (pp); pp_string (pp, ":n [style=\"invis\",constraint=true];\n"); /* Terminate per-function "subgraph" */ diff --git a/gcc/analyzer/supergraph.h b/gcc/analyzer/supergraph.h index 2677aca..86f918b 100644 --- a/gcc/analyzer/supergraph.h +++ b/gcc/analyzer/supergraph.h @@ -111,14 +111,14 @@ public: supergraph (logger *logger); ~supergraph (); - supernode *get_node_for_function_entry (function *fun) const + supernode *get_node_for_function_entry (const function &fun) const { - return get_node_for_block (ENTRY_BLOCK_PTR_FOR_FN (fun)); + return get_node_for_block (ENTRY_BLOCK_PTR_FOR_FN (&fun)); } - supernode *get_node_for_function_exit (function *fun) const + supernode *get_node_for_function_exit (const function &fun) const { - return get_node_for_block (EXIT_BLOCK_PTR_FOR_FN (fun)); + return get_node_for_block (EXIT_BLOCK_PTR_FOR_FN (&fun)); } supernode *get_node_for_block (basic_block bb) const diff --git a/gcc/function.cc b/gcc/function.cc index 5ffd438..9488181 100644 --- a/gcc/function.cc +++ b/gcc/function.cc @@ -6391,7 +6391,7 @@ fndecl_name (tree fndecl) /* Returns the name of function FN. */ const char * -function_name (struct function *fn) +function_name (const function *fn) { tree fndecl = (fn == NULL) ? NULL : fn->decl; return fndecl_name (fndecl); diff --git a/gcc/function.h b/gcc/function.h index 2d775b8..19e15bd 100644 --- a/gcc/function.h +++ b/gcc/function.h @@ -730,7 +730,7 @@ extern poly_int64 get_stack_dynamic_offset (); /* Returns the name of the current function. */ extern const char *fndecl_name (tree); -extern const char *function_name (struct function *); +extern const char *function_name (const function *); extern const char *current_function_name (void); extern void used_types_insert (tree); diff --git a/gcc/testsuite/c-c++-common/analyzer/call-summaries-pr114159.c b/gcc/testsuite/c-c++-common/analyzer/call-summaries-pr114159.c new file mode 100644 index 0000000..19b545a --- /dev/null +++ b/gcc/testsuite/c-c++-common/analyzer/call-summaries-pr114159.c @@ -0,0 +1,20 @@ +/* Verify we don't ICE on this case with these options. */ + +/* { dg-additional-options "-fanalyzer-call-summaries --param=analyzer-max-svalue-depth=0 -Wno-analyzer-symbol-too-complex" } */ + +int foo_i; +void bar() {} +void foo() { + if (foo_i) + bar(); + else + goto f1; + bar(); +f1: + bar(); +} +int main() { + foo(); + foo(); + return 0; +} -- cgit v1.1 From b05f474c8f7768dad50a99a2d676660ee4db09c6 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Fri, 1 Mar 2024 00:16:41 +0000 Subject: Daily bump. --- gcc/ChangeLog | 63 +++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 87 +++++++++++++++++++++++++++++++++++++++++++++++++ gcc/cp/ChangeLog | 28 ++++++++++++++++ gcc/fortran/ChangeLog | 31 ++++++++++++++++++ gcc/testsuite/ChangeLog | 55 +++++++++++++++++++++++++++++++ 6 files changed, 265 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 10fa428..fe6bb91 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,66 @@ +2024-02-29 David Malcolm + + PR analyzer/114159 + * function.cc (function_name): Make param const. + * function.h (function_name): Likewise. + +2024-02-29 Georg-Johann Lay + + PR target/114100 + * doc/invoke.texi (AVR Options) <-mfuse-add>: Document. + * config/avr/avr.opt (-mfuse-add=): New target option. + * common/config/avr/avr-common.cc (avr_option_optimization_table) + [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1. + [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2. + * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass. + * config/avr/avr-protos.h (avr_split_tiny_move) + (make_avr_pass_fuse_add): New protos. + * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses + avr_split_tiny_move to split indirect memory accesses. + (gen_move_clobbercc): New define_expand helper. + * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data. + (avr_pass_fuse_add): New class from rtl_opt_pass. + (make_avr_pass_fuse_add, avr_split_tiny_move): New functions. + (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions. + (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets + of PLUS addressing for AVR_TINY. + (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X. + (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y. + (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS. + +2024-02-29 Georg-Johann Lay + + PR target/114132 + * config/avr/avr.h (CUMULATIVE_ARGS) : New field. + * config/avr/avr.cc (avr_init_cumulative_args): Initialize it. + (avr_function_arg): Set it. + (avr_frame_pointer_required_p): Use it instead of .nregs. + +2024-02-29 Andrew Pinski + + PR target/108174 + * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make + static and mark with GTY. + +2024-02-29 Xi Ruoyao + + * config/loongarch/loongarch.md + (loongarch__w__w_extended): New define_insn. + +2024-02-29 Xi Ruoyao + + * config/loongarch/loongarch.md (CRC): New define_int_iterator. + (crc): New define_int_attr. + (loongarch_crc_w__w, loongarch_crcc_w__w): Unify + into ... + (loongarch__w__w): ... here. + +2024-02-29 Kito Cheng + + PR target/114130 + * config/riscv/sync.md (atomic_compare_and_swap): Sign + extend the expected value if needed. + 2024-02-28 Cupertino Miranda * config.gcc (target_gtfiles): Change coreout to btfext-out. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 4c39afe..88d4f65 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240229 +20240301 diff --git a/gcc/analyzer/ChangeLog b/gcc/analyzer/ChangeLog index 98fa45c..49824f0 100644 --- a/gcc/analyzer/ChangeLog +++ b/gcc/analyzer/ChangeLog @@ -1,3 +1,90 @@ +2024-02-29 David Malcolm + + PR analyzer/114159 + * analyzer.cc: Include "tree-dfa.h". + (get_ssa_default_def): New decl. + * analyzer.h (get_ssa_default_def): New. + * call-info.cc (call_info::call_info): New ctor taking an explicit + called_fn. + * call-info.h (call_info::call_info): Likewise. + * call-summary.cc (call_summary_replay::call_summary_replay): + Convert param from function * to const function &. + * call-summary.h (call_summary_replay::call_summary_replay): + Likewise. + * checker-event.h (state_change_event::get_dest_function): + Constify return value. + * engine.cc (point_and_state::validate): Update for conversion to + const function &. + (exploded_node::on_stmt): Likewise. + (call_summary_edge_info::call_summary_edge_info): Likewise. + Pass in called_fn to call_info ctor. + (exploded_node::replay_call_summaries): Update for conversion to + const function &. Convert per_function_data from * to &. + (exploded_node::replay_call_summary): Update for conversion to + const function &. + (exploded_graph::add_function_entry): Likewise. + (toplevel_function_p): Likewise. + (add_tainted_args_callback): Likewise. + (exploded_graph::build_initial_worklist): Likewise. + (exploded_graph::maybe_create_dynamic_call): Likewise. + (maybe_update_for_edge): Likewise. + (exploded_graph::on_escaped_function): Likewise. + * exploded-graph.h (exploded_node::replay_call_summaries): + Likewise. + (exploded_node::replay_call_summary): Likewise. + (exploded_graph::add_function_entry): Likewise. + * program-point.cc (function_point::from_function_entry): + Likewise. + (program_point::from_function_entry): Likewise. + * program-point.h (function_point::from_function_entry): Likewise. + (program_point::from_function_entry): Likewise. + * program-state.cc (program_state::push_frame): Likewise. + (program_state::get_current_function): Constify return type. + * program-state.h (program_state::push_frame): Update for + conversion to const function &. + (program_state::get_current_function): Likewise. + * region-model-manager.cc + (region_model_manager::get_frame_region): Likewise. + * region-model-manager.h + (region_model_manager::get_frame_region): Likewise. + * region-model.cc (region_model::called_from_main_p): Likewise. + (region_model::update_for_gcall): Likewise. + (region_model::push_frame): Likewise. + (region_model::get_current_function): Constify return type. + (region_model::pop_frame): Update for conversion to + const function &. + (selftest::test_stack_frames): Likewise. + (selftest::test_get_representative_path_var): Likewise. + (selftest::test_state_merging): Likewise. + (selftest::test_alloca): Likewise. + * region-model.h (region_model::push_frame): Likewise. + (region_model::get_current_function): Likewise. + * region.cc (frame_region::dump_to_pp): Likewise. + (frame_region::get_region_for_local): Likewise. + * region.h (class frame_region): Likewise. + * sm-signal.cc (signal_unsafe_call::describe_state_change): + Likewise. + (update_model_for_signal_handler): Likewise. + (signal_delivery_edge_info_t::update_model): Likewise. + (register_signal_handler::impl_transition): Likewise. + * state-purge.cc (class gimple_op_visitor): Likewise. + (state_purge_map::state_purge_map): Likewise. + (state_purge_map::get_or_create_data_for_decl): Likewise. + (state_purge_per_ssa_name::state_purge_per_ssa_name): Likewise. + (state_purge_per_ssa_name::add_to_worklist): Likewise. + (state_purge_per_ssa_name::process_point): Likewise. + (state_purge_per_decl::add_to_worklist): Likewise. + (state_purge_annotator::print_needed): Likewise. + * state-purge.h + (state_purge_map::get_or_create_data_for_decl): Likewise. + (class state_purge_per_tree): Likewise. + (class state_purge_per_ssa_name): Likewise. + (class state_purge_per_decl): Likewise. + * supergraph.cc (supergraph::dump_dot_to_pp): Likewise. + * supergraph.h + (supergraph::get_node_for_function_entry): Likewise. + (supergraph::get_node_for_function_exit): Likewise. + 2024-02-27 David Malcolm PR analyzer/110483 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 1ff86c8..4339b52 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,31 @@ +2024-02-29 Marek Polacek + + PR c++/113987 + * call.cc (conv_binds_to_reference_parm_p): New. + * cp-tree.h (conv_binds_to_reference_parm_p): Declare. + * init.cc (find_uninit_fields_r): Call it. + +2024-02-29 Nathaniel Shead + + PR c++/111710 + * cp-tree.h (DECL_MODULE_KEYED_DECLS_P): Remove tree checking. + (struct lang_decl_base): Update comments and fix whitespace. + * module.cc (trees_out::lang_decl_bools): Always write + module_keyed_decls_p flag... + (trees_in::lang_decl_bools): ...and always read it. + (trees_out::decl_value): Handle all kinds of keyed decls. + (trees_in::decl_value): Likewise. + (trees_in::tree_value): Deduplicate LAMBDA_EXPRs. + (maybe_key_decl): Also support lambdas attached to fields, + parameters, and types. Key lambdas attached to fields to their + class. + (trees_out::get_merge_kind): Likewise. + (trees_out::key_mergeable): Likewise. + (trees_in::key_mergeable): Support keyed decls in a TYPE_DECL + container. + * parser.cc (cp_parser_class_head): Start a lambda scope when + parsing base classes. + 2024-02-28 Jakub Jelinek Patrick Palka diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 644d9ec..f6b6830 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,34 @@ +2024-02-29 Alexander Westbrooks + + PR fortran/82943 + PR fortran/86148 + PR fortran/86268 + * decl.cc (gfc_get_pdt_instance): Set the PDT instance field + 'f2k_derived', if not set already, to point to the given + PDT template 'f2k_derived' namespace in order to give the + PDT instance referential access to the typebound procedures + of the template. + * gfortran.h (gfc_pdt_is_instance_of): Add prototype. + * resolve.cc (resolve_typebound_procedure): If the derived type + does not have the attribute 'pdt_template' set, compare the + dummy argument to the 'resolve_bindings_derived' type like usual. + If the derived type is a 'pdt_template', then check if the + dummy argument is an instance of the PDT template. If the derived + type is a PDT template, and the dummy argument is an instance of + that template, but the dummy argument 'param_list' is not + SPEC_ASSUMED, check if there are any LEN parameters in the + dummy argument. If there are no LEN parameters, then this implies + that there are only KIND parameters in the dummy argument. + If there are LEN parameters, this would be an error, for all + LEN parameters for the dummy argument MUST be assumed for + typebound procedures of PDTs. + (resolve_pdt): Add a check for ALLOCATABLE and POINTER attributes for + SPEC_DEFERRED parameters of PDT class symbols. ALLOCATABLE and + POINTER attributes for a PDT class symbol are stored in the + 'class_pointer' and 'allocatable' attributes of the '_data' + component respectively. + * symbol.cc (gfc_pdt_is_instance_of): New function. + 2024-02-26 Harald Anlauf PR fortran/114012 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1cb1870..deb15e9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,58 @@ +2024-02-29 David Malcolm + + PR analyzer/114159 + * c-c++-common/analyzer/call-summaries-pr114159.c: New test. + +2024-02-29 Georg-Johann Lay + + PR target/114132 + * gcc.target/avr/pr114132-1.c: New test. + * gcc.target/avr/torture/pr114132-2.c: New test. + +2024-02-29 Marek Polacek + + PR c++/113987 + * g++.dg/warn/Wuninitialized-15.C: Turn dg-warning into dg-bogus. + * g++.dg/warn/Wuninitialized-34.C: New test. + +2024-02-29 Gaius Mulley + + PR modula2/102344 + * gm2/pim/pass/TestLong4.mod: Rewrite. + * gm2/cpp/pass/testlong4.mod: New test. + +2024-02-29 Andrew Pinski + + PR target/108174 + * gcc.target/aarch64/acle/memtag_4.c: New test. + +2024-02-29 Xi Ruoyao + + * gcc.target/loongarch/crc-sext.c: New test; + +2024-02-29 Nathaniel Shead + + PR c++/111710 + * g++.dg/modules/lambda-7.h: New test. + * g++.dg/modules/lambda-7_a.H: New test. + * g++.dg/modules/lambda-7_b.C: New test. + * g++.dg/modules/lambda-7_c.C: New test. + +2024-02-29 Kito Cheng + + * gcc.target/riscv/pr114130.c: New. + +2024-02-29 Alexander Westbrooks + + PR fortran/82943 + PR fortran/86148 + PR fortran/86268 + * gfortran.dg/pdt_4.f03: Update modified error message. + * gfortran.dg/pdt_34.f03: New test. + * gfortran.dg/pdt_35.f03: New test. + * gfortran.dg/pdt_36.f03: New test. + * gfortran.dg/pdt_37.f03: New test. + 2024-02-28 Jakub Jelinek Patrick Palka -- cgit v1.1 From d3d0fcb652748191714e4c0b2541e977a7fc7bd7 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 1 Mar 2024 11:04:51 +0100 Subject: bitint: Handle VCE from large/huge _BitInt SSA_NAME from load [PR114156] When adding checks in which case not to merge a VIEW_CONVERT_EXPR from large/huge _BitInt to vector/complex etc., I missed the case of loads. Those are handled differently later. Anyway, I think the load case is something we can handle just fine, so the following patch does that instead of preventing the merging gimple_lower_bitint; we'd then copy from memory to memory and and do the vce only on the second one, it is just better to vce the first one. 2024-03-01 Jakub Jelinek PR middle-end/114156 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow rhs1 of a VCE to have no underlying variable if it is a load and handle that case. * gcc.dg/bitint-96.c: New test. --- gcc/gimple-lower-bitint.cc | 16 ++++++++++++++++ gcc/testsuite/gcc.dg/bitint-96.c | 17 +++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/bitint-96.c (limited to 'gcc') diff --git a/gcc/gimple-lower-bitint.cc b/gcc/gimple-lower-bitint.cc index d7bf029..15a2712 100644 --- a/gcc/gimple-lower-bitint.cc +++ b/gcc/gimple-lower-bitint.cc @@ -5329,6 +5329,22 @@ bitint_large_huge::lower_stmt (gimple *stmt) gimple_assign_set_rhs1 (stmt, rhs1); gimple_assign_set_rhs_code (stmt, SSA_NAME); } + else if (m_names == NULL + || !bitmap_bit_p (m_names, SSA_NAME_VERSION (rhs1))) + { + gimple *g = SSA_NAME_DEF_STMT (rhs1); + gcc_assert (gimple_assign_load_p (g)); + tree mem = gimple_assign_rhs1 (g); + tree ltype = TREE_TYPE (lhs); + addr_space_t as = TYPE_ADDR_SPACE (TREE_TYPE (mem)); + if (as != TYPE_ADDR_SPACE (ltype)) + ltype + = build_qualified_type (ltype, + TYPE_QUALS (ltype) + | ENCODE_QUAL_ADDR_SPACE (as)); + rhs1 = build1 (VIEW_CONVERT_EXPR, ltype, mem); + gimple_assign_set_rhs1 (stmt, rhs1); + } else { int part = var_to_partition (m_map, rhs1); diff --git a/gcc/testsuite/gcc.dg/bitint-96.c b/gcc/testsuite/gcc.dg/bitint-96.c new file mode 100644 index 0000000..237eb47 --- /dev/null +++ b/gcc/testsuite/gcc.dg/bitint-96.c @@ -0,0 +1,17 @@ +/* PR middle-end/114156 */ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-msse2" { target i?86-*-* x86_64-*-* } } */ + +#if __BITINT_MAXWIDTH__ >= 128 +_BitInt(128) a, b; +#else +int a, b; +#endif + +void +foo (void) +{ + int u = b; + __builtin_memmove (&a, &b, sizeof (a)); +} -- cgit v1.1 From c6f5f773323ab689a665bc208c3b221db42fe624 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 1 Mar 2024 11:07:36 +0100 Subject: function: Fix another TYPE_NO_NAMED_ARGS_STDARG_P spot When looking at PR114175 (although that bug seems to be now a riscv backend bug), I've noticed that for the TYPE_NO_NAMED_ARGS_STDARG_P functions which return value through hidden reference, like #include struct S { char a[64]; }; int n; struct S foo (...) { struct S s = {}; va_list ap; va_start (ap); for (int i = 0; i < n; ++i) if ((i & 1)) s.a[0] += va_arg (ap, double); else s.a[0] += va_arg (ap, int); va_end (ap); return s; } we were incorrectly calling assign_parms_setup_varargs twice, once at the start of the function and once in if (cfun->stdarg && !DECL_CHAIN (parm)) assign_parms_setup_varargs (&all, &data, false); where parm is the last and only "named" parameter. The first call, guarded with TYPE_NO_NAMED_ARGS_STDARG_P, was added in r13-3549 and is needed for int bar (...) etc. functions using va_start/va_arg/va_end, otherwise the FOR_EACH_VEC_ELT (fnargs, i, parm) in which the other call is will not iterate at all. But we shouldn't be doing that if we have the hidden return pointer. With the following patch on the above testcase with -O0 -std=c23 the assembly difference is: pushq %rbp .cfi_def_cfa_offset 16 .cfi_offset 6, -16 movq %rsp, %rbp .cfi_def_cfa_register 6 pushq %rbx subq $192, %rsp .cfi_offset 3, -24 - movq %rdi, -192(%rbp) - movq %rsi, -184(%rbp) - movq %rdx, -176(%rbp) - movq %rcx, -168(%rbp) - movq %r8, -160(%rbp) - movq %r9, -152(%rbp) - testb %al, %al - je .L2 - movaps %xmm0, -144(%rbp) - movaps %xmm1, -128(%rbp) - movaps %xmm2, -112(%rbp) - movaps %xmm3, -96(%rbp) - movaps %xmm4, -80(%rbp) - movaps %xmm5, -64(%rbp) - movaps %xmm6, -48(%rbp) - movaps %xmm7, -32(%rbp) -.L2: movq %rdi, -312(%rbp) movq %rdi, -192(%rbp) movq %rsi, -184(%rbp) movq %rdx, -176(%rbp) movq %rcx, -168(%rbp) movq %r8, -160(%rbp) movq %r9, -152(%rbp) testb %al, %al - je .L13 + je .L12 movaps %xmm0, -144(%rbp) movaps %xmm1, -128(%rbp) movaps %xmm2, -112(%rbp) movaps %xmm3, -96(%rbp) movaps %xmm4, -80(%rbp) movaps %xmm5, -64(%rbp) movaps %xmm6, -48(%rbp) movaps %xmm7, -32(%rbp) -.L13: +.L12: plus some renumbering of labels later on which clearly shows that because of this bug, we were saving all the registers twice rather then once. With -O2 -std=c23 some of it is DCEd, but we still get subq $160, %rsp .cfi_def_cfa_offset 168 - testb %al, %al - je .L2 - movaps %xmm0, 24(%rsp) - movaps %xmm1, 40(%rsp) - movaps %xmm2, 56(%rsp) - movaps %xmm3, 72(%rsp) - movaps %xmm4, 88(%rsp) - movaps %xmm5, 104(%rsp) - movaps %xmm6, 120(%rsp) - movaps %xmm7, 136(%rsp) -.L2: movq %rdi, -24(%rsp) movq %rsi, -16(%rsp) movq %rdx, -8(%rsp) movq %rcx, (%rsp) movq %r8, 8(%rsp) movq %r9, 16(%rsp) testb %al, %al - je .L13 + je .L12 movaps %xmm0, 24(%rsp) movaps %xmm1, 40(%rsp) movaps %xmm2, 56(%rsp) movaps %xmm3, 72(%rsp) movaps %xmm4, 88(%rsp) movaps %xmm5, 104(%rsp) movaps %xmm6, 120(%rsp) movaps %xmm7, 136(%rsp) -.L13: +.L12: difference, i.e. this time not all, but the floating point args were conditionally all saved twice. 2024-03-01 Jakub Jelinek * function.cc (assign_parms): Only call assign_parms_setup_varargs early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty. --- gcc/function.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/function.cc b/gcc/function.cc index 9488181..3cef6c1 100644 --- a/gcc/function.cc +++ b/gcc/function.cc @@ -3650,7 +3650,8 @@ assign_parms (tree fndecl) assign_parms_initialize_all (&all); fnargs = assign_parms_augmented_arg_list (&all); - if (TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (fndecl))) + if (TYPE_NO_NAMED_ARGS_STDARG_P (TREE_TYPE (fndecl)) + && fnargs.is_empty ()) { struct assign_parm_data_one data = {}; assign_parms_setup_varargs (&all, &data, false); -- cgit v1.1 From 0a01d1232ff0a8b094270fbf45c9fd0ea46df19f Mon Sep 17 00:00:00 2001 From: Pan Li Date: Fri, 23 Feb 2024 15:37:28 +0800 Subject: RISC-V: Introduce gcc option mrvv-vector-bits for RVV This patch would like to introduce one new gcc option for RVV. To appoint the bits size of one RVV vector register. Valid arguments to '-mrvv-vector-bits=' are: * scalable * zvl The scalable will pick up the zvl*b in the march as the minimal vlen. For example, the minimal vlen will be 512 when march=rv64gcv_zvl512b and mrvv-vector-bits=scalable. The zvl will pick up the zvl*b in the march as exactly vlen. For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024b and mrvv-vector-bits=zvl. The internal option --param=riscv-autovec-preference will be replaced by option -mrvv-vector-bits. Aka: * -mrvv-vector-bits=scalable indicates --param=riscv-autovec-preference=scalable * -mrvv-vector-bits=zvl indicates --param=riscv-autovec-preference=fixed-vlmax You can also take -fno-tree-vectorize for --param=riscv-autovec-preference=none. The internal option --param=riscv-autovec-preference is unavailable after this patch. Given below sample for more details: void test_rvv_vector_bits () { vint32m1_t x; asm volatile ("def %0": "=vr"(x)); asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); asm volatile ("use %0": : "vr"(x)); } With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128) csrr t0,vlenb sub sp,sp,t0 def v1 vs1r.v v1,0(sp) vl1re32.v v1,0(sp) use v1 csrr t0,vlenb add sp,sp,t0 jr ra With -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128) addi sp,sp,-16 def v1 vs1r.v v1,0(sp) vl1re32.v v1,0(sp) use v1 addi sp,sp,16 jr ra The below test are passed for this patch. * The riscv fully regression test. PR target/112817 gcc/ChangeLog: * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL. * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove. (enum rvv_vector_bits_enum): New enum for different RVV vector bits. * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update comments for option replacement. * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of riscv_autovec_preference to rvv_vector_bits. (vls_mode_valid_p): Ditto. (estimated_poly_value): Ditto. * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to vector chunks and honor new option mrvv-vector-bits. (riscv_override_options_internal): Update comments and rename the vector chunks. * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove internal option param=riscv-autovec-preference. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr111296.C: Replace param=riscv-autovec-preference to mrvv-vector-bits. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c: Ditto. * gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto. * gcc.target/riscv/rvv/autovec/align-1.c: Ditto. * gcc.target/riscv/rvv/autovec/align-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-immediate.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-1.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-2.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-3.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-4.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-5.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-6.c: Ditto. * gcc.target/riscv/rvv/autovec/bug-8.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c: * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/cond/pr111401.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Diito. * gcc.target/riscv/rvv/autovec/fold-min-poly.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Diito. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Diito. * gcc.target/riscv/rvv/autovec/madd-split2-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/live_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: Diito. * gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-10.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-11.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-12.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-13.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-14.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-15.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-17.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-18.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-19.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-6.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-7.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-8.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/post-ra-avl.c: Diito. * gcc.target/riscv/rvv/autovec/pr110950.c: Diito. * gcc.target/riscv/rvv/autovec/pr110964.c: Diito. * gcc.target/riscv/rvv/autovec/pr110989.c: Diito. * gcc.target/riscv/rvv/autovec/pr111232.c: Diito. * gcc.target/riscv/rvv/autovec/pr111295.c: Diito. * gcc.target/riscv/rvv/autovec/pr111313.c: Diito. * gcc.target/riscv/rvv/autovec/pr112326.c: Diito. * gcc.target/riscv/rvv/autovec/pr112552.c: Diito. * gcc.target/riscv/rvv/autovec/pr112554.c: Diito. * gcc.target/riscv/rvv/autovec/pr112561.c: Diito. * gcc.target/riscv/rvv/autovec/pr112597-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr112599-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr112599-3.c: Diito. * gcc.target/riscv/rvv/autovec/pr112694-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr112854.c: Diito. * gcc.target/riscv/rvv/autovec/pr112872.c: Diito. * gcc.target/riscv/rvv/autovec/pr112999.c: Diito. * gcc.target/riscv/rvv/autovec/pr113393-1.c: Diito. * gcc.target/riscv/rvv/autovec/pr113393-2.c: Diito. * gcc.target/riscv/rvv/autovec/pr113393-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Diito. * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/scalable-1.c: Diito. * gcc.target/riscv/rvv/autovec/series-1.c: Diito. * gcc.target/riscv/rvv/autovec/series_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/slp-mask-1.c: Diito. * gcc.target/riscv/rvv/autovec/slp-mask-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c: Diito. * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Diito. * gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/v-1.c: Diito. * gcc.target/riscv/rvv/autovec/v-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: Diito. * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: Diito. * gcc.target/riscv/rvv/autovec/vls/pr110994.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Diito. * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Diito. * gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: Diito. * gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: Diito. * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: Diito. * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-8.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-9.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Diito. * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x-3.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: Diito. * gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Diito. * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Diito. * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Diito. * gcc.target/riscv/rvv/base/cpymem-1.c: Diito. * gcc.target/riscv/rvv/base/cpymem-2.c: Diito. * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Diito. * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Diito. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: Diito. * gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: Diito. * gcc.target/riscv/rvv/base/poly-selftest-1.c: Diito. * gcc.target/riscv/rvv/base/pr110119-1.c: Diito. * gcc.target/riscv/rvv/base/pr110119-2.c: Diito. * gcc.target/riscv/rvv/base/pr111720-0.c: Diito. * gcc.target/riscv/rvv/base/pr111720-1.c: Diito. * gcc.target/riscv/rvv/base/pr111720-10.c: Diito. * gcc.target/riscv/rvv/base/pr111720-2.c: Diito. * gcc.target/riscv/rvv/base/pr111720-3.c: Diito. * gcc.target/riscv/rvv/base/pr111720-4.c: Diito. * gcc.target/riscv/rvv/base/pr111720-5.c: Diito. * gcc.target/riscv/rvv/base/pr111720-6.c: Diito. * gcc.target/riscv/rvv/base/pr111720-7.c: Diito. * gcc.target/riscv/rvv/base/pr111720-8.c: Diito. * gcc.target/riscv/rvv/base/pr111720-9.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-1.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-2.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-3.c: Diito. * gcc.target/riscv/rvv/base/vf_avl-4.c: Diito. * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Diito. * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Diito. * gcc.target/riscv/rvv/rvv.exp: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-100.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-101.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-103.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-104.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-105.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-106.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-108.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-109.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-31.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-32.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-33.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-34.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-40.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-42.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-43.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-45.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-52.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-53.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-54.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-55.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-57.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-58.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-59.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-60.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-61.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-62.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-63.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-64.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-73.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-75.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-78.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-81.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-85.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-97.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-98.c: Diito. * gcc.target/riscv/rvv/vsetvl/avl_single-99.c: Diito. * gcc.target/riscv/rvv/vsetvl/dump-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/ffload-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr108270.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109399.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109547.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109615.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109743-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109748.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109773-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr109974.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111234.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111255.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111927.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr111947.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112092-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112092-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112713-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112713-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112776.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112813-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112929-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr113248.c: Diito. * gcc.target/riscv/rvv/vsetvl/pr113696.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: Diito. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: Diito. * gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Diito. * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-avlprop.cc | 2 +- gcc/config/riscv/riscv-opts.h | 15 ++++---- gcc/config/riscv/riscv-selftests.cc | 2 +- gcc/config/riscv/riscv-v.cc | 16 ++++---- gcc/config/riscv/riscv.cc | 21 +++++++---- gcc/config/riscv/riscv.opt | 31 +++++++-------- gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-6.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul4-8.c | 2 +- .../vect/costmodel/riscv/rvv/dynamic-lmul8-12.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c | 2 +- .../gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/align-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/align-2.c | 2 +- .../riscv/rvv/autovec/binop/copysign-run.c | 2 +- .../riscv/rvv/autovec/binop/copysign-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/copysign-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/copysign-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/fmax-1.c | 2 +- .../riscv/rvv/autovec/binop/fmax_run-1.c | 2 +- .../riscv/rvv/autovec/binop/fmax_zvfh-1.c | 2 +- .../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/fmin-1.c | 2 +- .../riscv/rvv/autovec/binop/fmin_run-1.c | 2 +- .../riscv/rvv/autovec/binop/fmin_zvfh-1.c | 2 +- .../riscv/rvv/autovec/binop/fmin_zvfh_run-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/mulh-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/mulh-2.c | 2 +- .../riscv/rvv/autovec/binop/mulh_run-1.c | 2 +- .../riscv/rvv/autovec/binop/mulh_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/narrow-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/narrow-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/narrow-3.c | 2 +- .../riscv/rvv/autovec/binop/narrow_run-1.c | 2 +- .../riscv/rvv/autovec/binop/narrow_run-2.c | 2 +- .../riscv/rvv/autovec/binop/narrow_run-3.c | 2 +- .../riscv/rvv/autovec/binop/shift-immediate.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/shift-run.c | 2 +- .../riscv/rvv/autovec/binop/shift-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/shift-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/shift-scalar-run.c | 2 +- .../riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c | 2 +- .../rvv/autovec/binop/shift-scalar-template.h | 2 +- .../riscv/rvv/autovec/binop/vadd-run-nofm.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vadd-run.c | 2 +- .../riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vadd-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vadd-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vadd-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vand-run.c | 2 +- .../riscv/rvv/autovec/binop/vand-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vand-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vcompress-avlprop-1.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-run-nofm.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vdiv-run.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vdiv-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmax-run.c | 2 +- .../riscv/rvv/autovec/binop/vmax-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmax-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmax-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmin-run.c | 2 +- .../riscv/rvv/autovec/binop/vmin-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmin-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmin-zvfh-run.c | 2 +- .../riscv/rvv/autovec/binop/vmul-run-nofm.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmul-run.c | 2 +- .../riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vmul-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vmul-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vmul-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vor-run.c | 2 +- .../riscv/rvv/autovec/binop/vor-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vor-rv64gcv.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vrem-run.c | 2 +- .../riscv/rvv/autovec/binop/vrem-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vrem-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vsub-run-nofm.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vsub-run.c | 2 +- .../riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vsub-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c | 2 +- .../riscv/rvv/autovec/binop/vsub-rv64gcv.c | 2 +- .../riscv/rvv/autovec/binop/vsub-zvfh-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vxor-run.c | 2 +- .../riscv/rvv/autovec/binop/vxor-rv32gcv.c | 2 +- .../riscv/rvv/autovec/binop/vxor-rv64gcv.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-10.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-11.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith-9.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-10.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-11.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_arith_run-9.c | 2 +- .../autovec/cond/cond_convert_float2float-rv32-1.c | 2 +- .../autovec/cond/cond_convert_float2float-rv32-2.c | 2 +- .../autovec/cond/cond_convert_float2float-rv64-1.c | 2 +- .../autovec/cond/cond_convert_float2float-rv64-2.c | 2 +- .../autovec/cond/cond_convert_float2float_run-1.c | 2 +- .../autovec/cond/cond_convert_float2float_run-2.c | 2 +- .../autovec/cond/cond_convert_float2int-rv32-1.c | 2 +- .../autovec/cond/cond_convert_float2int-rv32-2.c | 2 +- .../autovec/cond/cond_convert_float2int-rv64-1.c | 2 +- .../autovec/cond/cond_convert_float2int-rv64-2.c | 2 +- .../autovec/cond/cond_convert_float2int_run-1.c | 2 +- .../autovec/cond/cond_convert_float2int_run-2.c | 2 +- .../cond/cond_convert_float2int_zvfh-rv32-1.c | 2 +- .../cond/cond_convert_float2int_zvfh-rv32-2.c | 2 +- .../cond/cond_convert_float2int_zvfh-rv64-1.c | 2 +- .../cond/cond_convert_float2int_zvfh-rv64-2.c | 2 +- .../cond/cond_convert_float2int_zvfh_run-1.c | 2 +- .../cond/cond_convert_float2int_zvfh_run-2.c | 2 +- .../autovec/cond/cond_convert_int2float-rv32-1.c | 2 +- .../autovec/cond/cond_convert_int2float-rv32-2.c | 2 +- .../autovec/cond/cond_convert_int2float-rv64-1.c | 2 +- .../autovec/cond/cond_convert_int2float-rv64-2.c | 2 +- .../autovec/cond/cond_convert_int2float_run-1.c | 2 +- .../autovec/cond/cond_convert_int2float_run-2.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int-rv32-1.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int-rv32-2.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int-rv64-1.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int-rv64-2.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int_run-1.c | 2 +- .../rvv/autovec/cond/cond_convert_int2int_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_copysign-run.c | 2 +- .../riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c | 2 +- .../riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c | 2 +- .../rvv/autovec/cond/cond_copysign-zvfh-run.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fadd_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_fmul_run-5.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max-1.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max-2.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max-3.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max-4.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max-5.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max_run-1.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max_run-2.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max_run-3.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max_run-4.c | 2 +- .../rvv/autovec/cond/cond_logical_min_max_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_mulh-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_mulh-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_mulh_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_mulh_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_narrow_shift-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_narrow_shift-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_narrow_shift-3.c | 2 +- .../rvv/autovec/cond/cond_narrow_shift_run-1.c | 2 +- .../rvv/autovec/cond/cond_narrow_shift_run-2.c | 2 +- .../rvv/autovec/cond/cond_narrow_shift_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift-9.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_shift_run-9.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary-8.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-2.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-3.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-4.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-5.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-6.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-7.c | 2 +- .../riscv/rvv/autovec/cond/cond_unary_run-8.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-1.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-2.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-3.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-4.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-5.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-6.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-7.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-8.c | 2 +- .../rvv/autovec/cond/cond_widen_complicate-9.c | 2 +- .../riscv/rvv/autovec/cond/cond_widen_reduc-1.c | 2 +- .../riscv/rvv/autovec/cond/cond_widen_reduc-2.c | 2 +- .../rvv/autovec/cond/cond_widen_reduc_run-1.c | 2 +- .../rvv/autovec/cond/cond_widen_reduc_run-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/cond/pr111401.c | 2 +- .../autovec/conversions/vec-narrow-int64-float16.c | 2 +- .../autovec/conversions/vec-widen-float16-int64.c | 2 +- .../riscv/rvv/autovec/conversions/vfcvt-itof-run.c | 2 +- .../rvv/autovec/conversions/vfcvt-itof-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfcvt-itof-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfcvt-itof-zvfh-run.c | 2 +- .../riscv/rvv/autovec/conversions/vfcvt_rtz-run.c | 2 +- .../rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c | 2 +- .../rvv/autovec/conversions/vfncvt-ftoi-run.c | 2 +- .../rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c | 2 +- .../rvv/autovec/conversions/vfncvt-itof-run.c | 2 +- .../rvv/autovec/conversions/vfncvt-itof-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfncvt-itof-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfncvt-itof-zvfh-run.c | 2 +- .../riscv/rvv/autovec/conversions/vfncvt-run.c | 2 +- .../riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfncvt-zvfh-run.c | 2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-run.c | 2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c | 2 +- .../rvv/autovec/conversions/vfwcvt-itof-run.c | 2 +- .../rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c | 2 +- .../rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c | 2 +- .../riscv/rvv/autovec/conversions/vfwcvt-run.c | 2 +- .../riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c | 2 +- .../rvv/autovec/conversions/vfwcvt-zvfh-run.c | 2 +- .../riscv/rvv/autovec/conversions/vncvt-run.c | 2 +- .../riscv/rvv/autovec/conversions/vncvt-rv32gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vncvt-rv64gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vsext-run.c | 2 +- .../riscv/rvv/autovec/conversions/vsext-rv32gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vsext-rv64gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vzext-run.c | 2 +- .../riscv/rvv/autovec/conversions/vzext-rv32gcv.c | 2 +- .../riscv/rvv/autovec/conversions/vzext-rv64gcv.c | 2 +- .../gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/fold-min-poly.c | 2 +- .../rvv/autovec/gather-scatter/strided_load-1.c | 2 +- .../rvv/autovec/gather-scatter/strided_load-2.c | 2 +- .../rvv/autovec/gather-scatter/strided_store-1.c | 2 +- .../rvv/autovec/gather-scatter/strided_store-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/madd-split2-1.c | 2 +- .../riscv/rvv/autovec/partial/gimple_fold-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/live-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/partial/live-2.c | 2 +- .../riscv/rvv/autovec/partial/live_run-1.c | 2 +- .../riscv/rvv/autovec/partial/live_run-2.c | 2 +- .../riscv/rvv/autovec/partial/multiple_rgroup-1.c | 2 +- .../riscv/rvv/autovec/partial/multiple_rgroup-2.c | 2 +- .../riscv/rvv/autovec/partial/multiple_rgroup-3.c | 2 +- .../riscv/rvv/autovec/partial/multiple_rgroup-4.c | 2 +- .../rvv/autovec/partial/multiple_rgroup_run-1.c | 2 +- .../rvv/autovec/partial/multiple_rgroup_run-2.c | 2 +- .../rvv/autovec/partial/multiple_rgroup_run-3.c | 2 +- .../rvv/autovec/partial/multiple_rgroup_run-4.c | 2 +- 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.../gcc.target/riscv/rvv/autovec/vls/pr110994.c | 2 +- .../riscv/rvv/autovec/vmv-imm-fixed-rv32.c | 2 +- .../riscv/rvv/autovec/vmv-imm-fixed-rv64.c | 2 +- .../gcc.target/riscv/rvv/autovec/vmv-imm-run.c | 2 +- .../gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c | 2 +- .../gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c | 2 +- .../riscv/rvv/autovec/vreinterpet-fixed.c | 2 +- .../riscv/rvv/autovec/widen/vec-avg-run.c | 2 +- .../riscv/rvv/autovec/widen/vec-avg-rv32gcv.c | 2 +- .../riscv/rvv/autovec/widen/vec-avg-rv64gcv.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-10.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-11.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-12.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-4.c | 2 +- .../gcc.target/riscv/rvv/autovec/widen/widen-5.c | 2 +- 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+- .../riscv/rvv/autovec/widen/widen_reduc_run-1.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-1.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-10.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-11.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-12.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-2.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-3.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-4.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-5.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-6.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-7.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-8.c | 2 +- .../riscv/rvv/autovec/widen/widen_run-9.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-1.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-10.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-11.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-12.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-2.c | 2 +- .../riscv/rvv/autovec/widen/widen_run_zvfh-3.c | 2 +- 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2 +- .../riscv/rvv/autovec/zve32x_zvl2048b-1.c | 2 +- .../riscv/rvv/autovec/zve32x_zvl256b-1.c | 2 +- .../riscv/rvv/autovec/zve32x_zvl4096b-1.c | 2 +- .../riscv/rvv/autovec/zve32x_zvl512b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64d-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64d-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64d-3.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl1024b-1.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl128b-1.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl128b-2.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl2048b-1.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl256b-1.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl4096b-1.c | 2 +- .../riscv/rvv/autovec/zve64d_zvl512b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64f-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64f-2.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64f-3.c | 2 +- .../riscv/rvv/autovec/zve64f_zvl1024b-1.c | 2 +- .../riscv/rvv/autovec/zve64f_zvl128b-1.c | 2 +- .../riscv/rvv/autovec/zve64f_zvl128b-2.c | 2 +- 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.../gcc.target/riscv/rvv/base/cpymem-strategy-3.c | 4 +- .../gcc.target/riscv/rvv/base/cpymem-strategy-4.c | 4 +- .../riscv/rvv/base/float-point-dynamic-frm-77.c | 2 +- .../riscv/rvv/base/float-point-frm-autovec-1.c | 2 +- .../riscv/rvv/base/float-point-frm-autovec-2.c | 2 +- .../riscv/rvv/base/float-point-frm-autovec-3.c | 2 +- .../riscv/rvv/base/float-point-frm-autovec-4.c | 2 +- .../gcc.target/riscv/rvv/base/poly-selftest-1.c | 2 +- .../gcc.target/riscv/rvv/base/pr110119-1.c | 2 +- .../gcc.target/riscv/rvv/base/pr110119-2.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-0.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-1.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-10.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-2.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-3.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-4.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-5.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-6.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-7.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-8.c | 2 +- .../gcc.target/riscv/rvv/base/pr111720-9.c | 2 +- .../gcc.target/riscv/rvv/base/rvv-vector-bits-1.c | 7 ++++ .../gcc.target/riscv/rvv/base/rvv-vector-bits-2.c | 7 ++++ .../gcc.target/riscv/rvv/base/rvv-vector-bits-3.c | 9 +++++ .../gcc.target/riscv/rvv/base/rvv-vector-bits-4.c | 9 +++++ .../gcc.target/riscv/rvv/base/rvv-vector-bits-5.c | 17 +++++++++ .../gcc.target/riscv/rvv/base/rvv-vector-bits-6.c | 17 +++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c | 2 +- .../riscv/rvv/base/zvl-unimplemented-1.c | 2 +- .../riscv/rvv/base/zvl-unimplemented-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 44 +++++++++++----------- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_prop-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_prop-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-10.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-100.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-101.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-102.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-103.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-104.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-105.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-106.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-107.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-108.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-109.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-11.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-12.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-13.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-14.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-15.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-16.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-17.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-18.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-19.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-20.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-21.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-22.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-23.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-24.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-25.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-26.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-27.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-28.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-29.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-30.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-31.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-32.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-33.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_single-34.c | 2 +- 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.../gcc.target/riscv/rvv/vsetvl/ffload-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/ffload-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/ffload-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/ffload-5.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/ffload-6.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/ffload-7.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-1.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-10.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-11.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-12.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-13.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-14.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-15.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-16.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-17.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-2.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-3.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-4.c | 2 +- .../riscv/rvv/vsetvl/imm_loop_invariant-5.c | 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.../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-19.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-20.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-21.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-22.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-24.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-4.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-5.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-6.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-7.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-8.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-9.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl_int.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c | 2 +- 1351 files changed, 1482 insertions(+), 1413 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c (limited to 'gcc') diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc index 893b839..4ae15f2 100644 --- a/gcc/config/riscv/riscv-avlprop.cc +++ b/gcc/config/riscv/riscv-avlprop.cc @@ -506,7 +506,7 @@ pass_avlprop::execute (function *fn) simplify_replace_vlmax_avl (rinsn, prop.second); } - if (riscv_autovec_preference == RVV_FIXED_VLMAX) + if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL) { /* Simplify VLMAX AVL into immediate AVL. E.g. Simplify this following case: diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 4edddba..281dd06 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -72,13 +72,6 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; -/* RISC-V auto-vectorization preference. */ -enum riscv_autovec_preference_enum { - NO_AUTOVEC, - RVV_SCALABLE, - RVV_FIXED_VLMAX -}; - /* RISC-V auto-vectorization RVV LMUL. */ enum riscv_autovec_lmul_enum { RVV_M1 = 1, @@ -129,6 +122,14 @@ enum vsetvl_strategy_enum { VSETVL_OPT_NO_FUSION, }; +/* RVV vector bits for option -mrvv-vector-bits, default is scalable. */ +enum rvv_vector_bits_enum { + /* scalable indicates taking the value of zvl*b as the minimal vlen. */ + RVV_VECTOR_BITS_SCALABLE, + /* zvl indicates taking the value of zvl*b as the exactly vlen. */ + RVV_VECTOR_BITS_ZVL, +}; + #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT)) /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is diff --git a/gcc/config/riscv/riscv-selftests.cc b/gcc/config/riscv/riscv-selftests.cc index 289916b..34d01ac 100644 --- a/gcc/config/riscv/riscv-selftests.cc +++ b/gcc/config/riscv/riscv-selftests.cc @@ -378,7 +378,7 @@ riscv_run_selftests (void) compile-time unknown POLY value. Since we never need to compute a compile-time unknown POLY value - when --param=riscv-autovec-preference=fixed-vlmax, disable poly + when -mrvv-vector-bits=zvl, disable poly selftests in such situation. */ run_poly_int_selftests (); run_const_vector_selftests (); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 29d58de..2d32db0 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -912,14 +912,14 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) } /* SCALABLE means that the vector-length is agnostic (run-time invariant and - compile-time unknown). FIXED meands that the vector-length is specific - (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing + compile-time unknown). ZVL meands that the vector-length is specific + (compile-time known by march like zvl*b). Both SCALABLE and ZVL are doing auto-vectorization using VLMAX vsetvl configuration. */ static bool autovec_use_vlmax_p (void) { - return (riscv_autovec_preference == RVV_SCALABLE - || riscv_autovec_preference == RVV_FIXED_VLMAX); + return rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE + || rvv_vector_bits == RVV_VECTOR_BITS_ZVL; } /* This function emits VLMAX vrgather instruction. Emit vrgather.vx/vi when sel @@ -4431,7 +4431,7 @@ vls_mode_valid_p (machine_mode vls_mode) if (!TARGET_VECTOR || TARGET_XTHEADVECTOR) return false; - if (riscv_autovec_preference == RVV_SCALABLE) + if (rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE) { if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL && !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR, @@ -4448,7 +4448,7 @@ vls_mode_valid_p (machine_mode vls_mode) return true; } - if (riscv_autovec_preference == RVV_FIXED_VLMAX) + if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL) { machine_mode inner_mode = GET_MODE_INNER (vls_mode); int precision = GET_MODE_PRECISION (inner_mode).to_constant (); @@ -5123,13 +5123,13 @@ estimated_poly_value (poly_int64 val, unsigned int kind) unsigned int width_source = BITS_PER_RISCV_VECTOR.is_constant () ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant () - : (unsigned int) RVV_SCALABLE; + : (unsigned int) RVV_VECTOR_BITS_SCALABLE; /* If there is no core-specific information then the minimum and likely values are based on TARGET_MIN_VLEN vectors and the maximum is based on the architectural maximum of 65536 bits. */ unsigned int min_vlen_bytes = TARGET_MIN_VLEN / 8 - 1; - if (width_source == RVV_SCALABLE) + if (width_source == RVV_VECTOR_BITS_SCALABLE) switch (kind) { case POLY_VALUE_MIN: diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5e984ee..9f64f67 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -8801,10 +8801,10 @@ riscv_init_machine_status (void) return ggc_cleared_alloc (); } -/* Return the VLEN value associated with -march. +/* Return the VLEN value associated with -march and -mwrvv-vector-bits. TODO: So far we only support length-agnostic value. */ static poly_uint16 -riscv_convert_vector_bits (struct gcc_options *opts) +riscv_convert_vector_chunks (struct gcc_options *opts) { int chunk_num; int min_vlen = TARGET_MIN_VLEN_OPTS (opts); @@ -8847,10 +8847,15 @@ riscv_convert_vector_bits (struct gcc_options *opts) compile-time constant if TARGET_VECTOR is disabled. */ if (TARGET_VECTOR_OPTS_P (opts)) { - if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX) - return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8); - else - return poly_uint16 (chunk_num, chunk_num); + switch (opts->x_rvv_vector_bits) + { + case RVV_VECTOR_BITS_SCALABLE: + return poly_uint16 (chunk_num, chunk_num); + case RVV_VECTOR_BITS_ZVL: + return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8); + default: + gcc_unreachable (); + } } else return 1; @@ -8920,8 +8925,8 @@ riscv_override_options_internal (struct gcc_options *opts) if (TARGET_VECTOR && TARGET_BIG_ENDIAN) sorry ("Current RISC-V GCC does not support RVV in big-endian mode"); - /* Convert -march to a chunks count. */ - riscv_vector_chunks = riscv_convert_vector_bits (opts); + /* Convert -march and -mrvv-vector-bits to a chunks count. */ + riscv_vector_chunks = riscv_convert_vector_chunks (opts); } /* Implement TARGET_OPTION_OVERRIDE. */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 20685c4..45a9517 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -529,23 +529,6 @@ Target RejectNegative Joined UInteger Var(riscv_strcmp_inline_limit) Init(64) Max number of bytes to compare as part of inlined strcmp/strncmp routines (default: 64). Enum -Name(riscv_autovec_preference) Type(enum riscv_autovec_preference_enum) -Valid arguments to -param=riscv-autovec-preference=: - -EnumValue -Enum(riscv_autovec_preference) String(none) Value(NO_AUTOVEC) - -EnumValue -Enum(riscv_autovec_preference) String(scalable) Value(RVV_SCALABLE) - -EnumValue -Enum(riscv_autovec_preference) String(fixed-vlmax) Value(RVV_FIXED_VLMAX) - --param=riscv-autovec-preference= -Target RejectNegative Joined Enum(riscv_autovec_preference) Var(riscv_autovec_preference) Init(RVV_SCALABLE) --param=riscv-autovec-preference= Set the preference of auto-vectorization in the RISC-V port. - -Enum Name(riscv_autovec_lmul) Type(enum riscv_autovec_lmul_enum) The RVV possible LMUL (-param=riscv-autovec-lmul=): @@ -607,3 +590,17 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR) mstringop-strategy= Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO) Specify stringop expansion strategy. + +Enum +Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum) +The possible RVV vector register lengths: + +EnumValue +Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE) + +EnumValue +Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL) + +mrvv-vector-bits= +Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE) +-mrvv-vector-bits= Set the kind of bits for an RVV vector register. diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C index 6eb14fd..7410457 100644 --- a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C +++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable" } */ +/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable" } */ struct a { diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c index d2766f5..bd7ce23 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c index 362c49f..61619a0c 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c index d0f3542..8a2ebf5 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=scalable -fselective-scheduling -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=scalable -fselective-scheduling -fdump-tree-vect-details" } */ void foo (int *restrict a, int *restrict b, int n) diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c index 2dc39ad..6d8a1d4 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #define N 40 diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c index bc4f40d..9401e39 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #define TYPE double #define N 200 diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c index c809362..07e0cdf 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */ int f[12][100]; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c index 5c55a66..215f6de 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ typedef struct rtx_def *rtx; struct replacement { diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c index 117d54f..9ab2ab9 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ typedef struct { int iatom[3]; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c index 64a53cf..af3712c 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=dynamic -mrvv-vector-bits=zvl" } */ #include "pr113247-1.c" diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c index c2a46d8..470b103 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "pr113247-1.c" diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c index 31cecec..acc7081 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -ftree-vectorize -mrvv-vector-bits=zvl" } */ unsigned char a; diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c index b0305db..3947a9a 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 -ftree-vectorize --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */ unsigned char a; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c index 64007ee..d1cd70d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=scalable" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=scalable" } */ void __attribute__((noinline, noclone)) f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c index a82f34e..c36819e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/align-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */ void __attribute__((noinline, noclone)) f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int count) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c index d97555b..bbe6e90 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c index db29e37..71c8dd7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */ #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c index 1c25049..76dbe5b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */ #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c index e71b658..47938ea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c index d635499..bc04881 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c index 31661ee..20c67c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */ #include #include "fmax-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c index 7e04cbf..88815d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c index f8c39e3..bbfad07 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */ #include #include "fmax_zvfh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c index 0d2b53e..90f9378 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c index 19641373..7d49e6f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X #include "fmax_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c index c7865be..d8d362e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c index 14913ee..3881892 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X #include "fmax_zvfh_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c index 265a332..fd9c1c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c index 18faaad..664593c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c index 6f7689d..e79d6aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "mulh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c index a0f744a..25c7806 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "mulh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c index 48a2386..06ce0b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c index 86b7661..846ae1a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c index 370498f..70772c0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c index 32a7200..d33a2a7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include #include "narrow-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c index 5c414b1..01123e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include #include "narrow-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c index 21f8e8f..04a621b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include #include "narrow-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c index a2e1c33..1036c5d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-immediate.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -O2 -mrvv-vector-bits=scalable" } */ #define uint8_t unsigned char diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c index d661c19..087138c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c index d534885..c80e404 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c index a533dc7..95e974a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "shift-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c index 4790688..08f3558 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c index 8850d38..e1383fd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c index 82a5fe2..ecfcc5e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "shift-scalar-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h index 2cf645a..604696f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h @@ -1,6 +1,6 @@ /* Test shifts by scalar (immediate or register) amount. */ /* { dg-do run } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model --save-temps" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model --save-temps" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c index b6328d0..1de8685 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vadd-run.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c index ba453d1..f62bb39 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c index 60c760d..06a30de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c index cd0da74..a3b0126 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c index 86d5283..64dd344 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c index 30c3ef7..ef52f49 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c index 6c2d096..c567dec 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c index 848b6eb..5a03db2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c index f7636ab..a306170 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c index dee8a2d..536212c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "vand-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c index 43f79fe..32d81be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #define MAX 10 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c index 8b26617..e436d27 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vdiv-run.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c index 4ce2cee..fee2d99 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c index f7d7704..095dcaa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c index bb421fa..8a40080 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c index 0dd4df6..b1fae22 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c index 9764cc3..4ec78b2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math -fdump-tree-optimized-details" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c index c9f9d83..7b9e5eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vdiv-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c index 9b03aa3..282356d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c index fbfa3ab..9876ce3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c index cf01ebc..c079932 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c index 85e19c1..292a23f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmax-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c index 6fce322..512a802 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c index 8764073..079ed7c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c index 193dacc..3ee49f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c index b24d4f3..9ae8c88 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmin-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c index 4f4566a..dccf9a5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vmul-run.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c index 3704995..988876d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c index 3e0f061..571623d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c index 7d3dfad..19a1f1d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c index ca245e2..4ff7a1d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c index a549d6f..e2c2f2f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c index 63bcf70..491b365 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vmul-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c index 10b3499..f69a82c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c index 70ea8ef..2001568 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c index 44d09a2..f09944e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "vor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c index a08038e..6425ea6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c index 7628f4a..4056495 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c @@ -1,4 +1,4 @@ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */ #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c index 8af9a8b..a6b82ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -fdump-tree-optimized-details" } */ #include "vrem-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c index 318323e..b83ebce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vsub-run.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c index bd44f5a..461521a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c index c4ab934..4853f0bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c index f09d066..57fcb70 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c index 9e71911..54166c2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c index 9f44f5f..626d7c1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c index b438bea..1a5770f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c index 9c03d8f..6229442 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c index 83b223e..9ea9df8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c index 6ba007c..6cc943a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "vxor-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c index 8805997..86ad19c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -O3 -fdump-tree-optimized" } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -fno-vect-cost-model -O3 -fdump-tree-optimized" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c index 9ff93d3..07f9d91 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-2.c @@ -1,6 +1,6 @@ /* { dg-do run } */ /* { dg-require-effective-target riscv_v } */ -/* { dg-options "--param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */ +/* { dg-options "--param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -ftree-vectorize -fno-tree-loop-distribute-patterns -fno-vect-cost-model -fno-common -O2" } */ #define N 128 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c index 643e91b..9af5add 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -O2 -ffast-math" } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=scalable -fno-vect-cost-model -O2 -ffast-math" } */ #define N 16 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c index c860e92..1b6ad26 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */ typedef struct { short a; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c index df16fb2..1a3fc16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-lmul=m4 -mrvv-vector-bits=zvl" } */ typedef unsigned char u8; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c index 975c481..8bbbf84 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gc_zve32f -mabi=lp64d -O2 -mrvv-vector-bits=zvl" } */ extern void abort(void); extern void exit(int); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c index 07b7e16..91fc5dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -O3 --param=riscv-autovec-lmul=m2 -mrvv-vector-bits=zvl" } */ union U { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c index 99a230d..0faedac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c index 1a82440..40fa108 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c index 07a9074..e52a23a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-trapping-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-trapping-math -fno-vect-cost-model" } */ /* The difference here is that nueq can use LTGT. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c index a73f7d8..fc762ad 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c index 1055338..4349217 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "vcond-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c index 234535d..355012d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ /* { dg-require-effective-target fenv_exceptions } */ #include "vcond-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c index e547da6..c111b55 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-trapping-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-trapping-math" } */ /* { dg-require-effective-target fenv_exceptions } */ #define TEST_EXCEPTIONS 0 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c index b72a44f..bfe8c41 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "vcond-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c index afd73c2..0a3b847 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c index f549b9e..0f62f26 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c index 8b6ae61..f55a1b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c index 8b6ae61..f55a1b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c index 7f7d08a..c17f618 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c index 8b1acea..68c34c2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include "cond_arith-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c index d659f67..790a2d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c index ef9e365..919de83 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include "cond_arith-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c index 48c2a2b..8180d44 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c index 375a7b9..2aeba68 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c index fc8b351..4298e8c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c index df22bd3..d82a478 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_arith-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c index 8e0d365..63c5cab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_arith-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c index b2da299..85b53b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_arith_run-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c index 2832cc5..ff8af28 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_arith_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c index a73d9f7..98d5806 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_arith-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c index e57f7db..4462a45 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_arith_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c index 03092f4..19d381f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_arith-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c index 47055de..56e12fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_arith_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c index 8d679cd..09019ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_arith-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c index 1e317d9..b51260d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_arith-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c index c1a5f71..b82302f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */ #include "cond_arith-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c index 07512e5..1cfa93b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c index d2d1ea3..8bf0e99 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c index f793e93..b2d162d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c index 79b835a..df571f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c index 31509ec..59432d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c index cb4fa18..0631019 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c index b740001..54971cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c index 3bc1a4e..b8da8b0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c index a65317c..5e8ef50 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c index b764b72..7af99c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c index 3f14547..497e8cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_float2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c index a47602a..0fc40c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_float2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c index c13f134..dad6ee0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c index ebb0a59..733ee5e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c index 2405c7f..672b595 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c index 3b2455c..c55b414 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c index 00f01ca..7f25a0c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_float2int_zvfh-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c index c3dc653..8e42674 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_float2int_zvfh-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c index a211192..764c860 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c index a211192..764c860 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c index 4b35569..f967914 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_int2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c index 42239ad..8c43bb1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c index cb7f35d..be31f3c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2float-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c index 1ec6c59..1c53f172 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2float-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c index 84988a7..5eb6030 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c index 2b6c72f..aa6d6d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c index e800abe..33cb991 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c index 904e01c..082d9e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c index 07b28dc..d5080e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2int-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c index 3bf63dc..e733009 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_convert_int2int-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c index f223ba2..d0c1d66 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c index 7340cc9..2d12dd1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */ #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c index 471b56a..b45e139 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -O3 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */ #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c index 79a5130..ac85495 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "cond_copysign-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c index 6f37680..2d30805 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c index eba1ab5..dd55e47 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c index c58eae9..f99ae26 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c index 4ad7f72..e4d67ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c index daec93b..61f6457 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_fadd-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c index 2908bea..aa1ab02 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_fadd-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c index e35419e..e4ba2d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_fadd-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c index 515afb2..0a07658 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_fadd-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c index b4df366..88a23aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c index b2ac8e1..6c1236a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c index 6941a7b..95f4f04 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c index 30cee81..eb5f068 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c index 9b6a03e..009c613 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c index 345f6ef..3b6161a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c index 26a2179..6ee57db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c index f78fa09..eae9303 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c index e344485..090481e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c index 7517087..3551cc3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c index 98b3c48..e182d33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c index e56eea7..7e7030f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c index 0fddce1..a93775e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c index ea0c105..1d686e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c index d282772..8005504 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c index 735b899..714e5e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fma_fnma-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c index fedee13..1415d79 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c index 76f69e4..20feebc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c index bb8d1ae..998877d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c index e4bb383..c2def15 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c index 3dc1fb8..0d12168 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax-1.c" #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c index 0cf6756..5283c5b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax-2.c" #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c index df4a5de..0fb82a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax-3.c" #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c index 1b94951..aea43e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax-4.c" #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c index 1afa2f2..69356fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c index 23762b7..8199791 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c index 1837fda..f9c118f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c index 766e42c..69cf109 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c index ae6381a..8d29a9a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax_zvfh-1.c" #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c index 697abb2..551de89 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax_zvfh-2.c" #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c index d4ee99f..0b8b312 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax_zvfh-3.c" #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c index c006c64..7ad3226 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include "cond_fmax_zvfh-4.c" #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c index 59b22db..3e00efa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c index 500c4bc..7d503bf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c index 85b9238..830af53 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c index 5ec7fd7..2326741 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c index 139f9f7..821333a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X #include "cond_fmax_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c index e9449b8..800b931 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X #include "cond_fmax_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c index f70c344..82e52f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X #include "cond_fmax_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c index fe700a2..823f9e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X #include "cond_fmax_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c index a839dc3..c5fcbb8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c index 7a3fca2..936316b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c index ed04936..faf7033 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c index 3ba72d2..7eafc53 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c index 01a7dfd..a760434 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c index c2d693e..0aa5728 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c index 4c46968..f72e418 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c index 49a0c67..cd7f4ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -fno-signaling-nans" } */ #define FN(X) __builtin_fmin##X #include "cond_fmax_zvfh_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c index d3bf00e..52770ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c index f593d56..586f33a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c index cc23b12..e7b2d9d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c index bd7b27a..38597cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c index bd7b27a..38597cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c index bcb356e..15975bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c index d86ceb8..3dbc1c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c index 87c497a..83da5f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c index 08de30f..3412e97 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c index 46c2157..5f4866b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c index 266bee7..aaa8d98 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c index e325f9b..91e1727 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_fms_fnms-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c index 9c9ed43..507645b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c index 3e7d1db..880198b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c index e3c306d..698bf20 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c index 57163ef..5be3612 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c index 2e031a9..ae41331 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c index 29a75ce..9baf89b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_fmul-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c index 744f48a..da777a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_fmul-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c index edd940c..975fc60 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_fmul-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c index 4dea086..d092835 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_fmul-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c index c3763b1..7954732 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_fmul-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c index f902702..80ef479 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c index 70daec9..852835d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c index 72d498e..20ddec0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c index a28bf57..bd7f14d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c index 03fb859..6bb1619 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c index 9ef36dd..4d4752b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_logical_min_max-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c index 0d1aec2..29b1680 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_logical_min_max-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c index caf9c6a..92fc5ec 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_logical_min_max-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c index bea7c98..2e9b828 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_logical_min_max-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c index bacceb3..8e589c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_logical_min_max-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c index 6ff2dc5..e0bdf26 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c index c4c2b50..aab3c8d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c index 5dd0b34..6bcf2bf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_mulh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c index 183542d..b62d41d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_mulh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c index d068110..6d3748e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c index 2637991..90c1f59 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c index 17a640b..8ad0ae1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c index ff3646a..a0bfa61 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_narrow_shift-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c index f3ae207..3962dc4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_narrow_shift-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c index 0fcf2c5..27e4147 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_narrow_shift-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c index 1c8a4ca..7c9c54a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c index eb375dd..cc7f33e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c index ab1c9e9..f84e6ea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c index c7dd3df..bf429c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c index cdaa3e1..b632bf2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c index aa957dd..f61c706 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c index 1f271c6..355154e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c index f6dc7ff..b3f29b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c index df3f390..ec3e645 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c index 00c309c..5e08880 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_shift-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c index ec6f0f8..44543c3e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_shift-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c index 8c62825..8615891 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_shift-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c index 32a6f6c..5995912 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_shift-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c index 0b0730e..3ca8e22 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_shift-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c index 31f44ec..a1ed9d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_shift-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c index fdd225e..3183efc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_shift-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c index 8ab8e84..0da7770 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_shift-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c index fcaa1cd..8a1618e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_shift-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c index d6b2f0f..1753817 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c index 1c5d3f0..081185e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c index c632d63..7c62bc4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c index 8e1bc60..fe6e669 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c index c3981c8..8c24929 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */ #include "cond_sqrt-1.c" #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c index a48e281..fc6bb6d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_sqrt-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c index e80ac75..f40c023 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math " } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math " } */ #include "cond_sqrt-zvfh-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c index 6f437b6..c7e04e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ #include "cond_sqrt-zvfh-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c index 28a5e02..2233c6e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c index e456e68..4886bff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c index e2a8733..a75bde9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c index 37c7ccb..ef2784b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c index 2b4857f..3d90f7b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c index 4519a56..da9740f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c index 0368f1c..e0a7994 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c index e3c19e4..a70a1a3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c index 71e5196..803ec9c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_unary-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c index c2d68fc..2f3ffe2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_unary-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c index e1e38d9..97d495a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_unary-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c index 2f5b967..23be9f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_unary-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c index d507a38..95c4118 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_unary-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c index fc6cbd2..776ce11 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_unary-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c index 1825372..ff3bbce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_unary-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c index 157310e..c5c0aba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "cond_unary-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c index c67593d..31491f3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c index f8fdebb..d1997d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c index ef61a4f..d02a8e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c index 9aa6355..59ca535 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c index efbd3d1..c091ec3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c index 083571c..f804696 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c index 41017c3..4a3f301 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c index 8aea32d..dfac156 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c index 9e32211..4b431ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c index 47889f3..a80c3b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include #define TEST_TYPE(TYPE1, TYPE2, N) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c index 662d135..c2a207d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include "cond_widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c index e738ede..9dbecee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include "cond_widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c index 60f92ca..7c31901 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include "cond_widen_reduc-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c index f593db3..08d9839 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/pr111401.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ double __attribute__ ((noipa)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c index c24d66a..1611ea8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ /* This test ensures that we vectorize the conversion by having the vectorizer create an intermediate type. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c index 3fd1260..91bcf2c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-trapping-math -fdump-tree-vect-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-trapping-math -fdump-tree-vect-details" } */ /* This test ensures that we vectorize the conversion by having the vectorizer create an intermediate type. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c index 3098ba6..ee822bf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c index dae1442..12ac56b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */ #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c index ccb2bb5..1cecd1d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */ #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c index bd85f3f..4db500d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c index 2000cfd..e519704 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c index 0a79adf..9ee22e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */ #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c index e749847..3cf50838 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */ #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c index 3164fed..a6a58e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfcvt_rtz-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c index 5bec699..64693ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c index 43967af..8b40c7c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */ #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c index d49370b..5dec77e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */ #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c index dbbbb61..ea654d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfncvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c index f516677..e7d013f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c index 73e4644..a5bd094 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */ #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c index e9d31a7..cdecf9c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */ #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c index 0342d14..7a110f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh} } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfncvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c index 41b8781..3ec64d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c index 10fe75d..efdef981 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c index fd40fa2..da8974c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c index 6eb9f14..2cf18cf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c index 333bd7a..11a0a55 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c index 0ab42af..9581202 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -fno-trapping-math -mrvv-vector-bits=scalable" } */ #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c index e1a4b63..7df211d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -fno-trapping-math -mrvv-vector-bits=scalable" } */ #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c index 3d11654..026ef26 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfwcvt-ftoi-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c index adf67a8..3f0ea5a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c index cf18099..6d2409f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable" } */ #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c index b115388..acc36e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable" } */ #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c index 8df59a9..295cb3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfwcvt-itof-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c index bf369d6..0d9f834 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c index 006bdb2..3f0a113 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c index 7ec7107..d48b656 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c index 9f2c983..f4ca172 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ #include "vfwcvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c index 2dfd6eb..ac3ce59 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c index 2b5aa00..cc3d624 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c index 29349b3..0b43787 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "vncvt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c index ed1fa35..c6409f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c index 538216a..7f40f5f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c index 29348cc..833f1da 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "vsext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c index 3770f83..89ea307 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c index 3e92843..0ed4a14 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c index cee0012..9c60c0f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "vzext-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c index 61eac38..ee5f18c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c index 3f524db..85917fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fold-min-poly.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1" } */ +/* { dg-options " -march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1" } */ void foo1 (int* restrict a, int* restrict b, int n) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c index b1e6a17..53263d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c index 2c9e7dd..6fef474 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c index 3e6a340..ad23ed4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c index 6906af1..65f3f00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c index e10a9e9..4f99a5f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -fno-cprop-registers -fno-dce -mrvv-vector-bits=scalable" } */ long foo (long *__restrict a, long *__restrict b, long n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c index 7021182..cf6d742 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3 -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c index 15ce74a..84349fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c index 69c2a44..020d08e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c index ecd3219..06f3138 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "live-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c index 3724dac..c25e8f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/live_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "live-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c index 69cc3be..3d8f631 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "multiple_rgroup-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c index d1c4190..8a485c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "multiple_rgroup-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c index 9579749..0efa7e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c index e87961e..b572557 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c index 4352140..7ff46e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl" } */ #include "multiple_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c index 13602c4..04789ff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl" } */ #include "multiple_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c index 292a9af..f70fb2a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl" } */ #include "multiple_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c index a764161..fda6bf7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl" } */ #include "multiple_rgroup-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c index 15178a2..a851229 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c @@ -1,5 +1,5 @@ /* { dg-do compile } *. -/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c index e27090d..cac82dc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c index ca88d42..ce50d80 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/select_vl-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-schedule-insns --param riscv-autovec-lmul=m1 -O3 -ftree-vectorize" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c index 10cc698..9d02869 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fno-tree-loop-distribute-patterns -fdump-tree-vect-details" } */ #include "single_rgroup-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c index 24490dc..1b2f1f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "single_rgroup-2.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c index 9cbae13..f7133b3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "single_rgroup-3.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c index 52d21b2..103a12e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns --param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-fno-vect-cost-model -fno-tree-loop-distribute-patterns -mrvv-vector-bits=scalable" } */ #include "single_rgroup-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c index d753d56..8971f48 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl" } */ #include "single_rgroup-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c index 04edbc7..79cb2b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "single_rgroup-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c index 0a1d1f7..fae1ab5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c index c521561..ed37194 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c index ccb5ab6..32def0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c index 03529f4..41dc574 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c index 807cb49..bed0e1a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c index e0d089e..d75f461 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c index 731b028..7057e0d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c index 05220c3..02fb365 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c index 50d06d5..3adec12 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c index 06bf10e..8f1a7e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c index dda2075..2fa6168 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c index 5605b1b..08ac776 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c index 5e64231..88598e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c index e18ebd3..7543eca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c index c78b370..eaa580f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c index 9fca6bd..324cae0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c index 3dd744b..fedbf29 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c index cf2fd1d..42c6923 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c index 1b99ffd..d7599bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c index cb07c96..715bd72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c index b7ba21c..b13828a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-10.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "slp-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c index 0f8bdad..3c330d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-11.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "slp-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c index 75ec419..b2a853c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-12.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "slp-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c index 555a73f..b38f8eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-13.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "slp-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c index 0219528..680240e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-14.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "slp-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c index 6d3218fc..76ebe06 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-15.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "slp-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c index 490003e..c0a3b18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-16.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c index 1ea6a27..473ae6f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-17.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c index 6685e03..a0f9cce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-18.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c index 58de15b..7649a91 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-19.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-19.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c index d3ee634..28c1ec4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c index d4dc241..a595795 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c index 5a4b768..fea844d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c index 8084657..7974774 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c index 881dc79..46df36f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c index 886b9c4..269be8c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "slp-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c index 7e41733..cc336ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "slp-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c index c010564..ee2d2b3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp_run-9.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "slp-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c index bff6dcb..ceb2524 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/post-ra-avl.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ int a, b, c, e; short d[7][7] = {}; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c index 17dd439..49d9680 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-vect-cost-model" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-vect-cost-model" } */ int a; void b() { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c index cf2d1fb..eee205a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110964.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast" } */ int *a; long b, c; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c index 6e163a5..5922279 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */ int a, b, c; double *d; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c index edad140..3875eea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c index fa20a21..7a0b671 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable -Wno-implicit-function-declaration" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize -mrvv-vector-bits=scalable -Wno-implicit-function-declaration" } */ #include int a, b, c, e, f, g, h, i, j, k; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c index a4f8c37..4a9f946 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2 -fno-vect-cost-model" } */ #define K 32 short in[2*K][K]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c index 2ad5013..1a853f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ void f (int *__restrict y, int *__restrict x, int *__restrict z, int n) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c index 4ef76cd..7ee4ad3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112552.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -w -Wno-incompatible-pointer-types" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -w -Wno-incompatible-pointer-types" } */ int a, c, d; void (*b)(); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c index 4afa7c2..05aae27 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112554.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ int a; void b() { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c index 25e61fa..01945b2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */ +/* { dg-options "-O3 -ftree-vectorize -mrvv-vector-bits=zvl -mcmodel=medlow" } */ int printf(char *, ...); int a, b, c, e; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c index 73aa3ee2..fc67bb4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c index 911b692..441736c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c index 0954fe2..8721d35 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112599-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gcv_zvfh_zfh_zvl1024b -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c index f50df65..3743ac8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112694-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-options "-march=rv32gc_zve64d_zvfh_zfh -mabi=ilp32d -mcmodel=medany -fdiagnostics-plain-output -ftree-vectorize -O2 --param riscv-autovec-lmul=m1 -std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c index 8f7f13f..d0c6744 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112854.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv32gcv_zvl1024b -mabi=ilp32d -mrvv-vector-bits=zvl" } */ short a, b; void c(int d) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c index 5c1d218..61c9f01 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112872.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */ int a, c; char b; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c index c049c5a..a1244c1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112999.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O3 -fno-vect-cost-model -fno-tree-loop-distribute-patterns" } */ int a[1024]; int b[1024]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c index 57c5cff..d65fe78 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-1.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ /* { dg-require-effective-target riscv_v } */ #define SIZE 128 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c index c36a16d..2d203ea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-2.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax --param=riscv-autovec-lmul=m2" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl --param=riscv-autovec-lmul=m2" } */ /* { dg-require-effective-target riscv_v } */ __attribute__((noinline, noclone)) static int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c index 063cf85..b34b528 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113393-3.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O3 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */ /* { dg-require-effective-target riscv_v } */ #include "pr113393-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c index 6c86f29..1078731 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */ #define N 32 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c index c5fe520..a0bee1c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ #include "extract_last-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c index 85547c8..b3a1ecb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */ #define N 32 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c index c165cb3..29ed2fa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ #include "extract_last-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c index 9a04af6..779d051 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */ #define TYPE double #include "extract_last-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c index 88f8a4c..dfebfa5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ #include "extract_last-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c index b1eea0d..f572dd8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ #include "extract_last-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c index 2c94ef5..73d99b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c index a9ac667..6021a9e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ #include "extract_last-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c index dc7fa63..6f2d1c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */ #define TYPE uint8_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c index 4e434a1..8bb262e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ #include "extract_last-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c index e75e9b2..927d758 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */ #define TYPE int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c index a37eb26..3fc2580 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-optimized" } */ #include "extract_last-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c index c7ae0d7..c5899d2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-optimized" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-optimized" } */ #define TYPE uint64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c index 7415310..407db84 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */ #include "extract_last-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c index 367fa23..3df4bbd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "extract_last_run-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c index cff23b5..7ac371e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */ #include "extract_last-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c index fa05d11..77aa120 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "extract_last_run-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c index 90a0ff5..42e28f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */ #include "extract_last-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c index 77ef983..080450e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "extract_last_run-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c index e969f10..6985b9a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "extract_last_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c index 6433f10..007e645 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */ #include "extract_last-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c index ad620c2..4a8aa02 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "extract_last_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c index 1d984b1..8383cfb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */ #include "extract_last-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c index 0339102..53a7df0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "extract_last_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c index 2f078e2..1cfdf7a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */ #include "extract_last-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c index eac1b531..a577712 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "extract_last_run-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c index d23fe74..6318033 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl -fno-vect-cost-model" } */ #include "extract_last-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c index 0d543af..82a5c15 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c index be339bd..645a760 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c index 136a8a3..4af5921 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c index c363834..d882e36 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c index f00a128..57f47eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c index e973041..0af893d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c index 30961f0..cc44a06 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include "reduc-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c index e2e65be..d91382c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */ void __attribute__((noipa)) add_loop (unsigned int *x, int n, unsigned int *res) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c index 4cbcccd..fe47aa3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */ int __attribute__((noipa)) add_loop (int *x, int n, int res) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c index 6810561..6630d30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model -fdump-tree-optimized-details" } */ float __attribute__((noipa)) add_loop (float *x, int n, float res) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c index 1a3ca9c..d736a89 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ double foo (double *a, double *b, double *c) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c index 17a6b6f..55cb6eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -ffast-math" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c index 91004e7..0aa66ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model" } */ #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c index 83beabe..1a99df6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -ffast-math" } */ #include "reduc_call-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c index 3523c0f..3222f20 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ double foo (double *restrict r, const double *restrict a, const double *restrict b, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c index f52af7a..37d669b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include "reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c index 6dc372f..2ff247d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c index 36ba4b1..511dab8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "reduc-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c index dceb88e..bf6b8a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include "reduc-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c index 772003a..591b23c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include "reduc-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c index c47e3fc..ee1c25e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=fixed-vlmax -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=zvl -ffast-math -fno-vect-cost-model" } */ #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c index ec526c0..d98c2a4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c index c9ffd8c..0ace3a7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c index 29200df..7726b46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #define N 0x1100 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c index c293e9a..5146b86 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c index 2e1e7ab..fc173d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define NUM_ELEMS(TYPE) ((int) (5 * (256 / sizeof (TYPE)) + 3)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c index f559d40..e259f3e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ double mat[100][2]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c index 428d371..94f9670 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ double mat[100][8]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c index 24add22..e826118 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ double mat[100][12]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c index c1567b0..607d8be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */ float double_reduc (float (*i)[16]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c index f742a82..f55088f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */ float double_reduc (float *i, float *j) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c index 74b989d..d22a3a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "reduc_strict-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c index 340d56b..59e8ab0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "reduc_strict-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c index b3bba24..272b459 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable --param vect-epilogues-nomask=0 -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c index ab047d7..fb77955 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-signaling-nans" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-signaling-nans" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c index 3c03a87..3ae1fc6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/scalable-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -O3 -fno-vect-cost-model -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c index 1c69722..43da34e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c index 2a9ffbc..b318364 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */ +/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4" } */ #include "series-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c index ee1baa5..d82a673 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fdump-tree-slp-details" } */ +/* { dg-additional-options "-std=gnu99 -O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-slp-details" } */ void __attribute__ ((noipa)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c index b7d86c6..5b0e541 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=gnu99 -O3 --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=gnu99 -O3 -mrvv-vector-bits=scalable" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c index e5dc10a..f8c9f83 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c index 9d61a85..8426bc3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c index a686236..581a2dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c index e3c48df..4bb06a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c index 81f1a7a..87502f3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c index 911af2a..c6085fd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c index 112face..042dec4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c index cf29d64..23b85f13 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c index c8c8742..fde2006 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c index 5a6a4de..fddc038 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c index c6c2b6b..8a476dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c index aa2642a..4ef9d93 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c index eeecb03..67bbdfe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c index 1153362..72247bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_load-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c index 6df5f08..79c97a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c index 532b458..f6fe53a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c index 92ed236..05851d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c index 4a4048f..ee84d13 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c index eca8d5a..6bde96d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c index 3cce1620..cec7e30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c index 9d0073b..49f5cb6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c index d4e9895..a700519 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c index 02a28fa..9e5a4067 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c index c07df7e..ce87627 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c index 4c1314b..c105abc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c index 5152875..a695259 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c index 3b04191..1a29b46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c index 2ffe943..c94f1b0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "mask_struct_store-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c index f49d92d..b467378 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #include #ifndef TYPE diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c index dc4d651..b80e174 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE _Float16 #define ITYPE int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c index 36ade63..1b976ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE float #define ITYPE int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c index a2a93c4..b36ca8d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE double #define ITYPE int64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c index 4da1c41..76b3996 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c index f652a35b..1abce7a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c index 29d32ab..dfd51b2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c index 15de93e..10088bd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c index 44eb072..f460ec2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c index f6f559e..3cb01dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c index 2a61a79..52ded08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE uint16_t #include "struct_vect-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c index 3d818da..48395e9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE uint32_t #include "struct_vect-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c index b5ad45e..03829dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE uint64_t #include "struct_vect-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c index 63b83df..aef9cb7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE float #include "struct_vect-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c index 2494744..59020b0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c index dd01769..c13f1e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE uint16_t #define ITYPE int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c index bedf17a..7a30314 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE uint32_t #define ITYPE int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c index 8b60822..85a9022 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE uint64_t #define ITYPE int64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c index a499c7c..dafa565 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #include "struct_vect-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c index 049280b..a8ff07d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=gnu99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=gnu99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE _Float16 #define ITYPE int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c index 387d697..93bd254 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE float #define ITYPE int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c index 391caa4..6d4f54d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE double #define ITYPE int64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c index 711ea44..1b19b01 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "struct_vect-13.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c index bb66c5f..7e51b9e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "struct_vect-14.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c index 07d6c08..2007c00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "struct_vect-15.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c index d2a0046..21506db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "struct_vect-16.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c index c34a8ab..8e30b33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "struct_vect-17.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c index 5346c90..126edb4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "struct_vect-18.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c index 6ac6182..4cf0905 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE uint16_t #include "struct_vect_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c index f64174b..1075b37 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE uint32_t #include "struct_vect_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c index 610ee8e..9f4790c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE uint64_t #include "struct_vect_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c index 5dfa0ba..980f506 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=fixed-vlmax -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2" } */ #define TYPE float #include "struct_vect_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c index c836bcd..72d29b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "struct_vect-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c index 2023b33..18b6192 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE uint16_t #define ITYPE int16_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c index 476c54a..728f9aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE uint32_t #define ITYPE int32_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c index 2cb2efa..db6f1f1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #define TYPE uint64_t #define ITYPE int64_t diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c index 38e4815..6da2cd2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c index 4130869..05cf275 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c index a8685c6..e8929bd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c index d13ab41..9d71890 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c index f00c608..c13401d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c index 1886fc2..fa64ce0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c index fff5191..c43d0b3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c index 238cd5d..a1ca5ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c index 8d9e63c..b75ae25 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c index 7fdf512..88905ea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c index a73e04b..701d84d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-schedule-insns -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c index b5ee009..ef9958b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c index c5fab3f..a30ddf9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c index a65c398..b1d117c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c index 9725cfa..fbe53f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c index 97be71c..6f23bcc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */ #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c index 1336742..ba005e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c index de6d404..f749ef3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */ #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c index 4d73a54..00b793d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c index 6fa28a2..34b8b4b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c index 33faf05..7bdf19e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */ #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c index 4480799..89e4938 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c index c89f583..d31c9bd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-vect-cost-model" } */ #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c index 2de649b..221b03e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-schedule-insns -fno-vect-cost-model" } */ #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c index af6d5c6..afb988e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c index f4a2060..b4761bf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c index 0060592..1b9efa9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c index f295e87..bc21c30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c index 9dedaa9..170d976 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c index 09e44bb..b885801 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c index 3a2bdcc..87be031 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c index e672fc1..3de31dc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c index 1a25928..f54d96c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c index c6ebc12..2871362 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c index e764723..047aefc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c index 05878d0..a744bd5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c @@ -1,4 +1,4 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include "ternop_run-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c index 56599d7..01dd791 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c index d4492f9..9db0d23 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c index dd6e6f7..08dcb3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c index 8bdc4e9..08eb3b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c index 7817134..0db89cf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c index 3e96688..344871b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c index f6a07a9..39108aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c index 4de0124..d2122da 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c index 9e79c03..652d5fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c index 61b97f1..950936a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c index 52ef262..f4292a0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c index 2bc4d96..0636dd6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c index 6c707e3..cbda6c4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c index 4d57fe5..90efe8a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c index 80f1d54..2bf3c3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c index 29b1683..0f85892 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c index 3f9036c..581fab5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c index e9ad951..b71ea15 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c index fb0cb1f..c6892aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c index 06f6dbd..c148155 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c index b7f931e..f546964 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c index 3a712fd..b17970b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c index f01cf6d..b72f2a7a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c index eb8a105..5a190aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include "ternop-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c index 49cdffe..f3be58e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c index dea790c..8575191 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */ #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c index b58f1aa..d1bd43a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */ #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c index f0c00de..22b5f60 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "abs-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c index 9c065be..fad528a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c index 5719d9c..0199f8c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -fdump-tree-slp-details" } */ int x[8]; int y[8]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c index 739d197..67753d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c index dc3f7c4..5a1f910 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c index 31d9975..3799f98 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c index c974ef0..a1ecd4d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_zvfh && riscv_zfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vfsqrt-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c index 1429731..100b8ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c index 4a9ceb5..66b512e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c index 2c5e2bd..d32c6a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=zvl -ffast-math" } */ #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c index 38c8c7a..6e233c1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -ffast-math" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl -ffast-math" } */ #include "vneg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c index 6df15bc..2941a34 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c index ecc4316..9f9f5d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c index 67e28af..6bdb558 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "vnot-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c index ebbe5e2..00a602a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c index 66d8ea1..3968e53 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c index 24daca5..64a114e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c index 264a096..f1600e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */ #include #include #define N 16 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c index 06521d1..44fe7aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c index 1690615..c41f11b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m2" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c index 10b292b..12174f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m4" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m4" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c index f7e6765..7ecfc80 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m8" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 --param riscv-autovec-lmul=m8" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c index 1d0acf9c..5dfa458 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c index c6a65ac..07c869e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c index 0cb39b7..06af9da 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c index ffc1f19..3554b6c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c index eea1f97..0957abd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c index 3f69cc7..4f265d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c index d9f65ab..32bbea7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c index 7f9aa9f..85ab1ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c index 908d564b..0020b61 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c index 71ccf54..18786e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "combine-merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c index 9c19b9e..44de048 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "combine-merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c index 5983757..216ecb4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c index c6cd7bb..481f409 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c index 0fc2cef..d30a0d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c index 54b89ed..1b0a191 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c index 4b27502..1ea57b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c index 4b85c71..39b7e81 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c index 349541b9..b3d859d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include #include "compress-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c index c91de2e..5aa7b3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include #include "compress-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c index 55476e4..cf3477d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include #include "compress-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c index 711b071..d5480ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include #include "compress-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c index 95e89e8..5c0ce6b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include #include "compress-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c index e83ae74..a1d2696 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include #include "compress-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c index 7dc2b99..cb94234 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c index 9aa9100..ce96aa5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c index d12424e..ea41ae3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include #include "consecutive-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c index 8362e9f..8a7a679 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include #include "consecutive-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c index 9ed7c4f..d73bad4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c index e3c62b7..77edb56 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "init-repeat-sequence-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c index 2395bd6..84d7bab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "init-repeat-sequence-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c index eb3f670..3a4c745 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "init-repeat-sequence-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c index 875efa3..f016688 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "insert-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c index a3f4357b..55c7ed4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "insert-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c index 3e3ecd1..2b39e0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c index f07b658..4b2d077 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c index 57bf8fa..3b6895e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c index 8bc29c3..5ef7036 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c index f6140fb..ec8f198 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c index 7ab4bca..986b85c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c index a501026..b5ebce0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c index 934cdd9..b960d99 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include "merge-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c index 9309e46..e907320 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include "merge-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c index e2dcc19..db16077a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include "merge-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c index df4fb96..dda8b3b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include "merge-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c index 7c32bf0..8d429b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include "merge-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c index 8a1ecd6..7945baa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include "merge-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c index 90a1d58..8401f1d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O3 --param riscv-autovec-preference=fixed-vlmax -Wno-psabi" } */ +/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */ #include "merge-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c index 55c5945..2172d77 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ #include "perm-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c index a17b61d..8874c05 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ #include "perm-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c index 1824564..139ff08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ #include "perm-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c index 6951fd2..08f03de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ #include "perm-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c index dc22e72..6b7db30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ #include "perm-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c index 24398f2..240acf2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */ #include "perm-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c index 71b1305..dce65f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O0 -Wno-psabi" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O0 -Wno-psabi" } */ #include "perm-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c index 7710654..463a584 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c index d75d9c5..304a0a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "repeat-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c index 98c04a5..eae8c3e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "repeat-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c index bd4ba41..990ba84 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "repeat-3.c" int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c index edcf4f9..6203597 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "repeat-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c index bc26e6d..f3a636c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "repeat-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c index c8482876b..af113e41 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3" } */ #include "repeat-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c index b48252a..89c1af3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c index 46d2777..d84c21d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c index 469c30d..0a0d9b2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param=riscv-autovec-lmul=m8" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */ #include "trailing-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c index cbb0b15..194d18b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param=riscv-autovec-lmul=m8" } */ +/* { dg-options "-mrvv-vector-bits=zvl -O3 --param=riscv-autovec-lmul=m8" } */ #include "trailing-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c index 217885c..28b8a82 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c index 0abc6cf..a53ef39 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64 --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64 -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c index f45e6a7..d45fb4c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c index 6716b0a..1885004 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c index 0a649ac..3a4ed22 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c index fd5146f5..e3f3b39 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c index 4723312..4c876ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c index 40e1b93..5542d48 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b --param riscv-autovec-preference=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c index ed66a2c..999ddf6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c index ab8e79c..e816c7e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d --param riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -mrvv-vector-bits=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c index d8aa5c5..aa7a749 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ typedef char v16qi __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c index 57376a3..cec8b30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ typedef short v8hi __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c index b37cd56..6b595a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ typedef int v4si __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c index 0788447..d6bf318 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ typedef long long v2di __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c index ec8658d..5835138 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ typedef float v4sf __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c index bbb53a1..bbacbfc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable" } */ typedef long long v2df __attribute__ ((vector_size (16))); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c index fcacc78..cf6a6c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d --param=riscv-autovec-preference=scalable -O2" } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -mrvv-vector-bits=scalable -O2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c index e8d017f..e8a76ec 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fno-builtin" } */ #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c index f85ad41..f1fba3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax -fno-builtin" } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl -fno-builtin" } */ #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c index 7a50b70..cb709b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */ #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c index 6843bc6..f00a02a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */ +/* { dg-additional-options "-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */ #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c index 39fb2a6..9db546d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin" } */ +/* { dg-additional-options "-std=c99 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=scalable -fno-builtin" } */ #include "vmv-imm-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c index 534d5fe..5635bb3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c index 537f135..3737568 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -lm" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -mrvv-vector-bits=scalable -lm" } */ #include #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c index 6874a3d..5880ccc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */ #include "vec-avg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c index 06f35e1..916f33d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable" } */ #include "vec-avg-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c index b6cbb10..677ac4f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c index 28aacb9..cc18f76 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c index 6d39bff..331fea4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c index 1f50fd2..cc60e5a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -O3 -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c index 9fcdae5..48aaf19 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c index d070be2..4c517c9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c index 65e9828..1718fd3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c index e744c3d..fee3872 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c index b79438c..91dd98d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c index dc98161..d9431ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c index 4ab08b2..340e692 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c index d63aaa1..3506660 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c index 5a38f43..9356e2b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c index 7c7f1c6..4aab746 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c index 9ded3cd..450250a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c index 66183e7..276765a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c index 1f42761..c4bc401 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c index 977d9de..ea40357 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c index 5d93a0ed..407b169 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c index 1a496bc..00f9dff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c index 4d2f7cc..58ee650 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c index 8075646..213c4d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh_zvl128b -mabi=lp64d -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math" } */ #include #define TEST_TYPE(TYPE1, TYPE2, N) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c index 7ae5080..4f0888c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include #define TEST_TYPE(TYPE1, TYPE2) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c index a922aa7..fd99a5d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */ #include #define TEST_TYPE(TYPE1, TYPE2, N) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c index 40352a5..9b468df 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "widen_reduc_order-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c index 3552f2f..3c46672 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "widen_reduc_order-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c index f003420..641efc4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model" } */ #include "widen_reduc-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c index f20a892..4437159 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c index cabb011..bbb0faf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-10.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c index fc9c69c..41211a3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-11.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c index 324a39b..af94188 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-12.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c index cb755c1..5495a07 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c index a0887fc..18772ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c index 3c21b24..9bf6d71 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include #include "widen-4.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c index 52bd00c..c7e8cdd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c index 566341e..34c7b02 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c index c6bbf4f..ec65507 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c index f7dbc06..50683eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c index 042bc5b..478e1d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-9.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable" } */ #include #include "widen-9.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c index 41c5734..6b12934 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c index 99ceef0..e142527 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-10.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c index cec71f9..a8afbc5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-11.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c index 4afdcba..707feb4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-12.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c index ffb8d7f..132c8c2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-2.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c index 5c23112..8ed4ce5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-3.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c index a91a516..ab7c6d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-5.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c index 5b7f000..660272c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-6.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c index f01efa3..972330d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-7.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c index ed79ac8..4cee4b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v && riscv_zvfh } } } */ -/* { dg-additional-options "--param=riscv-autovec-preference=scalable -ffast-math" } */ +/* { dg-additional-options "-mrvv-vector-bits=scalable -ffast-math" } */ #include #include "widen-8.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c index ab57e89..66b4dc6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c index 7cdc174..34fb439 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c index 5654a34..a2d38a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c index 867b4e8..041e07f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c index 1a4362b..3106f97 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c index 7f499be..bc1fc0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl -fno-vect-cost-model -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c index d22eb15..7b834ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c index 54d82a8..e50af33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c index 6119a10..89980c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c index fd85203..2d01b2b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32f_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c index d23de3e..c09d50d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c index 1602f5f..2b242c1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c index 5cc8f14..8b054b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c index 74825c4..335bb0c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c index c477a96..010078c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c index 2de09a2..143c529 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c index 8096c28..98fadb6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c index 9a133d1..8896895 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c index 0030349..ae4eb24 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c index 8809a40..db17f9d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve32x_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c index 94d88cc..58c30e8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c index 95d54d7..a0e6d2e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c index 6a23713..34d34e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c index 013af76..d5d3381 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c index e13c27d..51339a6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c index 2042996..14cd9cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c index 9cfcdf1..6d4fd4e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c index e0c0aea..b8294c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c index b823e63..1b38f9d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c index 6824b74..f18109a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64d_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c index 87f3b2f..35da49d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c index f9f44a9..7ffb19b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c index a4618e0..2dfcc6d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c index cc4fabd..3908170 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c index e767629..f710b54 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c index 64caef5..eb6449e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c index 5f9acbb..a4616cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c index b3debc7..47337d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c index 5f9acbb..a4616cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c index 6e99d37..658a95e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64f_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c index 64fbe45..c74645c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c index 12703a7..7c25e17 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c index a30e733..d7ee31f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c index b3d17c4..79622c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x_zvl1024b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c index fc676a3..e134ca7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c index b98a870..bc7cb70 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d -fno-vect-cost-model -mrvv-vector-bits=zvl -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c index b110771..8a0bfc0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x_zvl2048b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c index 509d75d..f81f02b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x_zvl256b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c index 0410eba..95e0fbb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x_zvl4096b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c index 2af91a2..8eddce0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details" } */ +/* { dg-options "-march=rv32gc_zve64x_zvl512b -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-vect-details" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c index 1c41790..bf1c5f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv_zvfhmin -mabi=ilp32d --param riscv-autovec-preference=scalable -ffast-math -fdump-rtl-final" } */ +/* { dg-options "-march=rv32gcv_zvfhmin -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math -fdump-rtl-final" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c index dc9a9bb..638e90f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c index 552f9e7..380d0c1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d -mrvv-vector-bits=zvl" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c index 9efe258..25b34ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c @@ -50,7 +50,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) Use extern here so that we get a known alignment, lest DATA_ALIGNMENT force us to make the scan pattern accomodate code for different alignments depending on word size. -** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-preference=fixed-vlmax" } } } +** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" "-mrvv-vector-bits=zvl" } } } ** lui\s+[ta][0-7],%hi\(a_a\) ** addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) ** lui\s+[ta][0-7],%hi\(a_b\) @@ -62,7 +62,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */ /* -** f3: { target { { any-opts "-mcmodel=medlow --param=riscv-autovec-preference=fixed-vlmax" "-mcmodel=medlow -march=rv64gcv_zvl512b --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } } +** f3: { target { { any-opts "-mcmodel=medlow -mrvv-vector-bits=zvl" "-mcmodel=medlow -march=rv64gcv_zvl512b -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } } ** lui\s+[ta][0-7],%hi\(a_a\) ** lui\s+[ta][0-7],%hi\(a_b\) ** addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\) @@ -73,7 +73,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */ /* -** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } +** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" "-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts "-mrvv-vector-bits=zvl" } } } ** lui\s+[ta][0-7],%hi\(a_a\) ** lui\s+[ta][0-7],%hi\(a_b\) ** addi\s+a4,[ta][0-7],%lo\(a_b\) @@ -85,7 +85,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */ /* -** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-preference=fixed-vlmax" } } } +** f3: { target { { any-opts "-mcmodel=medany" } && { no-opts "-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl1024b" "--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m8" "--param=riscv-autovec-lmul=m4" "-mrvv-vector-bits=zvl" } } } ** lla\s+[ta][0-7],a_a ** lla\s+[ta][0-7],a_b ** vsetivli\s+zero,16,e32,m8,ta,ma @@ -105,7 +105,7 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l) */ /* -** f3: { target { { any-opts "-mcmodel=medany --param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" } } } +** f3: { target { { any-opts "-mcmodel=medany -mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" } } } ** lla\s+[ta][0-7],a_a ** lla\s+[ta][0-7],a_b ** vl(1|2|4)re32\.v\s+v\d+,0\([ta][0-7]\) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c index f1914a3..1161ccb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c @@ -8,7 +8,7 @@ typedef struct { char c[32]; } c32; typedef struct { short s; char c[30]; } s16; /* A short struct copy can use vsetivli. -** f1: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } +** f1: { target { no-opts "-mrvv-vector-bits=zvl" } } ** vsetivli\s+zero,16,e8,m(1|f8|f2|f4),ta,ma ** vle8.v\s+v1,0\(a1\) ** vse8.v\s+v1,0\(a0\) @@ -16,7 +16,7 @@ typedef struct { short s; char c[30]; } s16; */ /* -** f1: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } +** f1: { target { { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } ** vl1re8.v\s+v1,0\(a1\) ** vs1r.v\s+v1,0\(a0\) ** ret @@ -28,7 +28,7 @@ void f1 (c16 *a, c16* b) } /* A longer one needs li. -** f2: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } +** f2: { target { no-opts "-mrvv-vector-bits=zvl" } } ** li\s+[ta][0-7],32 ** vsetvli\s+zero,[ta][0-7],e8,m(f4|f2|1|2|8),ta,ma ** vle8.v\s+v(1|2|8),0\(a1\) @@ -37,7 +37,7 @@ void f1 (c16 *a, c16* b) */ /* -** f2: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } +** f2: { target { { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } ** vl2re8.v\s+v2,0\(a1\) ** vs2r.v\s+v2,0\(a0\) ** ret @@ -49,7 +49,7 @@ void f2 (c32 *a, c32* b) /* A 32 byte struct is still short enough for vsetivli if we can use an element width larger than 8. -** f3: { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } +** f3: { target { no-opts "-mrvv-vector-bits=zvl" } } ** vsetivli\s+zero,16,e16,m(f2|f4|1|2|8),ta,ma ** vle16.v\s+v(1|2|8),0\(a1\) ** vse16.v\s+v(1|2|8),0\(a0\) @@ -57,7 +57,7 @@ void f2 (c32 *a, c32* b) */ /* -** f3: { target { { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } +** f3: { target { { any-opts "-mrvv-vector-bits=zvl" } && { no-opts "-march=rv64gcv_zvl1024b" "-march=rv64gcv_zvl256b" "-march=rv64gcv_zvl512b --param=riscv-autovec-lmul=dynamic" } } } ** vl2re16.v\s+v2,0\(a1\) ** vs2r.v\s+v2,0\(a0\) ** ret diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c index 1e11ac0..2ca585d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-3.c @@ -3,5 +3,5 @@ #include "cpymem-strategy.h" -/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */ -/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */ +/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "-mrvv-vector-bits=zvl" } } } } */ +/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "-mrvv-vector-bits=zvl" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c index 6bbcb54..61b6cbb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-strategy-4.c @@ -3,5 +3,5 @@ #include "cpymem-strategy.h" -/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */ -/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "--param=riscv-autovec-preference=fixed-vlmax" } } } } */ +/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 4 { target { no-opts "-mrvv-vector-bits=zvl" } } } } */ +/* { dg-final { scan-assembler-times {v[ls]+e[0-9]+\.v\tv[0-9]+\,0\([a-z0-9]+\)} 2 { target { any-opts "-mrvv-vector-bits=zvl" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c index 9920a24..23a1233 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zbb --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */ +/* { dg-options "-march=rv64gcv_zbb -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c index ccdd6d4..1b528d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */ +/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c index 89e43cd..bea91b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */ +/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c index cb0ea58..9a289fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */ +/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c index c043761..af9a301 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3" } */ +/* { dg-options "-march=rv64gcv -mrvv-vector-bits=zvl -ffast-math -mabi=lp64 -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c index 0f128ac..1f2b027 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/poly-selftest-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -fself-test=$srcdir/selftests --param=riscv-autovec-preference=fixed-vlmax -S" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O0 -fself-test=$srcdir/selftests -mrvv-vector-bits=zvl -S" } */ /* Verify that -fself-test does not fail on a non empty source. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c index ca974da..696be49 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c index 561b62c..9fbf60d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110119-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-march=rv64gczve32x -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c index 2514869..8265105 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-0.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c index 7bb5a6f..682d3e9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c index a4c8bc6..215eb99 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c index 71f5696..73a9f51 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c index e932d46..bec9b28 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c index 8b12f9d..c897805 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c index 5290527..5604ca2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c index f69fcbd..9c64844 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c index fb09ffc..0bb2260 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c index 2d99c6f..1ad588f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c index 7216631..5b28863 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr111720-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -ftree-vectorize -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c new file mode 100644 index 0000000..2070846 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */ + +#include "riscv_vector.h" + +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */ +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c new file mode 100644 index 0000000..54c86ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */ + +#include "riscv_vector.h" + +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */ +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c new file mode 100644 index 0000000..9c9aceb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c @@ -0,0 +1,9 @@ +/* Test that we do not have error when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */ + +void test_rvv_vector_bits_zvl (int *a, int *b, int *out) +{ + for (int i = 0; i < 8; i++) + out[i] = a[i] + b[i]; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c new file mode 100644 index 0000000..9589bf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c @@ -0,0 +1,9 @@ +/* Test that we do not have error when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */ + +void test_rvv_vector_bits_zvl (int *a, int *b, int *out) +{ + for (int i = 0; i < 8; i++) + out[i] = a[i] + b[i]; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c new file mode 100644 index 0000000..1f03bbc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */ + +#include "riscv_vector.h" + +void test_rvv_vector_bits_zvl () +{ + vint32m1_t x; + asm volatile ("def %0": "=vr"(x)); + asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); + asm volatile ("use %0": : "vr"(x)); +} + +/* { dg-final { scan-assembler-not {csrr\s+[atx][0-9]+,\s*vlenb} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c new file mode 100644 index 0000000..ea76209 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */ + +#include "riscv_vector.h" + +void test_rvv_vector_bits_scalable () +{ + vint32m1_t x; + asm volatile ("def %0": "=vr"(x)); + asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); + asm volatile ("use %0": : "vr"(x)); +} + +/* { dg-final { scan-assembler-times {csrr\s+[atx][0-9]+,\s*vlenb} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c index 8f352db..57e3473 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=zvl" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c index 5a94a51..d984293 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ float f[12][100]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c index 116b5b5..5d2902b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ void foo (int *src, int *dst, int size) { int i; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c index 1b4bfd9..f1d3cc8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl" } */ #include "riscv_vector.h" void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c index 1912a24..f3dfc53 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d -mrvv-vector-bits=zvl" } */ void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c index 884e834..d8ccaac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */ +/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d -mrvv-vector-bits=scalable" } */ void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC does not support VLEN > 4096bit for 'V' Extension" } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 1ceb10c..fe404c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -42,7 +42,7 @@ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ "-O3 -ftree-vectorize" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls/*.\[cS\]]] \ - "-O3 -ftree-vectorize --param riscv-autovec-preference=scalable" $CFLAGS + "-O3 -ftree-vectorize -mrvv-vector-bits=scalable" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/struct/*.\[cS\]]] \ "" "-O3 -ftree-vectorize" @@ -93,30 +93,30 @@ foreach op $AUTOVEC_TEST_OPTS { # VLS-VLMAX tests dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls-vlmax/*.\[cS\]]] \ - "-std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax" $CFLAGS + "-std=c99 -O3 -ftree-vectorize -mrvv-vector-bits=zvl" $CFLAGS # gather-scatter tests set AUTOVEC_TEST_OPTS [list \ - {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O3 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=dynamic -ffast-math} \ - {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O2 --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=dynamic -ffast-math} \ - {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O3 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \ - {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \ - {-ftree-vectorize -O2 --param riscv-autovec-preference=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ] + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \ + {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O2 -mrvv-vector-bits=zvl --param riscv-autovec-lmul=dynamic -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} \ + {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m1 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m2 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m4 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=m8 -fno-vect-cost-model -ffast-math} \ + {-ftree-vectorize -O2 -mrvv-vector-bits=scalable --param riscv-autovec-lmul=dynamic -ffast-math} ] foreach op $AUTOVEC_TEST_OPTS { dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/gather-scatter/*.\[cS\]]] \ "" "$op" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c index 70eb5d7..727e704 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c index d98d965..981183c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c index 799e29b..fd07603 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c index 36de289..9d36388 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c index 00e1931..a231fb1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c index 4c43ae0..7516a33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c index a5b576a..47dafe6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c index 48abfd1..b4bca35 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c index 844d1fc..6f3527f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c index da69a5b..2ec94b2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c index 1d1bf10..5f2ef67 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c index a3ffc3c..81fd011 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c index ea91076..f7a47e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c index e605331..21bc072 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c index 024087a..5539486 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c index 85a59f8..267ade0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c index 6e07988..2172193 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c index 567e50a..0379429 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ int d0, sj, v0, rp, zi; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c index 4ef4c51..f71386c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c index 248e80a..46fa911 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c index 04bb681..87e6056 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-100.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c index ba341c7..fdc48e9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-101.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c index 739c550..a2d6955 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c index c9c4c92..95b28b3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-103.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c index 9c2fa0a..e90403f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c index 3f0a6be..f181614 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c index b21adc0..eb0fdb1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c index 7b8acc2..bb6616f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c index 325bc59..80ef8f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c index f99126c..12c87ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c index 37ac5da..ea25376 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c index ca5ffad..8184f27 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c index 33e9572..0160575 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c index 2c9a896..88f218c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c index 135cdbf..3f42bf6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c index 7b8ec62..0c9633f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c index 5e0906f..5a429ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c index b73ef38..6fb09ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c index a2ba509..d814b31 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c index 721ae13..430df63 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c index 8af7265..dcc58eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c index d461781..3a64b3b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c index 9939834..b3a57a3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-22.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c index eacebe3..158be6e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-23.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c index a2d0eca..89d41f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-24.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c index c19958c..c517871 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-25.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c index 769673a..cd9a5c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c index 1d422e9..20916e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-27.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c index 386fb5b..04a2430 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-28.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c index 652d3eb..d6e93293 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-29.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c index 754f426..76cd102 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c index 305caf3..265deca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-30.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c index 3defd39..41b1c66 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-31.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c index 370171b..b22f6f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c index 43ee066..d079346 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-33.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c index 6d63a8b..28c4eb4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-34.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c index 8fdadff..498354c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-35.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c index 1db27d8..35cad2d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c index 092e2aa..cd3e961 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c index 9f5896b..4bdc127 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-38.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c index d278db5..fa5f3c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c index 1f4d784..cf2ece8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c index 926dc63..142511c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-40.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c index 4dedf36..99c1722 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c index 86c51f9..70016b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-42.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c index 8f22056..ead7a40 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-43.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c index 5b7582b..f689739 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-44.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c index 8b02f99..5b11d76 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-45.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c index 0f0feec..db4e3fd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-46.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c index 5c451d3..da007d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-47.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c index 921a6d2..52d3640 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-48.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c index 67f3d45..f955574 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-49.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c index 9aa0c99..0b0c12f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c index 786d5d6..33e6007 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-50.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c index 3f4ee86..23c459f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-51.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c index 69c89a7..f2a9d7c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-52.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c index 645cf06..65435ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-53.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c index c8bba03..e23fca1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-54.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c index e9fbc73..2006144 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-55.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c index f5a02fe..5db1a40 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c index 2eb6e43..cd58b60 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-57.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c index 6f57200..7452982f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-58.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c index 9ea60a1..41c8b00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-59.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c index a928e46..b6776cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c index d156c39..a057ae3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-60.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c index 5bffa37..c7897ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-61.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c index e196906..7c66d74 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-62.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c index 0e62ad3..5bbd554 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-63.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c index 290e941..0eb9af9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-64.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c index 775f72f..f0750d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-65.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c index 9cc630c..6e99546 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c index 2a2c35a..3f22fc8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c index 632d464..bf95e1c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c index 369961f..31e19d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-69.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c index 8e82034..c756ac8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c index acd96f6..0a8d4e8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-70.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c index e945882..07a64b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c index 0c00da4..cbbaaff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c index 7360c87..caec9ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-73.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c index fb7d874..116737f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-74.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c index 9198a62..9e1a92f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-75.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c index d7975b9..fcfc3ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c index a638d21..261879f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c index 5d9778d..920b30a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-78.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c index 5bb00de..d53f515 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-79.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c index 718abcf..d846491 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c index 5ea4757..a2f934e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-80.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c index be0787d..c1e6e9a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-81.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c index 0cdd656..707beda 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c index dd39a65..6e64712 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c index 91c899c..9f9aafc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-84.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c index b513beb..5eccae4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-85.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c index 9a4217f..14b934ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c index 0b22c04..eebc490 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-87.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c index ff0f746..c98dbdc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c index bdd74d6..51de91f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-89.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c index a81ed65..000d8fb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c index 1c98ec5..82db207 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c index c39fea4..d8b5d6f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c index 1ff85ad..d4ab9f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c index 1701f6b..5545696 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-93.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c index d36d69f..ea94329 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-94.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c index a075688..a43af9b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-95.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c index abe54e8..b6c9dac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-96.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c index 6e62419..79487d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-97.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c index 7aab0e0..7203d53 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-98.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c index 7a06d70..d1cff47 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-99.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c index 5b4bd43..821c1ea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/dump-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fdump-rtl-vsetvl-details" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c index 5e87191..f314c19 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c index 211a1c5..b43c6ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c index 6113e36..b4f7cc4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c index d893492..0bbf8d8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c index 78c785a..cf87fbc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c index 0cf6c4f..4808071 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c index 19044ea..ed51378 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c index e540e96..421de63 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c index 7afac64..aee6843 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c index 9097f72..b8c5db9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c index 28c6d35..05794d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c index ac65a12..399339a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c index e9273f0..3b02aaf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c index d22aef6..d1123e5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c index 3189929..3e25d4c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c index 381589e..b97ee42 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c index b3d2907..acb4443 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c index 9ca53ab..78d2eba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c index 82872f1..77fdcd4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c index 22645c0..03010f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c index 55419d2..ebf52de 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c index a82f76b..295b435 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c index 48ba536..163c88b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c index 611c35a..635642f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c @@ -1,7 +1,7 @@ #include "riscv_vector.h" /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c index e198892..cee9e36 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c index a045681..b6336f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c index 79061f4..138f1a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c index 3945dca..90e5a89 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c index 7266c59..d413fe3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c index 9a02380..563398a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c index cceabd7..f1ddf9a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c index 185f971..879afdc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c index 48ec42d..b9d1d3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c index 8a601c1..46b79ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c index 80dfbff..05604f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c index e2bac85..b55f74a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c index 784ff3c..50874c9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c index ade612b..6303935 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c index 7ae5c5a..6e51078 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c index 1b7ce74..7f225f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c index b6c5bcd..ccba3ad 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c index bcdbe75..fed6151 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c index 6477daf..1ceadd7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c index 79d2eb8..7310487 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-move-loop-invariants" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c index 642a089..1a5bb93 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c index a476994..4f7a9d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c index 5fa6c8b..32c4f03 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c index e8a1fd0..927ea1f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c index c92e59e..9289059 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c index 19bee67..8564184 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c index 4fab8e4..946dc88 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr108270.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c index 1daba8f..e7de576 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109399.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c index 0ddb261..995f8d2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109547.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c index 33a073a..082499d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109615.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c index 273eb43..99018d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c index 7fe7be6..bbb2174 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c index 3f06b6e..04fe318 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c index 87ec80e..e64f294 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109743-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c index 9bb1302..4e3845f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109748.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c index 7848ff2..9738fe7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c index 80e9abc..e0abb7b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c index 0efd15b..3e4a821 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109974.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zbb -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv_zbb -mabi=ilp32d -mrvv-vector-bits=zvl -O3" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c index 64ca51b..803ce57 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c index 71d2c9a..85a3b91 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3" } */ #include "pr111037-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c index 5e1859c..c8124c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c index 76dd7cb..5949085 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c index d8f2cbd..871cf65 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c index a19d920..91bd4ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c index 61dcc53..01eec56 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111927.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c index 14192be..54498e8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111947.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O2 -Wno-implicit-int" } */ char *a; b() { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c index 7722751..9aa932e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c index 727b2db..5fe42d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112092-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c index 06e4b2d..39b5d5f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c index 2cae1b4..231bf21 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112713-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c index b60853d..8d303f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112776.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c index c0a6bf2..5108c9d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112813-1.c @@ -1,6 +1,6 @@ /* Test that we do not have ice when compile */ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv_zvl256b -mabi=ilp32d -O3" } */ int a, c, d, f, j; int b[7]; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c index c3ecbf8..86d65dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112929-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ int printf(char *, ...); int a, l, i, p, q, t, n, o; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c index 27f0b18..63817f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr112988-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ int a = 0; int p, q, r, x = 230; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c index b3b5061..d952813 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113248.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mtune=generic-ooo --param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ +/* { dg-options "-mtune=generic-ooo -mrvv-vector-bits=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c index 5d7c5f5..568560b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c index bb01691..bfa81ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c index 3b42566..4ba8160 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c index e8551ec..f40f75e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c index 50d8d0d..18daacc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c index 44a0700..0d1e400 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c index e702c5e..e10f12e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c index 9d037f6..5407483 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c index 899df3e..e2963dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c index f19897a..aa18c3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c index 3a033bb..81eba9e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c index 2b9fbd2..a7c1478 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c index b5a02c0..7f7e228 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c index f19897a..aa18c3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c index 9c0c319..5f770ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c index e293d86..dc012c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c index f227e5c..18700d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c index df6e16e..bd52573 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c index 71a608f..c2284c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c index 8373067..a0a5be3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c index fb12365..ffa95f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c index f4f0e52..d997762 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c index 7e01b81..2b3722d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c index 93ec13a..af46a81 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c index 9b0d88d..131bb18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c index ee321fc..f0a4fa7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c index 5615cb1..ee29135 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c index c906b15..e9ee058 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c index 8c4c47e..7fbec5e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c index 99dbbba..4de390c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c index 40bff0f..6832209 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c index 857dc3a..3e0f290 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c index b067f9b..3372f04 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c index eeacb8e..950c0f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c index 75ef23f..49f31ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c index b639251..797afbb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c index bea7ede..bea9fbc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c index 5a361b5..018e7aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c index f0e0ff6..f38353b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c index 5e562fa..8fa74c9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c index 9dc954a..0623b54 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c index fddaeae..9e3dc44 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c index b353b06..f8f69bd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c index 80a8046..798c321 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c index d9965ca..8e61389 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c index 0e84394..15e82e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c index 95a227b..d1a6a94 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c index d6b6a2b..bf8440e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c index 9e01bffd..13d1d29 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c index f9f2420..8fe51a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c index ecacd4b..50b54ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c index fd4f6d5..391581d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c index 4436cd9..0520463 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c index 16b2c32..d394244 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c index 12bb03d..e25d33b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c index 0eadad1..d7f6d18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c index 8679fab..1354c5e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c index 9130d1c..6366dd9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c index 18e41b9..bbe7785 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c index 394553d..bbff028 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c index 048087f..b76226b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c index 1a4fdb1..7481b23 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c index 9247589..56415a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c index 9e811a9..4befbde 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c index 738b53f..0a467ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c index 0cbc6a4..ac5e015 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c index e7846f0..a69193a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c index 9b2b0ae..da9b367 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c index c0735a5..7d014ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c index cb90750..e4b60b5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c index a63eae7..3cf9023e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c index 607c802..51b199b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c index 48f3cdf..97713d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c index 610c944..972fb6d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c index 7ea1218..9e158c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c index 25fc05c..d09065d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c index cc4fbba..35bd9f1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c index ebbaafc..6c7c063e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c index e52a55e..f2034c0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c index 0341845..48fed4e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c index 85686e8..c9bd447 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c index 0b03e75..24c6bb8b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c index d72414f..b7a715c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c index 2a55f2d..ddc3f2c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c index eb2a710..b96f267 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c index 7a4b0a7..9914507 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c index 0dbda08..7d490c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c index 66e1b73..2c8d367 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c index dedbc94..bf8d8b8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c index 26db192..8772aab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c index bb2ca39..56956eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c index 293b109..284423b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c index ddc293b..cf244f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c index 87ea397..1c12d48 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c index d296fe6..b73cfb0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c index 510e0de..8a4a7c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c index f5a9f6a..3a16406 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c index 73eb9c7..e018649 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c index c925bcf..ef02f6b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c index 94325b4..dc8bba6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c index 9de3aa3..14dc2d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c index 9ed3bfd..c84230d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c index ef3f76a..ae34783 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c index 302b2f6..0572b72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c index 1dd7933..3e5ee3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c index 756036e..51d22b2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c index a5d6c9a..6d238e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c index ffbe7c8..f6f55be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c index 0c5a119..7e4afbb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c index b1faaee..c7c8b6a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c index b80bdde..8094807 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c index c0b8b4c..231b86b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c index 5366b8b..2c9f916 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c index 3a3e9bc..f78180a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c index 181d0e7..420eea4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c index 8c67890..66129ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c index 597e066..44ff89a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c index 02a08cc..16b52c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c index b6cf5ab..1021c1e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c index c7fec26..4490e20 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c index a89c1d5..68f1093 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c index f39b32c..1751a2b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c index 6f61bb6..723a1c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c index b42c2b2..f2dab3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c index 8caeed7..94fb31f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c index d129caf..1805bcd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c index 830739d..68d0af7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c index e4ff921..89c785e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c index f8e6ed5..af4ba3c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c index 225749f..a081dda 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c index 1f27a6b..e27c76c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c index e91a4e4..16c8fd9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c index d0a920f..af0df89 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c index 27e7892..69c6423 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c index 8d37f7b..78d8e9d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c index a3817a3..993e420 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c index 369850a..d1547c9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c index a8c404d..836619f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c index ef691dd..e61bb9c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c index 1345fa0..b4b4c66 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c index d6cbb2b..0910b0c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c index 364bd69..661e5c0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c index 5b26167..8cbbfab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c index 4cbfc67..10df345 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c index 7a28e84..fb7197a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c index 8ca376e..6683374 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c index 4291d8d..7066d77 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c index 3e6599d..4528900 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c index e767b12..4d1acf9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c index 0d5183e..5bfc659 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c index e452d85..5ba8cc2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c index 7503fbe..42c0d55 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c index 6b3439a..501a715 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c index 3a739e2..e4d7f38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c index ac0204f..bf038bc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c index 4a903cf..d7378f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c index 9fb73cf..fcff488 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c index e44537e..80d4eb3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c index 006df7e..9a3c60f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c index cc6d822..35c5ac3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c index 9704e444..7a20223 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c index b2f967b..04bfe69 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c index 31ebc13..2496773 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c index bac607b..10f5949 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c index a620523..7918c4e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c index 9c293dd..1bc8398 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c index 355a030..1c02d03 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c index 85668d0..c21439e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ /* Test insert-vsetvl PASS whether it's able to eliminate vsetvl for same vtype in VLMAX. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c index 71a0ccc..ff5437e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c index adb14e5..7dcbc3d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -O3" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c index d3a060f..4ab8d0c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c index bd1d9b2..a3a9ac2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c index 1ef0bf8..1f13e86 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c index 518c747..ac332a7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c index 1400e67..7f02d9b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c index 4824b75..283d2cf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c index b798852..6985c47 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c index d314122..87a2a08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c index 476735d..454c4a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c index c7b7db3..1490fb6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c index 80ff75f..c95f0dc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c index e2deea7..e277d31 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c index 0671bce..a48bce0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c index 1bac9fd..bdea9a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c index 8dddd88..449e46c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c index c6b39aa..1165c9a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c index 8ba5680..21fef46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c index 127dc7f..ac29887 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c index 127dc7f..ac29887 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c index e19e869..1cccb98 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c index 90eca5b..7c8d122 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c index 17b217b..12ab77e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c index 17b217b..12ab77e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ // PR113249 /* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c index be31df1..e6c5b09 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c index 9a55309..4273d2c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c index 81bb251..f576b17 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c index 6fe2813..48ddad9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c index 765ac30..a290da4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c index 992c2a1..dfba731 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c index d218d04..610727b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c index d06203a..54e3236 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c index fb05c11..4b88075 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c index ee1501e..59a5fb3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c index 1544f02..30269ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c index 810f9f3..3934164 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c index 854568f..c0147b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c index c134f55..cd67dca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c index f519cd4..be14365 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c index e2b84d6..79e58dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c index 493ef97..7096159e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c index a7539b5..71b934e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c index bfa798f..5fc1938 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c index 6e1e44f..c267674 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c index 4e6cc90..27bc5c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c index 762558f..b3e3e4d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c index 0b659fd..2bdc957 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c index ef7d022..4f0d003 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c index 2cd966e..703e47e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=fixed-vlmax -O2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64 --param=riscv-autovec-lmul=m8 -mrvv-vector-bits=zvl -O2" } */ struct a_struct { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c index 1b9f4d8..5665a23 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-lmul=m4 -O3 -fomit-frame-pointer -funroll-loops" } */ int safe_lshift_func_int32_t_s_s_left, safe_lshift_func_int32_t_s_s_right, safe_sub_func_uint64_t_u_u_ui2, safe_mul_func_uint64_t_u_u_ui2, g_79_2, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c index f340364..a5d8932 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c index 98eacc1..865746b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-vsetvl-details" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -fdump-rtl-vsetvl-details" } */ #include "riscv_vector.h" void diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c index bec3928..7483659 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c index be50905..b49766e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c index 3cf6b16..69996eb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c index b9b6f26..76450f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c index 65a8415..42bf2b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c index 08fd74f..84d7938 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c index 0143aa1..2304246 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c index fe44fb3..ea6417b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c index 7d1f2e1..7f0462f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c index de4ba0a..cbc414b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c index 91c2a4f..7e06d30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c index 975ba97..3df00d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c index bfe575e..f2642f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c index 466f3a8..42b7fe3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c index 5acc2ac..3228a75 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c index b2e3382..f7c139d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c index 558690a..ca9b54b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c index a679f54..cafa89f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c index d350752..6375639 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c index be50905..b49766e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c index d36560b..5c21ad0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O3" } */ #include -- cgit v1.1 From 4547628c78618616595f4b5e1bef2b582c77793d Mon Sep 17 00:00:00 2001 From: xuli Date: Fri, 1 Mar 2024 09:10:12 +0000 Subject: RISC-V: Add riscv_vector_cc function attribute Standard vector calling convention variant will only enabled when function has vector argument or returning value by default, however user may also want to invoke function without that during a vectorized loop at some situation, but it will cause a huge performance penalty due to vector register store/restore. So user can declare function with this riscv_vector_cc attribute like below, that could enforce function will use standard vector calling convention variant. void foo() __attribute__((riscv_vector_cc)); [[riscv::vector_cc]] void foo(); // For C++11 and C23 For more details please reference the below link. https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 gcc/ChangeLog: * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc attribute to riscv_attribute_table. (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function. (riscv_fntype_abi): Add riscv_vector_cc attribute check. * doc/extend.texi: Add riscv_vector_cc attribute description. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C: New test. * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c: New test. * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c: New test. --- gcc/config/riscv/riscv.cc | 55 ++++++++++++++++++---- gcc/doc/extend.texi | 10 ++++ .../rvv/base/attribute-riscv_vector_cc-error.C | 21 +++++++++ .../base/attribute-riscv_vector_cc-callee-saved.c | 30 ++++++++++++ .../rvv/base/attribute-riscv_vector_cc-error.c | 11 +++++ 5 files changed, 119 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c (limited to 'gcc') diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9f64f67..56cd8d2 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -537,24 +537,52 @@ static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); /* Defining target-specific uses of __attribute__. */ -TARGET_GNU_ATTRIBUTES (riscv_attribute_table, +static const attribute_spec riscv_gnu_attributes[] = { /* Syntax: { name, min_len, max_len, decl_required, type_required, function_type_required, affects_type_identity, handler, exclude } */ /* The attribute telling no prologue/epilogue. */ - { "naked", 0, 0, true, false, false, false, - riscv_handle_fndecl_attribute, NULL }, + {"naked", 0, 0, true, false, false, false, riscv_handle_fndecl_attribute, + NULL}, /* This attribute generates prologue/epilogue for interrupt handlers. */ - { "interrupt", 0, 1, false, true, true, false, - riscv_handle_type_attribute, NULL }, + {"interrupt", 0, 1, false, true, true, false, riscv_handle_type_attribute, + NULL}, /* The following two are used for the built-in properties of the Vector type and are not used externally */ {"RVV sizeless type", 4, 4, false, true, false, true, NULL, NULL}, - {"RVV type", 0, 0, false, true, false, true, NULL, NULL} -}); + {"RVV type", 0, 0, false, true, false, true, NULL, NULL}, + /* This attribute is used to declare a function, forcing it to use the + standard vector calling convention variant. Syntax: + __attribute__((riscv_vector_cc)). */ + {"riscv_vector_cc", 0, 0, false, true, true, true, NULL, NULL} +}; + +static const scoped_attribute_specs riscv_gnu_attribute_table = +{ + "gnu", {riscv_gnu_attributes} +}; + +static const attribute_spec riscv_attributes[] = +{ + /* This attribute is used to declare a function, forcing it to use the + standard vector calling convention variant. Syntax: + [[riscv::vector_cc]]. */ + {"vector_cc", 0, 0, false, true, true, true, NULL, NULL} +}; + +static const scoped_attribute_specs riscv_nongnu_attribute_table = +{ + "riscv", {riscv_attributes} +}; + +static const scoped_attribute_specs *const riscv_attribute_table[] = +{ + &riscv_gnu_attribute_table, + &riscv_nongnu_attribute_table +}; /* Order for the CLOBBERs/USEs of gpr_save. */ static const unsigned gpr_save_reg_order[] = { @@ -5425,6 +5453,16 @@ riscv_arguments_is_vector_type_p (const_tree fntype) return false; } +/* Return true if FUNC is a riscv_vector_cc function. + For more details please reference the below link. + https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */ +static bool +riscv_vector_cc_function_p (const_tree fntype) +{ + return lookup_attribute ("vector_cc", TYPE_ATTRIBUTES (fntype)) != NULL_TREE + || lookup_attribute ("riscv_vector_cc", TYPE_ATTRIBUTES (fntype)) != NULL_TREE; +} + /* Implement TARGET_FNTYPE_ABI. */ static const predefined_function_abi & @@ -5434,7 +5472,8 @@ riscv_fntype_abi (const_tree fntype) reference the below link. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389 */ if (riscv_return_value_is_vector_type_p (fntype) - || riscv_arguments_is_vector_type_p (fntype)) + || riscv_arguments_is_vector_type_p (fntype) + || riscv_vector_cc_function_p (fntype)) return riscv_v_abi (); return default_function_abi; diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index efd78014..6c2c7ae 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -6314,6 +6314,16 @@ Permissible values for this parameter are @code{user}, @code{supervisor}, and @code{machine}. If there is no parameter, then it defaults to @code{machine}. +@cindex @code{riscv_vector_cc} function attribute, RISC-V +@item riscv_vector_cc +Use this attribute to force the function to use the vector calling +convention variant. + +@smallexample +void foo() __attribute__((riscv_vector_cc)); +[[riscv::vector_cc]] void foo(); // For C++11 and C23 +@end smallexample + @end table The following target-specific function attributes are available for the diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C b/gcc/testsuite/g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C new file mode 100644 index 0000000..63a353b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O1" } */ + +[[riscv::vector_cc]] void foo();// For C++11 and C23 + +[[riscv::vector_cc]] int var; /* { dg-warning "'vector_cc' attribute only applies to function types" } */ + +void __attribute__((riscv_vector_cc)) func(); +void __attribute__((riscv_vector_cc(1))) func_invalid(); /* { dg-error "wrong number of arguments specified for 'riscv_vector_cc' attribute" } */ + +void test_no_attribute(int); +void __attribute__((riscv_vector_cc)) test_no_attribute(int x) { } + +class test_cc { + __attribute__((riscv_vector_cc)) void member_func(); +}; + +void test_lambda() { + __attribute__((riscv_vector_cc)) auto lambda = []() { /* { dg-warning "'riscv_vector_cc' attribute only applies to function types" } */ + }; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c b/gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c new file mode 100644 index 0000000..b47ecb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +void __attribute__((riscv_vector_cc)) bar1 (int a); +void bar2 (); + +void __attribute__((riscv_vector_cc)) +foo1 (int a) +{ + bar1 (a); +} + +void __attribute__((riscv_vector_cc)) +foo2 (int a) +{ + char data[1024]; + bar2 (); +} + +void +foo3 (int *a) +{ + bar1 (*a); +} + +/* { dg-final { scan-assembler-not {\.variant_cc\tbar2} } } */ +/* { dg-final { scan-assembler-not {\.variant_cc\tfoo3} } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tbar1} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tfoo1} 1 } } */ +/* { dg-final { scan-assembler-times {\.variant_cc\tfoo2} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c b/gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c new file mode 100644 index 0000000..ceb5e5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O1" } */ + +__attribute__((riscv_vector_cc)) int var; /* { dg-warning "'riscv_vector_cc' attribute only applies to function types" } */ +[[riscv::vector_cc]] int var1; /* { dg-warning "'vector_cc' attribute only applies to function types" } */ + +void __attribute__((riscv_vector_cc)) func(); +void __attribute__((riscv_vector_cc(1))) func_invalid(); /* { dg-error "wrong number of arguments specified for 'riscv_vector_cc' attribute" } */ + +void test_no_attribute(int); +void __attribute__((riscv_vector_cc)) test_no_attribute(int x) { } -- cgit v1.1 From f9c30ea737b806caac917d8f501305151a2cbd57 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 29 Feb 2024 09:22:19 +0100 Subject: middle-end/114070 - VEC_COND_EXPR folding The following amends the PR114070 fix to optimistically allow the folding when we cannot expand the current vec_cond using vcond_mask and we're still before vector lowering. This leaves a small window between vectorization and lowering where we could break vec_conds that can be expanded via vcond{,u,eq}, most susceptible is the loop unrolling pass which applies VN and thus possibly folding to the unrolled body of a vectorized loop. This gets back the folding for targets that cannot do vectorization. It doesn't get back the folding for x86 with AVX512 for example since that can handle the original IL but not the folded since it misses some vcond_mask expanders. PR middle-end/114070 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)): Allow the folding if before lowering and the current IL isn't supported with vcond_mask. --- gcc/match.pd | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/match.pd b/gcc/match.pd index f3fffd8..4edba7c 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -5153,7 +5153,13 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (op (vec_cond:s @0 @1 @2) (vec_cond:s @0 @3 @4)) (if (TREE_CODE_CLASS (op) != tcc_comparison || types_match (type, TREE_TYPE (@1)) - || expand_vec_cond_expr_p (type, TREE_TYPE (@0), ERROR_MARK)) + || expand_vec_cond_expr_p (type, TREE_TYPE (@0), ERROR_MARK) + || (optimize_vectors_before_lowering_p () + /* The following is optimistic on the side of non-support, we are + missing the legacy vcond{,u,eq} cases. Do this only when + lowering will be able to fixup.. */ + && !expand_vec_cond_expr_p (TREE_TYPE (@1), + TREE_TYPE (@0), ERROR_MARK))) (vec_cond @0 (op! @1 @3) (op! @2 @4)))) /* (c ? a : b) op d --> c ? (a op d) : (b op d) */ @@ -5161,13 +5167,19 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (op (vec_cond:s @0 @1 @2) @3) (if (TREE_CODE_CLASS (op) != tcc_comparison || types_match (type, TREE_TYPE (@1)) - || expand_vec_cond_expr_p (type, TREE_TYPE (@0), ERROR_MARK)) + || expand_vec_cond_expr_p (type, TREE_TYPE (@0), ERROR_MARK) + || (optimize_vectors_before_lowering_p () + && !expand_vec_cond_expr_p (TREE_TYPE (@1), + TREE_TYPE (@0), ERROR_MARK))) (vec_cond @0 (op! @1 @3) (op! @2 @3)))) (simplify (op @3 (vec_cond:s @0 @1 @2)) (if (TREE_CODE_CLASS (op) != tcc_comparison || types_match (type, TREE_TYPE (@1)) - || expand_vec_cond_expr_p (type, TREE_TYPE (@0), ERROR_MARK)) + || expand_vec_cond_expr_p (type, TREE_TYPE (@0), ERROR_MARK) + || (optimize_vectors_before_lowering_p () + && !expand_vec_cond_expr_p (TREE_TYPE (@1), + TREE_TYPE (@0), ERROR_MARK))) (vec_cond @0 (op! @3 @1) (op! @3 @2))))) #if GIMPLE -- cgit v1.1 From 270d0f69cffbfa81f61c5a6b7f7de2c5919703c7 Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Fri, 1 Mar 2024 13:33:44 +0100 Subject: AVR: Document valid ranges of -mfuse-add= gcc/ * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document valid values for level. --- gcc/doc/invoke.texi | 1 + 1 file changed, 1 insertion(+) (limited to 'gcc') diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 7862c75..dc5fd86 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -23792,6 +23792,7 @@ subroutines. Code size is smaller. Optimize indirect memory accesses on reduced Tiny devices. The default uses @code{@var{level}=1} for optimizations @option{-Og} and @option{-O1}, and @code{@var{level}=2} for higher optimizations. +Valid values for @var{level} are @code{0}, @code{1} and @code{2}. @opindex mdouble @opindex mlong-double -- cgit v1.1 From 5b1fb8f8b4fe60745dece9b2f83c155c772ca66d Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 1 Mar 2024 14:57:15 +0100 Subject: dwarf2out: Don't move variable sized aggregates to comdat [PR114015] The following testcase ICEs, because we decide to move that struct { char a[n]; } DW_TAG_structure_type into .debug_types section / DW_UT_type DWARF5 unit, but refer from there to a DW_TAG_variable (created artificially for the array bounds). Even with non-bitint, I think it is just wrong to use .debug_types section / DW_UT_type for something that uses DW_OP_fbreg and similar in it, things clearly dependent on a particular function. In most cases, is_nested_in_subprogram (die) check results in such aggregates not being moved, but in the function parameter type case that is not the case. The following patch fixes it by returning false from should_move_die_to_comdat for non-constant sized aggregate types, i.e. when either we gave up on adding DW_AT_byte_size for it because it wasn't expressable, or when it is something non-constant (location description, reference, ...). 2024-03-01 Jakub Jelinek PR debug/114015 * dwarf2out.cc (should_move_die_to_comdat): Return false for aggregates without DW_AT_byte_size attribute or with non-constant DW_AT_byte_size. * gcc.dg/debug/dwarf2/pr114015.c: New test. --- gcc/dwarf2out.cc | 9 +++++++++ gcc/testsuite/gcc.dg/debug/dwarf2/pr114015.c | 14 ++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr114015.c (limited to 'gcc') diff --git a/gcc/dwarf2out.cc b/gcc/dwarf2out.cc index 5d64100..03d73f9 100644 --- a/gcc/dwarf2out.cc +++ b/gcc/dwarf2out.cc @@ -8215,6 +8215,15 @@ should_move_die_to_comdat (dw_die_ref die) || is_nested_in_subprogram (die) || contains_subprogram_definition (die)) return false; + if (die->die_tag != DW_TAG_enumeration_type) + { + /* Don't move non-constant size aggregates. */ + dw_attr_node *sz = get_AT (die, DW_AT_byte_size); + if (sz == NULL + || (AT_class (sz) != dw_val_class_unsigned_const + && AT_class (sz) != dw_val_class_unsigned_const_implicit)) + return false; + } return true; case DW_TAG_array_type: case DW_TAG_interface_type: diff --git a/gcc/testsuite/gcc.dg/debug/dwarf2/pr114015.c b/gcc/testsuite/gcc.dg/debug/dwarf2/pr114015.c new file mode 100644 index 0000000..a184ab5 --- /dev/null +++ b/gcc/testsuite/gcc.dg/debug/dwarf2/pr114015.c @@ -0,0 +1,14 @@ +/* PR debug/114015 */ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-g -fvar-tracking-assignments -fdebug-types-section -w" } */ + +#if __BITINT_MAXWIDTH__ >= 236 +typedef _BitInt(236) B; +#else +typedef _BitInt(63) B; +#endif + +int +foo (B n, struct { char a[n]; } o) +{ +} -- cgit v1.1 From b5377928a2a5cd2a79eda59e2eba7d0511bf7566 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 1 Mar 2024 15:42:52 +0100 Subject: calls: Further fixes for TYPE_NO_NAMED_ARGS_STDARG_P handling [PR114136] On Tue, Feb 27, 2024 at 04:41:32PM +0000, Richard Earnshaw wrote: > On Arm the PR107453 change is causing all anonymous arguments to be passed on the > stack, which is incorrect per the ABI. On a target that uses > 'pretend_outgoing_vararg_named', why is it correct to set n_named_args to > zero? Is it enough to guard both the statements you've added with > !targetm.calls.pretend_outgoing_args_named? The TYPE_NO_NAMED_ARGS_STDARG_P functions (C23 fns like void foo (...) {}) have NULL type_arg_types, so the list_length (type_arg_types) isn't done for it, but it should be handled as if it was non-NULL but list length was 0. So, for the if (type_arg_types != 0) n_named_args = (list_length (type_arg_types) /* Count the struct value address, if it is passed as a parm. */ + structure_value_addr_parm); else if (TYPE_NO_NAMED_ARGS_STDARG_P (funtype)) n_named_args = 0; else /* If we know nothing, treat all args as named. */ n_named_args = num_actuals; case, I think guarding it by any target hooks is wrong, although I guess it should have been n_named_args = structure_value_addr_parm; instead of n_named_args = 0; For the second if (type_arg_types != 0 && targetm.calls.strict_argument_naming (args_so_far)) ; else if (type_arg_types != 0 && ! targetm.calls.pretend_outgoing_varargs_named (args_so_far)) /* Don't include the last named arg. */ --n_named_args; else if (TYPE_NO_NAMED_ARGS_STDARG_P (funtype)) n_named_args = 0; else /* Treat all args as named. */ n_named_args = num_actuals; I think we should treat those as if type_arg_types was non-NULL with 0 elements in the list, except the --n_named_args would for !structure_value_addr_parm lead to n_named_args = -1, I think we want 0 for that case. 2024-03-01 Jakub Jelinek PR middle-end/114136 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set n_named_args initially before INIT_CUMULATIVE_ARGS to structure_value_addr_parm rather than 0, after it don't modify it if strict_argument_naming and clear only if !pretend_outgoing_varargs_named. --- gcc/calls.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/calls.cc b/gcc/calls.cc index 01f44734..21d78f9 100644 --- a/gcc/calls.cc +++ b/gcc/calls.cc @@ -2938,7 +2938,7 @@ expand_call (tree exp, rtx target, int ignore) /* Count the struct value address, if it is passed as a parm. */ + structure_value_addr_parm); else if (TYPE_NO_NAMED_ARGS_STDARG_P (funtype)) - n_named_args = 0; + n_named_args = structure_value_addr_parm; else /* If we know nothing, treat all args as named. */ n_named_args = num_actuals; @@ -2970,14 +2970,15 @@ expand_call (tree exp, rtx target, int ignore) we do not have any reliable way to pass unnamed args in registers, so we must force them into memory. */ - if (type_arg_types != 0 + if ((type_arg_types != 0 || TYPE_NO_NAMED_ARGS_STDARG_P (funtype)) && targetm.calls.strict_argument_naming (args_so_far)) ; else if (type_arg_types != 0 && ! targetm.calls.pretend_outgoing_varargs_named (args_so_far)) /* Don't include the last named arg. */ --n_named_args; - else if (TYPE_NO_NAMED_ARGS_STDARG_P (funtype)) + else if (TYPE_NO_NAMED_ARGS_STDARG_P (funtype) + && ! targetm.calls.pretend_outgoing_varargs_named (args_so_far)) n_named_args = 0; else /* Treat all args as named. */ -- cgit v1.1 From 4f82d5a95a244d0aa4f8b2541b47a21bce8a191b Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 1 Mar 2024 17:26:42 +0100 Subject: OpenMP/C++: Fix (first)private clause with member variables [PR110347] OpenMP permits '(first)private' for C++ member variables, which GCC handles by tagging those by DECL_OMP_PRIVATIZED_MEMBER, adding a temporary VAR_DECL and DECL_VALUE_EXPR pointing to the 'this->member_var' in the C++ front end. The idea is that in omp-low.cc, the DECL_VALUE_EXPR is used before the region (for 'firstprivate'; ignored for 'private') while in the region, the DECL itself is used. In gimplify, the value expansion is suppressed and deferred if the lang_hooks.decls.omp_disregard_value_expr (decl, shared) returns true - which is never the case if 'shared' is true. In OpenMP 4.5, only 'map' and 'use_device_ptr' was permitted for the 'target' directive. And when OpenMP 5.0's 'private'/'firstprivate' clauses was added, the the update that now 'shared' argument could be false was missed. The respective check has now been added. 2024-03-01 Jakub Jelinek Tobias Burnus PR c++/110347 gcc/ChangeLog: * gimplify.cc (omp_notice_variable): Fix 'shared' arg to lang_hooks.decls.omp_disregard_value_expr for (first)private in target regions. libgomp/ChangeLog: * testsuite/libgomp.c++/target-lambda-3.C: Moved from gcc/testsuite/g++.dg/gomp/ and fixed is-mapped handling. * testsuite/libgomp.c++/target-lambda-1.C: Modify to also also work without offloading. * testsuite/libgomp.c++/firstprivate-1.C: New test. * testsuite/libgomp.c++/firstprivate-2.C: New test. * testsuite/libgomp.c++/private-1.C: New test. * testsuite/libgomp.c++/private-2.C: New test. * testsuite/libgomp.c++/target-lambda-4.C: New test. * testsuite/libgomp.c++/use_device_ptr-1.C: New test. gcc/testsuite/ChangeLog: * g++.dg/gomp/target-lambda-1.C: Moved to become a run-time test under testsuite/libgomp.c++. Co-authored-by: Tobias Burnus --- gcc/gimplify.cc | 20 +++--- gcc/testsuite/g++.dg/gomp/target-lambda-1.C | 94 ----------------------------- 2 files changed, 13 insertions(+), 101 deletions(-) delete mode 100644 gcc/testsuite/g++.dg/gomp/target-lambda-1.C (limited to 'gcc') diff --git a/gcc/gimplify.cc b/gcc/gimplify.cc index 7f79b3c..6ebca96 100644 --- a/gcc/gimplify.cc +++ b/gcc/gimplify.cc @@ -8144,13 +8144,6 @@ omp_notice_variable (struct gimplify_omp_ctx *ctx, tree decl, bool in_code) n = splay_tree_lookup (ctx->variables, (splay_tree_key)decl); if ((ctx->region_type & ORT_TARGET) != 0) { - if (ctx->region_type & ORT_ACC) - /* For OpenACC, as remarked above, defer expansion. */ - shared = false; - else - shared = true; - - ret = lang_hooks.decls.omp_disregard_value_expr (decl, shared); if (n == NULL) { unsigned nflags = flags; @@ -8275,9 +8268,22 @@ omp_notice_variable (struct gimplify_omp_ctx *ctx, tree decl, bool in_code) } found_outer: omp_add_variable (ctx, decl, nflags); + if (ctx->region_type & ORT_ACC) + /* For OpenACC, as remarked above, defer expansion. */ + shared = false; + else + shared = (nflags & (GOVD_PRIVATE | GOVD_FIRSTPRIVATE)) == 0; + ret = lang_hooks.decls.omp_disregard_value_expr (decl, shared); } else { + if (ctx->region_type & ORT_ACC) + /* For OpenACC, as remarked above, defer expansion. */ + shared = false; + else + shared = ((n->value | flags) + & (GOVD_PRIVATE | GOVD_FIRSTPRIVATE)) == 0; + ret = lang_hooks.decls.omp_disregard_value_expr (decl, shared); /* If nothing changed, there's nothing left to do. */ if ((n->value & flags) == flags) return ret; diff --git a/gcc/testsuite/g++.dg/gomp/target-lambda-1.C b/gcc/testsuite/g++.dg/gomp/target-lambda-1.C deleted file mode 100644 index 5ce8cea..0000000 --- a/gcc/testsuite/g++.dg/gomp/target-lambda-1.C +++ /dev/null @@ -1,94 +0,0 @@ -// We use 'auto' without a function return type, so specify dialect here -// { dg-additional-options "-std=c++14 -fdump-tree-gimple" } -#include -#include - -template -void -omp_target_loop (int begin, int end, L loop) -{ - #pragma omp target teams distribute parallel for - for (int i = begin; i < end; i++) - loop (i); -} - -struct S -{ - int a, len; - int *ptr; - - auto merge_data_func (int *iptr, int &b) - { - auto fn = [=](void) -> bool - { - bool mapped; - #pragma omp target map(from:mapped) - { - mapped = (ptr != NULL && iptr != NULL); - if (mapped) - { - for (int i = 0; i < len; i++) - ptr[i] += a + b + iptr[i]; - } - } - return mapped; - }; - return fn; - } -}; - -int x = 1; - -int main (void) -{ - const int N = 10; - int *data1 = new int[N]; - int *data2 = new int[N]; - memset (data1, 0xab, sizeof (int) * N); - memset (data1, 0xcd, sizeof (int) * N); - - int val = 1; - int &valref = val; - #pragma omp target enter data map(alloc: data1[:N], data2[:N]) - - omp_target_loop (0, N, [=](int i) { data1[i] = val; }); - omp_target_loop (0, N, [=](int i) { data2[i] = valref + 1; }); - - #pragma omp target update from(data1[:N], data2[:N]) - - for (int i = 0; i < N; i++) - { - if (data1[i] != 1) abort (); - if (data2[i] != 2) abort (); - } - - #pragma omp target exit data map(delete: data1[:N], data2[:N]) - - int b = 8; - S s = { 4, N, data1 }; - auto f = s.merge_data_func (data2, b); - - if (f ()) abort (); - - #pragma omp target enter data map(to: data1[:N]) - if (f ()) abort (); - - #pragma omp target enter data map(to: data2[:N]) - if (!f ()) abort (); - - #pragma omp target exit data map(from: data1[:N], data2[:N]) - - for (int i = 0; i < N; i++) - { - if (data1[i] != 0xf) abort (); - if (data2[i] != 2) abort (); - } - - return 0; -} - -/* { dg-final { scan-tree-dump {#pragma omp target num_teams.* firstprivate\(b\) map\(alloc:MEM.* \[len: 0\]\) map\(firstprivate:iptr \[pointer assign, bias: 0\]\) map\(alloc:MEM.* \[len: 0\]\) map\(firstprivate:this \[pointer assign, bias: 0\]\) map\(to:\*__closure \[len: [0-9]+\]\) map\(firstprivate:__closure \[pointer assign, bias: 0\]\) map\(tofrom:\*_[0-9]+ \[len: [0-9]+\]\) map\(always_pointer:__closure->__this \[pointer assign, bias: 0\]\) map\(from:mapped \[len: [0-9]+\]\) map\(alloc:\*_[0-9]+ \[len: 0\]\) map\(alloc:\*_[0-9]+ \[len: 0\]\) map\(attach_zero_length_array_section:__closure->__iptr \[bias: 0\]\) map\(attach_zero_length_array_section:_[0-9]+->ptr \[bias: 0\]\)} "gimple" } } */ - -/* { dg-final { scan-tree-dump {#pragma omp target num_teams.* firstprivate\(end\) firstprivate\(begin\) map\(to:loop \[len: [0-9]+\]\) map\(alloc:\*_[0-9]+ \[len: 0\]\) map\(attach_zero_length_array_section:loop\.__data1 \[bias: 0\]\)} "gimple" } } */ - -/* { dg-final { scan-tree-dump {#pragma omp target num_teams.* firstprivate\(end\) firstprivate\(begin\) map\(to:loop \[len: [0-9]+\]\) map\(alloc:\*_[0-9]+ \[len: 0\]\) map\(attach_zero_length_array_section:loop\.__data2 \[bias: 0\]\)} "gimple" } } */ -- cgit v1.1 From 867cbadb912ab75d0eaf919a3f992595e508482b Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Fri, 1 Mar 2024 16:59:08 +0100 Subject: c++: Fix up decltype of non-dependent structured binding decl in template [PR92687] finish_decltype_type uses DECL_HAS_VALUE_EXPR_P (expr) check for DECL_DECOMPOSITION_P (expr) to determine if it is array/struct/vector/complex etc. subobject proxy case vs. structured binding using std::tuple_{size,element}. For non-templates or when templates are already instantiated, that works correctly, finalized DECL_DECOMPOSITION_P non-base vars indeed have DECL_VALUE_EXPR in the former case and don't have it in the latter. It works fine for dependent structured bindings as well, cp_finish_decomp in that case creates DECLTYPE_TYPE tree and defers the handling until instantiation. As the testcase shows, this doesn't work for the non-dependent structured binding case in templates, because DECL_HAS_VALUE_EXPR_P is set in that case always; cp_finish_decomp ends with: if (processing_template_decl) { for (unsigned int i = 0; i < count; i++) if (!DECL_HAS_VALUE_EXPR_P (v[i])) { tree a = build_nt (ARRAY_REF, decl, size_int (i), NULL_TREE, NULL_TREE); SET_DECL_VALUE_EXPR (v[i], a); DECL_HAS_VALUE_EXPR_P (v[i]) = 1; } } and those artificial ARRAY_REFs are used in various places during instantiation to find out what base the DECL_DECOMPOSITION_P VAR_DECLs have and their positions. The following patch fixes that by changing lookup_decomp_type, such that it doesn't ICE when called on a DECL_DECOMPOSITION_P var which isn't in a hash table, but returns NULL_TREE in that case, and for processing_template_decl asserts DECL_HAS_VALUE_EXPR_P is non-NULL and just calls lookup_decomp_type. If it returns non-NULL, it is a structured binding using tuple and its result is returned, otherwise it falls through to returning unlowered_expr_type (expr) because it is an array, structure etc. subobject proxy. For !processing_template_decl it keeps doing what it did before, DECL_HAS_VALUE_EXPR_P meaning it is an array/structure etc. subobject proxy, otherwise the tuple case. 2024-03-01 Jakub Jelinek PR c++/92687 * decl.cc (lookup_decomp_type): Return NULL_TREE if decomp_type_table doesn't have entry for V. * semantics.cc (finish_decltype_type): If ptds.saved, assert DECL_HAS_VALUE_EXPR_P is true and decide on tuple vs. non-tuple based on if lookup_decomp_type is NULL or not. * g++.dg/cpp1z/decomp59.C: New test. --- gcc/cp/decl.cc | 4 ++- gcc/cp/semantics.cc | 9 +++++ gcc/testsuite/g++.dg/cpp1z/decomp59.C | 63 +++++++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/cpp1z/decomp59.C (limited to 'gcc') diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc index 05e4600..993d7ef 100644 --- a/gcc/cp/decl.cc +++ b/gcc/cp/decl.cc @@ -9262,7 +9262,9 @@ static GTY((cache)) decl_tree_cache_map *decomp_type_table; tree lookup_decomp_type (tree v) { - return *decomp_type_table->get (v); + if (tree *slot = decomp_type_table->get (v)) + return *slot; + return NULL_TREE; } /* Mangle a decomposition declaration if needed. Arguments like diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc index 5784017..adb1ba4 100644 --- a/gcc/cp/semantics.cc +++ b/gcc/cp/semantics.cc @@ -11804,6 +11804,15 @@ finish_decltype_type (tree expr, bool id_expression_or_member_access_p, access expression). */ if (DECL_DECOMPOSITION_P (expr)) { + if (ptds.saved) + { + gcc_checking_assert (DECL_HAS_VALUE_EXPR_P (expr)); + /* DECL_HAS_VALUE_EXPR_P is always set if + processing_template_decl. If lookup_decomp_type + returns non-NULL, it is the tuple case. */ + if (tree ret = lookup_decomp_type (expr)) + return ret; + } if (DECL_HAS_VALUE_EXPR_P (expr)) /* Expr is an array or struct subobject proxy, handle bit-fields properly. */ diff --git a/gcc/testsuite/g++.dg/cpp1z/decomp59.C b/gcc/testsuite/g++.dg/cpp1z/decomp59.C new file mode 100644 index 0000000..52a72fa --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1z/decomp59.C @@ -0,0 +1,63 @@ +// PR c++/92687 +// { dg-do compile { target c++11 } } +// { dg-options "" } + +namespace std { + template struct tuple_size; + template struct tuple_element; +} + +struct A { + int i; + template int& get() { return i; } +}; + +template<> struct std::tuple_size { static const int value = 2; }; +template struct std::tuple_element { using type = int; }; + +template +struct is_reference { + static const bool value = false; +}; + +template +struct is_reference +{ + static const bool value = true; +}; + +template +struct is_reference +{ + static const bool value = true; +}; + +template +void +foo () +{ + auto [x, y] = A {}; // { dg-warning "structured bindings only available with" "" { target c++14_down } } + static_assert (!is_reference::value, ""); +} + +void +bar () +{ + auto [x, y] = A {}; // { dg-warning "structured bindings only available with" "" { target c++14_down } } + static_assert (!is_reference::value, ""); +} + +template +void +baz () +{ + auto [x, y] = T {}; // { dg-warning "structured bindings only available with" "" { target c++14_down } } + static_assert (!is_reference::value, ""); +} + +void +qux () +{ + foo<0> (); + baz (); +} -- cgit v1.1 From 4894c82b0c3cf0d6ec4bc1e96709b6140ec11f6e Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Fri, 1 Mar 2024 17:39:22 +0100 Subject: AVR: Overhaul help screen gcc/ * config/avr/avr.opt: Overhaul help screen. --- gcc/config/avr/avr.opt | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/avr.opt index ea35b7d..c3ca837 100644 --- a/gcc/config/avr/avr.opt +++ b/gcc/config/avr/avr.opt @@ -20,27 +20,27 @@ mcall-prologues Target Mask(CALL_PROLOGUES) Optimization -Use subroutines for function prologues and epilogues. +Optimization. Use subroutines for function prologues and epilogues. mmcu= Target RejectNegative Joined Var(avr_mmcu) MissingArgError(missing device or architecture after %qs) --mmcu=MCU Select the target MCU. +-mmcu= Select the target MCU. mgas-isr-prologues Target Var(avr_gasisr_prologues) UInteger Init(0) Optimization -Allow usage of __gcc_isr pseudo instructions in ISR prologues and epilogues. +Optimization. Allow usage of __gcc_isr pseudo instructions in ISR prologues and epilogues. mn-flash= Target RejectNegative Joined Var(avr_n_flash) UInteger Init(-1) -Set the number of 64 KiB flash segments. +This option is used internally. Set the number of 64 KiB flash segments. mskip-bug Target Mask(SKIP_BUG) -Indicate presence of a processor erratum. +This option is used internally. Indicate presence of a processor erratum. Do not skip 32-bit instructions. mrmw Target Mask(RMW) -Enable Read-Modify-Write (RMW) instructions support/use. +This option is used internally. Enable Read-Modify-Write (RMW) instructions support/use. mdeb Target Undocumented Mask(ALL_DEBUG) @@ -50,7 +50,7 @@ Target RejectNegative Joined Undocumented Var(avr_log_details) mshort-calls Target RejectNegative Mask(SHORT_CALLS) -Use RJMP / RCALL even though CALL / JMP are available. +This option is used internally for multilib generation and selection. Assume RJMP / RCALL can target all program memory. mint8 Target Mask(INT8) @@ -62,11 +62,11 @@ Change the stack pointer without disabling interrupts. mbranch-cost= Target Joined RejectNegative UInteger Var(avr_branch_cost) Init(0) Optimization -Set the branch costs for conditional branch instructions. Reasonable values are small, non-negative integers. The default branch cost is 0. +-mbranch-cost= Optimization. Set the branch costs for conditional branch instructions. Reasonable values are small, non-negative integers. The default branch cost is 0. mmain-is-OS_task Target Mask(MAIN_IS_OS_TASK) Optimization -Treat main as if it had attribute OS_task. +Optimization. Treat main as if it had attribute OS_task. morder1 Target Undocumented Mask(ORDER_1) @@ -80,7 +80,7 @@ Change only the low 8 bits of the stack pointer. mrelax Target Optimization -Relax branches. +Optimization. Relax branches. mpmem-wrap-around Target @@ -88,15 +88,15 @@ Make the linker relaxation machine assume that a program counter wrap-around occ maccumulate-args Target Mask(ACCUMULATE_OUTGOING_ARGS) Optimization -Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards. This option can lead to reduced code size for functions that call many functions that get their arguments on the stack like, for example printf. +Optimization. Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards. This option can lead to reduced code size for functions that call many functions that get their arguments on the stack like, for example printf. mstrict-X Target Var(avr_strict_X) Init(0) Optimization -When accessing RAM, use X as imposed by the hardware, i.e. just use pre-decrement, post-increment and indirect addressing with the X register. Without this option, the compiler may assume that there is an addressing mode X+const similar to Y+const and Z+const and emit instructions to emulate such an addressing mode for X. +Optimization. When accessing RAM, use X as imposed by the hardware, i.e. just use pre-decrement, post-increment and indirect addressing with the X register. Without this option, the compiler may assume that there is an addressing mode X+const similar to Y+const and Z+const and emit instructions to emulate such an addressing mode for X. mflmap Target Var(avr_flmap) Init(0) -The device has the bitfield NVMCTRL_CTRLB.FLMAP. This option is used internally. +This option is used internally. The device has the bitfield NVMCTRL_CTRLB.FLMAP. mrodata-in-ram Target Var(avr_rodata_in_ram) Init(-1) @@ -105,15 +105,15 @@ The device has the .rodata section located in the RAM area. ;; For rationale behind -msp8 see explanation in avr.h. msp8 Target RejectNegative Var(avr_sp8) Init(0) -The device has no SPH special function register. This option will be overridden by the compiler driver with the correct setting if presence/absence of SPH can be deduced from -mmcu=MCU. +This option is used internally for multilib generation and selection. The device has no SPH special function register. mfuse-add -Target Alias(mfuse-add=, 1, 0) Optimization -Split register additions from load/store instructions. Most useful on Reduced Tiny. +Target Alias(mfuse-add=, 2, 0) Optimization +Optimization. Split register additions from load/store instructions. Most useful on Reduced Tiny. mfuse-add= Target Joined RejectNegative UInteger Var(avr_fuse_add) Init(0) Optimization IntegerRange(0, 3) -Split register additions from load/store instructions. Most useful on Reduced Tiny. +-mfuse-add=<0,2> Optimization. Split register additions from load/store instructions. Most useful on Reduced Tiny. Waddr-space-convert Warning C Var(avr_warn_addr_space_convert) Init(0) @@ -129,7 +129,7 @@ Allow to use truncation instead of rounding towards zero for fractional fixed-po mabsdata Target Mask(ABSDATA) -Assume that all data in static storage can be accessed by LDS / STS. This option is only useful for reduced Tiny devices. +Assume that all data in static storage can be accessed by LDS / STS instructions. This option is only useful for reduced Tiny devices like ATtiny40. mdouble= Target Joined RejectNegative Var(avr_double) Init(0) Enum(avr_bits_e) Save -- cgit v1.1 From a6a1920b592b58c38137c5c891b3bbb02b084f38 Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Fri, 1 Mar 2024 12:50:18 -0500 Subject: c++: auto(x) partial substitution [PR110025, PR114138] In r12-6773-g09845ad7569bac we gave CTAD placeholders a level of 0 and ensured we never replaced them via tsubst. It turns out that autos representing an explicit cast need the same treatment and for the same reason: such autos appear in an expression context and so their level gets easily messed up after partial substitution, leading to premature replacement via an incidental tsubst instead of via do_auto_deduction. This patch fixes this by extending the r12-6773 approach to auto(x). PR c++/110025 PR c++/114138 gcc/cp/ChangeLog: * cp-tree.h (make_cast_auto): Declare. * parser.cc (cp_parser_functional_cast): If the type is an auto, replace it with a level-less one via make_cast_auto. * pt.cc (find_parameter_packs_r): Don't treat level-less auto as a type parameter pack. (tsubst) : Generalize CTAD placeholder auto handling to all level-less autos. (make_cast_auto): Define. (do_auto_deduction): Handle replacement of a level-less auto. gcc/testsuite/ChangeLog: * g++.dg/cpp23/auto-fncast16.C: New test. * g++.dg/cpp23/auto-fncast17.C: New test. * g++.dg/cpp23/auto-fncast18.C: New test. Reviewed-by: Jason Merrill --- gcc/cp/cp-tree.h | 1 + gcc/cp/parser.cc | 11 +++++ gcc/cp/pt.cc | 36 +++++++++++++++- gcc/testsuite/g++.dg/cpp23/auto-fncast16.C | 12 ++++++ gcc/testsuite/g++.dg/cpp23/auto-fncast17.C | 15 +++++++ gcc/testsuite/g++.dg/cpp23/auto-fncast18.C | 69 ++++++++++++++++++++++++++++++ 6 files changed, 142 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp23/auto-fncast16.C create mode 100644 gcc/testsuite/g++.dg/cpp23/auto-fncast17.C create mode 100644 gcc/testsuite/g++.dg/cpp23/auto-fncast18.C (limited to 'gcc') diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 06c2637..4469d96 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -7477,6 +7477,7 @@ extern tree make_decltype_auto (void); extern tree make_constrained_auto (tree, tree); extern tree make_constrained_decltype_auto (tree, tree); extern tree make_template_placeholder (tree); +extern tree make_cast_auto (void); extern bool template_placeholder_p (tree); extern bool ctad_template_p (tree); extern bool unparenthesized_id_or_class_member_access_p (tree); diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc index 3ee9d49..a310b9e 100644 --- a/gcc/cp/parser.cc +++ b/gcc/cp/parser.cc @@ -33314,6 +33314,17 @@ cp_parser_functional_cast (cp_parser* parser, tree type) if (!type) type = error_mark_node; + if (TREE_CODE (type) == TYPE_DECL + && is_auto (TREE_TYPE (type))) + type = TREE_TYPE (type); + + if (is_auto (type) + && !AUTO_IS_DECLTYPE (type) + && !PLACEHOLDER_TYPE_CONSTRAINTS (type) + && !CLASS_PLACEHOLDER_TEMPLATE (type)) + /* auto(x) and auto{x} need to use a level-less auto. */ + type = make_cast_auto (); + if (cp_lexer_next_token_is (parser->lexer, CPP_OPEN_BRACE)) { cp_lexer_set_source_position (parser->lexer); diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc index 2803824..c4bc54a 100644 --- a/gcc/cp/pt.cc +++ b/gcc/cp/pt.cc @@ -3921,7 +3921,8 @@ find_parameter_packs_r (tree *tp, int *walk_subtrees, void* data) parameter pack (14.6.3), or the type-specifier-seq of a type-id that is a pack expansion, the invented template parameter is a template parameter pack. */ - if (ppd->type_pack_expansion_p && is_auto (t)) + if (ppd->type_pack_expansion_p && is_auto (t) + && TEMPLATE_TYPE_LEVEL (t) != 0) TEMPLATE_TYPE_PARAMETER_PACK (t) = true; if (TEMPLATE_TYPE_PARAMETER_PACK (t)) parameter_pack_p = true; @@ -16297,9 +16298,19 @@ tsubst (tree t, tree args, tsubst_flags_t complain, tree in_decl) } case TEMPLATE_TYPE_PARM: - if (template_placeholder_p (t)) + if (TEMPLATE_TYPE_LEVEL (t) == 0) { + /* This is either an ordinary level-less auto or a CTAD placeholder + auto. These get replaced only via do_auto_deduction which, in the + ordinary case, temporarily overrides its level to 1 before calling + tsubst. CTAD placeholders are replaced via do_class_deduction. */ + gcc_checking_assert (is_auto (t)); tree tmpl = CLASS_PLACEHOLDER_TEMPLATE (t); + if (!tmpl) + /* Ordinary level-less auto has nothing to substitute. */ + return t; + + /* Substitute the template of this CTAD placeholder. */ tmpl = tsubst_expr (tmpl, args, complain, in_decl); if (TREE_CODE (tmpl) == TEMPLATE_TEMPLATE_PARM) tmpl = TEMPLATE_TEMPLATE_PARM_TEMPLATE_DECL (tmpl); @@ -29311,6 +29322,17 @@ template_placeholder_p (tree t) return is_auto (t) && CLASS_PLACEHOLDER_TEMPLATE (t); } +/* Return an auto for an explicit cast expression auto(x). + Like CTAD placeholders, these have level 0 so that they're + not accidentally replaced via tsubst and are always directly + resolved via do_auto_deduction. */ + +tree +make_cast_auto () +{ + return make_auto_1 (auto_identifier, true, /*level=*/0); +} + /* Make a "constrained auto" type-specifier. This is an auto or decltype(auto) type with constraints that must be associated after deduction. The constraint is formed from the given concept CON @@ -31213,6 +31235,16 @@ do_auto_deduction (tree type, tree init, tree auto_node, } } + if (TEMPLATE_TYPE_LEVEL (auto_node) == 0) + { + /* Substitute this level-less auto via tsubst by temporarily + overriding its level to 1. */ + TEMPLATE_TYPE_LEVEL (auto_node) = 1; + type = tsubst (type, targs, complain, NULL_TREE); + TEMPLATE_TYPE_LEVEL (auto_node) = 0; + return type; + } + if (TEMPLATE_TYPE_LEVEL (auto_node) == 1) /* The outer template arguments are already substituted into type (but we still may have used them for constraint checking above). */; diff --git a/gcc/testsuite/g++.dg/cpp23/auto-fncast16.C b/gcc/testsuite/g++.dg/cpp23/auto-fncast16.C new file mode 100644 index 0000000..e2c13f6 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp23/auto-fncast16.C @@ -0,0 +1,12 @@ +// PR c++/110025 +// { dg-do compile { target c++23 } } + +template +struct A { }; + +template +A f(); + +int main() { + f<0>(); +} diff --git a/gcc/testsuite/g++.dg/cpp23/auto-fncast17.C b/gcc/testsuite/g++.dg/cpp23/auto-fncast17.C new file mode 100644 index 0000000..25186df --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp23/auto-fncast17.C @@ -0,0 +1,15 @@ +// PR c++/110025 +// { dg-do compile { target c++23 } } + +template struct tuple; + +template +using constant_t = int; + +template +using constants_t = tuple...>; + +using ty0 = constants_t<>; +using ty1 = constants_t<1>; +using ty2 = constants_t<1, 2>; +using ty3 = constants_t<1, 2, 3>; diff --git a/gcc/testsuite/g++.dg/cpp23/auto-fncast18.C b/gcc/testsuite/g++.dg/cpp23/auto-fncast18.C new file mode 100644 index 0000000..4656723 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp23/auto-fncast18.C @@ -0,0 +1,69 @@ +// PR c++/114138 +// { dg-do compile { target c++23 } } + +namespace std { + template + T&& declval() noexcept requires true; + + template + void declval() noexcept; + + namespace detail { + struct none_such; + template + using none_such_t = none_such; + + template + extern const none_such_t _getter_for; + + template + using _decay_t = decltype(auto(declval())); + + static_assert(__is_same_as(_decay_t, void)); + } + + template + using _result_of_t = decltype(Fn(declval()...)); + + template + using tuple_element_t = _result_of_t>, char(*)[I+1], Tuple>; + + template + struct pair { + First first; + Second second; + }; + + template + inline constexpr bool _is_pair = false; + + template + inline constexpr bool _is_pair> = true; + + template + concept Pair = _is_pair()))>; + + template + requires (I <= 1) + decltype(auto) get(P&& p) noexcept { + if constexpr (I == 0) { + return (static_cast(p).first); + } else { + return (static_cast(p).second); + } + } + + namespace detail { + inline constexpr auto _pair_getter = + [](char(*)[J], Pair&& p) noexcept -> decltype(auto) { + return std::get(static_cast(p)); + }; + + template + inline constexpr auto _getter_for> = _pair_getter; + } + +} + +static_assert(__is_same_as(int&, std::tuple_element_t<0, std::pair&>)); +static_assert(__is_same_as(float&&, std::tuple_element_t<1, std::pair&&>)); -- cgit v1.1 From db0b6746be075e43c8142585968483e125bb52d0 Mon Sep 17 00:00:00 2001 From: Harald Anlauf Date: Fri, 1 Mar 2024 19:21:27 +0100 Subject: Fortran: improve checks of NULL without MOLD as actual argument [PR104819] gcc/fortran/ChangeLog: PR fortran/104819 * check.cc (gfc_check_null): Handle nested NULL()s. (is_c_interoperable): Check for MOLD argument of NULL() as part of the interoperability check. * interface.cc (gfc_compare_actual_formal): Extend checks for NULL() actual arguments for presence of MOLD argument when required by Interp J3/22-146. gcc/testsuite/ChangeLog: PR fortran/104819 * gfortran.dg/assumed_rank_9.f90: Adjust testcase use of NULL(). * gfortran.dg/pr101329.f90: Adjust testcase to conform to interp. * gfortran.dg/null_actual_4.f90: New test. --- gcc/fortran/check.cc | 5 +++- gcc/fortran/interface.cc | 30 ++++++++++++++++++++++++ gcc/testsuite/gfortran.dg/assumed_rank_9.f90 | 13 +++++++---- gcc/testsuite/gfortran.dg/null_actual_4.f90 | 35 ++++++++++++++++++++++++++++ gcc/testsuite/gfortran.dg/pr101329.f90 | 4 ++-- 5 files changed, 79 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/null_actual_4.f90 (limited to 'gcc') diff --git a/gcc/fortran/check.cc b/gcc/fortran/check.cc index d661cf3..db74dcf 100644 --- a/gcc/fortran/check.cc +++ b/gcc/fortran/check.cc @@ -4384,6 +4384,9 @@ gfc_check_null (gfc_expr *mold) if (mold == NULL) return true; + if (mold->expr_type == EXPR_NULL) + return true; + if (!variable_check (mold, 0, true)) return false; @@ -5216,7 +5219,7 @@ is_c_interoperable (gfc_expr *expr, const char **msg, bool c_loc, bool c_f_ptr) { *msg = NULL; - if (expr->expr_type == EXPR_NULL) + if (expr->expr_type == EXPR_NULL && expr->ts.type == BT_UNKNOWN) { *msg = "NULL() is not interoperable"; return false; diff --git a/gcc/fortran/interface.cc b/gcc/fortran/interface.cc index 231f2f2..64b9055 100644 --- a/gcc/fortran/interface.cc +++ b/gcc/fortran/interface.cc @@ -3296,6 +3296,36 @@ gfc_compare_actual_formal (gfc_actual_arglist **ap, gfc_formal_arglist *formal, && a->expr->ts.type != BT_ASSUMED) gfc_find_vtab (&a->expr->ts); + /* Interp J3/22-146: + "If the context of the reference to NULL is an + corresponding to an dummy argument, MOLD shall be + present." */ + if (a->expr->expr_type == EXPR_NULL + && a->expr->ts.type == BT_UNKNOWN + && f->sym->as + && f->sym->as->type == AS_ASSUMED_RANK) + { + gfc_error ("Intrinsic % without % argument at %L " + "passed to assumed-rank dummy %qs", + &a->expr->where, f->sym->name); + ok = false; + goto match; + } + + if (a->expr->expr_type == EXPR_NULL + && a->expr->ts.type == BT_UNKNOWN + && f->sym->ts.type == BT_CHARACTER + && !f->sym->ts.deferred + && f->sym->ts.u.cl + && f->sym->ts.u.cl->length == NULL) + { + gfc_error ("Intrinsic % without % argument at %L " + "passed to assumed-length dummy %qs", + &a->expr->where, f->sym->name); + ok = false; + goto match; + } + if (a->expr->expr_type == EXPR_NULL && ((f->sym->ts.type != BT_CLASS && !f->sym->attr.pointer && (f->sym->attr.allocatable || !f->sym->attr.optional diff --git a/gcc/testsuite/gfortran.dg/assumed_rank_9.f90 b/gcc/testsuite/gfortran.dg/assumed_rank_9.f90 index 1296d06..5e59ec1 100644 --- a/gcc/testsuite/gfortran.dg/assumed_rank_9.f90 +++ b/gcc/testsuite/gfortran.dg/assumed_rank_9.f90 @@ -26,19 +26,20 @@ program main type(t), target :: y class(t), allocatable, target :: yac - + type(t), pointer :: ypt + y%i = 489 allocate (yac) yac%i = 489 j = 0 call fc() - call fc(null()) + call fc(null(yac)) call fc(y) call fc(yac) if (j /= 2) STOP 1 j = 0 - call gc(null()) +! call gc(null(yac)) ! ICE call gc(y) call gc(yac) deallocate (yac) @@ -54,13 +55,14 @@ program main j = 0 call ft() - call ft(null()) + call ft(null(yac)) call ft(y) call ft(yac) if (j /= 2) STOP 4 j = 0 - call gt(null()) + call gt(null(ypt)) +! call gt(null(yac)) ! ICE call gt(y) call gt(yac) deallocate (yac) @@ -73,6 +75,7 @@ program main yac%i = 489 call ht(yac) if (j /= 1) STOP 6 + deallocate (yac) contains diff --git a/gcc/testsuite/gfortran.dg/null_actual_4.f90 b/gcc/testsuite/gfortran.dg/null_actual_4.f90 new file mode 100644 index 0000000..e03d5c8 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/null_actual_4.f90 @@ -0,0 +1,35 @@ +! { dg-do compile } +! PR fortran/104819 +! +! Reject NULL without MOLD as actual to an assumed-rank dummy. +! See also interpretation request at +! https://j3-fortran.org/doc/year/22/22-101r1.txt +! +! Test nested NULL() + +program p + implicit none + integer, pointer :: a, a3(:,:,:) + character(10), pointer :: c + + call foo (a) + call foo (a3) + call foo (null (a)) + call foo (null (a3)) + call foo (null (null (a))) ! Valid: nested NULL()s + call foo (null (null (a3))) ! Valid: nested NULL()s + call foo (null ()) ! { dg-error "passed to assumed-rank dummy" } + + call str (null (c)) + call str (null (null (c))) + call str (null ()) ! { dg-error "passed to assumed-length dummy" } +contains + subroutine foo (x) + integer, pointer, intent(in) :: x(..) + print *, rank (x) + end + + subroutine str (x) + character(len=*), pointer, intent(in) :: x + end +end diff --git a/gcc/testsuite/gfortran.dg/pr101329.f90 b/gcc/testsuite/gfortran.dg/pr101329.f90 index b82210d..aca171b 100644 --- a/gcc/testsuite/gfortran.dg/pr101329.f90 +++ b/gcc/testsuite/gfortran.dg/pr101329.f90 @@ -8,6 +8,6 @@ program p integer(c_int64_t), pointer :: ip8 print *, c_sizeof (c_null_ptr) ! valid print *, c_sizeof (null ()) ! { dg-error "is not interoperable" } - print *, c_sizeof (null (ip4)) ! { dg-error "is not interoperable" } - print *, c_sizeof (null (ip8)) ! { dg-error "is not interoperable" } + print *, c_sizeof (null (ip4)) ! valid + print *, c_sizeof (null (ip8)) ! valid end -- cgit v1.1 From 64221c7bffbdd399e49554b0fb08b38325657596 Mon Sep 17 00:00:00 2001 From: David Faust Date: Fri, 1 Mar 2024 10:43:24 -0800 Subject: testsuite: ctf: make array in ctf-file-scope-1 fixed length The array member of struct SFOO in the ctf-file-scope-1 caused the test to fail for the BPF target, since BPF does not support dynamic stack allocation. The array does not need to variable length for the sake of the test, so make it fixed length instead to allow the test to run successfully for the bpf-unknown-none target. gcc/testsuite/ * gcc.dg/debug/ctf/ctf-file-scope-1.c (SFOO): Make array member fixed-length. --- gcc/testsuite/gcc.dg/debug/ctf/ctf-file-scope-1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/debug/ctf/ctf-file-scope-1.c b/gcc/testsuite/gcc.dg/debug/ctf/ctf-file-scope-1.c index a683113..ddfb31d 100644 --- a/gcc/testsuite/gcc.dg/debug/ctf/ctf-file-scope-1.c +++ b/gcc/testsuite/gcc.dg/debug/ctf/ctf-file-scope-1.c @@ -9,7 +9,7 @@ int foo (int n) { - typedef struct { int a[n]; } SFOO; + typedef struct { int a[6]; } SFOO; SFOO a; __attribute__ ((noinline)) SFOO gfoo (void) { return a; } -- cgit v1.1 From c7607c4cf18986025430ca8626abfe56bfe87106 Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Thu, 25 Jan 2024 16:38:51 -0500 Subject: c++: implement [[gnu::no_dangling]] [PR110358] Since -Wdangling-reference has false positives that can't be prevented, we should offer an easy way to suppress the warning. Currently, that is only possible by using a #pragma, either around the enclosing class or around the call site. But #pragma GCC diagnostic tend to be onerous. A better solution would be to have an attribute. To that end, this patch adds a new attribute, [[gnu::no_dangling]]. This attribute takes an optional bool argument to support cases like: template struct [[gnu::no_dangling(std::is_reference_v)]] S { // ... }; PR c++/110358 PR c++/109642 gcc/cp/ChangeLog: * call.cc (no_dangling_p): New. (reference_like_class_p): Use it. (do_warn_dangling_reference): Use it. Don't warn when the function or its enclosing class has attribute gnu::no_dangling. * tree.cc (cxx_gnu_attributes): Add gnu::no_dangling. (handle_no_dangling_attribute): New. gcc/ChangeLog: * doc/extend.texi: Document gnu::no_dangling. * doc/invoke.texi: Mention that gnu::no_dangling disables -Wdangling-reference. gcc/testsuite/ChangeLog: * g++.dg/ext/attr-no-dangling1.C: New test. * g++.dg/ext/attr-no-dangling2.C: New test. * g++.dg/ext/attr-no-dangling3.C: New test. * g++.dg/ext/attr-no-dangling4.C: New test. * g++.dg/ext/attr-no-dangling5.C: New test. * g++.dg/ext/attr-no-dangling6.C: New test. * g++.dg/ext/attr-no-dangling7.C: New test. * g++.dg/ext/attr-no-dangling8.C: New test. * g++.dg/ext/attr-no-dangling9.C: New test. --- gcc/cp/call.cc | 38 +++++++++++++--- gcc/cp/tree.cc | 26 +++++++++++ gcc/doc/extend.texi | 48 ++++++++++++++++++++ gcc/doc/invoke.texi | 6 +++ gcc/testsuite/g++.dg/ext/attr-no-dangling1.C | 40 +++++++++++++++++ gcc/testsuite/g++.dg/ext/attr-no-dangling2.C | 29 +++++++++++++ gcc/testsuite/g++.dg/ext/attr-no-dangling3.C | 24 ++++++++++ gcc/testsuite/g++.dg/ext/attr-no-dangling4.C | 14 ++++++ gcc/testsuite/g++.dg/ext/attr-no-dangling5.C | 31 +++++++++++++ gcc/testsuite/g++.dg/ext/attr-no-dangling6.C | 65 ++++++++++++++++++++++++++++ gcc/testsuite/g++.dg/ext/attr-no-dangling7.C | 31 +++++++++++++ gcc/testsuite/g++.dg/ext/attr-no-dangling8.C | 30 +++++++++++++ gcc/testsuite/g++.dg/ext/attr-no-dangling9.C | 25 +++++++++++ 13 files changed, 401 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ext/attr-no-dangling1.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-no-dangling2.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-no-dangling3.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-no-dangling4.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-no-dangling5.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-no-dangling6.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-no-dangling7.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-no-dangling8.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-no-dangling9.C (limited to 'gcc') diff --git a/gcc/cp/call.cc b/gcc/cp/call.cc index c40ef2e..9e4c807 100644 --- a/gcc/cp/call.cc +++ b/gcc/cp/call.cc @@ -14033,11 +14033,7 @@ std_pair_ref_ref_p (tree t) return true; } -/* Return true if a class CTYPE is either std::reference_wrapper or - std::ref_view, or a reference wrapper class. We consider a class - a reference wrapper class if it has a reference member. We no - longer check that it has a constructor taking the same reference type - since that approach still generated too many false positives. */ +/* Return true if a class T has a reference member. */ static bool class_has_reference_member_p (tree t) @@ -14061,12 +14057,41 @@ class_has_reference_member_p_r (tree binfo, void *) ? integer_one_node : NULL_TREE); } + +/* Return true if T (either a class or a function) has been marked as + not-dangling. */ + +static bool +no_dangling_p (tree t) +{ + t = lookup_attribute ("no_dangling", TYPE_ATTRIBUTES (t)); + if (!t) + return false; + + t = TREE_VALUE (t); + if (!t) + return true; + + t = build_converted_constant_bool_expr (TREE_VALUE (t), tf_warning_or_error); + t = cxx_constant_value (t); + return t == boolean_true_node; +} + +/* Return true if a class CTYPE is either std::reference_wrapper or + std::ref_view, or a reference wrapper class. We consider a class + a reference wrapper class if it has a reference member. We no + longer check that it has a constructor taking the same reference type + since that approach still generated too many false positives. */ + static bool reference_like_class_p (tree ctype) { if (!CLASS_TYPE_P (ctype)) return false; + if (no_dangling_p (ctype)) + return true; + /* Also accept a std::pair. */ if (std_pair_ref_ref_p (ctype)) return true; @@ -14173,7 +14198,8 @@ do_warn_dangling_reference (tree expr, bool arg_p) but probably not to one of its arguments. */ || (DECL_OBJECT_MEMBER_FUNCTION_P (fndecl) && DECL_OVERLOADED_OPERATOR_P (fndecl) - && DECL_OVERLOADED_OPERATOR_IS (fndecl, INDIRECT_REF))) + && DECL_OVERLOADED_OPERATOR_IS (fndecl, INDIRECT_REF)) + || no_dangling_p (TREE_TYPE (fndecl))) return NULL_TREE; tree rettype = TREE_TYPE (TREE_TYPE (fndecl)); diff --git a/gcc/cp/tree.cc b/gcc/cp/tree.cc index ad31271..e75be9a 100644 --- a/gcc/cp/tree.cc +++ b/gcc/cp/tree.cc @@ -47,6 +47,7 @@ static tree verify_stmt_tree_r (tree *, int *, void *); static tree handle_init_priority_attribute (tree *, tree, tree, int, bool *); static tree handle_abi_tag_attribute (tree *, tree, tree, int, bool *); static tree handle_contract_attribute (tree *, tree, tree, int, bool *); +static tree handle_no_dangling_attribute (tree *, tree, tree, int, bool *); /* If REF is an lvalue, returns the kind of lvalue that REF is. Otherwise, returns clk_none. */ @@ -5102,6 +5103,8 @@ static const attribute_spec cxx_gnu_attributes[] = handle_init_priority_attribute, NULL }, { "abi_tag", 1, -1, false, false, false, true, handle_abi_tag_attribute, NULL }, + { "no_dangling", 0, 1, false, true, false, false, + handle_no_dangling_attribute, NULL }, }; const scoped_attribute_specs cxx_gnu_attribute_table = @@ -5391,6 +5394,29 @@ handle_contract_attribute (tree *ARG_UNUSED (node), tree ARG_UNUSED (name), return NULL_TREE; } +/* Handle a "no_dangling" attribute; arguments as in + struct attribute_spec.handler. */ + +tree +handle_no_dangling_attribute (tree *node, tree name, tree args, int, + bool *no_add_attrs) +{ + if (args && TREE_CODE (TREE_VALUE (args)) == STRING_CST) + { + error ("%qE attribute argument must be an expression that evaluates " + "to true or false", name); + *no_add_attrs = true; + } + else if (!FUNC_OR_METHOD_TYPE_P (*node) + && !RECORD_OR_UNION_TYPE_P (*node)) + { + warning (OPT_Wattributes, "%qE attribute ignored", name); + *no_add_attrs = true; + } + + return NULL_TREE; +} + /* Return a new PTRMEM_CST of the indicated TYPE. The MEMBER is the thing pointed to by the constant. */ diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 6c2c7ae..f679c81 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -29327,6 +29327,54 @@ Some_Class B __attribute__ ((init_priority (543))); Note that the particular values of @var{priority} do not matter; only their relative ordering. +@cindex @code{no_dangling} type attribute +@cindex @code{no_dangling} function attribute +@item no_dangling + +This attribute can be applied on a class type, function, or member +function. Dangling references to classes marked with this attribute +will have the @option{-Wdangling-reference} diagnostic suppressed; so +will references returned from the @code{gnu::no_dangling}-marked +functions. For example: + +@smallexample +class [[gnu::no_dangling]] S @{ @dots{} @}; +@end smallexample + +Or: + +@smallexample +class A @{ + int *p; + [[gnu::no_dangling]] int &foo() @{ return *p; @} +@}; + +[[gnu::no_dangling]] const int & +foo (const int &i) +@{ + @dots{} +@} +@end smallexample + +This attribute takes an optional argument, which must be an expression that +evaluates to true or false: + +@smallexample +template +struct [[gnu::no_dangling(std::is_reference_v)]] S @{ + @dots{} +@}; +@end smallexample + +Or: + +@smallexample +template +[[gnu::no_dangling(std::is_reference_v)]] int& foo (T& t) @{ + @dots{} +@}; +@end smallexample + @cindex @code{warn_unused} type attribute @item warn_unused diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index dc5fd86..bdf05be 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -3908,6 +3908,9 @@ const T& foo (const T&) @{ @dots{} @} #pragma GCC diagnostic pop @end smallexample +The @code{#pragma} can also surround the class; in that case, the warning +will be disabled for all the member functions. + @option{-Wdangling-reference} also warns about code like @smallexample @@ -3932,6 +3935,9 @@ struct Span @{ as @code{std::span}-like; that is, the class is a non-union class that has a pointer data member and a trivial destructor. +The warning can be disabled by using the @code{gnu::no_dangling} attribute +(@pxref{C++ Attributes}). + This warning is enabled by @option{-Wall}. @opindex Wdelete-non-virtual-dtor diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling1.C b/gcc/testsuite/g++.dg/ext/attr-no-dangling1.C new file mode 100644 index 0000000..dff34e8 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling1.C @@ -0,0 +1,40 @@ +// { dg-do compile { target c++11 } } +// { dg-options "-Wdangling-reference" } + +int g = 42; + +struct [[gnu::no_dangling]] A { + ~A(); + int *i; + int &foo() { return *i; } +}; + +struct A2 { + ~A2(); + int *i; + [[gnu::no_dangling]] int &foo() { return *i; } + [[gnu::no_dangling]] static int &bar (const int &) { return *&g; } +}; + +union [[gnu::no_dangling]] U { }; + +A a() { return A{&g}; } +A2 a2() { return A2{&g}; } + +class X { }; +const X x1; +const X x2; + +[[gnu::no_dangling]] const X& get(const int& i) +{ + return i == 0 ? x1 : x2; +} + +void +test () +{ + [[maybe_unused]] const X& x = get (10); // { dg-bogus "dangling" } + [[maybe_unused]] const int &i = a().foo(); // { dg-bogus "dangling" } + [[maybe_unused]] const int &j = a2().foo(); // { dg-bogus "dangling" } + [[maybe_unused]] const int &k = a2().bar(10); // { dg-bogus "dangling" } +} diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling2.C b/gcc/testsuite/g++.dg/ext/attr-no-dangling2.C new file mode 100644 index 0000000..4cdc97e --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling2.C @@ -0,0 +1,29 @@ +// { dg-do compile { target c++11 } } +// Negative tests. + +struct [[no_dangling]] A { // { dg-warning "ignored" } + [[no_dangling]] int &foo (int &); // { dg-warning "ignored" } +}; + +[[no_dangling]] int &bar (int &); // { dg-warning "ignored" } + +[[gnu::no_dangling]] int i; // { dg-warning "ignored" } +[[gnu::no_dangling]] double d; // { dg-warning "ignored" } +[[gnu::no_dangling]] typedef int T; // { dg-warning "ignored" } + +[[gnu::no_dangling()]] int &fn1 (int &); // { dg-error "parentheses" } +[[gnu::no_dangling("a")]] int &fn2 (int &); // { dg-error "must be an expression" } +[[gnu::no_dangling(true, true)]] int &fn3 (int &); // { dg-error "wrong number of arguments" } + +enum [[gnu::no_dangling]] E { // { dg-warning "ignored" } + X [[gnu::no_dangling]] // { dg-warning "ignored" } +}; + +[[gnu::no_dangling]]; // { dg-warning "ignored" } + +void +g () +{ + goto L; +[[gnu::no_dangling]] L:; // { dg-warning "ignored" } +} diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling3.C b/gcc/testsuite/g++.dg/ext/attr-no-dangling3.C new file mode 100644 index 0000000..764b104 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling3.C @@ -0,0 +1,24 @@ +// { dg-do compile { target c++11 } } +// { dg-options "-Wdangling-reference" } + +template +struct [[gnu::no_dangling]] Span { + T* data_; + int len_; + // So that our heuristic doesn't suppress the warning anyway. + ~Span(); + + [[nodiscard]] constexpr auto operator[](int n) const noexcept -> T& { return data_[n]; } + [[nodiscard]] constexpr auto front() const noexcept -> T& { return data_[0]; } + [[nodiscard]] constexpr auto back() const noexcept -> T& { return data_[len_ - 1]; } +}; + +auto get() -> Span; + +auto f() -> int { + int const& a = get().front(); // { dg-bogus "dangling" } + int const& b = get().back(); // { dg-bogus "dangling" } + int const& c = get()[0]; // { dg-bogus "dangling" } + + return a + b + c; +} diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling4.C b/gcc/testsuite/g++.dg/ext/attr-no-dangling4.C new file mode 100644 index 0000000..e910723 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling4.C @@ -0,0 +1,14 @@ +// { dg-do compile { target c++11 } } + +#if !__has_attribute(no_dangling) +#error unsupported +#endif + +#ifdef __has_cpp_attribute +# if !__has_cpp_attribute(no_dangling) +# error no_dangling +# endif +#endif + +struct [[gnu::no_dangling]] S { }; +static_assert (__builtin_has_attribute (S, no_dangling), ""); diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling5.C b/gcc/testsuite/g++.dg/ext/attr-no-dangling5.C new file mode 100644 index 0000000..ec50754 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling5.C @@ -0,0 +1,31 @@ +// PR c++/110358 +// { dg-do compile { target c++20 } } +// { dg-options "-Wdangling-reference" } + +template +struct Span { + T* data_; + int len_; + ~Span(); + + [[nodiscard]] constexpr auto operator[](int n) const noexcept -> T& { return data_[n]; } +}; + +template <> +struct [[gnu::no_dangling]] Span { + int* data_; + int len_; + ~Span(); + + [[nodiscard]] constexpr auto operator[](int n) const noexcept -> int& { return data_[n]; } +}; + +auto getch() -> Span; +auto geti() -> Span; + +void +f () +{ + [[maybe_unused]] const auto &a = getch()[0]; // { dg-warning "dangling reference" } + [[maybe_unused]] const auto &b = geti()[0]; // { dg-bogus "dangling reference" } +} diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling6.C b/gcc/testsuite/g++.dg/ext/attr-no-dangling6.C new file mode 100644 index 0000000..235a5fd --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling6.C @@ -0,0 +1,65 @@ +// PR c++/110358 +// { dg-do compile { target c++20 } } +// { dg-options "-Wdangling-reference" } + +class X { }; +const X x1; +const X x2; + +constexpr bool val () { return true; } +struct ST { static constexpr bool value = true; }; +struct SF { static constexpr bool value = false; }; + +template +[[gnu::no_dangling(T::value)]] +const X& get (const int& i) +{ + return i == 0 ? x1 : x2; +} + +template +[[gnu::no_dangling(B)]] +const X& foo (const int& i) +{ + return i == 0 ? x1 : x2; +} + +[[gnu::no_dangling(val ())]] +const X& bar (const int& i) +{ + return i == 0 ? x1 : x2; +} + +[[gnu::no_dangling(!val ())]] +const X& baz (const int& i) +{ + return i == 0 ? x1 : x2; +} + +template +struct [[gnu::no_dangling(T::value)]] +Span { + T* data_; + int len_; + ~Span(); + + [[nodiscard]] constexpr auto operator[](int n) const noexcept -> T& { return data_[n]; } +}; + +auto geti() -> Span; +auto gety() -> Span; + +void +test () +{ + [[maybe_unused]] const X& x1 = get (10); // { dg-bogus "dangling" } + [[maybe_unused]] const X& x2 = get (10); // { dg-warning "dangling" } + [[maybe_unused]] const X& x3 = foo (10); // { dg-bogus "dangling" } + [[maybe_unused]] const X& x4 = foo (10); // { dg-warning "dangling" } + [[maybe_unused]] const X& x7 = foo<> (10); // { dg-bogus "dangling" } + [[maybe_unused]] const X& x5 = bar (10); // { dg-bogus "dangling" } + [[maybe_unused]] const X& x6 = baz (10); // { dg-warning "dangling" } + + [[maybe_unused]] const auto &b1 = geti()[0]; // { dg-bogus "dangling" } + [[maybe_unused]] const auto &b2 = gety()[0]; // { dg-warning "dangling" } +} diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling7.C b/gcc/testsuite/g++.dg/ext/attr-no-dangling7.C new file mode 100644 index 0000000..3c392ed --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling7.C @@ -0,0 +1,31 @@ +// PR c++/110358 +// { dg-do compile { target c++20 } } +// { dg-options "-Wdangling-reference" } + +class X { }; +const X x1; +const X x2; + +template +[[gnu::no_dangling(N)]] const X& get(const int& i); // { dg-error "parameter packs not expanded" } + +template +[[gnu::no_dangling(T::x)]] // { dg-error "member" } +const X& foo(const int& i); + +bool val () { return true; } + +[[gnu::no_dangling(val ())]] // { dg-error "call" } +const X& bar (const int& i); + +[[gnu::no_dangling(20)]] const X& fn1 (const int &); + +void +test () +{ + [[maybe_unused]] const X& x1 = bar (10); // { dg-warning "dangling" } + [[maybe_unused]] const X& x2 = foo (10); // { dg-error "no matching" } + [[maybe_unused]] const X& x3 // { dg-warning "dangling" } + = fn1 (10); // { dg-error "narrowing" } +} + diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling8.C b/gcc/testsuite/g++.dg/ext/attr-no-dangling8.C new file mode 100644 index 0000000..8208d75 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling8.C @@ -0,0 +1,30 @@ +// PR c++/110358 +// { dg-do compile { target c++20 } } +// { dg-options "-Wdangling-reference" } + +template constexpr bool is_reference_v = false; +template constexpr bool is_reference_v = true; +template constexpr bool is_reference_v = true; + +template +struct [[gnu::no_dangling(is_reference_v)]] S { + int &foo (const int &); +}; + +template +struct X { + template + struct [[gnu::no_dangling(is_reference_v && is_reference_v)]] Y { + int &foo (const int &); + }; +}; + +void +g () +{ + [[maybe_unused]] const int &x0 = S().foo (42); // { dg-bogus "dangling" } + [[maybe_unused]] const int &x1 = S().foo (42); // { dg-warning "dangling" } + [[maybe_unused]] const auto &x2 = X::Y<>().foo (42); // { dg-warning "dangling" } + [[maybe_unused]] const auto &x3 = X::Y<>().foo (42); // { dg-bogus "dangling" } +} + diff --git a/gcc/testsuite/g++.dg/ext/attr-no-dangling9.C b/gcc/testsuite/g++.dg/ext/attr-no-dangling9.C new file mode 100644 index 0000000..65b4f71 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/attr-no-dangling9.C @@ -0,0 +1,25 @@ +// PR c++/110358 +// { dg-do compile { target c++20 } } +// { dg-options "-Wdangling-reference" } + +template +struct bool_constant { + static constexpr bool value = B; + constexpr operator bool() const { return value; } +}; + +using true_type = bool_constant; +using false_type = bool_constant; + +struct S { + template + [[gnu::no_dangling(B)]] int &foo (const int &); +}; + +void +g () +{ + [[maybe_unused]] const int &x0 = S().foo (42); // { dg-warning "dangling" } + [[maybe_unused]] const int &x1 = S().foo (42); // { dg-bogus "dangling" } +} + -- cgit v1.1 From e15ef78e4a1e50a51a92468e32186fbad59dd628 Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Fri, 1 Mar 2024 16:50:20 -0500 Subject: c++/modules: complete_vars ICE with non-exported constexpr var Here after stream-in of the non-exported constexpr global 'A a' we call maybe_register_incomplete_var, which we'd expect to be a no-op here but it manages to take its second branch and pushes {a, NULL_TREE} onto incomplete_vars. Later after defining B we ICE from complete_vars due to this pushed NULL_TREE class context. Judging by the two commits that introduced/modified this part of maybe_register_incomplete_var, r196852 and r214333, it seems this second branch is only concerned with constexpr static data members (whose initializer may contain a pointer-to-member for a not-yet-complete class) So this patch restricts this branch accordingly so it's not inadvertently taken during stream-in. gcc/cp/ChangeLog: * decl.cc (maybe_register_incomplete_var): Restrict second branch to static data members from a not-yet-complete class. gcc/testsuite/ChangeLog: * g++.dg/modules/cexpr-4_a.C: New test. * g++.dg/modules/cexpr-4_b.C: New test. Reviewed-by: Jason Merrill --- gcc/cp/decl.cc | 2 ++ gcc/testsuite/g++.dg/modules/cexpr-4_a.C | 10 ++++++++++ gcc/testsuite/g++.dg/modules/cexpr-4_b.C | 6 ++++++ 3 files changed, 18 insertions(+) create mode 100644 gcc/testsuite/g++.dg/modules/cexpr-4_a.C create mode 100644 gcc/testsuite/g++.dg/modules/cexpr-4_b.C (limited to 'gcc') diff --git a/gcc/cp/decl.cc b/gcc/cp/decl.cc index 993d7ef..dbc3df2 100644 --- a/gcc/cp/decl.cc +++ b/gcc/cp/decl.cc @@ -18979,6 +18979,8 @@ maybe_register_incomplete_var (tree var) vec_safe_push (incomplete_vars, iv); } else if (!(DECL_LANG_SPECIFIC (var) && DECL_TEMPLATE_INFO (var)) + && DECL_CLASS_SCOPE_P (var) + && TYPE_BEING_DEFINED (DECL_CONTEXT (var)) && decl_constant_var_p (var) && (TYPE_PTRMEM_P (inner_type) || CLASS_TYPE_P (inner_type))) { diff --git a/gcc/testsuite/g++.dg/modules/cexpr-4_a.C b/gcc/testsuite/g++.dg/modules/cexpr-4_a.C new file mode 100644 index 0000000..44eea35 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/cexpr-4_a.C @@ -0,0 +1,10 @@ +// { dg-additional-options "-fmodules-ts" } +export module Cexpr4; +// { dg-module-cmi "Cexpr4" } + +struct A { int m = 42; }; + +constexpr A a; + +export +inline int f() { return a.m; } diff --git a/gcc/testsuite/g++.dg/modules/cexpr-4_b.C b/gcc/testsuite/g++.dg/modules/cexpr-4_b.C new file mode 100644 index 0000000..8ead58e --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/cexpr-4_b.C @@ -0,0 +1,6 @@ +// { dg-additional-options "-fmodules-ts" } +import Cexpr4; + +int v = f(); + +struct B { }; -- cgit v1.1 From b7b387e1200fd182599195979d5d21656fa8969d Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Fri, 1 Mar 2024 14:54:04 -0700 Subject: [14 regression] Fix insn types in risc-v port So one of the broad goals we've had over the last few months has been to ensure that every insn has a scheduling type and that every insn is associated with an insn reservation in the scheduler. This avoids some amazingly bad behavior in the scheduler. I won't go through the gory details. I was recently analyzing a code quality regression with dhrystone (ugh!) and one of the issues was poor scheduling which lengthened the lifetime of a pseudo and ultimately resulted in needing an additional callee saved register save/restore. This was ultimately tracked down incorrect types on a few patterns. So I did an audit of all the patterns that had types added/changed as part of this effort and found a variety of problems, primarily in the various move patterns and extension patterns. This is a regression relative to gcc-13. Naturally the change in types affects scheduling, which in turn changes the precise code we generate and causes some testsuite fallout. I considered updating the regexps since the change in the resulting output is pretty consistent. But of course the test would still be sensitive to things like load latency. So instead I just turned off the 2nd phase scheduler in the affected tests. Bootstrapped and regression tested on rv64gc-linux-gnu. gcc * config/riscv/riscv.md (zero_extendqi2_internal): Fix type attribute. (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise. (movdi_32bit, movdi_64bit, movsi_internal): Likewise. (movhi_internal, movqi_internal): Likewise. (movsf_softfloat, movsf_hardfloat): Likewise. (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise. (movdf_softfloat): Likewise. gcc/testsuite * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Turn off second phase scheduler. * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise. * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise. --- gcc/config/riscv/riscv.md | 28 +++++++++++----------- .../riscv/rvv/autovec/vls/calling-convention-1.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-2.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-3.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-4.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-5.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-6.c | 2 +- .../riscv/rvv/autovec/vls/calling-convention-7.c | 2 +- 8 files changed, 21 insertions(+), 21 deletions(-) (limited to 'gcc') diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1fec130..b16ed97 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1836,7 +1836,7 @@ andi\t%0,%1,0xff lbu\t%0,%1" [(set_attr "move_type" "andi,load") - (set_attr "type" "multi") + (set_attr "type" "arith,load") (set_attr "mode" "")]) ;; @@ -1861,7 +1861,7 @@ sext.w\t%0,%1 lw\t%0,%1" [(set_attr "move_type" "move,load") - (set_attr "type" "multi") + (set_attr "type" "move,load") (set_attr "mode" "DI")]) (define_expand "extend2" @@ -1938,7 +1938,7 @@ || reg_or_0_operand (operands[1], HFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "HF")]) (define_insn "*movhf_softfloat" @@ -1949,7 +1949,7 @@ || reg_or_0_operand (operands[1], HFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,move,load,store,mtc,mfc") - (set_attr "type" "fmove") + (set_attr "type" "fmove,move,load,store,mtc,mfc") (set_attr "mode" "HF")]) (define_insn "*movhf_softfloat_boxing" @@ -2182,7 +2182,7 @@ { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") (set_attr "mode" "DI") - (set_attr "type" "move") + (set_attr "type" "move,move,load,store,move,fpload,move,fmove,fpstore,move") (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) (define_insn "*movdi_64bit" @@ -2194,7 +2194,7 @@ { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") (set_attr "mode" "DI") - (set_attr "type" "move") + (set_attr "type" "move,move,load,store,mtc,fpload,mfc,fmove,fpstore,move") (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) ;; 32-bit Integer moves @@ -2217,7 +2217,7 @@ { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb") (set_attr "mode" "SI") - (set_attr "type" "move") + (set_attr "type" "move,move,load,store,mtc,fpload,mfc,fpstore,move") (set_attr "ext" "base,base,base,base,f,f,f,f,vector")]) ;; 16-bit Integer moves @@ -2244,7 +2244,7 @@ { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") (set_attr "mode" "HI") - (set_attr "type" "move") + (set_attr "type" "move,move,load,store,mtc,mfc,move") (set_attr "ext" "base,base,base,base,f,f,vector")]) ;; HImode constant generation; see riscv_move_integer for details. @@ -2288,7 +2288,7 @@ { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") (set_attr "mode" "QI") - (set_attr "type" "move") + (set_attr "type" "move,move,load,store,mtc,mfc,move") (set_attr "ext" "base,base,base,base,f,f,vector")]) ;; 32-bit floating point moves @@ -2310,7 +2310,7 @@ || reg_or_0_operand (operands[1], SFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "SF")]) (define_insn "*movsf_softfloat" @@ -2321,7 +2321,7 @@ || reg_or_0_operand (operands[1], SFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "move,load,store") (set_attr "mode" "SF")]) ;; 64-bit floating point moves @@ -2346,7 +2346,7 @@ || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "DF")]) (define_insn "*movdf_hardfloat_rv64" @@ -2357,7 +2357,7 @@ || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "fmove,fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") (set_attr "mode" "DF")]) (define_insn "*movdf_softfloat" @@ -2368,7 +2368,7 @@ || reg_or_0_operand (operands[1], DFmode))" { return riscv_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,load,store") - (set_attr "type" "fmove") + (set_attr "type" "fmove,fpload,fpstore") (set_attr "mode" "DF")]) (define_insn "movsidf2_low_rv32" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c index 28b8a82..60c838e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c index d45fb4c..b9922a6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c index 1885004..989d45d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c index 3a4ed22..b8bb293 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c index e3f3b39..f0357d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c index 4c876ac..edf6539 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c index 5542d48..e001a73 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3" } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mrvv-vector-bits=scalable -mabi=lp64d -O3 -fno-schedule-insns2" } */ #include "def.h" -- cgit v1.1 From 2823b4d96d9ec4ad4e67e5e8edaa1b060a467491 Mon Sep 17 00:00:00 2001 From: Nathaniel Shead Date: Thu, 29 Feb 2024 22:49:13 +1100 Subject: c++: Ensure DECL_CONTEXT is set for temporary vars [PR114005] Modules streaming requires DECL_CONTEXT to be set for anything streamed. This patch ensures that 'create_temporary_var' does set a DECL_CONTEXT for these variables (such as the backing storage for initializer_lists) even if not inside a function declaration. PR c++/114005 gcc/cp/ChangeLog: * init.cc (create_temporary_var): Use current_scope instead of current_function_decl. gcc/testsuite/ChangeLog: * g++.dg/modules/pr114005_a.C: New test. * g++.dg/modules/pr114005_b.C: New test. Signed-off-by: Nathaniel Shead --- gcc/cp/init.cc | 2 +- gcc/testsuite/g++.dg/modules/pr114005_a.C | 8 ++++++++ gcc/testsuite/g++.dg/modules/pr114005_b.C | 7 +++++++ 3 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/modules/pr114005_a.C create mode 100644 gcc/testsuite/g++.dg/modules/pr114005_b.C (limited to 'gcc') diff --git a/gcc/cp/init.cc b/gcc/cp/init.cc index 1a341f7..d2586fa 100644 --- a/gcc/cp/init.cc +++ b/gcc/cp/init.cc @@ -4258,7 +4258,7 @@ create_temporary_var (tree type) TREE_USED (decl) = 1; DECL_ARTIFICIAL (decl) = 1; DECL_IGNORED_P (decl) = 1; - DECL_CONTEXT (decl) = current_function_decl; + DECL_CONTEXT (decl) = current_scope (); return decl; } diff --git a/gcc/testsuite/g++.dg/modules/pr114005_a.C b/gcc/testsuite/g++.dg/modules/pr114005_a.C new file mode 100644 index 0000000..4046834 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/pr114005_a.C @@ -0,0 +1,8 @@ +// { dg-additional-options "-fmodules-ts" } +// { dg-module-cmi M } + +module; +#include + +export module M; +export constexpr std::initializer_list foo{ 1, 2, 3 }; diff --git a/gcc/testsuite/g++.dg/modules/pr114005_b.C b/gcc/testsuite/g++.dg/modules/pr114005_b.C new file mode 100644 index 0000000..88317ce --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/pr114005_b.C @@ -0,0 +1,7 @@ +// { dg-additional-options "-fmodules-ts" } + +import M; + +int main() { + return foo.size(); +} -- cgit v1.1 From 852b58552991099141f9df5782e1f28d8606af9d Mon Sep 17 00:00:00 2001 From: Nathaniel Shead Date: Fri, 1 Mar 2024 11:08:23 +1100 Subject: c++: Stream definitions for implicit instantiations [PR114170] An implicit instantiation has an initializer depending on whether DECL_INITIALIZED_P is set (like normal VAR_DECLs) which needs to be written to ensure that consumers of header modules properly emit definitions for these instantiations. This patch ensures that we correctly fallback to checking this flag when DECL_INITIAL is not set for a template instantiation. For variables with non-trivial dynamic initialization, DECL_INITIAL can be empty after 'split_nonconstant_init' but DECL_INITIALIZED_P is still set; we need to check the latter to determine if we need to go looking for a definition to emit (often in 'static_aggregates' here). This is the case in the linked testcase. However, for template specialisations (not instantiations?) we primarily care about DECL_INITIAL; if the variable has initialization depending on a template parameter then we'll need to emit that definition even though it doesn't yet have DECL_INITIALIZED_P set; this is the case in e.g. template int value = N; As a drive-by fix, also ensures that the count of initializers matches the actual number of initializers written. This doesn't seem to be necessary for correctness in the current testsuite, but feels wrong and makes debugging harder when initializers aren't properly written for other reasons. PR c++/114170 gcc/cp/ChangeLog: * module.cc (has_definition): Fall back to DECL_INITIALIZED_P when DECL_INITIAL is not set on a template. (module_state::write_inits): Only increment count when initializers are actually written. gcc/testsuite/ChangeLog: * g++.dg/modules/var-tpl-2_a.H: New test. * g++.dg/modules/var-tpl-2_b.C: New test. Signed-off-by: Nathaniel Shead --- gcc/cp/module.cc | 9 ++++++--- gcc/testsuite/g++.dg/modules/var-tpl-2_a.H | 10 ++++++++++ gcc/testsuite/g++.dg/modules/var-tpl-2_b.C | 10 ++++++++++ 3 files changed, 26 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/g++.dg/modules/var-tpl-2_a.H create mode 100644 gcc/testsuite/g++.dg/modules/var-tpl-2_b.C (limited to 'gcc') diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc index 1b2ba2e..355ee5d 100644 --- a/gcc/cp/module.cc +++ b/gcc/cp/module.cc @@ -11585,9 +11585,11 @@ has_definition (tree decl) break; case VAR_DECL: + /* DECL_INITIALIZED_P might not be set on a dependent VAR_DECL. */ if (DECL_LANG_SPECIFIC (decl) - && DECL_TEMPLATE_INFO (decl)) - return DECL_INITIAL (decl); + && DECL_TEMPLATE_INFO (decl) + && DECL_INITIAL (decl)) + return true; else { if (!DECL_INITIALIZED_P (decl)) @@ -17528,13 +17530,14 @@ module_state::write_inits (elf_out *to, depset::hash &table, unsigned *crc_ptr) tree list = static_aggregates; for (int passes = 0; passes != 2; passes++) { - for (tree init = list; init; init = TREE_CHAIN (init), count++) + for (tree init = list; init; init = TREE_CHAIN (init)) if (TREE_LANG_FLAG_0 (init)) { tree decl = TREE_VALUE (init); dump ("Initializer:%u for %N", count, decl); sec.tree_node (decl); + ++count; } list = tls_aggregates; diff --git a/gcc/testsuite/g++.dg/modules/var-tpl-2_a.H b/gcc/testsuite/g++.dg/modules/var-tpl-2_a.H new file mode 100644 index 0000000..607fc0b --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/var-tpl-2_a.H @@ -0,0 +1,10 @@ +// PR c++/114170 +// { dg-additional-options "-fmodule-header" } +// { dg-module-cmi {} } + +inline int f() { return 42; } + +template +inline int v = f(); + +inline int g() { return v; } diff --git a/gcc/testsuite/g++.dg/modules/var-tpl-2_b.C b/gcc/testsuite/g++.dg/modules/var-tpl-2_b.C new file mode 100644 index 0000000..6d2ef40 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/var-tpl-2_b.C @@ -0,0 +1,10 @@ +// PR c++/114170 +// { dg-module-do run } +// { dg-additional-options "-fmodules-ts" } + +import "var-tpl-2_a.H"; + +int main() { + if (v != 42) + __builtin_abort(); +} -- cgit v1.1 From 574fd1f17f100c7c355ad26bc525ab5a3386bb2d Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Fri, 1 Mar 2024 17:24:15 -0500 Subject: c++/modules: depending local enums [PR104919, PR106009] For local enums defined in a non-template function or a function template instantiation it seems we neglect to make the function depend on the enum definition (which modules considers logically separate), which ultimately causes the enum definition to not be properly streamed before uses within the function definition are streamed. The code responsible for noting such dependencies is gcc/cp/module.cc @@ -8784,17 +8784,6 @@ trees_out::decl_node (tree decl, walk_kind ref) depset *dep = NULL; if (streaming_p ()) dep = dep_hash->find_dependency (decl); ! else if (TREE_CODE (ctx) != FUNCTION_DECL ! || TREE_CODE (decl) == TEMPLATE_DECL ! || (dep_hash->sneakoscope && DECL_IMPLICIT_TYPEDEF_P (decl)) ! || (DECL_LANG_SPECIFIC (decl) ! && DECL_MODULE_IMPORT_P (decl))) ! { ! auto kind = (TREE_CODE (decl) == NAMESPACE_DECL ! && !DECL_NAMESPACE_ALIAS (decl) ! ? depset::EK_NAMESPACE : depset::EK_DECL); ! dep = dep_hash->add_dependency (decl, kind); ! } if (!dep) { and the condition there notably excludes local TYPE_DECLs from a non-template-pattern function (when streaming a template pattern we'll see be dealing with the corresponding TEMPLATE_DECL of the local TYPE_DECL here, so we'll add the dependency). Local classes on the other hand seem to work properly, but perhaps by accident: with a local class we end up making the function depend on the injected-class-name of the local class rather than the local class as a whole because the injected-class-name satisfies the criteria (since its context is the local class, not the function). The 'sneakoscope' flag is set when walking a function declaration and its purpose seems to be to catch a local type that escapes the function via a deduced return type (so called voldemort types) and note a dependency on them. But there seems to be no reason to restrict this behavior to voldemort types, and indeed consistently noting the dependency for all local types fixes these PRs (almost). So this patch gets rid of this flag and enables the dependency tracking unconditionally. This was nearly enough to make things work, except we now ran into issues with the local TYPE_/CONST_DECL copies from the pre-gimplified version of a constexpr function body during streaming. Rather than making modules cope with this, it occurred to me that we don't need to make copies of local types when saving the pre-gimplified body (and when making further copies thereof); only VAR_DECLs etc need to be copied (so that we don't conflate local variables from different recursive calls to the same function during constexpr evaluation). So this patch adjusts copy_fn accordingly. PR c++/104919 PR c++/106009 gcc/cp/ChangeLog: * module.cc (depset::hash::sneakoscope): Remove. (trees_out::decl_node): Always add a dependency on a local type. (depset::hash::find_dependencies): Remove sneakoscope stuff. gcc/ChangeLog: * tree-inline.cc (remap_decl): Handle copy_decl returning the original decl. (remap_decls): Handle remap_decl returning the original decl. (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and CONST_DECL. gcc/testsuite/ChangeLog: * g++.dg/modules/tdef-7.h: Remove outdated comment. * g++.dg/modules/tdef-7_b.C: Don't expect two TYPE_DECLs. * g++.dg/modules/enum-13_a.C: New test. * g++.dg/modules/enum-13_b.C: New test. --- gcc/cp/module.cc | 12 ++---------- gcc/testsuite/g++.dg/modules/enum-13_a.C | 23 +++++++++++++++++++++++ gcc/testsuite/g++.dg/modules/enum-13_b.C | 8 ++++++++ gcc/testsuite/g++.dg/modules/tdef-7.h | 2 -- gcc/testsuite/g++.dg/modules/tdef-7_b.C | 2 +- gcc/tree-inline.cc | 14 +++++++++++--- 6 files changed, 45 insertions(+), 16 deletions(-) create mode 100644 gcc/testsuite/g++.dg/modules/enum-13_a.C create mode 100644 gcc/testsuite/g++.dg/modules/enum-13_b.C (limited to 'gcc') diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc index 355ee5d..67f132d 100644 --- a/gcc/cp/module.cc +++ b/gcc/cp/module.cc @@ -2522,13 +2522,12 @@ public: hash *chain; /* Original table. */ depset *current; /* Current depset being depended. */ unsigned section; /* When writing out, the section. */ - bool sneakoscope; /* Detecting dark magic (of a voldemort). */ bool reached_unreached; /* We reached an unreached entity. */ public: hash (size_t size, hash *c = NULL) : parent (size), chain (c), current (NULL), section (0), - sneakoscope (false), reached_unreached (false) + reached_unreached (false) { worklist.create (size); } @@ -8753,7 +8752,7 @@ trees_out::decl_node (tree decl, walk_kind ref) dep = dep_hash->find_dependency (decl); else if (TREE_CODE (ctx) != FUNCTION_DECL || TREE_CODE (decl) == TEMPLATE_DECL - || (dep_hash->sneakoscope && DECL_IMPLICIT_TYPEDEF_P (decl)) + || DECL_IMPLICIT_TYPEDEF_P (decl) || (DECL_LANG_SPECIFIC (decl) && DECL_MODULE_IMPORT_P (decl))) { @@ -13432,14 +13431,7 @@ depset::hash::find_dependencies (module_state *module) add_namespace_context (item, ns); } - // FIXME: Perhaps p1815 makes this redundant? Or at - // least simplifies it. Voldemort types are only - // ever emissable when containing (inline) function - // definition is emitted? - /* Turn the Sneakoscope on when depending the decl. */ - sneakoscope = true; walker.decl_value (decl, current); - sneakoscope = false; if (current->has_defn ()) walker.write_definition (decl); } diff --git a/gcc/testsuite/g++.dg/modules/enum-13_a.C b/gcc/testsuite/g++.dg/modules/enum-13_a.C new file mode 100644 index 0000000..1d0c86d --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/enum-13_a.C @@ -0,0 +1,23 @@ +// PR c++/104919 +// PR c++/106009 +// { dg-additional-options -fmodules-ts } +// { dg-module-cmi Enum13 } + +export module Enum13; + +export +constexpr int f() { + enum E { e = 42 }; + return e; +} + +template +constexpr int ft(T) { + enum E { e = 43 }; + return e; +} + +export +constexpr int g() { + return ft(0); +} diff --git a/gcc/testsuite/g++.dg/modules/enum-13_b.C b/gcc/testsuite/g++.dg/modules/enum-13_b.C new file mode 100644 index 0000000..16d4a7c --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/enum-13_b.C @@ -0,0 +1,8 @@ +// PR c++/104919 +// PR c++/106009 +// { dg-additional-options -fmodules-ts } + +import Enum13; + +static_assert(f() == 42); +static_assert(g() == 43); diff --git a/gcc/testsuite/g++.dg/modules/tdef-7.h b/gcc/testsuite/g++.dg/modules/tdef-7.h index 5bc21e1..6125f04 100644 --- a/gcc/testsuite/g++.dg/modules/tdef-7.h +++ b/gcc/testsuite/g++.dg/modules/tdef-7.h @@ -1,7 +1,5 @@ constexpr void duration_cast () { - // the constexpr's body's clone merely duplicates the TYPE_DECL, it - // doesn't create a kosher typedef typedef int __to_rep; } diff --git a/gcc/testsuite/g++.dg/modules/tdef-7_b.C b/gcc/testsuite/g++.dg/modules/tdef-7_b.C index c526ca8..ea76458 100644 --- a/gcc/testsuite/g++.dg/modules/tdef-7_b.C +++ b/gcc/testsuite/g++.dg/modules/tdef-7_b.C @@ -5,5 +5,5 @@ import "tdef-7_a.H"; // { dg-final { scan-lang-dump-times {merge key \(matched\) function_decl:'::duration_cast} 1 module } } // { dg-final { scan-lang-dump-not {merge key \(new\)} module } } -// { dg-final { scan-lang-dump-times {merge key \(unique\) type_decl:'#null#'} 2 module } } +// { dg-final { scan-lang-dump-times {merge key \(unique\) type_decl:'#null#'} 1 module } } // { dg-final { scan-lang-dump-times {Cloned:-[0-9]* typedef integer_type:'::duration_cast::__to_rep'} 1 module } } diff --git a/gcc/tree-inline.cc b/gcc/tree-inline.cc index 75c10eb..f0a067f 100644 --- a/gcc/tree-inline.cc +++ b/gcc/tree-inline.cc @@ -370,7 +370,7 @@ remap_decl (tree decl, copy_body_data *id) need this decl for TYPE_STUB_DECL. */ insert_decl_map (id, decl, t); - if (!DECL_P (t)) + if (!DECL_P (t) || t == decl) return t; /* Remap types, if necessary. */ @@ -765,7 +765,7 @@ remap_decls (tree decls, vec **nonlocalized_list, TREE_CHAIN. If we remapped this variable to the return slot, it's already declared somewhere else, so don't declare it here. */ - if (new_var == id->retvar) + if (new_var == old_var || new_var == id->retvar) ; else if (!new_var) { @@ -6610,7 +6610,15 @@ copy_fn (tree fn, tree& parms, tree& result) id.src_cfun = DECL_STRUCT_FUNCTION (fn); id.decl_map = &decl_map; - id.copy_decl = copy_decl_no_change; + id.copy_decl = [] (tree decl, copy_body_data *id) + { + if (TREE_CODE (decl) == TYPE_DECL || TREE_CODE (decl) == CONST_DECL) + /* Don't make copies of local types or injected enumerators, + the C++ constexpr evaluator doesn't need them and they + confuse modules streaming. */ + return decl; + return copy_decl_no_change (decl, id); + }; id.transform_call_graph_edges = CB_CGE_DUPLICATE; id.transform_new_cfg = false; id.transform_return_to_modify = false; -- cgit v1.1 From 306a4c3223533d930521e80d5c455d379b0f48b5 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sat, 2 Mar 2024 00:17:11 +0000 Subject: Daily bump. --- gcc/ChangeLog | 109 ++++ gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog | 61 ++ gcc/fortran/ChangeLog | 10 + gcc/testsuite/ChangeLog | 1449 +++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 1630 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fe6bb91..845ae73 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,112 @@ +2024-03-01 Patrick Palka + + PR c++/104919 + PR c++/106009 + * tree-inline.cc (remap_decl): Handle copy_decl returning the + original decl. + (remap_decls): Handle remap_decl returning the original decl. + (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and + CONST_DECL. + +2024-03-01 Jeff Law + + * config/riscv/riscv.md (zero_extendqi2_internal): Fix + type attribute. + (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise. + (movdi_32bit, movdi_64bit, movsi_internal): Likewise. + (movhi_internal, movqi_internal): Likewise. + (movsf_softfloat, movsf_hardfloat): Likewise. + (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise. + (movdf_softfloat): Likewise. + +2024-03-01 Marek Polacek + + PR c++/110358 + PR c++/109642 + * doc/extend.texi: Document gnu::no_dangling. + * doc/invoke.texi: Mention that gnu::no_dangling disables + -Wdangling-reference. + +2024-03-01 Georg-Johann Lay + + * config/avr/avr.opt: Overhaul help screen. + +2024-03-01 Jakub Jelinek + Tobias Burnus + + PR c++/110347 + * gimplify.cc (omp_notice_variable): Fix 'shared' arg to + lang_hooks.decls.omp_disregard_value_expr for + (first)private in target regions. + +2024-03-01 Jakub Jelinek + + PR middle-end/114136 + * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set + n_named_args initially before INIT_CUMULATIVE_ARGS to + structure_value_addr_parm rather than 0, after it don't modify + it if strict_argument_naming and clear only if + !pretend_outgoing_varargs_named. + +2024-03-01 Jakub Jelinek + + PR debug/114015 + * dwarf2out.cc (should_move_die_to_comdat): Return false for + aggregates without DW_AT_byte_size attribute or with non-constant + DW_AT_byte_size. + +2024-03-01 Georg-Johann Lay + + * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document + valid values for level. + +2024-03-01 Richard Biener + + PR middle-end/114070 + * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)): + Allow the folding if before lowering and the current IL + isn't supported with vcond_mask. + +2024-03-01 xuli + + * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc + attribute to riscv_attribute_table. + (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function. + (riscv_fntype_abi): Add riscv_vector_cc attribute check. + * doc/extend.texi: Add riscv_vector_cc attribute description. + +2024-03-01 Pan Li + + PR target/112817 + * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace + RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL. + * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove. + (enum rvv_vector_bits_enum): New enum for different RVV vector bits. + * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update + comments for option replacement. + * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of + riscv_autovec_preference to rvv_vector_bits. + (vls_mode_valid_p): Ditto. + (estimated_poly_value): Ditto. + * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to + vector chunks and honor new option mrvv-vector-bits. + (riscv_override_options_internal): Update comments and rename the + vector chunks. + * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove + internal option param=riscv-autovec-preference. + +2024-03-01 Jakub Jelinek + + * function.cc (assign_parms): Only call assign_parms_setup_varargs + early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty. + +2024-03-01 Jakub Jelinek + + PR middle-end/114156 + * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow + rhs1 of a VCE to have no underlying variable if it is a load and + handle that case. + 2024-02-29 David Malcolm PR analyzer/114159 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 88d4f65..e129c99 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240301 +20240302 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 4339b52..347e55c7 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,64 @@ +2024-03-01 Patrick Palka + + PR c++/104919 + PR c++/106009 + * module.cc (depset::hash::sneakoscope): Remove. + (trees_out::decl_node): Always add a dependency on a local type. + (depset::hash::find_dependencies): Remove sneakoscope stuff. + +2024-03-01 Nathaniel Shead + + PR c++/114170 + * module.cc (has_definition): Fall back to DECL_INITIALIZED_P + when DECL_INITIAL is not set on a template. + (module_state::write_inits): Only increment count when + initializers are actually written. + +2024-03-01 Nathaniel Shead + + PR c++/114005 + * init.cc (create_temporary_var): Use current_scope instead of + current_function_decl. + +2024-03-01 Patrick Palka + + * decl.cc (maybe_register_incomplete_var): Restrict second + branch to static data members from a not-yet-complete class. + +2024-03-01 Marek Polacek + + PR c++/110358 + PR c++/109642 + * call.cc (no_dangling_p): New. + (reference_like_class_p): Use it. + (do_warn_dangling_reference): Use it. Don't warn when the function + or its enclosing class has attribute gnu::no_dangling. + * tree.cc (cxx_gnu_attributes): Add gnu::no_dangling. + (handle_no_dangling_attribute): New. + +2024-03-01 Patrick Palka + + PR c++/110025 + PR c++/114138 + * cp-tree.h (make_cast_auto): Declare. + * parser.cc (cp_parser_functional_cast): If the type is an auto, + replace it with a level-less one via make_cast_auto. + * pt.cc (find_parameter_packs_r): Don't treat level-less auto + as a type parameter pack. + (tsubst) : Generalize CTAD placeholder + auto handling to all level-less autos. + (make_cast_auto): Define. + (do_auto_deduction): Handle replacement of a level-less auto. + +2024-03-01 Jakub Jelinek + + PR c++/92687 + * decl.cc (lookup_decomp_type): Return NULL_TREE if decomp_type_table + doesn't have entry for V. + * semantics.cc (finish_decltype_type): If ptds.saved, assert + DECL_HAS_VALUE_EXPR_P is true and decide on tuple vs. non-tuple based + on if lookup_decomp_type is NULL or not. + 2024-02-29 Marek Polacek PR c++/113987 diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index f6b6830..77b8b15 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,13 @@ +2024-03-01 Harald Anlauf + + PR fortran/104819 + * check.cc (gfc_check_null): Handle nested NULL()s. + (is_c_interoperable): Check for MOLD argument of NULL() as part of + the interoperability check. + * interface.cc (gfc_compare_actual_formal): Extend checks for NULL() + actual arguments for presence of MOLD argument when required by + Interp J3/22-146. + 2024-02-29 Alexander Westbrooks PR fortran/82943 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index deb15e9..c1fc1c5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,1452 @@ +2024-03-01 Patrick Palka + + PR c++/104919 + PR c++/106009 + * g++.dg/modules/tdef-7.h: Remove outdated comment. + * g++.dg/modules/tdef-7_b.C: Don't expect two TYPE_DECLs. + * g++.dg/modules/enum-13_a.C: New test. + * g++.dg/modules/enum-13_b.C: New test. + +2024-03-01 Nathaniel Shead + + PR c++/114170 + * g++.dg/modules/var-tpl-2_a.H: New test. + * g++.dg/modules/var-tpl-2_b.C: New test. + +2024-03-01 Nathaniel Shead + + PR c++/114005 + * g++.dg/modules/pr114005_a.C: New test. + * g++.dg/modules/pr114005_b.C: New test. + +2024-03-01 Jeff Law + + * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Turn off + second phase scheduler. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Likewise. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Likewise. + +2024-03-01 Patrick Palka + + * g++.dg/modules/cexpr-4_a.C: New test. + * g++.dg/modules/cexpr-4_b.C: New test. + +2024-03-01 Marek Polacek + + PR c++/110358 + PR c++/109642 + * g++.dg/ext/attr-no-dangling1.C: New test. + * g++.dg/ext/attr-no-dangling2.C: New test. + * g++.dg/ext/attr-no-dangling3.C: New test. + * g++.dg/ext/attr-no-dangling4.C: New test. + * g++.dg/ext/attr-no-dangling5.C: New test. + * g++.dg/ext/attr-no-dangling6.C: New test. + * g++.dg/ext/attr-no-dangling7.C: New test. + * g++.dg/ext/attr-no-dangling8.C: New test. + * g++.dg/ext/attr-no-dangling9.C: New test. + +2024-03-01 David Faust + + * gcc.dg/debug/ctf/ctf-file-scope-1.c (SFOO): Make array member + fixed-length. + +2024-03-01 Harald Anlauf + + PR fortran/104819 + * gfortran.dg/assumed_rank_9.f90: Adjust testcase use of NULL(). + * gfortran.dg/pr101329.f90: Adjust testcase to conform to interp. + * gfortran.dg/null_actual_4.f90: New test. + +2024-03-01 Patrick Palka + + PR c++/110025 + PR c++/114138 + * g++.dg/cpp23/auto-fncast16.C: New test. + * g++.dg/cpp23/auto-fncast17.C: New test. + * g++.dg/cpp23/auto-fncast18.C: New test. + +2024-03-01 Jakub Jelinek + + PR c++/92687 + * g++.dg/cpp1z/decomp59.C: New test. + +2024-03-01 Jakub Jelinek + Tobias Burnus + + PR c++/110347 + * g++.dg/gomp/target-lambda-1.C: Moved to become a + run-time test under testsuite/libgomp.c++. + +2024-03-01 Jakub Jelinek + + PR debug/114015 + * gcc.dg/debug/dwarf2/pr114015.c: New test. + +2024-03-01 xuli + + * g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C: New test. + * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c: New test. + * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c: New test. + +2024-03-01 Pan Li + + PR target/112817 + * g++.target/riscv/rvv/base/pr111296.C: Replace + param=riscv-autovec-preference to mrvv-vector-bits. + * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-6.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-8.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-12.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/pr113112-2.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/pr113112-3.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/pr113112-5.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/pr113247-2.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/pr113247-4.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/pr113281-2.c: Ditto. + * gcc.dg/vect/costmodel/riscv/rvv/pr113281-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/align-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/align-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/copysign-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/copysign-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/copysign-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/fmax-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/fmin-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/fmin_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/mulh-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/mulh-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/narrow-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/narrow-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/narrow_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/narrow_run-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/shift-immediate.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vadd-run-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vdiv-run-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmul-run-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vsub-run-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/bug-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/bug-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/bug-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/bug-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/bug-5.c: Ditto. + * gcc.target/riscv/rvv/autovec/bug-6.c: Ditto. + * gcc.target/riscv/rvv/autovec/bug-8.c: Ditto. + * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/cmp/vcond-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-10.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-11.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-10.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-11.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-5.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-6.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-7.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-8.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_arith_run-9.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv32-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh-rv64-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_zvfh_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_copysign-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fadd_run-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c: + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-1.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-2.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-3.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-4.c: Ditto. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma_run-8.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_fmul_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_mulh-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_mulh-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_mulh_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_narrow_shift_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift-6.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-8.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_shift_run-9.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_sqrt-zvfh-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_sqrt_run-zvfh-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/cond_widen_reduc_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/cond/pr111401.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vec-narrow-int64-float16.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vec-widen-float16-int64.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt-itof-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-itof-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfncvt-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-ftoi-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-itof-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vfwcvt-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vncvt-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vsext-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vsext-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vzext-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/conversions/vzext-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Diito. + * gcc.target/riscv/rvv/autovec/fold-min-poly.c: Diito. + * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c: Diito. + * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Diito. + * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Diito. + * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Diito. + * gcc.target/riscv/rvv/autovec/madd-split2-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/gimple_fold-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/live-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/live-2.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/live_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/live_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-3.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-4.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup-2.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup-3.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-10.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-11.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-12.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-13.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-14.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-15.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-16.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-17.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-18.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-19.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-2.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-3.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-4.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-5.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-6.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-7.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-8.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-10.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-11.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-12.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-13.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-14.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-15.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-16.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-17.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-18.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-19.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-8.c: Diito. + * gcc.target/riscv/rvv/autovec/partial/slp_run-9.c: Diito. + * gcc.target/riscv/rvv/autovec/post-ra-avl.c: Diito. + * gcc.target/riscv/rvv/autovec/pr110950.c: Diito. + * gcc.target/riscv/rvv/autovec/pr110964.c: Diito. + * gcc.target/riscv/rvv/autovec/pr110989.c: Diito. + * gcc.target/riscv/rvv/autovec/pr111232.c: Diito. + * gcc.target/riscv/rvv/autovec/pr111295.c: Diito. + * gcc.target/riscv/rvv/autovec/pr111313.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112326.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112552.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112554.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112561.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112597-1.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112599-1.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112599-3.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112694-1.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112854.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112872.c: Diito. + * gcc.target/riscv/rvv/autovec/pr112999.c: Diito. + * gcc.target/riscv/rvv/autovec/pr113393-1.c: Diito. + * gcc.target/riscv/rvv/autovec/pr113393-2.c: Diito. + * gcc.target/riscv/rvv/autovec/pr113393-3.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc-1.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc-10.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc-2.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc-3.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc-4.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc-5.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc-6.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc-7.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc-8.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc-9.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_run-8.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-1.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-2.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-3.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-4.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-5.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-6.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict-7.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_strict_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c: Diito. + * gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c: Diito. + * gcc.target/riscv/rvv/autovec/scalable-1.c: Diito. + * gcc.target/riscv/rvv/autovec/series-1.c: Diito. + * gcc.target/riscv/rvv/autovec/series_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/slp-mask-1.c: Diito. + * gcc.target/riscv/rvv/autovec/slp-mask-run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-1.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-2.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-3.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-4.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-5.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-6.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load-7.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_load_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-1.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-2.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-3.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-4.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-5.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-6.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store-7.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-1.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-10.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-11.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-12.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-13.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-14.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-15.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-16.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-17.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-18.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-2.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-3.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-5.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-6.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-7.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-8.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect-9.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-11.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-12.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-13.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-14.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-15.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-16.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-17.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-18.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-8.c: Diito. + * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-9.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-10.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-11.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-12.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-7.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-8.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop-9.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-10.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-11.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-12.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-8.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run-9.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-1.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-10.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-11.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-12.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-2.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-3.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-4.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-5.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-6.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-7.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-8.c: Diito. + * gcc.target/riscv/rvv/autovec/ternop/ternop_run_zvfh-9.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/unop/vnot-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/v-1.c: Diito. + * gcc.target/riscv/rvv/autovec/v-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/pr110985.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls-vlmax/trailing_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-10.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-3.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-4.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-5.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-6.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-7.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-8.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-9.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/calling-convention-run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/vls/pr110994.c: Diito. + * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv32.c: Diito. + * gcc.target/riscv/rvv/autovec/vmv-imm-fixed-rv64.c: Diito. + * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Diito. + * gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: Diito. + * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Diito. + * gcc.target/riscv/rvv/autovec/vreinterpet-fixed.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/vec-avg-run.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-1.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-10.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-11.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-12.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-2.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-3.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-5.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-6.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-7.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-8.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-9.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-complicate-1.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-complicate-2.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-complicate-3.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-complicate-5.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-complicate-6.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-10.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-11.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-12.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Diito. + * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32f-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32f-2.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32f-3.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32x-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32x-2.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32x-3.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64d-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64d-2.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64d-3.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64d_zvl256b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64d_zvl512b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64f-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64f-2.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64f-3.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64f_zvl1024b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64f_zvl2048b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64f_zvl256b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64f_zvl4096b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64f_zvl512b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64x-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64x-2.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64x-3.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64x_zvl1024b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64x_zvl2048b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64x_zvl256b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64x_zvl4096b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zve64x_zvl512b-1.c: Diito. + * gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Diito. + * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Diito. + * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Diito. + * gcc.target/riscv/rvv/base/cpymem-1.c: Diito. + * gcc.target/riscv/rvv/base/cpymem-2.c: Diito. + * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Diito. + * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Diito. + * gcc.target/riscv/rvv/base/float-point-dynamic-frm-77.c: Diito. + * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: Diito. + * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: Diito. + * gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: Diito. + * gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: Diito. + * gcc.target/riscv/rvv/base/poly-selftest-1.c: Diito. + * gcc.target/riscv/rvv/base/pr110119-1.c: Diito. + * gcc.target/riscv/rvv/base/pr110119-2.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-0.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-1.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-10.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-2.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-3.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-4.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-5.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-6.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-7.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-8.c: Diito. + * gcc.target/riscv/rvv/base/pr111720-9.c: Diito. + * gcc.target/riscv/rvv/base/vf_avl-1.c: Diito. + * gcc.target/riscv/rvv/base/vf_avl-2.c: Diito. + * gcc.target/riscv/rvv/base/vf_avl-3.c: Diito. + * gcc.target/riscv/rvv/base/vf_avl-4.c: Diito. + * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Diito. + * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Diito. + * gcc.target/riscv/rvv/rvv.exp: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-100.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-101.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-103.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-104.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-105.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-106.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-107.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-108.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-109.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-17.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-18.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-19.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-20.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-21.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-22.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-24.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-25.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-26.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-31.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-32.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-33.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-34.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-37.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-38.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-39.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-40.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-41.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-42.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-43.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-45.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-49.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-52.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-53.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-54.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-55.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-57.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-58.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-59.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-60.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-61.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-62.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-63.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-64.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-73.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-74.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-75.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-78.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-79.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-80.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-81.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-85.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-87.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-97.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-98.c: Diito. + * gcc.target/riscv/rvv/vsetvl/avl_single-99.c: Diito. + * gcc.target/riscv/rvv/vsetvl/dump-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/ffload-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/ffload-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/ffload-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/ffload-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/ffload-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/ffload-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr108270.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109399.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109547.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109615.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109743-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109743-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109743-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109743-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109748.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109773-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109773-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr109974.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr111037-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr111037-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr111037-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr111037-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr111234.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr111255.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr111927.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr111947.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr112092-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr112092-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr112713-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr112713-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr112776.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr112813-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr112929-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr112988-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr113248.c: Diito. + * gcc.target/riscv/rvv/vsetvl/pr113696.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-17.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-18.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-19.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-20.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-21.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-22.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-23.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-24.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-25.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-26.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-27.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-30.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-31.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-34.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-35.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-36.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-38.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-39.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-40.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-41.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-42.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-43.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-44.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-46.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-25.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-26.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-27.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-28.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_call-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_call-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_call-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_call-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_complex_loop-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-17.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-18.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-19.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-20.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-21.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-22.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-23.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-24.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-25.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-26.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-27.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-28.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_block-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_single_vtype-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: Diito. + * gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: Diito. + * gcc.target/riscv/rvv/vsetvl/wredsum_vlmax.c: Diito. + * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test. + * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test. + * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test. + * gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test. + * gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test. + * gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test. + +2024-03-01 Jakub Jelinek + + PR middle-end/114156 + * gcc.dg/bitint-96.c: New test. + 2024-02-29 David Malcolm PR analyzer/114159 -- cgit v1.1 From 96bad6c06d0108014a2b0e5d0921cb18066bb789 Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Sat, 2 Mar 2024 10:03:06 +0100 Subject: AVR: target/114100 - Factor in -mtiny-stack in frame pointer adjustments gcc/ PR target/114100 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust the low part of the frame pointer with 8-bit stack pointer. --- gcc/config/avr/avr.cc | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 94ef7c5..d39d670 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -8983,14 +8983,17 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, && frame_pointer_needed && REGNO (xop[0]) == FRAME_POINTER_REGNUM) { - rtx xval16 = simplify_gen_subreg (HImode, xval, imode, i); - if (xval16 == const1_rtx || xval16 == constm1_rtx) + if (AVR_HAVE_8BIT_SP) + { + avr_asm_len ("subi %A0,%n2", xop, plen, 1); + return; + } + else if (xop[2] == const1_rtx || xop[2] == constm1_rtx) { - avr_asm_len ((code == PLUS) == (xval16 == const1_rtx) + avr_asm_len (xop[2] == const1_rtx ? "ld __tmp_reg__,%a0+" : "ld __tmp_reg__,-%a0", xop, plen, 1); - i++; - continue; + return; } } -- cgit v1.1 From c8d12343a9417055f3fc89bbdbb6e0ea508bcca2 Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Sat, 2 Mar 2024 12:26:04 +0100 Subject: AVR: Adjust some comments. gcc/ * config/avr/avr.cc: Adjust some comments. --- gcc/config/avr/avr.cc | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index d39d670..e312ddf 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -1517,7 +1517,7 @@ avr_outgoing_args_size (void) } -/* Implement TARGET_STARTING_FRAME_OFFSET. */ +/* Implement `TARGET_STARTING_FRAME_OFFSET'. */ /* This is the offset from the frame pointer register to the first stack slot that contains a variable living in the frame. */ @@ -1583,6 +1583,7 @@ avr_allocate_stack_slots_for_args (void) } +/* Implement `TARGET_CAN_ELIMINATE'. */ /* Return true if register FROM can be eliminated via register TO. */ static bool @@ -1604,6 +1605,8 @@ avr_warn_func_return (tree decl) return !avr_naked_function_p (decl); } + +/* Worker function for `INITIAL_ELIMINATION_OFFSET'. */ /* Compute offset between arg_pointer and frame_pointer. */ int @@ -1676,6 +1679,7 @@ avr_build_builtin_va_list (void) } +/* Worker function for `INCOMING_RETURN_ADDR_RTX'. */ /* Return contents of MEM at frame pointer + stack size + 1 (+2 if 3-byte PC). This is return address of function. */ @@ -2990,7 +2994,7 @@ avr_asm_function_end_prologue (FILE *file) } -/* Implement `EPILOGUE_USES'. */ +/* Worker function for `EPILOGUE_USES'. */ int avr_epilogue_uses (int regno ATTRIBUTE_UNUSED) @@ -3934,8 +3938,7 @@ avr_print_operand (FILE *file, rtx x, int code) } -/* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */ - +/* Implement `TARGET_USE_BY_PIECES_INFRASTRUCTURE_P'. */ /* Prefer sequence of loads/stores for moves of size upto two - two pairs of load/store instructions are always better than the 5 instruction sequence for a loop (1 instruction @@ -11302,7 +11305,8 @@ avr_addr_space_diagnose_usage (addr_space_t as, location_t loc) (void) avr_addr_space_supported_p (as, loc); } -/* Implement `TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID. Zero is a valid + +/* Implement `TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID'. Zero is a valid address in all address spaces. Even in ADDR_SPACE_FLASH1 etc.., a zero address is valid and means 0x0000, where RAMPZ is set to the appropriate segment value. */ @@ -11313,6 +11317,7 @@ avr_addr_space_zero_address_valid (addr_space_t) return true; } + /* Look if DECL shall be placed in program memory space by means of attribute `progmem' or some address-space qualifier. Return non-zero if DECL is data that must end up in Flash and @@ -13496,7 +13501,8 @@ jump_over_one_insn_p (rtx_insn *insn, rtx dest) && avr_2word_insn_p (next_active_insn (insn)))); } -/* Implement TARGET_HARD_REGNO_NREGS. CCmode is four units for historical + +/* Implement `TARGET_HARD_REGNO_NREGS'. CCmode is four units for historical reasons. If this hook is not defined, TARGET_HARD_REGNO_NREGS reports that CCmode requires four registers. Define this hook to allow CCmode to fit in a single REG_CC. For @@ -13513,7 +13519,7 @@ avr_hard_regno_nregs (unsigned int regno, machine_mode mode) } -/* Implement TARGET_HARD_REGNO_MODE_OK. On the enhanced core, anything +/* Implement `TARGET_HARD_REGNO_MODE_OK'. On the enhanced core, anything larger than 1 byte must start in even numbered register for "movw" to work (this way we don't have to check for odd registers everywhere). */ @@ -13551,7 +13557,7 @@ avr_hard_regno_mode_ok (unsigned int regno, machine_mode mode) } -/* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */ +/* Implement `TARGET_HARD_REGNO_CALL_PART_CLOBBERED'. */ static bool avr_hard_regno_call_part_clobbered (unsigned, unsigned regno, @@ -14241,6 +14247,7 @@ avr_out_sbxx_branch (rtx_insn *insn, rtx operands[]) return ""; } + /* Worker function for `TARGET_ASM_CONSTRUCTOR'. */ static void @@ -14261,7 +14268,7 @@ avr_asm_out_dtor (rtx symbol, int priority) } -/* Worker function for `TARGET_RETURN_IN_MEMORY'. */ +/* Implement `TARGET_RETURN_IN_MEMORY'. */ static bool avr_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) @@ -14584,7 +14591,6 @@ avr_convert_to_type (tree type, tree expr) /* Implement `TARGET_LEGITIMATE_COMBINED_INSN'. */ - /* PR78883: Filter out paradoxical SUBREGs of MEM which are not handled properly by following passes. As INSN_SCHEDULING is off and hence general_operand accepts such expressions, ditch them now. */ @@ -15984,6 +15990,8 @@ avr_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *arg, return NULL_TREE; } + +/* Implement `TARGET_MD_ASM_ADJUST'. */ /* Prepend to CLOBBERS hard registers that are automatically clobbered for an asm. We do this for CC_REGNUM to maintain source compatibility with the original cc0-based compiler. */ -- cgit v1.1 From 9ca5e579d3e1acdbf0519f7a43928ecc9bb0193f Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Sat, 2 Mar 2024 13:37:00 +0100 Subject: AVR: Use REG_ constants instead of magic numbers . There are some places where avr.cc uses magic numbers like 17 that are actually register numbers. This patch defines constants like REG_17 and uses them instead of the magic numbers when a register number is meant. gcc/ * config/avr/avr.md (REG_0, ... REG_36): New define_constants. * config/avr/avr.cc: Use them instead of magic numbers when it means a register number. --- gcc/config/avr/avr.cc | 58 ++++++++++++++++++++++++++------------------------- gcc/config/avr/avr.md | 33 +++++++++++++++++++---------- 2 files changed, 52 insertions(+), 39 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index e312ddf..5c71c7f 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -171,10 +171,10 @@ static bool avr_rtx_costs (rtx, machine_mode, int, int, int *, bool); /* Allocate registers from r25 to r8 for parameters for function calls. */ -#define FIRST_CUM_REG 26 +#define FIRST_CUM_REG REG_26 /* Last call saved register */ -#define LAST_CALLEE_SAVED_REG (AVR_TINY ? 19 : 17) +#define LAST_CALLEE_SAVED_REG (AVR_TINY ? REG_19 : REG_17) /* Implicit target register of LPM instruction (R0) */ extern GTY(()) rtx lpm_reg_rtx; @@ -197,8 +197,8 @@ extern GTY(()) rtx cc_reg_rtx; rtx cc_reg_rtx; /* RTXs for all general purpose registers as QImode */ -extern GTY(()) rtx all_regs_rtx[32]; -rtx all_regs_rtx[32]; +extern GTY(()) rtx all_regs_rtx[REG_32]; +rtx all_regs_rtx[REG_32]; /* SREG, the processor status */ extern GTY(()) rtx sreg_rtx; @@ -542,7 +542,7 @@ avr_casei_sequence_check_operands (rtx *xop) if (AVR_HAVE_EIJMP_EICALL // The last clobber op of the tablejump. - && xop[8] == all_regs_rtx[24]) + && xop[8] == all_regs_rtx[REG_24]) { // $6 is: (subreg:SI ($5) 0) sub_5 = xop[6]; @@ -1171,7 +1171,7 @@ avr_init_machine_status (void) void avr_init_expanders (void) { - for (int regno = 0; regno < 32; regno ++) + for (int regno = REG_0; regno < REG_32; regno ++) all_regs_rtx[regno] = gen_rtx_REG (QImode, regno); lpm_reg_rtx = all_regs_rtx[LPM_REGNO]; @@ -1549,7 +1549,7 @@ avr_regs_to_save (HARD_REG_SET *set) || cfun->machine->is_OS_main) return 0; - for (int reg = 0; reg < 32; reg++) + for (int reg = REG_0; reg < REG_32; reg++) { /* Do not push/pop __tmp_reg__, __zero_reg__, as well as any global register variables. */ @@ -2300,9 +2300,9 @@ avr_pass_fuse_add::execute (function *func) FOR_EACH_BB_FN (bb, func) { - Ldi_Insn prev_ldi_insns[32]; - Add_Insn prev_add_insns[32]; - Mem_Insn prev_mem_insns[32]; + Ldi_Insn prev_ldi_insns[REG_32]; + Add_Insn prev_add_insns[REG_32]; + Mem_Insn prev_mem_insns[REG_32]; rtx_insn *insn, *curr; avr_dump ("\n;; basic block %d\n\n", bb->index); @@ -2484,7 +2484,7 @@ avr_incoming_return_addr_rtx (void) static int avr_hregs_split_reg (HARD_REG_SET *set) { - for (int regno = 0; regno < 32; regno++) + for (int regno = REG_0; regno < REG_32; regno++) if (TEST_HARD_REG_BIT (*set, regno)) { // Don't remove a register from *SET which might indicate that @@ -2620,9 +2620,9 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) first_reg = (LAST_CALLEE_SAVED_REG + 1) - (live_seq - 2); - for (reg = 29, offset = -live_seq + 1; + for (reg = REG_29, offset = -live_seq + 1; reg >= first_reg; - reg = (reg == 28 ? LAST_CALLEE_SAVED_REG : reg - 1), ++offset) + reg = (reg == REG_28 ? LAST_CALLEE_SAVED_REG : reg - 1), ++offset) { rtx m, r; @@ -2636,7 +2636,7 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) } else /* !minimize */ { - for (int reg = 0; reg < 32; ++reg) + for (int reg = REG_0; reg < REG_32; ++reg) if (TEST_HARD_REG_BIT (set, reg)) emit_push_byte (reg, true); @@ -3795,7 +3795,7 @@ avr_print_operand (FILE *file, rtx x, int code) { if (x == zero_reg_rtx) fprintf (file, "__zero_reg__"); - else if (code == 'r' && REGNO (x) < 32) + else if (code == 'r' && REGNO (x) < REG_32) fprintf (file, "%d", (int) REGNO (x)); else fprintf (file, "%s", reg_names[REGNO (x) + abcd]); @@ -4136,7 +4136,9 @@ avr_asm_final_postscan_insn (FILE *stream, rtx_insn *insn, rtx *, int) int avr_function_arg_regno_p (int r) { - return AVR_TINY ? IN_RANGE (r, 20, 25) : IN_RANGE (r, 8, 25); + return AVR_TINY + ? IN_RANGE (r, REG_20, REG_25) + : IN_RANGE (r, REG_8, REG_25); } @@ -4148,7 +4150,7 @@ void avr_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, tree fndecl ATTRIBUTE_UNUSED) { - cum->nregs = AVR_TINY ? 6 : 18; + cum->nregs = 1 + AVR_TINY ? REG_25 - REG_20 : REG_25 - REG_8; cum->regno = FIRST_CUM_REG; cum->has_stack_args = 0; if (!libname && stdarg_p (fntype)) @@ -4216,7 +4218,7 @@ avr_function_arg_advance (cumulative_args_t cum_v, a function must not pass arguments in call-saved regs in order to get tail-called. */ - if (cum->regno >= 8 + if (cum->regno >= REG_8 && cum->nregs >= 0 && !call_used_or_fixed_reg_p (cum->regno)) { @@ -4233,7 +4235,7 @@ avr_function_arg_advance (cumulative_args_t cum_v, user has fixed a GPR needed to pass an argument, an (implicit) function call will clobber that fixed register. See PR45099 for an example. */ - if (cum->regno >= 8 + if (cum->regno >= REG_8 && cum->nregs >= 0) { for (int regno = cum->regno; regno < cum->regno + bytes; regno++) @@ -4348,7 +4350,7 @@ avr_find_unused_d_reg (rtx_insn *insn, rtx exclude) bool isr_p = (avr_interrupt_function_p (current_function_decl) || avr_signal_function_p (current_function_decl)); - for (int regno = 16; regno < 32; regno++) + for (int regno = REG_16; regno < REG_32; regno++) { rtx reg = all_regs_rtx[regno]; @@ -7117,7 +7119,7 @@ avr_out_compare64 (rtx_insn *insn, rtx *op, int *plen) { rtx xop[3]; - xop[0] = gen_rtx_REG (DImode, 18); + xop[0] = gen_rtx_REG (DImode, ACC_A); xop[1] = op[0]; xop[2] = op[1]; @@ -7340,7 +7342,7 @@ out_shift_with_cnt (const char *templ, rtx_insn *insn, rtx operands[], /* No scratch register available, use one from LD_REGS (saved in __tmp_reg__) that doesn't overlap with registers to shift. */ - op[3] = all_regs_rtx[((REGNO (op[0]) - 1) & 15) + 16]; + op[3] = all_regs_rtx[((REGNO (op[0]) - 1) & 15) + REG_16]; op[4] = tmp_reg_rtx; saved_in_tmp = true; @@ -13712,8 +13714,8 @@ output_reload_in_const (rtx *op, rtx clobber_reg, int *len, bool clear_p) /* (REG:SI 14) is special: It's neither in LD_REGS nor in NO_LD_REGS but has some subregs that are in LD_REGS. Use the MSB (REG:QI 17). */ - if (REGNO (dest) < 16 - && REGNO (dest) + GET_MODE_SIZE (mode) > 16) + if (REGNO (dest) < REG_16 + && REGNO (dest) + GET_MODE_SIZE (mode) > REG_16) { clobber_reg = all_regs_rtx[REGNO (dest) + n_bytes - 1]; } @@ -14093,7 +14095,7 @@ avr_conditional_register_usage (void) - R0-R15 are not available in Tiny Core devices - R16 and R17 are fixed registers. */ - for (size_t i = 0; i <= 17; i++) + for (size_t i = REG_0; i <= REG_17; i++) { fixed_regs[i] = 1; call_used_regs[i] = 1; @@ -14103,7 +14105,7 @@ avr_conditional_register_usage (void) - R18, R19, R20 and R21 are the callee saved registers in Tiny Core devices */ - for (size_t i = 18; i <= LAST_CALLEE_SAVED_REG; i++) + for (size_t i = REG_18; i <= LAST_CALLEE_SAVED_REG; i++) { call_used_regs[i] = 0; } @@ -15180,9 +15182,9 @@ avr_map_decompose (unsigned int f, const avr_map_op_t *g, bool val_const_p) fake values. Mimic effect of reloading xop[3]: Unused operands are mapped to 0 and used operands are reloaded to xop[0]. */ - xop[0] = all_regs_rtx[24]; + xop[0] = all_regs_rtx[REG_24]; xop[1] = gen_int_mode (f_ginv.map, SImode); - xop[2] = all_regs_rtx[25]; + xop[2] = all_regs_rtx[REG_25]; xop[3] = val_used_p ? xop[0] : const0_rtx; avr_out_insert_bits (xop, &f_ginv.cost); diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 8f6bc28..028f9f1 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -51,22 +51,33 @@ ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL. ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL. +;; Used in avr.cc to avoid magic numbers for register numbers. +(define_constants + [(REG_0 0) (REG_1 1) (REG_2 2) + (REG_8 8) (REG_9 9) (REG_10 10) (REG_11 11) + (REG_12 12) (REG_13 13) (REG_14 14) (REG_15 15) + (REG_16 16) (REG_17 17) (REG_18 18) (REG_19 19) + (REG_20 20) (REG_21 21) (REG_22 22) (REG_23 23) + (REG_24 24) (REG_25 25) (REG_26 26) (REG_27 27) + (REG_28 28) (REG_29 29) (REG_30 30) (REG_31 31) + (REG_32 32) (REG_36 36) + ]) (define_constants - [(REG_X 26) - (REG_Y 28) - (REG_Z 30) - (REG_W 24) - (REG_SP 32) - (REG_CC 36) - (LPM_REGNO 0) ; implicit target register of LPM - (TMP_REGNO 0) ; temporary register r0 - (ZERO_REGNO 1) ; zero register r1 + [(REG_X REG_26) + (REG_Y REG_28) + (REG_Z REG_30) + (REG_W REG_24) + (REG_SP REG_32) + (REG_CC REG_36) + (LPM_REGNO REG_0) ; implicit target register of LPM + (TMP_REGNO REG_0) ; temporary register r0 + (ZERO_REGNO REG_1) ; zero register r1 ]) (define_constants - [(TMP_REGNO_TINY 16) ; r16 is temp register for AVR_TINY - (ZERO_REGNO_TINY 17) ; r17 is zero register for AVR_TINY + [(TMP_REGNO_TINY REG_16) ; r16 is temp register for AVR_TINY + (ZERO_REGNO_TINY REG_17) ; r17 is zero register for AVR_TINY ]) (define_c_enum "unspec" -- cgit v1.1 From ef1b7885843d73c94313f5e693fa48ecd793043e Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Sun, 3 Mar 2024 00:17:08 +0000 Subject: Daily bump. --- gcc/ChangeLog | 16 ++++++++++++++++ gcc/DATESTAMP | 2 +- 2 files changed, 17 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 845ae73..dd72057 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2024-03-02 Georg-Johann Lay + + * config/avr/avr.md (REG_0, ... REG_36): New define_constants. + * config/avr/avr.cc: Use them instead of magic numbers when it + means a register number. + +2024-03-02 Georg-Johann Lay + + * config/avr/avr.cc: Adjust some comments. + +2024-03-02 Georg-Johann Lay + + PR target/114100 + * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust + the low part of the frame pointer with 8-bit stack pointer. + 2024-03-01 Patrick Palka PR c++/104919 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index e129c99..00dd9af 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240302 +20240303 -- cgit v1.1 From 623f52775e677bb3d6e9e7ef97196741dd904b1e Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Sun, 3 Mar 2024 02:26:37 +0100 Subject: d: Fix gdc -O2 -mavx generates misaligned vmovdqa instruction [PR114171] PR d/114171 gcc/d/ChangeLog: * d-codegen.cc (lower_struct_comparison): Keep alignment of original type in reinterpret cast for comparison. gcc/testsuite/ChangeLog: * gdc.dg/torture/pr114171.d: New test. --- gcc/d/d-codegen.cc | 1 + gcc/testsuite/gdc.dg/torture/pr114171.d | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 gcc/testsuite/gdc.dg/torture/pr114171.d (limited to 'gcc') diff --git a/gcc/d/d-codegen.cc b/gcc/d/d-codegen.cc index 5bc2339..43d7739f 100644 --- a/gcc/d/d-codegen.cc +++ b/gcc/d/d-codegen.cc @@ -1006,6 +1006,7 @@ lower_struct_comparison (tree_code code, StructDeclaration *sd, if (tmode == NULL_TREE) tmode = make_unsigned_type (GET_MODE_BITSIZE (mode.require ())); + tmode = build_aligned_type (tmode, TYPE_ALIGN (stype)); t1ref = build_vconvert (tmode, t1ref); t2ref = build_vconvert (tmode, t2ref); diff --git a/gcc/testsuite/gdc.dg/torture/pr114171.d b/gcc/testsuite/gdc.dg/torture/pr114171.d new file mode 100644 index 0000000..0f9ffca --- /dev/null +++ b/gcc/testsuite/gdc.dg/torture/pr114171.d @@ -0,0 +1,29 @@ +// { dg-do run } +// { dg-additional-options "-mavx" { target avx_runtime } } +// { dg-skip-if "needs gcc/config.d" { ! d_runtime } } +import gcc.builtins; + +struct S1 +{ + string label; +} + +struct S2 +{ + ulong pad; + S1 label; +} + +pragma(inline, false) +auto newitem() +{ + void *p = __builtin_malloc(S2.sizeof); + __builtin_memset(p, 0, S2.sizeof); + return cast(S2*) p; +} + +int main() +{ + auto bn = newitem(); + return bn.label is S1.init ? 0 : 1; +} -- cgit v1.1 From 4ff8ffe7331cf174668cf5c729fd68ff327ab014 Mon Sep 17 00:00:00 2001 From: Oleg Endo Date: Sun, 3 Mar 2024 14:58:58 +0900 Subject: SH: Fix 101737 gcc/ChangeLog: PR target/101737 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input is not an insn, but e.g. a code label. --- gcc/config/sh/sh.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc index 27777c4..ef3c2e6 100644 --- a/gcc/config/sh/sh.cc +++ b/gcc/config/sh/sh.cc @@ -11767,7 +11767,8 @@ sh_insn_operands_modified_between_p (rtx_insn* operands_insn, bool sh_is_nott_insn (const rtx_insn* i) { - return i != NULL && GET_CODE (PATTERN (i)) == SET + return i != NULL_RTX && PATTERN (i) != NULL_RTX + && GET_CODE (PATTERN (i)) == SET && t_reg_operand (XEXP (PATTERN (i), 0), VOIDmode) && negt_reg_operand (XEXP (PATTERN (i), 1), VOIDmode); } -- cgit v1.1 From 1b9fb7c56e09983898efa350928665ac6b91620e Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Sun, 3 Mar 2024 10:21:20 +0100 Subject: AVR: Fix a typo in avr.cc. gcc/ * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo from r14-9273. --- gcc/config/avr/avr.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 5c71c7f..b86f431 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -170,7 +170,8 @@ static struct machine_function *avr_init_machine_status (void); static bool avr_rtx_costs (rtx, machine_mode, int, int, int *, bool); -/* Allocate registers from r25 to r8 for parameters for function calls. */ +/* Allocate registers from r25 to r8 for parameters for function calls + resp. r25 to r20 for reduced Tiny. */ #define FIRST_CUM_REG REG_26 /* Last call saved register */ @@ -4150,7 +4151,7 @@ void avr_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, tree fndecl ATTRIBUTE_UNUSED) { - cum->nregs = 1 + AVR_TINY ? REG_25 - REG_20 : REG_25 - REG_8; + cum->nregs = AVR_TINY ? 1 + REG_25 - REG_20 : 1 + REG_25 - REG_8; cum->regno = FIRST_CUM_REG; cum->has_stack_args = 0; if (!libname && stdarg_p (fntype)) -- cgit v1.1 From dae3456965064c9664c097c785ae9bf9fa203fa0 Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Sun, 3 Mar 2024 13:01:24 +0100 Subject: AVR: ad target/92792 - Remove insn attribute "cc" and its (dead) uses. The backend has remains of cc0 condition code. Unfortunately, all that information is useless with CCmode, and their use was removed with the removal of NOTICE_UPDATE_CC in PR92729 with r12-226 and r12-327. gcc/ PR target/92729 * config/avr/avr.md (define_attr "cc"): Remove. * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument from prototype. * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and its uses. Add insn argument. (avr_out_plus_symbol): Remove pcc argument and its uses. (avr_out_plus): Remove pcc argument and its uses. Adjust calls of avr_out_plus_symbol and avr_out_plus_1. (avr_out_round): Adjust call of avr_out_plus. --- gcc/config/avr/avr-protos.h | 2 +- gcc/config/avr/avr.cc | 61 +++++++++++---------------------------------- gcc/config/avr/avr.md | 4 --- 3 files changed, 16 insertions(+), 51 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h index 064a3d2..f4f3ffd 100644 --- a/gcc/config/avr/avr-protos.h +++ b/gcc/config/avr/avr-protos.h @@ -93,7 +93,7 @@ extern bool avr_split_tiny_move (rtx_insn *insn, rtx *operands); extern void avr_output_addr_vec (rtx_insn*, rtx); extern const char *avr_out_sbxx_branch (rtx_insn *insn, rtx operands[]); extern const char* avr_out_bitop (rtx, rtx*, int*); -extern const char* avr_out_plus (rtx, rtx*, int* =NULL, int* =NULL, bool =true); +extern const char* avr_out_plus (rtx, rtx*, int* =NULL, bool =true); extern const char* avr_out_round (rtx_insn *, rtx*, int* =NULL); extern const char* avr_out_addto_sp (rtx*, int*); extern const char* avr_out_xload (rtx_insn *, rtx*, int*); diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index b86f431..44d6e14 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -8799,6 +8799,7 @@ lshrsi3_out (rtx_insn *insn, rtx operands[], int *len) /* Output addition of register XOP[0] and compile time constant XOP[2]. + INSN is a single_set insn or an insn pattern. CODE == PLUS: perform addition by using ADD instructions or CODE == MINUS: perform addition by using SUB instructions: @@ -8811,7 +8812,6 @@ lshrsi3_out (rtx_insn *insn, rtx operands[], int *len) If PLEN == NULL, print assembler instructions to perform the operation; otherwise, set *PLEN to the length of the instruction sequence (in words) printed with PLEN == NULL. XOP[3] is an 8-bit scratch register or NULL_RTX. - Set *PCC to effect on cc0 according to respective CC_* insn attribute. CODE_SAT == UNKNOWN: Perform ordinary, non-saturating operation. CODE_SAT != UNKNOWN: Perform operation and saturate according to CODE_SAT. @@ -8825,7 +8825,7 @@ lshrsi3_out (rtx_insn *insn, rtx operands[], int *len) fixed-point rounding, cf. `avr_out_round'. */ static void -avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, +avr_out_plus_1 (rtx /*insn*/, rtx *xop, int *plen, enum rtx_code code, enum rtx_code code_sat, int sign, bool out_label) { /* MODE of the operation. */ @@ -8861,8 +8861,6 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, if (REG_P (xop[2])) { - *pcc = MINUS == code ? (int) CC_SET_CZN : (int) CC_CLOBBER; - for (int i = 0; i < n_bytes; i++) { /* We operate byte-wise on the destination. */ @@ -8888,21 +8886,13 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, goto saturate; } - /* Except in the case of ADIW with 16-bit register (see below) - addition does not set cc0 in a usable way. */ - - *pcc = (MINUS == code) ? CC_SET_CZN : CC_CLOBBER; - if (CONST_FIXED_P (xval)) xval = avr_to_int_mode (xval); /* Adding/Subtracting zero is a no-op. */ if (xval == const0_rtx) - { - *pcc = CC_NONE; - return; - } + return; if (MINUS == code) xval = simplify_unary_operation (NEG, imode, xval, imode); @@ -8947,9 +8937,6 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, /* To get usable cc0 no low-bytes must have been skipped. */ - if (i && !started) - *pcc = CC_CLOBBER; - if (!started && i % 2 == 0 && i + 2 <= n_bytes @@ -8968,9 +8955,6 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, started = true; avr_asm_len (code == PLUS ? "adiw %0,%1" : "sbiw %0,%1", op, plen, 1); - - if (n_bytes == 2 && PLUS == code) - *pcc = CC_SET_CZN; } i++; @@ -9018,7 +9002,6 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, { avr_asm_len ((code == PLUS) ^ (val8 == 1) ? "dec %0" : "inc %0", op, plen, 1); - *pcc = CC_CLOBBER; break; } @@ -9077,8 +9060,6 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, if (UNKNOWN == code_sat) return; - *pcc = (int) CC_CLOBBER; - /* Vanilla addition/subtraction is done. We are left with saturation. We have to compute A = A B where A is a register and @@ -9298,7 +9279,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, /* Output addition/subtraction of register XOP[0] and a constant XOP[2] that - is ont a compile-time constant: + is not a compile-time constant: XOP[0] = XOP[0] +/- XOP[2] @@ -9306,7 +9287,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, are additions/subtraction for pointer modes, i.e. HImode and PSImode. */ static const char * -avr_out_plus_symbol (rtx *xop, enum rtx_code code, int *plen, int *pcc) +avr_out_plus_symbol (rtx *xop, enum rtx_code code, int *plen) { machine_mode mode = GET_MODE (xop[0]); @@ -9314,8 +9295,6 @@ avr_out_plus_symbol (rtx *xop, enum rtx_code code, int *plen, int *pcc) gcc_assert (mode == HImode || mode == PSImode); - *pcc = MINUS == code ? (int) CC_SET_CZN : (int) CC_SET_N; - avr_asm_len (PLUS == code ? "subi %A0,lo8(-(%2))" CR_TAB "sbci %B0,hi8(-(%2))" : "subi %A0,lo8(%2)" CR_TAB "sbci %B0,hi8(%2)", @@ -9342,19 +9321,15 @@ avr_out_plus_symbol (rtx *xop, enum rtx_code code, int *plen, int *pcc) If PLEN == NULL output the instructions. If PLEN != NULL set *PLEN to the length of the sequence in words. - PCC is a pointer to store the instructions' effect on cc0. - PCC may be NULL. - - PLEN and PCC default to NULL. + PLEN defaults to NULL. OUT_LABEL defaults to TRUE. For a description, see AVR_OUT_PLUS_1. Return "" */ const char * -avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label) +avr_out_plus (rtx insn, rtx *xop, int *plen, bool out_label) { - int cc_plus, cc_minus, cc_dummy; int len_plus, len_minus; rtx op[4]; rtx xpattern = INSN_P (insn) ? single_set (as_a (insn)) : insn; @@ -9367,9 +9342,6 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label) = (PLUS == code_sat || SS_PLUS == code_sat || US_PLUS == code_sat ? PLUS : MINUS); - if (!pcc) - pcc = &cc_dummy; - /* PLUS and MINUS don't saturate: Use modular wrap-around. */ if (PLUS == code_sat || MINUS == code_sat) @@ -9377,7 +9349,7 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label) if (n_bytes <= 4 && REG_P (xop[2])) { - avr_out_plus_1 (xop, plen, code, pcc, code_sat, 0, out_label); + avr_out_plus_1 (insn, xop, plen, code, code_sat, 0, out_label); return ""; } @@ -9393,7 +9365,7 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label) && !CONST_INT_P (xop[2]) && !CONST_FIXED_P (xop[2])) { - return avr_out_plus_symbol (xop, code, plen, pcc); + return avr_out_plus_symbol (xop, code, plen); } op[0] = avr_to_int_mode (xop[0]); @@ -9420,18 +9392,15 @@ avr_out_plus (rtx insn, rtx *xop, int *plen, int *pcc, bool out_label) /* Work out the shortest sequence. */ - avr_out_plus_1 (op, &len_minus, MINUS, &cc_minus, code_sat, sign, out_label); - avr_out_plus_1 (op, &len_plus, PLUS, &cc_plus, code_sat, sign, out_label); + avr_out_plus_1 (insn, op, &len_minus, MINUS, code_sat, sign, out_label); + avr_out_plus_1 (insn, op, &len_plus, PLUS, code_sat, sign, out_label); if (plen) - { - *plen = (len_minus <= len_plus) ? len_minus : len_plus; - *pcc = (len_minus <= len_plus) ? cc_minus : cc_plus; - } + *plen = (len_minus <= len_plus) ? len_minus : len_plus; else if (len_minus <= len_plus) - avr_out_plus_1 (op, NULL, MINUS, pcc, code_sat, sign, out_label); + avr_out_plus_1 (insn, op, NULL, MINUS, code_sat, sign, out_label); else - avr_out_plus_1 (op, NULL, PLUS, pcc, code_sat, sign, out_label); + avr_out_plus_1 (insn, op, NULL, PLUS, code_sat, sign, out_label); return ""; } @@ -10560,7 +10529,7 @@ avr_out_round (rtx_insn *insn ATTRIBUTE_UNUSED, rtx *xop, int *plen) op[0] = xop[0]; op[1] = xop[1]; op[2] = xadd; - avr_out_plus (xpattern, op, plen_add, NULL, false /* Don't print "0:" */); + avr_out_plus (xpattern, op, plen_add, false /* Don't print "0:" */); avr_asm_len ("rjmp 1f" CR_TAB "0:", NULL, plen_add, 1); diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 028f9f1..7f73587 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -116,10 +116,6 @@ (include "predicates.md") (include "constraints.md") -;; Condition code settings. -(define_attr "cc" "none,set_czn,set_zn,set_vzn,set_n,compare,clobber, - plus,ldi" - (const_string "none")) (define_attr "type" "branch,branch1,arith,xcall" (const_string "arith")) -- cgit v1.1 From c0f5b6caff669037444506cb6008a378356ec209 Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Sun, 3 Mar 2024 18:15:58 +0100 Subject: AVR: ad target/114100 - Don't print unused frame pointer adjustments. Without -mfuse-add, when fake reg+offset addressing is used, the output routines are saving some instructions when the base reg is unused after. This patch adds that optimization for the case when the base is the frame pointer and the frame pointer adjustments are split away from the move insn by -mfuse-add in .split2. Direct usage of reg_unused_after is not possible because that function looks at the destination of the current insn, which won't work for offsetting the frame pointer in printing PLUS code. It can use an extended version of _reg_unused_after though. gcc/ PR target/114100 * config/avr/avr-protos.h (_reg_unused_after): Remove proto. * config/avr/avr.cc (_reg_unused_after): Make static. And add 3rd argument to skip the current insn. (reg_unused_after): Adjust call of reg_unused_after. (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output unneeded frame pointer adjustments. --- gcc/config/avr/avr-protos.h | 1 - gcc/config/avr/avr.cc | 36 +++++++++++++++++++++--------------- 2 files changed, 21 insertions(+), 16 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h index f4f3ffd..3e19409 100644 --- a/gcc/config/avr/avr-protos.h +++ b/gcc/config/avr/avr-protos.h @@ -110,7 +110,6 @@ extern const char* avr_out_reload_inpsi (rtx*, rtx, int*); extern const char* avr_out_lpm (rtx_insn *, rtx*, int*); extern void avr_notice_update_cc (rtx body, rtx_insn *insn); extern int reg_unused_after (rtx_insn *insn, rtx reg); -extern int _reg_unused_after (rtx_insn *insn, rtx reg); extern int avr_jump_mode (rtx x, rtx_insn *insn); extern int test_hard_reg_class (enum reg_class rclass, rtx x); extern int jump_over_one_insn_p (rtx_insn *insn, rtx dest); diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 44d6e14..7df2143 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -163,6 +163,7 @@ static int avr_operand_rtx_cost (rtx, machine_mode, enum rtx_code, int, bool); static void output_reload_in_const (rtx *, rtx, int *, bool); static struct machine_function *avr_init_machine_status (void); +static int _reg_unused_after (rtx_insn *insn, rtx reg, bool look_at_insn); /* Prototypes for hook implementors if needed before their implementation. */ @@ -8825,7 +8826,7 @@ lshrsi3_out (rtx_insn *insn, rtx operands[], int *len) fixed-point rounding, cf. `avr_out_round'. */ static void -avr_out_plus_1 (rtx /*insn*/, rtx *xop, int *plen, enum rtx_code code, +avr_out_plus_1 (rtx insn, rtx *xop, int *plen, enum rtx_code code, enum rtx_code code_sat, int sign, bool out_label) { /* MODE of the operation. */ @@ -8973,6 +8974,10 @@ avr_out_plus_1 (rtx /*insn*/, rtx *xop, int *plen, enum rtx_code code, && frame_pointer_needed && REGNO (xop[0]) == FRAME_POINTER_REGNUM) { + if (INSN_P (insn) + && _reg_unused_after (as_a (insn), xop[0], false)) + return; + if (AVR_HAVE_8BIT_SP) { avr_asm_len ("subi %A0,%n2", xop, plen, 1); @@ -10818,31 +10823,32 @@ int reg_unused_after (rtx_insn *insn, rtx reg) { return (dead_or_set_p (insn, reg) - || (REG_P (reg) && _reg_unused_after (insn, reg))); + || (REG_P (reg) && _reg_unused_after (insn, reg, true))); } -/* Return nonzero if REG is not used after INSN. +/* A helper for the previous function. + Return nonzero if REG is not used after INSN. We assume REG is a reload reg, and therefore does not live past labels. It may live past calls or jumps though. */ int -_reg_unused_after (rtx_insn *insn, rtx reg) +_reg_unused_after (rtx_insn *insn, rtx reg, bool look_at_insn) { - enum rtx_code code; - rtx set; - - /* If the reg is set by this instruction, then it is safe for our - case. Disregard the case where this is a store to memory, since - we are checking a register used in the store address. */ - set = single_set (insn); - if (set && !MEM_P (SET_DEST (set)) - && reg_overlap_mentioned_p (reg, SET_DEST (set))) - return 1; + if (look_at_insn) + { + /* If the reg is set by this instruction, then it is safe for our + case. Disregard the case where this is a store to memory, since + we are checking a register used in the store address. */ + rtx set = single_set (insn); + if (set && !MEM_P (SET_DEST (set)) + && reg_overlap_mentioned_p (reg, SET_DEST (set))) + return 1; + } while ((insn = NEXT_INSN (insn))) { rtx set; - code = GET_CODE (insn); + enum rtx_code code = GET_CODE (insn); #if 0 /* If this is a label that existed before reload, then the register -- cgit v1.1 From 318e0d44fe66ade59edb16a94565b3bfdc1883c6 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Sun, 3 Mar 2024 20:40:45 +0100 Subject: alpha: Introduce UMUL_HIGHPART rtx_code [PR113720] umuldi3_highpart expander does: if (REG_P (operands[2])) operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); on register_operand predicate, which also allows SUBREG RTX. So, subregs were emitted without ZERO_EXTEND RTX. But nowadays we have UMUL_HIGHPART that allows us to fix this issue while also simplifying the instruction RTX. PR target/113720 gcc/ChangeLog: * config/alpha/alpha.md (umuldi3_highpart): Remove expander. (*umuldi3_highpart_reg): Rename to umuldi3_highpart and simplify insn RTX using UMUL_HIGHPART rtx_code. (*umuldi3_highpart_const): Remove. --- gcc/config/alpha/alpha.md | 37 +++---------------------------------- 1 file changed, 3 insertions(+), 34 deletions(-) (limited to 'gcc') diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 94d5d33..79f12c5 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -683,41 +683,10 @@ [(set_attr "type" "imul") (set_attr "opsize" "")]) -(define_expand "umuldi3_highpart" - [(set (match_operand:DI 0 "register_operand") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI - (match_operand:DI 1 "register_operand")) - (match_operand:DI 2 "reg_or_8bit_operand")) - (const_int 64))))] - "" -{ - if (REG_P (operands[2])) - operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); -}) - -(define_insn "*umuldi3_highpart_reg" - [(set (match_operand:DI 0 "register_operand" "=r") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI - (match_operand:DI 1 "register_operand" "r")) - (zero_extend:TI - (match_operand:DI 2 "register_operand" "r"))) - (const_int 64))))] - "" - "umulh %1,%2,%0" - [(set_attr "type" "imul") - (set_attr "opsize" "udi")]) - -(define_insn "*umuldi3_highpart_const" +(define_insn "umuldi3_highpart" [(set (match_operand:DI 0 "register_operand" "=r") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) - (match_operand:TI 2 "cint8_operand" "I")) - (const_int 64))))] + (umul_highpart:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") + (match_operand:DI 2 "reg_or_8bit_operand" "rI")))] "" "umulh %1,%2,%0" [(set_attr "type" "imul") -- cgit v1.1 From 5cc61212b71a3e1264c8a9c0c35e13474be04f87 Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Sun, 3 Mar 2024 20:27:49 +0100 Subject: AVR: Use more C++ ish coding style. gcc/ * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED. Use bool in place of int for boolean logic (if possible). Move declarations to definitions (if possible). * config/avr/avr.md: Use C++ comments. Fix some indentation glitches. * config/avr/avr-dimode.md: Same. * config/avr/constraints.md: Same. * config/avr/predicates.md: Same. --- gcc/config/avr/avr-dimode.md | 4 +- gcc/config/avr/avr.cc | 334 ++++++++++++++++-------------------------- gcc/config/avr/avr.md | 135 ++++++++--------- gcc/config/avr/constraints.md | 8 +- gcc/config/avr/predicates.md | 16 +- 5 files changed, 202 insertions(+), 295 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr-dimode.md b/gcc/config/avr/avr-dimode.md index 6fcabda..4b74e77 100644 --- a/gcc/config/avr/avr-dimode.md +++ b/gcc/config/avr/avr-dimode.md @@ -43,8 +43,8 @@ ;; so that no DImode insn contains pseudos or needs reloading. (define_constants - [(ACC_A 18) - (ACC_B 10)]) + [(ACC_A 18) + (ACC_B 10)]) ;; Supported modes that are 8 bytes wide (define_mode_iterator ALL8 [DI DQ UDQ DA UDA TA UTA]) diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 7df2143..c8b2b50 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -163,7 +163,7 @@ static int avr_operand_rtx_cost (rtx, machine_mode, enum rtx_code, int, bool); static void output_reload_in_const (rtx *, rtx, int *, bool); static struct machine_function *avr_init_machine_status (void); -static int _reg_unused_after (rtx_insn *insn, rtx reg, bool look_at_insn); +static bool _reg_unused_after (rtx_insn *insn, rtx reg, bool look_at_insn); /* Prototypes for hook implementors if needed before their implementation. */ @@ -648,8 +648,6 @@ avr_optimize_casesi (rtx_insn *insns[5], rtx *xop) start_sequence(); - rtx_insn *seq1, *seq2, *last1, *last2; - rtx reg = copy_to_mode_reg (mode, xop[10]); rtx (*gen_add)(rtx,rtx,rtx) = QImode == mode ? gen_addqi3 : gen_addhi3; @@ -665,8 +663,8 @@ avr_optimize_casesi (rtx_insn *insns[5], rtx *xop) JUMP_LABEL (cbranch) = xop[4]; ++LABEL_NUSES (xop[4]); - seq1 = get_insns(); - last1 = get_last_insn(); + rtx_insn *seq1 = get_insns(); + rtx_insn *last1 = get_last_insn(); end_sequence(); emit_insn_after (seq1, insns[2]); @@ -686,8 +684,8 @@ avr_optimize_casesi (rtx_insn *insns[5], rtx *xop) emit_insn (pat_4); - seq2 = get_insns(); - last2 = get_last_insn(); + rtx_insn *seq2 = get_insns(); + rtx_insn *last2 = get_last_insn(); end_sequence(); emit_insn_after (seq2, insns[3]); @@ -1309,7 +1307,7 @@ avr_mem_memx_p (rtx x) /* A helper for the subsequent function attribute used to dig for attribute 'name' in a FUNCTION_DECL or FUNCTION_TYPE */ -static inline int +static inline bool avr_lookup_function_attribute1 (const_tree func, const char *name) { if (FUNCTION_DECL == TREE_CODE (func)) @@ -1329,7 +1327,7 @@ avr_lookup_function_attribute1 (const_tree func, const char *name) /* Return nonzero if FUNC is a naked function. */ -static int +static bool avr_naked_function_p (tree func) { return avr_lookup_function_attribute1 (func, "naked"); @@ -1338,7 +1336,7 @@ avr_naked_function_p (tree func) /* Return nonzero if FUNC is an interrupt function as specified by the "interrupt" attribute. */ -static int +static bool avr_interrupt_function_p (tree func) { return avr_lookup_function_attribute1 (func, "interrupt"); @@ -1347,7 +1345,7 @@ avr_interrupt_function_p (tree func) /* Return nonzero if FUNC is a signal function as specified by the "signal" attribute. */ -static int +static bool avr_signal_function_p (tree func) { return avr_lookup_function_attribute1 (func, "signal"); @@ -1355,7 +1353,7 @@ avr_signal_function_p (tree func) /* Return nonzero if FUNC is an OS_task function. */ -static int +static bool avr_OS_task_function_p (tree func) { return avr_lookup_function_attribute1 (func, "OS_task"); @@ -1363,7 +1361,7 @@ avr_OS_task_function_p (tree func) /* Return nonzero if FUNC is an OS_main function. */ -static int +static bool avr_OS_main_function_p (tree func) { return avr_lookup_function_attribute1 (func, "OS_main"); @@ -1373,7 +1371,7 @@ avr_OS_main_function_p (tree func) /* Return nonzero if FUNC is a no_gccisr function as specified by the "no_gccisr" attribute. */ -static int +static bool avr_no_gccisr_function_p (tree func) { return avr_lookup_function_attribute1 (func, "no_gccisr"); @@ -1536,12 +1534,11 @@ avr_starting_frame_offset (void) static int avr_regs_to_save (HARD_REG_SET *set) { - int count; + int count = 0; int int_or_sig_p = cfun->machine->is_interrupt || cfun->machine->is_signal; if (set) CLEAR_HARD_REG_SET (*set); - count = 0; /* No need to save any registers if the function never returns or has the "OS_task" or "OS_main" attribute. */ @@ -1589,7 +1586,7 @@ avr_allocate_stack_slots_for_args (void) /* Return true if register FROM can be eliminated via register TO. */ static bool -avr_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) +avr_can_eliminate (const int /*from*/, const int to) { return ((frame_pointer_needed && to == FRAME_POINTER_REGNUM) || !frame_pointer_needed); @@ -2546,12 +2543,10 @@ emit_push_byte (unsigned regno, bool frame_related_p) static void emit_push_sfr (rtx sfr, bool frame_related_p, bool clr_p, int treg) { - rtx_insn *insn; - gcc_assert (MEM_P (sfr)); /* IN treg, IO(SFR) */ - insn = emit_move_insn (all_regs_rtx[treg], sfr); + rtx_insn *insn = emit_move_insn (all_regs_rtx[treg], sfr); if (frame_related_p) RTX_FRAME_RELATED_P (insn) = 1; @@ -2592,7 +2587,7 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) || live_seq > 7)) { rtx pattern; - int first_reg, reg, offset; + int reg, offset; emit_move_insn (gen_rtx_REG (HImode, REG_X), gen_int_mode (size, HImode)); @@ -2620,7 +2615,7 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) /* Note that live_seq always contains r28+r29, but the other registers to be saved are all below 18. */ - first_reg = (LAST_CALLEE_SAVED_REG + 1) - (live_seq - 2); + int first_reg = (LAST_CALLEE_SAVED_REG + 1) - (live_seq - 2); for (reg = REG_29, offset = -live_seq + 1; reg >= first_reg; @@ -2686,15 +2681,15 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) int irq_state = -1; HOST_WIDE_INT size_cfa = size, neg_size; rtx_insn *fp_plus_insns; - rtx fp, my_fp; gcc_assert (frame_pointer_needed || !isr_p || !crtl->is_leaf); - fp = my_fp = (frame_pointer_needed - ? frame_pointer_rtx - : gen_rtx_REG (Pmode, REG_X)); + rtx my_fp = (frame_pointer_needed + ? frame_pointer_rtx + : gen_rtx_REG (Pmode, REG_X)); + rtx fp = my_fp; if (AVR_HAVE_8BIT_SP) { @@ -2844,9 +2839,7 @@ void avr_expand_prologue (void) { HARD_REG_SET set; - HOST_WIDE_INT size; - - size = get_frame_size() + avr_outgoing_args_size(); + HOST_WIDE_INT size = get_frame_size() + avr_outgoing_args_size(); cfun->machine->stack_usage = 0; @@ -2999,7 +2992,7 @@ avr_asm_function_end_prologue (FILE *file) /* Worker function for `EPILOGUE_USES'. */ int -avr_epilogue_uses (int regno ATTRIBUTE_UNUSED) +avr_epilogue_uses (int /*regno*/) { if (reload_completed && cfun->machine @@ -3013,11 +3006,9 @@ avr_epilogue_uses (int regno ATTRIBUTE_UNUSED) static void emit_pop_byte (unsigned regno) { - rtx mem, reg; - - mem = gen_rtx_PRE_INC (HImode, stack_pointer_rtx); + rtx mem = gen_rtx_PRE_INC (HImode, stack_pointer_rtx); mem = gen_frame_mem (QImode, mem); - reg = gen_rtx_REG (QImode, regno); + rtx reg = gen_rtx_REG (QImode, regno); emit_insn (gen_rtx_SET (reg, mem)); } @@ -3027,13 +3018,10 @@ emit_pop_byte (unsigned regno) void avr_expand_epilogue (bool sibcall_p) { - int live_seq; HARD_REG_SET set; - int minimize; - HOST_WIDE_INT size; bool isr_p = cfun->machine->is_interrupt || cfun->machine->is_signal; - size = get_frame_size() + avr_outgoing_args_size(); + HOST_WIDE_INT size = get_frame_size() + avr_outgoing_args_size(); /* epilogue: naked */ if (cfun->machine->is_naked) @@ -3045,14 +3033,14 @@ avr_expand_epilogue (bool sibcall_p) } avr_regs_to_save (&set); - live_seq = sequent_regs_live (); + int live_seq = sequent_regs_live (); - minimize = (TARGET_CALL_PROLOGUES - && live_seq - && !isr_p - && !cfun->machine->is_OS_task - && !cfun->machine->is_OS_main - && !AVR_TINY); + bool minimize = (TARGET_CALL_PROLOGUES + && live_seq + && !isr_p + && !cfun->machine->is_OS_task + && !cfun->machine->is_OS_main + && !AVR_TINY); if (minimize && (live_seq > 4 @@ -3081,17 +3069,15 @@ avr_expand_epilogue (bool sibcall_p) /* Try two methods to adjust stack and select shortest. */ int irq_state = -1; - rtx fp, my_fp; - rtx_insn *fp_plus_insns; - HOST_WIDE_INT size_max; gcc_assert (frame_pointer_needed || !isr_p || !crtl->is_leaf); - fp = my_fp = (frame_pointer_needed - ? frame_pointer_rtx - : gen_rtx_REG (Pmode, REG_X)); + rtx my_fp = (frame_pointer_needed + ? frame_pointer_rtx + : gen_rtx_REG (Pmode, REG_X)); + rtx fp = my_fp; if (AVR_HAVE_8BIT_SP) { @@ -3103,7 +3089,7 @@ avr_expand_epilogue (bool sibcall_p) /* For rationale see comment in prologue generation. */ - size_max = (HOST_WIDE_INT) GET_MODE_MASK (GET_MODE (my_fp)); + HOST_WIDE_INT size_max = (HOST_WIDE_INT) GET_MODE_MASK (GET_MODE (my_fp)); if (size > size_max) size = size_max; size = trunc_int_for_mode (size, GET_MODE (my_fp)); @@ -3128,21 +3114,19 @@ avr_expand_epilogue (bool sibcall_p) emit_insn (gen_movhi_sp_r (stack_pointer_rtx, fp, GEN_INT (irq_state))); - fp_plus_insns = get_insns (); + rtx_insn *fp_plus_insns = get_insns (); end_sequence (); /********** Method 2: Adjust Stack pointer **********/ if (avr_sp_immediate_operand (gen_int_mode (size, HImode), HImode)) { - rtx_insn *sp_plus_insns; - start_sequence (); emit_move_insn (stack_pointer_rtx, plus_constant (Pmode, stack_pointer_rtx, size)); - sp_plus_insns = get_insns (); + rtx_insn *sp_plus_insns = get_insns (); end_sequence (); /************ Use shortest method ************/ @@ -3177,7 +3161,7 @@ avr_expand_epilogue (bool sibcall_p) CLEAR_HARD_REG_BIT (set, treg); } - for (int reg = 31; reg >= 0; --reg) + for (int reg = REG_31; reg >= REG_0; --reg) if (TEST_HARD_REG_BIT (set, reg)) emit_pop_byte (reg); @@ -3261,21 +3245,16 @@ avr_cannot_modify_jumps_p (void) /* Naked Functions must not have any instructions after their epilogue, see PR42240 */ - if (reload_completed - && cfun->machine - && cfun->machine->is_naked) - { - return true; - } - - return false; + return (reload_completed + && cfun->machine + && cfun->machine->is_naked); } /* Implement `TARGET_MODE_DEPENDENT_ADDRESS_P'. */ static bool -avr_mode_dependent_address_p (const_rtx addr ATTRIBUTE_UNUSED, addr_space_t as) +avr_mode_dependent_address_p (const_rtx /*addr*/, addr_space_t as) { /* FIXME: Non-generic addresses are not mode-dependent in themselves. This hook just serves to hack around PR rtl-optimization/52543 by @@ -3480,9 +3459,8 @@ avr_legitimize_address (rtx x, rtx oldx, machine_mode mode) than 63 bytes or for R++ or --R addressing. */ rtx -avr_legitimize_reload_address (rtx *px, machine_mode mode, - int opnum, int type, int addr_type, - int ind_levels ATTRIBUTE_UNUSED, +avr_legitimize_reload_address (rtx *px, machine_mode mode, int opnum, + int type, int addr_type, int /*ind_levels*/, rtx (*mk_memloc)(rtx,int)) { rtx x = *px; @@ -3948,9 +3926,8 @@ avr_print_operand (FILE *file, rtx x, int code) static bool avr_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, - unsigned int align ATTRIBUTE_UNUSED, - enum by_pieces_operation op, - bool speed_p) + unsigned int align, + enum by_pieces_operation op, bool speed_p) { if (op != MOVE_BY_PIECES || (speed_p && size > MOVE_MAX_PIECES)) @@ -4090,8 +4067,8 @@ ret_cond_branch (rtx x, int len, int reverse) /* Output insn cost for next insn. */ void -avr_final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED, - int num_operands ATTRIBUTE_UNUSED) +avr_final_prescan_insn (rtx_insn *insn, rtx * /*operands*/, + int /*num_operands*/) { if (avr_log.rtx_costs) { @@ -4150,7 +4127,7 @@ avr_function_arg_regno_p (int r) void avr_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, - tree fndecl ATTRIBUTE_UNUSED) + tree /*fndecl*/) { cum->nregs = AVR_TINY ? 1 + REG_25 - REG_20 : 1 + REG_25 - REG_8; cum->regno = FIRST_CUM_REG; @@ -4168,12 +4145,9 @@ avr_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, static int avr_num_arg_regs (machine_mode mode, const_tree type) { - int size; - - if (mode == BLKmode) - size = int_size_in_bytes (type); - else - size = GET_MODE_SIZE (mode); + int size = (mode == BLKmode + ? int_size_in_bytes (type) + : GET_MODE_SIZE (mode)); /* Align all function arguments to start in even-numbered registers. Odd-sized arguments leave holes above them. */ @@ -4206,8 +4180,7 @@ avr_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) in the argument list. */ static void -avr_function_arg_advance (cumulative_args_t cum_v, - const function_arg_info &arg) +avr_function_arg_advance (cumulative_args_t cum_v, const function_arg_info &arg) { CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); int bytes = avr_num_arg_regs (arg.mode, arg.type); @@ -4261,8 +4234,6 @@ avr_function_arg_advance (cumulative_args_t cum_v, static bool avr_function_ok_for_sibcall (tree decl_callee, tree exp_callee) { - tree fntype_callee; - /* Tail-calling must fail if callee-saved regs are used to pass function args. We must not tail-call when `epilogue_restores' is used. Unfortunately, we cannot tell at this point if that @@ -4275,7 +4246,7 @@ avr_function_ok_for_sibcall (tree decl_callee, tree exp_callee) return false; } - fntype_callee = TREE_TYPE (CALL_EXPR_FN (exp_callee)); + tree fntype_callee = TREE_TYPE (CALL_EXPR_FN (exp_callee)); if (decl_callee) { @@ -4496,10 +4467,7 @@ avr_out_lpm (rtx_insn *insn, rtx *op, int *plen) rtx xop[7]; rtx dest = op[0]; rtx src = SET_SRC (single_set (insn)); - rtx addr; int n_bytes = GET_MODE_SIZE (GET_MODE (dest)); - int segment; - RTX_CODE code; addr_space_t as = MEM_ADDR_SPACE (src); if (plen) @@ -4513,8 +4481,8 @@ avr_out_lpm (rtx_insn *insn, rtx *op, int *plen) return ""; } - addr = XEXP (src, 0); - code = GET_CODE (addr); + rtx addr = XEXP (src, 0); + RTX_CODE code = GET_CODE (addr); gcc_assert (REG_P (dest)); gcc_assert (REG == code || POST_INC == code); @@ -4526,7 +4494,7 @@ avr_out_lpm (rtx_insn *insn, rtx *op, int *plen) xop[5] = tmp_reg_rtx; xop[6] = XEXP (rampz_rtx, 0); - segment = avr_addrspace[as].segment; + int segment = avr_addrspace[as].segment; /* Set RAMPZ as needed. */ @@ -4663,7 +4631,7 @@ avr_out_lpm (rtx_insn *insn, rtx *op, int *plen) /* Worker function for xload_8 insn. */ const char * -avr_out_xload (rtx_insn *insn ATTRIBUTE_UNUSED, rtx *op, int *plen) +avr_out_xload (rtx_insn * /*insn*/, rtx *op, int *plen) { rtx xop[4]; @@ -4960,14 +4928,13 @@ avr_out_movhi_r_mr_reg_disp_tiny (rtx_insn *insn, rtx op[], int *plen) static const char * avr_out_movhi_r_mr_pre_dec_tiny (rtx_insn *insn, rtx op[], int *plen) { - int mem_volatile_p = 0; rtx dest = op[0]; rtx src = op[1]; rtx base = XEXP (src, 0); /* "volatile" forces reading low byte first, even if less efficient, for correct operation with 16-bit I/O registers. */ - mem_volatile_p = MEM_VOLATILE_P (src); + bool mem_volatile_p = MEM_VOLATILE_P (src); if (reg_overlap_mentioned_p (dest, XEXP (base, 0))) fatal_insn ("incorrect insn:", insn); @@ -4993,7 +4960,7 @@ out_movhi_r_mr (rtx_insn *insn, rtx op[], int *plen) int reg_base = true_regnum (base); /* "volatile" forces reading low byte first, even if less efficient, for correct operation with 16-bit I/O registers. */ - int mem_volatile_p = MEM_VOLATILE_P (src); + bool mem_volatile_p = MEM_VOLATILE_P (src); if (reg_base > 0) { @@ -6306,7 +6273,7 @@ avr_out_movhi_mr_r_xmega (rtx_insn *insn, rtx op[], int *plen) /* "volatile" forces writing low byte first, even if less efficient, for correct operation with 16-bit I/O registers like SP. */ - int mem_volatile_p = MEM_VOLATILE_P (dest); + bool mem_volatile_p = MEM_VOLATILE_P (dest); if (CONSTANT_ADDRESS_P (base)) { @@ -6413,7 +6380,7 @@ avr_out_movhi_mr_r_reg_no_disp_tiny (rtx_insn *insn, rtx op[], int *plen) rtx base = XEXP (dest, 0); int reg_base = true_regnum (base); int reg_src = true_regnum (src); - int mem_volatile_p = MEM_VOLATILE_P (dest); + bool mem_volatile_p = MEM_VOLATILE_P (dest); if (reg_base == reg_src) { @@ -6481,7 +6448,6 @@ out_movhi_mr_r (rtx_insn *insn, rtx op[], int *plen) rtx base = XEXP (dest, 0); int reg_base = true_regnum (base); int reg_src = true_regnum (src); - int mem_volatile_p; /* "volatile" forces writing high-byte first (no-xmega) resp. low-byte first (xmega) even if less efficient, for correct @@ -6490,7 +6456,7 @@ out_movhi_mr_r (rtx_insn *insn, rtx op[], int *plen) if (AVR_XMEGA) return avr_out_movhi_mr_r_xmega (insn, op, plen); - mem_volatile_p = MEM_VOLATILE_P (dest); + bool mem_volatile_p = MEM_VOLATILE_P (dest); if (CONSTANT_ADDRESS_P (base)) { @@ -6937,9 +6903,6 @@ avr_out_compare (rtx_insn *insn, rtx *xop, int *plen) rtx xreg = xop[0]; rtx xval = xop[1]; - /* MODE of the comparison. */ - machine_mode mode; - /* Number of bytes to operate on. */ int n_bytes = GET_MODE_SIZE (GET_MODE (xreg)); @@ -6955,7 +6918,8 @@ avr_out_compare (rtx_insn *insn, rtx *xop, int *plen) xval = avr_to_int_mode (xop[1]); } - mode = GET_MODE (xreg); + /* MODE of the comparison. */ + machine_mode mode = GET_MODE (xreg); gcc_assert (REG_P (xreg)); gcc_assert ((CONST_INT_P (xval) && n_bytes <= 4) @@ -7119,11 +7083,7 @@ avr_out_compare (rtx_insn *insn, rtx *xop, int *plen) const char * avr_out_compare64 (rtx_insn *insn, rtx *op, int *plen) { - rtx xop[3]; - - xop[0] = gen_rtx_REG (DImode, ACC_A); - xop[1] = op[0]; - xop[2] = op[1]; + rtx xop[3] = { gen_rtx_REG (DImode, ACC_A), op[0], op[1] }; return avr_out_compare (insn, xop, plen); } @@ -10506,7 +10466,7 @@ avr_out_fract (rtx_insn *insn, rtx operands[], bool intsigned, int *plen) preparing operands for calls to `avr_out_plus' and `avr_out_bitop'. */ const char * -avr_out_round (rtx_insn *insn ATTRIBUTE_UNUSED, rtx *xop, int *plen) +avr_out_round (rtx_insn * /*insn*/, rtx *xop, int *plen) { scalar_mode mode = as_a (GET_MODE (xop[0])); scalar_int_mode imode = int_mode_for_mode (mode).require (); @@ -10577,7 +10537,6 @@ avr_rotate_bytes (rtx operands[]) /* Work out if byte or word move is needed. Odd byte rotates need QImode. Word move if no scratch is needed, otherwise use size of scratch. */ machine_mode move_mode = QImode; - int move_size, offset, size; if (num & 0xf) move_mode = QImode; @@ -10596,11 +10555,11 @@ avr_rotate_bytes (rtx operands[]) && QImode == move_mode) scratch = simplify_gen_subreg (move_mode, scratch, HImode, 0); - move_size = GET_MODE_SIZE (move_mode); + int move_size = GET_MODE_SIZE (move_mode); /* Number of bytes/words to rotate. */ - offset = (num >> 3) / move_size; + int offset = (num >> 3) / move_size; /* Number of moves needed. */ - size = GET_MODE_SIZE (mode) / move_size; + int size = GET_MODE_SIZE (mode) / move_size; /* Himode byte swap is special case to avoid a scratch register. */ if (mode == HImode && same_reg) { @@ -10718,7 +10677,6 @@ int avr_adjust_insn_length (rtx_insn *insn, int len) { rtx *op = recog_data.operand; - enum attr_adjust_len adjust_len; /* As we pretend jump tables in .text, fix branch offsets crossing jump tables now. */ @@ -10738,7 +10696,7 @@ avr_adjust_insn_length (rtx_insn *insn, int len) /* Read from insn attribute "adjust_len" if/how length is to be adjusted. */ - adjust_len = get_attr_adjust_len (insn); + enum attr_adjust_len adjust_len = get_attr_adjust_len (insn); if (adjust_len == ADJUST_LEN_NO) { @@ -10831,7 +10789,7 @@ reg_unused_after (rtx_insn *insn, rtx reg) We assume REG is a reload reg, and therefore does not live past labels. It may live past calls or jumps though. */ -int +bool _reg_unused_after (rtx_insn *insn, rtx reg, bool look_at_insn) { if (look_at_insn) @@ -10989,14 +10947,14 @@ avr_assemble_integer (rtx x, unsigned int size, int aligned_p) return default_assemble_integer (x, size, aligned_p); } -/* Implement TARGET_CLASS_MAX_NREGS. Reasons described in comments for +/* Implement `TARGET_CLASS_MAX_NREGS'. Reasons described in comments for avr_hard_regno_nregs. */ static unsigned char avr_class_max_nregs (reg_class_t rclass, machine_mode mode) { if (rclass == CC_REG && mode == CCmode) - return 1; + return 1; return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); } @@ -11010,8 +10968,8 @@ avr_class_max_nregs (reg_class_t rclass, machine_mode mode) static bool avr_class_likely_spilled_p (reg_class_t c) { - return (c != ALL_REGS && - (AVR_TINY ? 1 : c != ADDW_REGS)); + return (c != ALL_REGS + && (AVR_TINY ? 1 : c != ADDW_REGS)); } @@ -11028,10 +10986,8 @@ avr_class_likely_spilled_p (reg_class_t c) struct attribute_spec.handler. */ static tree -avr_handle_progmem_attribute (tree *node, tree name, - tree args ATTRIBUTE_UNUSED, - int flags ATTRIBUTE_UNUSED, - bool *no_add_attrs) +avr_handle_progmem_attribute (tree *node, tree name, tree args, + int /*flags*/, bool *no_add_attrs) { if (DECL_P (*node)) { @@ -11067,10 +11023,8 @@ avr_handle_progmem_attribute (tree *node, tree name, struct attribute_spec.handler. */ static tree -avr_handle_fndecl_attribute (tree *node, tree name, - tree args ATTRIBUTE_UNUSED, - int flags ATTRIBUTE_UNUSED, - bool *no_add_attrs) +avr_handle_fndecl_attribute (tree *node, tree name, tree /*args*/, + int /*flags*/, bool *no_add_attrs) { if (TREE_CODE (*node) != FUNCTION_DECL) { @@ -11083,10 +11037,8 @@ avr_handle_fndecl_attribute (tree *node, tree name, } static tree -avr_handle_fntype_attribute (tree *node, tree name, - tree args ATTRIBUTE_UNUSED, - int flags ATTRIBUTE_UNUSED, - bool *no_add_attrs) +avr_handle_fntype_attribute (tree *node, tree name, tree /*args*/, + int /*flags*/, bool *no_add_attrs) { if (TREE_CODE (*node) != FUNCTION_TYPE) { @@ -11126,7 +11078,7 @@ avr_handle_absdata_attribute (tree *node, tree name, tree /* args */, static tree avr_handle_addr_attribute (tree *node, tree name, tree args, - int flags ATTRIBUTE_UNUSED, bool *no_add) + int /*flags*/, bool *no_add) { bool io_p = startswith (IDENTIFIER_POINTER (name), "io"); HOST_WIDE_INT io_start = avr_arch->sfr_offset; @@ -11309,8 +11261,6 @@ avr_addr_space_zero_address_valid (addr_space_t) int avr_progmem_p (tree decl, tree attributes) { - tree a; - if (TREE_CODE (decl) != VAR_DECL) return 0; @@ -11324,7 +11274,7 @@ avr_progmem_p (tree decl, tree attributes) != lookup_attribute ("progmem", attributes)) return -1; - a = decl; + tree a = decl; do a = TREE_TYPE(a); @@ -11364,7 +11314,6 @@ avr_nonconst_pointer_addrspace (tree typ) if (POINTER_TYPE_P (typ)) { - addr_space_t as; tree target = TREE_TYPE (typ); /* Pointer to function: Test the function's return type. */ @@ -11379,7 +11328,7 @@ avr_nonconst_pointer_addrspace (tree typ) /* Pointers to non-generic address space must be const. */ - as = TYPE_ADDR_SPACE (target); + addr_space_t as = TYPE_ADDR_SPACE (target); if (!ADDR_SPACE_GENERIC_P (as) && !TYPE_READONLY (target) @@ -11498,7 +11447,6 @@ avr_insert_attributes (tree node, tree *attributes) && (TREE_STATIC (node) || DECL_EXTERNAL (node)) && avr_progmem_p (node, *attributes)) { - addr_space_t as; tree node0 = node; /* For C++, we have to peel arrays in order to get correct @@ -11511,7 +11459,7 @@ avr_insert_attributes (tree node, tree *attributes) if (error_mark_node == node0) return; - as = TYPE_ADDR_SPACE (TREE_TYPE (node)); + addr_space_t as = TYPE_ADDR_SPACE (TREE_TYPE (node)); if (!TYPE_READONLY (node0) && !TREE_READONLY (node)) @@ -11752,7 +11700,7 @@ avr_asm_named_section (const char *name, unsigned int flags, tree decl) if (!avr_has_rodata_p) avr_has_rodata_p = (startswith (name, ".rodata") - || startswith (name, ".gnu.linkonce.r")); + || startswith (name, ".gnu.linkonce.r")); if (!avr_need_clear_bss_p) avr_need_clear_bss_p = startswith (name, ".bss"); @@ -12170,8 +12118,7 @@ avr_adjust_reg_alloc_order (void) /* Implement `TARGET_REGISTER_MOVE_COST' */ static int -avr_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, - reg_class_t from, reg_class_t to) +avr_register_move_cost (machine_mode /*mode*/, reg_class_t from, reg_class_t to) { return (from == STACK_REG ? 6 : to == STACK_REG ? 12 @@ -12182,9 +12129,7 @@ avr_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, /* Implement `TARGET_MEMORY_MOVE_COST' */ static int -avr_memory_move_cost (machine_mode mode, - reg_class_t rclass ATTRIBUTE_UNUSED, - bool in ATTRIBUTE_UNUSED) +avr_memory_move_cost (machine_mode mode, reg_class_t /*rclass*/, bool /*in*/) { return (mode == QImode ? 2 : mode == HImode ? 4 @@ -12283,7 +12228,6 @@ avr_operand_rtx_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno, bool speed) { enum rtx_code code = GET_CODE (x); - int total; switch (code) { @@ -12300,7 +12244,7 @@ avr_operand_rtx_cost (rtx x, machine_mode mode, enum rtx_code outer, break; } - total = 0; + int total = 0; avr_rtx_costs (x, mode, outer, opno, &total, speed); return total; } @@ -12313,7 +12257,7 @@ avr_operand_rtx_cost (rtx x, machine_mode mode, enum rtx_code outer, static bool avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code, - int opno ATTRIBUTE_UNUSED, int *total, bool speed) + int /*opno*/, int *total, bool speed) { enum rtx_code code = GET_CODE (x); HOST_WIDE_INT val; @@ -13258,9 +13202,8 @@ avr_insn_cost (rtx_insn *insn, bool speed) /* Implement `TARGET_ADDRESS_COST'. */ static int -avr_address_cost (rtx x, machine_mode mode ATTRIBUTE_UNUSED, - addr_space_t as ATTRIBUTE_UNUSED, - bool speed ATTRIBUTE_UNUSED) +avr_address_cost (rtx x, machine_mode mode, addr_space_t /*as*/, + bool /*speed*/) { int cost = 4; @@ -13348,7 +13291,7 @@ avr_normalize_condition (RTX_CODE condition) static inline unsigned int avr_ret_register (void) { - return 24; + return REG_24; } @@ -13357,7 +13300,7 @@ avr_ret_register (void) static bool avr_function_value_regno_p (const unsigned int regno) { - return (regno == avr_ret_register ()); + return regno == avr_ret_register (); } @@ -13366,8 +13309,7 @@ avr_function_value_regno_p (const unsigned int regno) library function returns a value of mode MODE. */ static rtx -avr_libcall_value (machine_mode mode, - const_rtx func ATTRIBUTE_UNUSED) +avr_libcall_value (machine_mode mode, const_rtx /*func*/) { int offs = GET_MODE_SIZE (mode); @@ -13383,16 +13325,13 @@ avr_libcall_value (machine_mode mode, function returns a value of data type VALTYPE. */ static rtx -avr_function_value (const_tree type, - const_tree fn_decl_or_type ATTRIBUTE_UNUSED, - bool outgoing ATTRIBUTE_UNUSED) +avr_function_value (const_tree type, const_tree /*fn_decl_or_type*/, + bool /*outgoing*/) { - unsigned int offs; - if (TYPE_MODE (type) != BLKmode) return avr_libcall_value (TYPE_MODE (type), NULL_RTX); - offs = int_size_in_bytes (type); + unsigned int offs = int_size_in_bytes (type); if (offs < 2) offs = 2; if (offs > 2 && offs < GET_MODE_SIZE (SImode)) @@ -13562,9 +13501,8 @@ avr_hard_regno_call_part_clobbered (unsigned, unsigned regno, /* Implement `MODE_CODE_BASE_REG_CLASS'. */ enum reg_class -avr_mode_code_base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, - addr_space_t as, RTX_CODE outer_code, - RTX_CODE index_code ATTRIBUTE_UNUSED) +avr_mode_code_base_reg_class (machine_mode /*mode*/, addr_space_t as, + RTX_CODE outer_code, RTX_CODE /*index_code*/) { if (!ADDR_SPACE_GENERIC_P (as)) { @@ -13586,11 +13524,9 @@ avr_mode_code_base_reg_class (machine_mode mode ATTRIBUTE_UNUSED, /* Implement `REGNO_MODE_CODE_OK_FOR_BASE_P'. */ bool -avr_regno_mode_code_ok_for_base_p (int regno, - machine_mode mode ATTRIBUTE_UNUSED, - addr_space_t as ATTRIBUTE_UNUSED, - RTX_CODE outer_code, - RTX_CODE index_code ATTRIBUTE_UNUSED) +avr_regno_mode_code_ok_for_base_p (int regno, machine_mode /*mode*/, + addr_space_t as, RTX_CODE outer_code, + RTX_CODE /*index_code*/) { bool ok = false; @@ -13718,14 +13654,13 @@ output_reload_in_const (rtx *op, rtx clobber_reg, int *len, bool clear_p) for (int n = 0; n < n_bytes; n++) { - int ldreg_p; bool done_byte = false; rtx xop[3]; /* Crop the n-th destination byte. */ xdest[n] = simplify_gen_subreg (QImode, dest, mode, n); - ldreg_p = test_hard_reg_class (LD_REGS, xdest[n]); + int ldreg_p = test_hard_reg_class (LD_REGS, xdest[n]); if (!CONST_INT_P (src) && !CONST_FIXED_P (src) @@ -13920,8 +13855,6 @@ output_reload_insisf (rtx *op, rtx clobber_reg, int *len) || CONST_FIXED_P (op[1]) || CONST_DOUBLE_P (op[1]))) { - int len_clr, len_noclr; - /* In some cases it is better to clear the destination beforehand, e.g. CLR R2 CLR R3 MOVW R4,R2 INC R2 @@ -13934,6 +13867,7 @@ output_reload_insisf (rtx *op, rtx clobber_reg, int *len) Instead, we call the print function twice to get the lengths of both methods and use the shortest one. */ + int len_clr, len_noclr; output_reload_in_const (op, clobber_reg, &len_clr, true); output_reload_in_const (op, clobber_reg, &len_noclr, false); @@ -14129,8 +14063,7 @@ avr_hard_regno_scratch_ok (unsigned int regno) /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ int -avr_hard_regno_rename_ok (unsigned int old_reg, - unsigned int new_reg) +avr_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg) { /* Interrupt functions can only use registers that have already been saved by the prologue, even if they would normally be @@ -14249,7 +14182,7 @@ avr_asm_out_dtor (rtx symbol, int priority) /* Implement `TARGET_RETURN_IN_MEMORY'. */ static bool -avr_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) +avr_return_in_memory (const_tree type, const_tree /*fntype*/) { HOST_WIDE_INT size = int_size_in_bytes (type); HOST_WIDE_INT ret_size_limit = AVR_TINY ? 4 : 8; @@ -14444,7 +14377,6 @@ avr_addr_space_convert (rtx src, tree type_from, tree type_to) if (as_from != ADDR_SPACE_MEMX && as_to == ADDR_SPACE_MEMX) { - int msb; rtx sym = src; rtx reg = gen_reg_rtx (PSImode); @@ -14465,7 +14397,7 @@ avr_addr_space_convert (rtx src, tree type_from, tree type_to) /* Linearize memory: RAM has bit 23 set. */ - msb = ADDR_SPACE_GENERIC_P (as_from) + int msb = ADDR_SPACE_GENERIC_P (as_from) ? 0x80 : avr_addrspace[as_from].segment; @@ -14499,8 +14431,7 @@ avr_addr_space_convert (rtx src, tree type_from, tree type_to) /* Implement `TARGET_ADDR_SPACE_SUBSET_P'. */ static bool -avr_addr_space_subset_p (addr_space_t subset ATTRIBUTE_UNUSED, - addr_space_t superset ATTRIBUTE_UNUSED) +avr_addr_space_subset_p (addr_space_t /*subset*/, addr_space_t /*superset*/) { /* Allow any kind of pointer mess. */ @@ -14715,10 +14646,9 @@ avr_emit3_fix_outputs (rtx (*gen)(rtx,rtx,rtx), rtx *op, bool avr_emit_cpymemhi (rtx *xop) { - HOST_WIDE_INT count; machine_mode loop_mode; addr_space_t as = MEM_ADDR_SPACE (xop[1]); - rtx loop_reg, addr1, a_src, a_dest, insn, xas; + rtx loop_reg, addr1, insn; rtx a_hi8 = NULL_RTX; if (avr_mem_flash_p (xop[0])) @@ -14727,12 +14657,12 @@ avr_emit_cpymemhi (rtx *xop) if (!CONST_INT_P (xop[2])) return false; - count = INTVAL (xop[2]); + HOST_WIDE_INT count = INTVAL (xop[2]); if (count <= 0) return false; - a_src = XEXP (xop[1], 0); - a_dest = XEXP (xop[0], 0); + rtx a_src = XEXP (xop[1], 0); + rtx a_dest = XEXP (xop[0], 0); if (PSImode == GET_MODE (a_src)) { @@ -14766,7 +14696,7 @@ avr_emit_cpymemhi (rtx *xop) loop_reg = copy_to_mode_reg (loop_mode, gen_int_mode (count, loop_mode)); } - xas = GEN_INT (as); + rtx xas = GEN_INT (as); /* FIXME: Register allocator might come up with spill fails if it is left on its own. Thus, we allocate the pointer registers by hand: @@ -14819,20 +14749,16 @@ avr_emit_cpymemhi (rtx *xop) */ const char * -avr_out_cpymem (rtx_insn *insn ATTRIBUTE_UNUSED, rtx *op, int *plen) +avr_out_cpymem (rtx_insn * /*insn*/, rtx *op, int *plen) { addr_space_t as = (addr_space_t) INTVAL (op[0]); machine_mode loop_mode = GET_MODE (op[1]); bool sbiw_p = avr_adiw_reg_p (op[1]); - rtx xop[3]; + rtx xop[3] = { op[0], op[1], tmp_reg_rtx }; if (plen) *plen = 0; - xop[0] = op[0]; - xop[1] = op[1]; - xop[2] = tmp_reg_rtx; - /* Loop label */ avr_asm_len ("0:", xop, plen, 0); @@ -15238,7 +15164,6 @@ const char * avr_out_insert_bits (rtx *op, int *plen) { unsigned int map = UINTVAL (op[1]) & GET_MODE_MASK (SImode); - unsigned mask_fixed; bool fixp_p = true; rtx xop[4]; @@ -15256,7 +15181,7 @@ avr_out_insert_bits (rtx *op, int *plen) /* If MAP has fixed points it might be better to initialize the result with the bits to be inserted instead of moving all bits by hand. */ - mask_fixed = avr_map_metric (map, MAP_MASK_FIXED_0_7); + unsigned mask_fixed = avr_map_metric (map, MAP_MASK_FIXED_0_7); if (REGNO (xop[0]) == REGNO (xop[1])) { @@ -15347,7 +15272,7 @@ avr_bdesc[AVR_BUILTIN_COUNT] = /* Implement `TARGET_BUILTIN_DECL'. */ static tree -avr_builtin_decl (unsigned id, bool initialize_p ATTRIBUTE_UNUSED) +avr_builtin_decl (unsigned id, bool /*initialize_p*/) { if (id < AVR_BUILTIN_COUNT) return avr_bdesc[id].fndecl; @@ -15619,10 +15544,8 @@ avr_default_expand_builtin (enum insn_code icode, tree exp, rtx target) IGNORE is nonzero if the value is to be ignored. */ static rtx -avr_expand_builtin (tree exp, rtx target, - rtx subtarget ATTRIBUTE_UNUSED, - machine_mode mode ATTRIBUTE_UNUSED, - int ignore) +avr_expand_builtin (tree exp, rtx target, rtx /*subtarget*/, + machine_mode mode, int ignore) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); const char *bname = IDENTIFIER_POINTER (DECL_NAME (fndecl)); @@ -15775,8 +15698,7 @@ avr_fold_absfx (tree tval) /* Implement `TARGET_FOLD_BUILTIN'. */ static tree -avr_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *arg, - bool ignore ATTRIBUTE_UNUSED) +avr_fold_builtin (tree fndecl, int /*n_args*/, tree *arg, bool /*ignore*/) { unsigned int fcode = DECL_MD_FUNCTION_CODE (fndecl); tree val_type = TREE_TYPE (TREE_TYPE (fndecl)); @@ -15837,9 +15759,7 @@ avr_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *arg, { tree tbits = arg[1]; tree tval = arg[2]; - tree tmap; tree map_type = TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (fndecl))); - unsigned int map; bool changed = false; avr_map_op_t best_g; @@ -15851,8 +15771,8 @@ avr_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *arg, break; } - tmap = wide_int_to_tree (map_type, wi::to_wide (arg[0])); - map = TREE_INT_CST_LOW (tmap); + tree tmap = wide_int_to_tree (map_type, wi::to_wide (arg[0])); + unsigned int map = TREE_INT_CST_LOW (tmap); if (TREE_CODE (tval) != INTEGER_CST && avr_map_metric (map, MAP_MASK_PREIMAGE_F) == 0) diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 7f73587..6606837 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -377,8 +377,8 @@ rtx offset = gen_int_mode (targetm.starting_frame_offset (), Pmode); emit_move_insn (virtual_stack_vars_rtx, gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, offset)); - /* ; This might change the hard frame pointer in ways that aren't - ; apparent to early optimization passes, so force a clobber. */ + // This might change the hard frame pointer in ways that aren't + // apparent to early optimization passes, so force a clobber. emit_clobber (hard_frame_pointer_rtx); DONE; }) @@ -575,11 +575,10 @@ "&& 1" [(clobber (const_int 0))] { - /* ; Split away the high part of the address. GCC's register allocator - ; in not able to allocate segment registers and reload the resulting - ; expressions. Notice that no address register can hold a PSImode. */ + // Split away the high part of the address. GCC's register allocator + // in not able to allocate segment registers and reload the resulting + // expressions. Notice that no address register can hold a PSImode. - rtx_insn *insn; rtx addr = XEXP (operands[1], 0); rtx hi8 = gen_reg_rtx (QImode); rtx reg_z = gen_rtx_REG (HImode, REG_Z); @@ -587,7 +586,7 @@ emit_move_insn (reg_z, simplify_gen_subreg (HImode, addr, PSImode, 0)); emit_move_insn (hi8, simplify_gen_subreg (QImode, addr, PSImode, 2)); - insn = emit_insn (gen_xload_8 (operands[0], hi8)); + rtx_insn *insn = emit_insn (gen_xload_8 (operands[0], hi8)); set_mem_addr_space (SET_SRC (single_set (insn)), MEM_ADDR_SPACE (operands[1])); DONE; @@ -617,15 +616,15 @@ addr_space_t as = MEM_ADDR_SPACE (operands[1]); rtx_insn *insn; - /* Split the address to R21:Z */ + // Split the address to R21:Z emit_move_insn (reg_z, simplify_gen_subreg (HImode, addr, PSImode, 0)); emit_move_insn (gen_rtx_REG (QImode, 21), addr_hi8); - /* Load with code from libgcc */ + // Load with code from libgcc. insn = emit_insn (gen_xload__libgcc ()); set_mem_addr_space (SET_SRC (single_set (insn)), as); - /* Move to destination */ + // Move to destination. emit_move_insn (operands[0], gen_rtx_REG (mode, 22)); DONE; @@ -721,7 +720,7 @@ SUBREG_REG (src) = copy_to_mode_reg (GET_MODE (const_addr), const_addr); } - /* One of the operands has to be in a register. */ + // One of the operands has to be in a register. if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) { @@ -736,8 +735,8 @@ src = replace_equiv_address (src, copy_to_mode_reg (PSImode, addr)); if (!avr_xload_libgcc_p (mode)) - /* ; No here because gen_xload8_A only iterates over ALL1. - ; insn-emit does not depend on the mode, it's all about operands. */ + // No here because gen_xload8_A only iterates over ALL1. + // insn-emit does not depend on the mode, it's all about operands. emit_insn (gen_xload8qi_A (dest, src)); else emit_insn (gen_xload_A (dest, src)); @@ -747,7 +746,7 @@ if (avr_load_libgcc_p (src)) { - /* For the small devices, do loads per libgcc call. */ + // For the small devices, do loads per libgcc call. emit_insn (gen_load_libgcc (dest, src)); DONE; } @@ -1291,21 +1290,18 @@ (clobber (match_dup 4))])] "" { - rtx addr0; - machine_mode mode; - - /* If value to set is not zero, use the library routine. */ + // If value to set is not zero, use the library routine. if (operands[2] != const0_rtx) FAIL; if (!CONST_INT_P (operands[1])) FAIL; - mode = u8_operand (operands[1], VOIDmode) ? QImode : HImode; + machine_mode mode = u8_operand (operands[1], VOIDmode) ? QImode : HImode; operands[4] = gen_rtx_SCRATCH (mode); operands[1] = copy_to_mode_reg (mode, gen_int_mode (INTVAL (operands[1]), mode)); - addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); + rtx addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); operands[0] = gen_rtx_MEM (BLKmode, addr0); }) @@ -1392,10 +1388,9 @@ (clobber (scratch:QI))])] "" { - rtx addr; if (operands[2] != const0_rtx) FAIL; - addr = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); + rtx addr = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); operands[1] = gen_rtx_MEM (BLKmode, addr); operands[5] = addr; operands[4] = gen_reg_rtx (HImode); @@ -1640,10 +1635,10 @@ "" [(const_int 0)] { - /* Do not attempt to split this pattern. This FAIL is necessary - to prevent the splitter from matching *add3_split, splitting - it, and then failing later because constraints don't match, as split - does not look at constraints. */ + // Do not attempt to split this pattern. This FAIL is necessary + // to prevent the splitter from matching *add3_split, splitting + // it, and then failing later because constraints don't match, as split + // does not look at constraints. FAIL; } [(set_attr "length" "6") @@ -3221,10 +3216,10 @@ DONE; } - /* ; For small constants we can do better by extending them on the fly. - ; The constant can be loaded in one instruction and the widening - ; multiplication is shorter. First try the unsigned variant because it - ; allows constraint "d" instead of "a" for the signed version. */ + // For small constants we can do better by extending them on the fly. + // The constant can be loaded in one instruction and the widening + // multiplication is shorter. First try the unsigned variant because it + // allows constraint "d" instead of "a" for the signed version. */ if (s9_operand (operands[2], HImode)) { @@ -3415,8 +3410,8 @@ (set (match_dup 0) (reg:SI 22))] { - /* Do the QI -> HI extension explicitely before the multiplication. */ - /* Do the HI -> SI extension implicitely and after the multiplication. */ + // Do the QI -> HI extension explicitely before the multiplication. + // Do the HI -> SI extension implicitely and after the multiplication. if (QImode == mode) operands[1] = gen_rtx_ZERO_EXTEND (HImode, operands[1]); @@ -3467,8 +3462,8 @@ (set (match_dup 0) (reg:SI 22))] { - /* Do the QI -> HI extension explicitely before the multiplication. */ - /* Do the HI -> SI extension implicitely and after the multiplication. */ + // Do the QI -> HI extension explicitely before the multiplication. + // Do the HI -> SI extension implicitely and after the multiplication. if (QImode == mode) operands[1] = gen_rtx_SIGN_EXTEND (HImode, operands[1]); @@ -3581,8 +3576,8 @@ rtx xop1 = operands[1]; rtx xop2 = operands[2]; - /* Do the QI -> HI extension explicitely before the multiplication. */ - /* Do the HI -> SI extension implicitely and after the multiplication. */ + // Do the QI -> HI extension explicitely before the multiplication. + // Do the HI -> SI extension implicitely and after the multiplication. if (QImode == mode) xop1 = gen_rtx_fmt_e (, HImode, xop1); @@ -3600,8 +3595,8 @@ } else { - /* = SIGN_EXTEND */ - /* = ZERO_EXTEND */ + // = SIGN_EXTEND + // = ZERO_EXTEND operands[1] = xop2; operands[2] = xop1; @@ -4269,7 +4264,7 @@ (match_operand:SI 2 "pseudo_register_operand"))) (set (match_operand:SI 3 "pseudo_register_operand") (mod:SI (match_dup 1) - (match_dup 2))) + (match_dup 2))) (clobber (reg:SI 18)) (clobber (reg:SI 22)) (clobber (reg:HI 26)) @@ -4926,7 +4921,7 @@ else if (offset == 1 || offset == GET_MODE_BITSIZE (mode) -1) { - /*; Support rotate left/right by 1 */ + // Support rotate left/right by 1. emit_move_insn (operands[0], gen_rtx_ROTATE (mode, operands[1], operands[2])); @@ -5726,7 +5721,7 @@ (lshiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "") (match_operand:QI 2 "nop_general_operand" "")))]) -(define_split ; lshrqi3_const4 +(define_split ; lshrqi3_const4 [(set (match_operand:ALL1 0 "d_register_operand" "") (lshiftrt:ALL1 (match_dup 0) (const_int 4)))] @@ -5741,7 +5736,7 @@ operands[1] = avr_to_int_mode (operands[0]); }) -(define_split ; lshrqi3_const5 +(define_split ; lshrqi3_const5 [(set (match_operand:ALL1 0 "d_register_operand" "") (lshiftrt:ALL1 (match_dup 0) (const_int 5)))] @@ -5753,7 +5748,7 @@ operands[1] = avr_to_int_mode (operands[0]); }) -(define_split ; lshrqi3_const6 +(define_split ; lshrqi3_const6 [(set (match_operand:QI 0 "d_register_operand" "") (lshiftrt:QI (match_dup 0) (const_int 6)))] @@ -6160,17 +6155,17 @@ (define_insn_and_split "negsf2" [(set (match_operand:SF 0 "register_operand" "=d,r") - (neg:SF (match_operand:SF 1 "register_operand" "0,0")))] + (neg:SF (match_operand:SF 1 "register_operand" "0,0")))] "" "#" "&& reload_completed" [(parallel [(set (match_dup 0) - (neg:SF (match_dup 1))) + (neg:SF (match_dup 1))) (clobber (reg:CC REG_CC))])]) (define_insn "*negsf2" [(set (match_operand:SF 0 "register_operand" "=d,r") - (neg:SF (match_operand:SF 1 "register_operand" "0,0"))) + (neg:SF (match_operand:SF 1 "register_operand" "0,0"))) (clobber (reg:CC REG_CC))] "reload_completed" "@ @@ -7132,7 +7127,7 @@ : "rjmp %x0"; } [(set (attr "length") - (if_then_else (match_operand 0 "symbol_ref_operand" "") + (if_then_else (match_operand 0 "symbol_ref_operand" "") (if_then_else (match_test "!AVR_HAVE_JMP_CALL") (const_int 1) (const_int 2)) @@ -7695,7 +7690,6 @@ (pc)))] "dead_or_set_regno_p (insn, REG_CC)" { - const char *op; int jump_mode; if (avr_adiw_reg_p (operands[0])) output_asm_insn ("sbiw %0,1", operands); @@ -7704,7 +7698,7 @@ "sbc %B0,__zero_reg__", operands); jump_mode = avr_jump_mode (operands[2], insn); - op = ((EQ == ) ^ (jump_mode == 1)) ? "brcc" : "brcs"; + const char *op = ((EQ == ) ^ (jump_mode == 1)) ? "brcc" : "brcs"; operands[1] = gen_rtx_CONST_STRING (VOIDmode, op); switch (jump_mode) @@ -7736,16 +7730,14 @@ (pc)))] "dead_or_set_regno_p (insn, REG_CC)" { - const char *op; - int jump_mode; if (avr_adiw_reg_p (operands[0])) output_asm_insn ("sbiw %0,1", operands); else output_asm_insn ("subi %A0,1" CR_TAB "sbc %B0,__zero_reg__", operands); - jump_mode = avr_jump_mode (operands[2], insn); - op = ((EQ == ) ^ (jump_mode == 1)) ? "brcc" : "brcs"; + int jump_mode = avr_jump_mode (operands[2], insn); + const char *op = ((EQ == ) ^ (jump_mode == 1)) ? "brcc" : "brcs"; operands[1] = gen_rtx_CONST_STRING (VOIDmode, op); switch (jump_mode) @@ -7777,14 +7769,12 @@ (pc)))] "dead_or_set_regno_p (insn, REG_CC)" { - const char *op; - int jump_mode; output_asm_insn ("ldi %3,1" CR_TAB "sub %A0,%3" CR_TAB "sbc %B0,__zero_reg__", operands); - jump_mode = avr_jump_mode (operands[2], insn); - op = ((EQ == ) ^ (jump_mode == 1)) ? "brcc" : "brcs"; + int jump_mode = avr_jump_mode (operands[2], insn); + const char *op = ((EQ == ) ^ (jump_mode == 1)) ? "brcc" : "brcs"; operands[1] = gen_rtx_CONST_STRING (VOIDmode, op); switch (jump_mode) @@ -7813,13 +7803,10 @@ (pc)))] "dead_or_set_regno_p (insn, REG_CC)" { - const char *op; - int jump_mode; - output_asm_insn ("subi %A0,1", operands); - jump_mode = avr_jump_mode (operands[1], insn); - op = ((EQ == ) ^ (jump_mode == 1)) ? "brcc" : "brcs"; + int jump_mode = avr_jump_mode (operands[1], insn); + const char *op = ((EQ == ) ^ (jump_mode == 1)) ? "brcc" : "brcs"; operands[0] = gen_rtx_CONST_STRING (VOIDmode, op); switch (jump_mode) @@ -7927,7 +7914,7 @@ [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "L,P")] UNSPECV_ENABLE_IRQS) (set (match_operand:BLK 1 "" "") - (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))] + (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))] "" "@ cli @@ -8067,7 +8054,7 @@ (const_int 1)] UNSPECV_DELAY_CYCLES) (set (match_operand:BLK 1 "" "") - (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) (clobber (match_scratch:QI 2 "=&d"))] "" "#" @@ -8085,7 +8072,7 @@ (const_int 1)] UNSPECV_DELAY_CYCLES) (set (match_operand:BLK 1 "" "") - (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) (clobber (match_scratch:QI 2 "=&d")) (clobber (reg:CC REG_CC))] "reload_completed" @@ -8099,7 +8086,7 @@ (const_int 2)] UNSPECV_DELAY_CYCLES) (set (match_operand:BLK 1 "" "") - (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) (clobber (match_scratch:HI 2 "=&w,&d"))] "" "#" @@ -8119,7 +8106,7 @@ (const_int 2)] UNSPECV_DELAY_CYCLES) (set (match_operand:BLK 1 "" "") - (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) (clobber (match_scratch:HI 2 "=&w,&d")) (clobber (reg:CC REG_CC))] "reload_completed" @@ -8134,7 +8121,7 @@ (const_int 3)] UNSPECV_DELAY_CYCLES) (set (match_operand:BLK 1 "" "") - (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) (clobber (match_scratch:QI 2 "=&d")) (clobber (match_scratch:QI 3 "=&d")) (clobber (match_scratch:QI 4 "=&d"))] @@ -8156,7 +8143,7 @@ (const_int 3)] UNSPECV_DELAY_CYCLES) (set (match_operand:BLK 1 "" "") - (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) (clobber (match_scratch:QI 2 "=&d")) (clobber (match_scratch:QI 3 "=&d")) (clobber (match_scratch:QI 4 "=&d")) @@ -8176,7 +8163,7 @@ (const_int 4)] UNSPECV_DELAY_CYCLES) (set (match_operand:BLK 1 "" "") - (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) (clobber (match_scratch:QI 2 "=&d")) (clobber (match_scratch:QI 3 "=&d")) (clobber (match_scratch:QI 4 "=&d")) @@ -8200,7 +8187,7 @@ (const_int 4)] UNSPECV_DELAY_CYCLES) (set (match_operand:BLK 1 "" "") - (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) + (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER)) (clobber (match_scratch:QI 2 "=&d")) (clobber (match_scratch:QI 3 "=&d")) (clobber (match_scratch:QI 4 "=&d")) @@ -8781,7 +8768,7 @@ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "P,K")] UNSPECV_NOP) (set (match_operand:BLK 1 "" "") - (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))] + (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))] "" "@ nop @@ -8803,7 +8790,7 @@ (define_insn "*sleep" [(unspec_volatile [(const_int 0)] UNSPECV_SLEEP) (set (match_operand:BLK 0 "" "") - (unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))] + (unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))] "" "sleep" [(set_attr "length" "1")]) @@ -8823,7 +8810,7 @@ (define_insn "*wdr" [(unspec_volatile [(const_int 0)] UNSPECV_WDR) (set (match_operand:BLK 0 "" "") - (unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))] + (unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))] "" "wdr" [(set_attr "length" "1")]) diff --git a/gcc/config/avr/constraints.md b/gcc/config/avr/constraints.md index 91d2aa3..81ed63d 100644 --- a/gcc/config/avr/constraints.md +++ b/gcc/config/avr/constraints.md @@ -239,25 +239,25 @@ (define_constraint "Y01" "Fixed-point or integer constant with bit representation 0x1" (ior (and (match_code "const_fixed") - (match_test "INTVAL (avr_to_int_mode (op)) == 1")) + (match_test "INTVAL (avr_to_int_mode (op)) == 1")) (match_test "satisfies_constraint_P (op)"))) (define_constraint "Ym1" "Fixed-point or integer constant with bit representation -0x1" (ior (and (match_code "const_fixed") - (match_test "INTVAL (avr_to_int_mode (op)) == -1")) + (match_test "INTVAL (avr_to_int_mode (op)) == -1")) (match_test "satisfies_constraint_N (op)"))) (define_constraint "Y02" "Fixed-point or integer constant with bit representation 0x2" (ior (and (match_code "const_fixed") - (match_test "INTVAL (avr_to_int_mode (op)) == 2")) + (match_test "INTVAL (avr_to_int_mode (op)) == 2")) (match_test "satisfies_constraint_K (op)"))) (define_constraint "Ym2" "Fixed-point or integer constant with bit representation -0x2" (ior (and (match_code "const_fixed") - (match_test "INTVAL (avr_to_int_mode (op)) == -2")) + (match_test "INTVAL (avr_to_int_mode (op)) == -2")) (match_test "satisfies_constraint_Cm2 (op)"))) ;; Constraint that's the empty set. Useful with mode and code iterators. diff --git a/gcc/config/avr/predicates.md b/gcc/config/avr/predicates.md index 97fe222..1201366 100644 --- a/gcc/config/avr/predicates.md +++ b/gcc/config/avr/predicates.md @@ -50,10 +50,10 @@ ;; Return true if OP is a valid address for lower half of I/O space. (define_special_predicate "low_io_address_operand" (ior (and (match_code "const_int") - (match_test "IN_RANGE (INTVAL (op) - avr_arch->sfr_offset, - 0, 0x1F)")) + (match_test "IN_RANGE (INTVAL (op) - avr_arch->sfr_offset, + 0, 0x1F)")) (and (match_code "symbol_ref") - (match_test "SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_IO_LOW")))) + (match_test "SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_IO_LOW")))) ;; Return true if OP is a register_operand or low_io_operand. (define_predicate "reg_or_low_io_operand" @@ -74,10 +74,10 @@ ;; Return true if OP is a valid address of I/O space. (define_special_predicate "io_address_operand" (ior (and (match_code "const_int") - (match_test "IN_RANGE (INTVAL (op) - avr_arch->sfr_offset, - 0, 0x3F)")) + (match_test "IN_RANGE (INTVAL (op) - avr_arch->sfr_offset, + 0, 0x3F)")) (and (match_code "symbol_ref") - (match_test "SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_IO")))) + (match_test "SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_IO")))) ;; Return 1 if OP is a general operand not in flash memory (define_predicate "nop_general_operand" @@ -185,8 +185,8 @@ case SYMBOL_REF : return SYMBOL_REF_FUNCTION_P (op); case PLUS : - /* Assume canonical format of symbol + constant. - Fall through. */ + // Assume canonical format of symbol + constant. + // Fall through. case CONST : return text_segment_operand (XEXP (op, 0), VOIDmode); default : -- cgit v1.1 From 24975a9195743e8eb4ca213f35b9221d4eeb6b59 Mon Sep 17 00:00:00 2001 From: Greg McGary Date: Sun, 3 Mar 2024 14:49:49 -0700 Subject: [PATCH] combine: Don't simplify paradoxical SUBREG on WORD_REGISTER_OPERATIONS [PR113010] The sign-bit-copies of a sign-extending load cannot be known until runtime on WORD_REGISTER_OPERATIONS targets, except in the case of a zero-extending MEM load. See the fix for PR112758. gcc/ PR rtl-optimization/113010 * combine.cc (simplify_comparison): Simplify a SUBREG on WORD_REGISTER_OPERATIONS targets only if it is a zero-extending MEM load. gcc/testsuite * gcc.c-torture/execute/pr113010.c: New test. --- gcc/combine.cc | 15 +++++++++++++-- gcc/testsuite/gcc.c-torture/execute/pr113010.c | 9 +++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr113010.c (limited to 'gcc') diff --git a/gcc/combine.cc b/gcc/combine.cc index 76543d8..b09200d 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -12550,9 +12550,20 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) } /* If the inner mode is narrower and we are extracting the low part, - we can treat the SUBREG as if it were a ZERO_EXTEND. */ + we can treat the SUBREG as if it were a ZERO_EXTEND ... */ if (paradoxical_subreg_p (op0)) - ; + { + if (WORD_REGISTER_OPERATIONS + && GET_MODE_PRECISION (inner_mode) < BITS_PER_WORD + /* On WORD_REGISTER_OPERATIONS targets the bits + beyond sub_mode aren't considered undefined, + so optimize only if it is a MEM load when MEM loads + zero extend, because then the upper bits are all zero. */ + && !(MEM_P (SUBREG_REG (op0)) + && load_extend_op (inner_mode) == ZERO_EXTEND)) + break; + /* FALLTHROUGH to case ZERO_EXTEND */ + } else if (subreg_lowpart_p (op0) && GET_MODE_CLASS (mode) == MODE_INT && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode) diff --git a/gcc/testsuite/gcc.c-torture/execute/pr113010.c b/gcc/testsuite/gcc.c-torture/execute/pr113010.c new file mode 100644 index 0000000..2c84333 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr113010.c @@ -0,0 +1,9 @@ +int minus_1 = -1; + +int +main () +{ + if ((0, 0xffffffffull) >= minus_1) + __builtin_abort (); + return 0; +} -- cgit v1.1 From bbfbaa792b50ebd75b383be25f50c92f30243256 Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Sun, 3 Mar 2024 20:28:58 +0100 Subject: d: Merge upstream dmd, druntime f8bae04558, phobos ba2ade9dec D front-end changes: - Import dmd v2.108.1-beta-1. D runtime changes: - Import druntime v2.108.1-beta-1. Phobos changes: - Import phobos v2.108.1-beta-1. gcc/d/ChangeLog: * dmd/MERGE: Merge upstream dmd f8bae04558. * dmd/VERSION: Bump version to v2.108.0-beta.1. * d-builtins.cc (build_frontend_type): Update for new front-end interface. * d-codegen.cc (build_assert_call): Likewise. * d-convert.cc (d_array_convert): Likewise. * decl.cc (get_vtable_decl): Likewise. * expr.cc (ExprVisitor::visit (EqualExp *)): Likewise. (ExprVisitor::visit (VarExp *)): Likewise. (ExprVisitor::visit (ArrayLiteralExp *)): Likewise. (ExprVisitor::visit (AssocArrayLiteralExp)): Likewise. * intrinsics.cc (build_shuffle_mask_type): Likewise. (maybe_warn_intrinsic_mismatch): Likewise. * runtime.cc (get_libcall_type): Likewise. * typeinfo.cc (TypeInfoVisitor::layout_string): Likewise. (TypeInfoVisitor::visit(TypeInfoTupleDeclaration *)): Likewise. libphobos/ChangeLog: * libdruntime/MERGE: Merge upstream druntime 02d6d07a69. * src/MERGE: Merge upstream phobos a2ade9dec. --- gcc/d/d-builtins.cc | 6 +- gcc/d/d-codegen.cc | 2 +- gcc/d/d-convert.cc | 4 +- gcc/d/decl.cc | 2 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/VERSION | 2 +- gcc/d/dmd/constfold.d | 2 +- gcc/d/dmd/cparse.d | 8 +- gcc/d/dmd/cxxfrontend.d | 36 +++ gcc/d/dmd/denum.d | 1 - gcc/d/dmd/dinterpret.d | 4 +- gcc/d/dmd/dmodule.d | 16 +- gcc/d/dmd/expressionsem.d | 14 +- gcc/d/dmd/func.d | 176 -------------- gcc/d/dmd/funcsem.d | 168 +++++++++++++ gcc/d/dmd/location.d | 10 +- gcc/d/dmd/mtype.d | 321 +------------------------ gcc/d/dmd/mtype.h | 14 +- gcc/d/dmd/optimize.d | 2 +- gcc/d/dmd/safe.d | 2 +- gcc/d/dmd/typesem.d | 317 +++++++++++++++++++++++- gcc/d/expr.cc | 21 +- gcc/d/intrinsics.cc | 6 +- gcc/d/runtime.cc | 20 +- gcc/d/typeinfo.cc | 4 +- gcc/testsuite/gdc.test/compilable/issue24399.d | 9 + gcc/testsuite/gdc.test/compilable/issue24409.d | 17 ++ gcc/testsuite/gdc.test/runnable/issue24401.d | 6 + gcc/testsuite/gdc.test/runnable/test24371.d | 15 ++ gcc/testsuite/gdc.test/runnable_cxx/test7925.d | 7 - 30 files changed, 644 insertions(+), 570 deletions(-) create mode 100644 gcc/testsuite/gdc.test/compilable/issue24399.d create mode 100644 gcc/testsuite/gdc.test/compilable/issue24409.d create mode 100644 gcc/testsuite/gdc.test/runnable/issue24401.d create mode 100644 gcc/testsuite/gdc.test/runnable/test24371.d (limited to 'gcc') diff --git a/gcc/d/d-builtins.cc b/gcc/d/d-builtins.cc index dc50df4..4546c0e 100644 --- a/gcc/d/d-builtins.cc +++ b/gcc/d/d-builtins.cc @@ -197,8 +197,8 @@ build_frontend_type (tree type) length = size_binop (PLUS_EXPR, size_one_node, convert (sizetype, length)); - dtype = - dmd::addMod (dtype->sarrayOf (TREE_INT_CST_LOW (length)), mod); + dtype = dmd::sarrayOf (dtype, TREE_INT_CST_LOW (length)); + dtype = dmd::addMod (dtype, mod); builtin_converted_decls.safe_push (builtin_data (dtype, type)); return dtype; } @@ -214,7 +214,7 @@ build_frontend_type (tree type) if (!dtype) break; - dtype = dmd::addMod (dtype->sarrayOf (nunits), mod); + dtype = dmd::addMod (dmd::sarrayOf (dtype, nunits), mod); if (target.isVectorTypeSupported (dtype->size (), dtype->nextOf ())) break; diff --git a/gcc/d/d-codegen.cc b/gcc/d/d-codegen.cc index 43d7739f..2b3089b 100644 --- a/gcc/d/d-codegen.cc +++ b/gcc/d/d-codegen.cc @@ -1906,7 +1906,7 @@ build_assert_call (const Loc &loc, libcall_fn libcall, tree msg) tree str = build_string (len, filename); TREE_TYPE (str) = make_array_type (Type::tchar, len); - file = d_array_value (build_ctype (Type::tchar->arrayOf ()), + file = d_array_value (build_ctype (dmd::arrayOf (Type::tchar)), size_int (len), build_address (str)); } else diff --git a/gcc/d/d-convert.cc b/gcc/d/d-convert.cc index 4ccbf09..5c79cdf 100644 --- a/gcc/d/d-convert.cc +++ b/gcc/d/d-convert.cc @@ -957,7 +957,7 @@ d_array_convert (Expression *exp) if (tb->ty == TY::Tsarray) { - Type *totype = tb->nextOf ()->arrayOf (); + Type *totype = dmd::arrayOf (tb->nextOf ()); return convert_expr (build_expr (exp), exp->type, totype); } @@ -986,7 +986,7 @@ d_array_convert (Type *etype, Expression *exp) expr = compound_expr (modify_expr (var, expr), var); } - return d_array_value (build_ctype (exp->type->arrayOf ()), + return d_array_value (build_ctype (dmd::arrayOf (exp->type)), size_int (1), build_address (expr)); } else diff --git a/gcc/d/decl.cc b/gcc/d/decl.cc index 25398a3..3b7627d 100644 --- a/gcc/d/decl.cc +++ b/gcc/d/decl.cc @@ -2211,7 +2211,7 @@ get_vtable_decl (ClassDeclaration *decl) tree ident = mangle_internal_decl (decl, "__vtbl", "Z"); /* Note: Using a static array type for the VAR_DECL, the DECL_INITIAL value will have a different type. However the back-end seems to accept this. */ - tree type = build_ctype (Type::tvoidptr->sarrayOf (decl->vtbl.length)); + tree type = build_ctype (dmd::sarrayOf (Type::tvoidptr, decl->vtbl.length)); Dsymbol *vtblsym = decl->vtblSymbol (); vtblsym->csym = declare_extern_var (ident, type); diff --git a/gcc/d/dmd/MERGE b/gcc/d/dmd/MERGE index f11c5fb..4c0a0bc 100644 --- a/gcc/d/dmd/MERGE +++ b/gcc/d/dmd/MERGE @@ -1,4 +1,4 @@ -ceff48bf7db05503117f54fdc0cefcb89b711136 +f8bae0455851a1dfc8113d69323415f6de549e39 The first line of this file holds the git revision number of the last merge done from the dlang/dmd repository. diff --git a/gcc/d/dmd/VERSION b/gcc/d/dmd/VERSION index 1880c98..4168076 100644 --- a/gcc/d/dmd/VERSION +++ b/gcc/d/dmd/VERSION @@ -1 +1 @@ -v2.107.1-rc.1 +v2.108.0-beta.1 diff --git a/gcc/d/dmd/constfold.d b/gcc/d/dmd/constfold.d index 0686e1b..6ec31d5 100644 --- a/gcc/d/dmd/constfold.d +++ b/gcc/d/dmd/constfold.d @@ -36,7 +36,7 @@ import dmd.root.utf; import dmd.sideeffect; import dmd.target; import dmd.tokens; -import dmd.typesem : toDsymbol, equivalent; +import dmd.typesem : toDsymbol, equivalent, sarrayOf; private enum LOG = false; diff --git a/gcc/d/dmd/cparse.d b/gcc/d/dmd/cparse.d index e917d2c..aeedb49 100644 --- a/gcc/d/dmd/cparse.d +++ b/gcc/d/dmd/cparse.d @@ -2155,7 +2155,7 @@ final class CParser(AST) : Parser!AST error("function identifier-list cannot end with `...`"); ft.parameterList.varargs = AST.VarArg.KRvariadic; // but C11 allows extra arguments auto plLength = pl.length; - if (symbols.length != plLength) + if (symbols && symbols.length != plLength) error(token.loc, "%d identifiers does not match %d declarations", cast(int)plLength, cast(int)symbols.length); /* Transfer the types and storage classes from symbols[] to pl[] @@ -2176,6 +2176,12 @@ final class CParser(AST) : Parser!AST if (p.type || !(p.storageClass & STC.parameter)) error("storage class and type are not allowed in identifier-list"); + if (!symbols) + { + // Error already given in cparseDeclaration + p.type = AST.Type.terror; + continue; + } foreach (s; (*symbols)[]) // yes, quadratic { auto ad = s.isAttribDeclaration(); diff --git a/gcc/d/dmd/cxxfrontend.d b/gcc/d/dmd/cxxfrontend.d index 1b94a69..8c04634 100644 --- a/gcc/d/dmd/cxxfrontend.d +++ b/gcc/d/dmd/cxxfrontend.d @@ -475,6 +475,18 @@ bool equivalent(Type src, Type t) return dmd.typesem.equivalent(src, t); } +Type sarrayOf(Type type, dinteger_t dim) +{ + import dmd.typesem; + return dmd.typesem.sarrayOf(type, dim); +} + +Type arrayOf(Type type) +{ + import dmd.typesem; + return dmd.typesem.arrayOf(type); +} + Type constOf(Type type) { import dmd.typesem; @@ -535,6 +547,30 @@ Type sharedWildConstOf(Type type) return dmd.typesem.sharedWildConstOf(type); } +Type substWildTo(Type type, uint mod) +{ + import dmd.typesem; + return dmd.typesem.substWildTo(type, mod); +} + +Type unqualify(Type type, uint m) +{ + import dmd.typesem; + return dmd.typesem.unqualify(type, m); +} + +Type toHeadMutable(const(Type) type) +{ + import dmd.typesem; + return dmd.typesem.toHeadMutable(type); +} + +Type aliasthisOf(Type type) +{ + import dmd.typesem; + return dmd.typesem.aliasthisOf(type); +} + Type castMod(Type type, MOD mod) { import dmd.typesem; diff --git a/gcc/d/dmd/denum.d b/gcc/d/dmd/denum.d index 3679976..5c739ee 100644 --- a/gcc/d/dmd/denum.d +++ b/gcc/d/dmd/denum.d @@ -20,7 +20,6 @@ import dmd.astenums; import dmd.attrib; import dmd.gluelayer; import dmd.declaration; -import dmd.dscope; import dmd.dsymbol; import dmd.expression; import dmd.id; diff --git a/gcc/d/dmd/dinterpret.d b/gcc/d/dmd/dinterpret.d index 467e29f..c492490 100644 --- a/gcc/d/dmd/dinterpret.d +++ b/gcc/d/dmd/dinterpret.d @@ -50,7 +50,7 @@ import dmd.rootobject; import dmd.root.utf; import dmd.statement; import dmd.tokens; -import dmd.typesem : mutableOf, equivalent, pointerTo; +import dmd.typesem : mutableOf, equivalent, pointerTo, sarrayOf, arrayOf; import dmd.utils : arrayCastBigEndian; import dmd.visitor; @@ -3787,7 +3787,7 @@ public: if (v is v2 || !v.isOverlappedWith(v2)) continue; auto e = (*sle.elements)[i]; - if (e.op != EXP.void_) + if (e !is null && e.op != EXP.void_) (*sle.elements)[i] = voidInitLiteral(e.type, v).copy(); } } diff --git a/gcc/d/dmd/dmodule.d b/gcc/d/dmd/dmodule.d index a77e4f3..58bf3fd 100644 --- a/gcc/d/dmd/dmodule.d +++ b/gcc/d/dmd/dmodule.d @@ -1394,6 +1394,7 @@ private const(char)[] processSource (const(ubyte)[] src, Module mod) { enum SourceEncoding { utf16, utf32} enum Endian { little, big} + immutable loc = mod.getLoc(); /* * Convert a buffer from UTF32 to UTF8 @@ -1413,7 +1414,7 @@ private const(char)[] processSource (const(ubyte)[] src, Module mod) if (buf.length & 3) { - .error(mod.loc, "%s `%s` odd length of UTF-32 char source %llu", + .error(loc, "%s `%s` odd length of UTF-32 char source %llu", mod.kind, mod.toPrettyChars, cast(ulong) buf.length); return null; } @@ -1430,7 +1431,7 @@ private const(char)[] processSource (const(ubyte)[] src, Module mod) { if (u > 0x10FFFF) { - .error(mod.loc, "%s `%s` UTF-32 value %08x greater than 0x10FFFF", mod.kind, mod.toPrettyChars, u); + .error(loc, "%s `%s` UTF-32 value %08x greater than 0x10FFFF", mod.kind, mod.toPrettyChars, u); return null; } dbuf.writeUTF8(u); @@ -1460,7 +1461,7 @@ private const(char)[] processSource (const(ubyte)[] src, Module mod) if (buf.length & 1) { - .error(mod.loc, "%s `%s` odd length of UTF-16 char source %llu", mod.kind, mod.toPrettyChars, cast(ulong) buf.length); + .error(loc, "%s `%s` odd length of UTF-16 char source %llu", mod.kind, mod.toPrettyChars, cast(ulong) buf.length); return null; } @@ -1480,13 +1481,13 @@ private const(char)[] processSource (const(ubyte)[] src, Module mod) i++; if (i >= eBuf.length) { - .error(mod.loc, "%s `%s` surrogate UTF-16 high value %04x at end of file", mod.kind, mod.toPrettyChars, u); + .error(loc, "%s `%s` surrogate UTF-16 high value %04x at end of file", mod.kind, mod.toPrettyChars, u); return null; } const u2 = readNext(&eBuf[i]); if (u2 < 0xDC00 || 0xE000 <= u2) { - .error(mod.loc, "%s `%s` surrogate UTF-16 low value %04x out of range", mod.kind, mod.toPrettyChars, u2); + .error(loc, "%s `%s` surrogate UTF-16 low value %04x out of range", mod.kind, mod.toPrettyChars, u2); return null; } u = (u - 0xD7C0) << 10; @@ -1494,12 +1495,12 @@ private const(char)[] processSource (const(ubyte)[] src, Module mod) } else if (u >= 0xDC00 && u <= 0xDFFF) { - .error(mod.loc, "%s `%s` unpaired surrogate UTF-16 value %04x", mod.kind, mod.toPrettyChars, u); + .error(loc, "%s `%s` unpaired surrogate UTF-16 value %04x", mod.kind, mod.toPrettyChars, u); return null; } else if (u == 0xFFFE || u == 0xFFFF) { - .error(mod.loc, "%s `%s` illegal UTF-16 value %04x", mod.kind, mod.toPrettyChars, u); + .error(loc, "%s `%s` illegal UTF-16 value %04x", mod.kind, mod.toPrettyChars, u); return null; } dbuf.writeUTF8(u); @@ -1558,7 +1559,6 @@ private const(char)[] processSource (const(ubyte)[] src, Module mod) // It's UTF-8 if (buf[0] >= 0x80) { - auto loc = mod.getLoc(); .error(loc, "%s `%s` source file must start with BOM or ASCII character, not \\x%02X", mod.kind, mod.toPrettyChars, buf[0]); return null; } diff --git a/gcc/d/dmd/expressionsem.d b/gcc/d/dmd/expressionsem.d index b4d5274..db40ae0 100644 --- a/gcc/d/dmd/expressionsem.d +++ b/gcc/d/dmd/expressionsem.d @@ -12357,8 +12357,16 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor return result; } - void handleCatArgument(Expressions *arguments, Expression e) + void handleCatArgument(Expressions *arguments, Expression e, Type catType, bool isRightArg) { + auto tb = e.type.toBasetype(); + + if ((isRightArg && e.parens) || (!isRightArg && !tb.equals(catType))) + { + arguments.push(e); + return; + } + if (auto ce = e.isCatExp()) { Expression lowering = ce.lowering; @@ -12388,8 +12396,8 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor arguments.push(new StringExp(exp.loc, funcname.toDString())); } - handleCatArgument(arguments, exp.e1); - handleCatArgument(arguments, exp.e2); + handleCatArgument(arguments, exp.e1, exp.type.toBasetype(), false); + handleCatArgument(arguments, exp.e2, exp.type.toBasetype(), true); Expression id = new IdentifierExp(exp.loc, Id.empty); id = new DotIdExp(exp.loc, id, Id.object); diff --git a/gcc/d/dmd/func.d b/gcc/d/dmd/func.d index d890811..7003c2b 100644 --- a/gcc/d/dmd/func.d +++ b/gcc/d/dmd/func.d @@ -34,12 +34,10 @@ import dmd.dmodule; import dmd.dscope; import dmd.dstruct; import dmd.dsymbol; -import dmd.dsymbolsem; import dmd.dtemplate; import dmd.errors; import dmd.escape; import dmd.expression; -import dmd.funcsem; import dmd.globals; import dmd.hdrgen; import dmd.id; @@ -57,7 +55,6 @@ import dmd.semantic2; import dmd.semantic3; import dmd.statement_rewrite_walker; import dmd.statement; -import dmd.statementsem; import dmd.tokens; import dmd.typesem; import dmd.visitor; @@ -115,90 +112,6 @@ enum BUILTIN : ubyte toPrecReal } -/* Tweak all return statements and dtor call for nrvo_var, for correct NRVO. - */ -extern (C++) final class NrvoWalker : StatementRewriteWalker -{ - alias visit = typeof(super).visit; -public: - FuncDeclaration fd; - Scope* sc; - - override void visit(ReturnStatement s) - { - // See if all returns are instead to be replaced with a goto returnLabel; - if (fd.returnLabel) - { - /* Rewrite: - * return exp; - * as: - * vresult = exp; goto Lresult; - */ - auto gs = new GotoStatement(s.loc, Id.returnLabel); - gs.label = fd.returnLabel; - - Statement s1 = gs; - if (s.exp) - s1 = new CompoundStatement(s.loc, new ExpStatement(s.loc, s.exp), gs); - - replaceCurrent(s1); - } - } - - override void visit(TryFinallyStatement s) - { - DtorExpStatement des; - if (fd.isNRVO() && s.finalbody && (des = s.finalbody.isDtorExpStatement()) !is null && - fd.nrvo_var == des.var) - { - if (!(global.params.useExceptions && ClassDeclaration.throwable)) - { - /* Don't need to call destructor at all, since it is nrvo - */ - replaceCurrent(s._body); - s._body.accept(this); - return; - } - - /* Normally local variable dtors are called regardless exceptions. - * But for nrvo_var, its dtor should be called only when exception is thrown. - * - * Rewrite: - * try { s.body; } finally { nrvo_var.edtor; } - * // equivalent with: - * // s.body; scope(exit) nrvo_var.edtor; - * as: - * try { s.body; } catch(Throwable __o) { nrvo_var.edtor; throw __o; } - * // equivalent with: - * // s.body; scope(failure) nrvo_var.edtor; - */ - Statement sexception = new DtorExpStatement(Loc.initial, fd.nrvo_var.edtor, fd.nrvo_var); - Identifier id = Identifier.generateId("__o"); - - Statement handler = new PeelStatement(sexception); - if (sexception.blockExit(fd, null) & BE.fallthru) - { - auto ts = new ThrowStatement(Loc.initial, new IdentifierExp(Loc.initial, id)); - ts.internalThrow = true; - handler = new CompoundStatement(Loc.initial, handler, ts); - } - - auto catches = new Catches(); - auto ctch = new Catch(Loc.initial, getThrowable(), id, handler); - ctch.internalCatch = true; - ctch.catchSemantic(sc); // Run semantic to resolve identifier '__o' - catches.push(ctch); - - Statement s2 = new TryCatchStatement(Loc.initial, s._body, catches); - fd.hasNoEH = false; - replaceCurrent(s2); - s2.accept(this); - } - else - StatementRewriteWalker.visit(s); - } -} - private struct FUNCFLAG { bool purityInprocess; /// working on determining purity @@ -2022,44 +1935,6 @@ extern (C++) class FuncDeclaration : Declaration } /**************************************************** - * Declare result variable lazily. - */ - extern (D) final void buildResultVar(Scope* sc, Type tret) - { - if (!vresult) - { - Loc loc = fensure ? fensure.loc : this.loc; - - /* If inferRetType is true, tret may not be a correct return type yet. - * So, in here it may be a temporary type for vresult, and after - * fbody.dsymbolSemantic() running, vresult.type might be modified. - */ - vresult = new VarDeclaration(loc, tret, Id.result, null); - vresult.storage_class |= STC.nodtor | STC.temp; - if (!isVirtual()) - vresult.storage_class |= STC.const_; - vresult.storage_class |= STC.result; - - // set before the semantic() for checkNestedReference() - vresult.parent = this; - } - - if (sc && vresult.semanticRun == PASS.initial) - { - TypeFunction tf = type.toTypeFunction(); - if (tf.isref) - vresult.storage_class |= STC.ref_; - vresult.type = tret; - - vresult.dsymbolSemantic(sc); - - if (!sc.insert(vresult)) - .error(loc, "%s `%s` out result %s is already defined", kind, toPrettyChars, vresult.toChars()); - assert(vresult.parent == this); - } - } - - /**************************************************** * Merge into this function the 'in' contracts of all it overrides. * 'in's are OR'd together, i.e. only one of them needs to pass. */ @@ -2680,57 +2555,6 @@ extern (C++) class FuncDeclaration : Declaration } } -/******************************************************** - * Generate Expression to call the invariant. - * Input: - * ad aggregate with the invariant - * vthis variable with 'this' - * Returns: - * void expression that calls the invariant - */ -Expression addInvariant(AggregateDeclaration ad, VarDeclaration vthis) -{ - Expression e = null; - // Call invariant directly only if it exists - FuncDeclaration inv = ad.inv; - ClassDeclaration cd = ad.isClassDeclaration(); - - while (!inv && cd) - { - cd = cd.baseClass; - if (!cd) - break; - inv = cd.inv; - } - if (inv) - { - version (all) - { - // Workaround for https://issues.dlang.org/show_bug.cgi?id=13394 - // For the correct mangling, - // run attribute inference on inv if needed. - functionSemantic(inv); - } - - //e = new DsymbolExp(Loc.initial, inv); - //e = new CallExp(Loc.initial, e); - //e = e.semantic(sc2); - - /* https://issues.dlang.org/show_bug.cgi?id=13113 - * Currently virtual invariant calls completely - * bypass attribute enforcement. - * Change the behavior of pre-invariant call by following it. - */ - e = new ThisExp(Loc.initial); - e.type = ad.type.addMod(vthis.type.mod); - e = new DotVarExp(Loc.initial, e, inv, false); - e.type = inv.type; - e = new CallExp(Loc.initial, e); - e.type = Type.tvoid; - } - return e; -} - /*************************************************** * Visit each overloaded function/template in turn, and call dg(s) on it. * Exit when no more, or dg(s) returns nonzero. diff --git a/gcc/d/dmd/funcsem.d b/gcc/d/dmd/funcsem.d index b8b185c..2cadc40 100644 --- a/gcc/d/dmd/funcsem.d +++ b/gcc/d/dmd/funcsem.d @@ -65,6 +65,90 @@ import dmd.tokens; import dmd.typesem; import dmd.visitor; +/* Tweak all return statements and dtor call for nrvo_var, for correct NRVO. + */ +extern (C++) final class NrvoWalker : StatementRewriteWalker +{ + alias visit = typeof(super).visit; +public: + FuncDeclaration fd; + Scope* sc; + + override void visit(ReturnStatement s) + { + // See if all returns are instead to be replaced with a goto returnLabel; + if (fd.returnLabel) + { + /* Rewrite: + * return exp; + * as: + * vresult = exp; goto Lresult; + */ + auto gs = new GotoStatement(s.loc, Id.returnLabel); + gs.label = fd.returnLabel; + + Statement s1 = gs; + if (s.exp) + s1 = new CompoundStatement(s.loc, new ExpStatement(s.loc, s.exp), gs); + + replaceCurrent(s1); + } + } + + override void visit(TryFinallyStatement s) + { + DtorExpStatement des; + if (fd.isNRVO() && s.finalbody && (des = s.finalbody.isDtorExpStatement()) !is null && + fd.nrvo_var == des.var) + { + if (!(global.params.useExceptions && ClassDeclaration.throwable)) + { + /* Don't need to call destructor at all, since it is nrvo + */ + replaceCurrent(s._body); + s._body.accept(this); + return; + } + + /* Normally local variable dtors are called regardless exceptions. + * But for nrvo_var, its dtor should be called only when exception is thrown. + * + * Rewrite: + * try { s.body; } finally { nrvo_var.edtor; } + * // equivalent with: + * // s.body; scope(exit) nrvo_var.edtor; + * as: + * try { s.body; } catch(Throwable __o) { nrvo_var.edtor; throw __o; } + * // equivalent with: + * // s.body; scope(failure) nrvo_var.edtor; + */ + Statement sexception = new DtorExpStatement(Loc.initial, fd.nrvo_var.edtor, fd.nrvo_var); + Identifier id = Identifier.generateId("__o"); + + Statement handler = new PeelStatement(sexception); + if (sexception.blockExit(fd, null) & BE.fallthru) + { + auto ts = new ThrowStatement(Loc.initial, new IdentifierExp(Loc.initial, id)); + ts.internalThrow = true; + handler = new CompoundStatement(Loc.initial, handler, ts); + } + + auto catches = new Catches(); + auto ctch = new Catch(Loc.initial, getThrowable(), id, handler); + ctch.internalCatch = true; + ctch.catchSemantic(sc); // Run semantic to resolve identifier '__o' + catches.push(ctch); + + Statement s2 = new TryCatchStatement(Loc.initial, s._body, catches); + fd.hasNoEH = false; + replaceCurrent(s2); + s2.accept(this); + } + else + StatementRewriteWalker.visit(s); + } +} + /********************************** * Main semantic routine for functions. */ @@ -1755,3 +1839,87 @@ if (is(Decl == TemplateDeclaration) || is(Decl == FuncDeclaration)) if (constraintsTip) .tip(constraintsTip); } + +/******************************************************** + * Generate Expression to call the invariant. + * Input: + * ad aggregate with the invariant + * vthis variable with 'this' + * Returns: + * void expression that calls the invariant + */ +Expression addInvariant(AggregateDeclaration ad, VarDeclaration vthis) +{ + Expression e = null; + // Call invariant directly only if it exists + FuncDeclaration inv = ad.inv; + ClassDeclaration cd = ad.isClassDeclaration(); + + while (!inv && cd) + { + cd = cd.baseClass; + if (!cd) + break; + inv = cd.inv; + } + if (inv) + { + version (all) + { + // Workaround for https://issues.dlang.org/show_bug.cgi?id=13394 + // For the correct mangling, + // run attribute inference on inv if needed. + functionSemantic(inv); + } + + //e = new DsymbolExp(Loc.initial, inv); + //e = new CallExp(Loc.initial, e); + //e = e.semantic(sc2); + + /* https://issues.dlang.org/show_bug.cgi?id=13113 + * Currently virtual invariant calls completely + * bypass attribute enforcement. + * Change the behavior of pre-invariant call by following it. + */ + e = new ThisExp(Loc.initial); + e.type = ad.type.addMod(vthis.type.mod); + e = new DotVarExp(Loc.initial, e, inv, false); + e.type = inv.type; + e = new CallExp(Loc.initial, e); + e.type = Type.tvoid; + } + return e; +} + +/**************************************************** + * Declare result variable lazily. + */ +void buildResultVar(FuncDeclaration fd, Scope* sc, Type tret) +{ + if (!fd.vresult) + { + Loc loc = fd.fensure ? fd.fensure.loc : fd.loc; + /* If inferRetType is true, tret may not be a correct return type yet. + * So, in here it may be a temporary type for vresult, and after + * fbody.dsymbolSemantic() running, vresult.type might be modified. + */ + fd.vresult = new VarDeclaration(loc, tret, Id.result, null); + fd.vresult.storage_class |= STC.nodtor | STC.temp; + if (!fd.isVirtual()) + fd.vresult.storage_class |= STC.const_; + fd.vresult.storage_class |= STC.result; + // set before the semantic() for checkNestedReference() + fd.vresult.parent = fd; + } + if (sc && fd.vresult.semanticRun == PASS.initial) + { + TypeFunction tf = fd.type.toTypeFunction(); + if (tf.isref) + fd.vresult.storage_class |= STC.ref_; + fd.vresult.type = tret; + fd.vresult.dsymbolSemantic(sc); + if (!sc.insert(fd.vresult)) + .error(fd.loc, "%s `%s` out result %s is already defined", fd.kind, fd.toPrettyChars, fd.vresult.toChars()); + assert(fd.vresult.parent == fd); + } +} diff --git a/gcc/d/dmd/location.d b/gcc/d/dmd/location.d index d71ea58..ca6805e 100644 --- a/gcc/d/dmd/location.d +++ b/gcc/d/dmd/location.d @@ -115,15 +115,7 @@ nothrow: //printf("setting %s\n", name); filenames.push(name); fileIndex = cast(uint)filenames.length; - if (!fileIndex) - { - import dmd.globals : global; - import dmd.errors : error, fatal; - - global.gag = 0; // ensure error message gets printed - error(Loc.initial, "internal compiler error: file name index overflow!"); - fatal(); - } + assert(fileIndex, "internal compiler error: file name index overflow"); } else fileIndex = 0; diff --git a/gcc/d/dmd/mtype.d b/gcc/d/dmd/mtype.d index 843c402..2c9e058 100644 --- a/gcc/d/dmd/mtype.d +++ b/gcc/d/dmd/mtype.d @@ -1185,110 +1185,12 @@ extern (C++) abstract class Type : ASTNode return t; } - final Type arrayOf() - { - if (ty == Terror) - return this; - if (!arrayof) - { - Type t = new TypeDArray(this); - arrayof = t.merge(); - } - return arrayof; - } - - // Make corresponding static array type without semantic - final Type sarrayOf(dinteger_t dim) - { - assert(deco); - Type t = new TypeSArray(this, new IntegerExp(Loc.initial, dim, Type.tsize_t)); - // according to TypeSArray::semantic() - t = t.addMod(mod); - t = t.merge(); - return t; - } - final bool hasDeprecatedAliasThis() { auto ad = isAggregate(this); return ad && ad.aliasthis && (ad.aliasthis.isDeprecated || ad.aliasthis.sym.isDeprecated); } - final Type aliasthisOf() - { - auto ad = isAggregate(this); - if (!ad || !ad.aliasthis) - return null; - - auto s = ad.aliasthis.sym; - if (s.isAliasDeclaration()) - s = s.toAlias(); - - if (s.isTupleDeclaration()) - return null; - - if (auto vd = s.isVarDeclaration()) - { - auto t = vd.type; - if (vd.needThis()) - t = t.addMod(this.mod); - return t; - } - Dsymbol callable = s.isFuncDeclaration(); - callable = callable ? callable : s.isTemplateDeclaration(); - if (callable) - { - auto fd = resolveFuncCall(Loc.initial, null, callable, null, this, ArgumentList(), FuncResolveFlag.quiet); - if (!fd || fd.errors || !functionSemantic(fd)) - return Type.terror; - - auto t = fd.type.nextOf(); - if (!t) // https://issues.dlang.org/show_bug.cgi?id=14185 - return Type.terror; - t = t.substWildTo(mod == 0 ? MODFlags.mutable : mod); - return t; - } - if (auto d = s.isDeclaration()) - { - assert(d.type); - return d.type; - } - if (auto ed = s.isEnumDeclaration()) - { - return ed.type; - } - - //printf("%s\n", s.kind()); - return null; - } - - /** - * Check whether this type has endless `alias this` recursion. - * Returns: - * `true` if this type has an `alias this` that can be implicitly - * converted back to this type itself. - */ - extern (D) final bool checkAliasThisRec() - { - Type tb = toBasetype(); - AliasThisRec* pflag; - if (tb.ty == Tstruct) - pflag = &(cast(TypeStruct)tb).att; - else if (tb.ty == Tclass) - pflag = &(cast(TypeClass)tb).att; - else - return false; - - AliasThisRec flag = cast(AliasThisRec)(*pflag & AliasThisRec.typeMask); - if (flag == AliasThisRec.fwdref) - { - Type att = aliasthisOf(); - flag = att && att.implicitConvTo(this) ? AliasThisRec.yes : AliasThisRec.no; - } - *pflag = cast(AliasThisRec)(flag | (*pflag & ~AliasThisRec.typeMask)); - return flag == AliasThisRec.yes; - } - Type makeConst() { //printf("Type::makeConst() %p, %s\n", this, toChars()); @@ -1451,129 +1353,6 @@ extern (C++) abstract class Type : ASTNode return 0; } - Type substWildTo(uint mod) - { - //printf("+Type::substWildTo this = %s, mod = x%x\n", toChars(), mod); - Type t; - - if (Type tn = nextOf()) - { - // substitution has no effect on function pointer type. - if (ty == Tpointer && tn.ty == Tfunction) - { - t = this; - goto L1; - } - - t = tn.substWildTo(mod); - if (t == tn) - t = this; - else - { - if (ty == Tpointer) - t = t.pointerTo(); - else if (ty == Tarray) - t = t.arrayOf(); - else if (ty == Tsarray) - t = new TypeSArray(t, (cast(TypeSArray)this).dim.syntaxCopy()); - else if (ty == Taarray) - { - t = new TypeAArray(t, (cast(TypeAArray)this).index.syntaxCopy()); - } - else if (ty == Tdelegate) - { - t = new TypeDelegate(t.isTypeFunction()); - } - else - assert(0); - - t = t.merge(); - } - } - else - t = this; - - L1: - if (isWild()) - { - if (mod == MODFlags.immutable_) - { - t = t.immutableOf(); - } - else if (mod == MODFlags.wildconst) - { - t = t.wildConstOf(); - } - else if (mod == MODFlags.wild) - { - if (isWildConst()) - t = t.wildConstOf(); - else - t = t.wildOf(); - } - else if (mod == MODFlags.const_) - { - t = t.constOf(); - } - else - { - if (isWildConst()) - t = t.constOf(); - else - t = t.mutableOf(); - } - } - if (isConst()) - t = t.addMod(MODFlags.const_); - if (isShared()) - t = t.addMod(MODFlags.shared_); - - //printf("-Type::substWildTo t = %s\n", t.toChars()); - return t; - } - - final Type unqualify(uint m) - { - Type t = this.mutableOf().unSharedOf(); - - Type tn = ty == Tenum ? null : nextOf(); - if (tn && tn.ty != Tfunction) - { - Type utn = tn.unqualify(m); - if (utn != tn) - { - if (ty == Tpointer) - t = utn.pointerTo(); - else if (ty == Tarray) - t = utn.arrayOf(); - else if (ty == Tsarray) - t = new TypeSArray(utn, (cast(TypeSArray)this).dim); - else if (ty == Taarray) - { - t = new TypeAArray(utn, (cast(TypeAArray)this).index); - } - else - assert(0); - - t = t.merge(); - } - } - t = t.addMod(mod & ~m); - return t; - } - - /************************** - * Return type with the top level of it being mutable. - */ - inout(Type) toHeadMutable() inout - { - if (!mod) - return this; - Type unqualThis = cast(Type) this; - // `mutableOf` needs a mutable `this` only for caching - return cast(inout(Type)) unqualThis.mutableOf(); - } - inout(ClassDeclaration) isClassHandle() inout { return null; @@ -3396,55 +3175,6 @@ extern (C++) final class TypeFunction : TypeNext return linkage == LINK.d && parameterList.varargs == VarArg.variadic; } - override Type substWildTo(uint) - { - if (!iswild && !(mod & MODFlags.wild)) - return this; - - // Substitude inout qualifier of function type to mutable or immutable - // would break type system. Instead substitude inout to the most weak - // qualifer - const. - uint m = MODFlags.const_; - - assert(next); - Type tret = next.substWildTo(m); - Parameters* params = parameterList.parameters; - if (mod & MODFlags.wild) - params = parameterList.parameters.copy(); - for (size_t i = 0; i < params.length; i++) - { - Parameter p = (*params)[i]; - Type t = p.type.substWildTo(m); - if (t == p.type) - continue; - if (params == parameterList.parameters) - params = parameterList.parameters.copy(); - (*params)[i] = new Parameter(p.loc, p.storageClass, t, null, null, null); - } - if (next == tret && params == parameterList.parameters) - return this; - - // Similar to TypeFunction::syntaxCopy; - auto t = new TypeFunction(ParameterList(params, parameterList.varargs), tret, linkage); - t.mod = ((mod & MODFlags.wild) ? (mod & ~MODFlags.wild) | MODFlags.const_ : mod); - t.isnothrow = isnothrow; - t.isnogc = isnogc; - t.purity = purity; - t.isproperty = isproperty; - t.isref = isref; - t.isreturn = isreturn; - t.isreturnscope = isreturnscope; - t.isScopeQual = isScopeQual; - t.isreturninferred = isreturninferred; - t.isscopeinferred = isscopeinferred; - t.isInOutParam = false; - t.isInOutQual = false; - t.trust = trust; - t.fargs = fargs; - t.isctor = isctor; - return t.merge(); - } - extern(D) static const(char)* getMatchError(A...)(const(char)* format, A args) { if (global.gag && !global.params.v.showGaggedErrors) @@ -4316,7 +4046,7 @@ extern (C++) final class TypeStruct : Type MATCH m; if (!(ty == to.ty && sym == (cast(TypeStruct)to).sym) && sym.aliasthis && !(att & AliasThisRec.tracing)) { - if (auto ato = aliasthisOf()) + if (auto ato = aliasthisOf(this)) { att = cast(AliasThisRec)(att | AliasThisRec.tracing); m = ato.implicitConvTo(to); @@ -4353,7 +4083,7 @@ extern (C++) final class TypeStruct : Type if (t.hasWild() && sym.aliasthis && !(att & AliasThisRec.tracing)) { - if (auto ato = aliasthisOf()) + if (auto ato = aliasthisOf(this)) { att = cast(AliasThisRec)(att | AliasThisRec.tracing); wm = ato.deduceWild(t, isRef); @@ -4364,11 +4094,6 @@ extern (C++) final class TypeStruct : Type return wm; } - override inout(Type) toHeadMutable() inout - { - return this; - } - override void accept(Visitor v) { v.visit(this); @@ -4595,7 +4320,7 @@ extern (C++) final class TypeClass : Type MATCH m; if (sym.aliasthis && !(att & AliasThisRec.tracing)) { - if (auto ato = aliasthisOf()) + if (auto ato = aliasthisOf(this)) { att = cast(AliasThisRec)(att | AliasThisRec.tracing); m = ato.implicitConvTo(to); @@ -4644,7 +4369,7 @@ extern (C++) final class TypeClass : Type if (t.hasWild() && sym.aliasthis && !(att & AliasThisRec.tracing)) { - if (auto ato = aliasthisOf()) + if (auto ato = aliasthisOf(this)) { att = cast(AliasThisRec)(att | AliasThisRec.tracing); wm = ato.deduceWild(t, isRef); @@ -4655,11 +4380,6 @@ extern (C++) final class TypeClass : Type return wm; } - override inout(Type) toHeadMutable() inout - { - return this; - } - override bool isZeroInit(const ref Loc loc) { return true; @@ -5852,36 +5572,3 @@ TypeIdentifier getException() tid.addIdent(Id.Exception); return tid; } - -/************************************** - * Check and set 'att' if 't' is a recursive 'alias this' type - * - * The goal is to prevent endless loops when there is a cycle in the alias this chain. - * Since there is no multiple `alias this`, the chain either ends in a leaf, - * or it loops back on itself as some point. - * - * Example: S0 -> (S1 -> S2 -> S3 -> S1) - * - * `S0` is not a recursive alias this, so this returns `false`, and a rewrite to `S1` can be tried. - * `S1` is a recursive alias this type, but since `att` is initialized to `null`, - * this still returns `false`, but `att1` is set to `S1`. - * A rewrite to `S2` and `S3` can be tried, but when we want to try a rewrite to `S1` again, - * we notice `att == t`, so we're back at the start of the loop, and this returns `true`. - * - * Params: - * att = type reference used to detect recursion. Should be initialized to `null`. - * t = type of 'alias this' rewrite to attempt - * - * Returns: - * `false` if the rewrite is safe, `true` if it would loop back around - */ -bool isRecursiveAliasThis(ref Type att, Type t) -{ - //printf("+isRecursiveAliasThis(att = %s, t = %s)\n", att ? att.toChars() : "null", t.toChars()); - auto tb = t.toBasetype(); - if (att && tb.equivalent(att)) - return true; - else if (!att && tb.checkAliasThisRec()) - att = tb; - return false; -} diff --git a/gcc/d/dmd/mtype.h b/gcc/d/dmd/mtype.h index 57f4ec6..2f8bfa6 100644 --- a/gcc/d/dmd/mtype.h +++ b/gcc/d/dmd/mtype.h @@ -257,7 +257,6 @@ public: Type *arrayOf(); Type *sarrayOf(dinteger_t dim); bool hasDeprecatedAliasThis(); - Type *aliasthisOf(); virtual Type *makeConst(); virtual Type *makeImmutable(); virtual Type *makeShared(); @@ -271,11 +270,7 @@ public: virtual MATCH implicitConvTo(Type *to); virtual MATCH constConv(Type *to); virtual unsigned char deduceWild(Type *t, bool isRef); - virtual Type *substWildTo(unsigned mod); - Type *unqualify(unsigned m); - - virtual Type *toHeadMutable(); virtual ClassDeclaration *isClassHandle(); virtual structalign_t alignment(); virtual Expression *defaultInitLiteral(const Loc &loc); @@ -580,7 +575,6 @@ public: bool hasLazyParameters(); bool isDstyleVariadic() const; - Type *substWildTo(unsigned mod) override; MATCH constConv(Type *to) override; bool isnothrow() const; @@ -751,7 +745,6 @@ public: MATCH implicitConvTo(Type *to) override; MATCH constConv(Type *to) override; unsigned char deduceWild(Type *t, bool isRef) override; - Type *toHeadMutable() override; void accept(Visitor *v) override { v->visit(this); } }; @@ -804,7 +797,6 @@ public: MATCH implicitConvTo(Type *to) override; MATCH constConv(Type *to) override; unsigned char deduceWild(Type *t, bool isRef) override; - Type *toHeadMutable() override; bool isZeroInit(const Loc &loc) override; bool isscope() override; bool isBoolean() override; @@ -892,6 +884,8 @@ namespace dmd Type *pointerTo(Type *type); Type *referenceTo(Type *type); Type *merge2(Type *type); + Type *sarrayOf(Type *type, dinteger_t dim); + Type *arrayOf(Type *type); Type *constOf(Type *type); Type *immutableOf(Type *type); Type *mutableOf(Type *type); @@ -902,7 +896,11 @@ namespace dmd Type *wildConstOf(Type *type); Type *sharedWildOf(Type *type); Type *sharedWildConstOf(Type *type); + Type *unqualify(Type *type, unsigned m); + Type *toHeadMutable(Type *type); + Type *aliasthisOf(Type *type); Type *castMod(Type *type, MOD mod); Type *addMod(Type *type, MOD mod); Type *addStorageClass(Type *type, StorageClass stc); + Type *substWildTo(Type *type, unsigned mod); } diff --git a/gcc/d/dmd/optimize.d b/gcc/d/dmd/optimize.d index dd6b117..2c89a58 100644 --- a/gcc/d/dmd/optimize.d +++ b/gcc/d/dmd/optimize.d @@ -1349,7 +1349,7 @@ Expression optimize(Expression e, int result, bool keepLvalue = false) if (b++ == global.recursionLimit) { error(e.loc, "infinite loop while optimizing expression"); - fatal(); + return ErrorExp.get(); } auto ex = ret; diff --git a/gcc/d/dmd/safe.d b/gcc/d/dmd/safe.d index 8b57f7f..1e5fb47 100644 --- a/gcc/d/dmd/safe.d +++ b/gcc/d/dmd/safe.d @@ -26,7 +26,7 @@ import dmd.identifier; import dmd.mtype; import dmd.target; import dmd.tokens; -import dmd.typesem : hasPointers; +import dmd.typesem : hasPointers, arrayOf; import dmd.func : setUnsafe, setUnsafePreview; /************************************************************* diff --git a/gcc/d/dmd/typesem.d b/gcc/d/dmd/typesem.d index 61272ea..ad87ea0 100644 --- a/gcc/d/dmd/typesem.d +++ b/gcc/d/dmd/typesem.d @@ -1687,7 +1687,7 @@ Type typeSemantic(Type type, const ref Loc loc, Scope* sc) if (!ClassDeclaration.object) { .error(Loc.initial, "missing or corrupt object.d"); - fatal(); + return error(); } __gshared FuncDeclaration feq = null; @@ -6229,6 +6229,29 @@ Type referenceTo(Type type) return type.rto; } +// Make corresponding static array type without semantic +Type sarrayOf(Type type, dinteger_t dim) +{ + assert(type.deco); + Type t = new TypeSArray(type, new IntegerExp(Loc.initial, dim, Type.tsize_t)); + // according to TypeSArray.semantic() + t = t.addMod(type.mod); + t = t.merge(); + return t; +} + +Type arrayOf(Type type) +{ + if (type.ty == Terror) + return type; + if (!type.arrayof) + { + Type t = new TypeDArray(type); + type.arrayof = t.merge(); + } + return type.arrayof; +} + /******************************** * Convert to 'const'. */ @@ -6478,6 +6501,104 @@ Type sharedWildConstOf(Type type) return t; } +Type unqualify(Type type, uint m) +{ + Type t = type.mutableOf().unSharedOf(); + + Type tn = type.ty == Tenum ? null : type.nextOf(); + if (tn && tn.ty != Tfunction) + { + Type utn = tn.unqualify(m); + if (utn != tn) + { + if (type.ty == Tpointer) + t = utn.pointerTo(); + else if (type.ty == Tarray) + t = utn.arrayOf(); + else if (type.ty == Tsarray) + t = new TypeSArray(utn, (cast(TypeSArray)type).dim); + else if (type.ty == Taarray) + { + t = new TypeAArray(utn, (cast(TypeAArray)type).index); + } + else + assert(0); + + t = t.merge(); + } + } + t = t.addMod(type.mod & ~m); + return t; +} + +/************************** + * Return type with the top level of it being mutable. + * + * Params: + * t = type for which the top level mutable version is being returned + * + * Returns: + * type version with mutable top level + */ +Type toHeadMutable(const Type t) +{ + Type unqualType = cast(Type) t; + if (t.isTypeStruct() || t.isTypeClass()) + return unqualType; + + if (!t.mod) + return unqualType; + return unqualType.mutableOf(); +} + +Type aliasthisOf(Type type) +{ + auto ad = isAggregate(type); + if (!ad || !ad.aliasthis) + return null; + + auto s = ad.aliasthis.sym; + if (s.isAliasDeclaration()) + s = s.toAlias(); + + if (s.isTupleDeclaration()) + return null; + + if (auto vd = s.isVarDeclaration()) + { + auto t = vd.type; + if (vd.needThis()) + t = t.addMod(type.mod); + return t; + } + Dsymbol callable = s.isFuncDeclaration(); + callable = callable ? callable : s.isTemplateDeclaration(); + if (callable) + { + auto fd = resolveFuncCall(Loc.initial, null, callable, null, type, ArgumentList(), FuncResolveFlag.quiet); + if (!fd || fd.errors || !functionSemantic(fd)) + return Type.terror; + + auto t = fd.type.nextOf(); + if (!t) // https://issues.dlang.org/show_bug.cgi?id=14185 + return Type.terror; + t = t.substWildTo(type.mod == 0 ? MODFlags.mutable : type.mod); + return t; + } + if (auto d = s.isDeclaration()) + { + assert(d.type); + return d.type; + } + if (auto ed = s.isEnumDeclaration()) + { + return ed.type; + } + + //printf("%s\n", s.kind()); + return null; +} + /************************************ * Apply MODxxxx bits to existing type. */ @@ -6528,6 +6649,137 @@ Type castMod(Type type, MOD mod) return t; } +Type substWildTo(Type type, uint mod) +{ + auto tf = type.isTypeFunction(); + if (!tf) + { + //printf("+Type.substWildTo this = %s, mod = x%x\n", toChars(), mod); + Type t; + + if (Type tn = type.nextOf()) + { + // substitution has no effect on function pointer type. + if (type.ty == Tpointer && tn.ty == Tfunction) + { + t = type; + goto L1; + } + + t = tn.substWildTo(mod); + if (t == tn) + t = type; + else + { + if (type.ty == Tpointer) + t = t.pointerTo(); + else if (type.ty == Tarray) + t = t.arrayOf(); + else if (type.ty == Tsarray) + t = new TypeSArray(t, (cast(TypeSArray)type).dim.syntaxCopy()); + else if (type.ty == Taarray) + { + t = new TypeAArray(t, (cast(TypeAArray)type).index.syntaxCopy()); + } + else if (type.ty == Tdelegate) + { + t = new TypeDelegate(t.isTypeFunction()); + } + else + assert(0); + + t = t.merge(); + } + } + else + t = type; + + L1: + if (type.isWild()) + { + if (mod == MODFlags.immutable_) + { + t = t.immutableOf(); + } + else if (mod == MODFlags.wildconst) + { + t = t.wildConstOf(); + } + else if (mod == MODFlags.wild) + { + if (type.isWildConst()) + t = t.wildConstOf(); + else + t = t.wildOf(); + } + else if (mod == MODFlags.const_) + { + t = t.constOf(); + } + else + { + if (type.isWildConst()) + t = t.constOf(); + else + t = t.mutableOf(); + } + } + if (type.isConst()) + t = t.addMod(MODFlags.const_); + if (type.isShared()) + t = t.addMod(MODFlags.shared_); + + //printf("-Type.substWildTo t = %s\n", t.toChars()); + return t; + } + + if (!tf.iswild && !(tf.mod & MODFlags.wild)) + return tf; + + // Substitude inout qualifier of function type to mutable or immutable + // would break type system. Instead substitude inout to the most weak + // qualifer - const. + uint m = MODFlags.const_; + + assert(tf.next); + Type tret = tf.next.substWildTo(m); + Parameters* params = tf.parameterList.parameters; + if (tf.mod & MODFlags.wild) + params = tf.parameterList.parameters.copy(); + for (size_t i = 0; i < params.length; i++) + { + Parameter p = (*params)[i]; + Type t = p.type.substWildTo(m); + if (t == p.type) + continue; + if (params == tf.parameterList.parameters) + params = tf.parameterList.parameters.copy(); + (*params)[i] = new Parameter(p.loc, p.storageClass, t, null, null, null); + } + if (tf.next == tret && params == tf.parameterList.parameters) + return tf; + + // Similar to TypeFunction.syntaxCopy; + auto t = new TypeFunction(ParameterList(params, tf.parameterList.varargs), tret, tf.linkage); + t.mod = ((tf.mod & MODFlags.wild) ? (tf.mod & ~MODFlags.wild) | MODFlags.const_ : tf.mod); + t.isnothrow = tf.isnothrow; + t.isnogc = tf.isnogc; + t.purity = tf.purity; + t.isproperty = tf.isproperty; + t.isref = tf.isref; + t.isreturn = tf.isreturn; + t.isreturnscope = tf.isreturnscope; + t.isScopeQual = tf.isScopeQual; + t.isreturninferred = tf.isreturninferred; + t.isscopeinferred = tf.isscopeinferred; + t.isInOutParam = false; + t.isInOutQual = false; + t.trust = tf.trust; + t.fargs = tf.fargs; + t.isctor = tf.isctor; + return t.merge(); +} + /************************************ * Add MODxxxx bits to existing type. * We're adding, not replacing, so adding const to @@ -6633,6 +6885,69 @@ Type addMod(Type type, MOD mod) return t; } +/** + * Check whether this type has endless `alias this` recursion. + * + * Params: + * t = type to check whether it has a recursive alias this + * Returns: + * `true` if `t` has an `alias this` that can be implicitly + * converted back to `t` itself. + */ +private bool checkAliasThisRec(Type t) +{ + Type tb = t.toBasetype(); + AliasThisRec* pflag; + if (tb.ty == Tstruct) + pflag = &(cast(TypeStruct)tb).att; + else if (tb.ty == Tclass) + pflag = &(cast(TypeClass)tb).att; + else + return false; + + AliasThisRec flag = cast(AliasThisRec)(*pflag & AliasThisRec.typeMask); + if (flag == AliasThisRec.fwdref) + { + Type att = aliasthisOf(t); + flag = att && att.implicitConvTo(t) ? AliasThisRec.yes : AliasThisRec.no; + } + *pflag = cast(AliasThisRec)(flag | (*pflag & ~AliasThisRec.typeMask)); + return flag == AliasThisRec.yes; +} + +/************************************** + * Check and set 'att' if 't' is a recursive 'alias this' type + * + * The goal is to prevent endless loops when there is a cycle in the alias this chain. + * Since there is no multiple `alias this`, the chain either ends in a leaf, + * or it loops back on itself as some point. + * + * Example: S0 -> (S1 -> S2 -> S3 -> S1) + * + * `S0` is not a recursive alias this, so this returns `false`, and a rewrite to `S1` can be tried. + * `S1` is a recursive alias this type, but since `att` is initialized to `null`, + * this still returns `false`, but `att1` is set to `S1`. + * A rewrite to `S2` and `S3` can be tried, but when we want to try a rewrite to `S1` again, + * we notice `att == t`, so we're back at the start of the loop, and this returns `true`. + * + * Params: + * att = type reference used to detect recursion. Should be initialized to `null`. + * t = type of 'alias this' rewrite to attempt + * + * Returns: + * `false` if the rewrite is safe, `true` if it would loop back around + */ +bool isRecursiveAliasThis(ref Type att, Type t) +{ + //printf("+isRecursiveAliasThis(att = %s, t = %s)\n", att ? att.toChars() : "null", t.toChars()); + auto tb = t.toBasetype(); + if (att && tb.equivalent(att)) + return true; + else if (!att && tb.checkAliasThisRec()) + att = tb; + return false; +} + /******************************* Private *****************************************/ private: diff --git a/gcc/d/expr.cc b/gcc/d/expr.cc index 7fbabbe..d055e0b 100644 --- a/gcc/d/expr.cc +++ b/gcc/d/expr.cc @@ -464,7 +464,7 @@ public: else { /* Use _adEq2() to compare each element. */ - Type *t1array = t1elem->arrayOf (); + Type *t1array = dmd::arrayOf (t1elem); tree result = build_libcall (LIBCALL_ADEQ2, e->type, 3, d_array_convert (e->e1), d_array_convert (e->e2), @@ -2172,7 +2172,8 @@ public: { /* Generate a slice for non-zero initialized aggregates, otherwise create an empty array. */ - gcc_assert (e->type == dmd::constOf (Type::tvoid->arrayOf ())); + gcc_assert (e->type->isConst () + && e->type->nextOf ()->ty == TY::Tvoid); tree type = build_ctype (e->type); tree length = size_int (sd->dsym->structsize); @@ -2571,7 +2572,7 @@ public: /* Implicitly convert void[n] to ubyte[n]. */ if (tb->ty == TY::Tsarray && tb->nextOf ()->toBasetype ()->ty == TY::Tvoid) - tb = Type::tuns8->sarrayOf (tb->isTypeSArray ()->dim->toUInteger ()); + tb = dmd::sarrayOf (Type::tuns8, tb->isTypeSArray ()->dim->toUInteger ()); gcc_assert (tb->ty == TY::Tarray || tb->ty == TY::Tsarray || tb->ty == TY::Tpointer); @@ -2685,7 +2686,7 @@ public: /* Allocate space on the memory managed heap. */ tree mem = build_libcall (LIBCALL_ARRAYLITERALTX, dmd::pointerTo (etype), 2, - build_typeinfo (e, etype->arrayOf ()), + build_typeinfo (e, dmd::arrayOf (etype)), size_int (e->elements->length)); mem = d_save_expr (mem); @@ -2732,20 +2733,20 @@ public: /* Build an expression that assigns all expressions in KEYS to a constructor. */ - tree akeys = build_array_from_exprs (ta->index->sarrayOf (e->keys->length), - e->keys, this->constp_); + Type *tkarray = dmd::sarrayOf (ta->index, e->keys->length); + tree akeys = build_array_from_exprs (tkarray, e->keys, this->constp_); tree init = stabilize_expr (&akeys); /* Do the same with all expressions in VALUES. */ - tree avals = build_array_from_exprs (ta->next->sarrayOf (e->values->length), - e->values, this->constp_); + Type *tvarray = dmd::sarrayOf (ta->next, e->values->length); + tree avals = build_array_from_exprs (tvarray, e->values, this->constp_); init = compound_expr (init, stabilize_expr (&avals)); /* Generate: _d_assocarrayliteralTX (ti, keys, vals); */ - tree keys = d_array_value (build_ctype (ta->index->arrayOf ()), + tree keys = d_array_value (build_ctype (dmd::arrayOf (ta->index)), size_int (e->keys->length), build_address (akeys)); - tree vals = d_array_value (build_ctype (ta->next->arrayOf ()), + tree vals = d_array_value (build_ctype (dmd::arrayOf (ta->next)), size_int (e->values->length), build_address (avals)); diff --git a/gcc/d/intrinsics.cc b/gcc/d/intrinsics.cc index 8bbcdc1..c895c1a 100644 --- a/gcc/d/intrinsics.cc +++ b/gcc/d/intrinsics.cc @@ -274,7 +274,7 @@ build_shuffle_mask_type (tree type) gcc_assert (t != NULL); unsigned HOST_WIDE_INT nunits = TYPE_VECTOR_SUBPARTS (type).to_constant (); - return build_ctype (TypeVector::create (t->sarrayOf (nunits))); + return build_ctype (TypeVector::create (dmd::sarrayOf (t, nunits))); } /* Checks if call to intrinsic FUNCTION in CALLEXP matches the internal @@ -414,7 +414,7 @@ maybe_warn_intrinsic_mismatch (tree function, tree callexp) break; Type *inner = build_frontend_type (TREE_TYPE (vec0)); - Type *vector = TypeVector::create (inner->sarrayOf (nunits)); + Type *vector = TypeVector::create (dmd::sarrayOf (inner, nunits)); return warn_mismatched_argument (callexp, 1, build_ctype (vector), true); } @@ -479,7 +479,7 @@ maybe_warn_intrinsic_mismatch (tree function, tree callexp) break; Type *inner = build_frontend_type (TREE_TYPE (arg)); - Type *vector = TypeVector::create (inner->sarrayOf (nunits)); + Type *vector = TypeVector::create (dmd::sarrayOf (inner, nunits)); return warn_mismatched_argument (callexp, 0, build_ctype (vector), true); } diff --git a/gcc/d/runtime.cc b/gcc/d/runtime.cc index e5988c7..8a64c52 100644 --- a/gcc/d/runtime.cc +++ b/gcc/d/runtime.cc @@ -158,31 +158,31 @@ get_libcall_type (d_libcall_type type) break; case LCT_ARRAY_VOID: - libcall_types[type] = Type::tvoid->arrayOf (); + libcall_types[type] = dmd::arrayOf (Type::tvoid); break; case LCT_ARRAY_SIZE_T: - libcall_types[type] = Type::tsize_t->arrayOf (); + libcall_types[type] = dmd::arrayOf (Type::tsize_t); break; case LCT_ARRAY_BYTE: - libcall_types[type] = Type::tint8->arrayOf (); + libcall_types[type] = dmd::arrayOf (Type::tint8); break; case LCT_ARRAY_STRING: - libcall_types[type] = Type::tstring->arrayOf (); + libcall_types[type] = dmd::arrayOf (Type::tstring); break; case LCT_ARRAY_WSTRING: - libcall_types[type] = Type::twstring->arrayOf (); + libcall_types[type] = dmd::arrayOf (Type::twstring); break; case LCT_ARRAY_DSTRING: - libcall_types[type] = Type::tdstring->arrayOf (); + libcall_types[type] = dmd::arrayOf (Type::tdstring); break; case LCT_ARRAYARRAY_BYTE: - libcall_types[type] = Type::tint8->arrayOf ()->arrayOf (); + libcall_types[type] = dmd::arrayOf (Type::tint8); break; case LCT_POINTER_ASSOCARRAY: @@ -190,15 +190,15 @@ get_libcall_type (d_libcall_type type) break; case LCT_POINTER_VOIDPTR: - libcall_types[type] = Type::tvoidptr->arrayOf (); + libcall_types[type] = dmd::arrayOf (Type::tvoidptr); break; case LCT_ARRAYPTR_VOID: - libcall_types[type] = dmd::pointerTo (Type::tvoid->arrayOf ()); + libcall_types[type] = dmd::pointerTo (dmd::arrayOf (Type::tvoid)); break; case LCT_ARRAYPTR_BYTE: - libcall_types[type] = dmd::pointerTo (Type::tint8->arrayOf ()); + libcall_types[type] = dmd::pointerTo (dmd::arrayOf (Type::tint8)); break; case LCT_IMMUTABLE_CHARPTR: diff --git a/gcc/d/typeinfo.cc b/gcc/d/typeinfo.cc index 794737b..cadcbe8 100644 --- a/gcc/d/typeinfo.cc +++ b/gcc/d/typeinfo.cc @@ -415,7 +415,7 @@ class TypeInfoVisitor : public Visitor tree decl = this->internal_reference (value); TREE_READONLY (decl) = 1; - value = d_array_value (build_ctype (Type::tchar->arrayOf ()), + value = d_array_value (build_ctype (dmd::arrayOf (Type::tchar)), size_int (len), build_address (decl)); this->layout_field (value); } @@ -1137,7 +1137,7 @@ public: this->layout_base (Type::typeinfotypelist); /* TypeInfo[] elements; */ - Type *satype = Type::tvoidptr->sarrayOf (ti->arguments->length); + Type *satype = dmd::sarrayOf (Type::tvoidptr, ti->arguments->length); vec *elms = NULL; for (size_t i = 0; i < ti->arguments->length; i++) { diff --git a/gcc/testsuite/gdc.test/compilable/issue24399.d b/gcc/testsuite/gdc.test/compilable/issue24399.d new file mode 100644 index 0000000..ae3e744 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/issue24399.d @@ -0,0 +1,9 @@ +// REQUIRED_ARGS: -main +// LINK: +template rt_options() +{ + __gshared string[] rt_options = []; + string[] rt_options_tls = []; +} + +alias _ = rt_options!(); diff --git a/gcc/testsuite/gdc.test/compilable/issue24409.d b/gcc/testsuite/gdc.test/compilable/issue24409.d new file mode 100644 index 0000000..5d298df --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/issue24409.d @@ -0,0 +1,17 @@ +static struct S +{ + union + { + int i; + long l; + } +} + +int f() +{ + S* r = new S(); + r.i = 5; + return r.i; +} + +enum X = f(); diff --git a/gcc/testsuite/gdc.test/runnable/issue24401.d b/gcc/testsuite/gdc.test/runnable/issue24401.d new file mode 100644 index 0000000..109d543 --- /dev/null +++ b/gcc/testsuite/gdc.test/runnable/issue24401.d @@ -0,0 +1,6 @@ +// PERMUTE_ARGS: +// https://issues.dlang.org/show_bug.cgi?id=24401 +int main() +{ + return (() @trusted => 0)(); +} diff --git a/gcc/testsuite/gdc.test/runnable/test24371.d b/gcc/testsuite/gdc.test/runnable/test24371.d new file mode 100644 index 0000000..885f9b8 --- /dev/null +++ b/gcc/testsuite/gdc.test/runnable/test24371.d @@ -0,0 +1,15 @@ +// https://issues.dlang.org/show_bug.cgi?id=24371 + +void main() +{ + assert("b" ~ "c" == "bc"); + assert(["a"] ~ "b" == ["a", "b"]); + assert(["a"] ~ ("b" ~ "c") == ["a", "bc"]); + + auto strArr = ["a"]; + assert(strArr ~ ("b" ~ "c") == ["a", "bc"]); + auto str = "c"; + assert(["a"] ~ ("b" ~ str) == ["a", "bc"]); + + assert(strArr ~ ("b" ~ str) == ["a", "bc"]); +} diff --git a/gcc/testsuite/gdc.test/runnable_cxx/test7925.d b/gcc/testsuite/gdc.test/runnable_cxx/test7925.d index f05aac9..2d0b023 100644 --- a/gcc/testsuite/gdc.test/runnable_cxx/test7925.d +++ b/gcc/testsuite/gdc.test/runnable_cxx/test7925.d @@ -1,12 +1,5 @@ // EXTRA_CPP_SOURCES: cpp7925.cpp -/* -Exclude -O/-inline due to a codegen bug on OSX: -https://issues.dlang.org/show_bug.cgi?id=22556 - -PERMUTE_ARGS(osx): -release -g -*/ - import core.vararg; extern(C++) class C1 -- cgit v1.1 From 18af5a796a5bb06538ede5978728ccdf4ffeb387 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Mon, 4 Mar 2024 00:16:47 +0000 Subject: Daily bump. --- gcc/ChangeLog | 59 +++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/d/ChangeLog | 25 +++++++++++++++++++++ gcc/testsuite/ChangeLog | 9 ++++++++ 4 files changed, 94 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dd72057..321c6b0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,62 @@ +2024-03-03 Greg McGary + + PR rtl-optimization/113010 + * combine.cc (simplify_comparison): Simplify a SUBREG on + WORD_REGISTER_OPERATIONS targets only if it is a zero-extending + MEM load. + +2024-03-03 Georg-Johann Lay + + * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED. + Use bool in place of int for boolean logic (if possible). + Move declarations to definitions (if possible). + * config/avr/avr.md: Use C++ comments. Fix some indentation glitches. + * config/avr/avr-dimode.md: Same. + * config/avr/constraints.md: Same. + * config/avr/predicates.md: Same. + +2024-03-03 Uros Bizjak + + PR target/113720 + * config/alpha/alpha.md (umuldi3_highpart): Remove expander. + (*umuldi3_highpart_reg): Rename to umuldi3_highpart and + simplify insn RTX using UMUL_HIGHPART rtx_code. + (*umuldi3_highpart_const): Remove. + +2024-03-03 Georg-Johann Lay + + PR target/114100 + * config/avr/avr-protos.h (_reg_unused_after): Remove proto. + * config/avr/avr.cc (_reg_unused_after): Make static. And + add 3rd argument to skip the current insn. + (reg_unused_after): Adjust call of reg_unused_after. + (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output + unneeded frame pointer adjustments. + +2024-03-03 Georg-Johann Lay + + PR target/92729 + * config/avr/avr.md (define_attr "cc"): Remove. + * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument + from prototype. + * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and + its uses. Add insn argument. + (avr_out_plus_symbol): Remove pcc argument and its uses. + (avr_out_plus): Remove pcc argument and its uses. + Adjust calls of avr_out_plus_symbol and avr_out_plus_1. + (avr_out_round): Adjust call of avr_out_plus. + +2024-03-03 Georg-Johann Lay + + * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo + from r14-9273. + +2024-03-03 Oleg Endo + + PR target/101737 + * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input + is not an insn, but e.g. a code label. + 2024-03-02 Georg-Johann Lay * config/avr/avr.md (REG_0, ... REG_36): New define_constants. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 00dd9af..e000c3c 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240303 +20240304 diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog index 696fb584..595bb59 100644 --- a/gcc/d/ChangeLog +++ b/gcc/d/ChangeLog @@ -1,3 +1,28 @@ +2024-03-03 Iain Buclaw + + * dmd/MERGE: Merge upstream dmd f8bae04558. + * dmd/VERSION: Bump version to v2.108.0-beta.1. + * d-builtins.cc (build_frontend_type): Update for new front-end + interface. + * d-codegen.cc (build_assert_call): Likewise. + * d-convert.cc (d_array_convert): Likewise. + * decl.cc (get_vtable_decl): Likewise. + * expr.cc (ExprVisitor::visit (EqualExp *)): Likewise. + (ExprVisitor::visit (VarExp *)): Likewise. + (ExprVisitor::visit (ArrayLiteralExp *)): Likewise. + (ExprVisitor::visit (AssocArrayLiteralExp)): Likewise. + * intrinsics.cc (build_shuffle_mask_type): Likewise. + (maybe_warn_intrinsic_mismatch): Likewise. + * runtime.cc (get_libcall_type): Likewise. + * typeinfo.cc (TypeInfoVisitor::layout_string): Likewise. + (TypeInfoVisitor::visit(TypeInfoTupleDeclaration *)): Likewise. + +2024-03-03 Iain Buclaw + + PR d/114171 + * d-codegen.cc (lower_struct_comparison): Keep alignment of original + type in reinterpret cast for comparison. + 2024-02-25 Iain Buclaw * dmd/MERGE: Merge upstream dmd ceff48bf7d. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c1fc1c5..297ea5c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2024-03-03 Greg McGary + + * gcc.c-torture/execute/pr113010.c: New test. + +2024-03-03 Iain Buclaw + + PR d/114171 + * gdc.dg/torture/pr114171.d: New test. + 2024-03-01 Patrick Palka PR c++/104919 -- cgit v1.1 From d35b5b0e0a0727cfdaba5f859e44116c33648639 Mon Sep 17 00:00:00 2001 From: Roger Sayle Date: Mon, 4 Mar 2024 00:47:08 +0000 Subject: PR target/114187: Fix ?Fmode SUBREG simplification in simplify_subreg. This patch fixes PR target/114187 a typo/missed-optimization in simplify-rtx that's exposed by (my) changes to x86_64's parameter passing. The context is that construction of double word (TImode) values now uses the idiom: (ior:TI (ashift:TI (zero_extend:TI (reg:DI x)) (const_int 64 [0x40])) (zero_extend:TI (reg:DI y))) Extracting the DImode highpart and lowpart halves of this complex expression is supported by simplications in simplify_subreg. The problem is when the doubleword TImode value represents two DFmode fields, there isn't a direct simplification to extract the highpart or lowpart SUBREGs, but instead GCC uses two steps, extract the DImode {high,low} part and then cast the result back to a floating point mode, DFmode. The (buggy) code to do this is: /* If the outer mode is not integral, try taking a subreg with the equivalent integer outer mode and then bitcasting the result. Other simplifications rely on integer to integer subregs and we'd potentially miss out on optimizations otherwise. */ if (known_gt (GET_MODE_SIZE (innermode), GET_MODE_SIZE (outermode)) && SCALAR_INT_MODE_P (innermode) && !SCALAR_INT_MODE_P (outermode) && int_mode_for_size (GET_MODE_BITSIZE (outermode), 0).exists (&int_outermode)) { rtx tem = simplify_subreg (int_outermode, op, innermode, byte); if (tem) return simplify_gen_subreg (outermode, tem, int_outermode, byte); } The issue/mistake is that the second call, to simplify_subreg, shouldn't use "byte" as the final argument; the offset has already been handled by the first call, to simplify_subreg, and this second call is just a type conversion from an integer mode to floating point (from DImode to DFmode). Interestingly, this mistake was already spotted by Richard Sandiford when the optimization was originally contributed in January 2023. https://gcc.gnu.org/pipermail/gcc-patches/2023-January/610920.html >> Richard Sandiford writes: >> Also, the final line should pass 0 rather than byte. Unfortunately a miscommunication/misunderstanding in a later thread https://gcc.gnu.org/pipermail/gcc-patches/2023-February/612898.html resulted in this correction being undone. Using lowpart_subreg should avoid/reduce confusion in future. 2024-03-03 Roger Sayle gcc/ChangeLog PR target/114187 * simplify-rtx.cc (simplify_context::simplify_subreg): Call lowpart_subreg to perform type conversion, to avoid confusion over the offset to use in the call to simplify_reg_subreg. gcc/testsuite/ChangeLog PR target/114187 * g++.target/i386/pr114187.C: New test case. --- gcc/simplify-rtx.cc | 2 +- gcc/testsuite/g++.target/i386/pr114187.C | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.target/i386/pr114187.C (limited to 'gcc') diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index 36dd522..dceaa13 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -7846,7 +7846,7 @@ simplify_context::simplify_subreg (machine_mode outermode, rtx op, { rtx tem = simplify_subreg (int_outermode, op, innermode, byte); if (tem) - return simplify_gen_subreg (outermode, tem, int_outermode, byte); + return lowpart_subreg (outermode, tem, int_outermode); } /* If OP is a vector comparison and the subreg is not changing the diff --git a/gcc/testsuite/g++.target/i386/pr114187.C b/gcc/testsuite/g++.target/i386/pr114187.C new file mode 100644 index 0000000..69912a9 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr114187.C @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct P2d { + double x, y; +}; + +double sumxy_p(P2d p) { + return p.x + p.y; +} + +/* { dg-final { scan-assembler-not "movq" } } */ +/* { dg-final { scan-assembler-not "xchg" } } */ -- cgit v1.1 From ea1c16f95b8fbaba4a7f3663ff9933ebedfb92a5 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 4 Mar 2024 10:04:19 +0100 Subject: i386: Fix ICEs with SUBREGs from vector etc. constants to XFmode [PR114184] The Intel extended format has the various weird number categories, pseudo denormals, pseudo infinities, pseudo NaNs and unnormals. Those are not representable in the GCC real_value and so neither GIMPLE nor RTX VIEW_CONVERT_EXPR/SUBREG folding folds those into constants. As can be seen on the following testcase, because it isn't folded (since GCC 12, before that we were folding it) we can end up with a SUBREG of a CONST_VECTOR or similar constant, which isn't valid general_operand, so we ICE during vregs pass trying to recognize the move instruction. Initially I thought it is a middle-end bug, the movxf instruction has general_operand predicate, but the middle-end certainly never tests that predicate, seems moves are special optabs. And looking at other mov optabs, e.g. for vector modes the i386 patterns use nonimmediate_operand predicate on the input, yet ix86_expand_vector_move deals with CONSTANT_P and SUBREG of CONSTANT_P arguments which if the predicate was checked couldn't ever make it through. The following patch handles this case similarly to the ix86_expand_vector_move's SUBREG of CONSTANT_P case, does it just for XFmode because I believe that is the only mode that needs it from the scalar ones, others should just be folded. 2024-03-04 Jakub Jelinek PR target/114184 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or register. * gcc.target/i386/pr114184.c: New test. --- gcc/config/i386/i386-expand.cc | 14 ++++++++++++++ gcc/testsuite/gcc.target/i386/pr114184.c | 22 ++++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr114184.c (limited to 'gcc') diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index c98e0f8..3b1685a 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -451,6 +451,20 @@ ix86_expand_move (machine_mode mode, rtx operands[]) && GET_MODE (SUBREG_REG (op1)) == DImode && SUBREG_BYTE (op1) == 0) op1 = gen_rtx_ZERO_EXTEND (TImode, SUBREG_REG (op1)); + /* As not all values in XFmode are representable in real_value, + we might be called with unfoldable SUBREGs of constants. */ + if (mode == XFmode + && CONSTANT_P (SUBREG_REG (op1)) + && can_create_pseudo_p ()) + { + machine_mode imode = GET_MODE (SUBREG_REG (op1)); + rtx r = force_const_mem (imode, SUBREG_REG (op1)); + if (r) + r = validize_mem (r); + else + r = force_reg (imode, SUBREG_REG (op1)); + op1 = simplify_gen_subreg (mode, r, imode, SUBREG_BYTE (op1)); + } break; } diff --git a/gcc/testsuite/gcc.target/i386/pr114184.c b/gcc/testsuite/gcc.target/i386/pr114184.c new file mode 100644 index 0000000..360b3b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr114184.c @@ -0,0 +1,22 @@ +/* PR target/114184 */ +/* { dg-do compile } */ +/* { dg-options "-Og -mavx2" } */ + +typedef unsigned char V __attribute__((vector_size (32))); +typedef unsigned char W __attribute__((vector_size (16))); + +_Complex long double +foo (void) +{ + _Complex long double d; + *(V *)&d = (V) { 149, 136, 89, 42, 38, 240, 196, 194 }; + return d; +} + +long double +bar (void) +{ + long double d; + *(W *)&d = (W) { 149, 136, 89, 42, 38, 240, 196, 194 }; + return d; +} -- cgit v1.1 From 889fbc9454e2d4e2b9a11a9e02b3b7e698edcd1c Mon Sep 17 00:00:00 2001 From: Xi Ruoyao Date: Tue, 23 Jan 2024 19:58:21 +0800 Subject: testsuite: Make pr104992.c irrelated to target vector feature [PR113418] The vect_int_mod target selector is evaluated with the options in DEFAULT_VECTCFLAGS in effect, but these options are not automatically passed to tests out of the vect directories. So this test fails on targets where integer vector modulo operation is supported but requiring an option to enable, for example LoongArch. In this test case, the only expected optimization not happened in original is in corge because it needs forward propogation. So we can scan the forwprop2 dump (where the vector operation is not expanded to scalars yet) instead of optimized, then we don't need to consider vect_int_mod or not. gcc/testsuite/ChangeLog: PR testsuite/113418 * gcc.dg/pr104992.c (dg-options): Use -fdump-tree-forwprop2 instead of -fdump-tree-optimized. (dg-final): Scan forwprop2 dump instead of optimized, and remove the use of vect_int_mod. * lib/target-supports.exp (check_effective_target_vect_int_mod): Remove because it's not used anymore. --- gcc/testsuite/gcc.dg/pr104992.c | 5 ++--- gcc/testsuite/lib/target-supports.exp | 13 ------------- 2 files changed, 2 insertions(+), 16 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/pr104992.c b/gcc/testsuite/gcc.dg/pr104992.c index 82f8c75..6fd513d 100644 --- a/gcc/testsuite/gcc.dg/pr104992.c +++ b/gcc/testsuite/gcc.dg/pr104992.c @@ -1,6 +1,6 @@ /* PR tree-optimization/104992 */ /* { dg-do compile } */ -/* { dg-options "-O2 -Wno-psabi -fdump-tree-optimized" } */ +/* { dg-options "-O2 -Wno-psabi -fdump-tree-forwprop2" } */ #define vector __attribute__((vector_size(4*sizeof(int)))) @@ -54,5 +54,4 @@ __attribute__((noipa)) unsigned waldo (unsigned x, unsigned y, unsigned z) { return x / y * z == x; } -/* { dg-final { scan-tree-dump-times " % " 9 "optimized" { target { ! vect_int_mod } } } } */ -/* { dg-final { scan-tree-dump-times " % " 6 "optimized" { target vect_int_mod } } } */ +/* { dg-final { scan-tree-dump-times " % " 6 "forwprop2" } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 4138cc9..ae33c4f 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -9064,19 +9064,6 @@ proc check_effective_target_vect_long_mult { } { return $answer } -# Return 1 if the target supports vector int modulus, 0 otherwise. - -proc check_effective_target_vect_int_mod { } { - return [check_cached_effective_target_indexed vect_int_mod { - expr { ([istarget powerpc*-*-*] - && [check_effective_target_has_arch_pwr10]) - || [istarget amdgcn-*-*] - || ([istarget loongarch*-*-*] - && [check_effective_target_loongarch_sx]) - || ([istarget riscv*-*-*] - && [check_effective_target_riscv_v]) }}] -} - # Return 1 if the target supports vector even/odd elements extraction, 0 otherwise. proc check_effective_target_vect_extract_even_odd { } { -- cgit v1.1 From c27148f2f40654a638bcf429633be1c0561529d5 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 4 Mar 2024 11:15:07 +0100 Subject: bitint: Fix tree node sharing bug [PR114209] We ICE on the following testcase due to invalid tree sharing. The second hunk fixes that, the first one is from me looking around at other spots which might need end up with invalid tree sharing too. 2024-03-04 Jakub Jelinek PR middle-end/114209 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call unshare_expr when creating a MEM_REF from MEM_REF. (bitint_large_huge::lower_stmt): Call unshare_expr. * gcc.dg/bitint-97.c: New test. --- gcc/gimple-lower-bitint.cc | 4 ++-- gcc/testsuite/gcc.dg/bitint-97.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/bitint-97.c (limited to 'gcc') diff --git a/gcc/gimple-lower-bitint.cc b/gcc/gimple-lower-bitint.cc index 15a2712..e3c8518 100644 --- a/gcc/gimple-lower-bitint.cc +++ b/gcc/gimple-lower-bitint.cc @@ -620,7 +620,7 @@ bitint_large_huge::limb_access (tree type, tree var, tree idx, bool write_p) else if (TREE_CODE (var) == MEM_REF && tree_fits_uhwi_p (idx)) { ret - = build2 (MEM_REF, ltype, TREE_OPERAND (var, 0), + = build2 (MEM_REF, ltype, unshare_expr (TREE_OPERAND (var, 0)), size_binop (PLUS_EXPR, TREE_OPERAND (var, 1), build_int_cst (TREE_TYPE (TREE_OPERAND (var, 1)), tree_to_uhwi (idx) @@ -5342,7 +5342,7 @@ bitint_large_huge::lower_stmt (gimple *stmt) = build_qualified_type (ltype, TYPE_QUALS (ltype) | ENCODE_QUAL_ADDR_SPACE (as)); - rhs1 = build1 (VIEW_CONVERT_EXPR, ltype, mem); + rhs1 = build1 (VIEW_CONVERT_EXPR, ltype, unshare_expr (mem)); gimple_assign_set_rhs1 (stmt, rhs1); } else diff --git a/gcc/testsuite/gcc.dg/bitint-97.c b/gcc/testsuite/gcc.dg/bitint-97.c new file mode 100644 index 0000000..a859978 --- /dev/null +++ b/gcc/testsuite/gcc.dg/bitint-97.c @@ -0,0 +1,18 @@ +/* PR middle-end/114209 */ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-Og -std=c23 -fno-strict-aliasing" } */ +/* { dg-add-options float128 } */ +/* { dg-require-effective-target float128 } */ + +typedef signed char V __attribute__((__vector_size__(16))); +typedef _Float128 W __attribute__((__vector_size__(16))); + +_Float128 +foo (void *p) +{ + signed char c = *(_BitInt(128) *) p; + _Float128 f = *(_Float128 *) p; + W w = *(W *) p; + signed char r = ((union { W a; signed char b[16]; }) w).b[1]; + return r + f; +} -- cgit v1.1 From 324d2907c86f05e40dc52d226940308f53a956c2 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 4 Mar 2024 09:46:13 +0100 Subject: tree-optimization/114192 - scalar reduction kept live with early break vect The following fixes a missing replacement of the reduction value used in the epilog, causing the scalar reduction to be kept live across the early break exit path. PR tree-optimization/114192 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the appropriate def for the live out stmt in case of an alternate exit. --- gcc/tree-vect-loop.cc | 40 ++++++++++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 14 deletions(-) (limited to 'gcc') diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc index 35f1f8c..761cdc6 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -6066,20 +6066,32 @@ vect_create_epilog_for_reduction (loop_vec_info loop_vinfo, stmt_vec_info single_live_out_stmt[] = { stmt_info }; array_slice live_out_stmts = single_live_out_stmt; - if (slp_reduc) - /* All statements produce live-out values. */ - live_out_stmts = SLP_TREE_SCALAR_STMTS (slp_node); - else if (slp_node) - { - /* The last statement in the reduction chain produces the live-out - value. Note SLP optimization can shuffle scalar stmts to - optimize permutations so we have to search for the last stmt. */ - for (k = 0; k < group_size; ++k) - if (!REDUC_GROUP_NEXT_ELEMENT (SLP_TREE_SCALAR_STMTS (slp_node)[k])) - { - single_live_out_stmt[0] = SLP_TREE_SCALAR_STMTS (slp_node)[k]; - break; - } + if (LOOP_VINFO_EARLY_BREAKS (loop_vinfo) + && loop_exit != LOOP_VINFO_IV_EXIT (loop_vinfo) + /* ??? We should fend this off earlier. For conversions we create + multiple epilogues, one dead. */ + && stmt_info == reduc_info->reduc_def) + { + gcc_assert (!slp_node); + single_live_out_stmt[0] = reduc_info; + } + else + { + if (slp_reduc) + /* All statements produce live-out values. */ + live_out_stmts = SLP_TREE_SCALAR_STMTS (slp_node); + else if (slp_node) + { + /* The last statement in the reduction chain produces the live-out + value. Note SLP optimization can shuffle scalar stmts to + optimize permutations so we have to search for the last stmt. */ + for (k = 0; k < group_size; ++k) + if (!REDUC_GROUP_NEXT_ELEMENT (SLP_TREE_SCALAR_STMTS (slp_node)[k])) + { + single_live_out_stmt[0] = SLP_TREE_SCALAR_STMTS (slp_node)[k]; + break; + } + } } unsigned vec_num; -- cgit v1.1 From cde50296a19b109909089b91d532d2c8455f5f10 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 4 Mar 2024 10:38:31 +0100 Subject: tree-optimization/114203 - wrong CLZ niter computation For precision less than int we apply the adjustment to make it defined at zero after the adjustment to make it compute CLZ rather than CTZ. That's wrong. PR tree-optimization/114203 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ adjustment before making the result defined at zero. * gcc.dg/torture/pr114203.c: New testcase. --- gcc/testsuite/gcc.dg/torture/pr114203.c | 21 +++++++++++++++++++++ gcc/tree-ssa-loop-niter.cc | 7 +++---- 2 files changed, 24 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/torture/pr114203.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/torture/pr114203.c b/gcc/testsuite/gcc.dg/torture/pr114203.c new file mode 100644 index 0000000..0ef6279 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr114203.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ + +int __attribute__((noipa)) +foo (unsigned char b) +{ + int c = 0; + + while (b) { + b >>= 1; + c++; + } + + return c; +} + +int main() +{ + if (foo(0) != 0) + __builtin_abort (); + return 0; +} diff --git a/gcc/tree-ssa-loop-niter.cc b/gcc/tree-ssa-loop-niter.cc index 038e433..c6d010f 100644 --- a/gcc/tree-ssa-loop-niter.cc +++ b/gcc/tree-ssa-loop-niter.cc @@ -2288,6 +2288,9 @@ build_cltz_expr (tree src, bool leading, bool define_at_zero) src = fold_convert (unsigned_type_node, src); call = build_call_expr (fn, 1, src); + if (leading && prec < i_prec) + call = fold_build2 (MINUS_EXPR, integer_type_node, call, + build_int_cst (integer_type_node, i_prec - prec)); if (define_at_zero) { tree is_zero = fold_build2 (NE_EXPR, boolean_type_node, src, @@ -2295,10 +2298,6 @@ build_cltz_expr (tree src, bool leading, bool define_at_zero) call = fold_build3 (COND_EXPR, integer_type_node, is_zero, call, build_int_cst (integer_type_node, prec)); } - - if (leading && prec < i_prec) - call = fold_build2 (MINUS_EXPR, integer_type_node, call, - build_int_cst (integer_type_node, i_prec - prec)); } return call; -- cgit v1.1 From a19ab1c42aba47fbfb122a6160f504565aef0943 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Fri, 1 Mar 2024 11:07:21 +0100 Subject: tree-optimization/114164 - unsupported SIMD clone call, unsupported VEC_COND The following avoids creating unsupported VEC_COND_EXPRs as part of SIMD clone call mask argument setup during vectorization which results in inefficient decomposing of the operation during vector lowering. PR tree-optimization/114164 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if the code generated for mask argument setup is not supported. --- gcc/tree-vect-stmts.cc | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'gcc') diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc index be0e1a9..14a3ffb 100644 --- a/gcc/tree-vect-stmts.cc +++ b/gcc/tree-vect-stmts.cc @@ -4210,6 +4210,16 @@ vectorizable_simd_clone_call (vec_info *vinfo, stmt_vec_info stmt_info, " supported for mismatched vector sizes.\n"); return false; } + if (!expand_vec_cond_expr_p (clone_arg_vectype, + arginfo[i].vectype, ERROR_MARK)) + { + if (dump_enabled_p ()) + dump_printf_loc (MSG_MISSED_OPTIMIZATION, + vect_location, + "cannot compute mask argument for" + " in-branch vector clones.\n"); + return false; + } } else if (SCALAR_INT_MODE_P (bestn->simdclone->mask_mode)) { -- cgit v1.1 From 8fdac08b4d5f65973164a476bd255533ed97a766 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Mon, 4 Mar 2024 13:28:34 +0100 Subject: tree-optimization/114197 - unexpected if-conversion for vectorization The following avoids lowering a volatile bitfiled access and in case the if-converted and original loops end up in different outer loops because of simplifcations enabled scrap the result since that is not how the vectorizer expects the loops to be laid out. PR tree-optimization/114197 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if there are volatile bitfield accesses. (pass_if_conversion::execute): Throw away result if the if-converted and original loops are not nested as expected. * gcc.dg/torture/pr114197.c: New testcase. --- gcc/testsuite/gcc.dg/torture/pr114197.c | 15 +++++++++++++++ gcc/tree-if-conv.cc | 23 +++++++++++++++++++---- 2 files changed, 34 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/torture/pr114197.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/torture/pr114197.c b/gcc/testsuite/gcc.dg/torture/pr114197.c new file mode 100644 index 0000000..fb7e2fb --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr114197.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ + +#pragma pack(push) +struct a { + volatile signed b : 8; +}; +#pragma pack(pop) +int c; +static struct a d = {5}; +void e() { +f: + for (c = 8; c < 55; ++c) + if (!d.b) + goto f; +} diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc index db0d0f4..09d99fb 100644 --- a/gcc/tree-if-conv.cc +++ b/gcc/tree-if-conv.cc @@ -3701,6 +3701,14 @@ bitfields_to_lower_p (class loop *loop, if (dump_file && (dump_flags & TDF_DETAILS)) print_gimple_stmt (dump_file, stmt, 0, TDF_SLIM); + if (TREE_THIS_VOLATILE (op)) + { + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\t Bitfield NO OK to lower," + " the access is volatile.\n"); + return false; + } + if (!INTEGRAL_TYPE_P (TREE_TYPE (op))) { if (dump_file && (dump_flags & TDF_DETAILS)) @@ -4031,20 +4039,27 @@ pass_if_conversion::execute (function *fun) if (todo & TODO_update_ssa_any) update_ssa (todo & TODO_update_ssa_any); - /* If if-conversion elided the loop fall back to the original one. */ + /* If if-conversion elided the loop fall back to the original one. Likewise + if the loops are not nested in the same outer loop. */ for (unsigned i = 0; i < preds.length (); ++i) { gimple *g = preds[i]; if (!gimple_bb (g)) continue; - unsigned ifcvt_loop = tree_to_uhwi (gimple_call_arg (g, 0)); - unsigned orig_loop = tree_to_uhwi (gimple_call_arg (g, 1)); - if (!get_loop (fun, ifcvt_loop) || !get_loop (fun, orig_loop)) + auto ifcvt_loop = get_loop (fun, tree_to_uhwi (gimple_call_arg (g, 0))); + auto orig_loop = get_loop (fun, tree_to_uhwi (gimple_call_arg (g, 1))); + if (!ifcvt_loop || !orig_loop) { if (dump_file) fprintf (dump_file, "If-converted loop vanished\n"); fold_loop_internal_call (g, boolean_false_node); } + else if (loop_outer (ifcvt_loop) != loop_outer (orig_loop)) + { + if (dump_file) + fprintf (dump_file, "If-converted loop in different outer loop\n"); + fold_loop_internal_call (g, boolean_false_node); + } } return 0; -- cgit v1.1 From bd6e613c115c758f961999770acedc92d44d6950 Mon Sep 17 00:00:00 2001 From: Jan Dubiec Date: Mon, 4 Mar 2024 06:59:07 -0700 Subject: Fix 201001011-1.c on H8 Excerpt from gcc.sum: [...] PASS: gcc.c-torture/execute/20101011-1.c -O0 (test for excess errors) FAIL: gcc.c-torture/execute/20101011-1.c -O0 execution test PASS: gcc.c-torture/execute/20101011-1.c -O1 (test for excess errors) FAIL: gcc.c-torture/execute/20101011-1.c -O1 execution test [ ... ] This is because H8 MCUs do not throw a "divide by zero" exception. gcc/testsuite * gcc.c-torture/execute/20101011-1.c: Do not test on H8 series. --- gcc/testsuite/gcc.c-torture/execute/20101011-1.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c index d2c0f9a..9fa1030 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c @@ -26,6 +26,9 @@ #elif defined (__RX__) /* On RX division by zero does not trap. */ # define DO_TEST 0 +#elif defined (__H8300H__) || defined (__H8300S__) || defined (__H8300SX__) + /* On H8/300H, H8S and H8SX division by zero does not trap. */ +# define DO_TEST 0 #elif defined (__aarch64__) /* On AArch64 integer division by zero does not trap. */ # define DO_TEST 0 -- cgit v1.1 From 71244316cf714725930c2de61c79d635238595bf Mon Sep 17 00:00:00 2001 From: Mark Wielaard Date: Sun, 3 Mar 2024 20:50:32 +0100 Subject: Regenerate opt.urls There were several commits that didn't regenerate the opt.urls files. Fixes: 438ef143679e ("rs6000: Neuter option -mpower{8,9}-vector") Fixes: 50c549ef3db6 ("gccrs: enable -Winfinite-recursion warnings by default") Fixes: 25bb8a40abd9 ("Move docs for -Wuse-after-free and -Wuseless-cast") Fixes: 48448055fb70 ("AVR: Support .rodata in Flash for AVR64* and AVR128*") Fixes: 42503cc257fb ("AVR: Document option -mskip-bug") Fixes: 7de5bb642c12 ("i386: [APX] Document inline asm behavior and new switch") Fixes: 49a14ee488b8 ("Add -mevex512 into invoke.texi") Fixes: 4666cbde5e6d ("Sort warning options in c-family/c.opt.") Fixes: cda383616183 ("AVR: target/114100 - Better indirect accesses for reduced Tiny") gcc/c-family/ChangeLog: * c.opt.urls: Regenerate. gcc/ChangeLog: * common.opt.urls: Regenerate. * config/avr/avr.opt.urls: Likewise. * config/i386/i386.opt.urls: Likewise. * config/pru/pru.opt.urls: Likewise. * config/riscv/riscv.opt.urls: Likewise. * config/rs6000/rs6000.opt.urls: Likewise. gcc/rust/ChangeLog: * lang.opt.urls: Regenerate. --- gcc/c-family/c.opt.urls | 351 +++++++++++++++++++------------------- gcc/common.opt.urls | 4 +- gcc/config/avr/avr.opt.urls | 15 ++ gcc/config/i386/i386.opt.urls | 8 +- gcc/config/pru/pru.opt.urls | 2 +- gcc/config/riscv/riscv.opt.urls | 2 +- gcc/config/rs6000/rs6000.opt.urls | 3 - gcc/rust/lang.opt.urls | 3 + 8 files changed, 206 insertions(+), 182 deletions(-) (limited to 'gcc') diff --git a/gcc/c-family/c.opt.urls b/gcc/c-family/c.opt.urls index 5365c8e..9f97dc6 100644 --- a/gcc/c-family/c.opt.urls +++ b/gcc/c-family/c.opt.urls @@ -88,6 +88,9 @@ UrlSuffix(gcc/Warning-Options.html#index-Wabsolute-value) Waddress UrlSuffix(gcc/Warning-Options.html#index-Waddress) +Waddress-of-packed-member +UrlSuffix(gcc/Warning-Options.html#index-Waddress-of-packed-member) + Waligned-new UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Waligned-new) @@ -115,6 +118,9 @@ UrlSuffix(gcc/Warning-Options.html#index-Walloc-zero) Walloca-larger-than= UrlSuffix(gcc/Warning-Options.html#index-Walloca-larger-than_003d) LangUrlSuffix_D(gdc/Warnings.html#index-Walloca-larger-than) +Warith-conversion +UrlSuffix(gcc/Warning-Options.html#index-Warith-conversion) + Warray-bounds= UrlSuffix(gcc/Warning-Options.html#index-Warray-bounds) @@ -122,13 +128,10 @@ Warray-compare UrlSuffix(gcc/Warning-Options.html#index-Warray-compare) Warray-parameter -UrlSuffix(gcc/Warning-Options.html#index-Wno-array-parameter) +UrlSuffix(gcc/Warning-Options.html#index-Warray-parameter) Warray-parameter= -UrlSuffix(gcc/Warning-Options.html#index-Wno-array-parameter) - -Wzero-length-bounds -UrlSuffix(gcc/Warning-Options.html#index-Wzero-length-bounds) +UrlSuffix(gcc/Warning-Options.html#index-Warray-parameter) Wassign-intercept UrlSuffix(gcc/Objective-C-and-Objective-C_002b_002b-Dialect-Options.html#index-Wassign-intercept) @@ -148,9 +151,6 @@ UrlSuffix(gcc/Warning-Options.html#index-Wbool-compare) Wbool-operation UrlSuffix(gcc/Warning-Options.html#index-Wbool-operation) -Wframe-address -UrlSuffix(gcc/Warning-Options.html#index-Wframe-address) - Wbuiltin-declaration-mismatch UrlSuffix(gcc/Warning-Options.html#index-Wbuiltin-declaration-mismatch) LangUrlSuffix_D(gdc/Warnings.html#index-Wbuiltin-declaration-mismatch) @@ -217,6 +217,12 @@ UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wcatch-value) Wchar-subscripts UrlSuffix(gcc/Warning-Options.html#index-Wchar-subscripts) +Wclass-conversion +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wclass-conversion) + +Wclass-memaccess +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wclass-memaccess) + Wclobbered UrlSuffix(gcc/Warning-Options.html#index-Wclobbered) @@ -298,6 +304,12 @@ UrlSuffix(gcc/Warning-Options.html#index-Wdiscarded-qualifiers) Wdiv-by-zero UrlSuffix(gcc/Warning-Options.html#index-Wdiv-by-zero) +Wdouble-promotion +UrlSuffix(gcc/Warning-Options.html#index-Wdouble-promotion) + +Wduplicate-decl-specifier +UrlSuffix(gcc/Warning-Options.html#index-Wduplicate-decl-specifier) + Wduplicated-branches UrlSuffix(gcc/Warning-Options.html#index-Wduplicated-branches) @@ -307,6 +319,9 @@ UrlSuffix(gcc/Warning-Options.html#index-Wduplicated-cond) Weffc++ UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Weffc_002b_002b) +Welaborated-enum-base +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Welaborated-enum-base) + Wempty-body UrlSuffix(gcc/Warning-Options.html#index-Wempty-body) @@ -328,12 +343,18 @@ UrlSuffix(gcc/Warning-Options.html#index-Werror) LangUrlSuffix_D(gdc/Warnings.ht Wexceptions UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wexceptions) +Wexpansion-to-defined +UrlSuffix(gcc/Warning-Options.html#index-Wexpansion-to-defined) + Wextra UrlSuffix(gcc/Warning-Options.html#index-Wextra) LangUrlSuffix_D(gdc/Warnings.html#index-Wextra) Wextra-semi UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wextra-semi) +Wflex-array-member-not-at-end +UrlSuffix(gcc/Warning-Options.html#index-Wflex-array-member-not-at-end) + Wfloat-conversion UrlSuffix(gcc/Warning-Options.html#index-Wfloat-conversion) @@ -355,6 +376,9 @@ UrlSuffix(gcc/Warning-Options.html#index-Wformat-nonliteral) Wformat-overflow UrlSuffix(gcc/Warning-Options.html#index-Wformat-overflow) +Wformat-overflow= +UrlSuffix(gcc/Warning-Options.html#index-Wformat-overflow) + Wformat-security UrlSuffix(gcc/Warning-Options.html#index-Wformat-security) @@ -364,6 +388,9 @@ UrlSuffix(gcc/Warning-Options.html#index-Wformat-signedness) Wformat-truncation UrlSuffix(gcc/Warning-Options.html#index-Wformat-truncation) +Wformat-truncation= +UrlSuffix(gcc/Warning-Options.html#index-Wformat-truncation) + Wformat-y2k UrlSuffix(gcc/Warning-Options.html#index-Wformat-y2k) @@ -373,14 +400,8 @@ UrlSuffix(gcc/Warning-Options.html#index-Wformat-zero-length) Wformat= UrlSuffix(gcc/Warning-Options.html#index-Wformat) -Wformat-overflow= -UrlSuffix(gcc/Warning-Options.html#index-Wformat-overflow) - -Wformat-truncation= -UrlSuffix(gcc/Warning-Options.html#index-Wformat-truncation) - -Wflex-array-member-not-at-end -UrlSuffix(gcc/Warning-Options.html#index-Wflex-array-member-not-at-end) +Wframe-address +UrlSuffix(gcc/Warning-Options.html#index-Wframe-address) Wif-not-aligned UrlSuffix(gcc/Warning-Options.html#index-Wif-not-aligned) @@ -391,6 +412,18 @@ UrlSuffix(gcc/Warning-Options.html#index-Wignored-qualifiers) Wignored-attributes UrlSuffix(gcc/Warning-Options.html#index-Wignored-attributes) +Wimplicit +UrlSuffix(gcc/Warning-Options.html#index-Wimplicit) + +Wimplicit-fallthrough= +UrlSuffix(gcc/Warning-Options.html#index-Wimplicit-fallthrough) + +Wimplicit-function-declaration +UrlSuffix(gcc/Warning-Options.html#index-Wimplicit-function-declaration) + +Wimplicit-int +UrlSuffix(gcc/Warning-Options.html#index-Wimplicit-int) + Winaccessible-base UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Winaccessible-base) @@ -400,9 +433,6 @@ UrlSuffix(gcc/Warning-Options.html#index-Wincompatible-pointer-types) Winfinite-recursion UrlSuffix(gcc/Warning-Options.html#index-Winfinite-recursion) -Waddress-of-packed-member -UrlSuffix(gcc/Warning-Options.html#index-Waddress-of-packed-member) - Winit-self UrlSuffix(gcc/Warning-Options.html#index-Winit-self) @@ -412,24 +442,6 @@ UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Winit-list-lifetime) Winterference-size UrlSuffix(gcc/Warning-Options.html#index-Winterference-size) -Wimplicit -UrlSuffix(gcc/Warning-Options.html#index-Wimplicit) - -Wimplicit-fallthrough= -UrlSuffix(gcc/Warning-Options.html#index-Wimplicit-fallthrough) - -Wdouble-promotion -UrlSuffix(gcc/Warning-Options.html#index-Wdouble-promotion) - -Wexpansion-to-defined -UrlSuffix(gcc/Warning-Options.html#index-Wexpansion-to-defined) - -Wimplicit-function-declaration -UrlSuffix(gcc/Warning-Options.html#index-Wimplicit-function-declaration) - -Wimplicit-int -UrlSuffix(gcc/Warning-Options.html#index-Wimplicit-int) - Winherited-variadic-ctor UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Winherited-variadic-ctor) @@ -460,12 +472,12 @@ UrlSuffix(gcc/Warning-Options.html#index-Wjump-misses-init) Wliteral-suffix UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wliteral-suffix) -Wlogical-op -UrlSuffix(gcc/Warning-Options.html#index-Wlogical-op) - Wlogical-not-parentheses UrlSuffix(gcc/Warning-Options.html#index-Wlogical-not-parentheses) +Wlogical-op +UrlSuffix(gcc/Warning-Options.html#index-Wlogical-op) + Wlong-long UrlSuffix(gcc/Warning-Options.html#index-Wlong-long) @@ -475,12 +487,15 @@ UrlSuffix(gcc/Warning-Options.html#index-Wmain) Wmain UrlSuffix(gcc/Warning-Options.html#index-Wmain) -Wmemset-transposed-args -UrlSuffix(gcc/Warning-Options.html#index-Wmemset-transposed-args) +Wmaybe-uninitialized +UrlSuffix(gcc/Warning-Options.html#index-Wmaybe-uninitialized) Wmemset-elt-size UrlSuffix(gcc/Warning-Options.html#index-Wmemset-elt-size) +Wmemset-transposed-args +UrlSuffix(gcc/Warning-Options.html#index-Wmemset-transposed-args) + Wmisleading-indentation UrlSuffix(gcc/Warning-Options.html#index-Wmisleading-indentation) @@ -493,6 +508,9 @@ UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wmismatched-new-delete) Wmismatched-tags UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wmismatched-tags) +Wmissing-attributes +UrlSuffix(gcc/Warning-Options.html#index-Wmissing-attributes) + Wmissing-braces UrlSuffix(gcc/Warning-Options.html#index-Wmissing-braces) @@ -502,93 +520,6 @@ UrlSuffix(gcc/Warning-Options.html#index-Wmissing-declarations) Wmissing-field-initializers UrlSuffix(gcc/Warning-Options.html#index-Wmissing-field-initializers) -Wmissing-requires -UrlSuffix(gcc/Warning-Options.html#index-Wmissing-requires) - -Wmissing-template-keyword -UrlSuffix(gcc/Warning-Options.html#index-Wmissing-template-keyword) - -Wmultistatement-macros -UrlSuffix(gcc/Warning-Options.html#index-Wmultistatement-macros) - -Wmultiple-inheritance -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wmultiple-inheritance) - -Wnamespaces -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wnamespaces) - -Wnrvo -UrlSuffix(gcc/Warning-Options.html#index-Wno-nrvo) - -Wpacked-not-aligned -UrlSuffix(gcc/Warning-Options.html#index-Wno-packed-not-aligned) - -Wrange-loop-construct -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-range-loop-construct) - -Wredundant-tags -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-redundant-tags) - -Wsized-deallocation -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-sized-deallocation) - -Wsizeof-pointer-div -UrlSuffix(gcc/Warning-Options.html#index-Wno-sizeof-pointer-div) - -Wsizeof-array-div -UrlSuffix(gcc/Warning-Options.html#index-Wno-sizeof-array-div) - -Wsizeof-pointer-memaccess -UrlSuffix(gcc/Warning-Options.html#index-Wno-sizeof-pointer-memaccess) - -Wsizeof-array-argument -UrlSuffix(gcc/Warning-Options.html#index-Wno-sizeof-array-argument) - -Wstring-compare -UrlSuffix(gcc/Warning-Options.html#index-Wno-string-compare) - -Wstringop-overflow -UrlSuffix(gcc/Warning-Options.html#index-Wno-stringop-overflow) - -Wstringop-overflow= -UrlSuffix(gcc/Warning-Options.html#index-Wno-stringop-overflow) - -Wstringop-overread -UrlSuffix(gcc/Warning-Options.html#index-Wno-stringop-overread) - -Wstringop-truncation -UrlSuffix(gcc/Warning-Options.html#index-Wno-stringop-truncation) - -Wstrict-flex-arrays -UrlSuffix(gcc/Warning-Options.html#index-Wno-strict-flex-arrays) - -Wsuggest-attribute=format -UrlSuffix(gcc/Warning-Options.html#index-Wno-suggest-attribute_003dformat) - -Wsuggest-override -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-suggest-override) - -Wswitch -UrlSuffix(gcc/Warning-Options.html#index-Wno-switch) - -Wswitch-default -UrlSuffix(gcc/Warning-Options.html#index-Wno-switch-default) - -Wswitch-enum -UrlSuffix(gcc/Warning-Options.html#index-Wno-switch-enum) - -Wswitch-bool -UrlSuffix(gcc/Warning-Options.html#index-Wno-switch-bool) - -Wswitch-outside-range -UrlSuffix(gcc/Warning-Options.html#index-Wno-switch-outside-range) - -Wtemplates -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-templates) - -Wmissing-attributes -UrlSuffix(gcc/Warning-Options.html#index-Wmissing-attributes) - Wmissing-format-attribute UrlSuffix(gcc/Warning-Options.html#index-Wmissing-format-attribute) @@ -601,12 +532,27 @@ UrlSuffix(gcc/Warning-Options.html#index-Wmissing-parameter-type) Wmissing-prototypes UrlSuffix(gcc/Warning-Options.html#index-Wmissing-prototypes) +Wmissing-requires +UrlSuffix(gcc/Warning-Options.html#index-Wmissing-requires) + +Wmissing-template-keyword +UrlSuffix(gcc/Warning-Options.html#index-Wmissing-template-keyword) + Wmissing-variable-declarations UrlSuffix(gcc/Warning-Options.html#index-Wmissing-variable-declarations) Wmultichar UrlSuffix(gcc/Warning-Options.html#index-Wmultichar) +Wmultiple-inheritance +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wmultiple-inheritance) + +Wmultistatement-macros +UrlSuffix(gcc/Warning-Options.html#index-Wmultistatement-macros) + +Wnamespaces +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wnamespaces) + Wnarrowing UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wnarrowing) @@ -622,12 +568,6 @@ UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-noexcept-type) Wnon-template-friend UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-non-template-friend) -Wclass-conversion -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wclass-conversion) - -Wclass-memaccess -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wclass-memaccess) - Wnon-virtual-dtor UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-non-virtual-dtor) @@ -682,9 +622,15 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-override-init) Woverride-init-side-effects UrlSuffix(gcc/Warning-Options.html#index-Wno-override-init-side-effects) +Wnrvo +UrlSuffix(gcc/Warning-Options.html#index-Wno-nrvo) + Wpacked-bitfield-compat UrlSuffix(gcc/Warning-Options.html#index-Wno-packed-bitfield-compat) +Wpacked-not-aligned +UrlSuffix(gcc/Warning-Options.html#index-Wno-packed-not-aligned) + Wparentheses UrlSuffix(gcc/Warning-Options.html#index-Wno-parentheses) @@ -694,6 +640,12 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-pedantic) Wpessimizing-move UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-pessimizing-move) +Wplacement-new +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-placement-new) + +Wplacement-new= +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-placement-new) + ; skipping UrlSuffix for 'Wpmf-conversions' due to multiple URLs: ; duplicate: 'gcc/Bound-member-functions.html#index-Wno-pmf-conversions-1' ; duplicate: 'gcc/C_002b_002b-Dialect-Options.html#index-Wno-pmf-conversions' @@ -723,11 +675,8 @@ UrlSuffix(gcc/Objective-C-and-Objective-C_002b_002b-Dialect-Options.html#index-W Wprotocol UrlSuffix(gcc/Objective-C-and-Objective-C_002b_002b-Dialect-Options.html#index-Wno-protocol) -Wplacement-new -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-placement-new) - -Wplacement-new= -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-placement-new) +Wrange-loop-construct +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-range-loop-construct) Wredundant-decls UrlSuffix(gcc/Warning-Options.html#index-Wno-redundant-decls) @@ -735,12 +684,18 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-redundant-decls) Wredundant-move UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-redundant-move) +Wredundant-tags +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-redundant-tags) + Wregister UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-register) Wreorder UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-reorder) +Wrestrict +UrlSuffix(gcc/Warning-Options.html#index-Wno-restrict) + Wreturn-mismatch UrlSuffix(gcc/Warning-Options.html#index-Wno-return-mismatch) @@ -777,9 +732,6 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-shift-count-overflow) Wshift-negative-value UrlSuffix(gcc/Warning-Options.html#index-Wno-shift-negative-value) -Warith-conversion -UrlSuffix(gcc/Warning-Options.html#index-Warith-conversion) - Wsign-compare UrlSuffix(gcc/Warning-Options.html#index-Wno-sign-compare) @@ -792,30 +744,93 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-sign-conversion) Wsign-promo UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-sign-promo) -Wstrict-null-sentinel -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-strict-null-sentinel) +Wsized-deallocation +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-sized-deallocation) -Wstrict-prototypes -UrlSuffix(gcc/Warning-Options.html#index-Wno-strict-prototypes) +Wsizeof-array-div +UrlSuffix(gcc/Warning-Options.html#index-Wno-sizeof-array-div) + +Wsizeof-array-argument +UrlSuffix(gcc/Warning-Options.html#index-Wno-sizeof-array-argument) + +Wsizeof-pointer-div +UrlSuffix(gcc/Warning-Options.html#index-Wno-sizeof-pointer-div) + +Wsizeof-pointer-memaccess +UrlSuffix(gcc/Warning-Options.html#index-Wno-sizeof-pointer-memaccess) Wstrict-aliasing= UrlSuffix(gcc/Warning-Options.html#index-Wno-strict-aliasing) +Wstrict-flex-arrays +UrlSuffix(gcc/Warning-Options.html#index-Wno-strict-flex-arrays) + +Wstrict-null-sentinel +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-strict-null-sentinel) + Wstrict-overflow= UrlSuffix(gcc/Warning-Options.html#index-Wno-strict-overflow) +Wstrict-prototypes +UrlSuffix(gcc/Warning-Options.html#index-Wno-strict-prototypes) + Wstrict-selector-match UrlSuffix(gcc/Objective-C-and-Objective-C_002b_002b-Dialect-Options.html#index-Wno-strict-selector-match) +Wstring-compare +UrlSuffix(gcc/Warning-Options.html#index-Wno-string-compare) + +Wstringop-overflow +UrlSuffix(gcc/Warning-Options.html#index-Wno-stringop-overflow) + +Wstringop-overflow= +UrlSuffix(gcc/Warning-Options.html#index-Wno-stringop-overflow) + +Wstringop-overread +UrlSuffix(gcc/Warning-Options.html#index-Wno-stringop-overread) + +Wstringop-truncation +UrlSuffix(gcc/Warning-Options.html#index-Wno-stringop-truncation) + +Wsubobject-linkage +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-subobject-linkage) + +Wsuggest-attribute=format +UrlSuffix(gcc/Warning-Options.html#index-Wno-suggest-attribute_003dformat) + +Wsuggest-override +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-suggest-override) + +Wswitch +UrlSuffix(gcc/Warning-Options.html#index-Wno-switch) + +Wswitch-default +UrlSuffix(gcc/Warning-Options.html#index-Wno-switch-default) + +Wswitch-enum +UrlSuffix(gcc/Warning-Options.html#index-Wno-switch-enum) + +Wswitch-bool +UrlSuffix(gcc/Warning-Options.html#index-Wno-switch-bool) + +Wswitch-outside-range +UrlSuffix(gcc/Warning-Options.html#index-Wno-switch-outside-range) + Wsync-nand UrlSuffix(gcc/Warning-Options.html#index-Wno-sync-nand) Wsystem-headers UrlSuffix(gcc/Warning-Options.html#index-Wno-system-headers) +Wtemplates +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-templates) + Wtautological-compare UrlSuffix(gcc/Warning-Options.html#index-Wno-tautological-compare) +Wtemplate-id-cdtor +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-template-id-cdtor) + Wterminate UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-terminate) @@ -840,9 +855,6 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-unicode) Wuninitialized UrlSuffix(gcc/Warning-Options.html#index-Wno-uninitialized) -Wmaybe-uninitialized -UrlSuffix(gcc/Warning-Options.html#index-Wmaybe-uninitialized) - Wunknown-pragmas UrlSuffix(gcc/Warning-Options.html#index-Wno-unknown-pragmas) LangUrlSuffix_D(gdc/Warnings.html#index-Wno-unknown-pragmas) @@ -852,6 +864,12 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-unsuffixed-float-constants) Wunused UrlSuffix(gcc/Warning-Options.html#index-Wno-unused) +Wunused-const-variable +UrlSuffix(gcc/Warning-Options.html#index-Wno-unused-const-variable) + +Wunused-const-variable= +UrlSuffix(gcc/Warning-Options.html#index-Wno-unused-const-variable) + Wunused-local-typedefs UrlSuffix(gcc/Warning-Options.html#index-Wno-unused-local-typedefs) @@ -864,14 +882,11 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-unused-result) Wunused-variable UrlSuffix(gcc/Warning-Options.html#index-Wno-unused-variable) -Wunused-const-variable -UrlSuffix(gcc/Warning-Options.html#index-Wno-unused-const-variable) - -Wunused-const-variable= -UrlSuffix(gcc/Warning-Options.html#index-Wno-unused-const-variable) - Wuse-after-free= -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-use-after-free) +UrlSuffix(gcc/Warning-Options.html#index-Wno-use-after-free) + +Wuseless-cast +UrlSuffix(gcc/Warning-Options.html#index-Wno-useless-cast) Wvariadic-macros UrlSuffix(gcc/Warning-Options.html#index-Wno-variadic-macros) @@ -882,6 +897,9 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-varargs) LangUrlSuffix_D(gdc/Warnin Wvexing-parse UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-vexing-parse) +Wvirtual-move-assign +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-virtual-move-assign) + Wvla UrlSuffix(gcc/Warning-Options.html#index-Wno-vla) @@ -900,9 +918,6 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-volatile-register-var) Wvirtual-inheritance UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-virtual-inheritance) -Wvirtual-move-assign -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-virtual-move-assign) - Wwrite-strings UrlSuffix(gcc/Warning-Options.html#index-Wno-write-strings) @@ -912,20 +927,8 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-xor-used-as-pow) Wzero-as-null-pointer-constant UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-zero-as-null-pointer-constant) -Wuseless-cast -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-useless-cast) - -Wsubobject-linkage -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-subobject-linkage) - -Welaborated-enum-base -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Welaborated-enum-base) - -Wduplicate-decl-specifier -UrlSuffix(gcc/Warning-Options.html#index-Wduplicate-decl-specifier) - -Wrestrict -UrlSuffix(gcc/Warning-Options.html#index-Wno-restrict) +Wzero-length-bounds +UrlSuffix(gcc/Warning-Options.html#index-Wzero-length-bounds) ; skipping UrlSuffix for 'ansi' due to multiple URLs: ; duplicate: 'gcc/C-Dialect-Options.html#index-ansi-1' diff --git a/gcc/common.opt.urls b/gcc/common.opt.urls index 4cb2d7d..db43549 100644 --- a/gcc/common.opt.urls +++ b/gcc/common.opt.urls @@ -64,10 +64,10 @@ Warray-bounds= UrlSuffix(gcc/Warning-Options.html#index-Warray-bounds) Wuse-after-free -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-use-after-free) +UrlSuffix(gcc/Warning-Options.html#index-Wno-use-after-free) Wuse-after-free= -UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wno-use-after-free) +UrlSuffix(gcc/Warning-Options.html#index-Wno-use-after-free) Wattributes UrlSuffix(gcc/Warning-Options.html#index-Wattributes) diff --git a/gcc/config/avr/avr.opt.urls b/gcc/config/avr/avr.opt.urls index 7af6771..f38e673 100644 --- a/gcc/config/avr/avr.opt.urls +++ b/gcc/config/avr/avr.opt.urls @@ -12,6 +12,9 @@ UrlSuffix(gcc/AVR-Options.html#index-mgas-isr-prologues) mn-flash= UrlSuffix(gcc/AVR-Options.html#index-mn-flash) +mskip-bug +UrlSuffix(gcc/AVR-Options.html#index-mskip-bug) + mrmw UrlSuffix(gcc/AVR-Options.html#index-mrmw) @@ -42,9 +45,21 @@ UrlSuffix(gcc/AVR-Options.html#index-maccumulate-args) mstrict-X UrlSuffix(gcc/AVR-Options.html#index-mstrict-X) +mflmap +UrlSuffix(gcc/AVR-Options.html#index-mflmap) + +mrodata-in-ram +UrlSuffix(gcc/AVR-Options.html#index-mrodata-in-ram) + msp8 UrlSuffix(gcc/AVR-Options.html#index-msp8) +mfuse-add +UrlSuffix(gcc/AVR-Options.html#index-mfuse-add) + +mfuse-add= +UrlSuffix(gcc/AVR-Options.html#index-mfuse-add) + Waddr-space-convert UrlSuffix(gcc/AVR-Options.html#index-Waddr-space-convert) diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls index 9b988fd..0f20156 100644 --- a/gcc/config/i386/i386.opt.urls +++ b/gcc/config/i386/i386.opt.urls @@ -146,7 +146,7 @@ miamcu UrlSuffix(gcc/x86-Options.html#index-miamcu) mabi= -UrlSuffix(gcc/x86-Options.html#index-mabi-6) +UrlSuffix(gcc/x86-Options.html#index-mabi-7) mcall-ms2sysv-xlogues UrlSuffix(gcc/x86-Options.html#index-mcall-ms2sysv-xlogues) @@ -597,6 +597,12 @@ UrlSuffix(gcc/x86-Options.html#index-msm4) mapxf UrlSuffix(gcc/x86-Options.html#index-mapxf) +mapx-inline-asm-use-gpr32 +UrlSuffix(gcc/x86-Options.html#index-mapx-inline-asm-use-gpr32) + +mevex512 +UrlSuffix(gcc/x86-Options.html#index-mevex512) + musermsr UrlSuffix(gcc/x86-Options.html#index-musermsr) diff --git a/gcc/config/pru/pru.opt.urls b/gcc/config/pru/pru.opt.urls index 373b02d..1f8a26a 100644 --- a/gcc/config/pru/pru.opt.urls +++ b/gcc/config/pru/pru.opt.urls @@ -13,5 +13,5 @@ mloop UrlSuffix(gcc/PRU-Options.html#index-mloop) mabi= -UrlSuffix(gcc/PRU-Options.html#index-mabi-3) +UrlSuffix(gcc/PRU-Options.html#index-mabi-4) diff --git a/gcc/config/riscv/riscv.opt.urls b/gcc/config/riscv/riscv.opt.urls index e1ab966..f407958 100644 --- a/gcc/config/riscv/riscv.opt.urls +++ b/gcc/config/riscv/riscv.opt.urls @@ -12,7 +12,7 @@ UrlSuffix(gcc/RISC-V-Options.html#index-mbranch-cost-4) ; skipping UrlSuffix for 'mplt' due to finding no URLs mabi= -UrlSuffix(gcc/RISC-V-Options.html#index-mabi-4) +UrlSuffix(gcc/RISC-V-Options.html#index-mabi-5) mpreferred-stack-boundary= UrlSuffix(gcc/RISC-V-Options.html#index-mpreferred-stack-boundary) diff --git a/gcc/config/rs6000/rs6000.opt.urls b/gcc/config/rs6000/rs6000.opt.urls index 28bf073..c7c1cef 100644 --- a/gcc/config/rs6000/rs6000.opt.urls +++ b/gcc/config/rs6000/rs6000.opt.urls @@ -162,9 +162,6 @@ UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-msave-toc-indirect) mpower8-fusion UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mpower8-fusion) -mpower8-vector -UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mpower8-vector) - mcrypto UrlSuffix(gcc/RS_002f6000-and-PowerPC-Options.html#index-mcrypto) diff --git a/gcc/rust/lang.opt.urls b/gcc/rust/lang.opt.urls index 9cf8987..3d899ae 100644 --- a/gcc/rust/lang.opt.urls +++ b/gcc/rust/lang.opt.urls @@ -24,6 +24,9 @@ UrlSuffix(gcc/Warning-Options.html#index-Wno-unused-const-variable) Wunused-result UrlSuffix(gcc/Warning-Options.html#index-Wno-unused-result) +Winfinite-recursion +UrlSuffix(gcc/Warning-Options.html#index-Winfinite-recursion) + o UrlSuffix(gcc/Overall-Options.html#index-o) -- cgit v1.1 From 77eb86be8841989651b3150a020dd1a95910cc00 Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Thu, 22 Feb 2024 15:41:00 +0000 Subject: vect: Fix integer overflow calculating mask The masks and bitvectors were broken when nunits==32 on hosts where int is 32-bit. gcc/ChangeLog: * dojump.cc (do_compare_and_jump): Use full-width integers for shifts. * expr.cc (store_constructor): Likewise. (do_store_flag): Likewise. --- gcc/dojump.cc | 4 ++-- gcc/expr.cc | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'gcc') diff --git a/gcc/dojump.cc b/gcc/dojump.cc index ac744e5..88600cb 100644 --- a/gcc/dojump.cc +++ b/gcc/dojump.cc @@ -1318,10 +1318,10 @@ do_compare_and_jump (tree treeop0, tree treeop1, enum rtx_code signed_code, { gcc_assert (code == EQ || code == NE); op0 = expand_binop (mode, and_optab, op0, - GEN_INT ((1 << nunits) - 1), NULL_RTX, + GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), NULL_RTX, true, OPTAB_WIDEN); op1 = expand_binop (mode, and_optab, op1, - GEN_INT ((1 << nunits) - 1), NULL_RTX, + GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), NULL_RTX, true, OPTAB_WIDEN); } diff --git a/gcc/expr.cc b/gcc/expr.cc index 8d34d02..f7d7452 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -7879,8 +7879,8 @@ store_constructor (tree exp, rtx target, int cleared, poly_int64 size, auto nunits = TYPE_VECTOR_SUBPARTS (type).to_constant (); if (maybe_ne (GET_MODE_PRECISION (mode), nunits)) tmp = expand_binop (mode, and_optab, tmp, - GEN_INT ((1 << nunits) - 1), target, - true, OPTAB_WIDEN); + GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), + target, true, OPTAB_WIDEN); if (tmp != target) emit_move_insn (target, tmp); break; @@ -13707,11 +13707,11 @@ do_store_flag (sepops ops, rtx target, machine_mode mode) { gcc_assert (code == EQ || code == NE); op0 = expand_binop (mode, and_optab, op0, - GEN_INT ((1 << nunits) - 1), NULL_RTX, - true, OPTAB_WIDEN); + GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), + NULL_RTX, true, OPTAB_WIDEN); op1 = expand_binop (mode, and_optab, op1, - GEN_INT ((1 << nunits) - 1), NULL_RTX, - true, OPTAB_WIDEN); + GEN_INT ((HOST_WIDE_INT_1U << nunits) - 1), + NULL_RTX, true, OPTAB_WIDEN); } if (target == 0) -- cgit v1.1 From a89c5df317d1de74871e2a05c36aed9cbbb21f42 Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Mon, 4 Mar 2024 11:25:28 -0500 Subject: doc: update [[gnu::no_dangling]] ...to offer a more realistic example. gcc/ChangeLog: * doc/extend.texi: Update [[gnu::no_dangling]]. --- gcc/doc/extend.texi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index f679c81..df0982f 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -29370,7 +29370,8 @@ Or: @smallexample template -[[gnu::no_dangling(std::is_reference_v)]] int& foo (T& t) @{ +[[gnu::no_dangling(std::is_lvalue_reference_v)]] +decltype(auto) foo(T&& t) @{ @dots{} @}; @end smallexample -- cgit v1.1 From 0b49dfcf14aa428b67ffe308d1cb2bcd98f1cb95 Mon Sep 17 00:00:00 2001 From: Stam Markianos-Wright Date: Mon, 11 Dec 2023 14:52:35 +0000 Subject: arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns This patch adds an attribute to the mve md patterns to be able to identify predicable MVE instructions and what their predicated and unpredicated variants are. This attribute is used to encode the icode of the unpredicated variant of an instruction in its predicated variant. This will make it possible for us to transform VPT-predicated insns in the insn chain into their unpredicated equivalents when transforming the loop into a MVE Tail-Predicated Low Overhead Loop. For example: `mve_vldrbq_z_ -> mve_vldrbq_`. gcc/ChangeLog: * config/arm/arm.md (mve_unpredicated_insn): New attribute. * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define. (MVE_VPT_UNPREDICATED_INSN_P): Likewise. (MVE_VPT_PREDICABLE_INSN_P): Likewise. * config/arm/vec-common.md (mve_vshlq_): Add attribute. * config/arm/mve.md (arm_vcx1q_p_v16qi): Add attribute. (arm_vcx1qv16qi): Likewise. (arm_vcx1qav16qi): Likewise. (arm_vcx1qv16qi): Likewise. (arm_vcx2q_p_v16qi): Likewise. (arm_vcx2qv16qi): Likewise. (arm_vcx2qav16qi): Likewise. (arm_vcx2qv16qi): Likewise. (arm_vcx3q_p_v16qi): Likewise. (arm_vcx3qv16qi): Likewise. (arm_vcx3qav16qi): Likewise. (arm_vcx3qv16qi): Likewise. (@mve_q_): Likewise. (@mve_q_int_): Likewise. (@mve_q_v4si): Likewise. (@mve_q_n_): Likewise. (@mve_q_r_): Likewise. (@mve_q_f): Likewise. (@mve_q_m_): Likewise. (@mve_q_m_n_): Likewise. (@mve_q_m_r_): Likewise. (@mve_q_m_f): Likewise. (@mve_q_int_m_): Likewise. (@mve_q_p_v4si): Likewise. (@mve_q_p_): Likewise. (@mve_q_): Likewise. (@mve_q_f): Likewise. (@mve_q_m_): Likewise. (@mve_q_m_f): Likewise. (mve_vq_f): Likewise. (mve_q): Likewise. (mve_q_f): Likewise. (mve_vadciq_v4si): Likewise. (mve_vadciq_m_v4si): Likewise. (mve_vadcq_v4si): Likewise. (mve_vadcq_m_v4si): Likewise. (mve_vandq_): Likewise. (mve_vandq_f): Likewise. (mve_vandq_m_): Likewise. (mve_vandq_m_f): Likewise. (mve_vandq_s): Likewise. (mve_vandq_u): Likewise. (mve_vbicq_): Likewise. (mve_vbicq_f): Likewise. (mve_vbicq_m_): Likewise. (mve_vbicq_m_f): Likewise. (mve_vbicq_m_n_): Likewise. (mve_vbicq_n_): Likewise. (mve_vbicq_s): Likewise. (mve_vbicq_u): Likewise. (@mve_vclzq_s): Likewise. (mve_vclzq_u): Likewise. (@mve_vcmp_q_): Likewise. (@mve_vcmp_q_n_): Likewise. (@mve_vcmp_q_f): Likewise. (@mve_vcmp_q_n_f): Likewise. (@mve_vcmp_q_m_f): Likewise. (@mve_vcmp_q_m_n_): Likewise. (@mve_vcmp_q_m_): Likewise. (@mve_vcmp_q_m_n_f): Likewise. (mve_vctpq): Likewise. (mve_vctpq_m): Likewise. (mve_vcvtaq_): Likewise. (mve_vcvtaq_m_): Likewise. (mve_vcvtbq_f16_f32v8hf): Likewise. (mve_vcvtbq_f32_f16v4sf): Likewise. (mve_vcvtbq_m_f16_f32v8hf): Likewise. (mve_vcvtbq_m_f32_f16v4sf): Likewise. (mve_vcvtmq_): Likewise. (mve_vcvtmq_m_): Likewise. (mve_vcvtnq_): Likewise. (mve_vcvtnq_m_): Likewise. (mve_vcvtpq_): Likewise. (mve_vcvtpq_m_): Likewise. (mve_vcvtq_from_f_): Likewise. (mve_vcvtq_m_from_f_): Likewise. (mve_vcvtq_m_n_from_f_): Likewise. (mve_vcvtq_m_n_to_f_): Likewise. (mve_vcvtq_m_to_f_): Likewise. (mve_vcvtq_n_from_f_): Likewise. (mve_vcvtq_n_to_f_): Likewise. (mve_vcvtq_to_f_): Likewise. (mve_vcvttq_f16_f32v8hf): Likewise. (mve_vcvttq_f32_f16v4sf): Likewise. (mve_vcvttq_m_f16_f32v8hf): Likewise. (mve_vcvttq_m_f32_f16v4sf): Likewise. (mve_vdwdupq_m_wb_u_insn): Likewise. (mve_vdwdupq_wb_u_insn): Likewise. (mve_veorq_s>): Likewise. (mve_veorq_u>): Likewise. (mve_veorq_f): Likewise. (mve_vidupq_m_wb_u_insn): Likewise. (mve_vidupq_u_insn): Likewise. (mve_viwdupq_m_wb_u_insn): Likewise. (mve_viwdupq_wb_u_insn): Likewise. (mve_vldrbq_): Likewise. (mve_vldrbq_gather_offset_): Likewise. (mve_vldrbq_gather_offset_z_): Likewise. (mve_vldrbq_z_): Likewise. (mve_vldrdq_gather_base_v2di): Likewise. (mve_vldrdq_gather_base_wb_v2di_insn): Likewise. (mve_vldrdq_gather_base_wb_z_v2di_insn): Likewise. (mve_vldrdq_gather_base_z_v2di): Likewise. (mve_vldrdq_gather_offset_v2di): Likewise. (mve_vldrdq_gather_offset_z_v2di): Likewise. (mve_vldrdq_gather_shifted_offset_v2di): Likewise. (mve_vldrdq_gather_shifted_offset_z_v2di): Likewise. (mve_vldrhq_): Likewise. (mve_vldrhq_fv8hf): Likewise. (mve_vldrhq_gather_offset_): Likewise. (mve_vldrhq_gather_offset_fv8hf): Likewise. (mve_vldrhq_gather_offset_z_): Likewise. (mve_vldrhq_gather_offset_z_fv8hf): Likewise. (mve_vldrhq_gather_shifted_offset_): Likewise. (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise. (mve_vldrhq_gather_shifted_offset_z_): Likewise. (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise. (mve_vldrhq_z_): Likewise. (mve_vldrhq_z_fv8hf): Likewise. (mve_vldrwq_v4si): Likewise. (mve_vldrwq_fv4sf): Likewise. (mve_vldrwq_gather_base_v4si): Likewise. (mve_vldrwq_gather_base_fv4sf): Likewise. (mve_vldrwq_gather_base_wb_v4si_insn): Likewise. (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise. (mve_vldrwq_gather_base_wb_z_v4si_insn): Likewise. (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise. (mve_vldrwq_gather_base_z_v4si): Likewise. (mve_vldrwq_gather_base_z_fv4sf): Likewise. (mve_vldrwq_gather_offset_v4si): Likewise. (mve_vldrwq_gather_offset_fv4sf): Likewise. (mve_vldrwq_gather_offset_z_v4si): Likewise. (mve_vldrwq_gather_offset_z_fv4sf): Likewise. (mve_vldrwq_gather_shifted_offset_v4si): Likewise. (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise. (mve_vldrwq_gather_shifted_offset_z_v4si): Likewise. (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise. (mve_vldrwq_z_v4si): Likewise. (mve_vldrwq_z_fv4sf): Likewise. (mve_vmvnq_s): Likewise. (mve_vmvnq_u): Likewise. (mve_vornq_): Likewise. (mve_vornq_f): Likewise. (mve_vornq_m_): Likewise. (mve_vornq_m_f): Likewise. (mve_vornq_s): Likewise. (mve_vornq_u): Likewise. (mve_vorrq_): Likewise. (mve_vorrq_f): Likewise. (mve_vorrq_m_): Likewise. (mve_vorrq_m_f): Likewise. (mve_vorrq_m_n_): Likewise. (mve_vorrq_n_): Likewise. (mve_vorrq_s): Likewise. (mve_vorrq_s): Likewise. (mve_vsbciq_v4si): Likewise. (mve_vsbciq_m_v4si): Likewise. (mve_vsbcq_v4si): Likewise. (mve_vsbcq_m_v4si): Likewise. (mve_vshlcq_): Likewise. (mve_vshlcq_m_): Likewise. (mve_vshrq_m_n_): Likewise. (mve_vshrq_n_): Likewise. (mve_vstrbq_): Likewise. (mve_vstrbq_p_): Likewise. (mve_vstrbq_scatter_offset__insn): Likewise. (mve_vstrbq_scatter_offset_p__insn): Likewise. (mve_vstrdq_scatter_base_v2di): Likewise. (mve_vstrdq_scatter_base_p_v2di): Likewise. (mve_vstrdq_scatter_base_wb_v2di): Likewise. (mve_vstrdq_scatter_base_wb_p_v2di): Likewise. (mve_vstrdq_scatter_offset_v2di_insn): Likewise. (mve_vstrdq_scatter_offset_p_v2di_insn): Likewise. (mve_vstrdq_scatter_shifted_offset_v2di_insn): Likewise. (mve_vstrdq_scatter_shifted_offset_p_v2di_insn): Likewise. (mve_vstrhq_): Likewise. (mve_vstrhq_fv8hf): Likewise. (mve_vstrhq_p_): Likewise. (mve_vstrhq_p_fv8hf): Likewise. (mve_vstrhq_scatter_offset__insn): Likewise. (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise. (mve_vstrhq_scatter_offset_p__insn): Likewise. (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise. (mve_vstrhq_scatter_shifted_offset__insn): Likewise. (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise. (mve_vstrhq_scatter_shifted_offset_p__insn): Likewise. (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise. (mve_vstrwq_v4si): Likewise. (mve_vstrwq_fv4sf): Likewise. (mve_vstrwq_p_v4si): Likewise. (mve_vstrwq_p_fv4sf): Likewise. (mve_vstrwq_scatter_base_v4si): Likewise. (mve_vstrwq_scatter_base_fv4sf): Likewise. (mve_vstrwq_scatter_base_p_v4si): Likewise. (mve_vstrwq_scatter_base_p_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_v4si): Likewise. (mve_vstrwq_scatter_base_wb_fv4sf): Likewise. (mve_vstrwq_scatter_base_wb_p_v4si): Likewise. (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise. (mve_vstrwq_scatter_offset_v4si_insn): Likewise. (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise. (mve_vstrwq_scatter_offset_p_v4si_insn): Likewise. (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_v4si_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_p_v4si_insn): Likewise. (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise. --- gcc/config/arm/arm.h | 15 + gcc/config/arm/arm.md | 6 + gcc/config/arm/mve.md | 906 ++++++++++++++++++++++++++++--------------- gcc/config/arm/vec-common.md | 3 +- 4 files changed, 625 insertions(+), 305 deletions(-) (limited to 'gcc') diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 2a2207c..449e693 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2375,6 +2375,21 @@ extern int making_const_table; else if (TARGET_THUMB1) \ thumb1_final_prescan_insn (INSN) +/* These defines are useful to refer to the value of the mve_unpredicated_insn + insn attribute. Note that, because these use the get_attr_* function, these + will change recog_data if (INSN) isn't current_insn. */ +#define MVE_VPT_PREDICABLE_INSN_P(INSN) \ + (recog_memoized (INSN) >= 0 \ + && get_attr_mve_unpredicated_insn (INSN) != CODE_FOR_nothing) + +#define MVE_VPT_PREDICATED_INSN_P(INSN) \ + (MVE_VPT_PREDICABLE_INSN_P (INSN) \ + && recog_memoized (INSN) != get_attr_mve_unpredicated_insn (INSN)) + +#define MVE_VPT_UNPREDICATED_INSN_P(INSN) \ + (MVE_VPT_PREDICABLE_INSN_P (INSN) \ + && recog_memoized (INSN) == get_attr_mve_unpredicated_insn (INSN)) + #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5816409..81290e8 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -124,6 +124,12 @@ ; and not all ARM insns do. (define_attr "predicated" "yes,no" (const_string "no")) +; An attribute that encodes the CODE_FOR_ of the MVE VPT unpredicated +; version of a VPT-predicated instruction. For unpredicated instructions +; that are predicable, encode the same pattern's CODE_FOR_ as a way to +; encode that it is a predicable instruction. +(define_attr "mve_unpredicated_insn" "" (symbol_ref "CODE_FOR_nothing")) + ; LENGTH of an instruction (in bytes) (define_attr "length" "" (const_int 4)) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 0fabbaa..8aa0bde 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -17,7 +17,7 @@ ;; along with GCC; see the file COPYING3. If not see ;; . -(define_insn "*mve_mov" +(define_insn "mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w , w, r,Ux,w") (match_operand:MVE_types 1 "general_operand" " w,r,w,DnDm,UxUi,r,w, Ul"))] "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" @@ -81,18 +81,27 @@ return ""; } } - [(set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_store,mve_load") + [(set_attr_alternative "mve_unpredicated_insn" [(symbol_ref "CODE_FOR_mve_mov") + (symbol_ref "CODE_FOR_nothing") + (symbol_ref "CODE_FOR_nothing") + (symbol_ref "CODE_FOR_mve_mov") + (symbol_ref "CODE_FOR_mve_mov") + (symbol_ref "CODE_FOR_nothing") + (symbol_ref "CODE_FOR_mve_mov") + (symbol_ref "CODE_FOR_nothing")]) + (set_attr "type" "mve_move,mve_move,mve_move,mve_move,mve_load,multiple,mve_store,mve_load") (set_attr "length" "4,8,8,4,4,8,4,8") (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*") (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*")]) -(define_insn "*mve_vdup" +(define_insn "mve_vdup" [(set (match_operand:MVE_vecs 0 "s_register_operand" "=w") (vec_duplicate:MVE_vecs (match_operand: 1 "s_register_operand" "r")))] "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" "vdup.\t%q0, %1" - [(set_attr "length" "4") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vdup")) + (set_attr "length" "4") (set_attr "type" "mve_move")]) ;; @@ -145,7 +154,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; @@ -159,7 +169,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; @@ -173,7 +184,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "v.f%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vq_f")) + (set_attr "type" "mve_move") ]) ;; @@ -187,7 +199,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".%#\t%q0, %1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_f")) + (set_attr "type" "mve_move") ]) ;; @@ -201,7 +214,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; ;; [vcvttq_f32_f16]) @@ -214,7 +228,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvtt.f32.f16\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvttq_f32_f16v4sf")) + (set_attr "type" "mve_move") ]) ;; @@ -228,7 +243,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvtb.f32.f16\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtbq_f32_f16v4sf")) + (set_attr "type" "mve_move") ]) ;; @@ -242,7 +258,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvt.f%#.%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_to_f_")) + (set_attr "type" "mve_move") ]) ;; @@ -256,7 +273,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -270,7 +288,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvt.%#.f%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_from_f_")) + (set_attr "type" "mve_move") ]) ;; @@ -284,7 +303,8 @@ ] "TARGET_HAVE_MVE" "v.s%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vq_s")) + (set_attr "type" "mve_move") ]) ;; @@ -297,7 +317,8 @@ ] "TARGET_HAVE_MVE" "vmvn\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vmvnq_u")) + (set_attr "type" "mve_move") ]) (define_expand "mve_vmvnq_s" [ @@ -318,7 +339,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -331,7 +353,8 @@ ] "TARGET_HAVE_MVE" "vclz.i%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vclzq_s")) + (set_attr "type" "mve_move") ]) (define_expand "mve_vclzq_u" [ @@ -354,7 +377,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -368,7 +392,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -382,7 +407,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -397,7 +423,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -411,7 +438,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvtp.%#.f%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtpq_")) + (set_attr "type" "mve_move") ]) ;; @@ -425,7 +453,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvtn.%#.f%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtnq_")) + (set_attr "type" "mve_move") ]) ;; @@ -439,7 +468,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvtm.%#.f%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtmq_")) + (set_attr "type" "mve_move") ]) ;; @@ -453,7 +483,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvta.%#.f%#\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtaq_")) + (set_attr "type" "mve_move") ]) ;; @@ -467,7 +498,8 @@ ] "TARGET_HAVE_MVE" ".i%#\t%q0, %1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -481,7 +513,8 @@ ] "TARGET_HAVE_MVE" ".\t%q0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -495,7 +528,8 @@ ] "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "type" "mve_move") ]) ;; @@ -509,7 +543,8 @@ ] "TARGET_HAVE_MVE" "vctp.\t%1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vctpq")) + (set_attr "type" "mve_move") ]) ;; @@ -523,7 +558,8 @@ ] "TARGET_HAVE_MVE" "vpnot" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vpnotv16bi")) + (set_attr "type" "mve_move") ]) ;; @@ -538,7 +574,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_f")) + (set_attr "type" "mve_move") ]) ;; @@ -553,7 +590,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvt.f.\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_to_f_")) + (set_attr "type" "mve_move") ]) ;; [vcreateq_f]) @@ -599,7 +637,8 @@ ] "TARGET_HAVE_MVE" ".\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; Versions that take constant vectors as operand 2 (with all elements @@ -617,7 +656,8 @@ VALID_NEON_QREG_MODE (mode), true); } - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vshrq_n_s_imm")) + (set_attr "type" "mve_move") ]) (define_insn "mve_vshrq_n_u_imm" [ @@ -632,7 +672,8 @@ VALID_NEON_QREG_MODE (mode), true); } - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vshrq_n_u_imm")) + (set_attr "type" "mve_move") ]) ;; @@ -647,7 +688,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvt..f\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_from_f_")) + (set_attr "type" "mve_move") ]) ;; @@ -662,8 +704,9 @@ ] "TARGET_HAVE_MVE" "vpst\;t.32\t%Q0, %R0, %q1" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "type" "mve_move") + (set_attr "length""8")]) ;; ;; [vcmpneq_, vcmpcsq_, vcmpeqq_, vcmpgeq_, vcmpgtq_, vcmphiq_, vcmpleq_, vcmpltq_]) @@ -676,7 +719,8 @@ ] "TARGET_HAVE_MVE" "vcmp.%#\t, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcmpq_")) + (set_attr "type" "mve_move") ]) ;; @@ -691,7 +735,8 @@ ] "TARGET_HAVE_MVE" "vcmp.%# , %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcmpq_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -722,7 +767,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -739,7 +785,8 @@ ] "TARGET_HAVE_MVE" ".i%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -754,7 +801,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -769,7 +817,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%0, %q1" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -789,8 +838,11 @@ "@ vand\t%q0, %q1, %q2 * return neon_output_logic_immediate (\"vand\", &operands[2], mode, 1, VALID_NEON_QREG_MODE (mode));" - [(set_attr "type" "mve_move") + [(set_attr_alternative "mve_unpredicated_insn" [(symbol_ref "CODE_FOR_mve_vandq_u") + (symbol_ref "CODE_FOR_nothing")]) + (set_attr "type" "mve_move") ]) + (define_expand "mve_vandq_s" [ (set (match_operand:MVE_2 0 "s_register_operand") @@ -811,7 +863,8 @@ ] "TARGET_HAVE_MVE" "vbic\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vbicq_u")) + (set_attr "type" "mve_move") ]) (define_expand "mve_vbicq_s" @@ -835,7 +888,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -853,7 +907,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1, %q2, #" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; Auto vectorizer pattern for int vcadd @@ -876,7 +931,8 @@ ] "TARGET_HAVE_MVE" "veor\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_veorq_u")) + (set_attr "type" "mve_move") ]) (define_expand "mve_veorq_s" [ @@ -904,7 +960,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -920,7 +977,8 @@ ] "TARGET_HAVE_MVE" ".s%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -935,7 +993,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) @@ -954,7 +1013,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -972,7 +1032,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -988,7 +1049,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_int_")) + (set_attr "type" "mve_move") ]) ;; @@ -1004,7 +1066,8 @@ ] "TARGET_HAVE_MVE" ".i%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q")) + (set_attr "type" "mve_move") ]) ;; @@ -1018,7 +1081,8 @@ ] "TARGET_HAVE_MVE" "vorn\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vornq_s")) + (set_attr "type" "mve_move") ]) (define_expand "mve_vornq_u" @@ -1047,7 +1111,8 @@ "@ vorr\t%q0, %q1, %q2 * return neon_output_logic_immediate (\"vorr\", &operands[2], mode, 0, VALID_NEON_QREG_MODE (mode));" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vorrq_s")) + (set_attr "type" "mve_move") ]) (define_expand "mve_vorrq_u" [ @@ -1071,7 +1136,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -1087,7 +1153,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -1103,7 +1170,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_r_")) + (set_attr "type" "mve_move") ]) ;; @@ -1118,7 +1186,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -1133,7 +1202,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1148,7 +1218,8 @@ ] "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "type" "mve_move") ]) ;; @@ -1165,7 +1236,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1179,7 +1251,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vand\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vandq_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1193,7 +1266,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vbic\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vbicq_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1209,7 +1283,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%#\t%q0, %q1, %q2, #" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1223,7 +1298,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcmp.f%# , %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcmpq_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1238,7 +1314,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcmp.f%# , %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcmpq_n_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1253,8 +1330,10 @@ ] "TARGET_HAVE_MVE" "vpst\;vctpt.\t%1" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vctpq")) + (set_attr "type" "mve_move") + (set_attr "length""8") +]) ;; ;; [vcvtbq_f16_f32]) @@ -1268,7 +1347,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvtb.f16.f32\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtbq_f16_f32v8hf")) + (set_attr "type" "mve_move") ]) ;; @@ -1283,7 +1363,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vcvtt.f16.f32\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvttq_f16_f32v8hf")) + (set_attr "type" "mve_move") ]) ;; @@ -1297,7 +1378,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "veor\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_veorq_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1313,7 +1395,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1331,7 +1414,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%#\t%0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1346,7 +1430,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%# %q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1364,7 +1449,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%Q0, %R0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -1384,7 +1470,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -1400,7 +1487,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1414,7 +1502,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vorn\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vornq_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1428,7 +1517,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vorr\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vorrq_f")) + (set_attr "type" "mve_move") ]) ;; @@ -1444,7 +1534,8 @@ ] "TARGET_HAVE_MVE" ".i%# %q0, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -1460,7 +1551,8 @@ ] "TARGET_HAVE_MVE" ".s%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -1476,7 +1568,8 @@ ] "TARGET_HAVE_MVE" ".s%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -1494,7 +1587,8 @@ ] "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "type" "mve_move") ]) ;; @@ -1510,7 +1604,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -1526,7 +1621,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_poly_")) + (set_attr "type" "mve_move") ]) ;; @@ -1547,8 +1643,9 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcmpt.f%#\t, %q1, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcmpq_f")) + (set_attr "length""8")]) + ;; ;; [vcvtaq_m_u, vcvtaq_m_s]) ;; @@ -1562,8 +1659,10 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvtat.%#.f%#\t%q0, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtaq_")) + (set_attr "type" "mve_move") + (set_attr "length""8")]) + ;; ;; [vcvtq_m_to_f_s, vcvtq_m_to_f_u]) ;; @@ -1577,8 +1676,9 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvtt.f%#.%#\t%q0, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_to_f_")) + (set_attr "type" "mve_move") + (set_attr "length""8")]) ;; ;; [vqrshrnbq_n_u, vqrshrnbq_n_s] @@ -1604,7 +1704,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -1623,7 +1724,8 @@ ] "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "type" "mve_move") ]) ;; @@ -1639,7 +1741,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -1685,7 +1788,10 @@ (match_dup 4)] VSHLCQ))] "TARGET_HAVE_MVE" - "vshlc\t%q0, %1, %4") + "vshlc\t%q0, %1, %4" + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vshlcq_")) + (set_attr "type" "mve_move") +]) ;; ;; [vabsq_m_s] @@ -1705,7 +1811,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1721,7 +1828,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1744,7 +1852,8 @@ ] "TARGET_HAVE_MVE" "vpst\;vcmpt.%#\t, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcmpq_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1767,7 +1876,8 @@ ] "TARGET_HAVE_MVE" "vpst\;vcmpt.%#\t, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcmpq_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1783,7 +1893,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1800,7 +1911,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.s%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1819,7 +1931,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1838,7 +1951,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -1857,7 +1971,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1878,7 +1993,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -1894,7 +2010,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1910,7 +2027,8 @@ ] "TARGET_HAVE_MVE" "\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -1933,7 +2051,8 @@ ] "TARGET_HAVE_MVE" ".s%#\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -1950,7 +2069,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1967,7 +2087,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_r_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1983,7 +2104,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -1999,7 +2121,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -2015,7 +2138,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") ]) ;; @@ -2038,7 +2162,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.f%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2054,7 +2179,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.32\t%Q0, %R0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; ;; [vcmlaq, vcmlaq_rot90, vcmlaq_rot180, vcmlaq_rot270]) @@ -2072,7 +2198,9 @@ "@ vcmul.f%# %q0, %q2, %q3, # vcmla.f%# %q0, %q2, %q3, #" - [(set_attr "type" "mve_move") + [(set_attr_alternative "mve_unpredicated_insn" [(symbol_ref "CODE_FOR_mve_q_f") + (symbol_ref "CODE_FOR_mve_q_f")]) + (set_attr "type" "mve_move") ]) ;; @@ -2093,7 +2221,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcmpt.f%#\t, %q1, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcmpq_n_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2109,7 +2238,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvtbt.f16.f32\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtbq_f16_f32v8hf")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2125,7 +2255,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvtbt.f32.f16\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtbq_f32_f16v4sf")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2141,7 +2272,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvttt.f16.f32\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvttq_f16_f32v8hf")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2157,8 +2289,9 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvttt.f32.f16\t%q0, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvttq_f32_f16v4sf")) + (set_attr "type" "mve_move") + (set_attr "length""8")]) ;; ;; [vdupq_m_n_f]) @@ -2173,7 +2306,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.%#\t%q0, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2190,7 +2324,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%#\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; @@ -2207,7 +2342,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_f")) + (set_attr "type" "mve_move") ]) ;; @@ -2224,7 +2360,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.f%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2243,7 +2380,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.f%#\t%0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2262,7 +2400,8 @@ ] "TARGET_HAVE_MVE" ".%#\t%Q0, %R0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") ]) ;; @@ -2281,7 +2420,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%Q0, %R0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2298,7 +2438,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2319,7 +2460,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2335,7 +2477,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.i%#\t%q0, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2352,7 +2495,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.i%#\t%q0, %2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2368,7 +2512,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") ]) ;; @@ -2384,7 +2529,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2400,7 +2546,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2416,7 +2563,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2435,7 +2583,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.32\t%Q0, %R0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2451,7 +2600,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvtmt.%#.f%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtmq_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2467,7 +2617,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvtpt.%#.f%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtpq_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2483,7 +2634,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvtnt.%#.f%#\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtnq_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2500,7 +2652,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvtt.%#.f%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_from_f_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2516,7 +2669,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.\t%q0, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2532,8 +2686,9 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvtt.%#.f%#\t%q0, %q2" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_from_f_")) + (set_attr "type" "mve_move") + (set_attr "length""8")]) ;; ;; [vabavq_p_s, vabavq_p_u]) @@ -2549,7 +2704,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length" "8")]) ;; @@ -2566,8 +2722,9 @@ ] "TARGET_HAVE_MVE" "vpst\n\tt.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") + (set_attr "length" "8")]) ;; ;; [vsriq_m_n_s, vsriq_m_n_u]) @@ -2583,8 +2740,9 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") + (set_attr "length" "8")]) ;; ;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]) @@ -2600,7 +2758,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vcvtt.f%#.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vcvtq_n_to_f_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2640,7 +2799,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2659,8 +2819,9 @@ ] "TARGET_HAVE_MVE" "vpst\;t.i%# %q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") + (set_attr "length""8")]) ;; ;; [vaddq_m_u, vaddq_m_s] @@ -2678,7 +2839,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.i%#\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2698,7 +2860,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2715,8 +2878,9 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") + (set_attr "length""8")]) ;; ;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s] @@ -2735,7 +2899,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %q3, #" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2763,7 +2928,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2784,7 +2950,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2802,7 +2969,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_int_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2819,7 +2987,8 @@ ] "TARGET_HAVE_MVE" "vpst\;vornt\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vornq_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2837,7 +3006,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2855,7 +3025,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2872,7 +3043,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2892,7 +3064,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%Q0, %R0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2920,7 +3093,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2940,7 +3114,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.32\t%Q0, %R0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2958,7 +3133,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2976,7 +3152,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.%#\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_poly_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -2994,7 +3171,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.s%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -3012,7 +3190,8 @@ ] "TARGET_HAVE_MVE" "vpst\;t.s%#\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -3036,7 +3215,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.f%# %q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -3057,7 +3237,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.f%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -3077,7 +3258,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -3094,7 +3276,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_n_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -3116,7 +3299,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.f%#\t%q0, %q2, %q3, #" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -3136,7 +3320,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.f%#\t%q0, %q2, %q3, #" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -3153,7 +3338,8 @@ ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vornt\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vornq_f")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -3173,7 +3359,8 @@ output_asm_insn("vstrb.\t%q1, %E0",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrbq_")) + (set_attr "length" "4")]) ;; ;; [vstrbq_scatter_offset_s vstrbq_scatter_offset_u] @@ -3201,7 +3388,8 @@ VSTRBSOQ))] "TARGET_HAVE_MVE" "vstrb.\t%q2, [%0, %q1]" - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrbq_scatter_offset__insn")) + (set_attr "length" "4")]) ;; ;; [vstrwq_scatter_base_s vstrwq_scatter_base_u] @@ -3223,7 +3411,8 @@ output_asm_insn("vstrw.u32\t%q2, [%q0, %1]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_base_v4si")) + (set_attr "length" "4")]) ;; ;; [vldrbq_gather_offset_s vldrbq_gather_offset_u] @@ -3246,7 +3435,8 @@ output_asm_insn ("vldrb.\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrbq_gather_offset_")) + (set_attr "length" "4")]) ;; ;; [vldrbq_s vldrbq_u] @@ -3268,7 +3458,8 @@ output_asm_insn ("vldrb.\t%q0, %E1",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrbq_")) + (set_attr "length" "4")]) ;; ;; [vldrwq_gather_base_s vldrwq_gather_base_u] @@ -3288,7 +3479,8 @@ output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_base_v4si")) + (set_attr "length" "4")]) ;; ;; [vstrbq_scatter_offset_p_s vstrbq_scatter_offset_p_u] @@ -3320,7 +3512,8 @@ VSTRBSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrbt.\t%q2, [%0, %q1]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrbq_scatter_offset__insn")) + (set_attr "length" "8")]) ;; ;; [vstrwq_scatter_base_p_s vstrwq_scatter_base_p_u] @@ -3343,7 +3536,8 @@ output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_base_v4si")) + (set_attr "length" "8")]) (define_insn "mve_vstrbq_p_" [(set (match_operand: 0 "mve_memory_operand" "=Ux") @@ -3361,7 +3555,8 @@ output_asm_insn ("vpst\;vstrbt.\t%q1, %E0",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrbq_")) + (set_attr "length" "8")]) ;; ;; [vldrbq_gather_offset_z_s vldrbq_gather_offset_z_u] @@ -3386,7 +3581,8 @@ output_asm_insn ("vpst\n\tvldrbt.\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrbq_gather_offset_")) + (set_attr "length" "8")]) ;; ;; [vldrbq_z_s vldrbq_z_u] @@ -3409,7 +3605,8 @@ output_asm_insn ("vpst\;vldrbt.\t%q0, %E1",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrbq_")) + (set_attr "length" "8")]) ;; ;; [vldrwq_gather_base_z_s vldrwq_gather_base_z_u] @@ -3430,7 +3627,8 @@ output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_base_v4si")) + (set_attr "length" "8")]) ;; ;; [vldrhq_f] @@ -3449,7 +3647,8 @@ output_asm_insn ("vldrh.16\t%q0, %E1",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_fv8hf")) + (set_attr "length" "4")]) ;; ;; [vldrhq_gather_offset_s vldrhq_gather_offset_u] @@ -3472,7 +3671,8 @@ output_asm_insn ("vldrh.\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_gather_offset_")) + (set_attr "length" "4")]) ;; ;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u] @@ -3497,7 +3697,8 @@ output_asm_insn ("vpst\n\tvldrht.\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_gather_offset_")) + (set_attr "length" "8")]) ;; ;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u] @@ -3520,7 +3721,8 @@ output_asm_insn ("vldrh.\t%q0, [%m1, %q2, uxtw #1]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_gather_shifted_offset_")) + (set_attr "length" "4")]) ;; ;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u] @@ -3545,7 +3747,8 @@ output_asm_insn ("vpst\n\tvldrht.\t%q0, [%m1, %q2, uxtw #1]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_gather_shifted_offset_")) + (set_attr "length" "8")]) ;; ;; [vldrhq_s, vldrhq_u] @@ -3567,7 +3770,8 @@ output_asm_insn ("vldrh.\t%q0, %E1",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_")) + (set_attr "length" "4")]) ;; ;; [vldrhq_z_f] @@ -3587,7 +3791,8 @@ output_asm_insn ("vpst\;vldrht.16\t%q0, %E1",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_fv8hf")) + (set_attr "length" "8")]) ;; ;; [vldrhq_z_s vldrhq_z_u] @@ -3610,7 +3815,8 @@ output_asm_insn ("vpst\;vldrht.\t%q0, %E1",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_")) + (set_attr "length" "8")]) ;; ;; [vldrwq_f] @@ -3629,7 +3835,8 @@ output_asm_insn ("vldrw.32\t%q0, %E1",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_fv4sf")) + (set_attr "length" "4")]) ;; ;; [vldrwq_s vldrwq_u] @@ -3648,7 +3855,8 @@ output_asm_insn ("vldrw.32\t%q0, %E1",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_v4si")) + (set_attr "length" "4")]) ;; ;; [vldrwq_z_f] @@ -3668,7 +3876,8 @@ output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_fv4sf")) + (set_attr "length" "8")]) ;; ;; [vldrwq_z_s vldrwq_z_u] @@ -3688,7 +3897,8 @@ output_asm_insn ("vpst\;vldrwt.32\t%q0, %E1",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_v4si")) + (set_attr "length" "8")]) (define_expand "@mve_vld1q_f" [(match_operand:MVE_0 0 "s_register_operand") @@ -3728,7 +3938,8 @@ output_asm_insn ("vldrd.64\t%q0, [%q1, %2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrdq_gather_base_v2di")) + (set_attr "length" "4")]) ;; ;; [vldrdq_gather_base_z_s vldrdq_gather_base_z_u] @@ -3749,7 +3960,8 @@ output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%q1, %2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrdq_gather_base_v2di")) + (set_attr "length" "8")]) ;; ;; [vldrdq_gather_offset_s vldrdq_gather_offset_u] @@ -3769,7 +3981,8 @@ output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrdq_gather_offset_v2di")) + (set_attr "length" "4")]) ;; ;; [vldrdq_gather_offset_z_s vldrdq_gather_offset_z_u] @@ -3790,7 +4003,8 @@ output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrdq_gather_offset_v2di")) + (set_attr "length" "8")]) ;; ;; [vldrdq_gather_shifted_offset_s vldrdq_gather_shifted_offset_u] @@ -3810,7 +4024,8 @@ output_asm_insn ("vldrd.u64\t%q0, [%m1, %q2, uxtw #3]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrdq_gather_shifted_offset_v2di")) + (set_attr "length" "4")]) ;; ;; [vldrdq_gather_shifted_offset_z_s vldrdq_gather_shifted_offset_z_u] @@ -3831,7 +4046,8 @@ output_asm_insn ("vpst\n\tvldrdt.u64\t%q0, [%m1, %q2, uxtw #3]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrdq_gather_shifted_offset_v2di")) + (set_attr "length" "8")]) ;; ;; [vldrhq_gather_offset_f] @@ -3851,7 +4067,8 @@ output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_gather_offset_fv8hf")) + (set_attr "length" "4")]) ;; ;; [vldrhq_gather_offset_z_f] @@ -3873,7 +4090,8 @@ output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_gather_offset_fv8hf")) + (set_attr "length" "8")]) ;; ;; [vldrhq_gather_shifted_offset_f] @@ -3893,7 +4111,8 @@ output_asm_insn ("vldrh.f16\t%q0, [%m1, %q2, uxtw #1]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_gather_shifted_offset_fv8hf")) + (set_attr "length" "4")]) ;; ;; [vldrhq_gather_shifted_offset_z_f] @@ -3915,7 +4134,8 @@ output_asm_insn ("vpst\n\tvldrht.f16\t%q0, [%m1, %q2, uxtw #1]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrhq_gather_shifted_offset_fv8hf")) + (set_attr "length" "8")]) ;; ;; [vldrwq_gather_base_f] @@ -3935,7 +4155,8 @@ output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_base_fv4sf")) + (set_attr "length" "4")]) ;; ;; [vldrwq_gather_base_z_f] @@ -3956,7 +4177,8 @@ output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%q1, %2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_base_fv4sf")) + (set_attr "length" "8")]) ;; ;; [vldrwq_gather_offset_f] @@ -3976,7 +4198,8 @@ output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_offset_fv4sf")) + (set_attr "length" "4")]) ;; ;; [vldrwq_gather_offset_s vldrwq_gather_offset_u] @@ -3996,7 +4219,8 @@ output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_offset_v4si")) + (set_attr "length" "4")]) ;; ;; [vldrwq_gather_offset_z_f] @@ -4018,7 +4242,8 @@ output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_offset_fv4sf")) + (set_attr "length" "8")]) ;; ;; [vldrwq_gather_offset_z_s vldrwq_gather_offset_z_u] @@ -4040,7 +4265,8 @@ output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_offset_v4si")) + (set_attr "length" "8")]) ;; ;; [vldrwq_gather_shifted_offset_f] @@ -4060,7 +4286,8 @@ output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_shifted_offset_fv4sf")) + (set_attr "length" "4")]) ;; ;; [vldrwq_gather_shifted_offset_s vldrwq_gather_shifted_offset_u] @@ -4080,7 +4307,8 @@ output_asm_insn ("vldrw.u32\t%q0, [%m1, %q2, uxtw #2]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_shifted_offset_v4si")) + (set_attr "length" "4")]) ;; ;; [vldrwq_gather_shifted_offset_z_f] @@ -4102,7 +4330,8 @@ output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_shifted_offset_fv4sf")) + (set_attr "length" "8")]) ;; ;; [vldrwq_gather_shifted_offset_z_s vldrwq_gather_shifted_offset_z_u] @@ -4124,7 +4353,8 @@ output_asm_insn ("vpst\n\tvldrwt.u32\t%q0, [%m1, %q2, uxtw #2]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_shifted_offset_v4si")) + (set_attr "length" "8")]) ;; ;; [vstrhq_f] @@ -4143,7 +4373,8 @@ output_asm_insn ("vstrh.16\t%q1, %E0",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_fv8hf")) + (set_attr "length" "4")]) ;; ;; [vstrhq_p_f] @@ -4164,7 +4395,8 @@ output_asm_insn ("vpst\;vstrht.16\t%q1, %E0",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_fv8hf")) + (set_attr "length" "8")]) ;; ;; [vstrhq_p_s vstrhq_p_u] @@ -4186,7 +4418,8 @@ output_asm_insn ("vpst\;vstrht.\t%q1, %E0",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_")) + (set_attr "length" "8")]) ;; ;; [vstrhq_scatter_offset_p_s vstrhq_scatter_offset_p_u] @@ -4218,7 +4451,8 @@ VSTRHSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrht.\t%q2, [%0, %q1]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_scatter_offset__insn")) + (set_attr "length" "8")]) ;; ;; [vstrhq_scatter_offset_s vstrhq_scatter_offset_u] @@ -4246,7 +4480,8 @@ VSTRHSOQ))] "TARGET_HAVE_MVE" "vstrh.\t%q2, [%0, %q1]" - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_scatter_offset__insn")) + (set_attr "length" "4")]) ;; ;; [vstrhq_scatter_shifted_offset_p_s vstrhq_scatter_shifted_offset_p_u] @@ -4278,7 +4513,8 @@ VSTRHSSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrht.\t%q2, [%0, %q1, uxtw #1]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_scatter_shifted_offset__insn")) + (set_attr "length" "8")]) ;; ;; [vstrhq_scatter_shifted_offset_s vstrhq_scatter_shifted_offset_u] @@ -4307,7 +4543,8 @@ VSTRHSSOQ))] "TARGET_HAVE_MVE" "vstrh.\t%q2, [%0, %q1, uxtw #1]" - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_scatter_shifted_offset__insn")) + (set_attr "length" "4")]) ;; ;; [vstrhq_s, vstrhq_u] @@ -4326,7 +4563,8 @@ output_asm_insn ("vstrh.\t%q1, %E0",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_")) + (set_attr "length" "4")]) ;; ;; [vstrwq_f] @@ -4345,7 +4583,8 @@ output_asm_insn ("vstrw.32\t%q1, %E0",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_fv4sf")) + (set_attr "length" "4")]) ;; ;; [vstrwq_p_f] @@ -4366,7 +4605,8 @@ output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_fv4sf")) + (set_attr "length" "8")]) ;; ;; [vstrwq_p_s vstrwq_p_u] @@ -4387,7 +4627,8 @@ output_asm_insn ("vpst\;vstrwt.32\t%q1, %E0",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_v4si")) + (set_attr "length" "8")]) ;; ;; [vstrwq_s vstrwq_u] @@ -4406,7 +4647,8 @@ output_asm_insn ("vstrw.32\t%q1, %E0",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_v4si")) + (set_attr "length" "4")]) (define_expand "@mve_vst1q_f" [(match_operand: 0 "mve_memory_operand") @@ -4449,7 +4691,8 @@ output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrdq_scatter_base_v2di")) + (set_attr "length" "8")]) ;; ;; [vstrdq_scatter_base_s vstrdq_scatter_base_u] @@ -4471,7 +4714,8 @@ output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrdq_scatter_base_v2di")) + (set_attr "length" "4")]) ;; ;; [vstrdq_scatter_offset_p_s vstrdq_scatter_offset_p_u] @@ -4502,7 +4746,8 @@ VSTRDSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrdt.64\t%q2, [%0, %q1]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrdq_scatter_offset_v2di_insn")) + (set_attr "length" "8")]) ;; ;; [vstrdq_scatter_offset_s vstrdq_scatter_offset_u] @@ -4530,7 +4775,8 @@ VSTRDSOQ))] "TARGET_HAVE_MVE" "vstrd.64\t%q2, [%0, %q1]" - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrdq_scatter_offset_v2di_insn")) + (set_attr "length" "4")]) ;; ;; [vstrdq_scatter_shifted_offset_p_s vstrdq_scatter_shifted_offset_p_u] @@ -4562,7 +4808,8 @@ VSTRDSSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrdt.64\t%q2, [%0, %q1, uxtw #3]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrdq_scatter_shifted_offset_v2di_insn")) + (set_attr "length" "8")]) ;; ;; [vstrdq_scatter_shifted_offset_s vstrdq_scatter_shifted_offset_u] @@ -4591,7 +4838,8 @@ VSTRDSSOQ))] "TARGET_HAVE_MVE" "vstrd.64\t%q2, [%0, %q1, uxtw #3]" - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrdq_scatter_shifted_offset_v2di_insn")) + (set_attr "length" "4")]) ;; ;; [vstrhq_scatter_offset_f] @@ -4619,7 +4867,8 @@ VSTRHQSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vstrh.16\t%q2, [%0, %q1]" - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_scatter_offset_fv8hf_insn")) + (set_attr "length" "4")]) ;; ;; [vstrhq_scatter_offset_p_f] @@ -4650,7 +4899,8 @@ VSTRHQSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vstrht.16\t%q2, [%0, %q1]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_scatter_offset_fv8hf_insn")) + (set_attr "length" "8")]) ;; ;; [vstrhq_scatter_shifted_offset_f] @@ -4678,7 +4928,8 @@ VSTRHQSSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vstrh.16\t%q2, [%0, %q1, uxtw #1]" - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_scatter_shifted_offset_fv8hf_insn")) + (set_attr "length" "4")]) ;; ;; [vstrhq_scatter_shifted_offset_p_f] @@ -4710,7 +4961,8 @@ VSTRHQSSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vstrht.16\t%q2, [%0, %q1, uxtw #1]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrhq_scatter_shifted_offset_fv8hf_insn")) + (set_attr "length" "8")]) ;; ;; [vstrwq_scatter_base_f] @@ -4732,7 +4984,8 @@ output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_base_fv4sf")) + (set_attr "length" "4")]) ;; ;; [vstrwq_scatter_base_p_f] @@ -4755,7 +5008,8 @@ output_asm_insn ("vpst\n\tvstrwt.u32\t%q2, [%q0, %1]",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_base_fv4sf")) + (set_attr "length" "8")]) ;; ;; [vstrwq_scatter_offset_f] @@ -4783,7 +5037,8 @@ VSTRWQSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vstrw.32\t%q2, [%0, %q1]" - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_offset_fv4sf_insn")) + (set_attr "length" "4")]) ;; ;; [vstrwq_scatter_offset_p_f] @@ -4814,7 +5069,8 @@ VSTRWQSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vstrwt.32\t%q2, [%0, %q1]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_offset_fv4sf_insn")) + (set_attr "length" "8")]) ;; ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u] @@ -4845,7 +5101,8 @@ VSTRWSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrwt.32\t%q2, [%0, %q1]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_offset_v4si_insn")) + (set_attr "length" "8")]) ;; ;; [vstrwq_scatter_offset_s vstrwq_scatter_offset_u] @@ -4873,7 +5130,8 @@ VSTRWSOQ))] "TARGET_HAVE_MVE" "vstrw.32\t%q2, [%0, %q1]" - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_offset_v4si_insn")) + (set_attr "length" "4")]) ;; ;; [vstrwq_scatter_shifted_offset_f] @@ -4901,7 +5159,8 @@ VSTRWQSSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vstrw.32\t%q2, [%0, %q1, uxtw #2]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_shifted_offset_fv4sf_insn")) + (set_attr "length" "8")]) ;; ;; [vstrwq_scatter_shifted_offset_p_f] @@ -4933,7 +5192,8 @@ VSTRWQSSO_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_shifted_offset_fv4sf_insn")) + (set_attr "length" "8")]) ;; ;; [vstrwq_scatter_shifted_offset_p_s vstrwq_scatter_shifted_offset_p_u] @@ -4965,7 +5225,8 @@ VSTRWSSOQ))] "TARGET_HAVE_MVE" "vpst\;vstrwt.32\t%q2, [%0, %q1, uxtw #2]" - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_shifted_offset_v4si_insn")) + (set_attr "length" "8")]) ;; ;; [vstrwq_scatter_shifted_offset_s vstrwq_scatter_shifted_offset_u] @@ -4994,7 +5255,8 @@ VSTRWSSOQ))] "TARGET_HAVE_MVE" "vstrw.32\t%q2, [%0, %q1, uxtw #2]" - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_shifted_offset_v4si_insn")) + (set_attr "length" "4")]) ;; ;; [vidupq_n_u]) @@ -5062,7 +5324,8 @@ (match_operand:SI 6 "immediate_operand" "i")))] "TARGET_HAVE_MVE" "vpst\;\tvidupt.u%#\t%q0, %2, %4" - [(set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vidupq_u_insn")) + (set_attr "length""8")]) ;; ;; [vddupq_n_u]) @@ -5130,7 +5393,8 @@ (match_operand:SI 6 "immediate_operand" "i")))] "TARGET_HAVE_MVE" "vpst\;vddupt.u%#\t%q0, %2, %4" - [(set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vddupq_u_insn")) + (set_attr "length""8")]) ;; ;; [vdwdupq_n_u]) @@ -5246,8 +5510,9 @@ ] "TARGET_HAVE_MVE" "vpst\;vdwdupt.u%#\t%q2, %3, %R4, %5" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vdwdupq_wb_u_insn")) + (set_attr "type" "mve_move") + (set_attr "length""8")]) ;; ;; [viwdupq_n_u]) @@ -5363,7 +5628,8 @@ ] "TARGET_HAVE_MVE" "vpst\;\tviwdupt.u%#\t%q2, %3, %R4, %5" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_viwdupq_wb_u_insn")) + (set_attr "type" "mve_move") (set_attr "length""8")]) ;; @@ -5389,7 +5655,8 @@ output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_base_wb_v4si")) + (set_attr "length" "4")]) ;; ;; [vstrwq_scatter_base_wb_p_s vstrwq_scatter_base_wb_p_u] @@ -5415,7 +5682,8 @@ output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_base_wb_v4si")) + (set_attr "length" "8")]) ;; ;; [vstrwq_scatter_base_wb_f] @@ -5440,7 +5708,8 @@ output_asm_insn ("vstrw.u32\t%q2, [%q0, %1]!",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_base_wb_fv4sf")) + (set_attr "length" "4")]) ;; ;; [vstrwq_scatter_base_wb_p_f] @@ -5466,7 +5735,8 @@ output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrwq_scatter_base_wb_fv4sf")) + (set_attr "length" "8")]) ;; ;; [vstrdq_scatter_base_wb_s vstrdq_scatter_base_wb_u] @@ -5491,7 +5761,8 @@ output_asm_insn ("vstrd.u64\t%q2, [%q0, %1]!",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrdq_scatter_base_wb_v2di")) + (set_attr "length" "4")]) ;; ;; [vstrdq_scatter_base_wb_p_s vstrdq_scatter_base_wb_p_u] @@ -5517,7 +5788,8 @@ output_asm_insn ("vpst\;vstrdt.u64\t%q2, [%q0, %1]!",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vstrdq_scatter_base_wb_v2di")) + (set_attr "length" "8")]) (define_expand "mve_vldrwq_gather_base_wb_v4si" [(match_operand:V4SI 0 "s_register_operand") @@ -5569,7 +5841,8 @@ output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_base_wb_v4si_insn")) + (set_attr "length" "4")]) (define_expand "mve_vldrwq_gather_base_wb_z_v4si" [(match_operand:V4SI 0 "s_register_operand") @@ -5625,7 +5898,8 @@ output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_base_wb_v4si_insn")) + (set_attr "length" "8")]) (define_expand "mve_vldrwq_gather_base_wb_fv4sf" [(match_operand:V4SI 0 "s_register_operand") @@ -5677,7 +5951,8 @@ output_asm_insn ("vldrw.u32\t%q0, [%q1, %2]!",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_base_wb_fv4sf_insn")) + (set_attr "length" "4")]) (define_expand "mve_vldrwq_gather_base_wb_z_fv4sf" [(match_operand:V4SI 0 "s_register_operand") @@ -5734,7 +6009,8 @@ output_asm_insn ("vpst\;vldrwt.u32\t%q0, [%q1, %2]!",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrwq_gather_base_wb_fv4sf_insn")) + (set_attr "length" "8")]) (define_expand "mve_vldrdq_gather_base_wb_v2di" [(match_operand:V2DI 0 "s_register_operand") @@ -5787,7 +6063,8 @@ output_asm_insn ("vldrd.64\t%q0, [%q1, %2]!",ops); return ""; } - [(set_attr "length" "4")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrdq_gather_base_wb_v2di_insn")) + (set_attr "length" "4")]) (define_expand "mve_vldrdq_gather_base_wb_z_v2di" [(match_operand:V2DI 0 "s_register_operand") @@ -5826,7 +6103,7 @@ (unspec_volatile:SI [(reg:SI VFPCC_REGNUM)] UNSPEC_GET_FPSCR_NZCVQC))] "TARGET_HAVE_MVE" "vmrs\\t%0, FPSCR_nzcvqc" - [(set_attr "type" "mve_move")]) + [(set_attr "type" "mve_move")]) (define_insn "set_fpscr_nzcvqc" [(set (reg:SI VFPCC_REGNUM) @@ -5834,7 +6111,7 @@ VUNSPEC_SET_FPSCR_NZCVQC))] "TARGET_HAVE_MVE" "vmsr\\tFPSCR_nzcvqc, %0" - [(set_attr "type" "mve_move")]) + [(set_attr "type" "mve_move")]) ;; ;; [vldrdq_gather_base_wb_z_s vldrdq_gather_base_wb_z_u] @@ -5859,7 +6136,8 @@ output_asm_insn ("vpst\;vldrdt.u64\t%q0, [%q1, %2]!",ops); return ""; } - [(set_attr "length" "8")]) + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vldrdq_gather_base_wb_v2di_insn")) + (set_attr "length" "8")]) ;; ;; [vadciq_m_s, vadciq_m_u]) ;; @@ -5876,7 +6154,8 @@ ] "TARGET_HAVE_MVE" "vpst\;vadcit.i32\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vadciq_v4si")) + (set_attr "type" "mve_move") (set_attr "length" "8")]) ;; @@ -5893,7 +6172,8 @@ ] "TARGET_HAVE_MVE" "vadci.i32\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vadciq_v4si")) + (set_attr "type" "mve_move") (set_attr "length" "4")]) ;; @@ -5912,7 +6192,8 @@ ] "TARGET_HAVE_MVE" "vpst\;vadct.i32\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vadcq_v4si")) + (set_attr "type" "mve_move") (set_attr "length" "8")]) ;; @@ -5929,7 +6210,8 @@ ] "TARGET_HAVE_MVE" "vadc.i32\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vadcq_v4si")) + (set_attr "type" "mve_move") (set_attr "length" "4") (set_attr "conds" "set")]) @@ -5949,7 +6231,8 @@ ] "TARGET_HAVE_MVE" "vpst\;vsbcit.i32\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vsbciq_v4si")) + (set_attr "type" "mve_move") (set_attr "length" "8")]) ;; @@ -5966,7 +6249,8 @@ ] "TARGET_HAVE_MVE" "vsbci.i32\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vsbciq_v4si")) + (set_attr "type" "mve_move") (set_attr "length" "4")]) ;; @@ -5985,7 +6269,8 @@ ] "TARGET_HAVE_MVE" "vpst\;vsbct.i32\t%q0, %q2, %q3" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vsbcq_v4si")) + (set_attr "type" "mve_move") (set_attr "length" "8")]) ;; @@ -6002,7 +6287,8 @@ ] "TARGET_HAVE_MVE" "vsbc.i32\t%q0, %q1, %q2" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vsbcq_v4si")) + (set_attr "type" "mve_move") (set_attr "length" "4")]) ;; @@ -6031,7 +6317,7 @@ "vst21.\t{%q0, %q1}, %3", ops); return ""; } - [(set_attr "length" "8")]) + [(set_attr "length" "8")]) ;; ;; [vld2q]) @@ -6059,7 +6345,7 @@ "vld21.\t{%q0, %q1}, %3", ops); return ""; } - [(set_attr "length" "8")]) + [(set_attr "length" "8")]) ;; ;; [vld4q]) @@ -6402,7 +6688,8 @@ ] "TARGET_HAVE_MVE" "vpst\;vshlct\t%q0, %1, %4" - [(set_attr "type" "mve_move") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_vshlcq_")) + (set_attr "type" "mve_move") (set_attr "length" "8")]) ;; CDE instructions on MVE registers. @@ -6414,7 +6701,8 @@ UNSPEC_VCDE))] "TARGET_CDE && TARGET_HAVE_MVE" "vcx1\\tp%c1, %q0, #%c2" - [(set_attr "type" "coproc")] + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_arm_vcx1qv16qi")) + (set_attr "type" "coproc")] ) (define_insn "arm_vcx1qav16qi" @@ -6425,7 +6713,8 @@ UNSPEC_VCDEA))] "TARGET_CDE && TARGET_HAVE_MVE" "vcx1a\\tp%c1, %q0, #%c3" - [(set_attr "type" "coproc")] + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_arm_vcx1qav16qi")) + (set_attr "type" "coproc")] ) (define_insn "arm_vcx2qv16qi" @@ -6436,7 +6725,8 @@ UNSPEC_VCDE))] "TARGET_CDE && TARGET_HAVE_MVE" "vcx2\\tp%c1, %q0, %q2, #%c3" - [(set_attr "type" "coproc")] + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_arm_vcx2qv16qi")) + (set_attr "type" "coproc")] ) (define_insn "arm_vcx2qav16qi" @@ -6448,7 +6738,8 @@ UNSPEC_VCDEA))] "TARGET_CDE && TARGET_HAVE_MVE" "vcx2a\\tp%c1, %q0, %q3, #%c4" - [(set_attr "type" "coproc")] + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_arm_vcx2qav16qi")) + (set_attr "type" "coproc")] ) (define_insn "arm_vcx3qv16qi" @@ -6460,7 +6751,8 @@ UNSPEC_VCDE))] "TARGET_CDE && TARGET_HAVE_MVE" "vcx3\\tp%c1, %q0, %q2, %q3, #%c4" - [(set_attr "type" "coproc")] + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_arm_vcx3qv16qi")) + (set_attr "type" "coproc")] ) (define_insn "arm_vcx3qav16qi" @@ -6473,7 +6765,8 @@ UNSPEC_VCDEA))] "TARGET_CDE && TARGET_HAVE_MVE" "vcx3a\\tp%c1, %q0, %q3, %q4, #%c5" - [(set_attr "type" "coproc")] + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_arm_vcx3qav16qi")) + (set_attr "type" "coproc")] ) (define_insn "arm_vcx1q_p_v16qi" @@ -6485,7 +6778,8 @@ CDE_VCX))] "TARGET_CDE && TARGET_HAVE_MVE" "vpst\;vcx1t\\tp%c1, %q0, #%c3" - [(set_attr "type" "coproc") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_arm_vcx1qv16qi")) + (set_attr "type" "coproc") (set_attr "length" "8")] ) @@ -6499,7 +6793,8 @@ CDE_VCX))] "TARGET_CDE && TARGET_HAVE_MVE" "vpst\;vcx2t\\tp%c1, %q0, %q3, #%c4" - [(set_attr "type" "coproc") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_arm_vcx2qv16qi")) + (set_attr "type" "coproc") (set_attr "length" "8")] ) @@ -6514,11 +6809,12 @@ CDE_VCX))] "TARGET_CDE && TARGET_HAVE_MVE" "vpst\;vcx3t\\tp%c1, %q0, %q3, %q4, #%c5" - [(set_attr "type" "coproc") + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_arm_vcx3qv16qi")) + (set_attr "type" "coproc") (set_attr "length" "8")] ) -(define_insn "*movmisalign_mve_store" +(define_insn "movmisalign_mve_store" [(set (match_operand:MVE_VLD_ST 0 "mve_memory_operand" "=Ux") (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "s_register_operand" " w")] UNSPEC_MISALIGNED_ACCESS))] @@ -6526,11 +6822,12 @@ || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))) && !BYTES_BIG_ENDIAN && unaligned_access" "vstr.\t%q1, %E0" - [(set_attr "type" "mve_store")] + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_movmisalign_mve_store")) + (set_attr "type" "mve_store")] ) -(define_insn "*movmisalign_mve_load" +(define_insn "movmisalign_mve_load" [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w") (unspec:MVE_VLD_ST [(match_operand:MVE_VLD_ST 1 "mve_memory_operand" " Ux")] UNSPEC_MISALIGNED_ACCESS))] @@ -6538,7 +6835,8 @@ || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))) && !BYTES_BIG_ENDIAN && unaligned_access" "vldr.\t%q0, %E1" - [(set_attr "type" "mve_load")] + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_movmisalign_mve_load")) + (set_attr "type" "mve_load")] ) ;; Expander for VxBI moves diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index dac8885..ff1c27a 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -366,7 +366,8 @@ "@ .%#\t%0, %1, %2 * return neon_output_shift_immediate (\"vshl\", 'i', &operands[2], mode, VALID_NEON_QREG_MODE (mode), true);" - [(set_attr "type" "neon_shift_reg, neon_shift_imm")] + [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "type" "neon_shift_reg, neon_shift_imm")] ) (define_expand "vashl3" -- cgit v1.1 From 8594dfed927e4eda3d2b02f801538af04f549679 Mon Sep 17 00:00:00 2001 From: Andre Vieira Date: Wed, 14 Feb 2024 16:46:38 +0000 Subject: arm: Annotate instructions with mve_safe_imp_xlane_pred This patch annotates some MVE across lane instructions with a new attribute. We use this attribute to let the compiler know that these instructions can be safely implicitly predicated when tail predicating if their operands are guaranteed to have zeroed tail predicated lanes. These instructions were selected because having the value 0 in those lanes or 'tail-predicating' those lanes have the same effect. gcc/ChangeLog: * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute. * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator attribute. * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u, vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u, vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u, vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s, vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s, vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u, vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u, vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s, vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s, vmlsldavaxq_s): Added mve_safe_imp_xlane_pred. --- gcc/config/arm/arm.md | 6 ++++++ gcc/config/arm/iterators.md | 8 ++++++++ gcc/config/arm/mve.md | 12 ++++++++++++ 3 files changed, 26 insertions(+) (limited to 'gcc') diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 81290e8..814e871 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -130,6 +130,12 @@ ; encode that it is a predicable instruction. (define_attr "mve_unpredicated_insn" "" (symbol_ref "CODE_FOR_nothing")) +; An attribute used by the loop-doloop pass when determining whether it is +; safe to predicate a MVE instruction, that operates across lanes, and was +; previously not predicated. The pass will still check whether all inputs +; are predicated by the VCTP predication mask. +(define_attr "mve_safe_imp_xlane_pred" "yes,no" (const_string "no")) + ; LENGTH of an instruction (in bytes) (define_attr "length" "" (const_int 4)) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 547d87f..da49bd6 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -869,6 +869,14 @@ (plus "vadd") ]) +(define_int_attr mve_vmaxmin_safe_imp [ + (VMAXVQ_U "yes") + (VMAXVQ_S "no") + (VMAXAVQ_S "yes") + (VMINVQ_U "no") + (VMINVQ_S "no") + (VMINAVQ_S "no")]) + (define_int_attr mve_cmp_op1 [ (VCMPCSQ_M_U "cs") (VCMPEQQ_M_S "eq") (VCMPEQQ_M_U "eq") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 8aa0bde..d7bdcd8 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -393,6 +393,7 @@ "TARGET_HAVE_MVE" ".%#\t%0, %q1" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -529,6 +530,7 @@ "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q1" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -802,6 +804,7 @@ "TARGET_HAVE_MVE" ".%#\t%0, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1014,6 +1017,7 @@ "TARGET_HAVE_MVE" ".%#\t%0, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "") (set_attr "type" "mve_move") ]) @@ -1033,6 +1037,7 @@ "TARGET_HAVE_MVE" ".%#\t%0, %q1, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1219,6 +1224,7 @@ "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1450,6 +1456,7 @@ "TARGET_HAVE_MVE" ".%#\t%Q0, %R0, %q1, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1588,6 +1595,7 @@ "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q1, %q2" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1725,6 +1733,7 @@ "TARGET_HAVE_MVE" ".32\t%Q0, %R0, %q2, %q3" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_v4si")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1742,6 +1751,7 @@ "TARGET_HAVE_MVE" ".%#\t%0, %q2, %q3" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -1952,6 +1962,7 @@ "TARGET_HAVE_MVE" ".%#\t%0, %q2, %q3" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) @@ -2401,6 +2412,7 @@ "TARGET_HAVE_MVE" ".%#\t%Q0, %R0, %q2, %q3" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_q_")) + (set_attr "mve_safe_imp_xlane_pred" "yes") (set_attr "type" "mve_move") ]) -- cgit v1.1 From 8e92b66fdba16faf0d5ace279f1c02cec6a5cc23 Mon Sep 17 00:00:00 2001 From: Andre Vieira Date: Wed, 14 Feb 2024 17:01:11 +0000 Subject: arm: Fix a wrong attribute use and remove unused unspecs and iterators This patch fixes the erroneous use of a mode attribute without a mode iterator in the pattern and removes unused unspecs and iterators. gcc/ChangeLog: * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U, VMLALDAVAXQ_U cases. (VMLALDAVXQ): Remove iterator. (VMLALDAVXQ_P): Likewise. (VMLALDAVAXQ): Likewise. * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of mode iterator attribute with V4BI mode. * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U, VMLALDAVAXQ_U): Remove unused unspecs. --- gcc/config/arm/iterators.md | 9 +++------ gcc/config/arm/mve.md | 2 +- gcc/config/arm/unspecs.md | 3 --- 3 files changed, 4 insertions(+), 10 deletions(-) (limited to 'gcc') diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index da49bd6..8d066fc 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -2369,7 +2369,7 @@ (VSUBQ_S "s") (VSUBQ_U "u") (VADDVAQ_S "s") (VADDVAQ_U "u") (VADDLVAQ_S "s") (VADDLVAQ_U "u") (VBICQ_N_S "s") (VBICQ_N_U "u") (VMLALDAVQ_U "u") - (VMLALDAVQ_S "s") (VMLALDAVXQ_U "u") (VMLALDAVXQ_S "s") + (VMLALDAVQ_S "s") (VMLALDAVXQ_S "s") (VMOVNBQ_U "u") (VMOVNBQ_S "s") (VMOVNTQ_U "u") (VMOVNTQ_S "s") (VORRQ_N_S "s") (VORRQ_N_U "u") (VQMOVNBQ_U "u") (VQMOVNBQ_S "s") (VQMOVNTQ_S "s") @@ -2411,8 +2411,8 @@ (VREV16Q_M_S "s") (VREV16Q_M_U "u") (VQRSHRNTQ_N_U "u") (VMOVNTQ_M_U "u") (VMOVLBQ_M_U "u") (VMLALDAVAQ_U "u") (VQSHRNBQ_N_U "u") (VSHRNBQ_N_U "u") - (VRSHRNBQ_N_U "u") (VMLALDAVXQ_P_U "u") - (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VMLALDAVAXQ_U "u") + (VRSHRNBQ_N_U "u") + (VMVNQ_M_N_U "u") (VQSHRNTQ_N_U "u") (VQMOVNTQ_M_U "u") (VSHRNTQ_N_U "u") (VCVTMQ_M_S "s") (VCVTMQ_M_U "u") (VCVTNQ_M_S "s") (VCVTNQ_M_U "u") (VCVTPQ_M_S "s") (VCVTPQ_M_U "u") (VADDLVAQ_P_S "s") @@ -2761,7 +2761,6 @@ (define_int_iterator VADDLVAQ [VADDLVAQ_S VADDLVAQ_U]) (define_int_iterator VBICQ_N [VBICQ_N_S VBICQ_N_U]) (define_int_iterator VMLALDAVQ [VMLALDAVQ_U VMLALDAVQ_S]) -(define_int_iterator VMLALDAVXQ [VMLALDAVXQ_U VMLALDAVXQ_S]) (define_int_iterator VMOVNBQ [VMOVNBQ_U VMOVNBQ_S]) (define_int_iterator VMOVNTQ [VMOVNTQ_S VMOVNTQ_U]) (define_int_iterator VORRQ_N [VORRQ_N_U VORRQ_N_S]) @@ -2816,11 +2815,9 @@ (define_int_iterator VQSHRNBQ_N [VQSHRNBQ_N_U VQSHRNBQ_N_S]) (define_int_iterator VSHRNBQ_N [VSHRNBQ_N_U VSHRNBQ_N_S]) (define_int_iterator VRSHRNBQ_N [VRSHRNBQ_N_S VRSHRNBQ_N_U]) -(define_int_iterator VMLALDAVXQ_P [VMLALDAVXQ_P_U VMLALDAVXQ_P_S]) (define_int_iterator VQMOVNTQ_M [VQMOVNTQ_M_U VQMOVNTQ_M_S]) (define_int_iterator VMVNQ_M_N [VMVNQ_M_N_U VMVNQ_M_N_S]) (define_int_iterator VQSHRNTQ_N [VQSHRNTQ_N_U VQSHRNTQ_N_S]) -(define_int_iterator VMLALDAVAXQ [VMLALDAVAXQ_S VMLALDAVAXQ_U]) (define_int_iterator VSHRNTQ_N [VSHRNTQ_N_S VSHRNTQ_N_U]) (define_int_iterator VCVTMQ_M [VCVTMQ_M_S VCVTMQ_M_U]) (define_int_iterator VCVTNQ_M [VCVTNQ_M_S VCVTNQ_M_U]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index d7bdcd8..9fe5129 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -4605,7 +4605,7 @@ [(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux") (unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w") - (match_operand: 2 "vpr_register_operand" "Up") + (match_operand:V4BI 2 "vpr_register_operand" "Up") (match_dup 0)] VSTRWQ_F))] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index b9db306..46ac8b3 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -717,7 +717,6 @@ VCVTBQ_F16_F32 VCVTTQ_F16_F32 VMLALDAVQ_U - VMLALDAVXQ_U VMLALDAVXQ_S VMLALDAVQ_S VMLSLDAVQ_S @@ -934,7 +933,6 @@ VSHRNBQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U - VMLALDAVXQ_P_U VMLALDAVXQ_P_S VQMOVNTQ_M_U VQMOVNTQ_M_S @@ -943,7 +941,6 @@ VQSHRNTQ_N_U VQSHRNTQ_N_S VMLALDAVAXQ_S - VMLALDAVAXQ_U VSHRNTQ_N_S VSHRNTQ_N_U VCVTBQ_M_F16_F32 -- cgit v1.1 From 901e7bdab70e2275723ac31dacbbce0b6f68f4f4 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 4 Mar 2024 19:23:02 +0100 Subject: combine: Fix recent WORD_REGISTER_OPERATIONS check [PR113010] On Mon, Mar 04, 2024 at 05:18:39PM +0100, Rainer Orth wrote: > unfortunately, the patch broke Solaris/SPARC bootstrap > (sparc-sun-solaris2.11): > > .../gcc/combine.cc: In function 'rtx_code simplify_comparison(rtx_code, rtx_def**, rtx_def**)': > .../gcc/combine.cc:12101:25: error: '*(unsigned int*)((char*)&inner_mode + offsetof(scalar_int_mode, scalar_int_mode::m_mode))' may be used uninitialized [-Werror=maybe-uninitialized] > 12101 | scalar_int_mode mode, inner_mode, tmode; > | ^~~~~~~~~~ I don't see how it could ever work properly, inner_mode in that spot is just uninitialized. I think we shouldn't worry about paradoxical subregs of non-scalar_int_mode REGs/MEMs and for the scalar_int_mode ones should initialize inner_mode before we use it. Another option would be to use maybe_lt (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))), BITS_PER_WORD) and load_extend_op (GET_MODE (SUBREG_REG (op0))) == ZERO_EXTEND, or set machine_mode smode = GET_MODE (SUBREG_REG (op0)); and use it in those two spots. 2024-03-04 Jakub Jelinek PR rtl-optimization/113010 * combine.cc (simplify_comparison): Guard the WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG and initialize inner_mode. --- gcc/combine.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'gcc') diff --git a/gcc/combine.cc b/gcc/combine.cc index b09200d..a4479f8 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -12554,6 +12554,8 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) if (paradoxical_subreg_p (op0)) { if (WORD_REGISTER_OPERATIONS + && is_a (GET_MODE (SUBREG_REG (op0)), + &inner_mode) && GET_MODE_PRECISION (inner_mode) < BITS_PER_WORD /* On WORD_REGISTER_OPERATIONS targets the bits beyond sub_mode aren't considered undefined, -- cgit v1.1 From aadb311c1a3712a1360a252ae21cf7f375959b5c Mon Sep 17 00:00:00 2001 From: Joseph Myers Date: Mon, 4 Mar 2024 19:06:09 +0000 Subject: Update gcc sv.po * sv.po: Update. --- gcc/po/sv.po | 296 ++++++++++++++++++++++++++++++----------------------------- 1 file changed, 149 insertions(+), 147 deletions(-) (limited to 'gcc') diff --git a/gcc/po/sv.po b/gcc/po/sv.po index ff07a75..f24eb1b 100644 --- a/gcc/po/sv.po +++ b/gcc/po/sv.po @@ -32,7 +32,7 @@ msgstr "" "Project-Id-Version: gcc 14.1-b20240218\n" "Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n" "POT-Creation-Date: 2024-02-16 21:35+0000\n" -"PO-Revision-Date: 2024-02-25 10:21+0100\n" +"PO-Revision-Date: 2024-03-03 17:38+0100\n" "Last-Translator: Göran Uddeborg \n" "Language-Team: Swedish \n" "Language: sv\n" @@ -28578,37 +28578,37 @@ msgstr "ej stödd konstant adress:" #: ipa-strub.cc:684 #, gcc-internal-format msgid "%qD is not eligible for % because %<-fsplit-stack%> is enabled" -msgstr "%qD är inte berättigat till % för att %<-fsplit-stack%> är aktiverat" +msgstr "%qD är inte berättigat till % på grund av att %<-fsplit-stack%> är aktiverat" #: ipa-strub.cc:697 #, gcc-internal-format msgid "%qD is not eligible for % because of attribute %" -msgstr "" +msgstr "%qD är inte berättigat till % på grund av attriutet %" #: ipa-strub.cc:712 #, gcc-internal-format msgid "%qD is not eligible for % because of attribute %" -msgstr "" +msgstr "%qD är inte berättigat till % på grund av attributet %" #: ipa-strub.cc:846 #, gcc-internal-format msgid "%qD is not eligible for internal % because of attribute %" -msgstr "" +msgstr "%qD är inte berättigat till internt % på grund av attributet %" #: ipa-strub.cc:870 #, gcc-internal-format msgid "%qD is not eligible for internal % because it calls %qD" -msgstr "" +msgstr "%qD är inte berättigat till internt % på grund av att det anropar %qD" #: ipa-strub.cc:884 #, gcc-internal-format msgid "%qD is not eligible for internal % because it contains a non-local goto target" -msgstr "" +msgstr "%qD är inte berättigat till internt % på grund av att det innehåller ett icke-lokalt goto-mål" #: ipa-strub.cc:897 #, gcc-internal-format msgid "%qD is not eligible for internal % because the address of a local label escapes" -msgstr "" +msgstr "%qD är inte berättigat till internt % på grund av att det är adressen till en lokal etikett smiter" #: ipa-strub.cc:936 #, fuzzy, gcc-internal-format @@ -28625,37 +28625,37 @@ msgstr "för många argument för formatsträng" #: ipa-strub.cc:1227 #, gcc-internal-format msgid "%qD requires %, but no viable % mode was found" -msgstr "" +msgstr "%qD kräver %, men inget möjligt %-läge finns" #: ipa-strub.cc:1323 #, gcc-internal-format msgid "% mode %qE selected for %qD, when %qE was requested" -msgstr "" +msgstr "%-läget %qE valt till %qD, när %qE begärdes" #: ipa-strub.cc:1332 #, gcc-internal-format msgid "the incompatible selection was determined by ultimate alias target %qD" -msgstr "" +msgstr "det inkompatibla valet avgjordes av det slutliga aliasmålet %qD" #: ipa-strub.cc:1679 #, gcc-internal-format msgid "indirect non-% call in % context %qD" -msgstr "" +msgstr "indirekt icke-%-anrop i %-sammanhanget %qD" #: ipa-strub.cc:1698 #, gcc-internal-format msgid "calling % % %qD in non-% context %qD" -msgstr "" +msgstr "anropar % % %qD i icke-%-sammanhanget %qD" #: ipa-strub.cc:1708 #, gcc-internal-format msgid "calling non-% %qD in % context %qD" -msgstr "" +msgstr "anropar icke-% %qD i %-sammanhanget %qD" #: ipa-strub.cc:1712 #, gcc-internal-format msgid "calling %qD using non-% type %qT in % context %qD" -msgstr "" +msgstr "anropar %qD med icke-%-typen %qT i %-sammanhanget %qD" #: ipa-strub.cc:2834 #, fuzzy, gcc-internal-format @@ -29747,12 +29747,12 @@ msgstr "sektionsankare måste vara avaktiverade när ordningsändring på toppni #: opts.cc:1105 #, gcc-internal-format msgid "%<-ftrivial-auto-var-init=zero%> is not enabled by %<-fhardened%> because it was specified on the command line" -msgstr "" +msgstr "%<-ftrivial-auto-var-init=zero%> aktiveras inte av %<-fhardened%> eftersom det angavs på kommandoraden" #: opts.cc:1155 #, gcc-internal-format msgid "%<-fstack-protector-strong%> is not enabled by %<-fhardened%> because it was specified on the command line" -msgstr "" +msgstr "%<-fstack-protector-strong%> aktiveras inte av %<-fhardened%> eftersom det angavs på kommandoraden" #: opts.cc:1200 #, gcc-internal-format @@ -31069,7 +31069,7 @@ msgstr "%<-fstack-clash-protection%> stödjs inte på mål där stacken växer f #: toplev.cc:1598 #, gcc-internal-format msgid "%<-fstack-clash-protection%> is not enabled by %<-fhardened%> because %<-fstack-check%> was specified on the command line" -msgstr "" +msgstr "%<-fstack-clash-protection%> aktiveras inte av %<-fhardened%> eftersom %<-fstack-check%> specificerades på" #: toplev.cc:1608 #, gcc-internal-format @@ -31839,7 +31839,7 @@ msgstr "extra klammergrupp vid slutet av initierare" #: tree-cfg.cc:5720 #, gcc-internal-format msgid "probability of edge from entry block not initialized" -msgstr "" +msgstr "sannolikheten för bågen från ingångsblocket är inte initierad" #: tree-cfg.cc:5735 #, fuzzy, gcc-internal-format, gfc-internal-format @@ -33433,12 +33433,12 @@ msgstr "attributet %qE har ingen effekt på enhetslokala funktioner" #: c-family/c-attribs.cc:1921 c-family/c-attribs.cc:3492 #, gcc-internal-format msgid "%qE attribute ignored because %qD is not a variable" -msgstr "attributet %qE ignorerat för att %qD inte är en variabel" +msgstr "attributet %qE ignorerat eftersom %qD inte är en variabel" #: c-family/c-attribs.cc:1927 #, gcc-internal-format msgid "%qE attribute ignored because %qD is not a local variable" -msgstr "attributet %qE ignorerat för att %qD inte är en lokal variabel" +msgstr "attributet %qE ignorerat eftersom %qD inte är en lokal variabel" #: c-family/c-attribs.cc:1952 config/i386/i386-options.cc:4154 #, gcc-internal-format @@ -33579,7 +33579,7 @@ msgstr "minnesjustering kan inte anges för %q+D" #: c-family/c-attribs.cc:2685 #, gcc-internal-format msgid "ignoring attribute %<%E (%u)%> because it conflicts with attribute %<%E (%u)%>" -msgstr "ignorerar attributet %<%E (%u)%> för att det står i konflikt med attributet %<%E (%u)%>" +msgstr "ignorerar attributet %<%E (%u)%> eftersom det står i konflikt med attributet %<%E (%u)%>" #: c-family/c-attribs.cc:2730 #, gcc-internal-format @@ -33756,7 +33756,7 @@ msgstr "attributet %qE ignorerat typer som inte är klasser" #: c-family/c-attribs.cc:3403 jit/dummy-frontend.cc:592 #, gcc-internal-format msgid "%qE attribute ignored because %qT is already defined" -msgstr "attributet %qE ignorerat för att %qT redan är definierat" +msgstr "attributet %qE ignorerat eftersom %qT redan är definierat" #: c-family/c-attribs.cc:3416 jit/dummy-frontend.cc:605 #, gcc-internal-format @@ -33787,7 +33787,7 @@ msgstr "%qD deklarerades %qs vilket medför standardsynlighet" #: c-family/c-attribs.cc:3500 #, gcc-internal-format msgid "%qE attribute ignored because %qD does not have thread storage duration" -msgstr "attributet %qE ignorerat för att %qD inte har trådlagringsvaraktighet" +msgstr "attributet %qE ignorerat eftersom %qD inte har trådlagringsvaraktighet" #: c-family/c-attribs.cc:3522 #, gcc-internal-format @@ -35718,10 +35718,12 @@ msgstr "samma slingiterationsvariabler %qD använda i flera associerade slingor" msgid "two different outer iteration variables %qD and %qD used in a single loop" msgstr "två olika yttre iterationsvariabler %qD och %qD använda i en enda slinga" +# %s blir en oöversättbar engelsk text +# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114112 #: c-family/c-omp.cc:1810 #, gcc-internal-format msgid "variable %qD used %s is bound in intervening code" -msgstr "" +msgstr "variabeln %qD använd %s är bunden i mellanliggande kod" #: c-family/c-omp.cc:2409 #, gcc-internal-format @@ -35782,7 +35784,7 @@ msgstr "föråldrad flagga %<-I-%> använd, använd %<-iquote%> istället" #: c-family/c-opts.cc:373 #, gcc-internal-format msgid "%<-fdeps-format=%> unknown format %<%s%>" -msgstr "" +msgstr "%<-fdeps-format=%> okänt format %<%s%>" #: c-family/c-opts.cc:455 #, gcc-internal-format @@ -35857,7 +35859,7 @@ msgstr "externa TLS-initieringsfunktioner stödjs inte på denna målarkitektur" #: c-family/c-opts.cc:1149 #, gcc-internal-format msgid "%<-fconcepts-ts%> is deprecated and will be removed in GCC 15; please convert your code to C++20 concepts" -msgstr "" +msgstr "%<-fconcepts-ts%> undanbedes och kommer tas bort i GCC 15; konvertera din kod till C++20-koncept" #: c-family/c-opts.cc:1158 #, gcc-internal-format @@ -35882,7 +35884,7 @@ msgstr "när beroendefil %s öppnades: %m" #: c-family/c-opts.cc:1381 #, gcc-internal-format msgid "%<-MF%> and %<-fdeps-file=%> cannot share an output file %s: %m" -msgstr "" +msgstr "%<-MF%> och %<-fdeps-file=%> kan inte dela en utdatafil %s: %m" #: c-family/c-opts.cc:1391 #, gcc-internal-format @@ -35917,17 +35919,17 @@ msgstr "%<-fdirectives-only%> är inkompatibel med %<-traditional%>" #: c-family/c-opts.cc:1634 #, gcc-internal-format msgid "%<_FORTIFY_SOURCE%> is not enabled by %<-fhardened%> because optimizations are turned off" -msgstr "" +msgstr "%<_FORTIFY_SOURCE%> aktiveras inte av %<-fhardened%> eftersom optimeringar är avslagna" #: c-family/c-opts.cc:1638 #, gcc-internal-format msgid "%<_FORTIFY_SOURCE%> is not enabled by %<-fhardened%> because it was specified in %<-D%> or %<-U%>" -msgstr "" +msgstr "%<_FORTIFY_SOURCE%> aktiveras inte av %<-fhardened%> eftersom det angavs av %<-D%> eller %<-U%>" #: c-family/c-opts.cc:1644 #, gcc-internal-format msgid "%<_GLIBCXX_ASSERTIONS%> is not enabled by %<-fhardened%> because it was specified in %<-D%> or %<-U%>" -msgstr "" +msgstr "%<_GLIBCXX_ASSERTIONS%> aktiveras inte av %<-fhardened%> eftersom det angavs av %<-D%> eller %<-U%>" #: c-family/c-opts.cc:1768 #, gcc-internal-format @@ -37030,7 +37032,7 @@ msgstr "avbrottshanteringrutiner kan endast ha ett pekarargument och ett valfrit #: c-family/c-warn.cc:2293 #, gcc-internal-format msgid "earlier argument should specify number of elements, later size of each element" -msgstr "" +msgstr "tidigare argument skulle ange antalet element, senare storlek på varje element" #: c-family/c-warn.cc:2332 #, fuzzy, gcc-internal-format @@ -37525,7 +37527,7 @@ msgstr "%<-march=%s%>: utökningen %qs förekommer mer än en gång." #: common/config/riscv/riscv-common.cc:692 #, gcc-internal-format msgid "%<-march=%s%>: extension %qs starts with 's' but is unsupported standard supervisor extension" -msgstr "" +msgstr "%<-march=%s%>: utvidgningen %qs börjar med ”s” men är en standardövervakarutvidgning som inte stöjds" #: common/config/riscv/riscv-common.cc:700 #, fuzzy, gcc-internal-format @@ -37976,7 +37978,7 @@ msgstr "argument måste vara en 16-bitars konstant omedelbar" #: config/aarch64/aarch64-builtins.cc:2700 #, gcc-internal-format msgid "128-bit system register support requires the % extension" -msgstr "" +msgstr "128-bitars systemregisterstöd kräver utvidgningen %" #: config/aarch64/aarch64-builtins.cc:2715 #, fuzzy, gcc-internal-format @@ -38053,17 +38055,17 @@ msgstr "ACLE-funktionen %qD är inkompatibel med användningen av %qs" #: config/aarch64/aarch64-sve-builtins.cc:1112 #, gcc-internal-format msgid "ACLE function %qD cannot be called when SME streaming mode is enabled" -msgstr "" +msgstr "ACLE-funktionen %qD kan inte anropas när SME-strömningsläget är aktiverat" #: config/aarch64/aarch64-sve-builtins.cc:1119 #, gcc-internal-format msgid "ACLE function %qD can only be called when SME streaming mode is enabled" -msgstr "" +msgstr "ACLE-funktionen %qD kan endast anropas när SME-strömningsläget är aktiverat" #: config/aarch64/aarch64-sve-builtins.cc:1126 #, gcc-internal-format msgid "ACLE function %qD can only be called from a function that has %qs state" -msgstr "" +msgstr "ACLE-funktionen %qD kan endast anropas från en funktion som har tillståndet %qs" #: config/aarch64/aarch64-sve-builtins.cc:1154 #: config/arm/arm-mve-builtins.cc:571 @@ -38131,7 +38133,7 @@ msgstr "skickar %qT istället för det förväntade %qT som argument %d till %qE #: config/aarch64/aarch64-sve-builtins.cc:1777 #, gcc-internal-format msgid "passing mismatched tuple types %qT and %qT to arguments %d and %d of %qE" -msgstr "" +msgstr "skickar tupeltyperna %qT och %qT som inte stämmer överens till argument %d och %d till %qE" #: config/aarch64/aarch64-sve-builtins.cc:1788 #: config/arm/arm-mve-builtins.cc:1104 @@ -38227,12 +38229,12 @@ msgstr "skickar %qT som argument %d till %qE, vilken förväntar sig en vektor a #: config/aarch64/aarch64-sve-builtins.cc:2227 #, gcc-internal-format msgid "operations on multiple vectors must be predicated by %qs rather than %qs" -msgstr "" +msgstr "operationer på multipla vektorer måste föregås av %qs istället för %qs" #: config/aarch64/aarch64-sve-builtins.cc:2230 #, gcc-internal-format msgid "operations on single vectors must be predicated by %qs rather than %qs" -msgstr "" +msgstr "operationer på enstaka vektorer måste föregås av %qs istället för %qs" #: config/aarch64/aarch64-sve-builtins.cc:2246 #: config/arm/arm-mve-builtins.cc:1248 @@ -38544,7 +38546,7 @@ msgstr "attributet %qE kan inte användas på en SVE-funktionstyp" #: config/aarch64/aarch64.cc:754 #, gcc-internal-format msgid "cannot create a new %qs scope since %qs is shared with callers" -msgstr "" +msgstr "kan inte skapa en ny räckvidd %qs eftersom %qs delas med sin anropare" #: config/aarch64/aarch64.cc:770 #, fuzzy, gcc-internal-format @@ -38644,22 +38646,22 @@ msgstr "ACLE-funktionen %qD behöver ISA-utökningen %qs" #: config/aarch64/aarch64.cc:11089 config/aarch64/aarch64.cc:11093 #, gcc-internal-format msgid "call to a function that shares %qs state from a function that has no %qs state" -msgstr "" +msgstr "anrop av en funktion som delar %qs-tillstånd från en funktion som inte har något %qs-tillstånd" #: config/aarch64/aarch64.cc:11096 #, gcc-internal-format msgid "call to a function that shares SME state from a function that has no SME state" -msgstr "" +msgstr "anrop av en funktion som delar SME-tillstånd från en funktion som inte har något SME-tillstånd" #: config/aarch64/aarch64.cc:11154 #, gcc-internal-format msgid "call to a function that shares state other than %qs from a function that has %qs state" -msgstr "" +msgstr "anrop av en funktion som delar andra tillstånd än %qs från en funktion som inte har något %qs-tillstånd" #: config/aarch64/aarch64.cc:11156 #, gcc-internal-format msgid "use %<__arm_preserves(\"za\")%> if the callee preserves ZA" -msgstr "" +msgstr "använd %<__arm_preserves(\"za\")%> om den anropade bevarar ZA" #: config/aarch64/aarch64.cc:17859 #, gcc-internal-format @@ -39030,12 +39032,12 @@ msgstr "%qD definierades här" #: config/aarch64/aarch64.cc:29263 #, gcc-internal-format msgid "non-local gotos in functions with SME state" -msgstr "" +msgstr "icke-lokala goto i en funktion med SME-tillstånd" #: config/aarch64/aarch64.cc:29558 #, gcc-internal-format msgid "catching non-call exceptions in functions with SME state" -msgstr "" +msgstr "fångar ett icke-lokalt undantag i funktioner med SME-tillstånd" #: config/alpha/alpha.cc:420 #, gcc-internal-format @@ -39394,7 +39396,7 @@ msgstr "ogiltigt argument %<%s%> till %<-mharden-sls=%>" #: config/arm/aarch-common.cc:778 #, gcc-internal-format msgid "argument %<%s%> can only appear alone in %<%s%>" -msgstr "" +msgstr "argumentet %<%s%> ken endast förekomma ensamt i %<%s%>" #: config/arm/arm-builtins.cc:3125 #, gcc-internal-format, gfc-internal-format @@ -40944,22 +40946,22 @@ msgstr "% bör undvikas. Använd istället det som pa #: config/i386/i386-options.cc:2104 #, gcc-internal-format msgid "%<-mtune=knl%> support will be removed in GCC 15" -msgstr "" +msgstr "stödet för %<-mtune=knl%> kommer tas bort i GCC 15" #: config/i386/i386-options.cc:2105 #, gcc-internal-format msgid "% support will be removed in GCC 15" -msgstr "" +msgstr "stödet för % kommer tas bort i GCC 15" #: config/i386/i386-options.cc:2110 #, gcc-internal-format msgid "%<-mtune=knm%> support will be removed in GCC 15" -msgstr "" +msgstr "stödet för %<-mtune=knm%> kommer tas bort i GCC 15" #: config/i386/i386-options.cc:2111 #, gcc-internal-format msgid "% support will be removed in GCC 15" -msgstr "" +msgstr "stödet för % kommer tas bort i GCC 15" #. rep; movq isn't available in 32-bit code. #: config/i386/i386-options.cc:2138 @@ -41017,7 +41019,7 @@ msgstr "%<-mabi=%s%> stödjs inte med %<-fsanitize=thread%>" #: config/i386/i386-options.cc:2196 #, gcc-internal-format msgid "%<-mlam=u48%> is not compatible with Hardware-assisted AddressSanitizer, override to %<-mlam=u57%>" -msgstr "" +msgstr "%<-mlam=u48%> är inte kompatibelt med hårdvaruassisterad AddressSanitizer, åsidosätt till %<-mlam=u57%>" #: config/i386/i386-options.cc:2216 config/i386/i386-options.cc:2225 #: config/i386/i386-options.cc:2237 config/i386/i386-options.cc:2248 @@ -41073,22 +41075,22 @@ msgstr "CPU:n du valde stödjer inte instruktionsuppsättningen x86-64" #: config/i386/i386-options.cc:2327 #, gcc-internal-format msgid "%<-march=knl%> support will be removed in GCC 15" -msgstr "" +msgstr "stödet för %<-march=knl%> kommer tas bort i GCC 15" #: config/i386/i386-options.cc:2328 #, gcc-internal-format msgid "% support will be removed in GCC 15" -msgstr "" +msgstr "stödet för % kommer tas bort i GCC 15" #: config/i386/i386-options.cc:2333 #, gcc-internal-format msgid "%<-march=knm%> support will be removed in GCC 15" -msgstr "" +msgstr "stödet för %<-march=knm%> kommer tas bort i GCC 15" #: config/i386/i386-options.cc:2334 #, gcc-internal-format msgid "% support will be removed in GCC 15" -msgstr "" +msgstr "stödet för % kommer tas bort i GCC 15" #: config/i386/i386-options.cc:2411 #, gcc-internal-format @@ -41183,7 +41185,7 @@ msgstr "% ignoreras i 64-bitsläge" #: config/i386/i386-options.cc:2676 #, gcc-internal-format msgid "%<-mno-evex512%> or %<-mno-avx512XXX%> cannot disable AVX10 instructions when AVX10.1-512 is available" -msgstr "" +msgstr "%<-mno-evex512%> eller %<-mno-avx512XXX%> kan inte avaktivera AVX10-instruktioner när AVX10.1-512 är tillgängligt" #. We should not emit 512 bit instructions under AVX10.1-256 #. when EVEX512 is enabled w/o any AVX512 features enabled. @@ -41191,22 +41193,22 @@ msgstr "" #: config/i386/i386-options.cc:2690 #, gcc-internal-format msgid "Using %<-mevex512%> without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" -msgstr "" +msgstr "Att använda %<-mevex512%> utan några AVX512-funktioner aktiverade tillsammans med endast AVX10.1 kommer inte aktivera några AVX512- eller AVX10.1-512-funktioner, använder 256 som maximal vektorstorlek" #: config/i386/i386-options.cc:2697 config/i386/i386-options.cc:2703 #, gcc-internal-format msgid "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" -msgstr "" +msgstr "Vektorstorleken står i konflikt mellan AVX10.1 och AVX512, använder 512 som maximal vektorstorlek" #: config/i386/i386-options.cc:2711 #, gcc-internal-format msgid "%<-mno-avx512XXX%> cannot disable AVX10 instructions when AVX10 is available" -msgstr "" +msgstr "%<-mno-avx512XXX%> kan inte avaktivera AVX10-instruktioner när AVX10 är tillgängligt" #: config/i386/i386-options.cc:2721 #, gcc-internal-format msgid "%<-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512%> cannot disable AVX512 instructions when %<-mavx512XXX%>" -msgstr "" +msgstr "%<-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512%> kan inte avaktivera AVX512-instruktioner när %<-mavx512XXX%>" #: config/i386/i386-options.cc:2776 #, gcc-internal-format @@ -41311,7 +41313,7 @@ msgstr "%qs är inte ett giltigt basregister i %<-mstack-protector-guard-reg=%>" #: config/i386/i386-options.cc:3245 #, gcc-internal-format msgid "%<-fcf-protection=full%> is not enabled by %<-fhardened%> because it was specified on the command line" -msgstr "" +msgstr "%<-fcf-protection=full%> är inte aktiverat av %<-fhardened%> eftersom det angavs på kommandoraden" #: config/i386/i386-options.cc:3254 #, gcc-internal-format @@ -41812,17 +41814,17 @@ msgstr "okänd FPU-typ %<0x%x%>, %qs misslyckades" #: config/loongarch/loongarch-cpu.cc:177 #, gcc-internal-format msgid "floating-point unit %qs differs from PRID preset %qs" -msgstr "" +msgstr "flyttalsenheten %qs skiler från PRID-förinställningen %qs" #: config/loongarch/loongarch-cpu.cc:201 #, gcc-internal-format msgid "unknown SIMD extension (%qs disabled while %qs is enabled), disabling SIMD" -msgstr "" +msgstr "okänd SIMD-utvidgning (%qs avaktiverat medan %qs är aktiverat), avaktiverar SIMD" #: config/loongarch/loongarch-cpu.cc:239 #, gcc-internal-format msgid "detected base architecture %qs, but some of its features are not detected; the detected base architecture may be unreliable, only detected features will be enabled" -msgstr "" +msgstr "detekterade basarkitekturen %qs, men några av dess funktioner detekterades inte; den detekterade basarkitekturen kan vara opålitlig, endast detekterade funktioner kommer aktiveras" #: config/loongarch/loongarch-opts.cc:225 #, gcc-internal-format @@ -41843,12 +41845,12 @@ msgstr "%qs fungerar inte med en korskompilator" #: config/loongarch/loongarch-opts.cc:365 #, gcc-internal-format msgid "enabing %qs promotes %<%s%s%> to %<%s%s%>" -msgstr "" +msgstr "aktivering av %qs befordrar %<%s%s%> till %<%s%s%>" #: config/loongarch/loongarch-opts.cc:377 #, gcc-internal-format msgid "%qs is disabled by %<-m%s%>, because it requires %<%s%s%>" -msgstr "" +msgstr "%qs avaktiveras av %<-m%s%> eftersom det kräver %<%s%s%>" #: config/loongarch/loongarch-opts.cc:389 #, fuzzy, gcc-internal-format @@ -43236,27 +43238,27 @@ msgstr "okänd %<#pragma riscv intrinsic%>-flagga %qs" #: config/riscv/riscv-target-attr.cc:120 #, gcc-internal-format msgid "unexpected arch for % attribute: must start with + or rv" -msgstr "" +msgstr "oväntad arkitektur till attributet %: måste börja med + elller rv" #: config/riscv/riscv-target-attr.cc:132 #, gcc-internal-format msgid "unexpected arch for % attribute: bad string found %<%s%>" -msgstr "" +msgstr "oväntat arkitektur till attributet %: felaktig sträng funnen %<%s%>" #: config/riscv/riscv-target-attr.cc:156 #, gcc-internal-format msgid "% attribute: arch appears more than once" -msgstr "" +msgstr "attributet %: arkitekturen förekommer mer än en gång" #: config/riscv/riscv-target-attr.cc:167 #, gcc-internal-format msgid "% attribute: cpu appears more than once" -msgstr "" +msgstr "attributet %: cpu:n förekommer mer än en gång" #: config/riscv/riscv-target-attr.cc:174 #, gcc-internal-format msgid "% attribute: unknown CPU %qs" -msgstr "" +msgstr "attributet %: okänd CPU %qs" #: config/riscv/riscv-target-attr.cc:195 #, fuzzy, gcc-internal-format @@ -43267,7 +43269,7 @@ msgstr "målattribut stödjs inte på denna maskin" #: config/riscv/riscv-target-attr.cc:201 #, gcc-internal-format msgid "% attribute: unknown TUNE %qs" -msgstr "" +msgstr "attributet %: okänd TUNE %qs" #: config/riscv/riscv-target-attr.cc:240 #, fuzzy, gcc-internal-format @@ -43394,7 +43396,7 @@ msgstr "%<-mdiv%> kräver %<-march%> för att innefatta utökningen %" #: config/riscv/riscv.cc:8917 #, gcc-internal-format msgid "Current RISC-V GCC does not support VLEN greater than 4096bit for 'V' Extension" -msgstr "" +msgstr "Aktuell RISC-V GCC stödjer inte VLEN större än 4096 bitar till utökningen ”V”" #: config/riscv/riscv.cc:8923 #, fuzzy, gcc-internal-format @@ -45185,7 +45187,7 @@ msgstr "hopp in i räckvidd för identifierare med variabel typ" #: c/c-decl.cc:4093 #, gcc-internal-format msgid "jump skips OpenMP % allocation" -msgstr "" +msgstr "hoppet skippar OpenMP %-allokering" #: c/c-decl.cc:4096 #, gcc-internal-format @@ -46639,7 +46641,7 @@ msgstr "uppräkningsvärde för %qE är inte ett konstant heltalsuttryck" #: c/c-decl.cc:12641 #, gcc-internal-format msgid "%<_BitInt%> argument %qE is larger than % %qd" -msgstr "" +msgstr "argumentet %qE till %<_BitInt%> är större än % %qd" #: c/c-decl.cc:12689 #, gcc-internal-format @@ -47374,7 +47376,7 @@ msgstr "föreslår uttryckliga klamrar för att undvika tvetydighet i %" #: c/c-parser.cc:8122 c/c-parser.cc:8187 c/c-parser.cc:8306 cp/parser.cc:14614 #, gcc-internal-format msgid "loop not permitted in intervening code in OpenMP loop body" -msgstr "" +msgstr "en slinga är inte tillåten i mellanliggande kod i OpenMP:s slingkropp" #: c/c-parser.cc:8195 #, gcc-internal-format @@ -47863,7 +47865,7 @@ msgstr "absolutvärdesfunktionen %qD ges ett argument av typen %qT men har en pa #: c/c-parser.cc:12606 cp/parser.cc:8164 #, gcc-internal-format msgid "calls to the OpenMP runtime API are not permitted in intervening code" -msgstr "" +msgstr "anrop av OpenMP:s körtids-API är inte tillåtet i mellanliggande kod" #: c/c-parser.cc:12980 #, gcc-internal-format @@ -47943,7 +47945,7 @@ msgstr "%<#pragma GCC unroll%> kräver ett tilldelningsuttryck som beräknas til #: c/c-parser.cc:14470 cp/parser.cc:50733 #, gcc-internal-format msgid "intervening code must not contain OpenMP directives" -msgstr "" +msgstr "mellanliggande kod får inte innehålla OpemMP-direktiv" #: c/c-parser.cc:14490 c/c-parser.cc:23558 c/c-parser.cc:23867 #: c/c-parser.cc:23930 c/c-parser.cc:24040 cp/parser.cc:46383 @@ -48430,7 +48432,7 @@ msgstr "%<#pragma acc %s data%> har ingen dataflyttningsklausul" #: c/c-parser.cc:20109 cp/parser.cc:47244 #, gcc-internal-format msgid "% construct requires % clause" -msgstr "" +msgstr "konstruktionen % kräver en klausul %" #: c/c-parser.cc:20338 cp/parser.cc:3367 #, gcc-internal-format @@ -48487,7 +48489,7 @@ msgstr "mallparametern %qD deklarerad här" #: c/c-parser.cc:20580 #, gcc-internal-format msgid "variable %qD used in the % clause must not be modified between declaration of %qD and its % directive" -msgstr "" +msgstr "variabeln %qD använd i klausulen % får inte ändras mellan deklarationen av %qD och dess direktiv %" #: c/c-parser.cc:20583 #, fuzzy, gcc-internal-format @@ -48526,7 +48528,7 @@ msgstr "%qD förekommer mer än en gång i %-klausuler" #: c/c-parser.cc:20714 #, gcc-internal-format msgid "% clause required for static variable %qD" -msgstr "" +msgstr "klausulen % krävs för den statiska variabeln %qD" #: c/c-parser.cc:20721 #, fuzzy, gcc-internal-format @@ -48659,7 +48661,7 @@ msgstr "uttrycket % är inte ett l-värde-uttryck" #: c/c-parser.cc:21851 cp/parser.cc:43744 #, gcc-internal-format msgid "the % expression %qE should be the same as the % argument %qE" -msgstr "" +msgstr "uttrycket %qE till % skall vara detsamma som argumentet %qE till %" #: c/c-parser.cc:21882 cp/parser.cc:43780 #, gcc-internal-format @@ -49214,7 +49216,7 @@ msgstr "det går inte att blanda operander av typerna decimalt flyttal och annat #: c/c-typeck.cc:926 #, gcc-internal-format msgid "%<_Complex _BitInt(%d)%> unsupported" -msgstr "" +msgstr "%<_Complex _BitInt(%d)%> stödjs inte" #: c/c-typeck.cc:1472 #, fuzzy, gcc-internal-format @@ -51352,7 +51354,7 @@ msgstr " en ärvd konstruerare är inte en kandidat för initiering från ett u #: cp/call.cc:4109 #, gcc-internal-format msgid "some candidates omitted; use %<-fdiagnostics-all-candidates%> to display them" -msgstr "" +msgstr "några kandidater uteslutna; använd %<-fdiagnostics-all-candidates%> för att visa dem" #: cp/call.cc:4190 cp/call.cc:4735 #, gcc-internal-format @@ -51824,7 +51826,7 @@ msgstr "användning av multiversionsfunktion utan ett standardfall" #: cp/call.cc:10002 #, gcc-internal-format msgid "use %<-fdiagnostics-all-candidates%> to display considered candidates" -msgstr "" +msgstr "använd %<-fdiagnostics-all-candidates%> för att visa kandidater som övervägts" #: cp/call.cc:10125 #, gcc-internal-format @@ -52122,7 +52124,7 @@ msgstr "den temporära destruerades vid slutet av det fullständiga uttrycket %q #: cp/call.cc:14550 #, gcc-internal-format msgid "explicit conversion function was not considered" -msgstr "" +msgstr "en explicit konverteringsfunktion övervägdes inte" #: cp/class.cc:322 #, gcc-internal-format @@ -52414,7 +52416,7 @@ msgstr "pekarmedlemmen %q+D är deklarerad här" #: cp/class.cc:4316 #, gcc-internal-format msgid "layout of %qs member of type %qT changes in %qs" -msgstr "" +msgstr "layouten av %qs-medlemmen av typen %qT ändras i %qs" #: cp/class.cc:4709 #, gcc-internal-format @@ -52763,7 +52765,7 @@ msgstr "%qD är inte användbar som en %-funktion eftersom:" #: cp/constexpr.cc:1320 cp/constexpr.cc:6349 #, gcc-internal-format msgid "destroying %qE outside its lifetime" -msgstr "" +msgstr "förstör %qE utanför dess livstid" #: cp/constexpr.cc:1611 cp/constexpr.cc:3308 #: rust/backend/rust-constexpr.cc:3326 rust/backend/rust-constexpr.cc:3589 @@ -52929,7 +52931,7 @@ msgstr "%qE är inte ett konstant uttryck" #: cp/constexpr.cc:3547 #, gcc-internal-format msgid "address of non-static constexpr variable %qD may differ on each invocation of the enclosing function; add % to give it a constant address" -msgstr "" +msgstr "adressen till den icke-statiska constexpr-variabeln %qD kan skilja vid varje uppstar av den omgivande funktionen; ligg till % för att ge den en konstant adress" #: cp/constexpr.cc:3623 #, gcc-internal-format @@ -53183,12 +53185,12 @@ msgstr "ändring av den aktiva medlemmen av en union %qD till %qD under initieri #: cp/constexpr.cc:6517 #, gcc-internal-format msgid "%qD does not implicitly begin its lifetime because %qT does not have a non-deleted trivial default constructor, use % instead" -msgstr "" +msgstr "%qD börjar inte implicit sin livstid eftersom %qT inte har någon oraderad trivial standardkonstruerare, använd % istället" #: cp/constexpr.cc:6524 #, gcc-internal-format msgid "initializing %qD requires a member access expression as the left operand of the assignment" -msgstr "" +msgstr "initiering av %qD kräver ett medlemsåtkomstuttryck som vänster operand i tilldelningen" #: cp/constexpr.cc:6536 rust/backend/rust-constexpr.cc:2822 #, gcc-internal-format @@ -54237,7 +54239,7 @@ msgstr "båda grenarna av en %-sats markerad som %qs" #: cp/cp-gimplify.cc:536 #, gcc-internal-format msgid "%qD was promoted to an immediate function because its body contains an immediate-escalating expression %qE" -msgstr "" +msgstr "%qD befordrades till en omedelbar funktion eftersom dess kropp innehåller ett uttryck %qE som omedelbareskalerar" #: cp/cp-gimplify.cc:539 #, fuzzy, gcc-internal-format @@ -54910,7 +54912,7 @@ msgstr "statisk datamedlem %qD i namnlös klass" #: cp/decl.cc:2120 #, gcc-internal-format msgid "variable at namespace scope is not name-independent" -msgstr "" +msgstr "en variabel i namnrymdsräckvidd är inte namnoberoende" #: cp/decl.cc:2123 #, fuzzy, gcc-internal-format @@ -55109,7 +55111,7 @@ msgstr "hopp till case-etikett" #: cp/decl.cc:3694 #, gcc-internal-format msgid " as a possible target of computed goto" -msgstr "" +msgstr " som ett möjligt mål för beräknad goto" #: cp/decl.cc:3696 #, gcc-internal-format @@ -56020,7 +56022,7 @@ msgstr "vändeklaration är inte i klassdefinition" #: cp/decl.cc:10597 #, gcc-internal-format msgid "friend function template with constraints that depend on outer template parameters must be a definition" -msgstr "" +msgstr "en vänfunktionsmall med begränsningar som beror på yttre mallparametrar måste vara en definition" #: cp/decl.cc:10646 #, gcc-internal-format @@ -56714,7 +56716,7 @@ msgstr " medlemsfunktionstypen %qT är inte ett giltigt mallargument" #: cp/decl.cc:13377 #, gcc-internal-format msgid "the type of a pointer to explicit object member function is a regular pointer to function type" -msgstr "" +msgstr "typen på en pekare till en explicit objektmedlemsfunktion är en vanlig pekare på en funktionstyp" #: cp/decl.cc:13381 #, fuzzy, gcc-internal-format @@ -56725,7 +56727,7 @@ msgstr "typedef får inte vara en medlemsfunktionsdefinition" #: cp/decl.cc:13402 #, gcc-internal-format msgid "only the first parameter of a member function can be declared as an explicit object parameter" -msgstr "" +msgstr "endast den första parametern till en medlemsfunktion kan deklareras som en explicit objektparameter" #: cp/decl.cc:13407 #, fuzzy, gcc-internal-format @@ -56893,7 +56895,7 @@ msgstr "implicita mallar får inte vara %" #: cp/decl.cc:13722 #, gcc-internal-format msgid "an explicit object member function cannot be %" -msgstr "" +msgstr "en explicit objektmedlemsfunktion kan inte vara %" #: cp/decl.cc:13748 #, gcc-internal-format @@ -60486,7 +60488,7 @@ msgstr "typer får inte definieras i %<__builtin_offsetof%>" #: cp/parser.cc:8400 cp/parser.cc:8429 #, gcc-internal-format msgid "cannot use multidimensional subscript in OpenMP array section" -msgstr "" +msgstr "kan inte använda multidimensionellt index i OpenMP-vektorsektionen" #: cp/parser.cc:8687 cp/typeck.cc:3052 #, gcc-internal-format @@ -60591,7 +60593,7 @@ msgstr "typer får inte definieras i %<__builtin_offsetof%>" #: cp/parser.cc:11229 #, gcc-internal-format msgid "trailing argument to %<__type_pack_element%> is not a type" -msgstr "" +msgstr "avslutande argument till %<__type_pack_element%> är inte en typ" #: cp/parser.cc:11329 #, gcc-internal-format @@ -60707,7 +60709,7 @@ msgstr "en parameterdeklaration före lambdadeklarationsspecificerare är endast #: cp/parser.cc:11932 cp/pt.cc:14718 #, gcc-internal-format msgid "a lambda with captures may not have an explicit object parameter of an unrelated type" -msgstr "" +msgstr "ett lambda med fångster kan inte ha en explicit objektparameter av en orelaterad typ" #: cp/parser.cc:11945 #, fuzzy, gcc-internal-format @@ -60718,17 +60720,17 @@ msgstr "lambdaspecificeraren % med lambdafångst" #: cp/parser.cc:11954 #, gcc-internal-format msgid "the passed in closure object will not be mutated because it is taken by value" -msgstr "" +msgstr "det inskickade höljesobjektet kommer inte muteras eftersom det tas via värde" #: cp/parser.cc:11958 #, gcc-internal-format msgid "declare the explicit object parameter as non-const reference instead" -msgstr "" +msgstr "deklarera den explicita objektparametern som en icke-const-referens istället" #: cp/parser.cc:11962 #, gcc-internal-format msgid "explicit object parameter is already a mutable reference" -msgstr "" +msgstr "explicit objektparameter är redan en muterbar referens" #: cp/parser.cc:11969 #, fuzzy, gcc-internal-format @@ -60974,7 +60976,7 @@ msgstr "import-deklaration måste vara på global räckvidd" #: cp/parser.cc:15241 #, gcc-internal-format msgid "import specifying a module-partition must appear after a named module-declaration" -msgstr "" +msgstr "att importspecificera en mudulpartition måste förekomma efter en namngiven moduldeklaration" #: cp/parser.cc:15253 #, gcc-internal-format @@ -61489,7 +61491,7 @@ msgstr "typer får inte definieras i enum-bas" #: cp/parser.cc:21618 #, gcc-internal-format msgid "declaration of enumeration with fixed underlying type and no enumerator list is only permitted as a standalone declaration" -msgstr "" +msgstr "deklaration av en uppräkning med fixerad underliggande typ och ingen uppräknarlista är endast tillåtet som en fristående deklaration" #: cp/parser.cc:21622 #, gcc-internal-format @@ -64683,7 +64685,7 @@ msgstr "begärd minnesjustering är inte en heltalskonstant" #: cp/semantics.cc:4656 #, gcc-internal-format msgid "%<__type_pack_element%> index is negative" -msgstr "" +msgstr "indexet till %<__type_pack_element%> är negativt" #: cp/semantics.cc:4662 #, fuzzy, gcc-internal-format @@ -64997,17 +64999,17 @@ msgstr "%<#pragma omp atomic update%> använder två olika uttryck för minne" #: cp/semantics.cc:11509 #, gcc-internal-format msgid "% message must be a string literal or object with % and % members" -msgstr "" +msgstr "meddelandet i % måste vara en strängliteral eller ett objekt med medlemmarna % och %" #: cp/semantics.cc:11525 #, gcc-internal-format msgid "% message % must be implicitly convertible to %" -msgstr "" +msgstr "meddelandet % till % måste vara implicit konverterbart till %" #: cp/semantics.cc:11534 #, gcc-internal-format msgid "% message % must be implicitly convertible to %" -msgstr "" +msgstr "meddelandet % till % måste vara implicit konverterbart till %" #: cp/semantics.cc:11592 #, fuzzy, gcc-internal-format @@ -65018,7 +65020,7 @@ msgstr "%-uttryck måste vara ett konstant heltalsuttryck" #: cp/semantics.cc:11600 #, gcc-internal-format msgid "% message % %qE too large" -msgstr "" +msgstr "meddelandet % till % %qE är för stort" #: cp/semantics.cc:11627 #, fuzzy, gcc-internal-format @@ -66261,7 +66263,7 @@ msgstr "ogiltig kovariant returtyp för %q#D" #: cp/typeck.cc:11311 #, gcc-internal-format msgid "not eliding copy on return in %qD" -msgstr "" +msgstr "utelämnar inte kopiering vid retur i %qD" #: cp/typeck.cc:11898 #, gcc-internal-format @@ -66781,7 +66783,7 @@ msgstr "det går inte att konvertera %qH till %qI när argument skickas" #: d/d-convert.cc:759 #, gcc-internal-format msgid "parameters of type % {aka %qs} are decayed to pointer types, and require % to be converted back into a static array type" -msgstr "" +msgstr "parametrar av typen % {ävän kända som %qs} degenereras till pekartyper, och kräver % för att konverteras tillbaka till en statisk vektortyp" #: d/d-lang.cc:463 #, gcc-internal-format @@ -67011,7 +67013,7 @@ msgstr "%<-fmoduleinfo%> stödjs inte för denna målarkitektur" #: d/toir.cc:245 #, gcc-internal-format msgid "calling %qE without side effects discards return value of type %qT; prepend a % if intentional" -msgstr "" +msgstr "anrop av %qE utan sidoeffekter slänger returvärdet av typen %qT; lägg till en % före om det är avsiktligt" #: d/toir.cc:419 d/toir.cc:444 #, gcc-internal-format @@ -69874,7 +69876,7 @@ msgstr "Formella argumentnamnen till MODULE PROCEDURE stämmer inte (%s/%s) vid #: fortran/decl.cc:6809 #, gcc-internal-format msgid "MODULE PROCEDURE formal argument is alternate return and conflicts with %qs in the separate declaration at %C" -msgstr "" +msgstr "Formella argument till MODULE PROCEDURE är alternativ retur och i konflikt med %qs i den separata deklarationen vid %C" #: fortran/decl.cc:6814 #, gcc-internal-format, gfc-internal-format @@ -72103,7 +72105,7 @@ msgstr "Aktuellt argument till %qs skall vara en ALLOCATABLE vid %L" #: fortran/interface.cc:3693 #, gcc-internal-format msgid "Actual argument for %qs at %L is a function result and the dummy argument is ALLOCATABLE" -msgstr "" +msgstr "Aktuella argument till %qs vid %L är ett funktionsresultat och attrappargumentet är ALLOCATABLE" #: fortran/interface.cc:3731 #, gcc-internal-format @@ -74670,7 +74672,7 @@ msgstr "Listobjektet skall inte vara co-indexerat vid %C" #: fortran/openmp.cc:492 #, gcc-internal-format msgid "%qs at %L is part of the common block % and may only be specificed implicitly via the named common block" -msgstr "" +msgstr "%qs vid %L är del av common-blocket % och kan endast anges implicit via det namngivna common-blocket" #: fortran/openmp.cc:517 fortran/openmp.cc:618 fortran/openmp.cc:948 #: fortran/openmp.cc:6135 @@ -74786,7 +74788,7 @@ msgstr "%qs-direktivet nämnt båda gångerna i ABSENT- och CONTAINS-klausuler i #: fortran/openmp.cc:1745 #, gcc-internal-format, gfc-internal-format msgid "Duplicate %s modifier at %L in USES_ALLOCATORS clause" -msgstr "" +msgstr "Dubblerad %s-modifierare vid %L i en USES_ALLOCATORS-klausul" #: fortran/openmp.cc:1779 #, fuzzy, gcc-internal-format @@ -75115,7 +75117,7 @@ msgstr "IN, OUT, INOUT, INOUTSET eller MUTEXINOUTSET förväntades följt av %<) #: fortran/openmp.cc:4771 #, gcc-internal-format, gfc-internal-format msgid "The same depend object should be used as DEPOBJ argument at %L and as DESTROY argument at %L" -msgstr "" +msgstr "Samma beroendeobjekt skall användas som DEPOBJ-argument vid %L och som DESTROY-argument vid %L" #: fortran/openmp.cc:4785 #, gcc-internal-format, gfc-internal-format @@ -75230,7 +75232,7 @@ msgstr "Listpost %qs vid %L satt i föregående OMP DECLARE TARGET-direktiv till #: fortran/openmp.cc:5547 fortran/openmp.cc:5601 #, gcc-internal-format, gfc-internal-format msgid "DEVICE_TYPE must be ANY when used with INDIRECT at %L" -msgstr "" +msgstr "DEVICE_TYPE måste vara ANY när använt med INDIRECT vid %L" #: fortran/openmp.cc:5557 #, gcc-internal-format, gfc-internal-format @@ -75651,7 +75653,7 @@ msgstr "Den implicit deklarerade subrutinen %s används i !$OMP DECLARE REDUCTIO #: fortran/openmp.cc:7349 #, gcc-internal-format msgid "Unexpected function-result variable %qs at %L in declarative !$OMP ALLOCATE" -msgstr "" +msgstr "Oväntad funktionsresultatvariabel %qs vid %L i deklarativt !$OMP ALLOCATE" #: fortran/openmp.cc:7355 #, fuzzy, gcc-internal-format @@ -75662,12 +75664,12 @@ msgstr "Procedurpekare %qs i %s-klausul vid %L" #: fortran/openmp.cc:7361 #, gcc-internal-format msgid "Argument %qs at %L to declarative !$OMP ALLOCATE directive must be a variable" -msgstr "" +msgstr "Argumentet %qs vid %L till deklarativt !$OMP ALLOCATE-direktiv måste vara en variabel" #: fortran/openmp.cc:7368 #, gcc-internal-format msgid "Argument %qs at %L to declarative !$OMP ALLOCATE shall be in the same scope as the variable declaration" -msgstr "" +msgstr "Argumentet %qs vid %L till deklarativt !$OMP ALLOCATE skall ligga i samma räckvidd som variabeldeklarationen" #: fortran/openmp.cc:7375 #, fuzzy, gcc-internal-format @@ -75678,37 +75680,37 @@ msgstr "Skickat objekt-attrappargument till %qs vid %L får inte vara ALLOCATABL #: fortran/openmp.cc:7381 #, gcc-internal-format msgid "Unexpected coarray argument %qs as argument at %L to declarative !$OMP ALLOCATE" -msgstr "" +msgstr "Oväntat co-vektorargument %qs som argument vid %L till deklarativt !$OMP ALLOCATE" #: fortran/openmp.cc:7389 #, gcc-internal-format msgid "Duplicated common block % in !$OMP ALLOCATE at %L" -msgstr "" +msgstr "Dubblerat common-block % i !$OMP ALLOCATE vid %L" #: fortran/openmp.cc:7396 #, gcc-internal-format msgid "Duplicated variable %qs in !$OMP ALLOCATE at %L" -msgstr "" +msgstr "Dubblerad variabel %qs i !$OMP ALLOCATE vid %L" #: fortran/openmp.cc:7407 #, gcc-internal-format msgid "Sorry, EQUIVALENCE object %qs not supported with !$OMP ALLOCATE at %L" -msgstr "" +msgstr "Tyvärr, EQUIVALENCE-objektet %qs stödjs inte med !$OMP ALLOCATE vid %L" #: fortran/openmp.cc:7416 #, gcc-internal-format msgid "Sorry, Cray pointers and pointees such as %qs are not supported with !$OMP ALLOCATE at %L" -msgstr "" +msgstr "Tyvärr, Cray-pekare och -utpekade såsom %qs stödjs inte med !$OMP ALLOCATE vid %L" #: fortran/openmp.cc:7425 #, gcc-internal-format msgid "Unexpected allocatable variable %qs at %L in declarative !$OMP ALLOCATE directive" -msgstr "" +msgstr "Oväntad allokerbar variabel %qs vid %L i deklarativt !$OMP ALLOCATE-direktiv" #: fortran/openmp.cc:7430 #, gcc-internal-format msgid "Unexpected pointer variable %qs at %L in declarative !$OMP ALLOCATE directive" -msgstr "" +msgstr "Oväntad pekarvariabel %qs vid %L i deklarativt !$OMP ALLOCATE-direktiv" #: fortran/openmp.cc:7441 fortran/openmp.cc:7996 #, fuzzy, gcc-internal-format, gfc-internal-format @@ -75719,12 +75721,12 @@ msgstr "En ALIGN-modifierare kräver vid %L ett skalärt positivt konstant helta #: fortran/openmp.cc:7456 #, gcc-internal-format msgid "An ALLOCATOR clause is required as the list item %<%s%s%s%> at %L has the SAVE attribute" -msgstr "" +msgstr "En ALLOCATOR-klausul krävs då listelementet %<%s%s%s%> vid %L har attributet SAVE" #: fortran/openmp.cc:7461 #, gcc-internal-format msgid "Predefined allocator required in ALLOCATOR clause at %L as the list item %<%s%s%s%> at %L has the SAVE attribute" -msgstr "" +msgstr "En fördefinierad allokerare krävs i ALLOCATOR-klausulen vid %L då listelementet %<%s%s%s%> vid %L har attributet SAVE" #: fortran/openmp.cc:7475 fortran/openmp.cc:7980 #, gcc-internal-format @@ -75878,27 +75880,27 @@ msgstr "%qs angivet i en %-klausul vid %L men inte i en explicit priv #: fortran/openmp.cc:8139 #, gcc-internal-format msgid "%qs listed in % statement at %L but it is neither explicitly in listed in the % directive nor exists a directive without argument list" -msgstr "" +msgstr "%qs listad i %-satsen vid %L men den varken är explicit listat i direktivet % eller finns som ett direktiv utan argumentlista" #: fortran/openmp.cc:8150 #, gcc-internal-format msgid "Unexpected coarray %qs in % at %L, implicitly listed in % at %L" -msgstr "" +msgstr "Oväntad co-vektor %qs i % i %L, implicit listad i % vid %L" #: fortran/openmp.cc:8175 #, gcc-internal-format msgid "ALLOCATORS directive at %L inside a target region must specify an ALLOCATOR modifier for %qs" -msgstr "" +msgstr "Direktivet ALLOCATORS vid %L inuti en målregion måste ange en ALLOCATOR-modifierare för %qs" #: fortran/openmp.cc:8179 #, gcc-internal-format msgid "ALLOCATE directive at %L inside a target region must specify an ALLOCATOR clause for %qs" -msgstr "" +msgstr "Direktivet ALLOCATE vid %L inuti en målregion moste ange en ALLOCATOR-klausul för %qs" #: fortran/openmp.cc:8183 #, gcc-internal-format, gfc-internal-format msgid "ALLOCATE directive at %L inside a target region must specify an ALLOCATOR clause" -msgstr "" +msgstr "Direktivet ALLOCATE vid %L inuti en målregion måste ange en ALLOCATOR-klausul" #: fortran/openmp.cc:8206 #, gcc-internal-format @@ -76080,7 +76082,7 @@ msgstr "Listposten %qs i %s-klausul vid %L måste vara TYPE(C_PTR)" #: fortran/openmp.cc:8709 #, gcc-internal-format msgid "Memspace %qs at %L in USES_ALLOCATORS must be a predefined memory space" -msgstr "" +msgstr "Memspace %qs vid %L i USES_ALLOCATORS måste vara ett fördefinierat minnesutrymme" #: fortran/openmp.cc:8717 #, fuzzy, gcc-internal-format @@ -76091,17 +76093,17 @@ msgstr "%qs vid %L skall vara en skalär av typen integer(kind=omp_event_handle_ #: fortran/openmp.cc:8725 #, gcc-internal-format msgid "Allocator %qs at %L in USES_ALLOCATORS must either a variable or a predefined allocator" -msgstr "" +msgstr "Allokeraren %qs vid %L i USES_ALLOCATORS måste vara antingen en variabel eller en fördefinierad allokerare" #: fortran/openmp.cc:8730 #, gcc-internal-format msgid "A memory space or traits array may not be specified for predefined allocator %qs at %L" -msgstr "" +msgstr "Ett minnesutrymme eller en egenskapsvektor får inte anges för den fördefinierade allokeraren %qs vid %L" #: fortran/openmp.cc:8741 #, gcc-internal-format msgid "Traits array %qs in USES_ALLOCATORS %L must be a one-dimensional named constant array of type %" -msgstr "" +msgstr "Egenskapsvektorn %qs i USES_ALLOCATORS %L måste vara en endimensionell namngiven konstantvektor av typen %" #: fortran/openmp.cc:8771 #, gcc-internal-format @@ -76237,7 +76239,7 @@ msgstr "en %-klausul vid %L får inte användas tillsammans med en % construct at %L requires % clause" -msgstr "" +msgstr "Konstruktionen % vid %L kräver en %-klausul" #: fortran/openmp.cc:9380 #, gcc-internal-format, gfc-internal-format @@ -76383,17 +76385,17 @@ msgstr "Med INSCAN vid %L, slingkropp med !$OMP SCAN förväntades mellan två s #: fortran/openmp.cc:9955 #, gcc-internal-format, gfc-internal-format msgid "!$OMP SCAN at %L with zero executable statements in preceding structured block sequence" -msgstr "" +msgstr "!$OMP SCAN vid %L med noll körbara satser i föregående strukturerade blocksekvens" #: fortran/openmp.cc:9962 #, gcc-internal-format, gfc-internal-format msgid "!$OMP SCAN at %L with zero executable statements in succeeding structured block sequence" -msgstr "" +msgstr "!$OMP SCAN vid %L med noll körbara satser i efterföljande strukturerade blocksekvens" #: fortran/openmp.cc:10176 #, gcc-internal-format, gfc-internal-format msgid "%s cannot contain loop in intervening code at %L" -msgstr "" +msgstr "%s kan inte innehålla en slinga i mellanliggande kod vid %L" #: fortran/openmp.cc:10256 #, gcc-internal-format, gfc-internal-format -- cgit v1.1 From eae6b63b5b5426f943f58b5ae0bf0a6068ca8ad6 Mon Sep 17 00:00:00 2001 From: David Faust Date: Mon, 4 Mar 2024 09:35:01 -0800 Subject: bpf: add inline memset expansion Similar to memmove and memcpy, the BPF backend cannot fall back on a library call to implement __builtin_memset, and should always expand calls to it inline if possible. This patch implements simple inline expansion of memset in the BPF backend in a verifier-friendly way. Similar to memcpy and memmove, the size must be an integer constant, as is also required by clang. gcc/ * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype. * config/bpf/bpf.cc (bpf_expand_setmem): New. * config/bpf/bpf.md (setmemdi): New define_expand. gcc/testsuite/ * gcc.target/bpf/memset-1.c: New test. --- gcc/config/bpf/bpf-protos.h | 1 + gcc/config/bpf/bpf.cc | 66 +++++++++++++++++++++++++++++++++ gcc/config/bpf/bpf.md | 17 +++++++++ gcc/testsuite/gcc.target/bpf/memset-1.c | 39 +++++++++++++++++++ 4 files changed, 123 insertions(+) create mode 100644 gcc/testsuite/gcc.target/bpf/memset-1.c (limited to 'gcc') diff --git a/gcc/config/bpf/bpf-protos.h b/gcc/config/bpf/bpf-protos.h index 366acb8..ac0c2f4 100644 --- a/gcc/config/bpf/bpf-protos.h +++ b/gcc/config/bpf/bpf-protos.h @@ -36,5 +36,6 @@ class gimple_opt_pass; gimple_opt_pass *make_pass_lower_bpf_core (gcc::context *ctxt); bool bpf_expand_cpymem (rtx *, bool); +bool bpf_expand_setmem (rtx *); #endif /* ! GCC_BPF_PROTOS_H */ diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc index 22b0cf2..0e33f43 100644 --- a/gcc/config/bpf/bpf.cc +++ b/gcc/config/bpf/bpf.cc @@ -1309,6 +1309,72 @@ bpf_expand_cpymem (rtx *operands, bool is_move) return true; } +/* Expand setmem, as from __builtin_memset. + OPERANDS are the same as the setmem pattern. + Return true if the expansion was successful, false otherwise. */ + +bool +bpf_expand_setmem (rtx *operands) +{ + /* Size must be constant for this expansion to work. */ + if (!CONST_INT_P (operands[1])) + { + if (flag_building_libgcc) + warning (0, "could not inline call to %<__builtin_memset%>: " + "size must be constant"); + else + error ("could not inline call to %<__builtin_memset%>: " + "size must be constant"); + return false; + } + + /* Alignment is a CONST_INT. */ + gcc_assert (CONST_INT_P (operands[3])); + + rtx dst = operands[0]; + rtx size = operands[1]; + rtx val = operands[2]; + unsigned HOST_WIDE_INT size_bytes = UINTVAL (size); + unsigned align = UINTVAL (operands[3]); + enum machine_mode mode; + switch (align) + { + case 1: mode = QImode; break; + case 2: mode = HImode; break; + case 4: mode = SImode; break; + case 8: mode = DImode; break; + default: + gcc_unreachable (); + } + + unsigned iters = size_bytes >> ceil_log2 (align); + unsigned remainder = size_bytes & (align - 1); + unsigned inc = GET_MODE_SIZE (mode); + unsigned offset = 0; + + for (unsigned int i = 0; i < iters; i++) + { + emit_move_insn (adjust_address (dst, mode, offset), val); + offset += inc; + } + if (remainder & 4) + { + emit_move_insn (adjust_address (dst, SImode, offset), val); + offset += 4; + remainder -= 4; + } + if (remainder & 2) + { + emit_move_insn (adjust_address (dst, HImode, offset), val); + offset += 2; + remainder -= 2; + } + if (remainder & 1) + emit_move_insn (adjust_address (dst, QImode, offset), val); + + return true; +} + /* Finally, build the GCC target. */ struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md index ca677bc..ea688aa 100644 --- a/gcc/config/bpf/bpf.md +++ b/gcc/config/bpf/bpf.md @@ -663,4 +663,21 @@ FAIL; }) +;; memset +;; 0 is dst +;; 1 is length +;; 2 is value +;; 3 is alignment +(define_expand "setmemdi" + [(set (match_operand:BLK 0 "memory_operand") + (match_operand:QI 2 "nonmemory_operand")) + (use (match_operand:DI 1 "general_operand")) + (match_operand 3 "immediate_operand")] + "" + { + if (bpf_expand_setmem (operands)) + DONE; + FAIL; +}) + (include "atomic.md") diff --git a/gcc/testsuite/gcc.target/bpf/memset-1.c b/gcc/testsuite/gcc.target/bpf/memset-1.c new file mode 100644 index 0000000..9e9f8ef --- /dev/null +++ b/gcc/testsuite/gcc.target/bpf/memset-1.c @@ -0,0 +1,39 @@ +/* Ensure memset is expanded inline rather than emitting a libcall. */ + +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +struct context { + unsigned int data; + unsigned int data_end; + unsigned int data_meta; + unsigned int ingress; + unsigned int queue_index; + unsigned int egress; +}; + +void +set_small (struct context *ctx) +{ + void *data = (void *)(long)ctx->data; + char *dest = data; + __builtin_memset (dest + 4, 0, sizeof (struct context) - 4); +} + +void +set_large (struct context *ctx) +{ + void *data = (void *)(long)ctx->data; + char *dest = data; + __builtin_memset (dest, 0xfe, 130); +} + +void +set_variable (struct context *ctx) +{ + void *data = (void *)(long)ctx->data; + char *dest = data; + __builtin_memset (dest, 0xbc, ctx->data_meta); /* { dg-error "could not inline call" } */ +} + +/* { dg-final { scan-assembler-times "call" 0 } } */ -- cgit v1.1 From d646db0e35ad9d235635b204349f5d960072f9fe Mon Sep 17 00:00:00 2001 From: Gaius Mulley Date: Mon, 4 Mar 2024 21:46:32 +0000 Subject: PR modula2/114227 InstallTerminationProcedure does not work with -fiso This patch moves the initial/termination user procedure functionality in pim and iso versions of M2RTS into M2Dependent. This ensures that finalization/initialization procedures will always be invoked for both -fiso and -fpim. Prior to this patch M2Dependent called M2RTS for termination procedure cleanup and always invoked the pim M2RTS. gcc/m2/ChangeLog: PR modula2/114227 * gm2-libs-iso/M2RTS.mod (ProcedureChain): Remove. (ProcedureList): Remove. (ExecuteReverse): Remove. (ExecuteTerminationProcedures): Rewrite. (ExecuteInitialProcedures): Rewrite. (AppendProc): Remove. (InstallTerminationProcedure): Rewrite. (InstallInitialProcedure): Rewrite. (InitProcList): Remove. * gm2-libs/M2Dependent.def (InstallTerminationProcedure): New procedure. (ExecuteTerminationProcedures): New procedure. (InstallInitialProcedure): New procedure. (ExecuteInitialProcedures): New procedure. * gm2-libs/M2Dependent.mod (ProcedureChain): New type. (ProcedureList): New type. (ExecuteReverse): New procedure. (ExecuteTerminationProcedures): New procedure. (ExecuteInitialProcedures): New procedure. (AppendProc): New procedure. (InstallTerminationProcedure): New procedure. (InstallInitialProcedure): New procedure. (InitProcList): New procedure. * gm2-libs/M2RTS.mod (ProcedureChain): Remove. (ProcedureList): Remove. (ExecuteReverse): Remove. (ExecuteTerminationProcedures): Rewrite. (ExecuteInitialProcedures): Rewrite. (AppendProc): Remove. (InstallTerminationProcedure): Rewrite. (InstallInitialProcedure): Rewrite. (InitProcList): Remove. Signed-off-by: Gaius Mulley --- gcc/m2/gm2-libs-iso/M2RTS.mod | 73 ++---------------------- gcc/m2/gm2-libs/M2Dependent.def | 36 ++++++++++++ gcc/m2/gm2-libs/M2Dependent.mod | 120 ++++++++++++++++++++++++++++++++++++++-- gcc/m2/gm2-libs/M2RTS.mod | 73 ++---------------------- 4 files changed, 159 insertions(+), 143 deletions(-) (limited to 'gcc') diff --git a/gcc/m2/gm2-libs-iso/M2RTS.mod b/gcc/m2/gm2-libs-iso/M2RTS.mod index 14a9e81..291b8e9 100644 --- a/gcc/m2/gm2-libs-iso/M2RTS.mod +++ b/gcc/m2/gm2-libs-iso/M2RTS.mod @@ -45,20 +45,7 @@ CONST TYPE PtrToChar = POINTER TO CHAR ; - ProcedureChain = POINTER TO RECORD - p : PROC ; - prev, - next: ProcedureChain ; - END ; - - ProcedureList = RECORD - head, tail: ProcedureChain - END ; - - VAR - InitialProc, - TerminateProc : ProcedureList ; ExitValue : INTEGER ; isTerminating, isHalting, @@ -122,28 +109,13 @@ END RequestDependant ; (* - ExecuteReverse - execute the procedure associated with procptr - and then proceed to try and execute all previous - procedures in the chain. -*) - -PROCEDURE ExecuteReverse (procptr: ProcedureChain) ; -BEGIN - WHILE procptr # NIL DO - procptr^.p ; (* Invoke the procedure. *) - procptr := procptr^.prev - END -END ExecuteReverse ; - - -(* ExecuteTerminationProcedures - calls each installed termination procedure in reverse order. *) PROCEDURE ExecuteTerminationProcedures ; BEGIN - ExecuteReverse (TerminateProc.tail) + M2Dependent.ExecuteTerminationProcedures END ExecuteTerminationProcedures ; @@ -154,35 +126,11 @@ END ExecuteTerminationProcedures ; PROCEDURE ExecuteInitialProcedures ; BEGIN - ExecuteReverse (InitialProc.tail) + M2Dependent.ExecuteInitialProcedures END ExecuteInitialProcedures ; (* - AppendProc - append proc to the end of the procedure list - defined by proclist. -*) - -PROCEDURE AppendProc (VAR proclist: ProcedureList; proc: PROC) : BOOLEAN ; -VAR - pdes: ProcedureChain ; -BEGIN - NEW (pdes) ; - WITH pdes^ DO - p := proc ; - prev := proclist.tail ; - next := NIL - END ; - IF proclist.head = NIL - THEN - proclist.head := pdes - END ; - proclist.tail := pdes ; - RETURN TRUE -END AppendProc ; - - -(* InstallTerminationProcedure - installs a procedure, p, which will be called when the procedure ExecuteTerminationProcedures @@ -192,7 +140,7 @@ END AppendProc ; PROCEDURE InstallTerminationProcedure (p: PROC) : BOOLEAN ; BEGIN - RETURN AppendProc (TerminateProc, p) + RETURN M2Dependent.InstallTerminationProcedure (p) END InstallTerminationProcedure ; @@ -204,7 +152,7 @@ END InstallTerminationProcedure ; PROCEDURE InstallInitialProcedure (p: PROC) : BOOLEAN ; BEGIN - RETURN AppendProc (InitialProc, p) + RETURN M2Dependent.InstallInitialProcedure (p) END InstallInitialProcedure ; @@ -626,24 +574,11 @@ END NoException ; (* - InitProcList - initialize the head and tail pointers to NIL. -*) - -PROCEDURE InitProcList (VAR p: ProcedureList) ; -BEGIN - p.head := NIL ; - p.tail := NIL -END InitProcList ; - - -(* Init - *) PROCEDURE Init ; BEGIN - InitProcList (InitialProc) ; - InitProcList (TerminateProc) ; ExitValue := 0 ; isHalting := FALSE ; CallExit := FALSE ; (* default by calling abort *) diff --git a/gcc/m2/gm2-libs/M2Dependent.def b/gcc/m2/gm2-libs/M2Dependent.def index 9e31d57..b37c004 100644 --- a/gcc/m2/gm2-libs/M2Dependent.def +++ b/gcc/m2/gm2-libs/M2Dependent.def @@ -62,4 +62,40 @@ PROCEDURE RequestDependant (modulename, libname, dependantmodule, dependantlibname: ADDRESS) ; +(* + InstallTerminationProcedure - installs a procedure, p, which will + be called when the procedure + ExecuteTerminationProcedures + is invoked. It returns TRUE is the + procedure is installed. +*) + +PROCEDURE InstallTerminationProcedure (p: PROC) : BOOLEAN ; + + +(* + ExecuteInitialProcedures - executes the initial procedures installed + by InstallInitialProcedure. +*) + +PROCEDURE ExecuteInitialProcedures ; + + +(* + InstallInitialProcedure - installs a procedure to be executed just + before the BEGIN code section of the main + program module. +*) + +PROCEDURE InstallInitialProcedure (p: PROC) : BOOLEAN ; + + +(* + ExecuteTerminationProcedures - calls each installed termination procedure + in reverse order. +*) + +PROCEDURE ExecuteTerminationProcedures ; + + END M2Dependent. diff --git a/gcc/m2/gm2-libs/M2Dependent.mod b/gcc/m2/gm2-libs/M2Dependent.mod index e7b502e..d6dfa63 100644 --- a/gcc/m2/gm2-libs/M2Dependent.mod +++ b/gcc/m2/gm2-libs/M2Dependent.mod @@ -33,8 +33,6 @@ FROM SYSTEM IMPORT ADR ; FROM Storage IMPORT ALLOCATE ; FROM StrLib IMPORT StrCopy, StrLen, StrEqual ; -IMPORT M2RTS ; - TYPE PtrToChar = POINTER TO CHAR ; @@ -61,6 +59,16 @@ TYPE next : ModuleChain ; END ; + ProcedureList = RECORD + head, tail: ProcedureChain + END ; + + ProcedureChain = POINTER TO RECORD + p : PROC ; + prev, + next: ProcedureChain ; + END ; + VAR Modules : ARRAY DependencyState OF ModuleChain ; DynamicInitialization, @@ -72,6 +80,8 @@ VAR PreTrace, PostTrace, ForceTrace : BOOLEAN ; + InitialProc, + TerminateProc : ProcedureList ; (* @@ -816,8 +826,8 @@ BEGIN IF mptr^.dependency.appl THEN traceprintf3 (ModuleTrace, "application module: %s [%s]\n", mptr^.name, mptr^.libname); - traceprintf (ModuleTrace, " calling M2RTS_ExecuteInitialProcedures\n"); - M2RTS.ExecuteInitialProcedures ; + traceprintf (ModuleTrace, " calling ExecuteInitialProcedures\n"); + ExecuteInitialProcedures ; traceprintf (ModuleTrace, " calling application module\n"); END ; mptr^.init (argc, argv, envp) ; @@ -844,7 +854,7 @@ BEGIN traceprintf (ModuleTrace, " no ordered modules found during finishing\n") ELSE traceprintf (ModuleTrace, "ExecuteTerminationProcedures\n") ; - M2RTS.ExecuteTerminationProcedures ; + ExecuteTerminationProcedures ; traceprintf (ModuleTrace, "terminating modules in sequence\n") ; mptr := Modules[ordered]^.prev ; REPEAT @@ -1005,6 +1015,8 @@ PROCEDURE Init ; VAR state: DependencyState ; BEGIN + InitProcList (InitialProc) ; + InitProcList (TerminateProc) ; SetupDebugFlags ; FOR state := MIN (DependencyState) TO MAX (DependencyState) DO Modules[state] := NIL @@ -1030,6 +1042,104 @@ BEGIN END CheckInitialized ; +(* + ExecuteReverse - execute the procedure associated with procptr + and then proceed to try and execute all previous + procedures in the chain. +*) + +PROCEDURE ExecuteReverse (procptr: ProcedureChain) ; +BEGIN + WHILE procptr # NIL DO + procptr^.p ; (* Invoke the procedure. *) + procptr := procptr^.prev + END +END ExecuteReverse ; + + +(* + ExecuteTerminationProcedures - calls each installed termination procedure + in reverse order. +*) + +PROCEDURE ExecuteTerminationProcedures ; +BEGIN + ExecuteReverse (TerminateProc.tail) +END ExecuteTerminationProcedures ; + + +(* + ExecuteInitialProcedures - executes the initial procedures installed by + InstallInitialProcedure. +*) + +PROCEDURE ExecuteInitialProcedures ; +BEGIN + ExecuteReverse (InitialProc.tail) +END ExecuteInitialProcedures ; + + +(* + AppendProc - append proc to the end of the procedure list + defined by proclist. +*) + +PROCEDURE AppendProc (VAR proclist: ProcedureList; proc: PROC) : BOOLEAN ; +VAR + pdes: ProcedureChain ; +BEGIN + NEW (pdes) ; + WITH pdes^ DO + p := proc ; + prev := proclist.tail ; + next := NIL + END ; + IF proclist.head = NIL + THEN + proclist.head := pdes + END ; + proclist.tail := pdes ; + RETURN TRUE +END AppendProc ; + + +(* + InstallTerminationProcedure - installs a procedure, p, which will + be called when the procedure + ExecuteTerminationProcedures + is invoked. It returns TRUE if the + procedure is installed. +*) + +PROCEDURE InstallTerminationProcedure (p: PROC) : BOOLEAN ; +BEGIN + RETURN AppendProc (TerminateProc, p) +END InstallTerminationProcedure ; + + +(* + InstallInitialProcedure - installs a procedure to be executed just + before the BEGIN code section of the + main program module. +*) + +PROCEDURE InstallInitialProcedure (p: PROC) : BOOLEAN ; +BEGIN + RETURN AppendProc (InitialProc, p) +END InstallInitialProcedure ; + + +(* + InitProcList - initialize the head and tail pointers to NIL. +*) + +PROCEDURE InitProcList (VAR p: ProcedureList) ; +BEGIN + p.head := NIL ; + p.tail := NIL +END InitProcList ; + + BEGIN CheckInitialized END M2Dependent. diff --git a/gcc/m2/gm2-libs/M2RTS.mod b/gcc/m2/gm2-libs/M2RTS.mod index 765e6e5..41add83 100644 --- a/gcc/m2/gm2-libs/M2RTS.mod +++ b/gcc/m2/gm2-libs/M2RTS.mod @@ -45,20 +45,7 @@ CONST TYPE PtrToChar = POINTER TO CHAR ; - ProcedureList = RECORD - head, tail: ProcedureChain - END ; - - ProcedureChain = POINTER TO RECORD - p : PROC ; - prev, - next: ProcedureChain ; - END ; - - VAR - InitialProc, - TerminateProc: ProcedureList ; ExitValue : INTEGER ; isHalting, CallExit : BOOLEAN ; @@ -121,28 +108,13 @@ END RequestDependant ; (* - ExecuteReverse - execute the procedure associated with procptr - and then proceed to try and execute all previous - procedures in the chain. -*) - -PROCEDURE ExecuteReverse (procptr: ProcedureChain) ; -BEGIN - WHILE procptr # NIL DO - procptr^.p ; (* Invoke the procedure. *) - procptr := procptr^.prev - END -END ExecuteReverse ; - - -(* ExecuteTerminationProcedures - calls each installed termination procedure in reverse order. *) PROCEDURE ExecuteTerminationProcedures ; BEGIN - ExecuteReverse (TerminateProc.tail) + M2Dependent.ExecuteTerminationProcedures END ExecuteTerminationProcedures ; @@ -153,35 +125,11 @@ END ExecuteTerminationProcedures ; PROCEDURE ExecuteInitialProcedures ; BEGIN - ExecuteReverse (InitialProc.tail) + M2Dependent.ExecuteInitialProcedures END ExecuteInitialProcedures ; (* - AppendProc - append proc to the end of the procedure list - defined by proclist. -*) - -PROCEDURE AppendProc (VAR proclist: ProcedureList; proc: PROC) : BOOLEAN ; -VAR - pdes: ProcedureChain ; -BEGIN - NEW (pdes) ; - WITH pdes^ DO - p := proc ; - prev := proclist.tail ; - next := NIL - END ; - IF proclist.head = NIL - THEN - proclist.head := pdes - END ; - proclist.tail := pdes ; - RETURN TRUE -END AppendProc ; - - -(* InstallTerminationProcedure - installs a procedure, p, which will be called when the procedure ExecuteTerminationProcedures @@ -191,7 +139,7 @@ END AppendProc ; PROCEDURE InstallTerminationProcedure (p: PROC) : BOOLEAN ; BEGIN - RETURN AppendProc (TerminateProc, p) + RETURN M2Dependent.InstallTerminationProcedure (p) END InstallTerminationProcedure ; @@ -203,7 +151,7 @@ END InstallTerminationProcedure ; PROCEDURE InstallInitialProcedure (p: PROC) : BOOLEAN ; BEGIN - RETURN AppendProc (InitialProc, p) + RETURN M2Dependent.InstallInitialProcedure (p) END InstallInitialProcedure ; @@ -559,24 +507,11 @@ END Length ; (* - InitProcList - initialize the head and tail pointers to NIL. -*) - -PROCEDURE InitProcList (VAR p: ProcedureList) ; -BEGIN - p.head := NIL ; - p.tail := NIL -END InitProcList ; - - -(* Init - initialize the initial, terminate procedure lists and booleans. *) PROCEDURE Init ; BEGIN - InitProcList (InitialProc) ; - InitProcList (TerminateProc) ; ExitValue := 0 ; isHalting := FALSE ; CallExit := FALSE (* default by calling abort *) -- cgit v1.1 From ad0f4ef6f74741ea6178a8b795e49effc2bc2a9c Mon Sep 17 00:00:00 2001 From: Nathaniel Shead Date: Sun, 3 Mar 2024 23:48:17 +1100 Subject: c++: Support exporting using-decls in same namespace as target Currently a using-declaration bringing a name into its own namespace is a no-op, except for functions. This prevents people from being able to redeclare a name brought in from the GMF as exported, however, which this patch fixes. Apart from marking declarations as exported they are also now marked as effectively being in the module purview (due to the using-decl) so that they are properly processed, as 'add_binding_entity' assumes that declarations not in the module purview cannot possibly be exported. gcc/cp/ChangeLog: * name-lookup.cc (walk_module_binding): Remove completed FIXME. (do_nonmember_using_decl): Mark redeclared entities as exported when needed. Check for re-exporting internal linkage types. gcc/testsuite/ChangeLog: * g++.dg/modules/using-12.C: New test. * g++.dg/modules/using-13.h: New test. * g++.dg/modules/using-13_a.C: New test. * g++.dg/modules/using-13_b.C: New test. Signed-off-by: Nathaniel Shead --- gcc/cp/name-lookup.cc | 50 +++++++++++++++++---- gcc/testsuite/g++.dg/modules/using-12.C | 73 +++++++++++++++++++++++++++++++ gcc/testsuite/g++.dg/modules/using-13.h | 16 +++++++ gcc/testsuite/g++.dg/modules/using-13_a.C | 15 +++++++ gcc/testsuite/g++.dg/modules/using-13_b.C | 20 +++++++++ 5 files changed, 166 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/g++.dg/modules/using-12.C create mode 100644 gcc/testsuite/g++.dg/modules/using-13.h create mode 100644 gcc/testsuite/g++.dg/modules/using-13_a.C create mode 100644 gcc/testsuite/g++.dg/modules/using-13_b.C (limited to 'gcc') diff --git a/gcc/cp/name-lookup.cc b/gcc/cp/name-lookup.cc index 6444db3..dce4caf 100644 --- a/gcc/cp/name-lookup.cc +++ b/gcc/cp/name-lookup.cc @@ -4189,7 +4189,7 @@ walk_module_binding (tree binding, bitmap partitions, void *data) { // FIXME: We don't quite deal with using decls naming stat hack - // type. Also using decls exporting something from the same scope. + // type. tree current = binding; unsigned count = 0; @@ -5238,13 +5238,36 @@ do_nonmember_using_decl (name_lookup &lookup, bool fn_scope_p, } else if (insert_p) { - value = lookup.value; - if (revealing_p && module_exporting_p ()) - check_can_export_using_decl (value); + if (revealing_p + && module_exporting_p () + && check_can_export_using_decl (lookup.value) + && lookup.value == value + && !DECL_MODULE_EXPORT_P (value)) + { + /* We're redeclaring the same value, but this time as + newly exported: make sure to mark it as such. */ + if (TREE_CODE (value) == TEMPLATE_DECL) + { + DECL_MODULE_EXPORT_P (value) = true; + + tree result = DECL_TEMPLATE_RESULT (value); + retrofit_lang_decl (result); + DECL_MODULE_PURVIEW_P (result) = true; + DECL_MODULE_EXPORT_P (result) = true; + } + else + { + retrofit_lang_decl (value); + DECL_MODULE_PURVIEW_P (value) = true; + DECL_MODULE_EXPORT_P (value) = true; + } + } + else + value = lookup.value; } /* Now the type binding. */ - if (lookup.type && lookup.type != type) + if (lookup.type) { if (type && !decls_match (lookup.type, type)) { @@ -5253,9 +5276,20 @@ do_nonmember_using_decl (name_lookup &lookup, bool fn_scope_p, } else if (insert_p) { - type = lookup.type; - if (revealing_p && module_exporting_p ()) - check_can_export_using_decl (type); + if (revealing_p + && module_exporting_p () + && check_can_export_using_decl (lookup.type) + && lookup.type == type + && !DECL_MODULE_EXPORT_P (type)) + { + /* We're redeclaring the same type, but this time as + newly exported: make sure to mark it as such. */ + retrofit_lang_decl (type); + DECL_MODULE_PURVIEW_P (type) = true; + DECL_MODULE_EXPORT_P (type) = true; + } + else + type = lookup.type; } } diff --git a/gcc/testsuite/g++.dg/modules/using-12.C b/gcc/testsuite/g++.dg/modules/using-12.C new file mode 100644 index 0000000..54eacf7 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/using-12.C @@ -0,0 +1,73 @@ +// { dg-additional-options "-fmodules-ts" } +// { dg-module-cmi !bad } + +// Like using-10.C, but test exporting names within the same namespace. + +export module bad; + +// internal linkage +namespace s { + namespace { + struct a1 {}; // { dg-message "declared here with internal linkage" } + + template + struct b1; // { dg-message "declared here with internal linkage" } + + int x1; // { dg-message "declared here with internal linkage" } + + template + T y1; // { dg-message "declared here with internal linkage" } + + void f1(); // { dg-message "declared here with internal linkage" } + + template + void g1(); // { dg-message "declared here with internal linkage" } + + export using s::a1; // { dg-error "does not have external linkage" } + export using s::b1; // { dg-error "does not have external linkage" } + export using s::x1; // { dg-error "does not have external linkage" } + export using s::y1; // { dg-error "does not have external linkage" } + export using s::f1; // { dg-error "does not have external linkage" } + export using s::g1; // { dg-error "does not have external linkage" } + } +} + +// module linkage +namespace m { + struct a2 {}; // { dg-message "declared here with module linkage" } + + template + struct b2; // { dg-message "declared here with module linkage" } + + int x2; // { dg-message "declared here with module linkage" } + + template + T y2; // { dg-message "declared here with module linkage" } + + void f2(); // { dg-message "declared here with module linkage" } + + template + void g2(); // { dg-message "declared here with module linkage" } + + export using m::a2; // { dg-error "does not have external linkage" } + export using m::b2; // { dg-error "does not have external linkage" } + export using m::x2; // { dg-error "does not have external linkage" } + export using m::y2; // { dg-error "does not have external linkage" } + export using m::f2; // { dg-error "does not have external linkage" } + export using m::g2; // { dg-error "does not have external linkage" } +} + +namespace t { + using a = int; // { dg-message "declared here with no linkage" } + + template + using b = int; // { dg-message "declared here with no linkage" } + + typedef int c; // { dg-message "declared here with no linkage" } + + export using t::a; // { dg-error "does not have external linkage" } + export using t::b; // { dg-error "does not have external linkage" } + export using t::c; // { dg-error "does not have external linkage" } +} + +// { dg-prune-output "not writing module" } diff --git a/gcc/testsuite/g++.dg/modules/using-13.h b/gcc/testsuite/g++.dg/modules/using-13.h new file mode 100644 index 0000000..b8ef2a1 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/using-13.h @@ -0,0 +1,16 @@ +// Like using-11.h, but additional kinds of declarations. + +struct A {}; + +template struct B {}; +template <> struct B { using foo = int; }; +template struct B { using bar = T; }; + +using C = int; + +inline int D = 0; + +#if __cpp_concepts >= 201907L +template +concept E = true; +#endif diff --git a/gcc/testsuite/g++.dg/modules/using-13_a.C b/gcc/testsuite/g++.dg/modules/using-13_a.C new file mode 100644 index 0000000..fed33ac --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/using-13_a.C @@ -0,0 +1,15 @@ +// { dg-additional-options "-fmodules-ts" } +// { dg-module-cmi M } + +module; +#include "using-13.h" + +export module M; +export using ::A; +export using ::B; +export using ::C; +export using ::D; + +#if __cpp_concepts >= 201907L +export using ::E; +#endif diff --git a/gcc/testsuite/g++.dg/modules/using-13_b.C b/gcc/testsuite/g++.dg/modules/using-13_b.C new file mode 100644 index 0000000..49fa09d --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/using-13_b.C @@ -0,0 +1,20 @@ +// { dg-additional-options "-fmodules-ts" } + +import M; + +int main() { + A a; + + // Check all specialisations are correctly exported + B b; + B::foo b1; + B::bar b2; + + C c; + + auto d = D; + +#if __cpp_concepts >= 201907L + auto e = E; +#endif +} -- cgit v1.1 From 264e3ad419cf71b10e7951a23750ac3507e21df9 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Tue, 5 Mar 2024 00:18:04 +0000 Subject: Daily bump. --- gcc/ChangeLog | 323 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 4 + gcc/cp/ChangeLog | 6 + gcc/m2/ChangeLog | 36 ++++++ gcc/po/ChangeLog | 4 + gcc/rust/ChangeLog | 4 + gcc/testsuite/ChangeLog | 50 ++++++++ 8 files changed, 428 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 321c6b0..5eb0d89 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,326 @@ +2024-03-04 David Faust + + * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype. + * config/bpf/bpf.cc (bpf_expand_setmem): New. + * config/bpf/bpf.md (setmemdi): New define_expand. + +2024-03-04 Jakub Jelinek + + PR rtl-optimization/113010 + * combine.cc (simplify_comparison): Guard the + WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG + and initialize inner_mode. + +2024-03-04 Andre Vieira + + * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U, + VMLALDAVAXQ_U cases. + (VMLALDAVXQ): Remove iterator. + (VMLALDAVXQ_P): Likewise. + (VMLALDAVAXQ): Likewise. + * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of + mode iterator attribute with V4BI mode. + * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U, + VMLALDAVAXQ_U): Remove unused unspecs. + +2024-03-04 Andre Vieira + + * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute. + * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator + attribute. + * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u, + vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u, + vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u, + vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s, + vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s, + vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u, + vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u, + vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s, + vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s, + vmlsldavaxq_s): Added mve_safe_imp_xlane_pred. + +2024-03-04 Stam Markianos-Wright + + * config/arm/arm.md (mve_unpredicated_insn): New attribute. + * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define. + (MVE_VPT_UNPREDICATED_INSN_P): Likewise. + (MVE_VPT_PREDICABLE_INSN_P): Likewise. + * config/arm/vec-common.md (mve_vshlq_): Add attribute. + * config/arm/mve.md (arm_vcx1q_p_v16qi): Add attribute. + (arm_vcx1qv16qi): Likewise. + (arm_vcx1qav16qi): Likewise. + (arm_vcx1qv16qi): Likewise. + (arm_vcx2q_p_v16qi): Likewise. + (arm_vcx2qv16qi): Likewise. + (arm_vcx2qav16qi): Likewise. + (arm_vcx2qv16qi): Likewise. + (arm_vcx3q_p_v16qi): Likewise. + (arm_vcx3qv16qi): Likewise. + (arm_vcx3qav16qi): Likewise. + (arm_vcx3qv16qi): Likewise. + (@mve_q_): Likewise. + (@mve_q_int_): Likewise. + (@mve_q_v4si): Likewise. + (@mve_q_n_): Likewise. + (@mve_q_r_): Likewise. + (@mve_q_f): Likewise. + (@mve_q_m_): Likewise. + (@mve_q_m_n_): Likewise. + (@mve_q_m_r_): Likewise. + (@mve_q_m_f): Likewise. + (@mve_q_int_m_): Likewise. + (@mve_q_p_v4si): Likewise. + (@mve_q_p_): Likewise. + (@mve_q_): Likewise. + (@mve_q_f): Likewise. + (@mve_q_m_): Likewise. + (@mve_q_m_f): Likewise. + (mve_vq_f): Likewise. + (mve_q): Likewise. + (mve_q_f): Likewise. + (mve_vadciq_v4si): Likewise. + (mve_vadciq_m_v4si): Likewise. + (mve_vadcq_v4si): Likewise. + (mve_vadcq_m_v4si): Likewise. + (mve_vandq_): Likewise. + (mve_vandq_f): Likewise. + (mve_vandq_m_): Likewise. + (mve_vandq_m_f): Likewise. + (mve_vandq_s): Likewise. + (mve_vandq_u): Likewise. + (mve_vbicq_): Likewise. + (mve_vbicq_f): Likewise. + (mve_vbicq_m_): Likewise. + (mve_vbicq_m_f): Likewise. + (mve_vbicq_m_n_): Likewise. + (mve_vbicq_n_): Likewise. + (mve_vbicq_s): Likewise. + (mve_vbicq_u): Likewise. + (@mve_vclzq_s): Likewise. + (mve_vclzq_u): Likewise. + (@mve_vcmp_q_): Likewise. + (@mve_vcmp_q_n_): Likewise. + (@mve_vcmp_q_f): Likewise. + (@mve_vcmp_q_n_f): Likewise. + (@mve_vcmp_q_m_f): Likewise. + (@mve_vcmp_q_m_n_): Likewise. + (@mve_vcmp_q_m_): Likewise. + (@mve_vcmp_q_m_n_f): Likewise. + (mve_vctpq): Likewise. + (mve_vctpq_m): Likewise. + (mve_vcvtaq_): Likewise. + (mve_vcvtaq_m_): Likewise. + (mve_vcvtbq_f16_f32v8hf): Likewise. + (mve_vcvtbq_f32_f16v4sf): Likewise. + (mve_vcvtbq_m_f16_f32v8hf): Likewise. + (mve_vcvtbq_m_f32_f16v4sf): Likewise. + (mve_vcvtmq_): Likewise. + (mve_vcvtmq_m_): Likewise. + (mve_vcvtnq_): Likewise. + (mve_vcvtnq_m_): Likewise. + (mve_vcvtpq_): Likewise. + (mve_vcvtpq_m_): Likewise. + (mve_vcvtq_from_f_): Likewise. + (mve_vcvtq_m_from_f_): Likewise. + (mve_vcvtq_m_n_from_f_): Likewise. + (mve_vcvtq_m_n_to_f_): Likewise. + (mve_vcvtq_m_to_f_): Likewise. + (mve_vcvtq_n_from_f_): Likewise. + (mve_vcvtq_n_to_f_): Likewise. + (mve_vcvtq_to_f_): Likewise. + (mve_vcvttq_f16_f32v8hf): Likewise. + (mve_vcvttq_f32_f16v4sf): Likewise. + (mve_vcvttq_m_f16_f32v8hf): Likewise. + (mve_vcvttq_m_f32_f16v4sf): Likewise. + (mve_vdwdupq_m_wb_u_insn): Likewise. + (mve_vdwdupq_wb_u_insn): Likewise. + (mve_veorq_s>): Likewise. + (mve_veorq_u>): Likewise. + (mve_veorq_f): Likewise. + (mve_vidupq_m_wb_u_insn): Likewise. + (mve_vidupq_u_insn): Likewise. + (mve_viwdupq_m_wb_u_insn): Likewise. + (mve_viwdupq_wb_u_insn): Likewise. + (mve_vldrbq_): Likewise. + (mve_vldrbq_gather_offset_): Likewise. + (mve_vldrbq_gather_offset_z_): Likewise. + (mve_vldrbq_z_): Likewise. + (mve_vldrdq_gather_base_v2di): Likewise. + (mve_vldrdq_gather_base_wb_v2di_insn): Likewise. + (mve_vldrdq_gather_base_wb_z_v2di_insn): Likewise. + (mve_vldrdq_gather_base_z_v2di): Likewise. + (mve_vldrdq_gather_offset_v2di): Likewise. + (mve_vldrdq_gather_offset_z_v2di): Likewise. + (mve_vldrdq_gather_shifted_offset_v2di): Likewise. + (mve_vldrdq_gather_shifted_offset_z_v2di): Likewise. + (mve_vldrhq_): Likewise. + (mve_vldrhq_fv8hf): Likewise. + (mve_vldrhq_gather_offset_): Likewise. + (mve_vldrhq_gather_offset_fv8hf): Likewise. + (mve_vldrhq_gather_offset_z_): Likewise. + (mve_vldrhq_gather_offset_z_fv8hf): Likewise. + (mve_vldrhq_gather_shifted_offset_): Likewise. + (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise. + (mve_vldrhq_gather_shifted_offset_z_): Likewise. + (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise. + (mve_vldrhq_z_): Likewise. + (mve_vldrhq_z_fv8hf): Likewise. + (mve_vldrwq_v4si): Likewise. + (mve_vldrwq_fv4sf): Likewise. + (mve_vldrwq_gather_base_v4si): Likewise. + (mve_vldrwq_gather_base_fv4sf): Likewise. + (mve_vldrwq_gather_base_wb_v4si_insn): Likewise. + (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise. + (mve_vldrwq_gather_base_wb_z_v4si_insn): Likewise. + (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise. + (mve_vldrwq_gather_base_z_v4si): Likewise. + (mve_vldrwq_gather_base_z_fv4sf): Likewise. + (mve_vldrwq_gather_offset_v4si): Likewise. + (mve_vldrwq_gather_offset_fv4sf): Likewise. + (mve_vldrwq_gather_offset_z_v4si): Likewise. + (mve_vldrwq_gather_offset_z_fv4sf): Likewise. + (mve_vldrwq_gather_shifted_offset_v4si): Likewise. + (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise. + (mve_vldrwq_gather_shifted_offset_z_v4si): Likewise. + (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise. + (mve_vldrwq_z_v4si): Likewise. + (mve_vldrwq_z_fv4sf): Likewise. + (mve_vmvnq_s): Likewise. + (mve_vmvnq_u): Likewise. + (mve_vornq_): Likewise. + (mve_vornq_f): Likewise. + (mve_vornq_m_): Likewise. + (mve_vornq_m_f): Likewise. + (mve_vornq_s): Likewise. + (mve_vornq_u): Likewise. + (mve_vorrq_): Likewise. + (mve_vorrq_f): Likewise. + (mve_vorrq_m_): Likewise. + (mve_vorrq_m_f): Likewise. + (mve_vorrq_m_n_): Likewise. + (mve_vorrq_n_): Likewise. + (mve_vorrq_s): Likewise. + (mve_vorrq_s): Likewise. + (mve_vsbciq_v4si): Likewise. + (mve_vsbciq_m_v4si): Likewise. + (mve_vsbcq_v4si): Likewise. + (mve_vsbcq_m_v4si): Likewise. + (mve_vshlcq_): Likewise. + (mve_vshlcq_m_): Likewise. + (mve_vshrq_m_n_): Likewise. + (mve_vshrq_n_): Likewise. + (mve_vstrbq_): Likewise. + (mve_vstrbq_p_): Likewise. + (mve_vstrbq_scatter_offset__insn): Likewise. + (mve_vstrbq_scatter_offset_p__insn): Likewise. + (mve_vstrdq_scatter_base_v2di): Likewise. + (mve_vstrdq_scatter_base_p_v2di): Likewise. + (mve_vstrdq_scatter_base_wb_v2di): Likewise. + (mve_vstrdq_scatter_base_wb_p_v2di): Likewise. + (mve_vstrdq_scatter_offset_v2di_insn): Likewise. + (mve_vstrdq_scatter_offset_p_v2di_insn): Likewise. + (mve_vstrdq_scatter_shifted_offset_v2di_insn): Likewise. + (mve_vstrdq_scatter_shifted_offset_p_v2di_insn): Likewise. + (mve_vstrhq_): Likewise. + (mve_vstrhq_fv8hf): Likewise. + (mve_vstrhq_p_): Likewise. + (mve_vstrhq_p_fv8hf): Likewise. + (mve_vstrhq_scatter_offset__insn): Likewise. + (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise. + (mve_vstrhq_scatter_offset_p__insn): Likewise. + (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise. + (mve_vstrhq_scatter_shifted_offset__insn): Likewise. + (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise. + (mve_vstrhq_scatter_shifted_offset_p__insn): Likewise. + (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise. + (mve_vstrwq_v4si): Likewise. + (mve_vstrwq_fv4sf): Likewise. + (mve_vstrwq_p_v4si): Likewise. + (mve_vstrwq_p_fv4sf): Likewise. + (mve_vstrwq_scatter_base_v4si): Likewise. + (mve_vstrwq_scatter_base_fv4sf): Likewise. + (mve_vstrwq_scatter_base_p_v4si): Likewise. + (mve_vstrwq_scatter_base_p_fv4sf): Likewise. + (mve_vstrwq_scatter_base_wb_v4si): Likewise. + (mve_vstrwq_scatter_base_wb_fv4sf): Likewise. + (mve_vstrwq_scatter_base_wb_p_v4si): Likewise. + (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise. + (mve_vstrwq_scatter_offset_v4si_insn): Likewise. + (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise. + (mve_vstrwq_scatter_offset_p_v4si_insn): Likewise. + (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise. + (mve_vstrwq_scatter_shifted_offset_v4si_insn): Likewise. + (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise. + (mve_vstrwq_scatter_shifted_offset_p_v4si_insn): Likewise. + (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise. + +2024-03-04 Marek Polacek + + * doc/extend.texi: Update [[gnu::no_dangling]]. + +2024-03-04 Andrew Stubbs + + * dojump.cc (do_compare_and_jump): Use full-width integers for shifts. + * expr.cc (store_constructor): Likewise. + (do_store_flag): Likewise. + +2024-03-04 Mark Wielaard + + * common.opt.urls: Regenerate. + * config/avr/avr.opt.urls: Likewise. + * config/i386/i386.opt.urls: Likewise. + * config/pru/pru.opt.urls: Likewise. + * config/riscv/riscv.opt.urls: Likewise. + * config/rs6000/rs6000.opt.urls: Likewise. + +2024-03-04 Richard Biener + + PR tree-optimization/114197 + * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if + there are volatile bitfield accesses. + (pass_if_conversion::execute): Throw away result if the + if-converted and original loops are not nested as expected. + +2024-03-04 Richard Biener + + PR tree-optimization/114164 + * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if + the code generated for mask argument setup is not supported. + +2024-03-04 Richard Biener + + PR tree-optimization/114203 + * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ + adjustment before making the result defined at zero. + +2024-03-04 Richard Biener + + PR tree-optimization/114192 + * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the + appropriate def for the live out stmt in case of an alternate + exit. + +2024-03-04 Jakub Jelinek + + PR middle-end/114209 + * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call + unshare_expr when creating a MEM_REF from MEM_REF. + (bitint_large_huge::lower_stmt): Call unshare_expr. + +2024-03-04 Jakub Jelinek + + PR target/114184 + * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1 + is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or + register. + +2024-03-04 Roger Sayle + + PR target/114187 + * simplify-rtx.cc (simplify_context::simplify_subreg): Call + lowpart_subreg to perform type conversion, to avoid confusion + over the offset to use in the call to simplify_reg_subreg. + 2024-03-03 Greg McGary PR rtl-optimization/113010 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index e000c3c..8585b3d 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240304 +20240305 diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index 6a81681..a8f5bfb 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,7 @@ +2024-03-04 Mark Wielaard + + * c.opt.urls: Regenerate. + 2024-02-22 Jakub Jelinek PR c/114007 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 347e55c7..e6a6fbd 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2024-03-04 Nathaniel Shead + + * name-lookup.cc (walk_module_binding): Remove completed FIXME. + (do_nonmember_using_decl): Mark redeclared entities as exported + when needed. Check for re-exporting internal linkage types. + 2024-03-01 Patrick Palka PR c++/104919 diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog index 3adc420..95188be 100644 --- a/gcc/m2/ChangeLog +++ b/gcc/m2/ChangeLog @@ -1,3 +1,39 @@ +2024-03-04 Gaius Mulley + + PR modula2/114227 + * gm2-libs-iso/M2RTS.mod (ProcedureChain): Remove. + (ProcedureList): Remove. + (ExecuteReverse): Remove. + (ExecuteTerminationProcedures): Rewrite. + (ExecuteInitialProcedures): Rewrite. + (AppendProc): Remove. + (InstallTerminationProcedure): Rewrite. + (InstallInitialProcedure): Rewrite. + (InitProcList): Remove. + * gm2-libs/M2Dependent.def (InstallTerminationProcedure): + New procedure. + (ExecuteTerminationProcedures): New procedure. + (InstallInitialProcedure): New procedure. + (ExecuteInitialProcedures): New procedure. + * gm2-libs/M2Dependent.mod (ProcedureChain): New type. + (ProcedureList): New type. + (ExecuteReverse): New procedure. + (ExecuteTerminationProcedures): New procedure. + (ExecuteInitialProcedures): New procedure. + (AppendProc): New procedure. + (InstallTerminationProcedure): New procedure. + (InstallInitialProcedure): New procedure. + (InitProcList): New procedure. + * gm2-libs/M2RTS.mod (ProcedureChain): Remove. + (ProcedureList): Remove. + (ExecuteReverse): Remove. + (ExecuteTerminationProcedures): Rewrite. + (ExecuteInitialProcedures): Rewrite. + (AppendProc): Remove. + (InstallTerminationProcedure): Rewrite. + (InstallInitialProcedure): Rewrite. + (InitProcList): Remove. + 2024-02-25 Gaius Mulley PR modula2/113749 diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index c6cda1e..4d2e8b9 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2024-03-04 Joseph Myers + + * sv.po: Update. + 2024-02-26 Joseph Myers * sv.po, zh_CN.po: Update. diff --git a/gcc/rust/ChangeLog b/gcc/rust/ChangeLog index c8049e3..b37ca0e 100644 --- a/gcc/rust/ChangeLog +++ b/gcc/rust/ChangeLog @@ -1,3 +1,7 @@ +2024-03-04 Mark Wielaard + + * lang.opt.urls: Regenerate. + 2024-02-21 0xn4utilus * checks/errors/rust-ast-validation.cc (ASTValidation::visit): diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 297ea5c..5379865 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,53 @@ +2024-03-04 Nathaniel Shead + + * g++.dg/modules/using-12.C: New test. + * g++.dg/modules/using-13.h: New test. + * g++.dg/modules/using-13_a.C: New test. + * g++.dg/modules/using-13_b.C: New test. + +2024-03-04 David Faust + + * gcc.target/bpf/memset-1.c: New test. + +2024-03-04 Jan Dubiec + + * gcc.c-torture/execute/20101011-1.c: Do not test on H8 series. + +2024-03-04 Richard Biener + + PR tree-optimization/114197 + * gcc.dg/torture/pr114197.c: New testcase. + +2024-03-04 Richard Biener + + PR tree-optimization/114203 + * gcc.dg/torture/pr114203.c: New testcase. + +2024-03-04 Jakub Jelinek + + PR middle-end/114209 + * gcc.dg/bitint-97.c: New test. + +2024-03-04 Xi Ruoyao + + PR testsuite/113418 + * gcc.dg/pr104992.c (dg-options): Use -fdump-tree-forwprop2 + instead of -fdump-tree-optimized. + (dg-final): Scan forwprop2 dump instead of optimized, and remove + the use of vect_int_mod. + * lib/target-supports.exp (check_effective_target_vect_int_mod): + Remove because it's not used anymore. + +2024-03-04 Jakub Jelinek + + PR target/114184 + * gcc.target/i386/pr114184.c: New test. + +2024-03-04 Roger Sayle + + PR target/114187 + * g++.target/i386/pr114187.C: New test case. + 2024-03-03 Greg McGary * gcc.c-torture/execute/pr113010.c: New test. -- cgit v1.1 From 08edf85f747b9ac1850f9688c8a1bc7c2bf6b4e5 Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Mon, 4 Mar 2024 21:32:44 -0500 Subject: c++/modules: relax diagnostic about GMF contents Issuing a hard error when the GMF doesn't consist only of preprocessing directives happens to be inconvenient for automated testcase reduction via cvise. This patch relaxes this diagnostic into a pedwarn that can be disabled with -Wno-global-module. gcc/c-family/ChangeLog: * c.opt (Wglobal-module): New warning. gcc/cp/ChangeLog: * parser.cc (cp_parser_translation_unit): Relax GMF contents error into a pedwarn. gcc/ChangeLog: * doc/invoke.texi (-Wno-global-module): Document. gcc/testsuite/ChangeLog: * g++.dg/modules/friend-6_a.C: Pass -Wno-global-module instead of -Wno-pedantic. Remove now unnecessary preprocessing directives from GMF. Reviewed-by: Jason Merrill --- gcc/c-family/c.opt | 4 ++++ gcc/cp/parser.cc | 6 +++--- gcc/doc/invoke.texi | 8 +++++++- gcc/testsuite/g++.dg/modules/friend-6_a.C | 4 +--- 4 files changed, 15 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt index b7a4a1a..56cccf2 100644 --- a/gcc/c-family/c.opt +++ b/gcc/c-family/c.opt @@ -802,6 +802,10 @@ Wframe-address C ObjC C++ ObjC++ Var(warn_frame_address) Warning LangEnabledBy(C ObjC C++ ObjC++,Wall) Warn when __builtin_frame_address or __builtin_return_address is used unsafely. +Wglobal-module +C++ ObjC++ Var(warn_global_module) Warning Init(1) +Warn about the global module fragment not containing only preprocessing directives. + Wif-not-aligned C ObjC C++ ObjC++ Var(warn_if_not_aligned) Init(1) Warning Warn when the field in a struct is not aligned. diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc index a310b9e..e32acfc 100644 --- a/gcc/cp/parser.cc +++ b/gcc/cp/parser.cc @@ -5253,9 +5253,9 @@ cp_parser_translation_unit (cp_parser* parser) if (!warned) { warned = true; - error_at (token->location, - "global module fragment contents must be" - " from preprocessor inclusion"); + pedwarn (token->location, OPT_Wglobal_module, + "global module fragment contents must be" + " from preprocessor inclusion"); } } } diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index bdf05be..2390d47 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -256,7 +256,7 @@ in the following sections. -Wdeprecated-copy -Wdeprecated-copy-dtor -Wno-deprecated-enum-enum-conversion -Wno-deprecated-enum-float-conversion -Weffc++ -Wno-elaborated-enum-base --Wno-exceptions -Wextra-semi -Wno-inaccessible-base +-Wno-exceptions -Wextra-semi -Wno-global-module -Wno-inaccessible-base -Wno-inherited-variadic-ctor -Wno-init-list-lifetime -Winvalid-constexpr -Winvalid-imported-macros -Wno-invalid-offsetof -Wno-literal-suffix @@ -4774,6 +4774,12 @@ undefined behavior at runtime. This warning is enabled by default. @item -Wextra-semi @r{(C++, Objective-C++ only)} Warn about redundant semicolons after in-class function definitions. +@opindex Wno-global-module +@opindex Wglobal-module +@item -Wno-global-module @r{(C++ and Objective-C++ only)} +Disable the diagnostic for when the global module fragment of a module +unit does not consist only of preprocessor directives. + @opindex Winaccessible-base @opindex Wno-inaccessible-base @item -Wno-inaccessible-base @r{(C++, Objective-C++ only)} diff --git a/gcc/testsuite/g++.dg/modules/friend-6_a.C b/gcc/testsuite/g++.dg/modules/friend-6_a.C index 7493e8f..13f7710 100644 --- a/gcc/testsuite/g++.dg/modules/friend-6_a.C +++ b/gcc/testsuite/g++.dg/modules/friend-6_a.C @@ -1,11 +1,9 @@ -// { dg-additional-options "-fmodules-ts -Wno-pedantic" } +// { dg-additional-options "-fmodules-ts -Wno-global-module" } // { dg-module-cmi friend_6 } module; -# 1 "" 1 template struct Trans_NS___cxx11_basic_string { template friend class basic_stringbuf; }; template struct Trans_NS___cxx11_basic_string; -# 6 "" 2 export module friend_6; -- cgit v1.1 From 1a8dde963590b415768b070bd309b188858dc589 Mon Sep 17 00:00:00 2001 From: Pan Li Date: Tue, 5 Mar 2024 15:29:15 +0800 Subject: RISC-V: Cleanup unused code in riscv_v_adjust_bytesize [NFC] Cleanup mode_size related code which is not used anymore. Below tests are passed for this patch. * The RVV fully regresssion test. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused mode_size related code. Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 4 ---- 1 file changed, 4 deletions(-) (limited to 'gcc') diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 56cd8d2..691d967 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1527,10 +1527,6 @@ riscv_v_adjust_bytesize (machine_mode mode, int scale) return BYTES_PER_RISCV_VECTOR; poly_int64 nunits = GET_MODE_NUNITS (mode); - poly_int64 mode_size = GET_MODE_SIZE (mode); - - if (maybe_eq (mode_size, (uint16_t) -1)) - mode_size = riscv_vector_chunks * scale; if (nunits.coeffs[0] > 8) return exact_div (nunits, 8); -- cgit v1.1 From 8ee6d13e32279faf9ef4fd8eabfba0adfca0dfb9 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 5 Mar 2024 10:24:51 +0100 Subject: i386: For noreturn functions save at least the bp register if it is used [PR114116] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As mentioned in the PR, on x86_64 currently a lot of ICEs end up with crashes in the unwinder like: during RTL pass: expand pr114044-2.c: In function ‘foo’: pr114044-2.c:5:3: internal compiler error: in expand_fn_using_insn, at internal-fn.cc:208 5 | __builtin_clzg (a); | ^~~~~~~~~~~~~~~~~~ 0x7d9246 expand_fn_using_insn ../../gcc/internal-fn.cc:208 pr114044-2.c:5:3: internal compiler error: Segmentation fault 0x1554262 crash_signal ../../gcc/toplev.cc:319 0x2b20320 x86_64_fallback_frame_state ./md-unwind-support.h:63 0x2b20320 uw_frame_state_for ../../../libgcc/unwind-dw2.c:1013 0x2b2165d _Unwind_Backtrace ../../../libgcc/unwind.inc:303 0x2acbd69 backtrace_full ../../libbacktrace/backtrace.c:127 0x2a32fa6 diagnostic_context::action_after_output(diagnostic_t) ../../gcc/diagnostic.cc:781 0x2a331bb diagnostic_action_after_output(diagnostic_context*, diagnostic_t) ../../gcc/diagnostic.h:1002 0x2a331bb diagnostic_context::report_diagnostic(diagnostic_info*) ../../gcc/diagnostic.cc:1633 0x2a33543 diagnostic_impl ../../gcc/diagnostic.cc:1767 0x2a33c26 internal_error(char const*, ...) ../../gcc/diagnostic.cc:2225 0xe232c8 fancy_abort(char const*, int, char const*) ../../gcc/diagnostic.cc:2336 0x7d9246 expand_fn_using_insn ../../gcc/internal-fn.cc:208 Segmentation fault (core dumped) The problem are the PR38534 r14-8470 changes which avoid saving call-saved registers in noreturn functions. If such functions ever touch the bp register but because of the r14-8470 changes don't save it in the prologue, the caller or any other function in the backtrace uses a frame pointer and the noreturn function or anything it calls directly or indirectly calls backtrace, then the unwinder crashes, because bp register contains some unrelated value, but in the frames which do use frame pointer CFA is based on the bp register. In theory this could happen with any other call-saved register, e.g. code written by hand in assembly with .cfi_* directives could use any other call-saved register as register into which store the CFA or something related to that, but in reality at least compiler generated code and usual assembly probably just making sure bp doesn't contain garbage could be enough for backtrace purposes. In the debugger of course it will not be enough, the values of the arguments etc. can be lost (if DW_CFA_undefined is emitted) or garbage. So, I think for noreturn function we should at least save the bp register if we use it. If user asks for it using no_callee_saved_registers attribute, let's honor what is asked for (but then it is up to the user to make sure e.g. backtrace isn't called from the function or anything it calls). As discussed in the PR, whether to save bp or not shouldn't be based on whether compiling with -g or -g0, because we don't want code generation changes without/with debugging, it would also break -fcompare-debug, and users can call backtrace(3), that doesn't use debug info, just unwind info, even backtrace_symbols{,_fd}(3) don't use debug info but just looks at dynamic symbol table. The patch also adds check for no_caller_saved_registers attribute in the implicit addition of not saving callee saved register in noreturn functions, because on I think __attribute__((no_caller_saved_registers, noreturn)) will otherwise error that no_caller_saved_registers and no_callee_saved_registers attributes are incompatible (but user didn't specify anything like that). 2024-03-05 Jakub Jelinek PR target/114116 * config/i386/i386.h (enum call_saved_registers_type): Add TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator. * config/i386/i386-options.cc (ix86_set_func_type): Remove has_no_callee_saved_registers variable, add no_callee_saved_registers instead, initialize it depending on whether it is no_callee_saved_registers function or not. Don't set it if no_caller_saved_registers attribute is present. Adjust users. * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like TYPE_NO_CALLEE_SAVED_REGISTERS. (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP. * gcc.target/i386/pr38534-1.c: Allow push/pop of bp. * gcc.target/i386/pr38534-4.c: Likewise. * gcc.target/i386/pr38534-2.c: Likewise. * gcc.target/i386/pr38534-3.c: Likewise. * gcc.target/i386/pr114097-1.c: Likewise. * gcc.target/i386/stack-check-17.c: Expect no pop on ! ia32. --- gcc/config/i386/i386-options.cc | 33 ++++++++++++++++---------- gcc/config/i386/i386.cc | 10 ++++++-- gcc/config/i386/i386.h | 7 ++++-- gcc/testsuite/gcc.target/i386/pr114097-1.c | 4 ++-- gcc/testsuite/gcc.target/i386/pr38534-1.c | 4 ++-- gcc/testsuite/gcc.target/i386/pr38534-2.c | 4 ++-- gcc/testsuite/gcc.target/i386/pr38534-3.c | 4 ++-- gcc/testsuite/gcc.target/i386/pr38534-4.c | 4 ++-- gcc/testsuite/gcc.target/i386/stack-check-17.c | 4 ++-- 9 files changed, 45 insertions(+), 29 deletions(-) (limited to 'gcc') diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 1301f6b..2f8c85f 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -3384,7 +3384,9 @@ ix86_set_func_type (tree fndecl) { /* No need to save and restore callee-saved registers for a noreturn function with nothrow or compiled with -fno-exceptions unless when - compiling with -O0 or -Og. + compiling with -O0 or -Og. So that backtrace works for those at least + in most cases, save the bp register if it is used, because it often + is used in callers to compute CFA. NB: Can't use just TREE_THIS_VOLATILE to check if this is a noreturn function. The local-pure-const pass turns an interrupt function @@ -3394,15 +3396,20 @@ ix86_set_func_type (tree fndecl) function is marked with TREE_THIS_VOLATILE in the IR output, which leads to the incompatible attribute error in LTO1. Ignore the interrupt function in this case. */ - bool has_no_callee_saved_registers - = ((TREE_THIS_VOLATILE (fndecl) - && !lookup_attribute ("interrupt", - TYPE_ATTRIBUTES (TREE_TYPE (fndecl))) - && optimize - && !optimize_debug - && (TREE_NOTHROW (fndecl) || !flag_exceptions)) - || lookup_attribute ("no_callee_saved_registers", - TYPE_ATTRIBUTES (TREE_TYPE (fndecl)))); + enum call_saved_registers_type no_callee_saved_registers + = TYPE_DEFAULT_CALL_SAVED_REGISTERS; + if (lookup_attribute ("no_callee_saved_registers", + TYPE_ATTRIBUTES (TREE_TYPE (fndecl)))) + no_callee_saved_registers = TYPE_NO_CALLEE_SAVED_REGISTERS; + else if (TREE_THIS_VOLATILE (fndecl) + && optimize + && !optimize_debug + && (TREE_NOTHROW (fndecl) || !flag_exceptions) + && !lookup_attribute ("interrupt", + TYPE_ATTRIBUTES (TREE_TYPE (fndecl))) + && !lookup_attribute ("no_caller_saved_registers", + TYPE_ATTRIBUTES (TREE_TYPE (fndecl)))) + no_callee_saved_registers = TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP; if (cfun->machine->func_type == TYPE_UNKNOWN) { @@ -3413,7 +3420,7 @@ ix86_set_func_type (tree fndecl) error_at (DECL_SOURCE_LOCATION (fndecl), "interrupt and naked attributes are not compatible"); - if (has_no_callee_saved_registers) + if (no_callee_saved_registers) error_at (DECL_SOURCE_LOCATION (fndecl), "%qs and %qs attributes are not compatible", "interrupt", "no_callee_saved_registers"); @@ -3442,7 +3449,7 @@ ix86_set_func_type (tree fndecl) TYPE_ATTRIBUTES (TREE_TYPE (fndecl)))) cfun->machine->call_saved_registers = TYPE_NO_CALLER_SAVED_REGISTERS; - if (has_no_callee_saved_registers) + if (no_callee_saved_registers) { if (cfun->machine->call_saved_registers == TYPE_NO_CALLER_SAVED_REGISTERS) @@ -3451,7 +3458,7 @@ ix86_set_func_type (tree fndecl) "no_caller_saved_registers", "no_callee_saved_registers"); cfun->machine->call_saved_registers - = TYPE_NO_CALLEE_SAVED_REGISTERS; + = no_callee_saved_registers; } } } diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index fc50685..4b6b665 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -984,8 +984,9 @@ ix86_function_ok_for_sibcall (tree decl, tree exp) /* Sibling call isn't OK if callee has no callee-saved registers and the calling function has callee-saved registers. */ - if ((cfun->machine->call_saved_registers - != TYPE_NO_CALLEE_SAVED_REGISTERS) + if (cfun->machine->call_saved_registers != TYPE_NO_CALLEE_SAVED_REGISTERS + && (cfun->machine->call_saved_registers + != TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP) && lookup_attribute ("no_callee_saved_registers", TYPE_ATTRIBUTES (type))) return false; @@ -6649,6 +6650,11 @@ ix86_save_reg (unsigned int regno, bool maybe_eh_return, bool ignore_outlined) case TYPE_NO_CALLEE_SAVED_REGISTERS: return false; + + case TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP: + if (regno != HARD_FRAME_POINTER_REGNUM) + return false; + break; } if (regno == REAL_PIC_OFFSET_TABLE_REGNUM diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 35ce8b0..efd46a1 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2730,9 +2730,12 @@ enum call_saved_registers_type /* The current function is a function specified with the "interrupt" or "no_caller_saved_registers" attribute. */ TYPE_NO_CALLER_SAVED_REGISTERS, + /* The current function is a function specified with the + "no_callee_saved_registers" attribute. */ + TYPE_NO_CALLEE_SAVED_REGISTERS, /* The current function is a function specified with the "noreturn" - or "no_callee_saved_registers" attribute. */ - TYPE_NO_CALLEE_SAVED_REGISTERS + attribute. */ + TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP, }; enum queued_insn_type diff --git a/gcc/testsuite/gcc.target/i386/pr114097-1.c b/gcc/testsuite/gcc.target/i386/pr114097-1.c index b14c7b6..feeb916 100644 --- a/gcc/testsuite/gcc.target/i386/pr114097-1.c +++ b/gcc/testsuite/gcc.target/i386/pr114097-1.c @@ -22,5 +22,5 @@ no_return_to_caller (void) while (1); } -/* { dg-final { scan-assembler-not "push" } } */ -/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler-not "push\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "pop\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr38534-1.c b/gcc/testsuite/gcc.target/i386/pr38534-1.c index 280f3b4..c73c8d2 100644 --- a/gcc/testsuite/gcc.target/i386/pr38534-1.c +++ b/gcc/testsuite/gcc.target/i386/pr38534-1.c @@ -22,5 +22,5 @@ no_return_to_caller (void) while (1); } -/* { dg-final { scan-assembler-not "push" } } */ -/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler-not "push\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "pop\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr38534-2.c b/gcc/testsuite/gcc.target/i386/pr38534-2.c index 2e19989..0dc8720 100644 --- a/gcc/testsuite/gcc.target/i386/pr38534-2.c +++ b/gcc/testsuite/gcc.target/i386/pr38534-2.c @@ -12,7 +12,7 @@ foo (void) fn (); } -/* { dg-final { scan-assembler-not "push" } } */ -/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler-not "push\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "pop\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ /* { dg-final { scan-assembler-not "jmp\[\\t \]+_?bar" } } */ /* { dg-final { scan-assembler "call\[\\t \]+_?bar" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr38534-3.c b/gcc/testsuite/gcc.target/i386/pr38534-3.c index af6e195..554c594 100644 --- a/gcc/testsuite/gcc.target/i386/pr38534-3.c +++ b/gcc/testsuite/gcc.target/i386/pr38534-3.c @@ -13,7 +13,7 @@ foo (void) fn (); } -/* { dg-final { scan-assembler-not "push" } } */ -/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler-not "push\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "pop\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ /* { dg-final { scan-assembler-not "jmp" } } */ /* { dg-final { scan-assembler "call\[\\t \]+" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr38534-4.c b/gcc/testsuite/gcc.target/i386/pr38534-4.c index b204789..8073aac 100644 --- a/gcc/testsuite/gcc.target/i386/pr38534-4.c +++ b/gcc/testsuite/gcc.target/i386/pr38534-4.c @@ -12,7 +12,7 @@ foo (fn_t bar) fn (); } -/* { dg-final { scan-assembler-not "push" } } */ -/* { dg-final { scan-assembler-not "pop" } } */ +/* { dg-final { scan-assembler-not "push\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ +/* { dg-final { scan-assembler-not "pop\[^\n\r\]*(?:\[abcd\]x|\[sd\]i|sp|r\[0-9\]|\[xyz\]mm)" } } */ /* { dg-final { scan-assembler-not "jmp" } } */ /* { dg-final { scan-assembler "call\[\\t \]+" } } */ diff --git a/gcc/testsuite/gcc.target/i386/stack-check-17.c b/gcc/testsuite/gcc.target/i386/stack-check-17.c index 061484e..648572e 100644 --- a/gcc/testsuite/gcc.target/i386/stack-check-17.c +++ b/gcc/testsuite/gcc.target/i386/stack-check-17.c @@ -32,5 +32,5 @@ f3 (void) register on ia32 for a noreturn function. */ /* { dg-final { scan-assembler-times "push\[ql\]" 1 { target { ! ia32 } } } } */ /* { dg-final { scan-assembler-times "push\[ql\]" 3 { target ia32 } } } */ -/* { dg-final { scan-assembler-times "pop" 1 } } */ - +/* { dg-final { scan-assembler-not "pop" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times "pop" 1 { target ia32 } } } */ -- cgit v1.1 From 9d2bc5def30830e685ae2e3c2f4d07b967e2be63 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 5 Mar 2024 10:27:14 +0100 Subject: bitint: Handle BIT_FIELD_REF lowering [PR114157] The following patch adds support for BIT_FIELD_REF lowering with large/huge _BitInt lhs. BIT_FIELD_REF requires mode argument first operand, so the operand shouldn't be any huge _BitInt. If we only access limbs from inside of BIT_FIELD_REF using constant indexes, we can just create a new BIT_FIELD_REF to extract the limb, but if we need to use variable index in a loop, I'm afraid we need to spill it into memory, which is what the following patch does. If there is some bitwise type for the extraction, it extracts just what we need and not more than that, otherwise it spills the whole first argument of BIT_FIELD_REF and uses MEM_REF with an offset with VIEW_CONVERT_EXPR around it. 2024-03-05 Jakub Jelinek PR middle-end/114157 * gimple-lower-bitint.cc: Include stor-layout.h. (mergeable_op): Return true for BIT_FIELD_REF. (struct bitint_large_huge): Declare handle_bit_field_ref method. (bitint_large_huge::handle_bit_field_ref): New method. (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF. * gcc.dg/bitint-98.c: New test. * gcc.target/i386/avx2-pr114157.c: New test. * gcc.target/i386/avx512f-pr114157.c: New test. --- gcc/gimple-lower-bitint.cc | 85 ++++++++++++++++++++++++ gcc/testsuite/gcc.dg/bitint-98.c | 50 ++++++++++++++ gcc/testsuite/gcc.target/i386/avx2-pr114157.c | 5 ++ gcc/testsuite/gcc.target/i386/avx512f-pr114157.c | 5 ++ 4 files changed, 145 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/bitint-98.c create mode 100644 gcc/testsuite/gcc.target/i386/avx2-pr114157.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr114157.c (limited to 'gcc') diff --git a/gcc/gimple-lower-bitint.cc b/gcc/gimple-lower-bitint.cc index e3c8518..65e4ab3 100644 --- a/gcc/gimple-lower-bitint.cc +++ b/gcc/gimple-lower-bitint.cc @@ -54,6 +54,7 @@ along with GCC; see the file COPYING3. If not see #include "tree-cfgcleanup.h" #include "tree-switch-conversion.h" #include "ubsan.h" +#include "stor-layout.h" #include "gimple-lower-bitint.h" /* Split BITINT_TYPE precisions in 4 categories. Small _BitInt, where @@ -212,6 +213,7 @@ mergeable_op (gimple *stmt) case BIT_NOT_EXPR: case SSA_NAME: case INTEGER_CST: + case BIT_FIELD_REF: return true; case LSHIFT_EXPR: { @@ -435,6 +437,7 @@ struct bitint_large_huge tree handle_plus_minus (tree_code, tree, tree, tree); tree handle_lshift (tree, tree, tree); tree handle_cast (tree, tree, tree); + tree handle_bit_field_ref (tree, tree); tree handle_load (gimple *, tree); tree handle_stmt (gimple *, tree); tree handle_operand_addr (tree, gimple *, int *, int *); @@ -1685,6 +1688,86 @@ bitint_large_huge::handle_cast (tree lhs_type, tree rhs1, tree idx) return NULL_TREE; } +/* Helper function for handle_stmt method, handle a BIT_FIELD_REF. */ + +tree +bitint_large_huge::handle_bit_field_ref (tree op, tree idx) +{ + if (tree_fits_uhwi_p (idx)) + { + if (m_first) + m_data.safe_push (NULL); + ++m_data_cnt; + unsigned HOST_WIDE_INT sz = tree_to_uhwi (TYPE_SIZE (m_limb_type)); + tree bfr = build3 (BIT_FIELD_REF, m_limb_type, + TREE_OPERAND (op, 0), + TYPE_SIZE (m_limb_type), + size_binop (PLUS_EXPR, TREE_OPERAND (op, 2), + bitsize_int (tree_to_uhwi (idx) * sz))); + tree r = make_ssa_name (m_limb_type); + gimple *g = gimple_build_assign (r, bfr); + insert_before (g); + tree type = limb_access_type (TREE_TYPE (op), idx); + if (!useless_type_conversion_p (type, m_limb_type)) + r = add_cast (type, r); + return r; + } + tree var; + if (m_first) + { + unsigned HOST_WIDE_INT sz = tree_to_uhwi (TYPE_SIZE (TREE_TYPE (op))); + machine_mode mode; + tree type, bfr; + if (bitwise_mode_for_size (sz).exists (&mode) + && known_eq (GET_MODE_BITSIZE (mode), sz)) + type = bitwise_type_for_mode (mode); + else + { + mode = VOIDmode; + type = TYPE_MAIN_VARIANT (TREE_TYPE (TREE_OPERAND (op, 0))); + } + if (TYPE_ALIGN (type) < TYPE_ALIGN (TREE_TYPE (op))) + type = build_aligned_type (type, TYPE_ALIGN (TREE_TYPE (op))); + var = create_tmp_var (type); + TREE_ADDRESSABLE (var) = 1; + gimple *g; + if (mode != VOIDmode) + { + bfr = build3 (BIT_FIELD_REF, type, TREE_OPERAND (op, 0), + TYPE_SIZE (type), TREE_OPERAND (op, 2)); + g = gimple_build_assign (make_ssa_name (type), + BIT_FIELD_REF, bfr); + gimple_set_location (g, m_loc); + gsi_insert_after (&m_init_gsi, g, GSI_NEW_STMT); + bfr = gimple_assign_lhs (g); + } + else + bfr = TREE_OPERAND (op, 0); + g = gimple_build_assign (var, bfr); + gimple_set_location (g, m_loc); + gsi_insert_after (&m_init_gsi, g, GSI_NEW_STMT); + if (mode == VOIDmode) + { + unsigned HOST_WIDE_INT nelts + = CEIL (tree_to_uhwi (TYPE_SIZE (TREE_TYPE (op))), limb_prec); + tree atype = build_array_type_nelts (m_limb_type, nelts); + var = build2 (MEM_REF, atype, build_fold_addr_expr (var), + build_int_cst (build_pointer_type (type), + tree_to_uhwi (TREE_OPERAND (op, 2)) + / BITS_PER_UNIT)); + } + m_data.safe_push (var); + } + else + var = unshare_expr (m_data[m_data_cnt]); + ++m_data_cnt; + var = limb_access (TREE_TYPE (op), var, idx, false); + tree r = make_ssa_name (m_limb_type); + gimple *g = gimple_build_assign (r, var); + insert_before (g); + return r; +} + /* Add a new EH edge from SRC to EH_EDGE->dest, where EH_EDGE is an older EH edge, and except for virtual PHIs duplicate the PHI argument from the EH_EDGE to the new EH edge. */ @@ -2019,6 +2102,8 @@ bitint_large_huge::handle_stmt (gimple *stmt, tree idx) return handle_cast (TREE_TYPE (gimple_assign_lhs (stmt)), TREE_OPERAND (gimple_assign_rhs1 (stmt), 0), idx); + case BIT_FIELD_REF: + return handle_bit_field_ref (gimple_assign_rhs1 (stmt), idx); default: break; } diff --git a/gcc/testsuite/gcc.dg/bitint-98.c b/gcc/testsuite/gcc.dg/bitint-98.c new file mode 100644 index 0000000..1861b36 --- /dev/null +++ b/gcc/testsuite/gcc.dg/bitint-98.c @@ -0,0 +1,50 @@ +/* PR middle-end/114157 */ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-O2 -std=c23 -Wno-psabi -w" } */ + +#if __BITINT_MAXWIDTH__ >= 256 +_BitInt(256) d; +_BitInt(255) e; + +void +foo (long __attribute__((vector_size (64))) s) +{ + __builtin_memmove (&d, &s, sizeof (d)); +} + +void +bar (_BitInt(512) x) +{ + long __attribute__((vector_size (64))) s; + __builtin_memcpy (&s, &x, sizeof (s)); + __builtin_memcpy (&d, &s, sizeof (d)); +} + +void +baz (long __attribute__((vector_size (64))) s) +{ + _BitInt(256) d; + __builtin_memmove (&d, &s, sizeof (d)); + e = d; +} + +void +qux (long __attribute__((vector_size (64))) s) +{ + _BitInt(192) d; + __builtin_memmove (&d, &s, sizeof (d)); + e = d; +} +#else +int i; +#endif + +#if __BITINT_MAXWIDTH__ >= 1024 +_BitInt(512) +corge (long __attribute__((vector_size (1024))) s) +{ + _BitInt(512) d; + __builtin_memcpy (&d, &s, sizeof (d)); + return d; +} +#endif diff --git a/gcc/testsuite/gcc.target/i386/avx2-pr114157.c b/gcc/testsuite/gcc.target/i386/avx2-pr114157.c new file mode 100644 index 0000000..d0509ad --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx2-pr114157.c @@ -0,0 +1,5 @@ +/* PR middle-end/114157 */ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-O2 -std=c23 -Wno-psabi -w -mavx2 -mno-avx512f" } */ + +#include "../../gcc.dg/bitint-98.c" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-pr114157.c b/gcc/testsuite/gcc.target/i386/avx512f-pr114157.c new file mode 100644 index 0000000..430a358 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-pr114157.c @@ -0,0 +1,5 @@ +/* PR middle-end/114157 */ +/* { dg-do compile { target bitint } } */ +/* { dg-options "-O2 -std=c23 -Wno-psabi -w -mavx512f" } */ + +#include "../../gcc.dg/bitint-98.c" -- cgit v1.1 From aed445b0fd0c7ed16124c61e7eb732992426f103 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 5 Mar 2024 10:32:38 +0100 Subject: lower-subreg: Fix ROTATE handling [PR114211] On the following testcase, we have (insn 10 7 11 2 (set (reg/v:TI 106 [ h ]) (rotate:TI (reg/v:TI 106 [ h ]) (const_int 64 [0x40]))) "pr114211.c":8:5 1042 {rotl64ti2_doubleword} (nil)) before subreg1 and the pass decides to use (reg:DI 127 [ h ]) / (reg:DI 128 [ h+8 ]) register pair instead of (reg/v:TI 106 [ h ]). resolve_operand_for_swap_move_operator implements it by pretending it is an assignment from (concatn (reg:DI 127 [ h ]) (reg:DI 128 [ h+8 ])) to (concatn (reg:DI 128 [ h+8 ]) (reg:DI 127 [ h ])) The problem is that if the rotate argument is the same as destination or if there is even an overlap between the first half of the destination with second half of the source we emit incorrect code, because the store to (reg:DI 128 [ h+8 ]) overwrites what we need for source of the second move. The following patch detects that case and uses a temporary pseudo to hold the original (reg:DI 128 [ h+8 ]) value across the first store. 2024-03-05 Jakub Jelinek PR rtl-optimization/114211 * lower-subreg.cc (resolve_simple_move): For double-word rotates by BITS_PER_WORD if there is overlap between source and destination use a temporary. * gcc.dg/pr114211.c: New test. --- gcc/lower-subreg.cc | 15 +++++++++++++++ gcc/testsuite/gcc.dg/pr114211.c | 23 +++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/pr114211.c (limited to 'gcc') diff --git a/gcc/lower-subreg.cc b/gcc/lower-subreg.cc index 05fb27c..2f7f0a8 100644 --- a/gcc/lower-subreg.cc +++ b/gcc/lower-subreg.cc @@ -927,6 +927,21 @@ resolve_simple_move (rtx set, rtx_insn *insn) SRC's operator. */ dest = resolve_operand_for_swap_move_operator (dest); src = src_op; + if (resolve_reg_p (src)) + { + gcc_assert (GET_CODE (src) == CONCATN); + if (reg_overlap_mentioned_p (XVECEXP (dest, 0, 0), + XVECEXP (src, 0, 1))) + { + /* If there is overlap betwee the first half of the + destination and what will be stored to the second one, + use a temporary pseudo. See PR114211. */ + rtx tem = gen_reg_rtx (GET_MODE (XVECEXP (src, 0, 1))); + emit_move_insn (tem, XVECEXP (src, 0, 1)); + src = copy_rtx (src); + XVECEXP (src, 0, 1) = tem; + } + } } else if (resolve_reg_p (src_op)) { diff --git a/gcc/testsuite/gcc.dg/pr114211.c b/gcc/testsuite/gcc.dg/pr114211.c new file mode 100644 index 0000000..691dae5 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr114211.c @@ -0,0 +1,23 @@ +/* PR rtl-optimization/114211 */ +/* { dg-do run { target int128 } } */ +/* { dg-options "-O -fno-tree-coalesce-vars -Wno-psabi" } */ + +typedef unsigned __int128 V __attribute__((__vector_size__ (16))); +unsigned int u; +V v; + +V +foo (unsigned __int128 h) +{ + h = h << 64 | h >> 64; + h *= ~u; + return h + v; +} + +int +main () +{ + V x = foo (1); + if (x[0] != (unsigned __int128) 0xffffffff << 64) + __builtin_abort (); +} -- cgit v1.1 From 7890836de20912bd92afaf5abbeaf9d8c5b86542 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Tue, 5 Mar 2024 10:55:56 +0100 Subject: tree-optimization/114231 - use patterns for BB SLP discovery root stmts The following makes sure to use recognized patterns when vectorizing roots during BB SLP discovery. We need to apply those late since during root discovery we've not yet done pattern recognition. All parts of the vectorizer assume patterns get used, for the testcase we mix this up when doing live lane computation. PR tree-optimization/114231 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when processing a BB SLP root. * gcc.dg/vect/pr114231.c: New testcase. --- gcc/testsuite/gcc.dg/vect/pr114231.c | 12 ++++++++++++ gcc/tree-vect-slp.cc | 4 ++++ 2 files changed, 16 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/vect/pr114231.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/vect/pr114231.c b/gcc/testsuite/gcc.dg/vect/pr114231.c new file mode 100644 index 0000000..5e3a810 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr114231.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ + +void f(long*); +int ff[2]; +void f2(long, long, unsigned long); +void k(unsigned long x, unsigned long y) +{ + long t = x >> ff[0]; + long t1 = ff[1]; + unsigned long t2 = y >> ff[0]; + f2(t1, t+t2, t2); +} diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc index 895f4f7..324400d 100644 --- a/gcc/tree-vect-slp.cc +++ b/gcc/tree-vect-slp.cc @@ -3649,6 +3649,10 @@ vect_analyze_slp (vec_info *vinfo, unsigned max_tree_size) for (unsigned i = 0; i < bb_vinfo->roots.length (); ++i) { vect_location = bb_vinfo->roots[i].roots[0]->stmt; + /* Apply patterns. */ + for (unsigned j = 0; j < bb_vinfo->roots[i].stmts.length (); ++j) + bb_vinfo->roots[i].stmts[j] + = vect_stmt_to_vectorize (bb_vinfo->roots[i].stmts[j]); if (vect_build_slp_instance (bb_vinfo, bb_vinfo->roots[i].kind, bb_vinfo->roots[i].stmts, bb_vinfo->roots[i].roots, -- cgit v1.1 From 49a1a340ea0eef681f23b6861f3cdb6840aadd99 Mon Sep 17 00:00:00 2001 From: Roger Sayle Date: Tue, 5 Mar 2024 11:06:17 +0100 Subject: AVR: Improve output of insn "*insv.any_shift._split". The instructions printed by insn "*insv.any_shift._split" were sub-optimal. The code to print the improved output is lengthy and performed by new function avr_out_insv. As it turns out, the function can also handle shift-offsets of zero, which is "*andhi3", "*andpsi3" and "*andsi3". Thus, these tree insns get a new 3-operand alternative where the 3rd operand is an exact power of 2. gcc/ * config/avr/avr-protos.h (avr_out_insv): New proto. * config/avr/avr.cc (avr_out_insv): New function. (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case. (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs. * config/avr/avr.md (define_attr "adjust_len") Add insv. (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3): Add constraint alternative where the 3rd operand is a power of 2, and the source register may differ from the destination. (*insv.any_shift._split): Call avr_out_insv to output instructions. Set attr "length" to "insv". * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints. gcc/testsuite/ * gcc.target/avr/torture/insv-anyshift-hi.c: New test. * gcc.target/avr/torture/insv-anyshift-si.c: New test. --- gcc/config/avr/avr-protos.h | 1 + gcc/config/avr/avr.cc | 181 +++++++++++++++++++++ gcc/config/avr/avr.md | 98 ++++++----- gcc/config/avr/constraints.md | 15 ++ .../gcc.target/avr/torture/insv-anyshift-hi.c | 141 ++++++++++++++++ .../gcc.target/avr/torture/insv-anyshift-si.c | 89 ++++++++++ 6 files changed, 474 insertions(+), 51 deletions(-) create mode 100644 gcc/testsuite/gcc.target/avr/torture/insv-anyshift-hi.c create mode 100644 gcc/testsuite/gcc.target/avr/torture/insv-anyshift-si.c (limited to 'gcc') diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h index 3e19409..bb68031 100644 --- a/gcc/config/avr/avr-protos.h +++ b/gcc/config/avr/avr-protos.h @@ -58,6 +58,7 @@ extern const char *ret_cond_branch (rtx x, int len, int reverse); extern const char *avr_out_movpsi (rtx_insn *, rtx*, int*); extern const char *avr_out_sign_extend (rtx_insn *, rtx*, int*); extern const char *avr_out_insert_notbit (rtx_insn *, rtx*, int*); +extern const char *avr_out_insv (rtx_insn *, rtx*, int*); extern const char *avr_out_extr (rtx_insn *, rtx*, int*); extern const char *avr_out_extr_not (rtx_insn *, rtx*, int*); extern const char *avr_out_plus_set_ZN (rtx*, int*); diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index c8b2b50..36995e0 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -9795,6 +9795,178 @@ avr_out_insert_notbit (rtx_insn *insn, rtx op[], int *plen) } +/* Output instructions for XOP[0] = (XOP[1] XOP[2]) & XOP[3] where + - XOP[0] and XOP[1] have the same mode which is one of: QI, HI, PSI, SI. + - XOP[3] is an exact const_int power of 2. + - XOP[2] and XOP[3] are const_int. + - is any of: ASHIFT, LSHIFTRT, ASHIFTRT. + - The result depends on XOP[1]. + or XOP[0] = XOP[1] & XOP[2] where + - XOP[0] and XOP[1] have the same mode which is one of: HI, PSI, SI. + - XOP[2] is an exact const_int power of 2. + Returns "". + PLEN != 0: Set *PLEN to the code length in words. Don't output anything. + PLEN == 0: Output instructions. */ + +const char* +avr_out_insv (rtx_insn *insn, rtx xop[], int *plen) +{ + machine_mode mode = GET_MODE (xop[0]); + int n_bytes = GET_MODE_SIZE (mode); + rtx xsrc = SET_SRC (single_set (insn)); + + gcc_assert (AND == GET_CODE (xsrc)); + + rtx xop2 = xop[2]; + rtx xop3 = xop[3]; + + if (REG_P (XEXP (xsrc, 0))) + { + // This function can also handle AND with an exact power of 2, + // which can be regarded as a XOP[1] shift with offset 0. + rtx xshift = gen_rtx_ASHIFT (mode, xop[1], const0_rtx); + xsrc = gen_rtx_AND (mode, xshift, xop[2]); + xop3 = xop[2]; + xop2 = const0_rtx; + } + + // Any of ASHIFT, LSHIFTRT, ASHIFTRT. + enum rtx_code code = GET_CODE (XEXP (xsrc, 0)); + int shift = code == ASHIFT ? INTVAL (xop2) : -INTVAL (xop2); + + // Determines the position of the output bit. + unsigned mask = GET_MODE_MASK (mode) & INTVAL (xop3); + + // Position of the output / input bit, respectively. + int obit = exact_log2 (mask); + int ibit = obit - shift; + + gcc_assert (IN_RANGE (obit, 0, GET_MODE_BITSIZE (mode) - 1)); + gcc_assert (IN_RANGE (ibit, 0, GET_MODE_BITSIZE (mode) - 1)); + + // In the remainder, use the sub-bytes that hold the bits. + rtx op[4] = + { + // Output + simplify_gen_subreg (QImode, xop[0], mode, obit / 8), + GEN_INT (obit & 7), + // Input + simplify_gen_subreg (QImode, xop[1], mode, ibit / 8), + GEN_INT (ibit & 7) + }; + obit &= 7; + ibit &= 7; + + // The length of the default sequence at the end of this function. + // We only emit anything other than the default when we find a sequence + // that is strictly shorter than the default sequence; which is: + // BST + + BLD. + const int len0 = 2 + n_bytes - (n_bytes == 4 && AVR_HAVE_MOVW); + + // Finding something shorter than the default sequence implies that there + // must be at most 2 instructions that deal with the bytes containing the + // relevant bits. In addition, we need N_BYTES - 1 instructions to clear + // the remaining result bytes. + + const int n_clr = n_bytes - 1; + bool clr_p = false; + bool andi_p = false; + + if (plen) + *plen = 0; + + if (REGNO (op[0]) == REGNO (op[2]) + // Output reg allows ANDI. + && test_hard_reg_class (LD_REGS, op[0])) + { + if (1 + n_clr < len0 + // Same byte and bit: A single ANDI will do. + && obit == ibit) + { + clr_p = andi_p = true; + } + else if (2 + n_clr < len0 + // |obit - ibit| = 4: SWAP + ANDI will do. + && (obit == ibit + 4 || obit == ibit - 4)) + { + avr_asm_len ("swap %0", op, plen, 1); + clr_p = andi_p = true; + } + else if (2 + n_clr < len0 + // LSL + ANDI will do. + && obit == ibit + 1) + { + avr_asm_len ("lsl %0", op, plen, 1); + clr_p = andi_p = true; + } + else if (2 + n_clr < len0 + // LSR + ANDI will do. + && obit == ibit - 1) + { + avr_asm_len ("lsr %0", op, plen, 1); + clr_p = andi_p = true; + } + } + + if (REGNO (op[0]) != REGNO (op[2]) + && obit == ibit) + { + if (2 + n_clr < len0 + // Same bit but different byte: MOV + ANDI will do. + && test_hard_reg_class (LD_REGS, op[0])) + { + avr_asm_len ("mov %0,%2", op, plen, 1); + clr_p = andi_p = true; + } + else if (2 + n_clr < len0 + // Same bit but different byte: We can use ANDI + MOV, + // but only if the input byte is LD_REGS and unused after. + && test_hard_reg_class (LD_REGS, op[2]) + && reg_unused_after (insn, op[2])) + { + avr_asm_len ("andi %2,1<<%3" CR_TAB + "mov %0,%2", op, plen, 2); + clr_p = true; + } + } + + // Output remaining instructions of the shorter sequence. + + if (andi_p) + avr_asm_len ("andi %0,1<<%1", op, plen, 1); + + if (clr_p) + { + for (int b = 0; b < n_bytes; ++b) + { + rtx byte = simplify_gen_subreg (QImode, xop[0], mode, b); + if (REGNO (byte) != REGNO (op[0])) + avr_asm_len ("clr %0", &byte, plen, 1); + } + + // CLR_P means we found a shorter sequence, so we are done now. + return ""; + } + + // No shorter sequence found, just emit BST, CLR*, BLD sequence. + + avr_asm_len ("bst %2,%3", op, plen, -1); + + if (n_bytes == 4 && AVR_HAVE_MOVW) + avr_asm_len ("clr %A0" CR_TAB + "clr %B0" CR_TAB + "movw %C0,%A0", xop, plen, 3); + else + for (int b = 0; b < n_bytes; ++b) + { + rtx byte = simplify_gen_subreg (QImode, xop[0], mode, b); + avr_asm_len ("clr %0", &byte, plen, 1); + } + + return avr_asm_len ("bld %0,%1", op, plen, 1); +} + + /* Output instructions to extract a bit to 8-bit register XOP[0]. The input XOP[1] is a register or an 8-bit MEM in the lower I/O range. XOP[2] is the const_int bit position. Return "". @@ -10721,6 +10893,7 @@ avr_adjust_insn_length (rtx_insn *insn, int len) case ADJUST_LEN_OUT_BITOP: avr_out_bitop (insn, op, &len); break; case ADJUST_LEN_EXTR_NOT: avr_out_extr_not (insn, op, &len); break; case ADJUST_LEN_EXTR: avr_out_extr (insn, op, &len); break; + case ADJUST_LEN_INSV: avr_out_insv (insn, op, &len); break; case ADJUST_LEN_PLUS: avr_out_plus (insn, op, &len); break; case ADJUST_LEN_ADDTO_SP: avr_out_addto_sp (op, &len); break; @@ -12206,6 +12379,14 @@ avr_cbranch_cost (rtx x) return COSTS_N_INSNS (size + 1 + 1); } + if (GET_CODE (xreg) == ZERO_EXTRACT + && XEXP (xreg, 1) == const1_rtx) + { + // Branch on a single bit, with an additional edge due to less + // register pressure. + return (int) COSTS_N_INSNS (1.5); + } + bool reg_p = register_operand (xreg, mode); bool reg_or_0_p = reg_or_0_operand (xval, mode); diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 6606837..6bdf468 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -170,7 +170,7 @@ ashlhi, ashrhi, lshrhi, ashlsi, ashrsi, lshrsi, ashlpsi, ashrpsi, lshrpsi, - insert_bits, insv_notbit, + insert_bits, insv_notbit, insv, add_set_ZN, cmp_uext, cmp_sext, no" (const_string "no")) @@ -4380,10 +4380,10 @@ [(set_attr "length" "1,1,2")]) (define_insn_and_split "andhi3" - [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r") - (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0") - (match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,n"))) - (clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))] + [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r ,r") + (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,r ,0") + (match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,Cb2,n"))) + (clobber (match_scratch:QI 3 "=X,X,X,X ,X ,&d"))] "" "#" "&& reload_completed" @@ -4394,10 +4394,10 @@ (clobber (reg:CC REG_CC))])]) (define_insn "*andhi3" - [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r") - (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0") - (match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,n"))) - (clobber (match_scratch:QI 3 "=X,X,X,X ,&d")) + [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r ,r") + (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,r ,0") + (match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,Cb2,n"))) + (clobber (match_scratch:QI 3 "=X,X,X,X ,X ,&d")) (clobber (reg:CC REG_CC))] "reload_completed" { @@ -4405,17 +4405,19 @@ return "and %A0,%A2\;and %B0,%B2"; else if (which_alternative == 1) return "andi %A0,lo8(%2)\;andi %B0,hi8(%2)"; + else if (which_alternative == 4) + return avr_out_insv (insn, operands, NULL); return avr_out_bitop (insn, operands, NULL); } - [(set_attr "length" "2,2,2,4,4") - (set_attr "adjust_len" "*,*,out_bitop,out_bitop,out_bitop")]) + [(set_attr "length" "2,2,2,4,4,4") + (set_attr "adjust_len" "*,*,out_bitop,out_bitop,insv,out_bitop")]) (define_insn_and_split "andpsi3" - [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r") - (and:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0") - (match_operand:PSI 2 "nonmemory_operand" "r,n,Ca3,n"))) - (clobber (match_scratch:QI 3 "=X,X,X ,&d"))] + [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r ,r") + (and:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,r ,0") + (match_operand:PSI 2 "nonmemory_operand" "r,n,Ca3,Cb3,n"))) + (clobber (match_scratch:QI 3 "=X,X,X ,X ,&d"))] "" "#" "&& reload_completed" @@ -4426,10 +4428,10 @@ (clobber (reg:CC REG_CC))])]) (define_insn "*andpsi3" - [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r") - (and:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0") - (match_operand:PSI 2 "nonmemory_operand" "r,n,Ca3,n"))) - (clobber (match_scratch:QI 3 "=X,X,X ,&d")) + [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r ,r") + (and:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,r ,0") + (match_operand:PSI 2 "nonmemory_operand" "r,n,Ca3,Cb3,n"))) + (clobber (match_scratch:QI 3 "=X,X,X ,X ,&d")) (clobber (reg:CC REG_CC))] "reload_completed" { @@ -4438,16 +4440,19 @@ "and %B0,%B2" CR_TAB "and %C0,%C2"; + if (which_alternative == 3) + return avr_out_insv (insn, operands, NULL); + return avr_out_bitop (insn, operands, NULL); } - [(set_attr "length" "3,3,6,6") - (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")]) + [(set_attr "length" "3,3,6,5,6") + (set_attr "adjust_len" "*,out_bitop,out_bitop,insv,out_bitop")]) (define_insn_and_split "andsi3" - [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r") - (and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0") - (match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,n"))) - (clobber (match_scratch:QI 3 "=X,X,X ,&d"))] + [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r ,r") + (and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,r ,0") + (match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,Cb4,n"))) + (clobber (match_scratch:QI 3 "=X,X,X ,X ,&d"))] "" "#" "&& reload_completed" @@ -4458,10 +4463,10 @@ (clobber (reg:CC REG_CC))])]) (define_insn "*andsi3" - [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r") - (and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0") - (match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,n"))) - (clobber (match_scratch:QI 3 "=X,X,X ,&d")) + [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r ,r") + (and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,r ,0") + (match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,Cb4,n"))) + (clobber (match_scratch:QI 3 "=X,X,X ,X ,&d")) (clobber (reg:CC REG_CC))] "reload_completed" { @@ -4471,10 +4476,13 @@ "and %C0,%C2" CR_TAB "and %D0,%D2"; + if (which_alternative == 3) + return avr_out_insv (insn, operands, NULL); + return avr_out_bitop (insn, operands, NULL); } - [(set_attr "length" "4,4,8,8") - (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")]) + [(set_attr "length" "4,4,8,6,8") + (set_attr "adjust_len" "*,out_bitop,out_bitop,insv,out_bitop")]) (define_peephole2 ; andi [(parallel [(set (match_operand:QI 0 "d_register_operand" "") @@ -9852,6 +9860,12 @@ (const_int 1) (const_int 7)))]) +;; This insn serves as a combine bridge because insn combine will only +;; combine so much (3) insns at most. It's not actually an open coded +;; bit-insertion but just a part of it. It may occur in other contexts +;; than INSV though, and in such a case the code may be worse than without +;; this pattern. We still have to emit code for it in that case because +;; we cannot roll back. (define_insn_and_split "*insv.any_shift._split" [(set (match_operand:QISI 0 "register_operand" "=r") (and:QISI (any_shift:QISI (match_operand:QISI 1 "register_operand" "r") @@ -9874,27 +9888,9 @@ (clobber (reg:CC REG_CC))] "reload_completed" { - int shift = == ASHIFT ? INTVAL (operands[2]) : -INTVAL (operands[2]); - int mask = GET_MODE_MASK (mode) & INTVAL (operands[3]); - // Position of the output / input bit, respectively. - int obit = exact_log2 (mask); - int ibit = obit - shift; - gcc_assert (IN_RANGE (obit, 0, )); - gcc_assert (IN_RANGE (ibit, 0, )); - operands[3] = GEN_INT (obit); - operands[2] = GEN_INT (ibit); - - if ( == 1) return "bst %T1%T2\;clr %0\;" "bld %T0%T3"; - if ( == 2) return "bst %T1%T2\;clr %A0\;clr %B0\;" "bld %T0%T3"; - if ( == 3) return "bst %T1%T2\;clr %A0\;clr %B0\;clr %C0\;bld %T0%T3"; - return AVR_HAVE_MOVW - ? "bst %T1%T2\;clr %A0\;clr %B0\;movw %C0,%A0\;" "bld %T0%T3" - : "bst %T1%T2\;clr %A0\;clr %B0\;clr %C0\;clr %D0\;bld %T0%T3"; + return avr_out_insv (insn, operands, nullptr); } - [(set (attr "length") - (minus (symbol_ref "2 + ") - ; One less if we can use a MOVW to clear. - (symbol_ref " == 4 && AVR_HAVE_MOVW")))]) + [(set_attr "adjust_len" "insv")]) (define_insn_and_split "*extzv.hi2" diff --git a/gcc/config/avr/constraints.md b/gcc/config/avr/constraints.md index 81ed63d..fac54da 100644 --- a/gcc/config/avr/constraints.md +++ b/gcc/config/avr/constraints.md @@ -188,6 +188,21 @@ (and (match_code "const_int") (match_test "avr_popcount_each_byte (op, 4, (1<<0) | (1<<1) | (1<<8))"))) +(define_constraint "Cb2" + "Constant 2-byte integer that has exactly 1 bit set." + (and (match_code "const_int") + (match_test "single_one_operand (op, HImode)"))) + +(define_constraint "Cb3" + "Constant 3-byte integer that has exactly 1 bit set." + (and (match_code "const_int") + (match_test "single_one_operand (op, PSImode)"))) + +(define_constraint "Cb4" + "Constant 4-byte integer that has exactly 1 bit set." + (and (match_code "const_int") + (match_test "single_one_operand (op, SImode)"))) + (define_constraint "Cx2" "Constant 2-byte integer that allows XOR without clobber register." (and (match_code "const_int") diff --git a/gcc/testsuite/gcc.target/avr/torture/insv-anyshift-hi.c b/gcc/testsuite/gcc.target/avr/torture/insv-anyshift-hi.c new file mode 100644 index 0000000..7ee5c04 --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/insv-anyshift-hi.c @@ -0,0 +1,141 @@ +/* { dg-do run } */ +/* { dg-additional-options { -fno-split-wide-types } } */ + +typedef __UINT16_TYPE__ uint16_t; + +/* Testing inlined and completely folded versions of functions + against their non-inlined, non-folded counnterparts. */ + +#define MK_FUN1(OBIT, LSR) \ + static __inline__ __attribute__((__always_inline__)) \ + uint16_t fun1_lsr_##OBIT##_##LSR##_ai (int x, uint16_t a) \ + { \ + (void) x; \ + return (a >> LSR) & (1u << OBIT); \ + } \ + \ + __attribute__((__noinline__,__noclone__)) \ + uint16_t fun1_lsr_##OBIT##_##LSR##_ni (int x, uint16_t a) \ + { \ + return fun1_lsr_##OBIT##_##LSR##_ai (x, a); \ + } \ + \ + void test_fun1_lsr_##OBIT##_##LSR (void) \ + { \ + if (fun1_lsr_##OBIT##_##LSR##_ni (0, 1u << (OBIT + LSR)) \ + != fun1_lsr_##OBIT##_##LSR##_ai (0, 1u << (OBIT + LSR))) \ + __builtin_abort(); \ + \ + if (fun1_lsr_##OBIT##_##LSR##_ni (0, 1u << (OBIT + LSR)) \ + != fun1_lsr_##OBIT##_##LSR##_ai (0, -1u)) \ + __builtin_abort(); \ + } + +#define MK_FUN3(OBIT, LSR) \ + static __inline__ __attribute__((__always_inline__)) \ + uint16_t fun3_lsr_##OBIT##_##LSR##_ai (uint16_t a) \ + { \ + return (a >> LSR) & (1u << OBIT); \ + } \ + \ + __attribute__((__noinline__,__noclone__)) \ + uint16_t fun3_lsr_##OBIT##_##LSR##_ni (uint16_t a) \ + { \ + return fun3_lsr_##OBIT##_##LSR##_ai (a); \ + } \ + \ + void test_fun3_lsr_##OBIT##_##LSR (void) \ + { \ + if (fun3_lsr_##OBIT##_##LSR##_ni (1u << (OBIT + LSR)) \ + != fun3_lsr_##OBIT##_##LSR##_ai (1u << (OBIT + LSR))) \ + __builtin_abort(); \ + \ + if (fun3_lsr_##OBIT##_##LSR##_ni (1u << (OBIT + LSR)) \ + != fun3_lsr_##OBIT##_##LSR##_ai (-1u)) \ + __builtin_abort(); \ + } + + +#define MK_FUN2(OBIT, LSL) \ + static __inline__ __attribute__((__always_inline__)) \ + uint16_t fun2_lsl_##OBIT##_##LSL##_ai (uint16_t a) \ + { \ + return (a << LSL) & (1u << OBIT); \ + } \ + \ + __attribute__((__noinline__,__noclone__)) \ + uint16_t fun2_lsl_##OBIT##_##LSL##_ni (uint16_t a) \ + { \ + return fun2_lsl_##OBIT##_##LSL##_ai (a); \ + } \ + \ + void test_fun2_lsl_##OBIT##_##LSL (void) \ + { \ + if (fun2_lsl_##OBIT##_##LSL##_ni (1u << (OBIT - LSL)) \ + != fun2_lsl_##OBIT##_##LSL##_ai (1u << (OBIT - LSL))) \ + __builtin_abort(); \ + \ + if (fun2_lsl_##OBIT##_##LSL##_ni (1u << (OBIT - LSL)) \ + != fun2_lsl_##OBIT##_##LSL##_ai (-1u)) \ + __builtin_abort(); \ + } + + +MK_FUN1 (10, 4) +MK_FUN1 (6, 1) +MK_FUN1 (1, 5) +MK_FUN1 (0, 8) +MK_FUN1 (0, 4) +MK_FUN1 (0, 1) +MK_FUN1 (0, 0) + +MK_FUN3 (10, 4) +MK_FUN3 (6, 1) +MK_FUN3 (1, 5) +MK_FUN3 (0, 8) +MK_FUN3 (0, 4) +MK_FUN3 (0, 1) +MK_FUN3 (0, 0) + +MK_FUN2 (12, 8) +MK_FUN2 (15, 15) +MK_FUN2 (14, 12) +MK_FUN2 (8, 8) +MK_FUN2 (7, 4) +MK_FUN2 (5, 4) +MK_FUN2 (5, 1) +MK_FUN2 (4, 0) +MK_FUN2 (1, 0) +MK_FUN2 (0, 0) + +int main (void) +{ + test_fun1_lsr_10_4 (); + test_fun1_lsr_6_1 (); + test_fun1_lsr_1_5 (); + test_fun1_lsr_0_8 (); + test_fun1_lsr_0_4 (); + test_fun1_lsr_0_1 (); + test_fun1_lsr_0_0 (); + + test_fun3_lsr_10_4 (); + test_fun3_lsr_6_1 (); + test_fun3_lsr_1_5 (); + test_fun3_lsr_0_8 (); + test_fun3_lsr_0_4 (); + test_fun3_lsr_0_1 (); + test_fun3_lsr_0_0 (); + + test_fun2_lsl_12_8 (); + test_fun2_lsl_15_15 (); + test_fun2_lsl_14_12 (); + test_fun2_lsl_8_8 (); + test_fun2_lsl_7_4 (); + test_fun2_lsl_5_4 (); + test_fun2_lsl_5_1 (); + test_fun2_lsl_4_0 (); + test_fun2_lsl_1_0 (); + test_fun2_lsl_0_0 (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/avr/torture/insv-anyshift-si.c b/gcc/testsuite/gcc.target/avr/torture/insv-anyshift-si.c new file mode 100644 index 0000000..f52593c --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/torture/insv-anyshift-si.c @@ -0,0 +1,89 @@ +/* { dg-do run } */ + +typedef __UINT32_TYPE__ uint32_t; + +/* Testing inlined and completely folded versions of functions + against their non-inlined, non-folded counnterparts. */ + +#define MK_FUN1(OBIT, LSR) \ + static __inline__ __attribute__((__always_inline__)) \ + uint32_t fun1_lsr_##OBIT##_##LSR##_ai (int x, uint32_t a) \ + { \ + (void) x; \ + return (a >> LSR) & (1ul << OBIT); \ + } \ + \ + __attribute__((__noinline__,__noclone__)) \ + uint32_t fun1_lsr_##OBIT##_##LSR##_ni (int x, uint32_t a) \ + { \ + return fun1_lsr_##OBIT##_##LSR##_ai (x, a); \ + } \ + \ + void test_fun1_lsr_##OBIT##_##LSR (void) \ + { \ + if (fun1_lsr_##OBIT##_##LSR##_ni (0, 1ul << (OBIT + LSR)) \ + != fun1_lsr_##OBIT##_##LSR##_ai (0, 1ul << (OBIT + LSR))) \ + __builtin_abort(); \ + \ + if (fun1_lsr_##OBIT##_##LSR##_ni (0, 1ul << (OBIT + LSR)) \ + != fun1_lsr_##OBIT##_##LSR##_ai (0, -1ul)) \ + __builtin_abort(); \ + } + + +#define MK_FUN2(OBIT, LSL) \ + static __inline__ __attribute__((__always_inline__)) \ + uint32_t fun2_lsl_##OBIT##_##LSL##_ai (int x, uint32_t a) \ + { \ + (void) x; \ + return (a << LSL) & (1ul << OBIT); \ + } \ + \ + __attribute__((__noinline__,__noclone__)) \ + uint32_t fun2_lsl_##OBIT##_##LSL##_ni (int x, uint32_t a) \ + { \ + return fun2_lsl_##OBIT##_##LSL##_ai (x, a); \ + } \ + \ + void test_fun2_lsl_##OBIT##_##LSL (void) \ + { \ + if (fun2_lsl_##OBIT##_##LSL##_ni (0, 1ul << (OBIT - LSL)) \ + != fun2_lsl_##OBIT##_##LSL##_ai (0, 1ul << (OBIT - LSL))) \ + __builtin_abort(); \ + \ + if (fun2_lsl_##OBIT##_##LSL##_ni (0, 1ul << (OBIT - LSL)) \ + != fun2_lsl_##OBIT##_##LSL##_ai (0, -1ul)) \ + __builtin_abort(); \ + } + + +MK_FUN1 (13, 15) +MK_FUN1 (13, 16) +MK_FUN1 (13, 17) +MK_FUN1 (13, 12) +MK_FUN1 (0, 31) +MK_FUN1 (0, 8) +MK_FUN1 (0, 0) + +MK_FUN2 (12, 8) +MK_FUN2 (13, 8) +MK_FUN2 (16, 8) +MK_FUN2 (16, 0) + +int main (void) +{ + test_fun1_lsr_13_15 (); + test_fun1_lsr_13_16 (); + test_fun1_lsr_13_17 (); + test_fun1_lsr_13_12 (); + test_fun1_lsr_0_31 (); + test_fun1_lsr_0_8 (); + test_fun1_lsr_0_0 (); + + test_fun2_lsl_12_8 (); + test_fun2_lsl_13_8 (); + test_fun2_lsl_16_8 (); + test_fun2_lsl_16_0 (); + + return 0; +} -- cgit v1.1 From f628a30f4dbdee9b4531314d72c7762f1fbcf8ff Mon Sep 17 00:00:00 2001 From: Xi Ruoyao Date: Thu, 25 Jan 2024 23:49:13 +0800 Subject: LoongArch: Allow s9 as a register alias The psABI allows using s9 as an alias of r22. gcc/ChangeLog: * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add s9 as an alias of r22. gcc/testsuite/ChangeLog: * gcc.target/loongarch/regname-fp-s9.c: New test. --- gcc/config/loongarch/loongarch.h | 1 + gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c | 3 +++ 2 files changed, 4 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c (limited to 'gcc') diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h index 8b453ab..bf2351f 100644 --- a/gcc/config/loongarch/loongarch.h +++ b/gcc/config/loongarch/loongarch.h @@ -931,6 +931,7 @@ typedef struct { { "t8", 20 + GP_REG_FIRST }, \ { "x", 21 + GP_REG_FIRST }, \ { "fp", 22 + GP_REG_FIRST }, \ + { "s9", 22 + GP_REG_FIRST }, \ { "s0", 23 + GP_REG_FIRST }, \ { "s1", 24 + GP_REG_FIRST }, \ { "s2", 25 + GP_REG_FIRST }, \ diff --git a/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c b/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c new file mode 100644 index 0000000..d2e3b80 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/regname-fp-s9.c @@ -0,0 +1,3 @@ +/* { dg-do compile } */ +register long s9 asm("s9"); /* { dg-note "conflicts with 's9'" } */ +register long fp asm("fp"); /* { dg-warning "register of 'fp' used for multiple global register variables" } */ -- cgit v1.1 From db2e13d11a2c2ee60ff1db46dcacd7cecf30ce8f Mon Sep 17 00:00:00 2001 From: Mark Wielaard Date: Tue, 5 Mar 2024 13:01:08 +0100 Subject: Regenerate c.opt.urls Fixes: 08edf85f747b ("c++/modules: relax diagnostic about GMF contents") gcc/c-family/ChangeLog: * c.opt.urls: Regenerate. --- gcc/c-family/c.opt.urls | 3 +++ 1 file changed, 3 insertions(+) (limited to 'gcc') diff --git a/gcc/c-family/c.opt.urls b/gcc/c-family/c.opt.urls index 9f97dc6..6317198 100644 --- a/gcc/c-family/c.opt.urls +++ b/gcc/c-family/c.opt.urls @@ -403,6 +403,9 @@ UrlSuffix(gcc/Warning-Options.html#index-Wformat) Wframe-address UrlSuffix(gcc/Warning-Options.html#index-Wframe-address) +Wglobal-module +UrlSuffix(gcc/C_002b_002b-Dialect-Options.html#index-Wglobal-module) + Wif-not-aligned UrlSuffix(gcc/Warning-Options.html#index-Wif-not-aligned) -- cgit v1.1 From 08ec4adb0285f6a472865cf386bf035ed0eaebce Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Tue, 5 Mar 2024 15:29:45 +0100 Subject: AVR: Add two RTL peepholes. Register alloc may expand a 3-operand arithmetic X = Y o CST as X = CST X o= Y where it may be better to instead: X = Y X o= CST because 1) the first insn may use MOVW for "X = Y", and 2) the operation may be more efficient when performed with a constant, for example when ADIW or SBIW can be used, or some bytes of the constant are 0x00 or 0xff. gcc/ * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND in HI, PSI, SI that swap operation order from "X = CST, X o= Y" to "X = Y, X o= CST". --- gcc/config/avr/avr.md | 61 ++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 58 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 6bdf468..bc8a59c 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -932,6 +932,55 @@ operands[5] = gen_rtx_REG (HImode, REGNO (operands[3])); }) + +;; Register alloc may expand a 3-operand arithmetic X = Y o CST as +;; X = CST +;; X o= Y +;; where it may be better to instead: +;; X = Y +;; X o= CST +;; because 1) the first insn may use MOVW for "X = Y", and 2) the +;; operation may be more efficient when performed with a constant, +;; for example when ADIW or SBIW can be used, or some bytes of +;; the constant are 0x00 or 0xff. +(define_peephole2 + [(parallel [(set (match_operand:HISI 0 "d_register_operand") + (match_operand:HISI 1 "const_int_operand")) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 0) + (piaop:HISI (match_dup 0) + (match_operand:HISI 2 "register_operand"))) + (clobber (scratch:QI)) + (clobber (reg:CC REG_CC))])] + "! reg_overlap_mentioned_p (operands[0], operands[2])" + [(parallel [(set (match_dup 0) + (match_dup 2)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 0) + (piaop:HISI (match_dup 0) + (match_dup 1))) + (clobber (scratch:QI)) + (clobber (reg:CC REG_CC))])]) + +;; Same, but just for plus:HI without a scratch:QI. +(define_peephole2 + [(parallel [(set (match_operand:HI 0 "d_register_operand") + (match_operand:HI 1 "const_int_operand")) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 0) + (plus:HI (match_dup 0) + (match_operand:HI 2 "register_operand"))) + (clobber (reg:CC REG_CC))])] + "! reg_overlap_mentioned_p (operands[0], operands[2])" + [(parallel [(set (match_dup 0) + (match_dup 2)) + (clobber (reg:CC REG_CC))]) + (parallel [(set (match_dup 0) + (plus:HI (match_dup 0) + (match_dup 1))) + (clobber (reg:CC REG_CC))])]) + + ;; For LPM loads from AS1 we split ;; R = *Z ;; to @@ -1644,9 +1693,9 @@ [(set_attr "length" "6") (set_attr "adjust_len" "addto_sp")]) -;; "*addhi3" -;; "*addhq3" "*adduhq3" -;; "*addha3" "*adduha3" +;; "*addhi3_split" +;; "*addhq3_split" "*adduhq3_split" +;; "*addha3_split" "*adduha3_split" (define_insn_and_split "*add3_split" [(set (match_operand:ALL2 0 "register_operand" "=??r,d,!w ,d") (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0,0,0 ,0") @@ -1661,6 +1710,9 @@ "" [(set_attr "isa" "*,*,adiw,*")]) +;; "*addhi3" +;; "*addhq3" "*adduhq3" +;; "*addha3" "*adduha3" (define_insn "*add3" [(set (match_operand:ALL2 0 "register_operand" "=??r,d,!w ,d") (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0,0,0 ,0") @@ -1732,6 +1784,9 @@ (clobber (match_dup 3)) (clobber (reg:CC REG_CC))])]) +;; "*addhi3_clobber" +;; "*addhq3_clobber" "*adduhq3_clobber" +;; "*addha3_clobber" "*adduha3_clobber" (define_insn "*add3_clobber" [(set (match_operand:ALL2 0 "register_operand" "=!w ,d ,r") (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0 ,0 ,0") -- cgit v1.1 From 2ba3171f161452df476485272cc966bc523d9859 Mon Sep 17 00:00:00 2001 From: Saurabh Jha Date: Tue, 30 Jan 2024 15:03:36 +0000 Subject: Fix testcase pr112337.c to check the options [PR112337] gcc.target/arm/pr112337.c was failing to validate that adding MVE options was compatible with the test environment, so add the missing checks. gcc/testsuite/ChangeLog: PR target/112337 * gcc.target/arm/pr112337.c: Check for, then use the right MVE options. --- gcc/testsuite/gcc.target/arm/pr112337.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/arm/pr112337.c b/gcc/testsuite/gcc.target/arm/pr112337.c index 5dacf0a..10b7881 100644 --- a/gcc/testsuite/gcc.target/arm/pr112337.c +++ b/gcc/testsuite/gcc.target/arm/pr112337.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=armv8.1-m.main+fp.dp+mve.fp -mfloat-abi=hard" } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ #pragma GCC arm "arm_mve_types.h" int32x4_t h(void *p) { return __builtin_mve_vldrwq_sv4si(p); } -- cgit v1.1 From 067a012bde15bfb62d9af309d9d524ebfe91b705 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Tue, 5 Mar 2024 17:21:43 +0000 Subject: arm: check for low register before applying peephole [PR113510] For thumb1, when using a peephole to fuse mov reg, #const add reg, reg, SP into add reg, SP, #const we must first check that reg is a low register, otherwise we will ICE when trying to recognize the resulting insn. gcc/ChangeLog: PR target/113510 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use low_register_operand. --- gcc/config/arm/thumb1.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index 14d6df5..d7074b4 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -113,7 +113,7 @@ ;; Reloading and elimination of the frame pointer can ;; sometimes cause this optimization to be missed. (define_peephole2 - [(set (match_operand:SI 0 "arm_general_register_operand" "") + [(set (match_operand:SI 0 "low_register_operand" "") (match_operand:SI 1 "const_int_operand" "")) (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI SP_REGNUM)))] -- cgit v1.1 From 8776468d9e57ace5f832c1368243a6dbce9984d5 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 5 Mar 2024 17:51:24 +0000 Subject: aarch64: Remove SME2.1 forms of LUTI2/4 I was over-eager when adding support for strided SME2 instructions and accidentally included forms of LUTI2 and LUTI4 that are only available with SME2.1, not SME2. This patch removes them for now. We're planning to add proper support for SME2.1 in the GCC 15 timeframe. Sorry for the blunder :( gcc/ * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive and luti_strided. * config/aarch64/aarch64-sme.md (@aarch64_sme_lut): Remove stride_type attribute. (@aarch64_sme_lut_strided2): Delete. (@aarch64_sme_lut_strided4): Likewise. * config/aarch64/aarch64-early-ra.cc (is_stride_candidate) (early_ra::maybe_convert_to_strided_access): Remove support for strided LUTI2 and LUTI4. gcc/testsuite/ * gcc.target/aarch64/sme/strided_1.c (test5): Remove. --- gcc/config/aarch64/aarch64-early-ra.cc | 20 +------ gcc/config/aarch64/aarch64-sme.md | 70 ------------------------ gcc/config/aarch64/aarch64.md | 3 +- gcc/testsuite/gcc.target/aarch64/sme/strided_1.c | 55 ------------------- 4 files changed, 3 insertions(+), 145 deletions(-) (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-early-ra.cc b/gcc/config/aarch64/aarch64-early-ra.cc index 8530b0a..1e2c823 100644 --- a/gcc/config/aarch64/aarch64-early-ra.cc +++ b/gcc/config/aarch64/aarch64-early-ra.cc @@ -1060,8 +1060,7 @@ is_stride_candidate (rtx_insn *insn) return false; auto stride_type = get_attr_stride_type (insn); - return (stride_type == STRIDE_TYPE_LUTI_CONSECUTIVE - || stride_type == STRIDE_TYPE_LD1_CONSECUTIVE + return (stride_type == STRIDE_TYPE_LD1_CONSECUTIVE || stride_type == STRIDE_TYPE_ST1_CONSECUTIVE); } @@ -3212,8 +3211,7 @@ early_ra::maybe_convert_to_strided_access (rtx_insn *insn) auto stride_type = get_attr_stride_type (insn); rtx pat = PATTERN (insn); rtx op; - if (stride_type == STRIDE_TYPE_LUTI_CONSECUTIVE - || stride_type == STRIDE_TYPE_LD1_CONSECUTIVE) + if (stride_type == STRIDE_TYPE_LD1_CONSECUTIVE) op = SET_DEST (pat); else if (stride_type == STRIDE_TYPE_ST1_CONSECUTIVE) op = XVECEXP (SET_SRC (pat), 0, 1); @@ -3263,20 +3261,6 @@ early_ra::maybe_convert_to_strided_access (rtx_insn *insn) XVECEXP (SET_SRC (pat), 0, XVECLEN (SET_SRC (pat), 0) - 1) = *recog_data.dup_loc[0]; } - else if (stride_type == STRIDE_TYPE_LUTI_CONSECUTIVE) - { - auto bits = INTVAL (XVECEXP (SET_SRC (pat), 0, 4)); - if (range.count == 2) - pat = gen_aarch64_sme_lut_strided2 (bits, single_mode, - regs[0], regs[1], - recog_data.operand[1], - recog_data.operand[2]); - else - pat = gen_aarch64_sme_lut_strided4 (bits, single_mode, - regs[0], regs[1], regs[2], regs[3], - recog_data.operand[1], - recog_data.operand[2]); - } else gcc_unreachable (); PATTERN (insn) = pat; diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md index c95d4aa..78ad2fc 100644 --- a/gcc/config/aarch64/aarch64-sme.md +++ b/gcc/config/aarch64/aarch64-sme.md @@ -1939,74 +1939,4 @@ "TARGET_STREAMING_SME2 && !( == 4 && == 4 && == 8)" "luti\t%0, zt0, %1[%2]" - [(set_attr "stride_type" "luti_consecutive")] -) - -(define_insn "@aarch64_sme_lut_strided2" - [(set (match_operand:SVE_FULL_BHS 0 "aarch64_simd_register" "=Uwd") - (unspec:SVE_FULL_BHS - [(reg:V8DI ZT0_REGNUM) - (reg:DI SME_STATE_REGNUM) - (match_operand:VNx16QI 2 "register_operand" "w") - (match_operand:DI 3 "const_int_operand") - (const_int LUTI_BITS) - (const_int 0)] - UNSPEC_SME_LUTI)) - (set (match_operand:SVE_FULL_BHS 1 "aarch64_simd_register" "=w") - (unspec:SVE_FULL_BHS - [(reg:V8DI ZT0_REGNUM) - (reg:DI SME_STATE_REGNUM) - (match_dup 2) - (match_dup 3) - (const_int LUTI_BITS) - (const_int 1)] - UNSPEC_SME_LUTI))] - "TARGET_STREAMING_SME2 - && aarch64_strided_registers_p (operands, 2, 8)" - "luti\t{%0., %1.}, zt0, %2[%3]" - [(set_attr "stride_type" "luti_strided")] -) - -(define_insn "@aarch64_sme_lut_strided4" - [(set (match_operand:SVE_FULL_BHS 0 "aarch64_simd_register" "=Uwt") - (unspec:SVE_FULL_BHS - [(reg:V8DI ZT0_REGNUM) - (reg:DI SME_STATE_REGNUM) - (match_operand:VNx16QI 4 "register_operand" "w") - (match_operand:DI 5 "const_int_operand") - (const_int LUTI_BITS) - (const_int 0)] - UNSPEC_SME_LUTI)) - (set (match_operand:SVE_FULL_BHS 1 "aarch64_simd_register" "=w") - (unspec:SVE_FULL_BHS - [(reg:V8DI ZT0_REGNUM) - (reg:DI SME_STATE_REGNUM) - (match_dup 4) - (match_dup 5) - (const_int LUTI_BITS) - (const_int 1)] - UNSPEC_SME_LUTI)) - (set (match_operand:SVE_FULL_BHS 2 "aarch64_simd_register" "=w") - (unspec:SVE_FULL_BHS - [(reg:V8DI ZT0_REGNUM) - (reg:DI SME_STATE_REGNUM) - (match_dup 4) - (match_dup 5) - (const_int LUTI_BITS) - (const_int 2)] - UNSPEC_SME_LUTI)) - (set (match_operand:SVE_FULL_BHS 3 "aarch64_simd_register" "=w") - (unspec:SVE_FULL_BHS - [(reg:V8DI ZT0_REGNUM) - (reg:DI SME_STATE_REGNUM) - (match_dup 4) - (match_dup 5) - (const_int LUTI_BITS) - (const_int 3)] - UNSPEC_SME_LUTI))] - "TARGET_STREAMING_SME2 - && !( == 4 && == 8) - && aarch64_strided_registers_p (operands, 4, 4)" - "luti\t{%0., %1., %2., %3.}, zt0, %4[%5]" - [(set_attr "stride_type" "luti_strided")] ) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 33fbe1b..7d51d92 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -553,8 +553,7 @@ ;; The RTL mapping therefore applies at LD1 granularity, rather than ;; being broken down into individual types of load. (define_attr "stride_type" - "none,ld1_consecutive,ld1_strided,st1_consecutive,st1_strided, - luti_consecutive,luti_strided" + "none,ld1_consecutive,ld1_strided,st1_consecutive,st1_strided" (const_string "none")) ;; Attribute used to identify load pair and store pair instructions. diff --git a/gcc/testsuite/gcc.target/aarch64/sme/strided_1.c b/gcc/testsuite/gcc.target/aarch64/sme/strided_1.c index 3620fff..73aac06 100644 --- a/gcc/testsuite/gcc.target/aarch64/sme/strided_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sme/strided_1.c @@ -181,61 +181,6 @@ void test4(int32_t *dest, int32_t *src) __arm_streaming } /* -** test5: -** ptrue [^\n]+ -** ld1b [^\n]+ -** ld1b [^\n]+ -** ptrue ([^\n]+)\.s -** ld1w [^\n]+, \1/z, \[x0\] -** luti4 {z16\.s, z20\.s, z24\.s, z28\.s}, zt0, z[0-9]+\[0\] -** luti4 {z17\.s, z21\.s, z25\.s, z29\.s}, zt0, z[0-9]+\[1\] -** luti4 {z18\.s, z22\.s, z26\.s, z30\.s}, zt0, z[0-9]+\[0\] -** luti4 {z19\.s, z23\.s, z27\.s, z31\.s}, zt0, z[0-9]+\[1\] -** uclamp {z16\.s - z19\.s}, z[0-9]+\.s, z[0-9]+\.s -** uclamp {z20\.s - z23\.s}, z[0-9]+\.s, z[0-9]+\.s -** uclamp {z24\.s - z27\.s}, z[0-9]+\.s, z[0-9]+\.s -** uclamp {z28\.s - z31\.s}, z[0-9]+\.s, z[0-9]+\.s -** st1w {z16\.s - z19\.s}, \1, \[x0\] -** st1w {z20\.s - z23\.s}, \1, \[x0, #4, mul vl\] -** st1w {z24\.s - z27\.s}, \1, \[x0, #8, mul vl\] -** st1w {z28\.s - z31\.s}, \1, \[x0, #12, mul vl\] -** ret -*/ -void test5(uint32_t *dest, uint8_t *indices) - __arm_streaming __arm_preserves("za") __arm_inout("zt0") -{ - svuint8_t indices1 = svld1_vnum(svptrue_b8(), indices, 0); - svuint8_t indices2 = svld1_vnum(svptrue_b8(), indices, 2); - - svcount_t pg = svptrue_c32(); - svuint32x4_t bounds = svld1_x4(pg, dest); - - svuint32x4_t x0 = svluti4_lane_zt_u32_x4(0, indices1, 0); - svuint32x4_t x1 = svluti4_lane_zt_u32_x4(0, indices1, 1); - svuint32x4_t x2 = svluti4_lane_zt_u32_x4(0, indices2, 0); - svuint32x4_t x3 = svluti4_lane_zt_u32_x4(0, indices2, 1); - - svuint32x4_t y0 = svcreate4(svget4(x0, 0), svget4(x1, 0), - svget4(x2, 0), svget4(x3, 0)); - svuint32x4_t y1 = svcreate4(svget4(x0, 1), svget4(x1, 1), - svget4(x2, 1), svget4(x3, 1)); - svuint32x4_t y2 = svcreate4(svget4(x0, 2), svget4(x1, 2), - svget4(x2, 2), svget4(x3, 2)); - svuint32x4_t y3 = svcreate4(svget4(x0, 3), svget4(x1, 3), - svget4(x2, 3), svget4(x3, 3)); - - y0 = svclamp(y0, svget4(bounds, 0), svget4(bounds, 1)); - y1 = svclamp(y1, svget4(bounds, 2), svget4(bounds, 3)); - y2 = svclamp(y2, svget4(bounds, 0), svget4(bounds, 1)); - y3 = svclamp(y3, svget4(bounds, 2), svget4(bounds, 3)); - - svst1_vnum(pg, dest, 0, y0); - svst1_vnum(pg, dest, 4, y1); - svst1_vnum(pg, dest, 8, y2); - svst1_vnum(pg, dest, 12, y3); -} - -/* ** test6: ** ptrue [^\n]+ ** ld1h [^\n]+ -- cgit v1.1 From fca6f6fddb22b8665e840f455a7d0318d4575227 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 5 Mar 2024 19:48:25 +0000 Subject: asan: Handle poly-int sizes in ASAN_MARK [PR97696] This patch makes the expansion of IFN_ASAN_MARK let through poly-int-sized objects. The expansion itself was already generic enough, but the tests for the fast path were too strict. gcc/ PR sanitizer/97696 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int. gcc/testsuite/ PR sanitizer/97696 * gcc.target/aarch64/sve/pr97696.c: New test. --- gcc/asan.cc | 9 ++++---- gcc/testsuite/gcc.target/aarch64/sve/pr97696.c | 29 ++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr97696.c (limited to 'gcc') diff --git a/gcc/asan.cc b/gcc/asan.cc index 0fd7dd1..d621ec9 100644 --- a/gcc/asan.cc +++ b/gcc/asan.cc @@ -3795,9 +3795,7 @@ asan_expand_mark_ifn (gimple_stmt_iterator *iter) } tree len = gimple_call_arg (g, 2); - gcc_assert (tree_fits_shwi_p (len)); - unsigned HOST_WIDE_INT size_in_bytes = tree_to_shwi (len); - gcc_assert (size_in_bytes); + gcc_assert (poly_int_tree_p (len)); g = gimple_build_assign (make_ssa_name (pointer_sized_int_node), NOP_EXPR, base); @@ -3806,9 +3804,10 @@ asan_expand_mark_ifn (gimple_stmt_iterator *iter) tree base_addr = gimple_assign_lhs (g); /* Generate direct emission if size_in_bytes is small. */ - if (size_in_bytes - <= (unsigned)param_use_after_scope_direct_emission_threshold) + unsigned threshold = param_use_after_scope_direct_emission_threshold; + if (tree_fits_uhwi_p (len) && tree_to_uhwi (len) <= threshold) { + unsigned HOST_WIDE_INT size_in_bytes = tree_to_uhwi (len); const unsigned HOST_WIDE_INT shadow_size = shadow_mem_size (size_in_bytes); const unsigned int shadow_align diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr97696.c b/gcc/testsuite/gcc.target/aarch64/sve/pr97696.c new file mode 100644 index 0000000..8b7de18 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr97696.c @@ -0,0 +1,29 @@ +/* { dg-skip-if "" { no_fsanitize_address } } */ +/* { dg-options "-fsanitize=address -fsanitize-address-use-after-scope" } */ + +#include + +__attribute__((noinline, noclone)) int +foo (char *a) +{ + int i, j = 0; + asm volatile ("" : "+r" (a) : : "memory"); + for (i = 0; i < 12; i++) + j += a[i]; + return j; +} + +int +main () +{ + int i, j = 0; + for (i = 0; i < 4; i++) + { + char a[12]; + __SVInt8_t freq; + __builtin_bcmp (&freq, a, 10); + __builtin_memset (a, 0, sizeof (a)); + j += foo (a); + } + return j; +} -- cgit v1.1 From 5d24bf3afd1bea3e51b87fb7ff24c21e29913999 Mon Sep 17 00:00:00 2001 From: Cupertino Miranda Date: Thu, 29 Feb 2024 10:56:13 -0800 Subject: ctf: fix incorrect CTF for multi-dimensional array types PR debug/114186 DWARF DIEs of type DW_TAG_subrange_type are linked together to represent the information about the subsequent dimensions. The CTF processing was so far working through them in the opposite (incorrect) order. While fixing the issue, refactor the code a bit for readability. co-authored-By: Indu Bhagat gcc/ PR debug/114186 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array () in the correct order of the dimensions. (gen_ctf_subrange_type): Refactor out handling of DW_TAG_subrange_type DIE to here. gcc/testsuite/ PR debug/114186 * gcc.dg/debug/ctf/ctf-array-6.c: Add test. --- gcc/dwarf2ctf.cc | 158 +++++++++++++-------------- gcc/testsuite/gcc.dg/debug/ctf/ctf-array-6.c | 14 +++ 2 files changed, 89 insertions(+), 83 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/debug/ctf/ctf-array-6.c (limited to 'gcc') diff --git a/gcc/dwarf2ctf.cc b/gcc/dwarf2ctf.cc index dca86ed..77d6bf8 100644 --- a/gcc/dwarf2ctf.cc +++ b/gcc/dwarf2ctf.cc @@ -349,105 +349,97 @@ gen_ctf_pointer_type (ctf_container_ref ctfc, dw_die_ref ptr_type) return ptr_type_id; } -/* Generate CTF for an array type. */ +/* Recursively generate CTF for array dimensions starting at DIE C (of type + DW_TAG_subrange_type) until DIE LAST (of type DW_TAG_subrange_type) is + reached. ARRAY_ELEMS_TYPE_ID is base type for the array. */ static ctf_id_t -gen_ctf_array_type (ctf_container_ref ctfc, dw_die_ref array_type) +gen_ctf_subrange_type (ctf_container_ref ctfc, ctf_id_t array_elems_type_id, + dw_die_ref c, dw_die_ref last) { - dw_die_ref c; - ctf_id_t array_elems_type_id = CTF_NULL_TYPEID; + ctf_arinfo_t arinfo; + ctf_id_t array_node_type_id = CTF_NULL_TYPEID; - int vector_type_p = get_AT_flag (array_type, DW_AT_GNU_vector); - if (vector_type_p) - return array_elems_type_id; + dw_attr_node *upper_bound_at; + dw_die_ref array_index_type; + uint32_t array_num_elements; - dw_die_ref array_elems_type = ctf_get_AT_type (array_type); + if (dw_get_die_tag (c) == DW_TAG_subrange_type) + { + /* When DW_AT_upper_bound is used to specify the size of an + array in DWARF, it is usually an unsigned constant + specifying the upper bound index of the array. However, + for unsized arrays, such as foo[] or bar[0], + DW_AT_upper_bound is a signed integer constant + instead. */ + + upper_bound_at = get_AT (c, DW_AT_upper_bound); + if (upper_bound_at + && AT_class (upper_bound_at) == dw_val_class_unsigned_const) + /* This is the upper bound index. */ + array_num_elements = get_AT_unsigned (c, DW_AT_upper_bound) + 1; + else if (get_AT (c, DW_AT_count)) + array_num_elements = get_AT_unsigned (c, DW_AT_count); + else + { + /* This is a VLA of some kind. */ + array_num_elements = 0; + } + } + else + gcc_unreachable (); - /* First, register the type of the array elements if needed. */ - array_elems_type_id = gen_ctf_type (ctfc, array_elems_type); + /* Ok, mount and register the array type. Note how the array + type we register here is the type of the elements in + subsequent "dimensions", if there are any. */ + arinfo.ctr_nelems = array_num_elements; - /* DWARF array types pretend C supports multi-dimensional arrays. - So for the type int[N][M], the array type DIE contains two - subrange_type children, the first with upper bound N-1 and the - second with upper bound M-1. + array_index_type = ctf_get_AT_type (c); + arinfo.ctr_index = gen_ctf_type (ctfc, array_index_type); - CTF, on the other hand, just encodes each array type in its own - array type CTF struct. Therefore we have to iterate on the - children and create all the needed types. */ + if (c == last) + arinfo.ctr_contents = array_elems_type_id; + else + arinfo.ctr_contents = gen_ctf_subrange_type (ctfc, array_elems_type_id, + dw_get_die_sib (c), last); - c = dw_get_die_child (array_type); - gcc_assert (c); - do - { - ctf_arinfo_t arinfo; - dw_die_ref array_index_type; - uint32_t array_num_elements; + if (!ctf_type_exists (ctfc, c, &array_node_type_id)) + array_node_type_id = ctf_add_array (ctfc, CTF_ADD_ROOT, &arinfo, c); - c = dw_get_die_sib (c); + return array_node_type_id; +} - if (dw_get_die_tag (c) == DW_TAG_subrange_type) - { - dw_attr_node *upper_bound_at; - - array_index_type = ctf_get_AT_type (c); - - /* When DW_AT_upper_bound is used to specify the size of an - array in DWARF, it is usually an unsigned constant - specifying the upper bound index of the array. However, - for unsized arrays, such as foo[] or bar[0], - DW_AT_upper_bound is a signed integer constant - instead. */ - - upper_bound_at = get_AT (c, DW_AT_upper_bound); - if (upper_bound_at - && AT_class (upper_bound_at) == dw_val_class_unsigned_const) - /* This is the upper bound index. */ - array_num_elements = get_AT_unsigned (c, DW_AT_upper_bound) + 1; - else if (get_AT (c, DW_AT_count)) - array_num_elements = get_AT_unsigned (c, DW_AT_count); - else - { - /* This is a VLA of some kind. */ - array_num_elements = 0; - } - } - else if (dw_get_die_tag (c) == DW_TAG_enumeration_type) - { - array_index_type = 0; - array_num_elements = 0; - /* XXX writeme. */ - gcc_assert (1); - } - else - gcc_unreachable (); +/* Generate CTF for an ARRAY_TYPE. */ - /* Ok, mount and register the array type. Note how the array - type we register here is the type of the elements in - subsequent "dimensions", if there are any. */ +static ctf_id_t +gen_ctf_array_type (ctf_container_ref ctfc, + dw_die_ref array_type) +{ + dw_die_ref first, last, array_elems_type; + ctf_id_t array_elems_type_id = CTF_NULL_TYPEID; + ctf_id_t array_type_id = CTF_NULL_TYPEID; - arinfo.ctr_nelems = array_num_elements; - if (array_index_type) - arinfo.ctr_index = gen_ctf_type (ctfc, array_index_type); - else - arinfo.ctr_index = gen_ctf_type (ctfc, ctf_array_index_die); + int vector_type_p = get_AT_flag (array_type, DW_AT_GNU_vector); + if (vector_type_p) + return array_elems_type_id; - arinfo.ctr_contents = array_elems_type_id; - if (!ctf_type_exists (ctfc, c, &array_elems_type_id)) - array_elems_type_id = ctf_add_array (ctfc, CTF_ADD_ROOT, &arinfo, - c); - } - while (c != dw_get_die_child (array_type)); + /* Find the first and last array dimension DIEs. */ + last = dw_get_die_child (array_type); + first = dw_get_die_sib (last); -#if 0 /* Type de-duplication. - Consult the ctfc_types hash again before adding the CTF array type because - there can be cases where an array_type type may have been added by the - gen_ctf_type call above. */ - if (!ctf_type_exists (ctfc, array_type, &type_id)) - type_id = ctf_add_array (ctfc, CTF_ADD_ROOT, &arinfo, array_type); -#endif - - return array_elems_type_id; + Consult the ctfc_types before adding CTF type for the first dimension. */ + if (!ctf_type_exists (ctfc, first, &array_type_id)) + { + array_elems_type = ctf_get_AT_type (array_type); + /* First, register the type of the array elements if needed. */ + array_elems_type_id = gen_ctf_type (ctfc, array_elems_type); + + array_type_id = gen_ctf_subrange_type (ctfc, array_elems_type_id, first, + last); + } + + return array_type_id; } /* Generate CTF for a typedef. */ diff --git a/gcc/testsuite/gcc.dg/debug/ctf/ctf-array-6.c b/gcc/testsuite/gcc.dg/debug/ctf/ctf-array-6.c new file mode 100644 index 0000000..5564cb8 --- /dev/null +++ b/gcc/testsuite/gcc.dg/debug/ctf/ctf-array-6.c @@ -0,0 +1,14 @@ +/* CTF generation for multidimensional array. */ + +/* { dg-do compile ) */ +/* { dg-options "-O0 -gctf -dA" } */ + +/* { dg-final { scan-assembler-times "\[\t \]+0x2\[\t \]+\[^\n\]*cta_nelems" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]+0x3\[\t \]+\[^\n\]*cta_nelems" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]+0x4\[\t \]+\[^\n\]*cta_nelems" 1 } } */ + +/* { dg-final { scan-assembler-times "\[\t \]+0x1\[\t \]+\[^\n\]*cta_contents\[\\r\\n\]+\[^\\r\\n\]*\[\\r\\n\]+\[^\\r\\n\]*0x4\[\t \]+\[^\n\]*cta_nelems" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]+0x3\[\t \]+\[^\n\]*cta_contents\[\\r\\n\]+\[^\\r\\n\]*\[\\r\\n\]+\[^\\r\\n\]*0x3\[\t \]+\[^\n\]*cta_nelems" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]+0x4\[\t \]+\[^\n\]*cta_contents\[\\r\\n\]+\[^\\r\\n\]*\[\\r\\n\]+\[^\\r\\n\]*0x2\[\t \]+\[^\n\]*cta_nelems" 1 } } */ + +int a[2][3][4]; -- cgit v1.1 From 214dadf30a3bab0d02b8c6512a2d0475e2643dc7 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Wed, 6 Mar 2024 00:17:18 +0000 Subject: Daily bump. --- gcc/ChangeLog | 103 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 8 ++++ gcc/cp/ChangeLog | 5 +++ gcc/testsuite/ChangeLog | 63 +++++++++++++++++++++++++++++ 5 files changed, 180 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5eb0d89..89da260 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,106 @@ +2024-03-05 Cupertino Miranda + Indu Bhagat + + PR debug/114186 + * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array () + in the correct order of the dimensions. + (gen_ctf_subrange_type): Refactor out handling of + DW_TAG_subrange_type DIE to here. + +2024-03-05 Richard Sandiford + + PR sanitizer/97696 + * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int. + +2024-03-05 Richard Sandiford + + * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive + and luti_strided. + * config/aarch64/aarch64-sme.md + (@aarch64_sme_lut): Remove stride_type attribute. + (@aarch64_sme_lut_strided2): Delete. + (@aarch64_sme_lut_strided4): Likewise. + * config/aarch64/aarch64-early-ra.cc (is_stride_candidate) + (early_ra::maybe_convert_to_strided_access): Remove support for + strided LUTI2 and LUTI4. + +2024-03-05 Richard Earnshaw + + PR target/113510 + * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use + low_register_operand. + +2024-03-05 Georg-Johann Lay + + * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND + in HI, PSI, SI that swap operation order from "X = CST, X o= Y" + to "X = Y, X o= CST". + +2024-03-05 Xi Ruoyao + + * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add + s9 as an alias of r22. + +2024-03-05 Roger Sayle + + * config/avr/avr-protos.h (avr_out_insv): New proto. + * config/avr/avr.cc (avr_out_insv): New function. + (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case. + (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs. + * config/avr/avr.md (define_attr "adjust_len") Add insv. + (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3): + Add constraint alternative where the 3rd operand is a power + of 2, and the source register may differ from the destination. + (*insv.any_shift._split): Call avr_out_insv to output + instructions. Set attr "length" to "insv". + * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints. + +2024-03-05 Richard Biener + + PR tree-optimization/114231 + * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when + processing a BB SLP root. + +2024-03-05 Jakub Jelinek + + PR rtl-optimization/114211 + * lower-subreg.cc (resolve_simple_move): For double-word + rotates by BITS_PER_WORD if there is overlap between source + and destination use a temporary. + +2024-03-05 Jakub Jelinek + + PR middle-end/114157 + * gimple-lower-bitint.cc: Include stor-layout.h. + (mergeable_op): Return true for BIT_FIELD_REF. + (struct bitint_large_huge): Declare handle_bit_field_ref method. + (bitint_large_huge::handle_bit_field_ref): New method. + (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF. + +2024-03-05 Jakub Jelinek + + PR target/114116 + * config/i386/i386.h (enum call_saved_registers_type): Add + TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator. + * config/i386/i386-options.cc (ix86_set_func_type): Remove + has_no_callee_saved_registers variable, add no_callee_saved_registers + instead, initialize it depending on whether it is + no_callee_saved_registers function or not. Don't set it if + no_caller_saved_registers attribute is present. Adjust users. + * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle + TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like + TYPE_NO_CALLEE_SAVED_REGISTERS. + (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP. + +2024-03-05 Pan Li + + * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused + mode_size related code. + +2024-03-05 Patrick Palka + + * doc/invoke.texi (-Wno-global-module): Document. + 2024-03-04 David Faust * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 8585b3d..c7e324d 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240305 +20240306 diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog index a8f5bfb..c6450d7 100644 --- a/gcc/c-family/ChangeLog +++ b/gcc/c-family/ChangeLog @@ -1,3 +1,11 @@ +2024-03-05 Mark Wielaard + + * c.opt.urls: Regenerate. + +2024-03-05 Patrick Palka + + * c.opt (Wglobal-module): New warning. + 2024-03-04 Mark Wielaard * c.opt.urls: Regenerate. diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index e6a6fbd..41e9a44 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,8 @@ +2024-03-05 Patrick Palka + + * parser.cc (cp_parser_translation_unit): Relax GMF contents + error into a pedwarn. + 2024-03-04 Nathaniel Shead * name-lookup.cc (walk_module_binding): Remove completed FIXME. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5379865..3e20a20 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,66 @@ +2024-03-05 Cupertino Miranda + Indu Bhagat + + PR debug/114186 + * gcc.dg/debug/ctf/ctf-array-6.c: Add test. + +2024-03-05 Richard Sandiford + + PR sanitizer/97696 + * gcc.target/aarch64/sve/pr97696.c: New test. + +2024-03-05 Richard Sandiford + + * gcc.target/aarch64/sme/strided_1.c (test5): Remove. + +2024-03-05 Saurabh Jha + + PR target/112337 + * gcc.target/arm/pr112337.c: Check for, then use the right MVE + options. + +2024-03-05 Xi Ruoyao + + * gcc.target/loongarch/regname-fp-s9.c: New test. + +2024-03-05 Roger Sayle + + * gcc.target/avr/torture/insv-anyshift-hi.c: New test. + * gcc.target/avr/torture/insv-anyshift-si.c: New test. + +2024-03-05 Richard Biener + + PR tree-optimization/114231 + * gcc.dg/vect/pr114231.c: New testcase. + +2024-03-05 Jakub Jelinek + + PR rtl-optimization/114211 + * gcc.dg/pr114211.c: New test. + +2024-03-05 Jakub Jelinek + + PR middle-end/114157 + * gcc.dg/bitint-98.c: New test. + * gcc.target/i386/avx2-pr114157.c: New test. + * gcc.target/i386/avx512f-pr114157.c: New test. + +2024-03-05 Jakub Jelinek + + PR target/114116 + * gcc.target/i386/pr38534-1.c: Allow push/pop of bp. + * gcc.target/i386/pr38534-4.c: Likewise. + * gcc.target/i386/pr38534-2.c: Likewise. + * gcc.target/i386/pr38534-3.c: Likewise. + * gcc.target/i386/pr114097-1.c: Likewise. + * gcc.target/i386/stack-check-17.c: Expect no pop on ! ia32. + +2024-03-05 Patrick Palka + + * g++.dg/modules/friend-6_a.C: Pass -Wno-global-module instead + of -Wno-pedantic. Remove now unnecessary preprocessing + directives from GMF. + 2024-03-04 Nathaniel Shead * g++.dg/modules/using-12.C: New test. -- cgit v1.1 From b0d11bb02a4a4c7d61e9b53411ccdc54610b1429 Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Tue, 5 Mar 2024 20:36:36 -0500 Subject: c++/modules: befriending template from current class scope Here the TEMPLATE_DECL representing the template friend declaration naming B has class scope since the template B has class scope, but get_merge_kind assumes all DECL_UNINSTANTIATED_TEMPLATE_FRIEND_P TEMPLATE_DECL have namespace scope and wrongly returns MK_named instead of MK_local_friend for the friend. gcc/cp/ChangeLog: * module.cc (trees_out::get_merge_kind) : Accomodate class-scope DECL_UNINSTANTIATED_TEMPLATE_FRIEND_P TEMPLATE_DECL. Consolidate IDENTIFIER_ANON_P cases. gcc/testsuite/ChangeLog: * g++.dg/modules/friend-7.h: New test. * g++.dg/modules/friend-7_a.H: New test. * g++.dg/modules/friend-7_b.C: New test. Reviewed-by: Jason Merrill --- gcc/cp/module.cc | 19 +++++++++---------- gcc/testsuite/g++.dg/modules/friend-7.h | 5 +++++ gcc/testsuite/g++.dg/modules/friend-7_a.H | 3 +++ gcc/testsuite/g++.dg/modules/friend-7_b.C | 6 ++++++ 4 files changed, 23 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/g++.dg/modules/friend-7.h create mode 100644 gcc/testsuite/g++.dg/modules/friend-7_a.H create mode 100644 gcc/testsuite/g++.dg/modules/friend-7_b.C (limited to 'gcc') diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc index 67f132d..80b63a7 100644 --- a/gcc/cp/module.cc +++ b/gcc/cp/module.cc @@ -10498,21 +10498,20 @@ trees_out::get_merge_kind (tree decl, depset *dep) } } - if (RECORD_OR_UNION_TYPE_P (ctx)) + if (TREE_CODE (decl) == TEMPLATE_DECL + && DECL_UNINSTANTIATED_TEMPLATE_FRIEND_P (decl)) { - if (IDENTIFIER_ANON_P (DECL_NAME (decl))) - mk = MK_field; + mk = MK_local_friend; break; } - if (TREE_CODE (decl) == TEMPLATE_DECL - && DECL_UNINSTANTIATED_TEMPLATE_FRIEND_P (decl)) - mk = MK_local_friend; - else if (IDENTIFIER_ANON_P (DECL_NAME (decl))) + if (IDENTIFIER_ANON_P (DECL_NAME (decl))) { - if (DECL_IMPLICIT_TYPEDEF_P (decl) - && UNSCOPED_ENUM_P (TREE_TYPE (decl)) - && TYPE_VALUES (TREE_TYPE (decl))) + if (RECORD_OR_UNION_TYPE_P (ctx)) + mk = MK_field; + else if (DECL_IMPLICIT_TYPEDEF_P (decl) + && UNSCOPED_ENUM_P (TREE_TYPE (decl)) + && TYPE_VALUES (TREE_TYPE (decl))) /* Keyed by first enum value, and underlying type. */ mk = MK_enum; else diff --git a/gcc/testsuite/g++.dg/modules/friend-7.h b/gcc/testsuite/g++.dg/modules/friend-7.h new file mode 100644 index 0000000..c0f0039 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/friend-7.h @@ -0,0 +1,5 @@ +template +struct A { + template struct B { }; + template friend struct B; +}; diff --git a/gcc/testsuite/g++.dg/modules/friend-7_a.H b/gcc/testsuite/g++.dg/modules/friend-7_a.H new file mode 100644 index 0000000..e750e4c --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/friend-7_a.H @@ -0,0 +1,3 @@ +// { dg-additional-options "-fmodule-header" } +// { dg-module-cmi {} } +#include "friend-7.h" diff --git a/gcc/testsuite/g++.dg/modules/friend-7_b.C b/gcc/testsuite/g++.dg/modules/friend-7_b.C new file mode 100644 index 0000000..eb5e45a --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/friend-7_b.C @@ -0,0 +1,6 @@ +// { dg-additional-options "-fmodules-ts" } +#include "friend-7.h" +import "friend-7_a.H"; + +A a; +A::B b; -- cgit v1.1 From 21edfb0051ed8d0ff46d5638c2bce2dd71f26d1f Mon Sep 17 00:00:00 2001 From: Jerry DeLisle Date: Tue, 5 Mar 2024 20:49:23 -0800 Subject: Fortran: Add user defined error messages for UDTIO. The defines IOMSG_LEN and MSGLEN were redundant so these are combined into IOMSG_LEN as defined in io.h. The remainder of the patch adds checks for when a user defined derived type IO procedure sets the IOSTAT or IOMSG variables independent of the librrary defined I/O messages. PR libfortran/105456 libgfortran/ChangeLog: * io/io.h (IOMSG_LEN): Moved to here. * io/list_read.c (MSGLEN): Removed MSGLEN. (convert_integer): Changed MSGLEN to IOMSG_LEN. (parse_repeat): Likewise. (read_logical): Likewise. (read_integer): Likewise. (read_character): Likewise. (parse_real): Likewise. (read_complex): Likewise. (read_real): Likewise. (check_type): Likewise. (list_formatted_read_scalar): Adjust to IOMSG_LEN. (nml_read_obj): Add user defined error message. * io/transfer.c (unformatted_read): Add user defined error message. (unformatted_write): Add user defined error message. (formatted_transfer_scalar_read): Add user defined error message. (formatted_transfer_scalar_write): Add user defined error message. * io/write.c (list_formatted_write_scalar): Add user defined error message. (nml_write_obj): Add user defined error message. gcc/testsuite/ChangeLog: * gfortran.dg/pr105456-nmlr.f90: New test. * gfortran.dg/pr105456-nmlw.f90: New test. * gfortran.dg/pr105456-ruf.f90: New test. * gfortran.dg/pr105456-wf.f90: New test. * gfortran.dg/pr105456-wuf.f90: New test. --- gcc/testsuite/gfortran.dg/pr105456-nmlr.f90 | 60 +++++++++++++++++++++++++++++ gcc/testsuite/gfortran.dg/pr105456-nmlw.f90 | 60 +++++++++++++++++++++++++++++ gcc/testsuite/gfortran.dg/pr105456-ruf.f90 | 36 +++++++++++++++++ gcc/testsuite/gfortran.dg/pr105456-wf.f90 | 34 ++++++++++++++++ gcc/testsuite/gfortran.dg/pr105456-wuf.f90 | 34 ++++++++++++++++ 5 files changed, 224 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/pr105456-nmlr.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr105456-nmlw.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr105456-ruf.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr105456-wf.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr105456-wuf.f90 (limited to 'gcc') diff --git a/gcc/testsuite/gfortran.dg/pr105456-nmlr.f90 b/gcc/testsuite/gfortran.dg/pr105456-nmlr.f90 new file mode 100644 index 0000000..5ce5d08 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr105456-nmlr.f90 @@ -0,0 +1,60 @@ +! { dg-do run } +! { dg-shouldfail "The users message" } +module m + implicit none + type :: t + character :: c + integer :: k + contains + procedure :: write_formatted + generic :: write(formatted) => write_formatted + procedure :: read_formatted + generic :: read(formatted) => read_formatted + end type +contains + subroutine write_formatted(dtv, unit, iotype, v_list, iostat, iomsg) + class(t), intent(in) :: dtv + integer, intent(in) :: unit + character(*), intent(in) :: iotype + integer, intent(in) :: v_list(:) + integer, intent(out) :: iostat + character(*), intent(inout) :: iomsg + if (iotype.eq."NAMELIST") then + write (unit, '(a1,a1,i3)') dtv%c,',', dtv%k + else + write (unit,*) dtv%c, dtv%k + end if + end subroutine + subroutine read_formatted(dtv, unit, iotype, v_list, iostat, iomsg) + class(t), intent(inout) :: dtv + integer, intent(in) :: unit + character(*), intent(in) :: iotype + integer, intent(in) :: v_list(:) + integer, intent(out) :: iostat + character(*), intent(inout) :: iomsg + character :: comma + if (iotype.eq."NAMELIST") then + read (unit, '(a1,a1,i3)') dtv%c, comma, dtv%k + else + read (unit,*) dtv%c, comma, dtv%k + endif + iostat = 42 + iomsg = "The users message" + if (comma /= ',') STOP 1 + end subroutine +end module + +program p + use m + implicit none + character(len=50) :: buffer + type(t) :: x + namelist /nml/ x + x = t('a', 5) + write (buffer, nml) + if (buffer.ne.' &NML X=a, 5 /') STOP 1 + x = t('x', 0) + read (buffer, nml) + if (x%c.ne.'a'.or. x%k.ne.5) STOP 2 +end +! { dg-output "Fortran runtime error: The users message" } diff --git a/gcc/testsuite/gfortran.dg/pr105456-nmlw.f90 b/gcc/testsuite/gfortran.dg/pr105456-nmlw.f90 new file mode 100644 index 0000000..2c496e6 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr105456-nmlw.f90 @@ -0,0 +1,60 @@ +! { dg-do run } +! { dg-shouldfail "The users message" } +module m + implicit none + type :: t + character :: c + integer :: k + contains + procedure :: write_formatted + generic :: write(formatted) => write_formatted + procedure :: read_formatted + generic :: read(formatted) => read_formatted + end type +contains + subroutine write_formatted(dtv, unit, iotype, v_list, iostat, iomsg) + class(t), intent(in) :: dtv + integer, intent(in) :: unit + character(*), intent(in) :: iotype + integer, intent(in) :: v_list(:) + integer, intent(out) :: iostat + character(*), intent(inout) :: iomsg + if (iotype.eq."NAMELIST") then + write (unit, '(a1,a1,i3)') dtv%c,',', dtv%k + else + write (unit,*) dtv%c, dtv%k + end if + iostat = 42 + iomsg = "The users message" + end subroutine + subroutine read_formatted(dtv, unit, iotype, v_list, iostat, iomsg) + class(t), intent(inout) :: dtv + integer, intent(in) :: unit + character(*), intent(in) :: iotype + integer, intent(in) :: v_list(:) + integer, intent(out) :: iostat + character(*), intent(inout) :: iomsg + character :: comma + if (iotype.eq."NAMELIST") then + read (unit, '(a1,a1,i3)') dtv%c, comma, dtv%k + else + read (unit,*) dtv%c, comma, dtv%k + end if + if (comma /= ',') STOP 1 + end subroutine +end module + +program p + use m + implicit none + character(len=50) :: buffer + type(t) :: x + namelist /nml/ x + x = t('a', 5) + write (buffer, nml) + if (buffer.ne.' &NML X=a, 5 /') STOP 1 + x = t('x', 0) + read (buffer, nml) + if (x%c.ne.'a'.or. x%k.ne.5) STOP 2 +end +! { dg-output "Fortran runtime error: The users message" } diff --git a/gcc/testsuite/gfortran.dg/pr105456-ruf.f90 b/gcc/testsuite/gfortran.dg/pr105456-ruf.f90 new file mode 100644 index 0000000..c176c4a --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr105456-ruf.f90 @@ -0,0 +1,36 @@ +! { dg-do run } +! { dg-shouldfail "The users message" } +module sk1 + implicit none + type char + character :: ch + end type char + interface read (unformatted) + module procedure read_unformatted + end interface read (unformatted) +contains + subroutine read_unformatted (dtv, unit, piostat, piomsg) + class (char), intent(inout) :: dtv + integer, intent(in) :: unit + !character (len=*), intent(in) :: iotype + !integer, intent(in) :: vlist(:) + integer, intent(out) :: piostat + character (len=*), intent(inout) :: piomsg + read (unit,fmt='(A1)', advance="no", iostat=piostat, iomsg=piomsg) dtv%ch + piostat = 42 + piomsg="The users message" + end subroutine read_unformatted +end module sk1 + +program skip1 + use sk1 + implicit none + type (char) :: x + x%ch = 'X' + open (10, form='unformatted', status='scratch') + write (10) 'X' + rewind (10) + read (10) x +end program skip1 +! { dg-output ".*(unit = 10, file = .*)" } +! { dg-output "Fortran runtime error: The users message" } diff --git a/gcc/testsuite/gfortran.dg/pr105456-wf.f90 b/gcc/testsuite/gfortran.dg/pr105456-wf.f90 new file mode 100644 index 0000000..f1c5350 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr105456-wf.f90 @@ -0,0 +1,34 @@ +! { dg-do run } +! { dg-shouldfail "The users message" } +module sk1 + implicit none + type char + character :: ch + end type char + interface write (formatted) + module procedure write_formatted + end interface write (formatted) +contains + subroutine write_formatted (dtv, unit, iotype, vlist, piostat, piomsg) + class (char), intent(in) :: dtv + integer, intent(in) :: unit + character (len=*), intent(in) :: iotype + integer, intent(in) :: vlist(:) + integer, intent(out) :: piostat + character (len=*), intent(inout) :: piomsg + write (unit,fmt='(A1)', advance="no", iostat=piostat, iomsg=piomsg) dtv%ch + piostat = 42 + piomsg="The users message" + end subroutine write_formatted +end module sk1 + +program skip1 + use sk1 + implicit none + type (char) :: x + x%ch = 'X' + open (10, status='scratch') + write (10,*) x +end program skip1 +! { dg-output ".*(unit = 10, file = .*)" } +! { dg-output "Fortran runtime error: The users message" } diff --git a/gcc/testsuite/gfortran.dg/pr105456-wuf.f90 b/gcc/testsuite/gfortran.dg/pr105456-wuf.f90 new file mode 100644 index 0000000..2b637b7 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr105456-wuf.f90 @@ -0,0 +1,34 @@ +! { dg-do run } +! { dg-shouldfail "The users message" } +module sk1 + implicit none + type char + character :: ch + end type char + interface write (unformatted) + module procedure write_unformatted + end interface write (unformatted) +contains + subroutine write_unformatted (dtv, unit, piostat, piomsg) + class (char), intent(in) :: dtv + integer, intent(in) :: unit + !character (len=*), intent(in) :: iotype + !integer, intent(in) :: vlist(:) + integer, intent(out) :: piostat + character (len=*), intent(inout) :: piomsg + write (unit,fmt='(A1)', advance="no", iostat=piostat, iomsg=piomsg) dtv%ch + piostat = 42 + piomsg="The users message" + end subroutine write_unformatted +end module sk1 + +program skip1 + use sk1 + implicit none + type (char) :: x + x%ch = 'X' + open (10, form='unformatted', status='scratch') + write (10) x +end program skip1 +! { dg-output ".*(unit = 10, file = .*)" } +! { dg-output "Fortran runtime error: The users message" } -- cgit v1.1 From 1157d5de35b41eabe5ee51d532224864173c37bd Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 6 Mar 2024 09:35:37 +0100 Subject: i386: Fix up the vzeroupper REG_DEAD/REG_UNUSED note workaround [PR114190] When writing the rest_of_handle_insert_vzeroupper workaround to manually remove all the REG_DEAD/REG_UNUSED notes from the IL, I've missed that there is a df_analyze () call right after it and that the problems added earlier in the pass, like df_note_add_problem () done during mode switching, doesn't affect just the next df_analyze () call right after it, but all other df_analyze () calls until the end of the current pass where df_finish_pass removes the optional problems. So, as can be seen on the following patch, the workaround doesn't actually work there, because while rest_of_handle_insert_vzeroupper carefully removes all REG_DEAD/REG_UNUSED notes, the df_analyze () call at the end of the function immediately adds them in again (so, I must say I have no idea why the workaround worked on the earlier testcases). Now, I could move the df_analyze () call just before the REG_DEAD/REG_UNUSED note removal loop, but I think the following patch is better, because the df_analyze () call doesn't have to recompute the problem when we don't care about it and will actively strip all traces of it away. 2024-03-06 Jakub Jelinek PR rtl-optimization/114190 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper): Call df_remove_problem for df_note before calling df_analyze. * gcc.target/i386/avx-pr114190.c: New test. --- gcc/config/i386/i386-features.cc | 1 + gcc/testsuite/gcc.target/i386/avx-pr114190.c | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx-pr114190.c (limited to 'gcc') diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc index d3b9ae8..1de2a07 100644 --- a/gcc/config/i386/i386-features.cc +++ b/gcc/config/i386/i386-features.cc @@ -2690,6 +2690,7 @@ rest_of_handle_insert_vzeroupper (void) } } + df_remove_problem (df_note); df_analyze (); return 0; } diff --git a/gcc/testsuite/gcc.target/i386/avx-pr114190.c b/gcc/testsuite/gcc.target/i386/avx-pr114190.c new file mode 100644 index 0000000..fc5b261 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-pr114190.c @@ -0,0 +1,27 @@ +/* PR rtl-optimization/114190 */ +/* { dg-do run { target avx } } */ +/* { dg-options "-O2 -fno-dce -fharden-compares -mavx --param=max-rtl-if-conversion-unpredictable-cost=136 -mno-avx512f -Wno-psabi" } */ + +#include "avx-check.h" + +typedef unsigned char U __attribute__((vector_size (64))); +typedef unsigned int V __attribute__((vector_size (64))); +U u; + +V +foo (V a, V b) +{ + u[0] = __builtin_sub_overflow (0, (int) a[0], &a[b[7] & 5]) ? -u[1] : -b[3]; + b ^= 0 != b; + return (V) u + (V) a + (V) b; +} + +static void +avx_test (void) +{ + V x = foo ((V) { 1 }, (V) { 0, 0, 0, 1 }); + if (x[0] != -1U) + __builtin_abort (); + if (x[3] != -2U) + __builtin_abort (); +} -- cgit v1.1 From 0249744a9fe0775c2c895727aeebec4c59fd5f95 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 6 Mar 2024 09:02:31 +0100 Subject: tree-optimization/114246 - invalid call argument from DSE The following makes sure to strip type conversions added by build_fold_addr_expr before placing the result in a call argument. PR tree-optimization/114246 * tree-ssa-dse.cc (increment_start_addr): Strip useless type conversions from the adjusted address. * gcc.dg/torture/pr114246.c: New testcase. --- gcc/testsuite/gcc.dg/torture/pr114246.c | 11 +++++++++++ gcc/tree-ssa-dse.cc | 2 ++ 2 files changed, 13 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/torture/pr114246.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/torture/pr114246.c b/gcc/testsuite/gcc.dg/torture/pr114246.c new file mode 100644 index 0000000..eb20db5 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr114246.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-w" } */ + +int a, b; + +void +foo (void) +{ + __builtin_memcpy (&a, (char *)&b - 1, 2); + __builtin_memcpy (&a, &b, 1); +} diff --git a/gcc/tree-ssa-dse.cc b/gcc/tree-ssa-dse.cc index 7c34851..fce4fc7 100644 --- a/gcc/tree-ssa-dse.cc +++ b/gcc/tree-ssa-dse.cc @@ -49,6 +49,7 @@ along with GCC; see the file COPYING3. If not see #include "cfgloop.h" #include "tree-data-ref.h" #include "internal-fn.h" +#include "tree-ssa.h" /* This file implements dead store elimination. @@ -658,6 +659,7 @@ increment_start_addr (gimple *stmt, tree *where, int increment) *where, build_int_cst (ptr_type_node, increment))); + STRIP_USELESS_TYPE_CONVERSION (*where); } /* STMT is builtin call that writes bytes in bitmap ORIG, some bytes are dead -- cgit v1.1 From 3a910114fdb2aa76495c4c748acf6b9c7fbecc89 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 6 Mar 2024 09:25:15 +0100 Subject: tree-optimization/114249 - ICE with BB reduction vectorization When we scrap the last def of an odd lane numbered BB reduction we can end up recording a pattern def which will later wreck code generation. The following puts this logic where it better belongs, avoiding this issue. PR tree-optimization/114249 * tree-vect-slp.cc (vect_build_slp_instance): Move making a BB reduction lane number even ... (vect_slp_check_for_roots): ... here to avoid leaking pattern defs. * gcc.dg/vect/bb-slp-pr114249.c: New testcase. --- gcc/testsuite/gcc.dg/vect/bb-slp-pr114249.c | 20 ++++++++++++++++++++ gcc/tree-vect-slp.cc | 20 ++++++++++---------- 2 files changed, 30 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr114249.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr114249.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr114249.c new file mode 100644 index 0000000..64c93cd --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr114249.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ + +enum { SEG_THIN_POOL } read_only; +struct { + unsigned skip_block_zeroing; + unsigned ignore_discard; + unsigned no_discard_passdown; + unsigned error_if_no_space; +} _thin_pool_emit_segment_line_seg; +void dm_snprintf(); +void _emit_segment() +{ + int features = + (_thin_pool_emit_segment_line_seg.error_if_no_space ? 1 : 0) + + (read_only ? 1 : 0) + + (_thin_pool_emit_segment_line_seg.ignore_discard ? 1 : 0) + + (_thin_pool_emit_segment_line_seg.no_discard_passdown ? 1 : 0) + + (_thin_pool_emit_segment_line_seg.skip_block_zeroing ? 1 : 0); + dm_snprintf(features); +} diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc index 324400d..527b06c 100644 --- a/gcc/tree-vect-slp.cc +++ b/gcc/tree-vect-slp.cc @@ -3288,15 +3288,6 @@ vect_build_slp_instance (vec_info *vinfo, " %G", scalar_stmts[i]->stmt); } - /* When a BB reduction doesn't have an even number of lanes - strip it down, treating the remaining lane as scalar. - ??? Selecting the optimal set of lanes to vectorize would be nice - but SLP build for all lanes will fail quickly because we think - we're going to need unrolling. */ - if (kind == slp_inst_kind_bb_reduc - && (scalar_stmts.length () & 1)) - remain.safe_insert (0, gimple_get_lhs (scalar_stmts.pop ()->stmt)); - /* Build the tree for the SLP instance. */ unsigned int group_size = scalar_stmts.length (); bool *matches = XALLOCAVEC (bool, group_size); @@ -7549,6 +7540,7 @@ vect_slp_check_for_roots (bb_vec_info bb_vinfo) /* ??? For now do not allow mixing ops or externs/constants. */ bool invalid = false; unsigned remain_cnt = 0; + unsigned last_idx = 0; for (unsigned i = 0; i < chain.length (); ++i) { if (chain[i].code != code) @@ -7563,7 +7555,13 @@ vect_slp_check_for_roots (bb_vec_info bb_vinfo) (chain[i].op)->stmt) != chain[i].op)) remain_cnt++; + else + last_idx = i; } + /* Make sure to have an even number of lanes as we later do + all-or-nothing discovery, not trying to split further. */ + if ((chain.length () - remain_cnt) & 1) + remain_cnt++; if (!invalid && chain.length () - remain_cnt > 1) { vec stmts; @@ -7576,7 +7574,9 @@ vect_slp_check_for_roots (bb_vec_info bb_vinfo) stmt_vec_info stmt_info; if (chain[i].dt == vect_internal_def && ((stmt_info = bb_vinfo->lookup_def (chain[i].op)), - gimple_get_lhs (stmt_info->stmt) == chain[i].op)) + gimple_get_lhs (stmt_info->stmt) == chain[i].op) + && (i != last_idx + || (stmts.length () & 1))) stmts.quick_push (stmt_info); else remain.quick_push (chain[i].op); -- cgit v1.1 From 49d83e963aa453600088380aebd507e172eb80ad Mon Sep 17 00:00:00 2001 From: Nathaniel Shead Date: Wed, 6 Mar 2024 00:43:22 +1100 Subject: c++: Fix template deduction for conversion operators with xobj parameters [PR113629] Unification for conversion operators (DEDUCE_CONV) doesn't perform transformations like handling forwarding references. This is correct in general, but not for xobj parameters, which should be handled "normally" for the purposes of deduction: [temp.deduct.conv] only applies to the return type of the conversion function. PR c++/113629 gcc/cp/ChangeLog: * pt.cc (type_unification_real): Only use DEDUCE_CONV for the return type of a conversion function. gcc/testsuite/ChangeLog: * g++.dg/cpp23/explicit-obj-conv-op.C: New test. Signed-off-by: Nathaniel Shead Reviewed-by: Jason Merrill --- gcc/cp/pt.cc | 12 +++++- gcc/testsuite/g++.dg/cpp23/explicit-obj-conv-op.C | 49 +++++++++++++++++++++++ 2 files changed, 60 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.dg/cpp23/explicit-obj-conv-op.C (limited to 'gcc') diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc index c4bc54a..a6e6c80 100644 --- a/gcc/cp/pt.cc +++ b/gcc/cp/pt.cc @@ -23312,10 +23312,18 @@ type_unification_real (tree tparms, parameter pack is a non-deduced context. */ continue; + /* [temp.deduct.conv] only applies to the deduction of the return + type, which is always the first argument here. Other arguments + (notably, explicit object parameters) should undergo normal + call-like unification. */ + unification_kind_t kind = strict; + if (strict == DEDUCE_CONV && ia > 0) + kind = DEDUCE_CALL; + arg = args[ia]; ++ia; - if (unify_one_argument (tparms, full_targs, parm, arg, subr, strict, + if (unify_one_argument (tparms, full_targs, parm, arg, subr, kind, explain_p)) return 1; } @@ -23324,6 +23332,8 @@ type_unification_real (tree tparms, && parms != void_list_node && TREE_CODE (TREE_VALUE (parms)) == TYPE_PACK_EXPANSION) { + gcc_assert (strict != DEDUCE_CONV); + /* Unify the remaining arguments with the pack expansion type. */ tree argvec; tree parmvec = make_tree_vec (1); diff --git a/gcc/testsuite/g++.dg/cpp23/explicit-obj-conv-op.C b/gcc/testsuite/g++.dg/cpp23/explicit-obj-conv-op.C new file mode 100644 index 0000000..a6ae4ea --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp23/explicit-obj-conv-op.C @@ -0,0 +1,49 @@ +// PR c++/113629 +// { dg-do compile { target c++23 } } + +template constexpr bool is_lvalue = false; +template constexpr bool is_lvalue = true; + +struct A { + constexpr operator bool(this auto&& self) { + return is_lvalue; + } +}; + +constexpr A a; +static_assert(static_cast(a)); +static_assert((bool)a); +static_assert(!static_cast(A{})); +static_assert(!(bool)A{}); + +struct B : A {}; + +constexpr B b; +static_assert(static_cast(b)); +static_assert((bool)b); +static_assert(!static_cast(B{})); +static_assert(!(bool)B{}); + +struct C { + template + explicit constexpr operator R(this T&&) { + return is_lvalue; + } +}; + +constexpr C c; +static_assert(static_cast(c)); +static_assert((bool)c); +static_assert(!static_cast(C{})); +static_assert(!(bool)C{}); + +struct D { + explicit constexpr operator bool(this const D&) { return true; } + explicit constexpr operator bool(this const D&&) { return false; } +}; + +constexpr D d; +static_assert(static_cast(d)); +static_assert((bool)d); +static_assert(!static_cast(D{})); +static_assert(!(bool)D{}); -- cgit v1.1 From c7a9883663a888617b6e3584233aa756b30519f8 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 6 Mar 2024 10:04:56 +0000 Subject: aarch64: Define out-of-class static constants While reworking the aarch64 feature descriptions, I forgot to add out-of-class definitions of some static constants. This could lead to a build failure with some compilers. This was seen with some WIP to increase the number of extensions beyond 64. It's latent on trunk though, and a regression from before the rework. gcc/ * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add out-of-class definitions of static constants. --- gcc/config/aarch64/aarch64-feature-deps.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-feature-deps.h b/gcc/config/aarch64/aarch64-feature-deps.h index a1b81f9..3641bad 100644 --- a/gcc/config/aarch64/aarch64-feature-deps.h +++ b/gcc/config/aarch64/aarch64-feature-deps.h @@ -71,6 +71,9 @@ template struct info; static constexpr auto enable = flag | get_enable REQUIRES; \ static constexpr auto explicit_on = enable | get_enable EXPLICIT_ON; \ }; \ + const aarch64_feature_flags info::flag; \ + const aarch64_feature_flags info::enable; \ + const aarch64_feature_flags info::explicit_on; \ constexpr info IDENT () \ { \ return info (); \ -- cgit v1.1 From 7719b9be2daa55edf336d721839300e62a7abbdc Mon Sep 17 00:00:00 2001 From: Xi Ruoyao Date: Tue, 5 Mar 2024 20:46:57 +0800 Subject: LoongArch: testsuite: Rewrite {x,}vfcmp-{d,f}.c to avoid named registers Loops on named vector register are not vectorized (see comment 11 of PR113622), so the these test cases have been failing for a while. Rewrite them using check-function-bodies to remove hard coding register names. A barrier is needed to always load the first operand before the second operand. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vfcmp-f.c: Rewrite to avoid named registers. * gcc.target/loongarch/vfcmp-d.c: Likewise. * gcc.target/loongarch/xvfcmp-f.c: Likewise. * gcc.target/loongarch/xvfcmp-d.c: Likewise. --- gcc/testsuite/gcc.target/loongarch/vfcmp-d.c | 202 +++++++++++++-- gcc/testsuite/gcc.target/loongarch/vfcmp-f.c | 347 ++++++++++++++++++++------ gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c | 202 +++++++++++++-- gcc/testsuite/gcc.target/loongarch/xvfcmp-f.c | 204 +++++++++++++-- 4 files changed, 816 insertions(+), 139 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/loongarch/vfcmp-d.c b/gcc/testsuite/gcc.target/loongarch/vfcmp-d.c index 8b870ef..87e4ed1 100644 --- a/gcc/testsuite/gcc.target/loongarch/vfcmp-d.c +++ b/gcc/testsuite/gcc.target/loongarch/vfcmp-d.c @@ -1,28 +1,188 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mlsx -ffixed-f0 -ffixed-f1 -ffixed-f2 -fno-vect-cost-model" } */ +/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #define F double #define I long long #include "vfcmp-f.c" -/* { dg-final { scan-assembler "compare_quiet_equal:.*\tvfcmp\\.ceq\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_equal:.*\tvfcmp\\.cune\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_not_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater:.*\tvfcmp\\.slt\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater_equal:.*\tvfcmp\\.sle\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less:.*\tvfcmp\\.slt\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less_equal:.*\tvfcmp\\.sle\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_not_greater:.*\tvfcmp\\.sule\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_not_greater\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less_unordered:.*\tvfcmp\\.sult\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_not_less:.*\tvfcmp\\.sule\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_not_less\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater_unordered:.*\tvfcmp\\.sult\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less:.*\tvfcmp\\.clt\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less_equal:.*\tvfcmp\\.cle\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater:.*\tvfcmp\\.clt\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater_equal:.*\tvfcmp\\.cle\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_less:.*\tvfcmp\\.cule\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_not_less\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater_unordered:.*\tvfcmp\\.cult\\.d\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_greater:.*\tvfcmp\\.cule\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_not_greater\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less_unordered:.*\tvfcmp\\.cult\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_unordered:.*\tvfcmp\\.cun\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_ordered:.*\tvfcmp\\.cor\\.d\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_ordered\n" } } */ +/* +** compare_quiet_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.ceq.d (\$vr[0-9]+),(\1,\2|\2,\1) +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cune.d (\$vr[0-9]+),(\1,\2|\2,\1) +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.slt.d (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sle.d (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.slt.d (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sle.d (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_not_greater: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sule.d (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less_unordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sult.d (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_not_less: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sule.d (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater_unordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sult.d (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.clt.d (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cle.d (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.clt.d (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cle.d (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_less: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cule.d (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater_unordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cult.d (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_greater: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cule.d (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less_unordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cult.d (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_unordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cun.d (\$vr[0-9]+),(\1,\2|\2,\1) +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_ordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cor.d (\$vr[0-9]+),(\1,\2|\2,\1) +** vst \3,\$r6,0 +** jr \$r1 +*/ diff --git a/gcc/testsuite/gcc.target/loongarch/vfcmp-f.c b/gcc/testsuite/gcc.target/loongarch/vfcmp-f.c index b9110b9..8d26719 100644 --- a/gcc/testsuite/gcc.target/loongarch/vfcmp-f.c +++ b/gcc/testsuite/gcc.target/loongarch/vfcmp-f.c @@ -2,7 +2,8 @@ For details read C23 Annex F.3 and LoongArch Vol. 1 section 3.2.2.1. */ /* { dg-do compile } */ -/* { dg-options "-O2 -mlsx -ffixed-f0 -ffixed-f1 -ffixed-f2 -fno-vect-cost-model" } */ +/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #ifndef F #define F float @@ -19,160 +20,354 @@ typedef F VF __attribute__ ((vector_size (VL))); typedef I VI __attribute__ ((vector_size (VL))); -register VF a asm ("f0"); -register VF b asm ("f1"); -register VI c asm ("f2"); +#define ARGS const VF *a, const VF *b, VI *c void -compare_quiet_equal (void) +compare_quiet_equal (ARGS) { - c = (a == b); + VF _a = *a; + asm("" ::: "memory"); + *c = (_a == *b); } void -compare_quiet_not_equal (void) +compare_quiet_not_equal (ARGS) { - c = (a != b); + VF _a = *a; + asm("" ::: "memory"); + *c = (_a != *b); } void -compare_signaling_greater (void) +compare_signaling_greater (ARGS) { - c = (a > b); + VF _a = *a; + asm("" ::: "memory"); + *c = (_a > *b); } void -compare_signaling_greater_equal (void) +compare_signaling_greater_equal (ARGS) { - c = (a >= b); + VF _a = *a; + asm("" ::: "memory"); + *c = (_a >= *b); } void -compare_signaling_less (void) +compare_signaling_less (ARGS) { - c = (a < b); + VF _a = *a; + asm("" ::: "memory"); + *c = (_a < *b); } void -compare_signaling_less_equal (void) +compare_signaling_less_equal (ARGS) { - c = (a <= b); + VF _a = *a; + asm("" ::: "memory"); + *c = (_a <= *b); } void -compare_signaling_not_greater (void) +compare_signaling_not_greater (ARGS) { - c = ~(a > b); + VF _a = *a; + asm("" ::: "memory"); + *c = ~(_a > *b); } void -compare_signaling_less_unordered (void) +compare_signaling_less_unordered (ARGS) { - c = ~(a >= b); + VF _a = *a; + asm("" ::: "memory"); + *c = ~(_a >= *b); } void -compare_signaling_not_less (void) +compare_signaling_not_less (ARGS) { - c = ~(a < b); + VF _a = *a; + asm("" ::: "memory"); + *c = ~(_a < *b); } void -compare_signaling_greater_unordered (void) +compare_signaling_greater_unordered (ARGS) { - c = ~(a <= b); + VF _a = *a; + asm("" ::: "memory"); + *c = ~(_a <= *b); } void -compare_quiet_less (void) +compare_quiet_less (ARGS) { - for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) - c[i] = __builtin_isless (a[i], b[i]) ? -1 : 0; + VF _a = *a; + asm("" ::: "memory"); + for (int i = 0; i < sizeof (*c) / sizeof ((*c)[0]); i++) + (*c)[i] = __builtin_isless (_a[i], (*b)[i]) ? -1 : 0; } void -compare_quiet_less_equal (void) +compare_quiet_less_equal (ARGS) { - for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) - c[i] = __builtin_islessequal (a[i], b[i]) ? -1 : 0; + VF _a = *a; + asm("" ::: "memory"); + for (int i = 0; i < sizeof (*c) / sizeof ((*c)[0]); i++) + (*c)[i] = __builtin_islessequal (_a[i], (*b)[i]) ? -1 : 0; } void -compare_quiet_greater (void) +compare_quiet_greater (ARGS) { - for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) - c[i] = __builtin_isgreater (a[i], b[i]) ? -1 : 0; + VF _a = *a; + asm("" ::: "memory"); + for (int i = 0; i < sizeof (*c) / sizeof ((*c)[0]); i++) + (*c)[i] = __builtin_isgreater (_a[i], (*b)[i]) ? -1 : 0; } void -compare_quiet_greater_equal (void) +compare_quiet_greater_equal (ARGS) { - for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) - c[i] = __builtin_isgreaterequal (a[i], b[i]) ? -1 : 0; + VF _a = *a; + asm("" ::: "memory"); + for (int i = 0; i < sizeof (*c) / sizeof ((*c)[0]); i++) + (*c)[i] = __builtin_isgreaterequal (_a[i], (*b)[i]) ? -1 : 0; } void -compare_quiet_not_less (void) +compare_quiet_not_less (ARGS) { - for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) - c[i] = __builtin_isless (a[i], b[i]) ? 0 : -1; + VF _a = *a; + asm("" ::: "memory"); + for (int i = 0; i < sizeof (*c) / sizeof ((*c)[0]); i++) + (*c)[i] = __builtin_isless (_a[i], (*b)[i]) ? 0 : -1; } void -compare_quiet_greater_unordered (void) +compare_quiet_greater_unordered (ARGS) { - for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) - c[i] = __builtin_islessequal (a[i], b[i]) ? 0 : -1; + VF _a = *a; + asm("" ::: "memory"); + for (int i = 0; i < sizeof (*c) / sizeof ((*c)[0]); i++) + (*c)[i] = __builtin_islessequal (_a[i], (*b)[i]) ? 0 : -1; } void -compare_quiet_not_greater (void) +compare_quiet_not_greater (ARGS) { - for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) - c[i] = __builtin_isgreater (a[i], b[i]) ? 0 : -1; + VF _a = *a; + asm("" ::: "memory"); + for (int i = 0; i < sizeof (*c) / sizeof ((*c)[0]); i++) + (*c)[i] = __builtin_isgreater (_a[i], (*b)[i]) ? 0 : -1; } void -compare_quiet_less_unordered (void) +compare_quiet_less_unordered (ARGS) { - for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) - c[i] = __builtin_isgreaterequal (a[i], b[i]) ? 0 : -1; + VF _a = *a; + asm("" ::: "memory"); + for (int i = 0; i < sizeof (*c) / sizeof ((*c)[0]); i++) + (*c)[i] = __builtin_isgreaterequal (_a[i], (*b)[i]) ? 0 : -1; } void -compare_quiet_unordered (void) +compare_quiet_unordered (ARGS) { - for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) - c[i] = __builtin_isunordered (a[i], b[i]) ? -1 : 0; + VF _a = *a; + asm("" ::: "memory"); + for (int i = 0; i < sizeof (*c) / sizeof ((*c)[0]); i++) + (*c)[i] = __builtin_isunordered (_a[i], (*b)[i]) ? -1 : 0; } void -compare_quiet_ordered (void) +compare_quiet_ordered (ARGS) { - for (int i = 0; i < sizeof (c) / sizeof (c[0]); i++) - c[i] = __builtin_isunordered (a[i], b[i]) ? 0 : -1; + VF _a = *a; + asm("" ::: "memory"); + for (int i = 0; i < sizeof (*c) / sizeof ((*c)[0]); i++) + (*c)[i] = __builtin_isunordered (_a[i], (*b)[i]) ? 0 : -1; } -/* The "-" matches the .size directive after the function - body, so we can ensure the instruction is in the correct function. */ +/* +** compare_quiet_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.ceq.s (\$vr[0-9]+),(\1,\2|\2,\1) +** vst \3,\$r6,0 +** jr \$r1 +*/ -/* { dg-final { scan-assembler "compare_quiet_equal:.*\tvfcmp\\.ceq\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_equal:.*\tvfcmp\\.cune\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_not_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater:.*\tvfcmp\\.slt\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater_equal:.*\tvfcmp\\.sle\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less:.*\tvfcmp\\.slt\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less_equal:.*\tvfcmp\\.sle\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_not_greater:.*\tvfcmp\\.sule\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_not_greater\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less_unordered:.*\tvfcmp\\.sult\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_signaling_less_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_not_less:.*\tvfcmp\\.sule\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_not_less\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater_unordered:.*\tvfcmp\\.sult\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_signaling_greater_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less:.*\tvfcmp\\.clt\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less_equal:.*\tvfcmp\\.cle\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater:.*\tvfcmp\\.clt\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater_equal:.*\tvfcmp\\.cle\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_less:.*\tvfcmp\\.cule\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_not_less\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater_unordered:.*\tvfcmp\\.cult\\.s\t\\\$vr2,\\\$vr1,\\\$vr0.*-compare_quiet_greater_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_greater:.*\tvfcmp\\.cule\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_not_greater\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less_unordered:.*\tvfcmp\\.cult\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_less_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_unordered:.*\tvfcmp\\.cun\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_ordered:.*\tvfcmp\\.cor\\.s\t\\\$vr2,\\\$vr0,\\\$vr1.*-compare_quiet_ordered\n" } } */ +/* +** compare_quiet_not_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cune.s (\$vr[0-9]+),(\1,\2|\2,\1) +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.slt.s (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sle.s (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.slt.s (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sle.s (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_not_greater: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sule.s (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less_unordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sult.s (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_not_less: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sule.s (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater_unordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.sult.s (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.clt.s (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cle.s (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.clt.s (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater_equal: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cle.s (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_less: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cule.s (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater_unordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cult.s (\$vr[0-9]+),\2,\1 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_greater: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cule.s (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less_unordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cult.s (\$vr[0-9]+),\1,\2 +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_unordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cun.s (\$vr[0-9]+),(\1,\2|\2,\1) +** vst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_ordered: +** vld (\$vr[0-9]+),\$r4,0 +** vld (\$vr[0-9]+),\$r5,0 +** vfcmp.cor.s (\$vr[0-9]+),(\1,\2|\2,\1) +** vst \3,\$r6,0 +** jr \$r1 +*/ diff --git a/gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c b/gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c index d8017ca..b27efeb 100644 --- a/gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c +++ b/gcc/testsuite/gcc.target/loongarch/xvfcmp-d.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mlasx -ffixed-f0 -ffixed-f1 -ffixed-f2 -fno-vect-cost-model" } */ +/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #define F double #define I long long @@ -7,23 +8,182 @@ #include "vfcmp-f.c" -/* { dg-final { scan-assembler "compare_quiet_equal:.*\txvfcmp\\.ceq\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_equal:.*\txvfcmp\\.cune\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_not_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater:.*\txvfcmp\\.slt\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater_equal:.*\txvfcmp\\.sle\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less:.*\txvfcmp\\.slt\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less_equal:.*\txvfcmp\\.sle\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_not_greater:.*\txvfcmp\\.sule\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_not_greater\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less_unordered:.*\txvfcmp\\.sult\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_not_less:.*\txvfcmp\\.sule\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_not_less\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater_unordered:.*\txvfcmp\\.sult\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less:.*\txvfcmp\\.clt\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less_equal:.*\txvfcmp\\.cle\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater:.*\txvfcmp\\.clt\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater_equal:.*\txvfcmp\\.cle\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_less:.*\txvfcmp\\.cule\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_not_less\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater_unordered:.*\txvfcmp\\.cult\\.d\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_greater:.*\txvfcmp\\.cule\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_not_greater\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less_unordered:.*\txvfcmp\\.cult\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_unordered:.*\txvfcmp\\.cun\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_ordered:.*\txvfcmp\\.cor\\.d\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_ordered\n" } } */ +/* +** compare_quiet_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.ceq.d (\$xr[0-9]+),(\1,\2|\2,\1) +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cune.d (\$xr[0-9]+),(\1,\2|\2,\1) +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.slt.d (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sle.d (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.slt.d (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sle.d (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_not_greater: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sule.d (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less_unordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sult.d (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_not_less: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sule.d (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater_unordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sult.d (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.clt.d (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cle.d (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.clt.d (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cle.d (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_less: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cule.d (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater_unordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cult.d (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_greater: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cule.d (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less_unordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cult.d (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_unordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cun.d (\$xr[0-9]+),(\1,\2|\2,\1) +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_ordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cor.d (\$xr[0-9]+),(\1,\2|\2,\1) +** xvst \3,\$r6,0 +** jr \$r1 +*/ diff --git a/gcc/testsuite/gcc.target/loongarch/xvfcmp-f.c b/gcc/testsuite/gcc.target/loongarch/xvfcmp-f.c index b545564..1ca1e6c 100644 --- a/gcc/testsuite/gcc.target/loongarch/xvfcmp-f.c +++ b/gcc/testsuite/gcc.target/loongarch/xvfcmp-f.c @@ -1,27 +1,189 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mlasx -ffixed-f0 -ffixed-f1 -ffixed-f2" } */ +/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#define F float +#define I int #define VL 32 #include "vfcmp-f.c" -/* { dg-final { scan-assembler "compare_quiet_equal:.*\txvfcmp\\.ceq\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_equal:.*\txvfcmp\\.cune\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_not_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater:.*\txvfcmp\\.slt\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater_equal:.*\txvfcmp\\.sle\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less:.*\txvfcmp\\.slt\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less_equal:.*\txvfcmp\\.sle\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less_equal\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_not_greater:.*\txvfcmp\\.sule\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_not_greater\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_less_unordered:.*\txvfcmp\\.sult\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_signaling_less_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_not_less:.*\txvfcmp\\.sule\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_not_less\n" } } */ -/* { dg-final { scan-assembler "compare_signaling_greater_unordered:.*\txvfcmp\\.sult\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_signaling_greater_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less:.*\txvfcmp\\.clt\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less_equal:.*\txvfcmp\\.cle\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater:.*\txvfcmp\\.clt\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater_equal:.*\txvfcmp\\.cle\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater_equal\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_less:.*\txvfcmp\\.cule\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_not_less\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_greater_unordered:.*\txvfcmp\\.cult\\.s\t\\\$xr2,\\\$xr1,\\\$xr0.*-compare_quiet_greater_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_not_greater:.*\txvfcmp\\.cule\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_not_greater\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_less_unordered:.*\txvfcmp\\.cult\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_less_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_unordered:.*\txvfcmp\\.cun\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_unordered\n" } } */ -/* { dg-final { scan-assembler "compare_quiet_ordered:.*\txvfcmp\\.cor\\.s\t\\\$xr2,\\\$xr0,\\\$xr1.*-compare_quiet_ordered\n" } } */ +/* +** compare_quiet_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.ceq.s (\$xr[0-9]+),(\1,\2|\2,\1) +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cune.s (\$xr[0-9]+),(\1,\2|\2,\1) +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.slt.s (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sle.s (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.slt.s (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sle.s (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_not_greater: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sule.s (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_less_unordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sult.s (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_not_less: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sule.s (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_signaling_greater_unordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.sult.s (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.clt.s (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cle.s (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.clt.s (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater_equal: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cle.s (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_less: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cule.s (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_greater_unordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cult.s (\$xr[0-9]+),\2,\1 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_not_greater: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cule.s (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_less_unordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cult.s (\$xr[0-9]+),\1,\2 +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_unordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cun.s (\$xr[0-9]+),(\1,\2|\2,\1) +** xvst \3,\$r6,0 +** jr \$r1 +*/ + +/* +** compare_quiet_ordered: +** xvld (\$xr[0-9]+),\$r4,0 +** xvld (\$xr[0-9]+),\$r5,0 +** xvfcmp.cor.s (\$xr[0-9]+),(\1,\2|\2,\1) +** xvst \3,\$r6,0 +** jr \$r1 +*/ -- cgit v1.1 From 89c443a7e9a0780a52a698fb02d4f5173e025918 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Wed, 6 Mar 2024 10:31:02 +0100 Subject: tree-optimization/114239 - rework reduction epilogue driving The following reworks vectorizable_live_operation to pass the live stmt to vect_create_epilog_for_reduction also for early breaks and a peeled main exit. This is to be able to figure the scalar definition to replace. This reverts the PR114192 fix as it is subsumed by this cleanup. PR tree-optimization/114239 * tree-vect-loop.cc (vect_get_vect_def): Remove. (vect_create_epilog_for_reduction): The passed in stmt_info should now be the live stmt that produces the scalar reduction result. Revert PR114192 fix. Base reduction info off info_for_reduction. Remove special handling of early-break/peeled, restore original vector def gathering. Make sure to pick the correct exit PHIs. (vectorizable_live_operation): Pass in the proper stmt_info for early break exits. * gcc.dg/vect/vect-early-break_122-pr114239.c: New testcase. --- .../gcc.dg/vect/vect-early-break_122-pr114239.c | 29 ++++++ gcc/tree-vect-loop.cc | 105 +++++---------------- 2 files changed, 53 insertions(+), 81 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/vect-early-break_122-pr114239.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_122-pr114239.c b/gcc/testsuite/gcc.dg/vect/vect-early-break_122-pr114239.c new file mode 100644 index 0000000..7bf4db1 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_122-pr114239.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-add-options vect_early_break } */ +/* { dg-require-effective-target vect_early_break } */ + +int ip4_getbit_a, ip4_getbit_pos, ip4_clrbit_pos; +void ip4_clrbit(int *a) { *a &= ip4_clrbit_pos; } +typedef struct { + char pxlen; + int prefix; +} net_addr_ip4; +void fib_get_chain(); +int trie_match_longest_ip4(); +int trie_match_next_longest_ip4(net_addr_ip4 *n) { + int __trans_tmp_1; + while (n->pxlen) { + n->pxlen--; + ip4_clrbit(&n->prefix); + __trans_tmp_1 = ip4_getbit_a >> ip4_getbit_pos; + if (__trans_tmp_1) + return 1; + } + return 0; +} +void net_roa_check_ip4_trie_tab() { + net_addr_ip4 px0; + for (int _n = trie_match_longest_ip4(&px0); _n; + _n = trie_match_next_longest_ip4(&px0)) + fib_get_chain(); +} diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc index 761cdc6..20ee0aa 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -5897,35 +5897,6 @@ vect_create_partial_epilog (tree vec_def, tree vectype, code_helper code, return new_temp; } -/* Retrieves the definining statement to be used for a reduction. - For LAST_VAL_REDUC_P we use the current VEC_STMTs which correspond to the - final value after vectorization and otherwise we look at the reduction - definitions to get the first. */ - -tree -vect_get_vect_def (stmt_vec_info reduc_info, slp_tree slp_node, - slp_instance slp_node_instance, bool last_val_reduc_p, - unsigned i, vec &vec_stmts) -{ - tree def; - - if (slp_node) - { - if (!last_val_reduc_p) - slp_node = slp_node_instance->reduc_phis; - def = vect_get_slp_vect_def (slp_node, i); - } - else - { - if (!last_val_reduc_p) - reduc_info = STMT_VINFO_REDUC_DEF (vect_orig_stmt (reduc_info)); - vec_stmts = STMT_VINFO_VEC_STMTS (reduc_info); - def = gimple_get_lhs (vec_stmts[0]); - } - - return def; -} - /* Function vect_create_epilog_for_reduction Create code at the loop-epilog to finalize the result of a reduction @@ -5989,8 +5960,6 @@ vect_create_epilog_for_reduction (loop_vec_info loop_vinfo, loop-closed PHI of the inner loop which we remember as def for the reduction PHI generation. */ bool double_reduc = false; - bool last_val_reduc_p = LOOP_VINFO_IV_EXIT (loop_vinfo) == loop_exit - && !LOOP_VINFO_EARLY_BREAKS_VECT_PEELED (loop_vinfo); stmt_vec_info rdef_info = stmt_info; if (STMT_VINFO_DEF_TYPE (stmt_info) == vect_double_reduction_def) { @@ -6000,8 +5969,6 @@ vect_create_epilog_for_reduction (loop_vec_info loop_vinfo, (stmt_info->stmt, 0)); stmt_info = vect_stmt_to_vectorize (stmt_info); } - gphi *reduc_def_stmt - = as_a (STMT_VINFO_REDUC_DEF (vect_orig_stmt (stmt_info))->stmt); code_helper code = STMT_VINFO_REDUC_CODE (reduc_info); internal_fn reduc_fn = STMT_VINFO_REDUC_FN (reduc_info); tree vectype; @@ -6066,33 +6033,9 @@ vect_create_epilog_for_reduction (loop_vec_info loop_vinfo, stmt_vec_info single_live_out_stmt[] = { stmt_info }; array_slice live_out_stmts = single_live_out_stmt; - if (LOOP_VINFO_EARLY_BREAKS (loop_vinfo) - && loop_exit != LOOP_VINFO_IV_EXIT (loop_vinfo) - /* ??? We should fend this off earlier. For conversions we create - multiple epilogues, one dead. */ - && stmt_info == reduc_info->reduc_def) - { - gcc_assert (!slp_node); - single_live_out_stmt[0] = reduc_info; - } - else - { - if (slp_reduc) - /* All statements produce live-out values. */ - live_out_stmts = SLP_TREE_SCALAR_STMTS (slp_node); - else if (slp_node) - { - /* The last statement in the reduction chain produces the live-out - value. Note SLP optimization can shuffle scalar stmts to - optimize permutations so we have to search for the last stmt. */ - for (k = 0; k < group_size; ++k) - if (!REDUC_GROUP_NEXT_ELEMENT (SLP_TREE_SCALAR_STMTS (slp_node)[k])) - { - single_live_out_stmt[0] = SLP_TREE_SCALAR_STMTS (slp_node)[k]; - break; - } - } - } + if (slp_reduc) + /* All statements produce live-out values. */ + live_out_stmts = SLP_TREE_SCALAR_STMTS (slp_node); unsigned vec_num; int ncopies; @@ -6103,7 +6046,6 @@ vect_create_epilog_for_reduction (loop_vec_info loop_vinfo, } else { - stmt_vec_info reduc_info = loop_vinfo->lookup_stmt (reduc_def_stmt); vec_num = 1; ncopies = STMT_VINFO_VEC_STMTS (reduc_info).length (); } @@ -6247,18 +6189,19 @@ vect_create_epilog_for_reduction (loop_vec_info loop_vinfo, exit_bb = loop_exit->dest; exit_gsi = gsi_after_labels (exit_bb); reduc_inputs.create (slp_node ? vec_num : ncopies); - vec vec_stmts = vNULL; for (unsigned i = 0; i < vec_num; i++) { gimple_seq stmts = NULL; - def = vect_get_vect_def (rdef_info, slp_node, slp_node_instance, - last_val_reduc_p, i, vec_stmts); + if (slp_node) + def = vect_get_slp_vect_def (slp_node, i); + else + def = gimple_get_lhs (STMT_VINFO_VEC_STMTS (rdef_info)[0]); for (j = 0; j < ncopies; j++) { tree new_def = copy_ssa_name (def); phi = create_phi_node (new_def, exit_bb); if (j) - def = gimple_get_lhs (vec_stmts[j]); + def = gimple_get_lhs (STMT_VINFO_VEC_STMTS (rdef_info)[j]); if (LOOP_VINFO_IV_EXIT (loop_vinfo) == loop_exit) SET_PHI_ARG_DEF (phi, loop_exit->dest_idx, def); else @@ -6963,7 +6906,8 @@ vect_create_epilog_for_reduction (loop_vec_info loop_vinfo, { if (!flow_bb_inside_loop_p (loop, gimple_bb (USE_STMT (use_p)))) { - if (!is_gimple_debug (USE_STMT (use_p))) + if (!is_gimple_debug (USE_STMT (use_p)) + && gimple_bb (USE_STMT (use_p)) == loop_exit->dest) phis.safe_push (USE_STMT (use_p)); } else @@ -10765,26 +10709,21 @@ vectorizable_live_operation (vec_info *vinfo, stmt_vec_info stmt_info, { if (!vec_stmt_p) return true; - if (slp_node) - { - /* For reduction chains the meta-info is attached to - the group leader. */ - if (REDUC_GROUP_FIRST_ELEMENT (stmt_info)) - stmt_info = REDUC_GROUP_FIRST_ELEMENT (stmt_info); - /* For SLP reductions we vectorize the epilogue for - all involved stmts together. */ - else if (slp_index != 0) - return true; - } + /* For SLP reductions we vectorize the epilogue for all involved stmts + together. */ + if (slp_node && !REDUC_GROUP_FIRST_ELEMENT (stmt_info) && slp_index != 0) + return true; stmt_vec_info reduc_info = info_for_reduction (loop_vinfo, stmt_info); gcc_assert (reduc_info->is_reduc_info); if (STMT_VINFO_REDUC_TYPE (reduc_info) == FOLD_LEFT_REDUCTION || STMT_VINFO_REDUC_TYPE (reduc_info) == EXTRACT_LAST_REDUCTION) return true; - vect_create_epilog_for_reduction (loop_vinfo, stmt_info, slp_node, - slp_node_instance, - LOOP_VINFO_IV_EXIT (loop_vinfo)); + if (!LOOP_VINFO_EARLY_BREAKS (loop_vinfo) + || !LOOP_VINFO_EARLY_BREAKS_VECT_PEELED (loop_vinfo)) + vect_create_epilog_for_reduction (loop_vinfo, stmt_info, slp_node, + slp_node_instance, + LOOP_VINFO_IV_EXIT (loop_vinfo)); /* If early break we only have to materialize the reduction on the merge block, but we have to find an alternate exit first. */ @@ -10793,11 +10732,15 @@ vectorizable_live_operation (vec_info *vinfo, stmt_vec_info stmt_info, for (auto exit : get_loop_exit_edges (LOOP_VINFO_LOOP (loop_vinfo))) if (exit != LOOP_VINFO_IV_EXIT (loop_vinfo)) { - vect_create_epilog_for_reduction (loop_vinfo, stmt_info, + vect_create_epilog_for_reduction (loop_vinfo, reduc_info, slp_node, slp_node_instance, exit); break; } + if (LOOP_VINFO_EARLY_BREAKS_VECT_PEELED (loop_vinfo)) + vect_create_epilog_for_reduction (loop_vinfo, reduc_info, slp_node, + slp_node_instance, + LOOP_VINFO_IV_EXIT (loop_vinfo)); } return true; -- cgit v1.1 From b7d14310406a13aaf518c6c34728433077cd545a Mon Sep 17 00:00:00 2001 From: Georg-Johann Lay Date: Wed, 6 Mar 2024 12:46:25 +0100 Subject: AVR: Adjust rtx cost of plus + zero_extend. gcc/ * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust rtx cost. --- gcc/config/avr/avr.cc | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'gcc') diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index 36995e0..b87ae6a 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -12513,6 +12513,13 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code, return true; case PLUS: + if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND + && REG_P (XEXP (x, 1))) + { + *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) - 1); + return true; + } + switch (mode) { case E_QImode: -- cgit v1.1 From 71aad5231447484046b45e6c8381f8096d3c287d Mon Sep 17 00:00:00 2001 From: Thomas Schwinge Date: Mon, 4 Mar 2024 10:40:39 +0100 Subject: amdgcn: additional gfx1030/gfx1100 support: adjust test cases The "SDWA" changes in commit 99890e15527f1f04caef95ecdd135c9f1a077f08 "amdgcn: additional gfx1030/gfx1100 support" caused a few regressions: PASS: gcc.target/gcn/sram-ecc-3.c (test for excess errors) [-PASS:-]{+FAIL:+} gcc.target/gcn/sram-ecc-3.c scan-assembler zero_extendv64qiv64si2 PASS: gcc.target/gcn/sram-ecc-4.c (test for excess errors) [-PASS:-]{+FAIL:+} gcc.target/gcn/sram-ecc-4.c scan-assembler zero_extendv64hiv64si2 PASS: gcc.target/gcn/sram-ecc-7.c (test for excess errors) [-PASS:-]{+FAIL:+} gcc.target/gcn/sram-ecc-7.c scan-assembler zero_extendv64qiv64si2 PASS: gcc.target/gcn/sram-ecc-8.c (test for excess errors) [-PASS:-]{+FAIL:+} gcc.target/gcn/sram-ecc-8.c scan-assembler zero_extendv64hiv64si2 Those test cases need corresponding adjustment. gcc/testsuite/ * gcc.target/gcn/sram-ecc-3.c: Adjust. * gcc.target/gcn/sram-ecc-4.c: Likewise. * gcc.target/gcn/sram-ecc-7.c: Likewise. * gcc.target/gcn/sram-ecc-8.c: Likewise. --- gcc/testsuite/gcc.target/gcn/sram-ecc-3.c | 2 +- gcc/testsuite/gcc.target/gcn/sram-ecc-4.c | 2 +- gcc/testsuite/gcc.target/gcn/sram-ecc-7.c | 2 +- gcc/testsuite/gcc.target/gcn/sram-ecc-8.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c index 692d457..bc89e35 100644 --- a/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c +++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c @@ -18,4 +18,4 @@ f () a[n] = b[n]; } -/* { dg-final { scan-assembler "zero_extendv64qiv64si2" } } */ +/* { dg-final { scan-assembler "(\\\*zero_extendv64qiv64si_sdwa|\\\*zero_extendv64qiv64si_shift)" } } */ diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c index 61b8d55..ff7e2d0 100644 --- a/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c +++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c @@ -18,4 +18,4 @@ f () a[n] = b[n]; } -/* { dg-final { scan-assembler "zero_extendv64hiv64si2" } } */ +/* { dg-final { scan-assembler "(\\\*zero_extendv64hiv64si_sdwa|\\\*zero_extendv64hiv64si_shift)" } } */ diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c index 9d0ce6f..8d36397 100644 --- a/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c +++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c @@ -18,4 +18,4 @@ f () a[n] = b[n]; } -/* { dg-final { scan-assembler "zero_extendv64qiv64si2" } } */ +/* { dg-final { scan-assembler "(\\\*zero_extendv64qiv64si_sdwa|\\\*zero_extendv64qiv64si_shift)" } } */ diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c index 76e0288..a2b2507 100644 --- a/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c +++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c @@ -18,4 +18,4 @@ f () a[n] = b[n]; } -/* { dg-final { scan-assembler "zero_extendv64hiv64si2" } } */ +/* { dg-final { scan-assembler "(\\\*zero_extendv64hiv64si_sdwa|\\\*zero_extendv64hiv64si_shift)" } } */ -- cgit v1.1 From e772c0c05c36d0b0539effb4256be67bbedd77fb Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Wed, 6 Mar 2024 17:08:25 +0100 Subject: i386: Eliminate common code from x86_32 TARGET_MACHO part in ix86_expand_move Eliminate common code from x86_32 TARGET_MACHO part in ix86_expand_move and use generic code instead. No functional changes. gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]: Eliminate common code and use generic code instead. --- gcc/config/i386/i386-expand.cc | 37 +++++++++++-------------------------- 1 file changed, 11 insertions(+), 26 deletions(-) (limited to 'gcc') diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 3b1685a..2210e6f 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -471,9 +471,9 @@ ix86_expand_move (machine_mode mode, rtx operands[]) if ((flag_pic || MACHOPIC_INDIRECT) && symbolic_operand (op1, mode)) { +#if TARGET_MACHO if (TARGET_MACHO && !TARGET_64BIT) { -#if TARGET_MACHO /* dynamic-no-pic */ if (MACHOPIC_INDIRECT) { @@ -490,33 +490,18 @@ ix86_expand_move (machine_mode mode, rtx operands[]) emit_insn (insn); return; } - if (GET_CODE (op0) == MEM) - op1 = force_reg (Pmode, op1); - else - { - rtx temp = op0; - if (GET_CODE (temp) != REG) - temp = gen_reg_rtx (Pmode); - temp = legitimize_pic_address (op1, temp); - if (temp == op0) - return; - op1 = temp; - } - /* dynamic-no-pic */ -#endif } - else +#endif + + if (MEM_P (op0)) + op1 = force_reg (mode, op1); + else if (!(TARGET_64BIT && x86_64_movabs_operand (op1, DImode))) { - if (MEM_P (op0)) - op1 = force_reg (mode, op1); - else if (!(TARGET_64BIT && x86_64_movabs_operand (op1, DImode))) - { - rtx reg = can_create_pseudo_p () ? NULL_RTX : op0; - op1 = legitimize_pic_address (op1, reg); - if (op0 == op1) - return; - op1 = convert_to_mode (mode, op1, 1); - } + rtx reg = can_create_pseudo_p () ? NULL_RTX : op0; + op1 = legitimize_pic_address (op1, reg); + if (op0 == op1) + return; + op1 = convert_to_mode (mode, op1, 1); } } else -- cgit v1.1 From dc6c3bfb59baab28b998e18396c06087b6d9b0ed Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Tue, 5 Mar 2024 13:33:10 -0500 Subject: c++: ICE with noexcept and local specialization [PR114114] Here we ICE because we call register_local_specialization while local_specializations is null, so local_specializations->put (); crashes on null this. It's null since maybe_instantiate_noexcept calls push_to_top_level which creates a new scope. Normally, I would have guessed that we need a new local_specialization_stack. But here we're dealing with an operand of a noexcept, which is an unevaluated operand, and those aren't registered in the hash map. maybe_instantiate_noexcept wasn't signalling that it's substituting an unevaluated operand though. PR c++/114114 gcc/cp/ChangeLog: * pt.cc (maybe_instantiate_noexcept): Save/restore cp_unevaluated_operand, c_inhibit_evaluation_warnings, and cp_noexcept_operand around the tsubst_expr call. gcc/testsuite/ChangeLog: * g++.dg/cpp0x/noexcept84.C: New test. --- gcc/cp/pt.cc | 6 ++++++ gcc/testsuite/g++.dg/cpp0x/noexcept84.C | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 gcc/testsuite/g++.dg/cpp0x/noexcept84.C (limited to 'gcc') diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc index a6e6c80..d73f6d9 100644 --- a/gcc/cp/pt.cc +++ b/gcc/cp/pt.cc @@ -26879,10 +26879,16 @@ maybe_instantiate_noexcept (tree fn, tsubst_flags_t complain) if (orig_fn) ++processing_template_decl; + ++cp_unevaluated_operand; + ++c_inhibit_evaluation_warnings; + ++cp_noexcept_operand; /* Do deferred instantiation of the noexcept-specifier. */ noex = tsubst_expr (DEFERRED_NOEXCEPT_PATTERN (noex), DEFERRED_NOEXCEPT_ARGS (noex), tf_warning_or_error, fn); + --cp_unevaluated_operand; + --c_inhibit_evaluation_warnings; + --cp_noexcept_operand; /* Build up the noexcept-specification. */ spec = build_noexcept_spec (noex, tf_warning_or_error); diff --git a/gcc/testsuite/g++.dg/cpp0x/noexcept84.C b/gcc/testsuite/g++.dg/cpp0x/noexcept84.C new file mode 100644 index 0000000..06f3326 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/noexcept84.C @@ -0,0 +1,32 @@ +// PR c++/114114 +// { dg-do compile { target c++11 } } + +template +constexpr void +test () +{ + constexpr bool is_yes = B; + struct S { + constexpr S() noexcept(is_yes) { } + }; + S s; +} + +constexpr bool foo() { return true; } + +template +constexpr void +test2 () +{ + constexpr T (*pfn)() = &foo; + struct S { + constexpr S() noexcept(pfn()) { } + }; + S s; +} + +int main() +{ + test(); + test2(); +} -- cgit v1.1 From 93e1d4d24ed014387da97e2ce11556d68fe98e66 Mon Sep 17 00:00:00 2001 From: Harald Anlauf Date: Tue, 5 Mar 2024 21:54:26 +0100 Subject: Fortran: error recovery while simplifying expressions [PR103707,PR106987] When an exception is encountered during simplification of arithmetic expressions, the result may depend on whether range-checking is active (-frange-check) or not. However, the code path in the front-end should stay the same for "soft" errors for which the exception is triggered by the check, while "hard" errors should always terminate the simplification, so that error recovery is independent of the flag. Separation of arithmetic error codes into "hard" and "soft" errors shall be done consistently via is_hard_arith_error(). PR fortran/103707 PR fortran/106987 gcc/fortran/ChangeLog: * arith.cc (is_hard_arith_error): New helper function to determine whether an arithmetic error is "hard" or not. (check_result): Use it. (gfc_arith_divide): Set "Division by zero" only for regular numerators of real and complex divisions. (reduce_unary): Use is_hard_arith_error to determine whether a hard or (recoverable) soft error was encountered. Terminate immediately on hard error, otherwise remember code of first soft error. (reduce_binary_ac): Likewise. (reduce_binary_ca): Likewise. (reduce_binary_aa): Likewise. gcc/testsuite/ChangeLog: * gfortran.dg/pr99350.f90: * gfortran.dg/arithmetic_overflow_3.f90: New test. --- gcc/fortran/arith.cc | 134 +++++++++++++++------ .../gfortran.dg/arithmetic_overflow_3.f90 | 48 ++++++++ gcc/testsuite/gfortran.dg/pr99350.f90 | 2 +- 3 files changed, 143 insertions(+), 41 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/arithmetic_overflow_3.f90 (limited to 'gcc') diff --git a/gcc/fortran/arith.cc b/gcc/fortran/arith.cc index d17d1aa..b373c25 100644 --- a/gcc/fortran/arith.cc +++ b/gcc/fortran/arith.cc @@ -130,6 +130,30 @@ gfc_arith_error (arith code) } +/* Check if a certain arithmetic error code is severe enough to prevent + further simplification, as opposed to errors thrown by the range check + (e.g. overflow) or arithmetic exceptions that are tolerated with + -fno-range-check. */ + +static bool +is_hard_arith_error (arith code) +{ + switch (code) + { + case ARITH_OK: + case ARITH_OVERFLOW: + case ARITH_UNDERFLOW: + case ARITH_NAN: + case ARITH_DIV0: + case ARITH_ASYMMETRIC: + return false; + + default: + return true; + } +} + + /* Get things ready to do math. */ void @@ -579,10 +603,10 @@ check_result (arith rc, gfc_expr *x, gfc_expr *r, gfc_expr **rp) val = ARITH_OK; } - if (val == ARITH_OK || val == ARITH_OVERFLOW) - *rp = r; - else + if (is_hard_arith_error (val)) gfc_free_expr (r); + else + *rp = r; return val; } @@ -792,23 +816,26 @@ gfc_arith_divide (gfc_expr *op1, gfc_expr *op2, gfc_expr **resultp) break; case BT_REAL: - if (mpfr_sgn (op2->value.real) == 0 && flag_range_check == 1) - { - rc = ARITH_DIV0; - break; - } + /* Set "Division by zero" only for regular numerator. */ + if (flag_range_check == 1 + && mpfr_zero_p (op2->value.real) + && mpfr_regular_p (op1->value.real)) + rc = ARITH_DIV0; mpfr_div (result->value.real, op1->value.real, op2->value.real, GFC_RND_MODE); break; case BT_COMPLEX: - if (mpc_cmp_si_si (op2->value.complex, 0, 0) == 0 - && flag_range_check == 1) - { - rc = ARITH_DIV0; - break; - } + /* Set "Division by zero" only for regular numerator. */ + if (flag_range_check == 1 + && mpfr_zero_p (mpc_realref (op2->value.complex)) + && mpfr_zero_p (mpc_imagref (op2->value.complex)) + && ((mpfr_regular_p (mpc_realref (op1->value.complex)) + && mpfr_number_p (mpc_imagref (op1->value.complex))) + || (mpfr_regular_p (mpc_imagref (op1->value.complex)) + && mpfr_number_p (mpc_realref (op1->value.complex))))) + rc = ARITH_DIV0; gfc_set_model (mpc_realref (op1->value.complex)); if (mpc_cmp_si_si (op2->value.complex, 0, 0) == 0) @@ -1323,7 +1350,6 @@ reduce_unary (arith (*eval) (gfc_expr *, gfc_expr **), gfc_expr *op, gfc_constructor *c; gfc_expr *r; arith rc; - bool ov = false; if (op->expr_type == EXPR_CONSTANT) return eval (op, result); @@ -1335,19 +1361,22 @@ reduce_unary (arith (*eval) (gfc_expr *, gfc_expr **), gfc_expr *op, head = gfc_constructor_copy (op->value.constructor); for (c = gfc_constructor_first (head); c; c = gfc_constructor_next (c)) { - rc = reduce_unary (eval, c->expr, &r); + arith rc_tmp = reduce_unary (eval, c->expr, &r); - /* Remember any overflow encountered during reduction and continue, - but terminate on serious errors. */ - if (rc == ARITH_OVERFLOW) - ov = true; - else if (rc != ARITH_OK) - break; + /* Remember first recoverable ("soft") error encountered during + reduction and continue, but terminate on serious errors. */ + if (is_hard_arith_error (rc_tmp)) + { + rc = rc_tmp; + break; + } + else if (rc_tmp != ARITH_OK && rc == ARITH_OK) + rc = rc_tmp; gfc_replace_expr (c->expr, r); } - if (rc != ARITH_OK && rc != ARITH_OVERFLOW) + if (is_hard_arith_error (rc)) gfc_constructor_free (head); else { @@ -1368,7 +1397,7 @@ reduce_unary (arith (*eval) (gfc_expr *, gfc_expr **), gfc_expr *op, *result = r; } - return ov ? ARITH_OVERFLOW : rc; + return rc; } @@ -1384,22 +1413,31 @@ reduce_binary_ac (arith (*eval) (gfc_expr *, gfc_expr *, gfc_expr **), head = gfc_constructor_copy (op1->value.constructor); for (c = gfc_constructor_first (head); c; c = gfc_constructor_next (c)) { + arith rc_tmp; + gfc_simplify_expr (c->expr, 0); if (c->expr->expr_type == EXPR_CONSTANT) - rc = eval (c->expr, op2, &r); + rc_tmp = eval (c->expr, op2, &r); else if (c->expr->expr_type != EXPR_ARRAY) - rc = ARITH_NOT_REDUCED; + rc_tmp = ARITH_NOT_REDUCED; else - rc = reduce_binary_ac (eval, c->expr, op2, &r); + rc_tmp = reduce_binary_ac (eval, c->expr, op2, &r); - if (rc != ARITH_OK) - break; + /* Remember first recoverable ("soft") error encountered during + reduction and continue, but terminate on serious errors. */ + if (is_hard_arith_error (rc_tmp)) + { + rc = rc_tmp; + break; + } + else if (rc_tmp != ARITH_OK && rc == ARITH_OK) + rc = rc_tmp; gfc_replace_expr (c->expr, r); } - if (rc != ARITH_OK) + if (is_hard_arith_error (rc)) gfc_constructor_free (head); else { @@ -1438,22 +1476,31 @@ reduce_binary_ca (arith (*eval) (gfc_expr *, gfc_expr *, gfc_expr **), head = gfc_constructor_copy (op2->value.constructor); for (c = gfc_constructor_first (head); c; c = gfc_constructor_next (c)) { + arith rc_tmp; + gfc_simplify_expr (c->expr, 0); if (c->expr->expr_type == EXPR_CONSTANT) - rc = eval (op1, c->expr, &r); + rc_tmp = eval (op1, c->expr, &r); else if (c->expr->expr_type != EXPR_ARRAY) - rc = ARITH_NOT_REDUCED; + rc_tmp = ARITH_NOT_REDUCED; else - rc = reduce_binary_ca (eval, op1, c->expr, &r); + rc_tmp = reduce_binary_ca (eval, op1, c->expr, &r); - if (rc != ARITH_OK) - break; + /* Remember first recoverable ("soft") error encountered during + reduction and continue, but terminate on serious errors. */ + if (is_hard_arith_error (rc_tmp)) + { + rc = rc_tmp; + break; + } + else if (rc_tmp != ARITH_OK && rc == ARITH_OK) + rc = rc_tmp; gfc_replace_expr (c->expr, r); } - if (rc != ARITH_OK) + if (is_hard_arith_error (rc)) gfc_constructor_free (head); else { @@ -1503,10 +1550,17 @@ reduce_binary_aa (arith (*eval) (gfc_expr *, gfc_expr *, gfc_expr **), c && d; c = gfc_constructor_next (c), d = gfc_constructor_next (d)) { - rc = reduce_binary (eval, c->expr, d->expr, &r); + arith rc_tmp = reduce_binary (eval, c->expr, d->expr, &r); - if (rc != ARITH_OK) - break; + /* Remember first recoverable ("soft") error encountered during + reduction and continue, but terminate on serious errors. */ + if (is_hard_arith_error (rc_tmp)) + { + rc = rc_tmp; + break; + } + else if (rc_tmp != ARITH_OK && rc == ARITH_OK) + rc = rc_tmp; gfc_replace_expr (c->expr, r); } @@ -1514,7 +1568,7 @@ reduce_binary_aa (arith (*eval) (gfc_expr *, gfc_expr *, gfc_expr **), if (rc == ARITH_OK && (c || d)) rc = ARITH_INCOMMENSURATE; - if (rc != ARITH_OK) + if (is_hard_arith_error (rc)) gfc_constructor_free (head); else { diff --git a/gcc/testsuite/gfortran.dg/arithmetic_overflow_3.f90 b/gcc/testsuite/gfortran.dg/arithmetic_overflow_3.f90 new file mode 100644 index 0000000..4dc5527 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/arithmetic_overflow_3.f90 @@ -0,0 +1,48 @@ +! { dg-do compile } +! { dg-additional-options "-frange-check" } +! +! PR fortran/103707 +! PR fortran/106987 +! +! Check error recovery on arithmetic exceptions + +program p + implicit none + integer, parameter :: a(3) = [30,31,32] + integer, parameter :: e(1) = 2 + print *, 2 ** a ! { dg-error "Arithmetic overflow" } + print *, e ** 31 ! { dg-error "Arithmetic overflow" } +end + +! { dg-prune-output "Result of exponentiation" } + +subroutine s + implicit none + real, parameter :: inf = real (z'7F800000') + real, parameter :: nan = real (z'7FC00000') + + ! Unary operators + print *, -[inf,nan] ! { dg-error "Arithmetic overflow" } + print *, -[nan,inf] ! { dg-error "Arithmetic NaN" } + + ! Binary operators + print *, [1.]/[0.] ! { dg-error "Division by zero" } + print *, [0.]/[0.] ! { dg-error "Arithmetic NaN" } + print *, 0. / [(0.,0.)] ! { dg-error "Arithmetic NaN" } + print *, [1.,0.]/[0.,0.] ! { dg-error "Division by zero" } + print *, [(1.,1.)]/[0.] ! { dg-error "Division by zero" } + print *, [(1.,0.)]/[0.] ! { dg-error "Division by zero" } + print *, [(0.,0.)]/[0.] ! { dg-error "Arithmetic NaN" } + print *, - [1./0.]/[0.] ! { dg-error "Division by zero" } + print *, - [ 1/0 ] * 1 ! { dg-error "Division by zero" } + + ! Binary operators, exceptional input + print *, 1. / nan ! { dg-error "Arithmetic NaN" } + print *, [inf] / inf ! { dg-error "Arithmetic NaN" } + print *, inf + [nan] ! { dg-error "Arithmetic NaN" } + print *, [(1.,0.)]/[(nan,0.)] ! { dg-error "Arithmetic NaN" } + print *, [(1.,0.)]/[(0.,nan)] ! { dg-error "Arithmetic NaN" } + print *, [(1.,0.)]/[(inf,0.)] ! OK + print *, [nan,inf] / (0.) ! { dg-error "Arithmetic NaN" } + print *, [inf,nan] / (0.) ! { dg-error "Arithmetic overflow" } +end diff --git a/gcc/testsuite/gfortran.dg/pr99350.f90 b/gcc/testsuite/gfortran.dg/pr99350.f90 index 7f751b9..ec19881 100644 --- a/gcc/testsuite/gfortran.dg/pr99350.f90 +++ b/gcc/testsuite/gfortran.dg/pr99350.f90 @@ -7,7 +7,7 @@ program p character(:), pointer :: a end type type(t) :: z - character((0.)/0), target :: c = 'abc' ! { dg-error "Division by zero" } + character((0.)/0), target :: c = 'abc' ! { dg-error "Arithmetic NaN" } z%a => c ! The associate statement was not needed to trigger the ICE. associate (y => z%a) -- cgit v1.1 From 10cbfcd60f9e5bdbe486e1c0192e0f168d899b77 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Wed, 6 Mar 2024 09:50:44 -0700 Subject: [PR target/113001] Fix incorrect operand swapping in conditional move This bug totally fell off my radar. Sorry about that. We have some special casing the conditional move expander to simplify a conditional move when comparing a register against zero and that same register is one of the arms. Specifically a (eq (reg) (const_int 0)) where reg is also the true arm or (ne (reg) (const_int 0)) where reg is the false arm need not use the fully generalized conditional move, thus saving an instruction for those cases. In the NE case we swapped the operands, but didn't swap the condition, which led to the ICE due to an unrecognized pattern. THe backend actually has distinct patterns for those two cases. So swapping the operands is neither needed nor advisable. Regression tested on rv64gc and verified the new tests pass. Pushing to the trunk. PR target/113001 PR target/112871 gcc/ * config/riscv/riscv.cc (expand_conditional_move): Do not swap operands when the comparison operand is the same as the false arm for a NE test. gcc/testsuite * gcc.target/riscv/zicond-ice-3.c: New test. * gcc.target/riscv/zicond-ice-4.c: New test. --- gcc/config/riscv/riscv.cc | 2 -- gcc/testsuite/gcc.target/riscv/zicond-ice-3.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/riscv/zicond-ice-4.c | 22 ++++++++++++++++++++++ 3 files changed, 37 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-4.c (limited to 'gcc') diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 691d967..680c4a7 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4633,8 +4633,6 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) || (code == NE && rtx_equal_p (alt, op0))) { rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); - if (!rtx_equal_p (cons, op0)) - std::swap (alt, cons); alt = force_reg (mode, alt); emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond, diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-3.c b/gcc/testsuite/gcc.target/riscv/zicond-ice-3.c new file mode 100644 index 0000000..6509868 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d" { target { rv32 } } } */ + +long a, b; +int c, d; +void e(long *f) { + (b = *f) && --b; + for (; c;) + ; +} +void g() { + for (; d; d--) + e(&a); +} diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-4.c b/gcc/testsuite/gcc.target/riscv/zicond-ice-4.c new file mode 100644 index 0000000..2be02c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-4.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d" { target { rv32 } } } */ + +short a, c; +int b, d, i; +volatile char e; +static int f[] = {1, 1}; +long g; +int volatile h; +short(j)() { return b ? a : 0; } +void k() { +l: + h; + g = 0; + for (; g <= 2; g++) { + d | ((i || j() & (0 == f[g])) ^ i) && e; + if (c) + goto l; + } +} + -- cgit v1.1 From b575f37a342cebb954aa85fa45df0604bfa1ada9 Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Wed, 6 Mar 2024 17:35:16 +0000 Subject: ARM: Fix conditional execution [PR113915] By default most patterns can be conditionalized on Arm targets. However Thumb-2 predication requires the "predicable" attribute be explicitly set to "yes". Most patterns are shared between Arm and Thumb(-2) and are marked with "predicable". Given this sharing, it does not make sense to use a different default for Arm. So only consider conditional execution of instructions that have the predicable attribute set to yes. This ensures that patterns not explicitly marked as such are never conditionally executed. gcc/ChangeLog: PR target/113915 * config/arm/arm.md (NOCOND): Improve comment. (arm_rev*) Add predicable. * config/arm/arm.cc (arm_final_prescan_insn): Add check for PREDICABLE_YES. gcc/testsuite/ChangeLog: PR target/113915 * gcc.target/arm/builtin-bswap-1.c: Fix test to allow conditional execution both for Arm and Thumb-2. --- gcc/config/arm/arm.cc | 5 +++-- gcc/config/arm/arm.md | 6 ++++++ gcc/testsuite/gcc.target/arm/builtin-bswap-1.c | 15 ++++++--------- 3 files changed, 15 insertions(+), 11 deletions(-) (limited to 'gcc') diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 1cd6926..6a35fe4 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -25613,11 +25613,12 @@ arm_final_prescan_insn (rtx_insn *insn) break; case INSN: - /* Instructions using or affecting the condition codes make it - fail. */ + /* Check the instruction is explicitly marked as predicable. + Instructions using or affecting the condition codes are not. */ scanbody = PATTERN (this_insn); if (!(GET_CODE (scanbody) == SET || GET_CODE (scanbody) == PARALLEL) + || get_attr_predicable (this_insn) != PREDICABLE_YES || get_attr_conds (this_insn) != CONDS_NOCOND) fail = TRUE; break; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 814e871..1fd0014 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -319,6 +319,8 @@ ; ; NOCOND means that the instruction does not use or alter the condition ; codes but can be converted into a conditionally exectuted instruction. +; Given that NOCOND is the default for most instructions if omitted, +; the attribute predicable must be set to yes as well. (define_attr "conds" "use,set,clob,unconditional,nocond" (if_then_else @@ -12559,6 +12561,7 @@ revsh%?\t%0, %1" [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") + (set_attr "predicable" "no,yes,yes") (set_attr "type" "rev")] ) @@ -12572,6 +12575,7 @@ rev16%?\t%0, %1" [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") + (set_attr "predicable" "no,yes,yes") (set_attr "type" "rev")] ) @@ -12596,6 +12600,7 @@ rev16%?\t%0, %1" [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") + (set_attr "predicable" "no,yes,yes") (set_attr "type" "rev")] ) @@ -12616,6 +12621,7 @@ rev16%?\t%0, %1" [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") + (set_attr "predicable" "no,yes,yes") (set_attr "type" "rev")] ) diff --git a/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c b/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c index c1e7740..1a311a6 100644 --- a/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c +++ b/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c @@ -5,14 +5,11 @@ of the instructions. Add an -mtune option known to facilitate that. */ /* { dg-additional-options "-O2 -mtune=cortex-a53" } */ /* { dg-final { scan-assembler-not "orr\[ \t\]" } } */ -/* { dg-final { scan-assembler-times "revsh\\t" 1 { target { arm_nothumb } } } } */ -/* { dg-final { scan-assembler-times "revshne\\t" 1 { target { arm_nothumb } } } } */ -/* { dg-final { scan-assembler-times "revsh\\t" 2 { target { ! arm_nothumb } } } } */ -/* { dg-final { scan-assembler-times "rev16\\t" 1 { target { arm_nothumb } } } } */ -/* { dg-final { scan-assembler-times "rev16ne\\t" 1 { target { arm_nothumb } } } } */ -/* { dg-final { scan-assembler-times "rev16\\t" 2 { target { ! arm_nothumb } } } } */ -/* { dg-final { scan-assembler-times "rev\\t" 2 { target { arm_nothumb } } } } */ -/* { dg-final { scan-assembler-times "revne\\t" 2 { target { arm_nothumb } } } } */ -/* { dg-final { scan-assembler-times "rev\\t" 4 { target { ! arm_nothumb } } } } */ +/* { dg-final { scan-assembler-times "revsh\\t" 1 } } */ +/* { dg-final { scan-assembler-times "revshne\\t" 1 } } */ +/* { dg-final { scan-assembler-times "rev16\\t" 1 } } */ +/* { dg-final { scan-assembler-times "rev16ne\\t" 1 } } */ +/* { dg-final { scan-assembler-times "rev\\t" 2 } } */ +/* { dg-final { scan-assembler-times "revne\\t" 2 } } */ #include "builtin-bswap.x" -- cgit v1.1 From 9ae83078fe45d093bbaa02b8348f2407fe0c62d6 Mon Sep 17 00:00:00 2001 From: Robin Dapp Date: Mon, 15 Jan 2024 17:34:58 +0100 Subject: RISC-V: Adjust vec unit-stride load/store costs. Scalar loads provide offset addressing while unit-stride vector instructions cannot. The offset must be loaded into a general-purpose register before it can be used. In order to account for this, this patch adds an address arithmetic heuristic that keeps track of data reference operands. If we haven't seen the operand before we add the cost of a scalar statement. This helps to get rid of an lbm regression when vectorizing (roughly 0.5% fewer dynamic instructions). gcc5 improves by 0.2% and deepsjeng by 0.25%. wrf and nab degrade by 0.1%. This is because before we now adjust the cost of SLP as well as loop-vectorized instructions whereas we would only adjust loop-vectorized instructions before. Considering higher scalar_to_vec costs (3 vs 1) for all vectorization types causes some snippets not to get vectorized anymore. Given these costs the decision looks correct but appears worse when just counting dynamic instructions. In total SPECint 2017 has 4 bln dynamic instructions less and SPECfp 0.7 bln. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move... (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store offset handling. (costs::add_stmt_cost): Also adjust cost for statements without stmt_info. * config/riscv/riscv-vector-costs.h: Define zero constant. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c: New test. --- gcc/config/riscv/riscv-vector-costs.cc | 86 +++++++++++++++++++--- gcc/config/riscv/riscv-vector-costs.h | 10 +++ .../gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c | 51 +++++++++++++ .../gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c | 51 +++++++++++++ 4 files changed, 188 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c (limited to 'gcc') diff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc index 7c9840d..adf9c19 100644 --- a/gcc/config/riscv/riscv-vector-costs.cc +++ b/gcc/config/riscv/riscv-vector-costs.cc @@ -42,6 +42,7 @@ along with GCC; see the file COPYING3. If not see #include "backend.h" #include "tree-data-ref.h" #include "tree-ssa-loop-niter.h" +#include "tree-hash-traits.h" /* This file should be included last. */ #include "riscv-vector-costs.h" @@ -1047,18 +1048,81 @@ costs::better_main_loop_than_p (const vector_costs *uncast_other) const top of riscv_builtin_vectorization_cost handling which doesn't have any information on statement operation codes etc. */ -static unsigned -adjust_stmt_cost (enum vect_cost_for_stmt kind, tree vectype, int stmt_cost) +unsigned +costs::adjust_stmt_cost (enum vect_cost_for_stmt kind, loop_vec_info loop, + stmt_vec_info stmt_info, + slp_tree, tree vectype, int stmt_cost) { const cpu_vector_cost *costs = get_vector_costs (); switch (kind) { case scalar_to_vec: - return stmt_cost += (FLOAT_TYPE_P (vectype) ? costs->regmove->FR2VR - : costs->regmove->GR2VR); + stmt_cost += (FLOAT_TYPE_P (vectype) ? costs->regmove->FR2VR + : costs->regmove->GR2VR); + break; case vec_to_scalar: - return stmt_cost += (FLOAT_TYPE_P (vectype) ? costs->regmove->VR2FR - : costs->regmove->VR2GR); + stmt_cost += (FLOAT_TYPE_P (vectype) ? costs->regmove->VR2FR + : costs->regmove->VR2GR); + break; + case vector_load: + case vector_store: + { + /* Unit-stride vector loads and stores do not have offset addressing + as opposed to scalar loads and stores. + If the address depends on a variable we need an additional + add/sub for each load/store in the worst case. */ + if (stmt_info && stmt_info->stmt) + { + data_reference *dr = STMT_VINFO_DATA_REF (stmt_info); + class loop *father = stmt_info->stmt->bb->loop_father; + if (!loop && father && !father->inner && father->superloops) + { + tree ref; + if (TREE_CODE (dr->ref) != MEM_REF + || !(ref = TREE_OPERAND (dr->ref, 0)) + || TREE_CODE (ref) != SSA_NAME) + break; + + if (SSA_NAME_IS_DEFAULT_DEF (ref)) + break; + + if (memrefs.contains ({ref, cst0})) + break; + + memrefs.add ({ref, cst0}); + + /* In case we have not seen REF before and the base address + is a pointer operation try a bit harder. */ + tree base = DR_BASE_ADDRESS (dr); + if (TREE_CODE (base) == POINTER_PLUS_EXPR + || TREE_CODE (base) == POINTER_DIFF_EXPR) + { + /* Deconstruct BASE's first operand. If it is a binary + operation, i.e. a base and an "offset" store this + pair. Only increase the stmt_cost if we haven't seen + it before. */ + tree argp = TREE_OPERAND (base, 1); + typedef std::pair addr_pair; + addr_pair pair; + if (TREE_CODE_CLASS (TREE_CODE (argp)) == tcc_binary) + { + tree argp0 = tree_strip_nop_conversions + (TREE_OPERAND (argp, 0)); + tree argp1 = TREE_OPERAND (argp, 1); + pair = addr_pair (argp0, argp1); + if (memrefs.contains (pair)) + break; + + memrefs.add (pair); + stmt_cost += builtin_vectorization_cost (scalar_stmt, + NULL_TREE, 0); + } + } + } + } + break; + } + default: break; } @@ -1067,7 +1131,7 @@ adjust_stmt_cost (enum vect_cost_for_stmt kind, tree vectype, int stmt_cost) unsigned costs::add_stmt_cost (int count, vect_cost_for_stmt kind, - stmt_vec_info stmt_info, slp_tree, tree vectype, + stmt_vec_info stmt_info, slp_tree node, tree vectype, int misalign, vect_cost_model_location where) { int stmt_cost @@ -1080,6 +1144,7 @@ costs::add_stmt_cost (int count, vect_cost_for_stmt kind, if (loop_vinfo) analyze_loop_vinfo (loop_vinfo); + memrefs.empty (); m_analyzed_vinfo = true; } @@ -1092,11 +1157,12 @@ costs::add_stmt_cost (int count, vect_cost_for_stmt kind, as one iteration of the VLA loop. */ if (where == vect_body && m_unrolled_vls_niters) m_unrolled_vls_stmts += count * m_unrolled_vls_niters; - - if (vectype) - stmt_cost = adjust_stmt_cost (kind, vectype, stmt_cost); } + if (vectype) + stmt_cost = adjust_stmt_cost (kind, loop_vinfo, stmt_info, node, vectype, + stmt_cost); + return record_stmt_cost (stmt_info, where, count * stmt_cost); } diff --git a/gcc/config/riscv/riscv-vector-costs.h b/gcc/config/riscv/riscv-vector-costs.h index 4e2bbfd..ca0ef11 100644 --- a/gcc/config/riscv/riscv-vector-costs.h +++ b/gcc/config/riscv/riscv-vector-costs.h @@ -85,6 +85,12 @@ private: unsigned HOST_WIDE_INT m_unrolled_vls_niters = 0; unsigned HOST_WIDE_INT m_unrolled_vls_stmts = 0; + tree cst0 = build_int_cst (integer_type_node, 0); + + /* Store the memory references already processed. */ + typedef pair_hash tree_pair_hash; + hash_set memrefs; + void analyze_loop_vinfo (loop_vec_info); void record_potential_vls_unrolling (loop_vec_info); bool prefer_unrolled_loop () const; @@ -98,6 +104,10 @@ private: void record_potential_unexpected_spills (loop_vec_info); void adjust_vect_cost_per_loop (loop_vec_info); + unsigned adjust_stmt_cost (enum vect_cost_for_stmt kind, + loop_vec_info, + stmt_vec_info stmt_info, slp_tree, + tree vectype, int stmt_cost); }; } // namespace riscv_vector diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c new file mode 100644 index 0000000..530146a --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-tree-slp1-details" } */ + +#define f1 (1.0 / 3.0) +#define f2 (1.0 / 18.0) +#define f3 (1.0 / 36.0) + +#define SIZE_X 10 +#define SIZE_Y 10 +#define SIZE_Z 10 + +typedef enum {C = 0, + N, S, E, W, T, B, + NE, NW, SE, SW, + NT, NB, ST, SB, + ET, EB, WT, WB, + FLAGS, N_CELL_ENTRIES} CELL_ENTRIES; + +#define CALC_INDEX(x,y,z,e) ((e)+N_CELL_ENTRIES*((x)+ \ + (y)*SIZE_X+(z)*SIZE_X*SIZE_Y)) +#define GRID_ENTRY_SWEEP(g,dx,dy,dz,e) ((g)[CALC_INDEX(dx, dy, dz, e)+(i)]) +#define LOCAL(g,e) (GRID_ENTRY_SWEEP (g, 0, 0, 0, e)) + +void foo (double *grid) +{ + for( int i = CALC_INDEX(0, 0, -2, 0); \ + i < CALC_INDEX(0, 0, SIZE_Z + 2, 0); \ + i += N_CELL_ENTRIES ) { + LOCAL (grid, C ) = f1; + LOCAL (grid, N ) = f2; + LOCAL (grid, S ) = f2; + LOCAL (grid, E ) = f2; + LOCAL (grid, W ) = f2; + LOCAL (grid, T ) = f2; + LOCAL (grid, B ) = f2; + LOCAL (grid, NE) = f3; + LOCAL (grid, NW) = f3; + LOCAL (grid, SE) = f3; + LOCAL (grid, SW) = f3; + LOCAL (grid, NT) = f3; + LOCAL (grid, NB) = f3; + LOCAL (grid, ST) = f3; + LOCAL (grid, SB) = f3; + LOCAL (grid, ET) = f3; + LOCAL (grid, EB) = f3; + LOCAL (grid, WT) = f3; + LOCAL (grid, WB) = f3; + } +} + +/* { dg-final { scan-tree-dump-times "vectorized using SLP" 0 "slp1" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c new file mode 100644 index 0000000..7650a0e --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fdump-tree-slp1-details" } */ + +#define f1 3 +#define f2 4 +#define f3 5 + +#define SIZE_X 10 +#define SIZE_Y 10 +#define SIZE_Z 10 + +typedef enum {C = 0, + N, S, E, W, T, B, + NE, NW, SE, SW, + NT, NB, ST, SB, + ET, EB, WT, WB, + FLAGS, N_CELL_ENTRIES} CELL_ENTRIES; + +#define CALC_INDEX(x,y,z,e) ((e)+N_CELL_ENTRIES*((x)+ \ + (y)*SIZE_X+(z)*SIZE_X*SIZE_Y)) +#define GRID_ENTRY_SWEEP(g,dx,dy,dz,e) ((g)[CALC_INDEX(dx, dy, dz, e)+(i)]) +#define LOCAL(g,e) (GRID_ENTRY_SWEEP (g, 0, 0, 0, e)) + +void foo (unsigned long *grid) +{ + for( int i = CALC_INDEX(0, 0, -2, 0); \ + i < CALC_INDEX(0, 0, SIZE_Z + 2, 0); \ + i += N_CELL_ENTRIES ) { + LOCAL (grid, C ) = f1; + LOCAL (grid, N ) = f2; + LOCAL (grid, S ) = f2; + LOCAL (grid, E ) = f2; + LOCAL (grid, W ) = f2; + LOCAL (grid, T ) = f2; + LOCAL (grid, B ) = f2; + LOCAL (grid, NE) = f3; + LOCAL (grid, NW) = f3; + LOCAL (grid, SE) = f3; + LOCAL (grid, SW) = f3; + LOCAL (grid, NT) = f3; + LOCAL (grid, NB) = f3; + LOCAL (grid, ST) = f3; + LOCAL (grid, SB) = f3; + LOCAL (grid, ET) = f3; + LOCAL (grid, EB) = f3; + LOCAL (grid, WT) = f3; + LOCAL (grid, WB) = f3; + } +} + +/* { dg-final { scan-tree-dump-times "vectorized using SLP" 0 "slp1" } } */ -- cgit v1.1 From 59554a50be8ebbd52e8a6348a92110af182e1874 Mon Sep 17 00:00:00 2001 From: Robin Dapp Date: Wed, 6 Mar 2024 12:15:40 +0100 Subject: RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads [PR114200]. Three-operand instructions like vmacc are modeled with an implicit output reload when the output does not match one of the operands. For this we use vmv.v.v which is subject to length masking. In a situation where the current vl is less than the full vlenb and the fma's result value is used as input for a vector reduction (which is never length masked) we effectively only reduce vl elements. The masked-out elements are relevant for the reduction, though, leading to a wrong result. This patch replaces the vmv reloads by full-register reloads. gcc/ChangeLog: PR target/114200 PR target/114202 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr114200.c: New test. * gcc.target/riscv/rvv/autovec/pr114202.c: New test. --- gcc/config/riscv/vector.md | 96 +++++++++++----------- .../gcc.target/riscv/rvv/autovec/pr114200.c | 18 ++++ .../gcc.target/riscv/rvv/autovec/pr114202.c | 20 +++++ 3 files changed, 86 insertions(+), 48 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114200.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114202.c (limited to 'gcc') diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index f89f9c2..8b1c24c 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -5351,10 +5351,10 @@ "@ vmadd.vv\t%0,%4,%5%p1 vmacc.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%4\;vmacc.vv\t%0,%3,%4%p1 + vmv%m4r.v\t%0,%4\;vmacc.vv\t%0,%3,%4%p1 vmadd.vv\t%0,%4,%5%p1 vmacc.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%5\;vmacc.vv\t%0,%3,%4%p1" + vmv%m5r.v\t%0,%5\;vmacc.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "")]) @@ -5378,9 +5378,9 @@ "TARGET_VECTOR" "@ vmadd.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1 + vmv%m2r.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1 vmadd.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1" + vmv%m2r.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5409,9 +5409,9 @@ "TARGET_VECTOR" "@ vmacc.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1 + vmv%m4r.v\t%0,%4;vmacc.vv\t%0,%2,%3%p1 vmacc.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1" + vmv%m4r.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5462,9 +5462,9 @@ "TARGET_VECTOR" "@ vmadd.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1 + vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1 vmadd.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1" + vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -5494,9 +5494,9 @@ "TARGET_VECTOR" "@ vmacc.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 + vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 vmacc.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" + vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5562,9 +5562,9 @@ "TARGET_VECTOR && !TARGET_64BIT" "@ vmadd.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1 + vmv%m2r.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1 vmadd.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1" + vmv%m2r.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -5595,9 +5595,9 @@ "TARGET_VECTOR && !TARGET_64BIT" "@ vmacc.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 + vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 vmacc.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" + vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5649,10 +5649,10 @@ "@ vnmsub.vv\t%0,%4,%5%p1 vnmsac.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1 + vmv%m3r.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1 vnmsub.vv\t%0,%4,%5%p1 vnmsac.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1" + vmv%m3r.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "")]) @@ -5676,9 +5676,9 @@ "TARGET_VECTOR" "@ vnmsub.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1 + vmv%m2r.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1 vnmsub.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1" + vmv%m2r.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5707,9 +5707,9 @@ "TARGET_VECTOR" "@ vnmsac.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1 + vmv%m4r.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1 vnmsac.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1" + vmv%m4r.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5760,9 +5760,9 @@ "TARGET_VECTOR" "@ vnmsub.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1 + vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1 vnmsub.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1" + vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -5792,9 +5792,9 @@ "TARGET_VECTOR" "@ vnmsac.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 + vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 vnmsac.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" + vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5860,9 +5860,9 @@ "TARGET_VECTOR && !TARGET_64BIT" "@ vnmsub.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1 + vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1 vnmsub.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1" + vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -5893,9 +5893,9 @@ "TARGET_VECTOR && !TARGET_64BIT" "@ vnmsac.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 + vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 vnmsac.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" + vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -6555,10 +6555,10 @@ "@ vf.vv\t%0,%4,%5%p1 vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%3\;vf.vv\t%0,%4,%5%p1 + vmv%m3r.v\t%0,%3\;vf.vv\t%0,%4,%5%p1 vf.vv\t%0,%4,%5%p1 vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%3\;vf.vv\t%0,%4,%5%p1" + vmv%m3r.v\t%0,%3\;vf.vv\t%0,%4,%5%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set (attr "frm_mode") @@ -6586,9 +6586,9 @@ "TARGET_VECTOR" "@ vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1 + vmv%m2r.v\t%0,%2\;vf.vv\t%0,%3,%4%p1 vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" + vmv%m2r.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -6621,9 +6621,9 @@ "TARGET_VECTOR" "@ vf.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 + vmv%m4r.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 vf.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" + vmv%m4r.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -6680,9 +6680,9 @@ "TARGET_VECTOR" "@ vf.vf\t%0,%2,%4%p1 - vmv.v.v\t%0,%3\;vf.vf\t%0,%2,%4%p1 + vmv%m3r.v\t%0,%3\;vf.vf\t%0,%2,%4%p1 vf.vf\t%0,%2,%4%p1 - vmv.v.v\t%0,%3\;vf.vf\t%0,%2,%4%p1" + vmv%m3r.v\t%0,%3\;vf.vf\t%0,%2,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -6716,9 +6716,9 @@ "TARGET_VECTOR" "@ vf.vf\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 + vmv%m4r.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 vf.vf\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" + vmv%m4r.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -6778,10 +6778,10 @@ "@ vf.vv\t%0,%4,%5%p1 vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%3\;vf.vv\t%0,%4,%5%p1 + vmv%m3r.v\t%0,%3\;vf.vv\t%0,%4,%5%p1 vf.vv\t%0,%4,%5%p1 vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%3\;vf.vv\t%0,%4,%5%p1" + vmv%m3r.v\t%0,%3\;vf.vv\t%0,%4,%5%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set (attr "frm_mode") @@ -6810,9 +6810,9 @@ "TARGET_VECTOR" "@ vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1 + vmv%m2r.v\t%0,%2\;vf.vv\t%0,%3,%4%p1 vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" + vmv%m2r.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -6846,9 +6846,9 @@ "TARGET_VECTOR" "@ vf.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 + vmv%m4r.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 vf.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" + vmv%m4r.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -6907,9 +6907,9 @@ "TARGET_VECTOR" "@ vf.vf\t%0,%2,%4%p1 - vmv.v.v\t%0,%3\;vf.vf\t%0,%2,%4%p1 + vmv%m3r.v\t%0,%3\;vf.vf\t%0,%2,%4%p1 vf.vf\t%0,%2,%4%p1 - vmv.v.v\t%0,%3\;vf.vf\t%0,%2,%4%p1" + vmv%m3r.v\t%0,%3\;vf.vf\t%0,%2,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "3") @@ -6944,9 +6944,9 @@ "TARGET_VECTOR" "@ vf.vf\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 + vmv%m4r.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 vf.vf\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" + vmv%m4r.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114200.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114200.c new file mode 100644 index 0000000..ad64a02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114200.c @@ -0,0 +1,18 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-options { -march=rv64gcv -mabi=lp64d -O3 -fwrapv } } */ + +short a, e = 1; +_Bool b, d; +short c[300]; + +int main() { + for (int f = 0; f < 19; f++) { + for (int g = 0; g < 14; g++) + for (int h = 0; h < 10; h++) + a += c[g] + e; + b += d; + } + + if (a != 2660) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114202.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114202.c new file mode 100644 index 0000000..93a59bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114202.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-options { -march=rv64gcv -mabi=lp64d -O3 -fwrapv } } */ + +signed char a = 0, d = 0; +_Bool b; +signed char c[324]; +int e; + +int main() { + c[63] = 50; + for (int f = 0; f < 9; f++) { + for (unsigned g = 0; g < 12; g++) + for (char h = 0; h < 8; h++) + e = a += c[g * 9]; + b = e ? d : 0; + } + + if (a != 16) + __builtin_abort (); +} -- cgit v1.1 From 74e8cc28eda9b1d75588fcd4017a735911b9d2b4 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Wed, 6 Mar 2024 20:53:50 +0100 Subject: i386: Fix and improve insn constraint for V2QI arithmetic/shift insns optimize_function_for_size_p predicate is not stable during optab selection, because it also depends on node->count/node->frequency of the current function, which are updated during IPA, so they may change between early opts and late opts. Use optimize_size instead - optimize_size implies optimize_function_for_size_p (cfun), so if a named pattern uses "&& optimize_size" and the insn it splits into uses optimize_function_for_size_p (cfun), it shouldn't fail. PR target/114232 gcc/ChangeLog: * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead of optimize_function_for_size_p. Explictily enable for TARGET_SSE2. (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only. (v2qi3): Enable for optimize_size instead of optimize_function_for_size_p. Explictily enable for TARGET_SSE2. (v2qi SSE reg splitter): Enable for TARGET_SSE2 only. (v2qi3): Enable for optimize_size instead of optimize_function_for_size_p. --- gcc/config/i386/mmx.md | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) (limited to 'gcc') diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 2856ae6..9a8d603 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -2874,11 +2874,18 @@ (neg:V2QI (match_operand:V2QI 1 "register_operand" "0,Yw"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" + "!TARGET_PARTIAL_REG_STALL || optimize_size || TARGET_SSE2" "#" [(set_attr "isa" "*,sse2") (set_attr "type" "multi") - (set_attr "mode" "QI,TI")]) + (set_attr "mode" "QI,TI") + (set (attr "enabled") + (cond [(and (eq_attr "alternative" "0") + (and (match_test "TARGET_PARTIAL_REG_STALL") + (not (match_test "optimize_function_for_size_p (cfun)")))) + (symbol_ref "false") + ] + (const_string "*")))]) (define_split [(set (match_operand:V2QI 0 "general_reg_operand") @@ -2912,8 +2919,7 @@ (neg:V2QI (match_operand:V2QI 1 "sse_reg_operand"))) (clobber (reg:CC FLAGS_REG))] - "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) - && TARGET_SSE2 && reload_completed" + "TARGET_SSE2 && reload_completed" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (minus:V16QI (match_dup 0) (match_dup 1)))] @@ -2975,11 +2981,18 @@ (match_operand:V2QI 1 "register_operand" "0,0,Yw") (match_operand:V2QI 2 "register_operand" "Q,x,Yw"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" + "!TARGET_PARTIAL_REG_STALL || optimize_size || TARGET_SSE2" "#" [(set_attr "isa" "*,sse2_noavx,avx") (set_attr "type" "multi,sseadd,sseadd") - (set_attr "mode" "QI,TI,TI")]) + (set_attr "mode" "QI,TI,TI") + (set (attr "enabled") + (cond [(and (eq_attr "alternative" "0") + (and (match_test "TARGET_PARTIAL_REG_STALL") + (not (match_test "optimize_function_for_size_p (cfun)")))) + (symbol_ref "false") + ] + (const_string "*")))]) (define_split [(set (match_operand:V2QI 0 "general_reg_operand") @@ -3021,8 +3034,7 @@ (match_operand:V2QI 1 "sse_reg_operand") (match_operand:V2QI 2 "sse_reg_operand"))) (clobber (reg:CC FLAGS_REG))] - "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) - && TARGET_SSE2 && reload_completed" + "TARGET_SSE2 && reload_completed" [(set (match_dup 0) (plusminus:V16QI (match_dup 1) (match_dup 2)))] { @@ -3684,9 +3696,10 @@ (match_operand:V2QI 1 "register_operand" "0") (match_operand:QI 2 "nonmemory_operand" "cI"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" + "!TARGET_PARTIAL_REG_STALL || optimize_size" "#" - "&& reload_completed" + "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) + && reload_completed" [(parallel [(set (zero_extract:HI (match_dup 3) (const_int 8) (const_int 8)) (subreg:HI -- cgit v1.1 From 8b483cd5521de79c13cf4807fd004d442b9ad9cd Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Thu, 7 Mar 2024 00:17:38 +0000 Subject: Daily bump. --- gcc/ChangeLog | 91 +++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog | 19 +++++++++++ gcc/fortran/ChangeLog | 16 +++++++++ gcc/testsuite/ChangeLog | 90 ++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 217 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 89da260..b9b55d9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,94 @@ +2024-03-06 Uros Bizjak + + PR target/114232 + * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead + of optimize_function_for_size_p. Explictily enable for TARGET_SSE2. + (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only. + (v2qi3): Enable for optimize_size instead + of optimize_function_for_size_p. Explictily enable for TARGET_SSE2. + (v2qi SSE reg splitter): Enable for TARGET_SSE2 only. + (v2qi3): Enable for optimize_size instead + of optimize_function_for_size_p. + +2024-03-06 Robin Dapp + + PR target/114200 + PR target/114202 + * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v. + +2024-03-06 Robin Dapp + + * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move... + (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store + offset handling. + (costs::add_stmt_cost): Also adjust cost for statements without + stmt_info. + * config/riscv/riscv-vector-costs.h: Define zero constant. + +2024-03-06 Wilco Dijkstra + + PR target/113915 + * config/arm/arm.md (NOCOND): Improve comment. + (arm_rev*) Add predicable. + * config/arm/arm.cc (arm_final_prescan_insn): Add check for + PREDICABLE_YES. + +2024-03-06 Jeff Law + + PR target/113001 + PR target/112871 + * config/riscv/riscv.cc (expand_conditional_move): Do not swap + operands when the comparison operand is the same as the false + arm for a NE test. + +2024-03-06 Uros Bizjak + + * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]: + Eliminate common code and use generic code instead. + +2024-03-06 Georg-Johann Lay + + * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust + rtx cost. + +2024-03-06 Richard Biener + + PR tree-optimization/114239 + * tree-vect-loop.cc (vect_get_vect_def): Remove. + (vect_create_epilog_for_reduction): The passed in stmt_info + should now be the live stmt that produces the scalar reduction + result. Revert PR114192 fix. Base reduction info off + info_for_reduction. Remove special handling of + early-break/peeled, restore original vector def gathering. + Make sure to pick the correct exit PHIs. + (vectorizable_live_operation): Pass in the proper stmt_info + for early break exits. + +2024-03-06 Richard Sandiford + + * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add + out-of-class definitions of static constants. + +2024-03-06 Richard Biener + + PR tree-optimization/114249 + * tree-vect-slp.cc (vect_build_slp_instance): Move making + a BB reduction lane number even ... + (vect_slp_check_for_roots): ... here to avoid leaking + pattern defs. + +2024-03-06 Richard Biener + + PR tree-optimization/114246 + * tree-ssa-dse.cc (increment_start_addr): Strip useless + type conversions from the adjusted address. + +2024-03-06 Jakub Jelinek + + PR rtl-optimization/114190 + * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper): + Call df_remove_problem for df_note before calling df_analyze. + 2024-03-05 Cupertino Miranda Indu Bhagat diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index c7e324d..8b3f474 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20240306 +20240307 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 41e9a44..fbf3739 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,22 @@ +2024-03-06 Marek Polacek + + PR c++/114114 + * pt.cc (maybe_instantiate_noexcept): Save/restore + cp_unevaluated_operand, c_inhibit_evaluation_warnings, and + cp_noexcept_operand around the tsubst_expr call. + +2024-03-06 Nathaniel Shead + + PR c++/113629 + * pt.cc (type_unification_real): Only use DEDUCE_CONV for the + return type of a conversion function. + +2024-03-06 Patrick Palka + + * module.cc (trees_out::get_merge_kind) : + Accomodate class-scope DECL_UNINSTANTIATED_TEMPLATE_FRIEND_P + TEMPLATE_DECL. Consolidate IDENTIFIER_ANON_P cases. + 2024-03-05 Patrick Palka * parser.cc (cp_parser_translation_unit): Relax GMF contents diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 77b8b15..fb11c05 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,19 @@ +2024-03-06 Harald Anlauf + + PR fortran/103707 + PR fortran/106987 + * arith.cc (is_hard_arith_error): New helper function to determine + whether an arithmetic error is "hard" or not. + (check_result): Use it. + (gfc_arith_divide): Set "Division by zero" only for regular + numerators of real and complex divisions. + (reduce_unary): Use is_hard_arith_error to determine whether a hard + or (recoverable) soft error was encountered. Terminate immediately + on hard error, otherwise remember code of first soft error. + (reduce_binary_ac): Likewise. + (reduce_binary_ca): Likewise. + (reduce_binary_aa): Likewise. + 2024-03-01 Harald Anlauf PR fortran/104819 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3e20a20..ea18659 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,93 @@ +2024-03-06 Robin Dapp + + * gcc.target/riscv/rvv/autovec/pr114200.c: New test. + * gcc.target/riscv/rvv/autovec/pr114202.c: New test. + +2024-03-06 Robin Dapp + + * gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c: New test. + * gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c: New test. + +2024-03-06 Wilco Dijkstra + + PR target/113915 + * gcc.target/arm/builtin-bswap-1.c: Fix test to allow conditional + execution both for Arm and Thumb-2. + +2024-03-06 Jeff Law + + PR target/113001 + PR target/112871 + * gcc.target/riscv/zicond-ice-3.c: New test. + * gcc.target/riscv/zicond-ice-4.c: New test. + +2024-03-06 Harald Anlauf + + PR fortran/103707 + PR fortran/106987 + * gfortran.dg/pr99350.f90: + * gfortran.dg/arithmetic_overflow_3.f90: New test. + +2024-03-06 Marek Polacek + + PR c++/114114 + * g++.dg/cpp0x/noexcept84.C: New test. + +2024-03-06 Thomas Schwinge + + * gcc.target/gcn/sram-ecc-3.c: Adjust. + * gcc.target/gcn/sram-ecc-4.c: Likewise. + * gcc.target/gcn/sram-ecc-7.c: Likewise. + * gcc.target/gcn/sram-ecc-8.c: Likewise. + +2024-03-06 Richard Biener + + PR tree-optimization/114239 + * gcc.dg/vect/vect-early-break_122-pr114239.c: New testcase. + +2024-03-06 Xi Ruoyao + + * gcc.target/loongarch/vfcmp-f.c: Rewrite to avoid named + registers. + * gcc.target/loongarch/vfcmp-d.c: Likewise. + * gcc.target/loongarch/xvfcmp-f.c: Likewise. + * gcc.target/loongarch/xvfcmp-d.c: Likewise. + +2024-03-06 Nathaniel Shead + + PR c++/113629 + * g++.dg/cpp23/explicit-obj-conv-op.C: New test. + +2024-03-06 Richard Biener + + PR tree-optimization/114249 + * gcc.dg/vect/bb-slp-pr114249.c: New testcase. + +2024-03-06 Richard Biener + + PR tree-optimization/114246 + * gcc.dg/torture/pr114246.c: New testcase. + +2024-03-06 Jakub Jelinek + + PR rtl-optimization/114190 + * gcc.target/i386/avx-pr114190.c: New test. + +2024-03-06 Jerry DeLisle + + PR libfortran/105456 + * gfortran.dg/pr105456-nmlr.f90: New test. + * gfortran.dg/pr105456-nmlw.f90: New test. + * gfortran.dg/pr105456-ruf.f90: New test. + * gfortran.dg/pr105456-wf.f90: New test. + * gfortran.dg/pr105456-wuf.f90: New test. + +2024-03-06 Patrick Palka + + * g++.dg/modules/friend-7.h: New test. + * g++.dg/modules/friend-7_a.H: New test. + * g++.dg/modules/friend-7_b.C: New test. + 2024-03-05 Cupertino Miranda Indu Bhagat -- cgit v1.1 From 03932d3203bce244edd812b81921c2f16ea18d86 Mon Sep 17 00:00:00 2001 From: Jerry DeLisle Date: Wed, 6 Mar 2024 19:46:04 -0800 Subject: Fortran: Fix issue with using snprintf function. The previous patch used snprintf to set the message string. The message string is not a formatted string and the snprintf will interpret '%' related characters as format specifiers when there are no associated output variables. A segfault ensues. This change replaces snprintf with a fortran string copy function and null terminates the message string. PR libfortran/105456 libgfortran/ChangeLog: * io/list_read.c (list_formatted_read_scalar): Use fstrcpy from libgfortran/runtime/string.c to replace snprintf. (nml_read_obj): Likewise. * io/transfer.c (unformatted_read): Likewise. (unformatted_write): Likewise. (formatted_transfer_scalar_read): Likewise. (formatted_transfer_scalar_write): Likewise. * io/write.c (list_formatted_write_scalar): Likewise. (nml_write_obj): Likewise. gcc/testsuite/ChangeLog: * gfortran.dg/pr105456.f90: Revise using '%' characters in users error message. --- gcc/testsuite/gfortran.dg/pr105456.f90 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gfortran.dg/pr105456.f90 b/gcc/testsuite/gfortran.dg/pr105456.f90 index 1883238..60cd3b6 100644 --- a/gcc/testsuite/gfortran.dg/pr105456.f90 +++ b/gcc/testsuite/gfortran.dg/pr105456.f90 @@ -19,7 +19,7 @@ contains character :: ch read (unit,fmt='(A1)', advance="no", iostat=piostat, iomsg=piomsg) ch piostat = 42 - piomsg="The users message" + piomsg="The users message containing % and %% and %s and other stuff" dtv%ch = ch end subroutine read_formatted end module sk1 @@ -35,4 +35,4 @@ program skip1 write (*,'(10(A))') "Read: '",x%ch,"'" end program skip1 ! { dg-output ".*(unit = 10, file = .*)" } -! { dg-output "Fortran runtime error: The users message" } +! { dg-output "Fortran runtime error: The users message containing % and %% and %s and other stuff" } -- cgit v1.1 From 1cd8254ebad7b73993d2acee80a7caf37c21878a Mon Sep 17 00:00:00 2001 From: "demin.han" Date: Mon, 26 Feb 2024 14:50:15 +0800 Subject: RISC-V: Refactor expand_vec_cmp [NFC] There are two expand_vec_cmp functions. They have same structure and similar code. We can use default arguments instead of overloading. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments (expand_vec_cmp_float): Adapt arguments Signed-off-by: demin.han --- gcc/config/riscv/riscv-protos.h | 2 +- gcc/config/riscv/riscv-v.cc | 44 +++++++++++++---------------------------- 2 files changed, 15 insertions(+), 31 deletions(-) (limited to 'gcc') diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 80efdf2..b873559 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -603,7 +603,7 @@ bool simm5_p (rtx); bool neg_simm5_p (rtx); #ifdef RTX_CODE bool has_vi_variant_p (rtx_code, rtx); -void expand_vec_cmp (rtx, rtx_code, rtx, rtx); +void expand_vec_cmp (rtx, rtx_code, rtx, rtx, rtx = nullptr, rtx = nullptr); bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); void expand_cond_len_unop (unsigned, rtx *); void expand_cond_len_binop (unsigned, rtx *); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 2d32db0..967f4e3 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2775,7 +2775,8 @@ vectorize_related_mode (machine_mode vector_mode, scalar_mode element_mode, /* Expand an RVV comparison. */ void -expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1) +expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask, + rtx maskoff) { machine_mode mask_mode = GET_MODE (target); machine_mode data_mode = GET_MODE (op0); @@ -2785,8 +2786,8 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1) { rtx lt = gen_reg_rtx (mask_mode); rtx gt = gen_reg_rtx (mask_mode); - expand_vec_cmp (lt, LT, op0, op1); - expand_vec_cmp (gt, GT, op0, op1); + expand_vec_cmp (lt, LT, op0, op1, mask, maskoff); + expand_vec_cmp (gt, GT, op0, op1, mask, maskoff); icode = code_for_pred (IOR, mask_mode); rtx ops[] = {target, lt, gt}; emit_vlmax_insn (icode, BINARY_MASK_OP, ops); @@ -2794,33 +2795,16 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1) } rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1); - rtx ops[] = {target, cmp, op0, op1}; - emit_vlmax_insn (icode, COMPARE_OP, ops); -} - -void -expand_vec_cmp (rtx target, rtx_code code, rtx mask, rtx maskoff, rtx op0, - rtx op1) -{ - machine_mode mask_mode = GET_MODE (target); - machine_mode data_mode = GET_MODE (op0); - insn_code icode = get_cmp_insn_code (code, data_mode); - - if (code == LTGT) + if (!mask && !maskoff) { - rtx lt = gen_reg_rtx (mask_mode); - rtx gt = gen_reg_rtx (mask_mode); - expand_vec_cmp (lt, LT, mask, maskoff, op0, op1); - expand_vec_cmp (gt, GT, mask, maskoff, op0, op1); - icode = code_for_pred (IOR, mask_mode); - rtx ops[] = {target, lt, gt}; - emit_vlmax_insn (icode, BINARY_MASK_OP, ops); - return; + rtx ops[] = {target, cmp, op0, op1}; + emit_vlmax_insn (icode, COMPARE_OP, ops); + } + else + { + rtx ops[] = {target, mask, maskoff, cmp, op0, op1}; + emit_vlmax_insn (icode, COMPARE_OP_MU, ops); } - - rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1); - rtx ops[] = {target, mask, maskoff, cmp, op0, op1}; - emit_vlmax_insn (icode, COMPARE_OP_MU, ops); } /* Expand an RVV floating-point comparison: @@ -2898,7 +2882,7 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1, else { /* vmfeq.vv v0, vb, vb, v0.t */ - expand_vec_cmp (eq0, EQ, eq0, eq0, op1, op1); + expand_vec_cmp (eq0, EQ, op1, op1, eq0, eq0); } break; default: @@ -2916,7 +2900,7 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1, if (code == ORDERED) emit_move_insn (target, eq0); else - expand_vec_cmp (eq0, code, eq0, eq0, op0, op1); + expand_vec_cmp (eq0, code, op0, op1, eq0, eq0); if (can_invert_p) { -- cgit v1.1 From 95b6ee96348041eaee9133f082b57f3e57ef0b11 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 7 Mar 2024 08:43:16 +0100 Subject: match.pd: Optimize a * !a to 0 [PR114009] The following patch attempts to fix an optimization regression through adding a simple simplification. We already have the /* (m1 CMP m2) * d -> (m1 CMP m2) ? d : 0 */ (if (!canonicalize_math_p ()) (for cmp (tcc_comparison) (simplify (mult:c (convert (cmp@0 @1 @2)) @3) (if (INTEGRAL_TYPE_P (type) && INTEGRAL_TYPE_P (TREE_TYPE (@0))) (cond @0 @3 { build_zero_cst (type); }))) optimization which otherwise triggers during the a * !a multiplication, but that is done only late and we aren't able through range assumptions optimize it yet anyway. The patch adds a specific simplification for it. If a is zero, then a * !a will be 0 * 1 (or for signed 1-bit 0 * -1) and so 0. If a is non-zero, then a * !a will be a * 0 and so again 0. THe pattern is valid for scalar integers, complex integers and vector types, but I think will actually trigger only for the scalar integers. For vector types I've added other two with VEC_COND_EXPR in it, for complex there are different GENERIC trees to match and it is something that likely would be never matched in GIMPLE, so I didn't handle that. 2024-03-07 Jakub Jelinek PR tree-optimization/114009 * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures argument even for GENERIC, not just for GIMPLE. * match.pd (a * !a -> 0): New simplifications. * gcc.dg/tree-ssa/pr114009.c: New test. --- gcc/genmatch.cc | 2 +- gcc/match.pd | 11 +++++++++++ gcc/testsuite/gcc.dg/tree-ssa/pr114009.c | 33 ++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr114009.c (limited to 'gcc') diff --git a/gcc/genmatch.cc b/gcc/genmatch.cc index 61c4c8c..c982c95 100644 --- a/gcc/genmatch.cc +++ b/gcc/genmatch.cc @@ -4071,7 +4071,7 @@ decision_tree::gen (vec &files, bool gimple) for (unsigned i = 0; i < as_a (s->s->s->match)->ops.length (); ++i) fp_decl (f, " tree ARG_UNUSED (_p%d),", i); - fp_decl (f, " tree *captures"); + fp_decl (f, " tree *ARG_UNUSED (captures)"); } for (unsigned i = 0; i < s->s->s->for_subst_vec.length (); ++i) { diff --git a/gcc/match.pd b/gcc/match.pd index 4edba7c..9ce3133 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -1219,6 +1219,17 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) && tree_nop_conversion_p (type, TREE_TYPE (@1))) (lshift @0 @2))) +/* Fold a * !a into 0. */ +(simplify + (mult:c @0 (convert? (eq @0 integer_zerop))) + { build_zero_cst (type); }) +(simplify + (mult:c @0 (vec_cond (eq @0 integer_zerop) @1 integer_zerop)) + { build_zero_cst (type); }) +(simplify + (mult:c @0 (vec_cond (ne @0 integer_zerop) integer_zerop @1)) + { build_zero_cst (type); }) + /* Shifts by precision or greater result in zero. */ (for shift (lshift rshift) (simplify diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr114009.c b/gcc/testsuite/gcc.dg/tree-ssa/pr114009.c new file mode 100644 index 0000000..3b0486e --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr114009.c @@ -0,0 +1,33 @@ +/* PR tree-optimization/114009 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wno-psabi -fdump-tree-forwprop1" } */ +/* { dg-final { scan-tree-dump-times " return 0;" 3 "forwprop1" } } */ +/* { dg-final { scan-tree-dump-times " (?:return| =) { 0, 0, 0, 0 };" 1 "forwprop1" } } */ + +int +foo (int x) +{ + x = (x / 2) * 2; + return (!x) * x; +} + +int +bar (int x, int y) +{ + (void) x; + return y * !y; +} + +unsigned long long +baz (unsigned long long x) +{ + return (!x) * x; +} + +typedef int V __attribute__((vector_size (4 * sizeof (int)))); + +V +qux (V x) +{ + return x * (x == 0); +} -- cgit v1.1 From 2f7d4728dbfd976788f77b8f43d4dc3c718b71b7 Mon Sep 17 00:00:00 2001 From: Yang Yujie Date: Wed, 6 Mar 2024 09:19:59 +0800 Subject: LoongArch: Use /lib instead of /lib64 as the library search path for MUSL. gcc/ChangeLog: * config.gcc: Add a case for loongarch*-*-linux-musl*. * config/loongarch/linux.h: Disable the multilib-compatible treatment for *musl* targets. * config/loongarch/musl.h: New file. --- gcc/config.gcc | 3 +++ gcc/config/loongarch/linux.h | 4 +++- gcc/config/loongarch/musl.h | 23 +++++++++++++++++++++++ 3 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 gcc/config/loongarch/musl.h (limited to 'gcc') diff --git a/gcc/config.gcc b/gcc/config.gcc index a1480b7..624e0da 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2538,6 +2538,9 @@ riscv*-*-freebsd*) loongarch*-*-linux*) tm_file="elfos.h gnu-user.h linux.h linux-android.h glibc-stdint.h ${tm_file}" + case ${target} in + *-linux-musl*) tm_file="${tm_file} loongarch/musl.h" + esac tm_file="${tm_file} loongarch/gnu-user.h loongarch/linux.h loongarch/loongarch-driver.h" extra_options="${extra_options} linux-android.opt" tmake_file="${tmake_file} loongarch/t-multilib loongarch/t-linux" diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h index 17d9f87..40d9ba6 100644 --- a/gcc/config/loongarch/linux.h +++ b/gcc/config/loongarch/linux.h @@ -21,7 +21,9 @@ along with GCC; see the file COPYING3. If not see * This ensures that a compiler configured with --disable-multilib * can work in a multilib environment. */ -#if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH) +#if !defined(LA_DEFAULT_TARGET_MUSL) \ + && defined(LA_DISABLE_MULTILIB) \ + && defined(LA_DISABLE_MULTIARCH) #if DEFAULT_ABI_BASE == ABI_BASE_LP64D #define ABI_LIBDIR "lib64" diff --git a/gcc/config/loongarch/musl.h b/gcc/config/loongarch/musl.h new file mode 100644 index 0000000..fa43bc8 --- /dev/null +++ b/gcc/config/loongarch/musl.h @@ -0,0 +1,23 @@ +/* Definitions for MUSL C library support. + Copyright (C) 2024 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + + +#ifndef LA_DEFAULT_TARGET_MUSL +#define LA_DEFAULT_TARGET_MUSL +#endif -- cgit v1.1 From ae1b05641ccf1cd4739b0998ce61cda6e5b772dd Mon Sep 17 00:00:00 2001 From: chenxiaolong Date: Wed, 6 Mar 2024 16:54:06 +0800 Subject: LoongArch: testsuite:Fix problems with incorrect results in vector test cases. In simd_correctness_check.h, the role of the macro ASSERTEQ_64 is to check the result of the passed vector values for the 64-bit data of each array element. It turns out that it uses the abs() function to check only the lower 32 bits of the data at a time, so it replaces abs() with the llabs() function. However, the following two problems may occur after modification: 1.FAIL in lasx-xvfrint_s.c and lsx-vfrint_s.c The reason for the error is because vector test cases that use __m{128,256} to define vector types are composed of 32-bit primitive types, they should use ASSERTEQ_32 instead of ASSERTEQ_64 to check for correctness. 2.FAIL in lasx-xvshuf_b.c and lsx-vshuf.c The cause of the error is that the expected result of the function setting in the test case is incorrect. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c: Replace ASSERTEQ_64 with the macro ASSERTEQ_32. * gcc.target/loongarch/vector/lasx/lasx-xvshuf_b.c: Modify the expected test results of some functions according to the function of the vector instruction. * gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c: Same modification as lasx-xvfrint_s.c. * gcc.target/loongarch/vector/lsx/lsx-vshuf.c: Same modification as lasx-xvshuf_b.c. * gcc.target/loongarch/vector/simd_correctness_check.h: Use the llabs() function instead of abs() to check the correctness of the results. --- .../loongarch/vector/lasx/lasx-xvfrint_s.c | 58 +++++++++++----------- .../loongarch/vector/lasx/lasx-xvshuf_b.c | 14 +++--- .../gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c | 50 +++++++++---------- .../gcc.target/loongarch/vector/lsx/lsx-vshuf.c | 12 ++--- .../loongarch/vector/simd_correctness_check.h | 2 +- 5 files changed, 68 insertions(+), 68 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c index fbfe300..4538528 100644 --- a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvfrint_s.c @@ -184,7 +184,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrne_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0xffffffff; *((int *)&__m256_op0[6]) = 0xffffffff; @@ -203,7 +203,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrne_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0xffffffff; *((int *)&__m256_op0[6]) = 0xffffffff; @@ -222,7 +222,7 @@ main () *((int *)&__m256_result[1]) = 0xffffffff; *((int *)&__m256_result[0]) = 0xffffffff; __m256_out = __lasx_xvfrintrne_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x01010101; *((int *)&__m256_op0[6]) = 0x01010101; @@ -241,7 +241,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrne_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x00000000; @@ -260,7 +260,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrne_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0xffffffff; *((int *)&__m256_op0[6]) = 0xffffffff; @@ -279,7 +279,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrne_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0xffffffff; *((int *)&__m256_op0[6]) = 0xffffffff; @@ -298,7 +298,7 @@ main () *((int *)&__m256_result[1]) = 0xffffffff; *((int *)&__m256_result[0]) = 0xffffffff; __m256_out = __lasx_xvfrintrne_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x01010101; *((int *)&__m256_op0[6]) = 0x01010101; @@ -317,7 +317,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrne_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x55555555; *((int *)&__m256_op0[6]) = 0x36aaaaac; @@ -336,7 +336,7 @@ main () *((int *)&__m256_result[1]) = 0x55555555; *((int *)&__m256_result[0]) = 0x80000000; __m256_out = __lasx_xvfrintrp_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x00000000; @@ -355,7 +355,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrp_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0xffffc741; *((int *)&__m256_op0[6]) = 0x8a023680; @@ -374,7 +374,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrp_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0xffffffff; @@ -393,7 +393,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0xffffffff; __m256_out = __lasx_xvfrintrp_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00200101; *((int *)&__m256_op0[6]) = 0x01610000; @@ -412,7 +412,7 @@ main () *((int *)&__m256_result[1]) = 0x3f800000; *((int *)&__m256_result[0]) = 0x3f800000; __m256_out = __lasx_xvfrintrp_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x00000000; @@ -431,7 +431,7 @@ main () *((int *)&__m256_result[1]) = 0xfefefefe; *((int *)&__m256_result[0]) = 0x3f800000; __m256_out = __lasx_xvfrintrp_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x1c1c1c1c; *((int *)&__m256_op0[6]) = 0x1c1c1c1c; @@ -450,7 +450,7 @@ main () *((int *)&__m256_result[1]) = 0xfffffffe; *((int *)&__m256_result[0]) = 0xffffff00; __m256_out = __lasx_xvfrintrp_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x00000000; @@ -469,7 +469,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrm_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x00000000; @@ -488,7 +488,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrm_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0xffffffff; *((int *)&__m256_op0[6]) = 0xffffffff; @@ -507,7 +507,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0xffffffff; __m256_out = __lasx_xvfrintrm_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x5d20a0a1; *((int *)&__m256_op0[6]) = 0x5d20a0a1; @@ -526,7 +526,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrm_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x001d001d; @@ -545,7 +545,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrm_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x00000000; @@ -564,7 +564,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrm_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x00000000; @@ -583,7 +583,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrm_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x00000000; @@ -602,7 +602,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrz_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0xffffffff; *((int *)&__m256_op0[6]) = 0xfffffffe; @@ -621,7 +621,7 @@ main () *((int *)&__m256_result[1]) = 0xffffffff; *((int *)&__m256_result[0]) = 0xfffffffe; __m256_out = __lasx_xvfrintrz_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x00000000; @@ -640,7 +640,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0x00000000; __m256_out = __lasx_xvfrintrz_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x00000000; *((int *)&__m256_op0[6]) = 0x00000000; @@ -659,7 +659,7 @@ main () *((int *)&__m256_result[1]) = 0x00000000; *((int *)&__m256_result[0]) = 0xffffffff; __m256_out = __lasx_xvfrintrz_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0x80000000; *((int *)&__m256_op0[6]) = 0x80000000; @@ -678,7 +678,7 @@ main () *((int *)&__m256_result[1]) = 0xffffffff; *((int *)&__m256_result[0]) = 0xffffffff; __m256_out = __lasx_xvfrintrz_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0xffffffff; *((int *)&__m256_op0[6]) = 0xffffffff; @@ -697,7 +697,7 @@ main () *((int *)&__m256_result[1]) = 0xffffffff; *((int *)&__m256_result[0]) = 0xffffffff; __m256_out = __lasx_xvfrintrz_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); *((int *)&__m256_op0[7]) = 0xf5fffc00; *((int *)&__m256_op0[6]) = 0xfc000000; @@ -716,7 +716,7 @@ main () *((int *)&__m256_result[1]) = 0xf5fffc00; *((int *)&__m256_result[0]) = 0xfc000000; __m256_out = __lasx_xvfrintrz_s (__m256_op0); - ASSERTEQ_64 (__LINE__, __m256_result, __m256_out); + ASSERTEQ_32 (__LINE__, __m256_result, __m256_out); return 0; } diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvshuf_b.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvshuf_b.c index b8ab387..910d293 100644 --- a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvshuf_b.c +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvshuf_b.c @@ -99,9 +99,9 @@ main () *((unsigned long *)&__m256i_op1[2]) = 0x7ff0000000000000; *((unsigned long *)&__m256i_op1[1]) = 0x7ff0000000000000; *((unsigned long *)&__m256i_op1[0]) = 0x7ff0000000000000; - *((unsigned long *)&__m256i_op2[3]) = 0x3ff0010000000000; + *((unsigned long *)&__m256i_op2[3]) = 0x3f11010000000000; *((unsigned long *)&__m256i_op2[2]) = 0x0000000000000000; - *((unsigned long *)&__m256i_op2[1]) = 0x3ff0010000000000; + *((unsigned long *)&__m256i_op2[1]) = 0x3f11010000000000; *((unsigned long *)&__m256i_op2[0]) = 0x0000000000000000; *((unsigned long *)&__m256i_result[3]) = 0x0000000000000000; *((unsigned long *)&__m256i_result[2]) = 0x0000000000000000; @@ -200,7 +200,7 @@ main () *((unsigned long *)&__m256i_op2[0]) = 0x0000000000000000; *((unsigned long *)&__m256i_result[3]) = 0x0000000000000000; *((unsigned long *)&__m256i_result[2]) = 0x0000000000000000; - *((unsigned long *)&__m256i_result[1]) = 0x0000000000000000; + *((unsigned long *)&__m256i_result[1]) = 0xffffffff00000000; *((unsigned long *)&__m256i_result[0]) = 0x0000000000000000; __m256i_out = __lasx_xvshuf_h (__m256i_op0, __m256i_op1, __m256i_op2); ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); @@ -351,7 +351,7 @@ main () *((unsigned long *)&__m256i_op2[1]) = 0x0000000000000001; *((unsigned long *)&__m256i_op2[0]) = 0x00000000012e2110; *((unsigned long *)&__m256i_result[3]) = 0x0000000000000001; - *((unsigned long *)&__m256i_result[2]) = 0x0000000200000000; + *((unsigned long *)&__m256i_result[2]) = 0x0000000000000000; *((unsigned long *)&__m256i_result[1]) = 0x00000000012e2110; *((unsigned long *)&__m256i_result[0]) = 0x0000000000000000; __m256i_out = __lasx_xvshuf_w (__m256i_op0, __m256i_op1, __m256i_op2); @@ -426,10 +426,10 @@ main () *((unsigned long *)&__m256i_op2[2]) = 0x8000000080000000; *((unsigned long *)&__m256i_op2[1]) = 0xdfffffffdfffffff; *((unsigned long *)&__m256i_op2[0]) = 0x8000000080000000; - *((unsigned long *)&__m256i_result[3]) = 0x8000000080000000; + *((unsigned long *)&__m256i_result[3]) = 0xdfffffff80000000; *((unsigned long *)&__m256i_result[2]) = 0x7fc00000dfffffff; - *((unsigned long *)&__m256i_result[1]) = 0x8000000080000000; - *((unsigned long *)&__m256i_result[0]) = 0x8000000080000000; + *((unsigned long *)&__m256i_result[1]) = 0x7fc0000000000000; + *((unsigned long *)&__m256i_result[0]) = 0x8000000000000000; __m256i_out = __lasx_xvshuf_w (__m256i_op0, __m256i_op1, __m256i_op2); ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out); diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c index 61f2832..5ba91ee 100644 --- a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c +++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c @@ -79,7 +79,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrne_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00130013; *((int *)&__m128_op0[2]) = 0x00130013; @@ -90,7 +90,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrne_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x20202020; *((int *)&__m128_op0[2]) = 0x20202020; @@ -101,7 +101,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrne_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00000000; *((int *)&__m128_op0[2]) = 0x00000000; @@ -112,7 +112,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrne_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0xffffffff; *((int *)&__m128_op0[2]) = 0xffffffff; @@ -123,7 +123,7 @@ main () *((int *)&__m128_result[1]) = 0xffffffff; *((int *)&__m128_result[0]) = 0xffffffff; __m128_out = __lsx_vfrintrne_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00000000; *((int *)&__m128_op0[2]) = 0x00000001; @@ -134,7 +134,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrne_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00000000; *((int *)&__m128_op0[2]) = 0x00000000; @@ -145,7 +145,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrne_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0xfffbfffb; *((int *)&__m128_op0[2]) = 0xfffbfffb; @@ -156,7 +156,7 @@ main () *((int *)&__m128_result[1]) = 0xfffbfffb; *((int *)&__m128_result[0]) = 0xfffbfffb; __m128_out = __lsx_vfrintrne_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x0ff780a1; *((int *)&__m128_op0[2]) = 0x0efc01af; @@ -167,7 +167,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0xfe7f0000; __m128_out = __lsx_vfrintrne_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00000000; *((int *)&__m128_op0[2]) = 0x00000000; @@ -178,7 +178,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrp_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00000000; *((int *)&__m128_op0[2]) = 0xefffffff; @@ -189,7 +189,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrp_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0xffffffff; *((int *)&__m128_op0[2]) = 0xffffff00; @@ -200,7 +200,7 @@ main () *((int *)&__m128_result[1]) = 0xffffffff; *((int *)&__m128_result[0]) = 0xffffff00; __m128_out = __lsx_vfrintrp_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0xffffb96b; *((int *)&__m128_op0[2]) = 0xffff57c9; @@ -211,7 +211,7 @@ main () *((int *)&__m128_result[1]) = 0xffff6080; *((int *)&__m128_result[0]) = 0xffff4417; __m128_out = __lsx_vfrintrp_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00ff00ff; *((int *)&__m128_op0[2]) = 0x00ff00ff; @@ -222,7 +222,7 @@ main () *((int *)&__m128_result[1]) = 0x62cbf96e; *((int *)&__m128_result[0]) = 0x4acfaf40; __m128_out = __lsx_vfrintrp_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00000000; *((int *)&__m128_op0[2]) = 0x00002000; @@ -233,7 +233,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x3f800000; __m128_out = __lsx_vfrintrp_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0xffffffff; *((int *)&__m128_op0[2]) = 0xffffffff; @@ -244,7 +244,7 @@ main () *((int *)&__m128_result[1]) = 0xffffffff; *((int *)&__m128_result[0]) = 0xffffffff; __m128_out = __lsx_vfrintrp_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x63636363; *((int *)&__m128_op0[2]) = 0x63abdf16; @@ -255,7 +255,7 @@ main () *((int *)&__m128_result[1]) = 0x42000000; *((int *)&__m128_result[0]) = 0x3f800000; __m128_out = __lsx_vfrintrp_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00000000; *((int *)&__m128_op0[2]) = 0x00000000; @@ -266,7 +266,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrm_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0xa5c4c774; *((int *)&__m128_op0[2]) = 0x856ba83b; @@ -277,7 +277,7 @@ main () *((int *)&__m128_result[1]) = 0xbf800000; *((int *)&__m128_result[0]) = 0x54691124; __m128_out = __lsx_vfrintrm_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00000000; *((int *)&__m128_op0[2]) = 0x00010002; @@ -288,7 +288,7 @@ main () *((int *)&__m128_result[1]) = 0xffffffff; *((int *)&__m128_result[0]) = 0xffd60015; __m128_out = __lsx_vfrintrm_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0xffffffff; *((int *)&__m128_op0[2]) = 0x3c992b2e; @@ -299,7 +299,7 @@ main () *((int *)&__m128_result[1]) = 0xffffffff; *((int *)&__m128_result[0]) = 0xffff730f; __m128_out = __lsx_vfrintrz_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00000000; *((int *)&__m128_op0[2]) = 0x00000001; @@ -310,7 +310,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrz_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x18171615; *((int *)&__m128_op0[2]) = 0x17161514; @@ -321,7 +321,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrz_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x62cbf96e; *((int *)&__m128_op0[2]) = 0x4acfaf40; @@ -332,7 +332,7 @@ main () *((int *)&__m128_result[1]) = 0xf0bc9a52; *((int *)&__m128_result[0]) = 0x78285a4a; __m128_out = __lsx_vfrintrz_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); *((int *)&__m128_op0[3]) = 0x00000000; *((int *)&__m128_op0[2]) = 0x00000000; @@ -343,7 +343,7 @@ main () *((int *)&__m128_result[1]) = 0x00000000; *((int *)&__m128_result[0]) = 0x00000000; __m128_out = __lsx_vfrintrz_s (__m128_op0); - ASSERTEQ_64 (__LINE__, __m128_result, __m128_out); + ASSERTEQ_32 (__LINE__, __m128_result, __m128_out); return 0; } diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vshuf.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vshuf.c index f3b800f..93a3078 100644 --- a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vshuf.c +++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vshuf.c @@ -33,7 +33,7 @@ main () *((unsigned long *)&__m128i_op2[1]) = 0x0000000000000000; *((unsigned long *)&__m128i_op2[0]) = 0x3f2f1f0f00000000; *((unsigned long *)&__m128i_result[1]) = 0x0000000000000000; - *((unsigned long *)&__m128i_result[0]) = 0x0000000000000000; + *((unsigned long *)&__m128i_result[0]) = 0x00ff00ff00000000; __m128i_out = __lsx_vshuf_b (__m128i_op0, __m128i_op1, __m128i_op2); ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); @@ -153,7 +153,7 @@ main () *((unsigned long *)&__m128i_op1[0]) = 0x000000002bfd9461; *((unsigned long *)&__m128i_op2[1]) = 0x00007fff00007fff; *((unsigned long *)&__m128i_op2[0]) = 0x0000000000000000; - *((unsigned long *)&__m128i_result[1]) = 0x0000000000000000; + *((unsigned long *)&__m128i_result[1]) = 0x00007fff00000000; *((unsigned long *)&__m128i_result[0]) = 0x0000000000000000; __m128i_out = __lsx_vshuf_h (__m128i_op0, __m128i_op1, __m128i_op2); ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); @@ -198,7 +198,7 @@ main () *((unsigned long *)&__m128i_op2[1]) = 0x00000000000000c0; *((unsigned long *)&__m128i_op2[0]) = 0x00000001ffffff29; *((unsigned long *)&__m128i_result[1]) = 0xffffff29ffffff29; - *((unsigned long *)&__m128i_result[0]) = 0x0000000100000001; + *((unsigned long *)&__m128i_result[0]) = 0xffffff2900000001; __m128i_out = __lsx_vshuf_w (__m128i_op0, __m128i_op1, __m128i_op2); ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); @@ -219,7 +219,7 @@ main () *((unsigned long *)&__m128i_op1[0]) = 0x0000000000000000; *((unsigned long *)&__m128i_op2[1]) = 0x0000000020000020; *((unsigned long *)&__m128i_op2[0]) = 0x0000000020000020; - *((unsigned long *)&__m128i_result[1]) = 0x2000002000000000; + *((unsigned long *)&__m128i_result[1]) = 0x0000000000000000; *((unsigned long *)&__m128i_result[0]) = 0x2000002020000020; __m128i_out = __lsx_vshuf_w (__m128i_op0, __m128i_op1, __m128i_op2); ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); @@ -241,7 +241,7 @@ main () *((unsigned long *)&__m128i_op1[0]) = 0x0000001000000010; *((unsigned long *)&__m128i_op2[1]) = 0x8000000100000000; *((unsigned long *)&__m128i_op2[0]) = 0x8000000000000103; - *((unsigned long *)&__m128i_result[1]) = 0x0000010300000103; + *((unsigned long *)&__m128i_result[1]) = 0x8000000000000103; *((unsigned long *)&__m128i_result[0]) = 0x0000010380000001; __m128i_out = __lsx_vshuf_w (__m128i_op0, __m128i_op1, __m128i_op2); ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); @@ -252,7 +252,7 @@ main () *((unsigned long *)&__m128i_op1[0]) = 0x0000000000000000; *((unsigned long *)&__m128i_op2[1]) = 0xffffffffffffffff; *((unsigned long *)&__m128i_op2[0]) = 0xffffffffffffffff; - *((unsigned long *)&__m128i_result[1]) = 0x0000000000000000; + *((unsigned long *)&__m128i_result[1]) = 0xffffffff00000000; *((unsigned long *)&__m128i_result[0]) = 0xffffffffffffffff; __m128i_out = __lsx_vshuf_w (__m128i_op0, __m128i_op1, __m128i_op2); ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out); diff --git a/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h index 551340b..c1adab5 100644 --- a/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h +++ b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h @@ -10,7 +10,7 @@ { \ long long *temp_ref = (long long *)&ref[i], \ *temp_res = (long long *)&res[i]; \ - if (abs (*temp_ref - *temp_res) > 0) \ + if (llabs (*temp_ref - *temp_res) > 0) \ { \ printf (" error: %s at line %ld , expected " #ref \ "[%ld]:0x%016lx, got: 0x%016lx\n", \ -- cgit v1.1 From e1bd0f293d8407d4e8149fbafd470612323dc938 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 7 Mar 2024 10:01:08 +0100 Subject: sccvn: Avoid UB in ao_ref_init_from_vn_reference [PR105533] When compiling libgcc or on e.g. int a[64]; int p; void foo (void) { int s = 1; while (p) { s -= 11; a[s] != 0; } } sccvn invokes UB in the compiler as detected by ubsan: ../../gcc/poly-int.h:1089:5: runtime error: left shift of negative value -40 The problem is that we still use C++11..C++17 as the implementation language and in those C++ versions shifting negative values left is UB (well defined since C++20) and above in offset += op->off << LOG2_BITS_PER_UNIT; op->off is poly_int64 with -40 value (in libgcc with -8). I understand the offset_int << LOG2_BITS_PER_UNIT shifts but it is then well defined during underlying implementation which is done on the uhwi limbs, but for poly_int64 we use offset += pop->off * BITS_PER_UNIT; a few lines earlier and I think that is both more readable in what it actually does and triggers UB only if there would be signed multiply overflow. In the end, the compiler will treat them the same at least at the RTL level (at least, if not and they aren't the same cost, it should). 2024-03-07 Jakub Jelinek PR middle-end/105533 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) : Multiple op->off by BITS_PER_UNIT instead of shifting it left by LOG2_BITS_PER_UNIT. --- gcc/tree-ssa-sccvn.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index 88d3b24..9364989 100644 --- a/gcc/tree-ssa-sccvn.cc +++ b/gcc/tree-ssa-sccvn.cc @@ -1221,7 +1221,7 @@ ao_ref_init_from_vn_reference (ao_ref *ref, if (maybe_eq (op->off, -1)) max_size = -1; else - offset += op->off << LOG2_BITS_PER_UNIT; + offset += op->off * BITS_PER_UNIT; break; case REALPART_EXPR: -- cgit v1.1 From c655c8d8d845b36c59babb2413ce7aa3584dbeda Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 7 Mar 2024 10:02:00 +0100 Subject: expand: Fix UB in choose_mult_variant [PR105533] As documented in the function comment, choose_mult_variant attempts to compute costs of 3 different cases, val, -val and val - 1. The -val case is actually only done if val fits into host int, so there should be no overflow, but the val - 1 case is done unconditionally. val is shwi (but inside of synth_mult already uhwi), so when val is HOST_WIDE_INT_MIN, val - 1 invokes UB. The following patch fixes that by using val - HOST_WIDE_INT_1U, but I'm not really convinced it would DTRT for > 64-bit modes, so I've guarded it as well. Though, arch would need to have really strange costs that something that could be expressed as x << 63 would be better expressed as (x * 0x7fffffffffffffff) + 1 In the long term, I think we should just rewrite choose_mult_variant/synth_mult etc. to work on wide_int. 2024-03-07 Jakub Jelinek PR middle-end/105533 * expmed.cc (choose_mult_variant): Only try the val - 1 variant if val is not HOST_WIDE_INT_MIN or if mode has exactly HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing val - 1. * gcc.dg/pr105533.c: New test. --- gcc/expmed.cc | 14 +++++++++----- gcc/testsuite/gcc.dg/pr105533.c | 9 +++++++++ 2 files changed, 18 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/pr105533.c (limited to 'gcc') diff --git a/gcc/expmed.cc b/gcc/expmed.cc index 5916d6e..4ec035e 100644 --- a/gcc/expmed.cc +++ b/gcc/expmed.cc @@ -3285,11 +3285,15 @@ choose_mult_variant (machine_mode mode, HOST_WIDE_INT val, limit.latency = mult_cost - op_cost; } - synth_mult (&alg2, val - 1, &limit, mode); - alg2.cost.cost += op_cost; - alg2.cost.latency += op_cost; - if (CHEAPER_MULT_COST (&alg2.cost, &alg->cost)) - *alg = alg2, *variant = add_variant; + if (val != HOST_WIDE_INT_MIN + || GET_MODE_UNIT_PRECISION (mode) == HOST_BITS_PER_WIDE_INT) + { + synth_mult (&alg2, val - HOST_WIDE_INT_1U, &limit, mode); + alg2.cost.cost += op_cost; + alg2.cost.latency += op_cost; + if (CHEAPER_MULT_COST (&alg2.cost, &alg->cost)) + *alg = alg2, *variant = add_variant; + } return MULT_COST_LESS (&alg->cost, mult_cost); } diff --git a/gcc/testsuite/gcc.dg/pr105533.c b/gcc/testsuite/gcc.dg/pr105533.c new file mode 100644 index 0000000..912685e --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr105533.c @@ -0,0 +1,9 @@ +/* PR middle-end/105533 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +long long +foo (long long x, long long y) +{ + return ((x < 0) & (y != 0)) * (-__LONG_LONG_MAX__ - 1); +} -- cgit v1.1 From b209d905f5ce1fa9d76ce634fd54245ff340960b Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 7 Mar 2024 10:02:49 +0100 Subject: bb-reorder: Fix -freorder-blocks-and-partition ICEs on aarch64 with asm goto [PR110079] The following testcase ICEs, because fix_crossing_unconditional_branches thinks that asm goto is an unconditional jump and removes it, replacing it with unconditional jump to one of the labels. This doesn't happen on x86 because the function in question isn't invoked there at all: /* If the architecture does not have unconditional branches that can span all of memory, convert crossing unconditional branches into indirect jumps. Since adding an indirect jump also adds a new register usage, update the register usage information as well. */ if (!HAS_LONG_UNCOND_BRANCH) fix_crossing_unconditional_branches (); I think for the asm goto case, for the non-fallthru edge if any we should handle it like any other fallthru (and fix_crossing_unconditional_branches doesn't really deal with those, it only looks at explicit branches at the end of bbs and we are in cfglayout mode at that point) and for the labels we just pass the labels as immediates to the assembly and it is up to the user to figure out how to store them/branch to them or whatever they want to do. So, the following patch fixes this by not treating asm goto as a simple unconditional jump. I really think that on the !HAS_LONG_UNCOND_BRANCH targets we have a bug somewhere else, where outofcfglayout or whatever should actually create those indirect jumps on the crossing edges instead of adding normal unconditional jumps, I see e.g. in __attribute__((cold)) int bar (char *); __attribute__((hot)) int baz (char *); void qux (int x) { if (__builtin_expect (!x, 1)) goto l1; bar (""); goto l1; l1: baz (""); } void corge (int x) { if (__builtin_expect (!x, 0)) goto l1; baz (""); l2: return; l1: bar (""); goto l2; } with -O2 -freorder-blocks-and-partition on aarch64 before/after this patch just b .L? jumps which I believe are +-32MB, so if .text is larger than 32MB, it could fail to link, but this patch doesn't address that. 2024-03-07 Jakub Jelinek PR rtl-optimization/110079 * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust asm goto. * gcc.dg/pr110079.c: New test. --- gcc/bb-reorder.cc | 3 ++- gcc/testsuite/gcc.dg/pr110079.c | 43 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/pr110079.c (limited to 'gcc') diff --git a/gcc/bb-reorder.cc b/gcc/bb-reorder.cc index 3137f88..7998c0a 100644 --- a/gcc/bb-reorder.cc +++ b/gcc/bb-reorder.cc @@ -2266,7 +2266,8 @@ fix_crossing_unconditional_branches (void) /* Make sure the jump is not already an indirect or table jump. */ if (!computed_jump_p (last_insn) - && !tablejump_p (last_insn, NULL, NULL)) + && !tablejump_p (last_insn, NULL, NULL) + && asm_noperands (PATTERN (last_insn)) < 0) { /* We have found a "crossing" unconditional branch. Now we must convert it to an indirect jump. First create diff --git a/gcc/testsuite/gcc.dg/pr110079.c b/gcc/testsuite/gcc.dg/pr110079.c new file mode 100644 index 0000000..1682f9c --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr110079.c @@ -0,0 +1,43 @@ +/* PR rtl-optimization/110079 */ +/* { dg-do compile { target lra } } */ +/* { dg-options "-O2" } */ +/* { dg-additional-options "-freorder-blocks-and-partition" { target freorder } } */ + +int a; +__attribute__((cold)) int bar (char *); +__attribute__((hot)) int baz (char *); + +void +foo (void) +{ +l1: + while (a) + ; + bar (""); + asm goto ("" : : : : l2); + asm (""); +l2: + goto l1; +} + +void +qux (void) +{ + asm goto ("" : : : : l1); + bar (""); + goto l1; +l1: + baz (""); +} + +void +corge (void) +{ + asm goto ("" : : : : l1); + baz (""); +l2: + return; +l1: + bar (""); + goto l2; +} -- cgit v1.1 From 77772f8a3da8ea30066d2201f8148714a8e89da5 Mon Sep 17 00:00:00 2001 From: Nathaniel Shead Date: Tue, 5 Mar 2024 15:17:09 +1100 Subject: c++: Stream DECL_CONTEXT for template template parms [PR98881] When streaming in a nested template-template parameter as in the attached testcase, we end up reaching the containing template-template parameter in 'tpl_parms_fini'. We should not set the DECL_CONTEXT to this (nested) template-template parameter, as it should already be the struct that the outer template-template parameter is declared on. The precise logic for what DECL_CONTEXT should be for a template template parameter in various situations seems rather obscure. Rather than trying to determine the assumptions that need to hold, it seems simpler to just always re-stream the DECL_CONTEXT as needed for now. PR c++/98881 gcc/cp/ChangeLog: * module.cc (trees_out::tpl_parms_fini): Stream out DECL_CONTEXT for template template parameters. (trees_in::tpl_parms_fini): Read it. gcc/testsuite/ChangeLog: * g++.dg/modules/tpl-tpl-parm-3.h: New test. * g++.dg/modules/tpl-tpl-parm-3_a.H: New test. * g++.dg/modules/tpl-tpl-parm-3_b.C: New test. * g++.dg/modules/tpl-tpl-parm-3_c.C: New test. Signed-off-by: Nathaniel Shead Reviewed-by: Patrick Palka Reviewed-by: Jason Merrill --- gcc/cp/module.cc | 41 ++++++------------------- gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3.h | 12 ++++++++ gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3_a.H | 5 +++ gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3_b.C | 5 +++ gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3_c.C | 15 +++++++++ 5 files changed, 47 insertions(+), 31 deletions(-) create mode 100644 gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3.h create mode 100644 gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3_a.H create mode 100644 gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3_b.C create mode 100644 gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3_c.C (limited to 'gcc') diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc index 80b63a7..f7e8b35 100644 --- a/gcc/cp/module.cc +++ b/gcc/cp/module.cc @@ -10126,23 +10126,12 @@ trees_out::tpl_parms_fini (tree tmpl, unsigned tpl_levels) tree dflt = TREE_PURPOSE (parm); tree_node (dflt); - if (streaming_p ()) - { - tree decl = TREE_VALUE (parm); - if (TREE_CODE (decl) == TEMPLATE_DECL) - { - tree ctx = DECL_CONTEXT (decl); - tree inner = DECL_TEMPLATE_RESULT (decl); - tree tpi = (TREE_CODE (inner) == TYPE_DECL - ? TEMPLATE_TYPE_PARM_INDEX (TREE_TYPE (decl)) - : DECL_INITIAL (inner)); - bool original = (TEMPLATE_PARM_LEVEL (tpi) - == TEMPLATE_PARM_ORIG_LEVEL (tpi)); - /* Original template template parms have a context - of their owning template. Reduced ones do not. */ - gcc_checking_assert (original ? ctx == tmpl : !ctx); - } - } + /* Template template parameters need a context of their owning + template. This is quite tricky to infer correctly on stream-in + (see PR c++/98881) so we'll just provide it directly. */ + tree decl = TREE_VALUE (parm); + if (TREE_CODE (decl) == TEMPLATE_DECL) + tree_node (DECL_CONTEXT (decl)); } } } @@ -10160,24 +10149,14 @@ trees_in::tpl_parms_fini (tree tmpl, unsigned tpl_levels) { tree parm = TREE_VEC_ELT (vec, ix); tree dflt = tree_node (); - if (get_overrun ()) - return false; TREE_PURPOSE (parm) = dflt; tree decl = TREE_VALUE (parm); if (TREE_CODE (decl) == TEMPLATE_DECL) - { - tree inner = DECL_TEMPLATE_RESULT (decl); - tree tpi = (TREE_CODE (inner) == TYPE_DECL - ? TEMPLATE_TYPE_PARM_INDEX (TREE_TYPE (decl)) - : DECL_INITIAL (inner)); - bool original = (TEMPLATE_PARM_LEVEL (tpi) - == TEMPLATE_PARM_ORIG_LEVEL (tpi)); - /* Original template template parms have a context - of their owning template. Reduced ones do not. */ - if (original) - DECL_CONTEXT (decl) = tmpl; - } + DECL_CONTEXT (decl) = tree_node (); + + if (get_overrun ()) + return false; } } return true; diff --git a/gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3.h b/gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3.h new file mode 100644 index 0000000..b0dcf35 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/tpl-tpl-parm-3.h @@ -0,0 +1,12 @@ +// PR c++/98881 + +template struct X {}; + +template