From c2962684e393007d8de59d37b8ac57b0b4843808 Mon Sep 17 00:00:00 2001 From: Jeff Law Date: Sun, 4 May 2025 11:05:44 -0600 Subject: [RISC-V] Adjust rvv tests after recent jump threading change Richi's jump threading patch is resulting in new jump threading opportunities triggering in various vsetvl related tests. When those new threading opportunities are realized on vector code we usually end up with a different number of vsetvls due to the inherent block copying. At first I was adjusting cases to work with the new jump threads, then realized we could easily end up back here if we change the threading heuristics and such. So I just made these tests disable jump threading. I didn't do it pervasively, just for those that have been affected. gcc/testsuite * gcc.target/riscv/rvv/vsetvl/avl_prop-2.c: Disable jump threading and adjust number of expected vsetvls as needed. * gcc.target/riscv/rvv/vsetvl/avl_single-56.c: Likewise. * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Likewise. * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Likewise. * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Likewise. --- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c | 4 ++-- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c | 6 +++--- 5 files changed, 8 insertions(+), 8 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c index 0379429..edb12a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-thread-jumps" } */ int d0, sj, v0, rp, zi; @@ -38,4 +38,4 @@ ka: goto ka; } -/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*1} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*1} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c index 5db1a40..3d3c5d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c index 3f22fc8..013d32c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c index 64666d3..aef8325 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c index 07a64b4..fa4328f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" @@ -50,5 +50,5 @@ void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m, size_t } } -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -- cgit v1.1