From c1d40097cbfefceed04bbb3d3c9e14dcf7b27403 Mon Sep 17 00:00:00 2001
From: Jakub Jelinek <jakub@redhat.com>
Date: Wed, 25 Apr 2012 21:40:31 +0200
Subject: re PR target/53110 (GCC-4.7 generates stupid x86_64 asm)

	PR target/53110
	* config/i386/i386.md (and<mode>3): For andq $0xffffffff, reg
	instead expand it as zero extension.

From-SVN: r186839
---
 gcc/ChangeLog           |  6 ++++++
 gcc/config/i386/i386.md | 12 +++++++++++-
 2 files changed, 17 insertions(+), 1 deletion(-)

(limited to 'gcc')

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 820ba1b..a93d3cd 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2012-04-25  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/53110
+	* config/i386/i386.md (and<mode>3): For andq $0xffffffff, reg
+	instead expand it as zero extension.
+
 2012-04-25  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR debug/52857
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 0b2fe55..60439f9 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -7694,7 +7694,17 @@
 	(and:SWIM (match_operand:SWIM 1 "nonimmediate_operand")
 		  (match_operand:SWIM 2 "<general_szext_operand>")))]
   ""
-  "ix86_expand_binary_operator (AND, <MODE>mode, operands); DONE;")
+{
+  if (<MODE>mode == DImode
+      && GET_CODE (operands[2]) == CONST_INT
+      && INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff
+      && REG_P (operands[1]))
+    emit_insn (gen_zero_extendsidi2 (operands[0],
+				     gen_lowpart (SImode, operands[1])));
+  else
+    ix86_expand_binary_operator (AND, <MODE>mode, operands);
+  DONE;
+})
 
 (define_insn "*anddi_1"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
-- 
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