From b8a55285ffabec4803d92012cc42a3e1729b802f Mon Sep 17 00:00:00 2001 From: Andrew Pinski Date: Mon, 8 Nov 2004 04:42:36 +0000 Subject: re PR target/18269 (-m64 -fPIC does not work on ppc-darwin) 2004-11-07 Andrew Pinski PR target/18269 * config/darwin.c (machopic_indirect_data_reference): Call gen_macho_high and gen_macho_low instead of checking the mode and calling gen_macho_high_di directly. * config/rs6000/rs6000.c (rs6000_emit_move): Likewise. * config/rs6000/rs6000.md: Move most of TARGET_MACHO expand/insns to darwin.md. (movdf_low, movsf_low, movsf_low_st, movsi_low, macho_correct_pic, load_macho_picbase, macho_low, macho_high): Removed. (builtin_setjmp_receiver): Call gen_macho_high and gen_macho_low instead of checking the mode and calling gen_macho_high_di directly. * config/rs6000/darwin.md (load_macho_picbase_di): Use the MD constant. (movdf_low_si, movsf_low_si, movsf_low_st_si, movsi_low_st): Moved from rs6000.md. (macho_high): New expander. (macho_high_si): Renamed version of macho_high from rs6000.md. (macho_low): New expander. (macho_low_si): Renamed version of macho_low from rs6000.md. (load_macho_picbase): New expander. (load_macho_picbase_si): Renamed version of load_macho_picbase from rs6000.md. (macho_correct_pic): New expander. (macho_correct_pic_si): Renamed version of macho_correct_pic from rs6000.md. From-SVN: r90257 --- gcc/ChangeLog | 28 +++++++ gcc/config/darwin.c | 12 +-- gcc/config/rs6000/darwin.md | 180 +++++++++++++++++++++++++++++++++++++++++++- gcc/config/rs6000/rs6000.c | 12 +-- gcc/config/rs6000/rs6000.md | 123 +----------------------------- 5 files changed, 214 insertions(+), 141 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d39640f..a4965d92 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,31 @@ +2004-11-07 Andrew Pinski + + PR target/18269 + * config/darwin.c (machopic_indirect_data_reference): + Call gen_macho_high and gen_macho_low instead of + checking the mode and calling gen_macho_high_di directly. + * config/rs6000/rs6000.c (rs6000_emit_move): Likewise. + * config/rs6000/rs6000.md: Move most of TARGET_MACHO expand/insns + to darwin.md. + (movdf_low, movsf_low, movsf_low_st, movsi_low, macho_correct_pic, + load_macho_picbase, macho_low, macho_high): Removed. + (builtin_setjmp_receiver): Call gen_macho_high and + gen_macho_low instead of checking the mode and calling + gen_macho_high_di directly. + * config/rs6000/darwin.md (load_macho_picbase_di): Use the MD constant. + (movdf_low_si, movsf_low_si, movsf_low_st_si, movsi_low_st): + Moved from rs6000.md. + (macho_high): New expander. + (macho_high_si): Renamed version of macho_high from rs6000.md. + (macho_low): New expander. + (macho_low_si): Renamed version of macho_low from rs6000.md. + (load_macho_picbase): New expander. + (load_macho_picbase_si): Renamed version of load_macho_picbase + from rs6000.md. + (macho_correct_pic): New expander. + (macho_correct_pic_si): Renamed version of macho_correct_pic + from rs6000.md. + 2004-11-07 Joseph S. Myers * c-decl.c (finish_struct): Use complete sentences for diagnostic diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c index 73581f7..e01b383 100644 --- a/gcc/config/darwin.c +++ b/gcc/config/darwin.c @@ -412,12 +412,8 @@ machopic_indirect_data_reference (rtx orig, rtx reg) if (defined && MACHO_DYNAMIC_NO_PIC_P) { #if defined (TARGET_TOC) - emit_insn (GET_MODE (orig) == DImode - ? gen_macho_high_di (reg, orig) - : gen_macho_high (reg, orig)); - emit_insn (GET_MODE (orig) == DImode - ? gen_macho_low_di (reg, reg, orig) - : gen_macho_low (reg, reg, orig)); + emit_insn (gen_macho_high (reg, orig)); + emit_insn (gen_macho_low (reg, reg, orig)); #else /* some other cpu -- writeme! */ abort (); @@ -613,9 +609,7 @@ machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) rtx asym = XEXP (orig, 0); rtx mem; - emit_insn (mode == DImode - ? gen_macho_high_di (temp_reg, asym) - : gen_macho_high (temp_reg, asym)); + emit_insn (gen_macho_high (temp_reg, asym)); mem = gen_const_mem (GET_MODE (orig), gen_rtx_LO_SUM (Pmode, temp_reg, asym)); emit_insn (gen_rtx_SET (VOIDmode, reg, mem)); diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index f1a585a..d77555d 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -27,6 +27,49 @@ Boston, MA 02111-1307, USA. */ "{cau|addis} %0,%1,ha16(%2)" [(set_attr "length" "4")]) +(define_insn "movdf_low_si" + [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") + (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") + (match_operand 2 "" ""))))] + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" + "* +{ + switch (which_alternative) + { + case 0: + return \"lfd %0,lo16(%2)(%1)\"; + case 1: + { + rtx operands2[4]; + operands2[0] = operands[0]; + operands2[1] = operands[1]; + operands2[2] = operands[2]; + if (TARGET_POWERPC64 && TARGET_32BIT) + /* Note, old assemblers didn't support relocation here. */ + return \"ld %0,lo16(%2)(%1)\"; + else + { + operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); + output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); +#if TARGET_MACHO + if (MACHO_DYNAMIC_NO_PIC_P) + output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands); + else + /* We cannot rely on ha16(low half)==ha16(high half), alas, + although in practice it almost always is. */ + output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); +#endif + return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); + } + } + default: + abort(); + } +}" + [(set_attr "type" "load") + (set_attr "length" "4,12")]) + + (define_insn "movdf_low_di" [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") @@ -69,6 +112,15 @@ Boston, MA 02111-1307, USA. */ [(set_attr "type" "load") (set_attr "length" "4,12")]) +(define_insn "movdf_low_st_si" + [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand 2 "" ""))) + (match_operand:DF 0 "gpc_reg_operand" "f"))] + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" + "stfd %0,lo16(%2)(%1)" + [(set_attr "type" "store") + (set_attr "length" "4")]) + (define_insn "movdf_low_st_di" [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") (match_operand 2 "" ""))) @@ -78,6 +130,17 @@ Boston, MA 02111-1307, USA. */ [(set_attr "type" "store") (set_attr "length" "4")]) +(define_insn "movsf_low_si" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") + (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") + (match_operand 2 "" ""))))] + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" + "@ + lfs %0,lo16(%2)(%1) + {l|lwz} %0,lo16(%2)(%1)" + [(set_attr "type" "load") + (set_attr "length" "4")]) + (define_insn "movsf_low_di" [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") @@ -89,6 +152,17 @@ Boston, MA 02111-1307, USA. */ [(set_attr "type" "load") (set_attr "length" "4")]) +(define_insn "movsf_low_st_si" + [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") + (match_operand 2 "" ""))) + (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" + "@ + stfs %0,lo16(%2)(%1) + {st|stw} %0,lo16(%2)(%1)" + [(set_attr "type" "store") + (set_attr "length" "4")]) + (define_insn "movsf_low_st_di" [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b") (match_operand 2 "" ""))) @@ -110,6 +184,15 @@ Boston, MA 02111-1307, USA. */ [(set_attr "type" "load") (set_attr "length" "4")]) +(define_insn "movsi_low_st" + [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand 2 "" ""))) + (match_operand:SI 0 "gpc_reg_operand" "r"))] + "TARGET_MACHO && ! TARGET_64BIT" + "{st|stw} %0,lo16(%2)(%1)" + [(set_attr "type" "store") + (set_attr "length" "4")]) + (define_insn "movdi_low_st" [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") (match_operand 2 "" ""))) @@ -119,12 +202,56 @@ Boston, MA 02111-1307, USA. */ [(set_attr "type" "store") (set_attr "length" "4")]) +;; Mach-O PIC trickery. +(define_expand "macho_high" + [(set (match_operand 0 "" "") + (high (match_operand 1 "" "")))] + "TARGET_MACHO" +{ + if (TARGET_64BIT) + emit_insn (gen_macho_high_di (operands[0], operands[1])); + else + emit_insn (gen_macho_high_si (operands[0], operands[1])); + + DONE; +}) + +(define_insn "macho_high_si" + [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") + (high:SI (match_operand 1 "" "")))] + "TARGET_MACHO && ! TARGET_64BIT" + "{liu|lis} %0,ha16(%1)") + + (define_insn "macho_high_di" [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r") (high:DI (match_operand 1 "" "")))] "TARGET_MACHO && TARGET_64BIT" "{liu|lis} %0,ha16(%1)") +(define_expand "macho_low" + [(set (match_operand 0 "" "") + (lo_sum (match_operand 1 "" "") + (match_operand 2 "" "")))] + "TARGET_MACHO" +{ + if (TARGET_64BIT) + emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2])); + else + emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2])); + + DONE; +}) + +(define_insn "macho_low_si" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") + (match_operand 2 "" "")))] + "TARGET_MACHO && ! TARGET_64BIT" + "@ + {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} + {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") + (define_insn "macho_low_di" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r") @@ -145,14 +272,65 @@ Boston, MA 02111-1307, USA. */ (match_dup 2))] "") +(define_expand "load_macho_picbase" + [(set (match_operand 0 "" "") + (unspec [(match_operand 1 "" "")] + UNSPEC_LD_MPIC))] + "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" +{ + if (TARGET_32BIT) + emit_insn (gen_load_macho_picbase_si (operands[0], operands[1])); + else + emit_insn (gen_load_macho_picbase_di (operands[0], operands[1])); + + DONE; +}) + +(define_insn "load_macho_picbase_si" + [(set (match_operand:SI 0 "register_operand" "=l") + (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] + UNSPEC_LD_MPIC))] + "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" + "bcl 20,31,%1\\n%1:" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + (define_insn "load_macho_picbase_di" [(set (match_operand:DI 0 "register_operand" "=l") - (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")] 15))] + (unspec:DI [(match_operand:DI 1 "immediate_operand" "s")] UNSPEC_LD_MPIC))] "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT" "bcl 20,31,%1\\n%1:" [(set_attr "type" "branch") (set_attr "length" "4")]) +(define_expand "macho_correct_pic" + [(set (match_operand 0 "" "") + (plus (match_operand 1 "" "") + (unspec [(match_operand 2 "" "") + (match_operand 3 "" "")] + UNSPEC_MPIC_CORRECT)))] + "DEFAULT_ABI == ABI_DARWIN" +{ + if (TARGET_32BIT) + emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2], + operands[3])); + else + emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2], + operands[3])); + + DONE; +}) + +(define_insn "macho_correct_pic_si" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (unspec:SI [(match_operand:SI 2 "immediate_operand" "s") + (match_operand:SI 3 "immediate_operand" "s")] + UNSPEC_MPIC_CORRECT)))] + "DEFAULT_ABI == ABI_DARWIN" + "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)" + [(set_attr "length" "8")]) + (define_insn "macho_correct_pic_di" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (plus:DI (match_operand:DI 1 "gpc_reg_operand" "r") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index fffdf0c..abd3473 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4428,16 +4428,8 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) return; } #endif - if (mode == DImode) - { - emit_insn (gen_macho_high_di (target, operands[1])); - emit_insn (gen_macho_low_di (operands[0], target, operands[1])); - } - else - { - emit_insn (gen_macho_high (target, operands[1])); - emit_insn (gen_macho_low (operands[0], target, operands[1])); - } + emit_insn (gen_macho_high (target, operands[1])); + emit_insn (gen_macho_low (operands[0], target, operands[1])); return; } diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 37f5883..79a9ad15 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7660,21 +7660,6 @@ {cal|la} %0,%2@l(%1) {ai|addic} %0,%1,%K2") -;; Mach-O PIC trickery. -(define_insn "macho_high" - [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") - (high:SI (match_operand 1 "" "")))] - "TARGET_MACHO && ! TARGET_64BIT" - "{liu|lis} %0,ha16(%1)") - -(define_insn "macho_low" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") - (match_operand 2 "" "")))] - "TARGET_MACHO && ! TARGET_64BIT" - "@ - {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} - {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") ;; Set up a register with a value from the GOT table @@ -7747,88 +7732,6 @@ [(set_attr "type" "load") (set_attr "length" "4")]) -(define_insn "movsi_low_st" - [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand 2 "" ""))) - (match_operand:SI 0 "gpc_reg_operand" "r"))] - "TARGET_MACHO && ! TARGET_64BIT" - "{st|stw} %0,lo16(%2)(%1)" - [(set_attr "type" "store") - (set_attr "length" "4")]) - -(define_insn "movdf_low" - [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") - (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") - (match_operand 2 "" ""))))] - "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" - "* -{ - switch (which_alternative) - { - case 0: - return \"lfd %0,lo16(%2)(%1)\"; - case 1: - { - rtx operands2[4]; - operands2[0] = operands[0]; - operands2[1] = operands[1]; - operands2[2] = operands[2]; - if (TARGET_POWERPC64 && TARGET_32BIT) - /* Note, old assemblers didn't support relocation here. */ - return \"ld %0,lo16(%2)(%1)\"; - else - { - operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); - output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); -#if TARGET_MACHO - if (MACHO_DYNAMIC_NO_PIC_P) - output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands); - else - /* We cannot rely on ha16(low half)==ha16(high half), alas, - although in practice it almost always is. */ - output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); -#endif - return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); - } - } - default: - abort(); - } -}" - [(set_attr "type" "load") - (set_attr "length" "4,12")]) - -(define_insn "movdf_low_st" - [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") - (match_operand 2 "" ""))) - (match_operand:DF 0 "gpc_reg_operand" "f"))] - "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" - "stfd %0,lo16(%2)(%1)" - [(set_attr "type" "store") - (set_attr "length" "4")]) - -(define_insn "movsf_low" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") - (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") - (match_operand 2 "" ""))))] - "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" - "@ - lfs %0,lo16(%2)(%1) - {l|lwz} %0,lo16(%2)(%1)" - [(set_attr "type" "load") - (set_attr "length" "4")]) - -(define_insn "movsf_low_st" - [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") - (match_operand 2 "" ""))) - (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] - "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" - "@ - stfs %0,lo16(%2)(%1) - {st|stw} %0,lo16(%2)(%1)" - [(set_attr "type" "store") - (set_attr "length" "4")]) - (define_insn "*movsi_internal1" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] @@ -10168,24 +10071,6 @@ "{l|lwz} %0,%2-%3(%1)" [(set_attr "type" "load")]) -(define_insn "load_macho_picbase" - [(set (match_operand:SI 0 "register_operand" "=l") - (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] - UNSPEC_LD_MPIC))] - "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" - "bcl 20,31,%1\\n%1:" - [(set_attr "type" "branch") - (set_attr "length" "4")]) - -(define_insn "macho_correct_pic" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") - (unspec:SI [(match_operand:SI 2 "immediate_operand" "s") - (match_operand:SI 3 "immediate_operand" "s")] - UNSPEC_MPIC_CORRECT)))] - "DEFAULT_ABI == ABI_DARWIN" - "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)" - [(set_attr "length" "8")]) ;; If the TOC is shared over a translation unit, as happens with all ;; the kinds of PIC that we support, we need to restore the TOC @@ -10212,12 +10097,8 @@ CODE_LABEL_NUMBER (operands[0])); tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); - emit_insn (TARGET_64BIT - ? gen_load_macho_picbase_di (picreg, tmplabrtx) - : gen_load_macho_picbase (picreg, tmplabrtx)); - emit_insn (TARGET_64BIT - ? gen_macho_correct_pic_di (picreg, picreg, picrtx, tmplabrtx) - : gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); + emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); + emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); } else #endif -- cgit v1.1