From aa5409e7ade24c9972a5402c131d866ccba84ff4 Mon Sep 17 00:00:00 2001 From: Adam Nemet Date: Fri, 26 Sep 2008 23:38:20 +0000 Subject: mips.h (ISA_HAS_DMUL3, [...]): Change them to yield false with MIPS16. * config/mips/mips.h (ISA_HAS_DMUL3, ISA_HAS_BADDU, ISA_HAS_BBIT, ISA_HAS_CINS, ISA_HAS_EXTS, ISA_HAS_SEQ_SNE, ISA_HAS_POP): Change them to yield false with MIPS16. From-SVN: r140714 --- gcc/ChangeLog | 6 ++++++ gcc/config/mips/mips.h | 16 +++++++++------- 2 files changed, 15 insertions(+), 7 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 740a943..456daf8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2008-09-26 Adam Nemet + + * config/mips/mips.h (ISA_HAS_DMUL3, ISA_HAS_BADDU, ISA_HAS_BBIT, + ISA_HAS_CINS, ISA_HAS_EXTS, ISA_HAS_SEQ_SNE, ISA_HAS_POP): Change + them to yield false with MIPS16. + 2008-09-26 Jakub Jelinek PR middle-end/37275 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 55e240e..dc390df 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -783,7 +783,9 @@ enum mips_code_readable_setting { && !TARGET_MIPS16) /* ISA has a three-operand multiplication instruction. */ -#define ISA_HAS_DMUL3 (TARGET_64BIT && TARGET_OCTEON) +#define ISA_HAS_DMUL3 (TARGET_64BIT \ + && TARGET_OCTEON \ + && !TARGET_MIPS16) /* ISA has the floating-point conditional move instructions introduced in mips4. */ @@ -1011,22 +1013,22 @@ enum mips_code_readable_setting { : ISA_HAS_LL_SC) /* ISA includes the baddu instruction. */ -#define ISA_HAS_BADDU TARGET_OCTEON +#define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16) /* ISA includes the bbit* instructions. */ -#define ISA_HAS_BBIT TARGET_OCTEON +#define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16) /* ISA includes the cins instruction. */ -#define ISA_HAS_CINS TARGET_OCTEON +#define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16) /* ISA includes the exts instruction. */ -#define ISA_HAS_EXTS TARGET_OCTEON +#define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16) /* ISA includes the seq and sne instructions. */ -#define ISA_HAS_SEQ_SNE TARGET_OCTEON +#define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16) /* ISA includes the pop instruction. */ -#define ISA_HAS_POP TARGET_OCTEON +#define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) /* The CACHE instruction is available in non-MIPS16 code. */ #define TARGET_CACHE_BUILTIN (mips_isa >= 3) -- cgit v1.1