From a0d1de846b992a626f8b1e9b42cc32de8f069e04 Mon Sep 17 00:00:00 2001 From: Richard Biener Date: Thu, 27 Mar 2025 13:17:40 +0100 Subject: target/119010 - fixup Zen4/Zen5 fp<->int convert reservations They were using ssecvt instead of sseicvt, I've also added handling for sseicvt2 which was introduced without fixing up automata, and the relevant instruction uses DFmode. IMO this is a quite messy area that could need TLC in the machine description itself. PR target/119010 * config/i386/zn4zn5.md (znver4_sse_icvt): Use sseicvt. (znver4_sse_icvt_store): Likewise. (znver5_sse_icvt_store): Likewise. (znver4_sse_icvt2): New. --- gcc/config/i386/zn4zn5.md | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/config/i386/zn4zn5.md b/gcc/config/i386/zn4zn5.md index e89d0f4..6720fda 100644 --- a/gcc/config/i386/zn4zn5.md +++ b/gcc/config/i386/zn4zn5.md @@ -1263,21 +1263,28 @@ (define_insn_reservation "znver4_sse_icvt" 3 (and (eq_attr "cpu" "znver4,znver5") - (and (eq_attr "type" "ssecvt") + (and (eq_attr "type" "sseicvt") (and (eq_attr "mode" "SI") (eq_attr "memory" "none")))) "znver4-direct,znver4-fpu2|znver4-fpu3") +(define_insn_reservation "znver4_sse_icvt2" 3 + (and (eq_attr "cpu" "znver4,znver5") + (and (eq_attr "type" "sseicvt2") + (and (eq_attr "mode" "DF") + (eq_attr "memory" "none")))) + "znver4-direct,znver4-fpu2|znver4-fpu3") + (define_insn_reservation "znver4_sse_icvt_store" 4 (and (eq_attr "cpu" "znver4") - (and (eq_attr "type" "ssecvt") + (and (eq_attr "type" "sseicvt") (and (eq_attr "mode" "SI") (eq_attr "memory" "store")))) "znver4-double,znver4-fpu2|znver4-fpu3,znver4-fp-store") (define_insn_reservation "znver5_sse_icvt_store" 4 (and (eq_attr "cpu" "znver5") - (and (eq_attr "type" "ssecvt") + (and (eq_attr "type" "sseicvt") (and (eq_attr "mode" "SI") (eq_attr "memory" "store")))) "znver4-double,znver4-fpu2|znver4-fpu3,znver5-fp-store256") -- cgit v1.1