From 9df4edf0af74e867df8ae6422143dc5ed4eb1c10 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Thu, 28 Aug 2025 21:51:02 +0800 Subject: RISC-V: Fix extension subset check in riscv_can_inline_p The extension subset check logic in riscv_ext_is_subset was incorrectly inverted, causing functions with more extensions to be incorrectly rejected from being inlined into functions with fewer extensions. This patch fixes the logic to correctly check if the callee's required extensions are a subset of the caller's extensions. The corrected logic now properly allows inlining when the caller has all the extensions that the callee requires. gcc/ * common/config/riscv/riscv-common.cc (riscv_ext_is_subset): Fix inverted logic in extension subset check. gcc/testsuite/ * gcc.target/riscv/can_inline_p_test-01.c: New test. * gcc.target/riscv/can_inline_p_test-02.c: New test. * gcc.target/riscv/can_inline_p_test-03.c: New test. * gcc.target/riscv/can_inline_p_test-04.c: New test. * gcc.target/riscv/riscv_vector.h: New header wrapper for vector tests. --- gcc/common/config/riscv/riscv-common.cc | 2 +- .../gcc.target/riscv/can_inline_p_test-01.c | 18 ++++++++++++++++++ .../gcc.target/riscv/can_inline_p_test-02.c | 20 ++++++++++++++++++++ .../gcc.target/riscv/can_inline_p_test-03.c | 19 +++++++++++++++++++ .../gcc.target/riscv/can_inline_p_test-04.c | 20 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/riscv_vector.h | 11 +++++++++++ 6 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/can_inline_p_test-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/can_inline_p_test-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/can_inline_p_test-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/can_inline_p_test-04.c create mode 100644 gcc/testsuite/gcc.target/riscv/riscv_vector.h (limited to 'gcc') diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 6582c15..d24fca6 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1626,7 +1626,7 @@ riscv_ext_is_subset (struct cl_target_option *opts, for (const auto &riscv_ext_info : riscv_ext_infos) { const auto &ext_info = riscv_ext_info.second; - if (ext_info.check_opts (opts) && !ext_info.check_opts (subset)) + if (!ext_info.check_opts (opts) && ext_info.check_opts (subset)) return false; } return true; diff --git a/gcc/testsuite/gcc.target/riscv/can_inline_p_test-01.c b/gcc/testsuite/gcc.target/riscv/can_inline_p_test-01.c new file mode 100644 index 0000000..b637a4d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/can_inline_p_test-01.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-einline-details" } */ + +#include "riscv_vector.h" +int +__attribute__((target("arch=+v"))) +foo (){ + return __riscv_vsetvl_e8m8 (100); +} + + +int bar(){ + return foo(); +} + +/* { dg-final { scan-tree-dump {not inlinable: bar/\d+ -> foo/\d+, target specific option mismatch} "einline" } } */ +/* { dg-final { scan-tree-dump-not {\(inlined\)} "einline" } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Og" ""} } */ diff --git a/gcc/testsuite/gcc.target/riscv/can_inline_p_test-02.c b/gcc/testsuite/gcc.target/riscv/can_inline_p_test-02.c new file mode 100644 index 0000000..2babd5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/can_inline_p_test-02.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-einline-details" } */ + +#include "riscv_vector.h" +int +__attribute__((target("arch=+v"))) +foo (){ + return __riscv_vsetvl_e8m8 (100); +} + + +int +__attribute__((target("arch=+zve32x"))) +bar(){ + return foo(); +} + +/* { dg-final { scan-tree-dump {not inlinable: bar/\d+ -> foo/\d+, target specific option mismatch} "einline" } } */ +/* { dg-final { scan-tree-dump-not {\(inlined\)} "einline" } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Og" ""} } */ diff --git a/gcc/testsuite/gcc.target/riscv/can_inline_p_test-03.c b/gcc/testsuite/gcc.target/riscv/can_inline_p_test-03.c new file mode 100644 index 0000000..1892674 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/can_inline_p_test-03.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-einline-details" } */ + +#include "riscv_vector.h" +int +__attribute__((target("arch=+zve32x"))) +foo (){ + return __riscv_vsetvl_e8m8 (100); +} + + +int +__attribute__((target("arch=+v"))) +bar(){ + return foo(); +} + +/* { dg-final { scan-tree-dump {Inlining foo/\d+ into bar/\d+} "einline" } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Og" ""} } */ diff --git a/gcc/testsuite/gcc.target/riscv/can_inline_p_test-04.c b/gcc/testsuite/gcc.target/riscv/can_inline_p_test-04.c new file mode 100644 index 0000000..4dba784 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/can_inline_p_test-04.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-einline-details" } */ + +#include "riscv_vector.h" +int +__attribute__((target("arch=+v,+zvl256b"))) +foo (){ + return __riscv_vsetvl_e8m8 (100); +} + + +int +__attribute__((target("arch=+v"))) +bar(){ + return foo(); +} + +/* { dg-final { scan-tree-dump {not inlinable: bar/\d+ -> foo/\d+, target specific option mismatch} "einline" } } */ +/* { dg-final { scan-tree-dump-not {\(inlined\)} "einline" } } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Og" ""} } */ diff --git a/gcc/testsuite/gcc.target/riscv/riscv_vector.h b/gcc/testsuite/gcc.target/riscv/riscv_vector.h new file mode 100644 index 0000000..fbb4858f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/riscv_vector.h @@ -0,0 +1,11 @@ +/* Wrapper of riscv_vector.h, prevent riscv_vector.h including stdint.h from + C library, that might cause problem on testing RV32 related testcase when + we disable multilib. */ +#ifndef _RISCV_VECTOR_WRAP_H + +#define _GCC_WRAP_STDINT_H +#include "stdint-gcc.h" +#include_next +#define _RISCV_VECTOR_WRAP_H + +#endif -- cgit v1.1