From 97aafa9cbb68ffa23aa9f018cc5cb30648a72427 Mon Sep 17 00:00:00 2001 From: Juzhe-Zhong Date: Tue, 29 Aug 2023 14:48:32 +0800 Subject: vect test: Remove xfail for riscv We are planning to enable "vect" testsuite with scalable vector auto-vectorization. This case XPASS: XPASS: gcc.dg/vect/no-scevccp-outer-12.c scan-tree-dump-times vect "OUTER LOOP VECTORIZED." 1 like ARM SVE. gcc/testsuite/ChangeLog: * gcc.dg/vect/no-scevccp-outer-12.c: Add riscv xfail. --- gcc/testsuite/gcc.dg/vect/no-scevccp-outer-12.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-12.c b/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-12.c index e9ec4ca..c2d3031 100644 --- a/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-12.c +++ b/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-12.c @@ -47,4 +47,4 @@ int main (void) } /* Until we support multiple types in the inner loop */ -/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! aarch64*-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! { aarch64*-*-* riscv*-*-* } } } } } */ -- cgit v1.1