From 8fdfd0cfdb7ca6b083a2a6205c40f512ea4631a9 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Tue, 2 Feb 2021 13:28:55 +0000 Subject: aarch64: Reimplement vqmovun_high* intrinsics using builtins Another transition from inline asm to builtin. Only 3 intrinsics converted this time but they use the "+w" constraint in their inline asm so are more likely to generate redundant moves so benefit more from reimplementation. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (sqxtun2): Define builtin. * config/aarch64/aarch64-simd.md (aarch64_sqxtun2_le): Define. (aarch64_sqxtun2_be): Likewise. (aarch64_sqxtun2): Likewise. * config/aarch64/arm_neon.h (vqmovun_high_s16): Reimplement using builtin. (vqmovun_high_s32): Likewise. (vqmovun_high_s64): Likewise. * config/aarch64/iterators.md (UNSPEC_SQXTUN2): Define. gcc/testsuite/ChangeLog: * gcc.target/aarch64/narrow_high-intrinsics.c: Adjust sqxtun2 scan. --- gcc/config/aarch64/aarch64-simd-builtins.def | 4 +++ gcc/config/aarch64/aarch64-simd.md | 39 ++++++++++++++++++++++ gcc/config/aarch64/arm_neon.h | 21 ++---------- gcc/config/aarch64/iterators.md | 1 + .../gcc.target/aarch64/narrow_high-intrinsics.c | 2 +- 5 files changed, 48 insertions(+), 19 deletions(-) (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 92dc27e..2f50ecc 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -241,6 +241,10 @@ BUILTIN_VQW (TERNOPU, umlsl_hi, 0, NONE) BUILTIN_VSQN_HSDI (UNOPUS, sqmovun, 0, NONE) + + /* Implemented by aarch64_sqxtun2. */ + BUILTIN_VQN (BINOP_UUS, sqxtun2, 0, NONE) + /* Implemented by aarch64_qmovn. */ BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0, NONE) BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0, NONE) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 992c7b8..eea5c87 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4256,6 +4256,45 @@ } ) +(define_insn "aarch64_sqxtun2_le" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (match_operand: 1 "register_operand" "0") + (unspec: + [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN2)))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "sqxtun2\\t%0., %2." + [(set_attr "type" "neon_sat_shift_imm_narrow_q")] +) + +(define_insn "aarch64_sqxtun2_be" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (unspec: + [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN2) + (match_operand: 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "sqxtun2\\t%0., %2." + [(set_attr "type" "neon_sat_shift_imm_narrow_q")] +) + +(define_expand "aarch64_sqxtun2" + [(match_operand: 0 "register_operand") + (match_operand: 1 "register_operand") + (unspec: + [(match_operand:VQN 2 "register_operand")] UNSPEC_SQXTUN2)] + "TARGET_SIMD" + { + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_sqxtun2_be (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_aarch64_sqxtun2_le (operands[0], operands[1], + operands[2])); + DONE; + } +) + ;; q (define_insn "aarch64_s" diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index fa22330..e32f7ab 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -9105,36 +9105,21 @@ __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovun_high_s16 (uint8x8_t __a, int16x8_t __b) { - uint8x16_t __result = vcombine_u8 (__a, vcreate_u8 (__AARCH64_UINT64_C (0x0))); - __asm__ ("sqxtun2 %0.16b, %1.8h" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sqxtun2v8hi_uus (__a, __b); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovun_high_s32 (uint16x4_t __a, int32x4_t __b) { - uint16x8_t __result = vcombine_u16 (__a, vcreate_u16 (__AARCH64_UINT64_C (0x0))); - __asm__ ("sqxtun2 %0.8h, %1.4s" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sqxtun2v4si_uus (__a, __b); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vqmovun_high_s64 (uint32x2_t __a, int64x2_t __b) { - uint32x4_t __result = vcombine_u32 (__a, vcreate_u32 (__AARCH64_UINT64_C (0x0))); - __asm__ ("sqxtun2 %0.4s, %1.2d" - : "+w"(__result) - : "w"(__b) - : /* No clobbers */); - return __result; + return __builtin_aarch64_sqxtun2v2di_uus (__a, __b); } __extension__ extern __inline int16x4_t diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 51c7c15..fb6e228 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -522,6 +522,7 @@ UNSPEC_USQADD ; Used in aarch64-simd.md. UNSPEC_SUQADD ; Used in aarch64-simd.md. UNSPEC_SQXTUN ; Used in aarch64-simd.md. + UNSPEC_SQXTUN2 ; Used in aarch64-simd.md. UNSPEC_SQXTN ; Used in aarch64-simd.md. UNSPEC_UQXTN ; Used in aarch64-simd.md. UNSPEC_SSRA ; Used in aarch64-simd.md. diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_high-intrinsics.c b/gcc/testsuite/gcc.target/aarch64/narrow_high-intrinsics.c index 5abcadc..6d9e831 100644 --- a/gcc/testsuite/gcc.target/aarch64/narrow_high-intrinsics.c +++ b/gcc/testsuite/gcc.target/aarch64/narrow_high-intrinsics.c @@ -121,5 +121,5 @@ ONE (vmovn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64) /* { dg-final { scan-assembler-times "uqrshrn2\\tv" 3} } */ /* { dg-final { scan-assembler-times "uqxtn2\\tv" 3} } */ /* { dg-final { scan-assembler-times "sqxtn2\\tv" 3} } */ -/* { dg-final { scan-assembler-times "sqxtun2 v" 3} } */ +/* { dg-final { scan-assembler-times "sqxtun2\\tv" 3} } */ /* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} } */ -- cgit v1.1