From 8b08db1e9beee0cc515c84d62c369a060816fecc Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Wed, 18 Dec 2013 08:18:22 +0000 Subject: sse.md (*fma_fmadd_): Extend to support masking. * config/i386/sse.md (*fma_fmadd_): Extend to support masking. (*fma_fmsub_): Ditto. (*fma_fnmadd_): Ditto. (*fma_fnmsub_): Ditto. (*fma_fmaddsub_): Ditto. (*fma_fmsubadd_): Ditto. (avx512f_vternlog): Ditto. (avx512f_fixupimm): Ditto. (avx512f_sfixupimm): Ditto. (avx512f_vpermi2var3): Ditto. (avx512f_vpermt2var3): Ditto. (avx512f_fmaddsub__maskz): New. (avx512f_vternlog_maskz): Ditto. (avx512f_fixupimm_maskz): Ditto. (avx512f_sfixupimm_maskz): Ditto. (avx512f_vpermi2var3_maskz): Ditto. (avx512f_vpermt2var3_maskz): Ditto. (avx512f_expand_maskz): Ditto. * config/i386/subst.md (sd_maskz_name): Ditto. (sd_mask_op4): Ditto. (sd_mask_op5): Ditto. (sd_mask_codefor): Ditto. (sd_mask_mode512bit_condition): Ditto. (sd): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin Co-Authored-By: Sergey Lega From-SVN: r206081 --- gcc/ChangeLog | 37 +++++++++- gcc/config/i386/sse.md | 178 ++++++++++++++++++++++++++++++++++++----------- gcc/config/i386/subst.md | 17 +++++ 3 files changed, 191 insertions(+), 41 deletions(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8830abc..7bf07cc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,39 @@ -2013-11-13 Alexander Ivchenko +2013-12-18 Alexander Ivchenko + Maxim Kuznetsov + Sergey Lega + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md (*fma_fmadd_): Extend to support masking. + (*fma_fmsub_): Ditto. + (*fma_fnmadd_): Ditto. + (*fma_fnmsub_): Ditto. + (*fma_fmaddsub_): Ditto. + (*fma_fmsubadd_): Ditto. + (avx512f_vternlog): Ditto. + (avx512f_fixupimm): Ditto. + (avx512f_sfixupimm): Ditto. + (avx512f_vpermi2var3): Ditto. + (avx512f_vpermt2var3): Ditto. + (avx512f_fmaddsub__maskz): New. + (avx512f_vternlog_maskz): Ditto. + (avx512f_fixupimm_maskz): Ditto. + (avx512f_sfixupimm_maskz): Ditto. + (avx512f_vpermi2var3_maskz): Ditto. + (avx512f_vpermt2var3_maskz): Ditto. + (avx512f_expand_maskz): Ditto. + * config/i386/subst.md (sd_maskz_name): Ditto. + (sd_mask_op4): Ditto. + (sd_mask_op5): Ditto. + (sd_mask_codefor): Ditto. + (sd_mask_mode512bit_condition): Ditto. + (sd): Ditto. + +2013-12-18 Alexander Ivchenko Maxim Kuznetsov Sergey Lega Anna Tikhonova diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 46842d2..adedf44 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -2698,17 +2698,17 @@ (match_operand:FMAMODE 3 "nonimmediate_operand")))] "") -(define_insn "*fma_fmadd_" +(define_insn "fma_fmadd_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x") (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x")))] - "" + "" "@ - vfmadd132\t{%2, %3, %0|%0, %3, %2} - vfmadd213\t{%3, %2, %0|%0, %2, %3} - vfmadd231\t{%2, %1, %0|%0, %1, %2} + vfmadd132\t{%2, %3, %0|%0, %3, %2} + vfmadd213\t{%3, %2, %0|%0, %2, %3} + vfmadd231\t{%2, %1, %0|%0, %1, %2} vfmadd\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -2747,18 +2747,18 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "*fma_fmsub_" +(define_insn "fma_fmsub_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x") (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") (neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x"))))] - "" + "" "@ - vfmsub132\t{%2, %3, %0|%0, %3, %2} - vfmsub213\t{%3, %2, %0|%0, %2, %3} - vfmsub231\t{%2, %1, %0|%0, %1, %2} + vfmsub132\t{%2, %3, %0|%0, %3, %2} + vfmsub213\t{%3, %2, %0|%0, %2, %3} + vfmsub231\t{%2, %1, %0|%0, %1, %2} vfmsub\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -2799,18 +2799,18 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "*fma_fnmadd_" +(define_insn "fma_fnmadd_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (neg:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand" "%0, 0, v, x,x")) (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x")))] - "" + "" "@ - vfnmadd132\t{%2, %3, %0|%0, %3, %2} - vfnmadd213\t{%3, %2, %0|%0, %2, %3} - vfnmadd231\t{%2, %1, %0|%0, %1, %2} + vfnmadd132\t{%2, %3, %0|%0, %3, %2} + vfnmadd213\t{%3, %2, %0|%0, %2, %3} + vfnmadd231\t{%2, %1, %0|%0, %1, %2} vfnmadd\t{%3, %2, %1, %0|%0, %1, %2, %3} vfnmadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -2851,7 +2851,7 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "*fma_fnmsub_" +(define_insn "fma_fnmsub_" [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") (fma:FMAMODE (neg:FMAMODE @@ -2859,11 +2859,11 @@ (match_operand:FMAMODE 2 "nonimmediate_operand" "vm, v,vm, x,m") (neg:FMAMODE (match_operand:FMAMODE 3 "nonimmediate_operand" " v,vm, 0,xm,x"))))] - "" + "" "@ - vfnmsub132\t{%2, %3, %0|%0, %3, %2} - vfnmsub213\t{%3, %2, %0|%0, %2, %3} - vfnmsub231\t{%2, %1, %0|%0, %1, %2} + vfnmsub132\t{%2, %3, %0|%0, %3, %2} + vfnmsub213\t{%3, %2, %0|%0, %2, %3} + vfnmsub231\t{%2, %1, %0|%0, %1, %2} vfnmsub\t{%3, %2, %1, %0|%0, %1, %2, %3} vfnmsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -2926,18 +2926,32 @@ UNSPEC_FMADDSUB))] "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") -(define_insn "*fma_fmaddsub_" +(define_expand "avx512f_fmaddsub__maskz" + [(match_operand:VF_512 0 "register_operand") + (match_operand:VF_512 1 "nonimmediate_operand") + (match_operand:VF_512 2 "nonimmediate_operand") + (match_operand:VF_512 3 "nonimmediate_operand") + (match_operand: 4 "register_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_fma_fmaddsub__maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "fma_fmaddsub_" [(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x") (unspec:VF [(match_operand:VF 1 "nonimmediate_operand" "%0, 0, v, x,x") (match_operand:VF 2 "nonimmediate_operand" "vm, v,vm, x,m") (match_operand:VF 3 "nonimmediate_operand" " v,vm, 0,xm,x")] UNSPEC_FMADDSUB))] - "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F)" + "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && " "@ - vfmaddsub132\t{%2, %3, %0|%0, %3, %2} - vfmaddsub213\t{%3, %2, %0|%0, %2, %3} - vfmaddsub231\t{%2, %1, %0|%0, %1, %2} + vfmaddsub132\t{%2, %3, %0|%0, %3, %2} + vfmaddsub213\t{%3, %2, %0|%0, %2, %3} + vfmaddsub231\t{%2, %1, %0|%0, %1, %2} vfmaddsub\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmaddsub\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -2978,7 +2992,7 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) -(define_insn "*fma_fmsubadd_" +(define_insn "fma_fmsubadd_" [(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x") (unspec:VF [(match_operand:VF 1 "nonimmediate_operand" "%0, 0, v, x,x") @@ -2986,11 +3000,11 @@ (neg:VF (match_operand:VF 3 "nonimmediate_operand" " v,vm, 0,xm,x"))] UNSPEC_FMADDSUB))] - "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F)" + "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && " "@ - vfmsubadd132\t{%2, %3, %0|%0, %3, %2} - vfmsubadd213\t{%3, %2, %0|%0, %2, %3} - vfmsubadd231\t{%2, %1, %0|%0, %1, %2} + vfmsubadd132\t{%2, %3, %0|%0, %3, %2} + vfmsubadd213\t{%3, %2, %0|%0, %2, %3} + vfmsubadd231\t{%2, %1, %0|%0, %1, %2} vfmsubadd\t{%3, %2, %1, %0|%0, %1, %2, %3} vfmsubadd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f,fma4,fma4") @@ -6443,7 +6457,22 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vternlog" +(define_expand "avx512f_vternlog_maskz" + [(match_operand:VI48_512 0 "register_operand") + (match_operand:VI48_512 1 "register_operand") + (match_operand:VI48_512 2 "register_operand") + (match_operand:VI48_512 3 "nonimmediate_operand") + (match_operand:SI 4 "const_0_to_255_operand") + (match_operand: 5 "register_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_vternlog_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + operands[4], CONST0_RTX (mode), operands[5])); + DONE; +}) + +(define_insn "avx512f_vternlog" [(set (match_operand:VI48_512 0 "register_operand" "=v") (unspec:VI48_512 [(match_operand:VI48_512 1 "register_operand" "0") @@ -6452,7 +6481,7 @@ (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_VTERNLOG))] "TARGET_AVX512F" - "vpternlog\t{%4, %3, %2, %0|%0, %2, %3, %4}" + "vpternlog\t{%4, %3, %2, %0|%0, %2, %3, %4}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -6539,7 +6568,23 @@ DONE; }) -(define_insn "avx512f_fixupimm" + +(define_expand "avx512f_fixupimm_maskz" + [(match_operand:VF_512 0 "register_operand") + (match_operand:VF_512 1 "register_operand") + (match_operand:VF_512 2 "register_operand") + (match_operand: 3 "nonimmediate_operand") + (match_operand:SI 4 "const_0_to_255_operand") + (match_operand: 5 "register_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_fixupimm_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + operands[4], CONST0_RTX (mode), operands[5])); + DONE; +}) + +(define_insn "avx512f_fixupimm" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 [(match_operand:VF_512 1 "register_operand" "0") @@ -6548,7 +6593,7 @@ (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -6568,7 +6613,22 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_sfixupimm" +(define_expand "avx512f_sfixupimm_maskz" + [(match_operand:VF_128 0 "register_operand") + (match_operand:VF_128 1 "register_operand") + (match_operand:VF_128 2 "register_operand") + (match_operand: 3 "nonimmediate_operand") + (match_operand:SI 4 "const_0_to_255_operand") + (match_operand: 5 "register_operand")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_sfixupimm_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + operands[4], CONST0_RTX (mode), operands[5])); + DONE; +}) + +(define_insn "avx512f_sfixupimm" [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (unspec:VF_128 @@ -6580,7 +6640,7 @@ (match_dup 1) (const_int 1)))] "TARGET_AVX512F" - "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; + "vfixupimm\t{%4, %3, %2, %0|%0, %2, %3, %4}"; [(set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -13892,7 +13952,21 @@ (set_attr "prefix" "") (set_attr "mode" "")]) -(define_insn "avx512f_vpermi2var3" +(define_expand "avx512f_vpermi2var3_maskz" + [(match_operand:VI48F_512 0 "register_operand" "=v") + (match_operand:VI48F_512 1 "register_operand" "v") + (match_operand: 2 "register_operand" "0") + (match_operand:VI48F_512 3 "nonimmediate_operand" "vm") + (match_operand: 4 "register_operand" "k")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_vpermi2var3_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "avx512f_vpermi2var3" [(set (match_operand:VI48F_512 0 "register_operand" "=v") (unspec:VI48F_512 [(match_operand:VI48F_512 1 "register_operand" "v") @@ -13900,7 +13974,7 @@ (match_operand:VI48F_512 3 "nonimmediate_operand" "vm")] UNSPEC_VPERMI2))] "TARGET_AVX512F" - "vpermi2\t{%3, %1, %0|%0, %1, %3}" + "vpermi2\t{%3, %1, %0|%0, %1, %3}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -13921,7 +13995,21 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vpermt2var3" +(define_expand "avx512f_vpermt2var3_maskz" + [(match_operand:VI48F_512 0 "register_operand" "=v") + (match_operand: 1 "register_operand" "v") + (match_operand:VI48F_512 2 "register_operand" "0") + (match_operand:VI48F_512 3 "nonimmediate_operand" "vm") + (match_operand: 4 "register_operand" "k")] + "TARGET_AVX512F" +{ + emit_insn (gen_avx512f_vpermt2var3_maskz_1 ( + operands[0], operands[1], operands[2], operands[3], + CONST0_RTX (mode), operands[4])); + DONE; +}) + +(define_insn "avx512f_vpermt2var3" [(set (match_operand:VI48F_512 0 "register_operand" "=v") (unspec:VI48F_512 [(match_operand: 1 "register_operand" "v") @@ -13929,7 +14017,7 @@ (match_operand:VI48F_512 3 "nonimmediate_operand" "vm")] UNSPEC_VPERMT2))] "TARGET_AVX512F" - "vpermt2\t{%3, %1, %0|%0, %1, %3}" + "vpermt2\t{%3, %1, %0|%0, %1, %3}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -14938,6 +15026,16 @@ (set_attr "memory" "store") (set_attr "mode" "")]) +(define_expand "avx512f_expand_maskz" + [(set (match_operand:VI48F_512 0 "register_operand") + (unspec:VI48F_512 + [(match_operand:VI48F_512 1 "nonimmediate_operand") + (match_operand:VI48F_512 2 "vector_move_operand") + (match_operand: 3 "register_operand")] + UNSPEC_EXPAND))] + "TARGET_AVX512F" + "operands[2] = CONST0_RTX (mode);") + (define_insn "avx512f_expand_mask" [(set (match_operand:VI48F_512 0 "register_operand" "=v,v") (unspec:VI48F_512 diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index 0fdef6d..594dc43 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -70,3 +70,20 @@ (and:SUBST_S (match_dup 1) (match_operand:SUBST_S 3 "register_operand" "k")))]) + +(define_subst_attr "sd_maskz_name" "sd" "" "_maskz_1") +(define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4") +(define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5") +(define_subst_attr "sd_mask_codefor" "sd" "*" "") +(define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(GET_MODE_SIZE (GET_MODE (operands[0])) == 64)") + +(define_subst "sd" + [(set (match_operand:SUBST_V 0) + (match_operand:SUBST_V 1))] + "" + [(set (match_dup 0) + (vec_merge:SUBST_V + (match_dup 1) + (match_operand:SUBST_V 2 "const0_operand" "C") + (match_operand: 3 "register_operand" "k"))) +]) -- cgit v1.1