From 70707f6c75be10f35bc206e9d59fa88234d3b568 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 29 Jun 2005 11:22:06 -0700 Subject: * config/alpha/alpha.md (vec_shl_, vec_shr_): New. From-SVN: r101434 --- gcc/ChangeLog | 4 ++++ gcc/config/alpha/alpha.md | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9849127..9bf9bc2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2005-06-29 Richard Henderson + * config/alpha/alpha.md (vec_shl_, vec_shr_): New. + +2005-06-29 Richard Henderson + * tree-vect-transform.c (vect_min_worthwhile_factor): Declare. (vect_create_epilog_for_reduction): Don't use vec_shr if the operation is emulated. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 157e8ca..35cc320 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -6361,6 +6361,26 @@ "" "eqv %1,%2,%0" [(set_attr "type" "ilog")]) + +(define_expand "vec_shl_" + [(set (match_operand:VEC 0 "register_operand" "") + (ashift:DI (match_operand:VEC 1 "register_operand" "") + (match_operand:DI 2 "reg_or_6bit_operand" "")))] + "" +{ + operands[0] = gen_lowpart (DImode, operands[0]); + operands[1] = gen_lowpart (DImode, operands[1]); +}) + +(define_expand "vec_shr_" + [(set (match_operand:VEC 0 "register_operand" "") + (lshiftrt:DI (match_operand:VEC 1 "register_operand" "") + (match_operand:DI 2 "reg_or_6bit_operand" "")))] + "" +{ + operands[0] = gen_lowpart (DImode, operands[0]); + operands[1] = gen_lowpart (DImode, operands[1]); +}) ;; Bit field extract patterns which use ext[wlq][lh] -- cgit v1.1