From 6913111a953ed51a4ad232a53abecb08ed42c703 Mon Sep 17 00:00:00 2001 From: Andreas Krebbel Date: Tue, 2 Apr 2019 11:06:30 +0000 Subject: S/390: arch13: vector load byte reversed element and replicate gcc/ChangeLog: 2019-04-02 Andreas Krebbel ("*vec_splats_bswap_vec", "*vec_splats_bswap_elem"): New insn definition. * config/s390/vx-builtins.md (V_HW_HSD): Move to ... * config/s390/vector.md (V_HW_HSD): ... here. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel * gcc.target/s390/zvector/replicate-bswap-1.c: New test. * gcc.target/s390/zvector/replicate-bswap-2.c: New test. From-SVN: r270088 --- gcc/ChangeLog | 7 ++++++ gcc/config/s390/vector.md | 20 ++++++++++++++++ gcc/config/s390/vx-builtins.md | 1 - gcc/testsuite/ChangeLog | 5 ++++ .../gcc.target/s390/zvector/replicate-bswap-1.c | 28 ++++++++++++++++++++++ .../gcc.target/s390/zvector/replicate-bswap-2.c | 28 ++++++++++++++++++++++ 6 files changed, 88 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-1.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-2.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 782aed6..bf0b327 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2019-04-02 Andreas Krebbel + ("*vec_splats_bswap_vec", "*vec_splats_bswap_elem"): + New insn definition. + * config/s390/vx-builtins.md (V_HW_HSD): Move to ... + * config/s390/vector.md (V_HW_HSD): ... here. + +2019-04-02 Andreas Krebbel + * config/s390/vecintrin.h: Map vec_vster low-level builtins to vec_vler. * config/s390/vx-builtins.md ("*vec_insert_and_zero_bswap") ("*vec_set_bswap_elem", "*vec_set_bswap_vec") diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index f25c866..8f02af4 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -34,6 +34,7 @@ (define_mode_iterator V_HW_64 [V2DI V2DF]) (define_mode_iterator VT_HW_HSDT [V8HI V4SI V4SF V2DI V2DF V1TI V1TF TI TF]) +(define_mode_iterator V_HW_HSD [V8HI V4SI (V4SF "TARGET_VXE") V2DI V2DF]) ; Including TI for instructions that support it (va, vn, ...) (define_mode_iterator VT_HW [V16QI V8HI V4SI V2DI V2DF V1TI TI (V4SF "TARGET_VXE") (V1TF "TARGET_VXE")]) @@ -548,6 +549,25 @@ #" [(set_attr "op_type" "VRX,VRI,VRI,*")]) +; vlbrreph, vlbrrepf, vlbrrepg +(define_insn "*vec_splats_bswap_vec" + [(set (match_operand:V_HW_HSD 0 "register_operand" "=v") + (bswap:V_HW_HSD + (vec_duplicate:V_HW_HSD (match_operand: 1 "memory_operand" "R"))))] + "TARGET_VXE2" + "vlbrrep\t%v0,%1" + [(set_attr "op_type" "VRX")]) + +; Why do we need both? Shouldn't there be a canonical form? +; vlbrreph, vlbrrepf, vlbrrepg +(define_insn "*vec_splats_bswap_elem" + [(set (match_operand:V_HW_HSD 0 "register_operand" "=v") + (vec_duplicate:V_HW_HSD + (bswap: (match_operand: 1 "memory_operand" "R"))))] + "TARGET_VXE2" + "vlbrrep\t%v0,%1" + [(set_attr "op_type" "VRX")]) + ; A TFmode operand resides in FPR register pairs while V1TF is in a ; single vector register. (define_insn "*vec_tf_to_v1tf" diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 8d837c4..1595ffb 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -22,7 +22,6 @@ (define_mode_iterator V_HW_32_64 [V4SI V2DI V2DF (V4SF "TARGET_VXE")]) (define_mode_iterator VI_HW_SD [V4SI V2DI]) -(define_mode_iterator V_HW_HSD [V8HI V4SI (V4SF "TARGET_VXE") V2DI V2DF]) (define_mode_iterator V_HW_4 [V4SI V4SF]) ; Full size vector modes with more than one element which are directly supported in vector registers by the hardware. (define_mode_iterator VEC_HW [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e0fa053..dfd5f16 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-04-02 Andreas Krebbel + + * gcc.target/s390/zvector/replicate-bswap-1.c: New test. + * gcc.target/s390/zvector/replicate-bswap-2.c: New test. + 2019-04-02 Alexander Monakov PR testsuite/89916 diff --git a/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-1.c b/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-1.c new file mode 100644 index 0000000..adecdb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-1.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=arch13 -mzvector -fno-asynchronous-unwind-tables -dp" } */ + +#include + +vector signed short +vlbrreph (const signed short *a) +{ + return vec_revb (vec_splats (*a)); +} + +/* { dg-final { scan-assembler-times "vlbrreph.*\n\tvlbrreph.*vec_splats_bswap_vecv8hi" 1 } } */ + +vector signed int +vlbrrepf (const signed int *a) +{ + return vec_revb (vec_splats (*a)); +} + +/* { dg-final { scan-assembler-times "vlbrrepf.*\n\tvlbrrepf.*vec_splats_bswap_vecv4si" 1 } } */ + +vector signed long long +vlbrrepg (const signed long long *a) +{ + return vec_revb (vec_splats (*a)); +} + +/* { dg-final { scan-assembler-times "vlbrrepg.*\n\tvlbrrepg.*vec_splats_bswap_vecv2di" 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-2.c b/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-2.c new file mode 100644 index 0000000..426dd54 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/replicate-bswap-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mzarch -march=arch13 -mzvector -fno-asynchronous-unwind-tables -dp" } */ + +#include + +vector unsigned short +vlbrreph (const unsigned short *a) +{ + return vec_splats (__builtin_bswap16 (*a)); +} + +/* { dg-final { scan-assembler-times "vlbrreph.*\n\tvlbrreph.*vec_splats_bswap_elemv8hi" 1 } } */ + +vector unsigned int +vlbrrepf (const unsigned int *a) +{ + return vec_splats (__builtin_bswap32 (*a)); +} + +/* { dg-final { scan-assembler-times "vlbrrepf.*\n\tvlbrrepf.*vec_splats_bswap_elemv4si" 1 } } */ + +vector unsigned long long +vlbrrepg (const unsigned long long *a) +{ + return vec_splats ((unsigned long long)__builtin_bswap64 (*a)); +} + +/* { dg-final { scan-assembler-times "vlbrrepg.*\n\tvlbrrepg.*vec_splats_bswap_elemv2di" 1 } } */ -- cgit v1.1