From 57cfbfbab8ec2a2ca4fb060bf95e0d03a8df57f2 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 8 May 2018 11:42:15 +0000 Subject: Move C++ SVE tests to g++.target/aarch64/sve 2018-05-08 Richard Sandiford gcc/testsuite/ * g++.dg/other/sve_const_pred_1.C: Rename to... * g++.target/aarch64/sve/const_pred_1.C: ...this. Remove aarch64 target selectors and explicit -march options. * g++.dg/other/sve_const_pred_2.C: Rename to... * g++.target/aarch64/sve/const_pred_2.C: ...this and adjust likewise. * g++.dg/other/sve_const_pred_3.C: Rename to... * g++.target/aarch64/sve/const_pred_3.C: ...this and adjust likewise. * g++.dg/other/sve_const_pred_4.C: Rename to... * g++.target/aarch64/sve/const_pred_4.C: ...this and adjust likewise. * g++.dg/other/sve_tls_2.C: Rename to... * g++.target/aarch64/sve/tls_2.C: ...this and adjust likewise. * g++.dg/other/sve_vcond_1.C: Rename to... * g++.target/aarch64/sve/vcond_1.C: ...this and adjust likewise. * g++.dg/other/sve_vcond_1_run.C: Rename to... * g++.target/aarch64/sve/vcond_1_run.C: ...this and adjust likewise. From-SVN: r260038 --- gcc/testsuite/ChangeLog | 18 ++ gcc/testsuite/g++.dg/other/sve_const_pred_1.C | 18 -- gcc/testsuite/g++.dg/other/sve_const_pred_2.C | 16 -- gcc/testsuite/g++.dg/other/sve_const_pred_3.C | 15 -- gcc/testsuite/g++.dg/other/sve_const_pred_4.C | 15 -- gcc/testsuite/g++.dg/other/sve_tls_2.C | 31 --- gcc/testsuite/g++.dg/other/sve_vcond_1.C | 243 --------------------- gcc/testsuite/g++.dg/other/sve_vcond_1_run.C | 46 ---- .../g++.target/aarch64/sve/const_pred_1.C | 18 ++ .../g++.target/aarch64/sve/const_pred_2.C | 16 ++ .../g++.target/aarch64/sve/const_pred_3.C | 15 ++ .../g++.target/aarch64/sve/const_pred_4.C | 15 ++ gcc/testsuite/g++.target/aarch64/sve/tls_2.C | 31 +++ gcc/testsuite/g++.target/aarch64/sve/vcond_1.C | 243 +++++++++++++++++++++ gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C | 46 ++++ 15 files changed, 402 insertions(+), 384 deletions(-) delete mode 100644 gcc/testsuite/g++.dg/other/sve_const_pred_1.C delete mode 100644 gcc/testsuite/g++.dg/other/sve_const_pred_2.C delete mode 100644 gcc/testsuite/g++.dg/other/sve_const_pred_3.C delete mode 100644 gcc/testsuite/g++.dg/other/sve_const_pred_4.C delete mode 100644 gcc/testsuite/g++.dg/other/sve_tls_2.C delete mode 100644 gcc/testsuite/g++.dg/other/sve_vcond_1.C delete mode 100644 gcc/testsuite/g++.dg/other/sve_vcond_1_run.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/tls_2.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/vcond_1.C create mode 100644 gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C (limited to 'gcc') diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 5393aab..2628d55 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,23 @@ 2018-05-08 Richard Sandiford + * g++.dg/other/sve_const_pred_1.C: Rename to... + * g++.target/aarch64/sve/const_pred_1.C: ...this. Remove aarch64 + target selectors and explicit -march options. + * g++.dg/other/sve_const_pred_2.C: Rename to... + * g++.target/aarch64/sve/const_pred_2.C: ...this and adjust likewise. + * g++.dg/other/sve_const_pred_3.C: Rename to... + * g++.target/aarch64/sve/const_pred_3.C: ...this and adjust likewise. + * g++.dg/other/sve_const_pred_4.C: Rename to... + * g++.target/aarch64/sve/const_pred_4.C: ...this and adjust likewise. + * g++.dg/other/sve_tls_2.C: Rename to... + * g++.target/aarch64/sve/tls_2.C: ...this and adjust likewise. + * g++.dg/other/sve_vcond_1.C: Rename to... + * g++.target/aarch64/sve/vcond_1.C: ...this and adjust likewise. + * g++.dg/other/sve_vcond_1_run.C: Rename to... + * g++.target/aarch64/sve/vcond_1_run.C: ...this and adjust likewise. + +2018-05-08 Richard Sandiford + PR testsuite/85586 * gcc.dg/vect/pr85586.c: Restrict LOOP VECTORIZED test to !vect_no_align. diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_1.C b/gcc/testsuite/g++.dg/other/sve_const_pred_1.C deleted file mode 100644 index cc124c0..0000000 --- a/gcc/testsuite/g++.dg/other/sve_const_pred_1.C +++ /dev/null @@ -1,18 +0,0 @@ -/* { dg-do compile { target aarch64*-*-* } } */ -/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */ - -#include - -typedef int8_t vnx16qi __attribute__((vector_size(32))); - -vnx16qi -foo (vnx16qi x, vnx16qi y) -{ - return (vnx16qi) { -1, 0, 0, -1, -1, -1, 0, 0, - -1, -1, -1, -1, 0, 0, 0, 0, - -1, -1, -1, -1, -1, -1, -1, -1, - 0, 0, 0, 0, 0, 0, 0, 0 } ? x : y; -} - -/* { dg-final { scan-assembler {\tldr\tp[0-9]+,} } } */ -/* { dg-final { scan-assembler {\t\.byte\t57\n\t\.byte\t15\n\t\.byte\t(255|-1)\n\t\.byte\t0\n} } } */ diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_2.C b/gcc/testsuite/g++.dg/other/sve_const_pred_2.C deleted file mode 100644 index e3bce39..0000000 --- a/gcc/testsuite/g++.dg/other/sve_const_pred_2.C +++ /dev/null @@ -1,16 +0,0 @@ -/* { dg-do compile { target aarch64*-*-* } } */ -/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */ - -#include - -typedef int16_t vnx8hi __attribute__((vector_size(32))); - -vnx8hi -foo (vnx8hi x, vnx8hi y) -{ - return (vnx8hi) { -1, 0, 0, -1, -1, -1, 0, 0, - -1, -1, -1, -1, 0, 0, 0, 0 } ? x : y; -} - -/* { dg-final { scan-assembler {\tldr\tp[0-9]+,} } } */ -/* { dg-final { scan-assembler {\t\.byte\t65\n\t\.byte\t5\n\t\.byte\t85\n\t\.byte\t0\n} } } */ diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_3.C b/gcc/testsuite/g++.dg/other/sve_const_pred_3.C deleted file mode 100644 index 9e75f39..0000000 --- a/gcc/testsuite/g++.dg/other/sve_const_pred_3.C +++ /dev/null @@ -1,15 +0,0 @@ -/* { dg-do compile { target aarch64*-*-* } } */ -/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */ - -#include - -typedef int32_t vnx4si __attribute__((vector_size(32))); - -vnx4si -foo (vnx4si x, vnx4si y) -{ - return (vnx4si) { -1, 0, 0, -1, -1, -1, 0, 0 } ? x : y; -} - -/* { dg-final { scan-assembler {\tldr\tp[0-9]+,} } } */ -/* { dg-final { scan-assembler {\t\.byte\t1\n\t\.byte\t16\n\t\.byte\t17\n\t\.byte\t0\n} } } */ diff --git a/gcc/testsuite/g++.dg/other/sve_const_pred_4.C b/gcc/testsuite/g++.dg/other/sve_const_pred_4.C deleted file mode 100644 index 04a1351..0000000 --- a/gcc/testsuite/g++.dg/other/sve_const_pred_4.C +++ /dev/null @@ -1,15 +0,0 @@ -/* { dg-do compile { target aarch64*-*-* } } */ -/* { dg-options "-O2 -march=armv8.2-a+sve -msve-vector-bits=256" } */ - -#include - -typedef int64_t vnx2di __attribute__((vector_size(32))); - -vnx2di -foo (vnx2di x, vnx2di y) -{ - return (vnx2di) { -1, 0, 0, -1 } ? x : y; -} - -/* { dg-final { scan-assembler {\tldr\tp[0-9]+,} } } */ -/* { dg-final { scan-assembler {\t\.byte\t1\n\t\.byte\t0\n\t\.byte\t0\n\t\.byte\t1\n} } } */ diff --git a/gcc/testsuite/g++.dg/other/sve_tls_2.C b/gcc/testsuite/g++.dg/other/sve_tls_2.C deleted file mode 100644 index ed46893..0000000 --- a/gcc/testsuite/g++.dg/other/sve_tls_2.C +++ /dev/null @@ -1,31 +0,0 @@ -/* { dg-do compile { target aarch64*-*-* } } */ -/* { dg-require-effective-target tls } */ -/* { dg-options "-O2 -march=armv8.2-a+sve -fPIC -msve-vector-bits=256" } */ - -#include - -typedef int8_t v32qi __attribute__((vector_size (32))); - -extern __thread int z; - -void -foo (v32qi *a, int *b) -{ - v32qi x = a[0], y = a[1]; - asm volatile ("" :: "w" ((v32qi) { -1, 0, 0, -1, -1, -1, 0, 0, - -1, -1, -1, -1, 0, 0, 0, 0, - -1, -1, -1, -1, -1, -1, -1, -1, - 0, 0, 0, 0, 0, 0, 0, 0 } ? x : y) - : "memory"); - if (*b) - { - x = a[2], y = a[3]; - asm volatile ("" :: "w" ((v32qi) { -1, 0, 0, -1, -1, -1, 0, 0, - -1, -1, -1, -1, 0, 0, 0, 0, - -1, -1, -1, -1, -1, -1, -1, -1, - 0, 0, 0, 0, 0, 0, 0, 0 } ? x : y), - "r" (z)); - } -} - -/* { dg-final { scan-assembler-times {\tldr\tp[0-9]} 2 } } */ diff --git a/gcc/testsuite/g++.dg/other/sve_vcond_1.C b/gcc/testsuite/g++.dg/other/sve_vcond_1.C deleted file mode 100644 index c1ad0b9..0000000 --- a/gcc/testsuite/g++.dg/other/sve_vcond_1.C +++ /dev/null @@ -1,243 +0,0 @@ -/* { dg-do assemble { target { aarch64_asm_sve_ok && { ! ilp32 } } } } */ -/* { dg-options "-march=armv8.2-a+sve -O -msve-vector-bits=256 --save-temps" } */ - -typedef __INT8_TYPE__ vnx16qi __attribute__((vector_size(32))); -typedef __INT16_TYPE__ vnx8hi __attribute__((vector_size(32))); -typedef __INT32_TYPE__ vnx4si __attribute__((vector_size(32))); -typedef __INT64_TYPE__ vnx2di __attribute__((vector_size(32))); - -typedef __UINT8_TYPE__ v32qu __attribute__((vector_size(32))); -typedef __UINT16_TYPE__ v16hu __attribute__((vector_size(32))); -typedef __UINT32_TYPE__ v8su __attribute__((vector_size(32))); -typedef __UINT64_TYPE__ v4du __attribute__((vector_size(32))); - -#define DEF_VCOND_VAR(TYPE, COND, SUFFIX) \ -TYPE vcond_##TYPE##_##SUFFIX (TYPE x, TYPE y, TYPE a, TYPE b) \ -{ \ - TYPE r; \ - r = a COND b ? x : y; \ - return r; \ -} - -#define DEF_VCOND_IMM(TYPE, COND, IMM, SUFFIX) \ -TYPE vcond_imm_##TYPE##_##SUFFIX (TYPE x, TYPE y, TYPE a) \ -{ \ - TYPE r; \ - r = a COND IMM ? x : y; \ - return r; \ -} - -#define TEST_COND_VAR_SIGNED_ALL(T, COND, SUFFIX) \ - T (vnx16qi, COND, SUFFIX) \ - T (vnx8hi, COND, SUFFIX) \ - T (vnx4si, COND, SUFFIX) \ - T (vnx2di, COND, SUFFIX) - -#define TEST_COND_VAR_UNSIGNED_ALL(T, COND, SUFFIX) \ - T (v32qu, COND, SUFFIX) \ - T (v16hu, COND, SUFFIX) \ - T (v8su, COND, SUFFIX) \ - T (v4du, COND, SUFFIX) - -#define TEST_COND_VAR_ALL(T, COND, SUFFIX) \ - TEST_COND_VAR_SIGNED_ALL (T, COND, SUFFIX) \ - TEST_COND_VAR_UNSIGNED_ALL (T, COND, SUFFIX) - -#define TEST_VAR_ALL(T) \ - TEST_COND_VAR_ALL (T, >, gt) \ - TEST_COND_VAR_ALL (T, <, lt) \ - TEST_COND_VAR_ALL (T, >=, ge) \ - TEST_COND_VAR_ALL (T, <=, le) \ - TEST_COND_VAR_ALL (T, ==, eq) \ - TEST_COND_VAR_ALL (T, !=, ne) - -#define TEST_COND_IMM_SIGNED_ALL(T, COND, IMM, SUFFIX) \ - T (vnx16qi, COND, IMM, SUFFIX) \ - T (vnx8hi, COND, IMM, SUFFIX) \ - T (vnx4si, COND, IMM, SUFFIX) \ - T (vnx2di, COND, IMM, SUFFIX) - -#define TEST_COND_IMM_UNSIGNED_ALL(T, COND, IMM, SUFFIX) \ - T (v32qu, COND, IMM, SUFFIX) \ - T (v16hu, COND, IMM, SUFFIX) \ - T (v8su, COND, IMM, SUFFIX) \ - T (v4du, COND, IMM, SUFFIX) - -#define TEST_COND_IMM_ALL(T, COND, IMM, SUFFIX) \ - TEST_COND_IMM_SIGNED_ALL (T, COND, IMM, SUFFIX) \ - TEST_COND_IMM_UNSIGNED_ALL (T, COND, IMM, SUFFIX) - -#define TEST_IMM_ALL(T) \ - /* Expect immediates to make it into the encoding. */ \ - TEST_COND_IMM_ALL (T, >, 5, gt) \ - TEST_COND_IMM_ALL (T, <, 5, lt) \ - TEST_COND_IMM_ALL (T, >=, 5, ge) \ - TEST_COND_IMM_ALL (T, <=, 5, le) \ - TEST_COND_IMM_ALL (T, ==, 5, eq) \ - TEST_COND_IMM_ALL (T, !=, 5, ne) \ - \ - TEST_COND_IMM_SIGNED_ALL (T, >, 15, gt2) \ - TEST_COND_IMM_SIGNED_ALL (T, <, 15, lt2) \ - TEST_COND_IMM_SIGNED_ALL (T, >=, 15, ge2) \ - TEST_COND_IMM_SIGNED_ALL (T, <=, 15, le2) \ - TEST_COND_IMM_SIGNED_ALL (T, ==, 15, eq2) \ - TEST_COND_IMM_SIGNED_ALL (T, !=, 15, ne2) \ - \ - TEST_COND_IMM_SIGNED_ALL (T, >, -16, gt3) \ - TEST_COND_IMM_SIGNED_ALL (T, <, -16, lt3) \ - TEST_COND_IMM_SIGNED_ALL (T, >=, -16, ge3) \ - TEST_COND_IMM_SIGNED_ALL (T, <=, -16, le3) \ - TEST_COND_IMM_SIGNED_ALL (T, ==, -16, eq3) \ - TEST_COND_IMM_SIGNED_ALL (T, !=, -16, ne3) \ - \ - TEST_COND_IMM_UNSIGNED_ALL (T, >, 0, gt4) \ - /* Testing if an unsigned value >= 0 or < 0 is pointless as it will \ - get folded away by the compiler. */ \ - TEST_COND_IMM_UNSIGNED_ALL (T, <=, 0, le4) \ - \ - TEST_COND_IMM_UNSIGNED_ALL (T, >, 31, gt5) \ - TEST_COND_IMM_UNSIGNED_ALL (T, <, 31, lt5) \ - TEST_COND_IMM_UNSIGNED_ALL (T, >=, 31, ge5) \ - TEST_COND_IMM_UNSIGNED_ALL (T, <=, 31, le5) \ - \ - /* Expect immediates to NOT make it into the encoding, and instead be \ - forced into a register. */ \ - TEST_COND_IMM_ALL (T, >, 32, gt6) \ - TEST_COND_IMM_ALL (T, <, 32, lt6) \ - TEST_COND_IMM_ALL (T, >=, 32, ge6) \ - TEST_COND_IMM_ALL (T, <=, 32, le6) \ - TEST_COND_IMM_ALL (T, ==, 32, eq6) \ - TEST_COND_IMM_ALL (T, !=, 32, ne6) - -TEST_VAR_ALL (DEF_VCOND_VAR) -TEST_IMM_ALL (DEF_VCOND_IMM) - -/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.b, p[0-7], z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ - - - -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ - -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ - -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ - -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ - -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ - -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ - -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ - -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ - -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ - -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ - -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ - -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ -/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ - - - -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */ - -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */ - - -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ - -/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ - -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ - -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ -/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ diff --git a/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C b/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C deleted file mode 100644 index b542356..0000000 --- a/gcc/testsuite/g++.dg/other/sve_vcond_1_run.C +++ /dev/null @@ -1,46 +0,0 @@ -/* { dg-do run { target aarch64_sve_hw } } */ -/* { dg-options "-O -march=armv8.2-a+sve" } */ -/* { dg-options "-O -march=armv8.2-a+sve -msve-vector-bits=256" { target aarch64_sve256_hw } } */ - -#include "sve_vcond_1.c" - -#define NUM_ELEMS(X) (sizeof (X) / sizeof (X[0])) - -#define TEST_VCOND_VAR(TYPE, COND, SUFFIX) \ -{ \ - TYPE x, y, a, b; \ - for (int i = 0; i < NUM_ELEMS (x); ++i) \ - { \ - a[i] = i - 2; \ - b[i] = NUM_ELEMS (x) - 2 - i; \ - x[i] = i * 2; \ - y[i] = -i * 3; \ - } \ - TYPE r = vcond_##TYPE##_##SUFFIX (x, y, a, b); \ - for (int i = 0; i < NUM_ELEMS (x); ++i) \ - if (r[i] != (a[i] COND b[i] ? x[i] : y[i])) \ - __builtin_abort (); \ -} - -#define TEST_VCOND_IMM(TYPE, COND, IMM, SUFFIX) \ -{ \ - TYPE x, y, a; \ - for (int i = 0; i < NUM_ELEMS (x); ++i) \ - { \ - a[i] = IMM - 2 + i; \ - x[i] = i * 2; \ - y[i] = -i * 3; \ - } \ - TYPE r = vcond_imm_##TYPE##_##SUFFIX (x, y, a); \ - for (int i = 0; i < NUM_ELEMS (x); ++i) \ - if (r[i] != (a[i] COND IMM ? x[i] : y[i])) \ - __builtin_abort (); \ -} - - -int main (int argc, char **argv) -{ - TEST_VAR_ALL (TEST_VCOND_VAR) - TEST_IMM_ALL (TEST_VCOND_IMM) - return 0; -} diff --git a/gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C new file mode 100644 index 0000000..25b7663 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_1.C @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int8_t vnx16qi __attribute__((vector_size(32))); + +vnx16qi +foo (vnx16qi x, vnx16qi y) +{ + return (vnx16qi) { -1, 0, 0, -1, -1, -1, 0, 0, + -1, -1, -1, -1, 0, 0, 0, 0, + -1, -1, -1, -1, -1, -1, -1, -1, + 0, 0, 0, 0, 0, 0, 0, 0 } ? x : y; +} + +/* { dg-final { scan-assembler {\tldr\tp[0-9]+,} } } */ +/* { dg-final { scan-assembler {\t\.byte\t57\n\t\.byte\t15\n\t\.byte\t(255|-1)\n\t\.byte\t0\n} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C new file mode 100644 index 0000000..4c781ca --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_2.C @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int16_t vnx8hi __attribute__((vector_size(32))); + +vnx8hi +foo (vnx8hi x, vnx8hi y) +{ + return (vnx8hi) { -1, 0, 0, -1, -1, -1, 0, 0, + -1, -1, -1, -1, 0, 0, 0, 0 } ? x : y; +} + +/* { dg-final { scan-assembler {\tldr\tp[0-9]+,} } } */ +/* { dg-final { scan-assembler {\t\.byte\t65\n\t\.byte\t5\n\t\.byte\t85\n\t\.byte\t0\n} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C new file mode 100644 index 0000000..6196ee0 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_3.C @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); + +vnx4si +foo (vnx4si x, vnx4si y) +{ + return (vnx4si) { -1, 0, 0, -1, -1, -1, 0, 0 } ? x : y; +} + +/* { dg-final { scan-assembler {\tldr\tp[0-9]+,} } } */ +/* { dg-final { scan-assembler {\t\.byte\t1\n\t\.byte\t16\n\t\.byte\t17\n\t\.byte\t0\n} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C b/gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C new file mode 100644 index 0000000..2bdf67fd --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/const_pred_4.C @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int64_t vnx2di __attribute__((vector_size(32))); + +vnx2di +foo (vnx2di x, vnx2di y) +{ + return (vnx2di) { -1, 0, 0, -1 } ? x : y; +} + +/* { dg-final { scan-assembler {\tldr\tp[0-9]+,} } } */ +/* { dg-final { scan-assembler {\t\.byte\t1\n\t\.byte\t0\n\t\.byte\t0\n\t\.byte\t1\n} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/tls_2.C b/gcc/testsuite/g++.target/aarch64/sve/tls_2.C new file mode 100644 index 0000000..9267f1e --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/tls_2.C @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target tls } */ +/* { dg-options "-O2 -fPIC -msve-vector-bits=256" } */ + +#include + +typedef int8_t v32qi __attribute__((vector_size (32))); + +extern __thread int z; + +void +foo (v32qi *a, int *b) +{ + v32qi x = a[0], y = a[1]; + asm volatile ("" :: "w" ((v32qi) { -1, 0, 0, -1, -1, -1, 0, 0, + -1, -1, -1, -1, 0, 0, 0, 0, + -1, -1, -1, -1, -1, -1, -1, -1, + 0, 0, 0, 0, 0, 0, 0, 0 } ? x : y) + : "memory"); + if (*b) + { + x = a[2], y = a[3]; + asm volatile ("" :: "w" ((v32qi) { -1, 0, 0, -1, -1, -1, 0, 0, + -1, -1, -1, -1, 0, 0, 0, 0, + -1, -1, -1, -1, -1, -1, -1, -1, + 0, 0, 0, 0, 0, 0, 0, 0 } ? x : y), + "r" (z)); + } +} + +/* { dg-final { scan-assembler-times {\tldr\tp[0-9]} 2 } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C b/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C new file mode 100644 index 0000000..2a80d21 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/vcond_1.C @@ -0,0 +1,243 @@ +/* { dg-do assemble { target { aarch64_asm_sve_ok && { ! ilp32 } } } } */ +/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */ + +typedef __INT8_TYPE__ vnx16qi __attribute__((vector_size(32))); +typedef __INT16_TYPE__ vnx8hi __attribute__((vector_size(32))); +typedef __INT32_TYPE__ vnx4si __attribute__((vector_size(32))); +typedef __INT64_TYPE__ vnx2di __attribute__((vector_size(32))); + +typedef __UINT8_TYPE__ v32qu __attribute__((vector_size(32))); +typedef __UINT16_TYPE__ v16hu __attribute__((vector_size(32))); +typedef __UINT32_TYPE__ v8su __attribute__((vector_size(32))); +typedef __UINT64_TYPE__ v4du __attribute__((vector_size(32))); + +#define DEF_VCOND_VAR(TYPE, COND, SUFFIX) \ +TYPE vcond_##TYPE##_##SUFFIX (TYPE x, TYPE y, TYPE a, TYPE b) \ +{ \ + TYPE r; \ + r = a COND b ? x : y; \ + return r; \ +} + +#define DEF_VCOND_IMM(TYPE, COND, IMM, SUFFIX) \ +TYPE vcond_imm_##TYPE##_##SUFFIX (TYPE x, TYPE y, TYPE a) \ +{ \ + TYPE r; \ + r = a COND IMM ? x : y; \ + return r; \ +} + +#define TEST_COND_VAR_SIGNED_ALL(T, COND, SUFFIX) \ + T (vnx16qi, COND, SUFFIX) \ + T (vnx8hi, COND, SUFFIX) \ + T (vnx4si, COND, SUFFIX) \ + T (vnx2di, COND, SUFFIX) + +#define TEST_COND_VAR_UNSIGNED_ALL(T, COND, SUFFIX) \ + T (v32qu, COND, SUFFIX) \ + T (v16hu, COND, SUFFIX) \ + T (v8su, COND, SUFFIX) \ + T (v4du, COND, SUFFIX) + +#define TEST_COND_VAR_ALL(T, COND, SUFFIX) \ + TEST_COND_VAR_SIGNED_ALL (T, COND, SUFFIX) \ + TEST_COND_VAR_UNSIGNED_ALL (T, COND, SUFFIX) + +#define TEST_VAR_ALL(T) \ + TEST_COND_VAR_ALL (T, >, gt) \ + TEST_COND_VAR_ALL (T, <, lt) \ + TEST_COND_VAR_ALL (T, >=, ge) \ + TEST_COND_VAR_ALL (T, <=, le) \ + TEST_COND_VAR_ALL (T, ==, eq) \ + TEST_COND_VAR_ALL (T, !=, ne) + +#define TEST_COND_IMM_SIGNED_ALL(T, COND, IMM, SUFFIX) \ + T (vnx16qi, COND, IMM, SUFFIX) \ + T (vnx8hi, COND, IMM, SUFFIX) \ + T (vnx4si, COND, IMM, SUFFIX) \ + T (vnx2di, COND, IMM, SUFFIX) + +#define TEST_COND_IMM_UNSIGNED_ALL(T, COND, IMM, SUFFIX) \ + T (v32qu, COND, IMM, SUFFIX) \ + T (v16hu, COND, IMM, SUFFIX) \ + T (v8su, COND, IMM, SUFFIX) \ + T (v4du, COND, IMM, SUFFIX) + +#define TEST_COND_IMM_ALL(T, COND, IMM, SUFFIX) \ + TEST_COND_IMM_SIGNED_ALL (T, COND, IMM, SUFFIX) \ + TEST_COND_IMM_UNSIGNED_ALL (T, COND, IMM, SUFFIX) + +#define TEST_IMM_ALL(T) \ + /* Expect immediates to make it into the encoding. */ \ + TEST_COND_IMM_ALL (T, >, 5, gt) \ + TEST_COND_IMM_ALL (T, <, 5, lt) \ + TEST_COND_IMM_ALL (T, >=, 5, ge) \ + TEST_COND_IMM_ALL (T, <=, 5, le) \ + TEST_COND_IMM_ALL (T, ==, 5, eq) \ + TEST_COND_IMM_ALL (T, !=, 5, ne) \ + \ + TEST_COND_IMM_SIGNED_ALL (T, >, 15, gt2) \ + TEST_COND_IMM_SIGNED_ALL (T, <, 15, lt2) \ + TEST_COND_IMM_SIGNED_ALL (T, >=, 15, ge2) \ + TEST_COND_IMM_SIGNED_ALL (T, <=, 15, le2) \ + TEST_COND_IMM_SIGNED_ALL (T, ==, 15, eq2) \ + TEST_COND_IMM_SIGNED_ALL (T, !=, 15, ne2) \ + \ + TEST_COND_IMM_SIGNED_ALL (T, >, -16, gt3) \ + TEST_COND_IMM_SIGNED_ALL (T, <, -16, lt3) \ + TEST_COND_IMM_SIGNED_ALL (T, >=, -16, ge3) \ + TEST_COND_IMM_SIGNED_ALL (T, <=, -16, le3) \ + TEST_COND_IMM_SIGNED_ALL (T, ==, -16, eq3) \ + TEST_COND_IMM_SIGNED_ALL (T, !=, -16, ne3) \ + \ + TEST_COND_IMM_UNSIGNED_ALL (T, >, 0, gt4) \ + /* Testing if an unsigned value >= 0 or < 0 is pointless as it will \ + get folded away by the compiler. */ \ + TEST_COND_IMM_UNSIGNED_ALL (T, <=, 0, le4) \ + \ + TEST_COND_IMM_UNSIGNED_ALL (T, >, 31, gt5) \ + TEST_COND_IMM_UNSIGNED_ALL (T, <, 31, lt5) \ + TEST_COND_IMM_UNSIGNED_ALL (T, >=, 31, ge5) \ + TEST_COND_IMM_UNSIGNED_ALL (T, <=, 31, le5) \ + \ + /* Expect immediates to NOT make it into the encoding, and instead be \ + forced into a register. */ \ + TEST_COND_IMM_ALL (T, >, 32, gt6) \ + TEST_COND_IMM_ALL (T, <, 32, lt6) \ + TEST_COND_IMM_ALL (T, >=, 32, ge6) \ + TEST_COND_IMM_ALL (T, <=, 32, le6) \ + TEST_COND_IMM_ALL (T, ==, 32, eq6) \ + TEST_COND_IMM_ALL (T, !=, 32, ne6) + +TEST_VAR_ALL (DEF_VCOND_VAR) +TEST_IMM_ALL (DEF_VCOND_IMM) + +/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.b, p[0-7], z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.h, p[0-7], z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.s, p[0-7], z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tsel\tz[0-9]+\.d, p[0-7], z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, z[0-9]+\.d\n} } } */ + + + +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ + +/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ + +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ + +/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ + +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ + +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #15\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #15\n} } } */ + +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpgt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ + +/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmplt\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ + +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpge\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ + +/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmple\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ + +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpeq\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ + +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #-16\n} } } */ +/* { dg-final { scan-assembler {\tcmpne\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #-16\n} } } */ + + + +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */ + +/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #0\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #0\n} } } */ + + +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmphi\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ + +/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmplo\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ + +/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmphs\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ + +/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.b, p[0-7]/z, z[0-9]+\.b, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, #31\n} } } */ +/* { dg-final { scan-assembler {\tcmpls\tp[0-7]\.d, p[0-7]/z, z[0-9]+\.d, #31\n} } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C b/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C new file mode 100644 index 0000000..d01745e --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/vcond_1_run.C @@ -0,0 +1,46 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O" } */ +/* { dg-options "-O -msve-vector-bits=256" { target aarch64_sve256_hw } } */ + +#include "sve_vcond_1.c" + +#define NUM_ELEMS(X) (sizeof (X) / sizeof (X[0])) + +#define TEST_VCOND_VAR(TYPE, COND, SUFFIX) \ +{ \ + TYPE x, y, a, b; \ + for (int i = 0; i < NUM_ELEMS (x); ++i) \ + { \ + a[i] = i - 2; \ + b[i] = NUM_ELEMS (x) - 2 - i; \ + x[i] = i * 2; \ + y[i] = -i * 3; \ + } \ + TYPE r = vcond_##TYPE##_##SUFFIX (x, y, a, b); \ + for (int i = 0; i < NUM_ELEMS (x); ++i) \ + if (r[i] != (a[i] COND b[i] ? x[i] : y[i])) \ + __builtin_abort (); \ +} + +#define TEST_VCOND_IMM(TYPE, COND, IMM, SUFFIX) \ +{ \ + TYPE x, y, a; \ + for (int i = 0; i < NUM_ELEMS (x); ++i) \ + { \ + a[i] = IMM - 2 + i; \ + x[i] = i * 2; \ + y[i] = -i * 3; \ + } \ + TYPE r = vcond_imm_##TYPE##_##SUFFIX (x, y, a); \ + for (int i = 0; i < NUM_ELEMS (x); ++i) \ + if (r[i] != (a[i] COND IMM ? x[i] : y[i])) \ + __builtin_abort (); \ +} + + +int main (int argc, char **argv) +{ + TEST_VAR_ALL (TEST_VCOND_VAR) + TEST_IMM_ALL (TEST_VCOND_IMM) + return 0; +} -- cgit v1.1