From 494ebfa7c9aacaeb6ec1fccc47a0e49f31eb2bb8 Mon Sep 17 00:00:00 2001 From: Tobias Burnus Date: Mon, 13 Dec 2021 12:37:40 +0100 Subject: Fortran: Handle compare in OpenMP atomic gcc/fortran/ChangeLog: PR fortran/103576 * openmp.c (is_scalar_intrinsic_expr): Fix condition. (resolve_omp_atomic): Fix/update checks, accept compare. * trans-openmp.c (gfc_trans_omp_atomic): Handle compare. libgomp/ChangeLog: * libgomp.texi (OpenMP 5.1): Set Fortran support for atomic to 'Y'. * testsuite/libgomp.fortran/atomic-19.f90: New test. gcc/testsuite/ChangeLog: * gfortran.dg/gomp/atomic-25.f90: Remove sorry, fix + add checks. * gfortran.dg/gomp/atomic-26.f90: Likewise. * gfortran.dg/gomp/atomic-21.f90: New test. --- gcc/fortran/openmp.c | 81 +++++----- gcc/fortran/trans-openmp.c | 211 ++++++++++++++++++++------- gcc/testsuite/gfortran.dg/gomp/atomic-21.f90 | 93 ++++++++++++ gcc/testsuite/gfortran.dg/gomp/atomic-25.f90 | 18 +-- gcc/testsuite/gfortran.dg/gomp/atomic-26.f90 | 26 +++- 5 files changed, 336 insertions(+), 93 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/gomp/atomic-21.f90 (limited to 'gcc') diff --git a/gcc/fortran/openmp.c b/gcc/fortran/openmp.c index 846fd7b..2036bc1 100644 --- a/gcc/fortran/openmp.c +++ b/gcc/fortran/openmp.c @@ -7552,10 +7552,10 @@ is_scalar_intrinsic_expr (gfc_expr *expr, bool must_be_var, bool conv_ok) return false; return (expr->rank == 0 && !gfc_is_coindexed (expr) - && (expr->ts.type != BT_INTEGER - || expr->ts.type != BT_REAL - || expr->ts.type != BT_COMPLEX - || expr->ts.type != BT_LOGICAL)); + && (expr->ts.type == BT_INTEGER + || expr->ts.type == BT_REAL + || expr->ts.type == BT_COMPLEX + || expr->ts.type == BT_LOGICAL)); } static void @@ -7574,12 +7574,9 @@ resolve_omp_atomic (gfc_code *code) code = code->block->next; /* resolve_blocks asserts this is initially EXEC_ASSIGN or EXEC_IF If it changed to EXEC_NOP, assume an error has been emitted already. */ - if (code->op == EXEC_NOP /* FIXME: || (code->next && code->next->op == EXEC_NOP)*/) + if (code->op == EXEC_NOP) return; - if (code->op == EXEC_IF && code->block->op == EXEC_IF) - comp_cond = code->block->expr1; - if (atomic_code->ext.omp_clauses->compare && atomic_code->ext.omp_clauses->capture) { @@ -7597,6 +7594,7 @@ resolve_omp_atomic (gfc_code *code) && next->block->op == EXEC_IF && next->block->next->op == EXEC_ASSIGN) { + comp_cond = next->block->expr1; stmt = next->block->next; if (stmt->next) { @@ -7604,11 +7602,20 @@ resolve_omp_atomic (gfc_code *code) goto unexpected; } } + else if (capture_stmt) + { + gfc_error ("Expected IF at %L in atomic compare capture", + &next->loc); + return; + } if (stmt && !capture_stmt && next->block->block) { if (next->block->block->expr1) - gfc_error ("Expected ELSE at %L in atomic compare capture", - &next->block->block->expr1->where); + { + gfc_error ("Expected ELSE at %L in atomic compare capture", + &next->block->block->expr1->where); + return; + } if (!code->block->block->next || code->block->block->next->op != EXEC_ASSIGN) { @@ -7623,10 +7630,8 @@ resolve_omp_atomic (gfc_code *code) goto unexpected; } } - if (stmt && !capture_stmt && code->op == EXEC_ASSIGN) - { - capture_stmt = code; - } + if (stmt && !capture_stmt && next->next->op == EXEC_ASSIGN) + capture_stmt = next->next; else if (!capture_stmt) { loc = &code->loc; @@ -7641,6 +7646,7 @@ resolve_omp_atomic (gfc_code *code) && code->block->op == EXEC_IF && code->block->next->op == EXEC_ASSIGN) { + comp_cond = code->block->expr1; stmt = code->block->next; if (stmt->next || code->block->block) { @@ -7703,8 +7709,7 @@ resolve_omp_atomic (gfc_code *code) { /* x = ... */ stmt = code; - if ((!atomic_code->ext.omp_clauses->compare && stmt->op != EXEC_ASSIGN) - || (atomic_code->ext.omp_clauses->compare && stmt->op != EXEC_IF)) + if (!atomic_code->ext.omp_clauses->compare && stmt->op != EXEC_ASSIGN) goto unexpected; gcc_assert (!code->next); } @@ -7720,7 +7725,7 @@ resolve_omp_atomic (gfc_code *code) "expression at %L", &comp_cond->where); return; } - if (!is_scalar_intrinsic_expr (comp_cond->value.op.op1, true, false)) + if (!is_scalar_intrinsic_expr (comp_cond->value.op.op1, true, true)) { gfc_error ("Expected scalar intrinsic variable at %L in atomic " "comparison", &comp_cond->value.op.op1->where); @@ -7781,14 +7786,6 @@ resolve_omp_atomic (gfc_code *code) break; } - if (atomic_code->ext.omp_clauses->compare - && !atomic_code->ext.omp_clauses->capture) - { - gfc_error ("Sorry, COMPARE clause in ATOMIC at %L is not yet " - "supported", &atomic_code->loc); - return; - } - if (atomic_code->ext.omp_clauses->capture) { if (!is_scalar_intrinsic_expr (capture_stmt->expr1, true, false)) @@ -7818,8 +7815,31 @@ resolve_omp_atomic (gfc_code *code) } } - if (atomic_code->ext.omp_clauses->capture - && !expr_references_sym (stmt_expr2, var, NULL)) + if (atomic_code->ext.omp_clauses->compare) + { + gfc_expr *var_expr; + if (comp_cond->value.op.op1->expr_type == EXPR_VARIABLE) + var_expr = comp_cond->value.op.op1; + else + var_expr = comp_cond->value.op.op1->value.function.actual->expr; + if (var_expr->symtree->n.sym != var) + { + gfc_error ("For !$OMP ATOMIC COMPARE, the first operand in comparison" + " at %L must be the variable %qs that the update statement" + " writes into at %L", &var_expr->where, var->name, + &stmt->expr1->where); + return; + } + if (stmt_expr2->rank != 0 || expr_references_sym (stmt_expr2, var, NULL)) + { + gfc_error ("expr in !$OMP ATOMIC COMPARE assignment var = expr " + "must be scalar and cannot reference var at %L", + &stmt_expr2->where); + return; + } + } + else if (atomic_code->ext.omp_clauses->capture + && !expr_references_sym (stmt_expr2, var, NULL)) atomic_code->ext.omp_clauses->atomic_op = (gfc_omp_atomic_op) (atomic_code->ext.omp_clauses->atomic_op | GFC_OMP_ATOMIC_SWAP); @@ -7829,8 +7849,7 @@ resolve_omp_atomic (gfc_code *code) gfc_intrinsic_op op = stmt_expr2->value.op.op; gfc_intrinsic_op alt_op = INTRINSIC_NONE; - if (atomic_code->ext.omp_clauses->fail != OMP_MEMORDER_UNSET - && !atomic_code->ext.omp_clauses->compare) + if (atomic_code->ext.omp_clauses->fail != OMP_MEMORDER_UNSET) gfc_error ("!$OMP ATOMIC UPDATE at %L with FAIL clause requiries either" " the COMPARE clause or using the intrinsic MIN/MAX " "procedure", &atomic_code->loc); @@ -8042,10 +8061,6 @@ resolve_omp_atomic (gfc_code *code) else gfc_error ("!$OMP ATOMIC assignment must have an operator or " "intrinsic on right hand side at %L", &stmt_expr2->where); - - if (atomic_code->ext.omp_clauses->compare) - gfc_error ("Sorry, COMPARE clause in ATOMIC at %L is not yet " - "supported", &atomic_code->loc); return; unexpected: diff --git a/gcc/fortran/trans-openmp.c b/gcc/fortran/trans-openmp.c index d8229a5..aa0b0a5 100644 --- a/gcc/fortran/trans-openmp.c +++ b/gcc/fortran/trans-openmp.c @@ -4488,13 +4488,13 @@ gfc_trans_omp_atomic (gfc_code *code) gfc_se lse; gfc_se rse; gfc_se vse; - gfc_expr *expr2, *e; + gfc_expr *expr1, *expr2, *e, *capture_expr1 = NULL, *capture_expr2 = NULL; gfc_symbol *var; stmtblock_t block; - tree lhsaddr, type, rhs, x; + tree lhsaddr, type, rhs, x, compare = NULL_TREE, comp_tgt = NULL_TREE; enum tree_code op = ERROR_MARK; enum tree_code aop = OMP_ATOMIC; - bool var_on_left = false; + bool var_on_left = false, else_branch = false; enum omp_memory_order mo, fail_mo; switch (atomic_code->ext.omp_clauses->memorder) { @@ -4514,18 +4514,86 @@ gfc_trans_omp_atomic (gfc_code *code) case OMP_MEMORDER_SEQ_CST: fail_mo = OMP_FAIL_MEMORY_ORDER_SEQ_CST; break; default: gcc_unreachable (); } - mo = (omp_memory_order) (mo | fail_mo); + mo = (omp_memory_order) (mo | fail_mo); code = code->block->next; - gcc_assert (code->op == EXEC_ASSIGN); - var = code->expr1->symtree->n.sym; + if (atomic_code->ext.omp_clauses->compare) + { + gfc_expr *comp_expr; + if (code->op == EXEC_IF) + { + comp_expr = code->block->expr1; + gcc_assert (code->block->next->op == EXEC_ASSIGN); + expr1 = code->block->next->expr1; + expr2 = code->block->next->expr2; + if (code->block->block) + { + gcc_assert (atomic_code->ext.omp_clauses->capture + && code->block->block->next->op == EXEC_ASSIGN); + else_branch = true; + aop = OMP_ATOMIC_CAPTURE_OLD; + capture_expr1 = code->block->block->next->expr1; + capture_expr2 = code->block->block->next->expr2; + } + else if (atomic_code->ext.omp_clauses->capture) + { + gcc_assert (code->next->op == EXEC_ASSIGN); + aop = OMP_ATOMIC_CAPTURE_NEW; + capture_expr1 = code->next->expr1; + capture_expr2 = code->next->expr2; + } + } + else + { + gcc_assert (atomic_code->ext.omp_clauses->capture + && code->op == EXEC_ASSIGN + && code->next->op == EXEC_IF); + aop = OMP_ATOMIC_CAPTURE_OLD; + capture_expr1 = code->expr1; + capture_expr2 = code->expr2; + expr1 = code->next->block->next->expr1; + expr2 = code->next->block->next->expr2; + comp_expr = code->next->block->expr1; + } + gfc_init_se (&lse, NULL); + gfc_conv_expr (&lse, comp_expr->value.op.op2); + gfc_add_block_to_block (&block, &lse.pre); + compare = lse.expr; + var = expr1->symtree->n.sym; + } + else + { + gcc_assert (code->op == EXEC_ASSIGN); + expr1 = code->expr1; + expr2 = code->expr2; + if (atomic_code->ext.omp_clauses->capture + && (expr2->expr_type == EXPR_VARIABLE + || (expr2->expr_type == EXPR_FUNCTION + && expr2->value.function.isym + && expr2->value.function.isym->id == GFC_ISYM_CONVERSION + && (expr2->value.function.actual->expr->expr_type + == EXPR_VARIABLE)))) + { + capture_expr1 = expr1; + capture_expr2 = expr2; + expr1 = code->next->expr1; + expr2 = code->next->expr2; + aop = OMP_ATOMIC_CAPTURE_OLD; + } + else if (atomic_code->ext.omp_clauses->capture) + { + aop = OMP_ATOMIC_CAPTURE_NEW; + capture_expr1 = code->next->expr1; + capture_expr2 = code->next->expr2; + } + var = expr1->symtree->n.sym; + } gfc_init_se (&lse, NULL); gfc_init_se (&rse, NULL); gfc_init_se (&vse, NULL); gfc_start_block (&block); - expr2 = code->expr2; if (((atomic_code->ext.omp_clauses->atomic_op & GFC_OMP_ATOMIC_MASK) != GFC_OMP_ATOMIC_WRITE) && expr2->expr_type == EXPR_FUNCTION @@ -4536,7 +4604,7 @@ gfc_trans_omp_atomic (gfc_code *code) if ((atomic_code->ext.omp_clauses->atomic_op & GFC_OMP_ATOMIC_MASK) == GFC_OMP_ATOMIC_READ) { - gfc_conv_expr (&vse, code->expr1); + gfc_conv_expr (&vse, expr1); gfc_add_block_to_block (&block, &vse.pre); gfc_conv_expr (&lse, expr2); @@ -4554,36 +4622,32 @@ gfc_trans_omp_atomic (gfc_code *code) return gfc_finish_block (&block); } - if (atomic_code->ext.omp_clauses->capture) + + if (capture_expr2 + && capture_expr2->expr_type == EXPR_FUNCTION + && capture_expr2->value.function.isym + && capture_expr2->value.function.isym->id == GFC_ISYM_CONVERSION) + capture_expr2 = capture_expr2->value.function.actual->expr; + gcc_assert (!capture_expr2 || capture_expr2->expr_type == EXPR_VARIABLE); + + if (aop == OMP_ATOMIC_CAPTURE_OLD) { - aop = OMP_ATOMIC_CAPTURE_NEW; - if (expr2->expr_type == EXPR_VARIABLE) - { - aop = OMP_ATOMIC_CAPTURE_OLD; - gfc_conv_expr (&vse, code->expr1); - gfc_add_block_to_block (&block, &vse.pre); - - gfc_conv_expr (&lse, expr2); - gfc_add_block_to_block (&block, &lse.pre); - gfc_init_se (&lse, NULL); - code = code->next; - var = code->expr1->symtree->n.sym; - expr2 = code->expr2; - if (expr2->expr_type == EXPR_FUNCTION - && expr2->value.function.isym - && expr2->value.function.isym->id == GFC_ISYM_CONVERSION) - expr2 = expr2->value.function.actual->expr; - } + gfc_conv_expr (&vse, capture_expr1); + gfc_add_block_to_block (&block, &vse.pre); + gfc_conv_expr (&lse, capture_expr2); + gfc_add_block_to_block (&block, &lse.pre); + gfc_init_se (&lse, NULL); } - gfc_conv_expr (&lse, code->expr1); + gfc_conv_expr (&lse, expr1); gfc_add_block_to_block (&block, &lse.pre); type = TREE_TYPE (lse.expr); lhsaddr = gfc_build_addr_expr (NULL, lse.expr); if (((atomic_code->ext.omp_clauses->atomic_op & GFC_OMP_ATOMIC_MASK) == GFC_OMP_ATOMIC_WRITE) - || (atomic_code->ext.omp_clauses->atomic_op & GFC_OMP_ATOMIC_SWAP)) + || (atomic_code->ext.omp_clauses->atomic_op & GFC_OMP_ATOMIC_SWAP) + || compare) { gfc_conv_expr (&rse, expr2); gfc_add_block_to_block (&block, &rse.pre); @@ -4675,6 +4739,10 @@ gfc_trans_omp_atomic (gfc_code *code) gcc_unreachable (); } e = expr2->value.function.actual->expr; + if (e->expr_type == EXPR_FUNCTION + && e->value.function.isym + && e->value.function.isym->id == GFC_ISYM_CONVERSION) + e = e->value.function.actual->expr; gcc_assert (e->expr_type == EXPR_VARIABLE && e->symtree != NULL && e->symtree->n.sym == var); @@ -4717,11 +4785,27 @@ gfc_trans_omp_atomic (gfc_code *code) NULL_TREE, NULL_TREE); } - rhs = gfc_evaluate_now (rse.expr, &block); + if (compare) + { + tree var = create_tmp_var_raw (TREE_TYPE (lhsaddr)); + DECL_CONTEXT (var) = current_function_decl; + lhsaddr = build4 (TARGET_EXPR, TREE_TYPE (lhsaddr), var, lhsaddr, NULL, + NULL); + lse.expr = build_fold_indirect_ref_loc (input_location, lhsaddr); + compare = convert (TREE_TYPE (lse.expr), compare); + compare = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node, + lse.expr, compare); + } + + if (expr2->expr_type == EXPR_VARIABLE || compare) + rhs = rse.expr; + else + rhs = gfc_evaluate_now (rse.expr, &block); if (((atomic_code->ext.omp_clauses->atomic_op & GFC_OMP_ATOMIC_MASK) == GFC_OMP_ATOMIC_WRITE) - || (atomic_code->ext.omp_clauses->atomic_op & GFC_OMP_ATOMIC_SWAP)) + || (atomic_code->ext.omp_clauses->atomic_op & GFC_OMP_ATOMIC_SWAP) + || compare) x = rhs; else { @@ -4741,6 +4825,30 @@ gfc_trans_omp_atomic (gfc_code *code) gfc_add_block_to_block (&block, &lse.pre); gfc_add_block_to_block (&block, &rse.pre); + if (aop == OMP_ATOMIC_CAPTURE_NEW) + { + gfc_conv_expr (&vse, capture_expr1); + gfc_add_block_to_block (&block, &vse.pre); + gfc_add_block_to_block (&block, &lse.pre); + } + + if (compare && else_branch) + { + tree var2 = create_tmp_var_raw (boolean_type_node); + DECL_CONTEXT (var2) = current_function_decl; + comp_tgt = build4 (TARGET_EXPR, boolean_type_node, var2, + boolean_false_node, NULL, NULL); + compare = fold_build2_loc (input_location, MODIFY_EXPR, TREE_TYPE (var2), + var2, compare); + TREE_OPERAND (compare, 0) = comp_tgt; + compare = omit_one_operand_loc (input_location, boolean_type_node, + compare, comp_tgt); + } + + if (compare) + x = build3_loc (input_location, COND_EXPR, type, compare, + convert (type, x), lse.expr); + if (aop == OMP_ATOMIC) { x = build2_v (OMP_ATOMIC, lhsaddr, convert (type, x)); @@ -4750,28 +4858,31 @@ gfc_trans_omp_atomic (gfc_code *code) } else { - if (aop == OMP_ATOMIC_CAPTURE_NEW) - { - code = code->next; - expr2 = code->expr2; - if (expr2->expr_type == EXPR_FUNCTION - && expr2->value.function.isym - && expr2->value.function.isym->id == GFC_ISYM_CONVERSION) - expr2 = expr2->value.function.actual->expr; - - gcc_assert (expr2->expr_type == EXPR_VARIABLE); - gfc_conv_expr (&vse, code->expr1); - gfc_add_block_to_block (&block, &vse.pre); - - gfc_init_se (&lse, NULL); - gfc_conv_expr (&lse, expr2); - gfc_add_block_to_block (&block, &lse.pre); - } x = build2 (aop, type, lhsaddr, convert (type, x)); OMP_ATOMIC_MEMORY_ORDER (x) = mo; OMP_ATOMIC_WEAK (x) = atomic_code->ext.omp_clauses->weak; - x = convert (TREE_TYPE (vse.expr), x); - gfc_add_modify (&block, vse.expr, x); + if (compare && else_branch) + { + tree vtmp = create_tmp_var_raw (TREE_TYPE (x)); + DECL_CONTEXT (vtmp) = current_function_decl; + x = fold_build2_loc (input_location, MODIFY_EXPR, + TREE_TYPE (vtmp), vtmp, x); + vtmp = build4 (TARGET_EXPR, TREE_TYPE (vtmp), vtmp, + build_zero_cst (TREE_TYPE (vtmp)), NULL, NULL); + TREE_OPERAND (x, 0) = vtmp; + tree x2 = convert (TREE_TYPE (vse.expr), vtmp); + x2 = fold_build2_loc (input_location, MODIFY_EXPR, + TREE_TYPE (vse.expr), vse.expr, x2); + x2 = build3_loc (input_location, COND_EXPR, void_type_node, comp_tgt, + void_node, x2); + x = omit_one_operand_loc (input_location, TREE_TYPE (x2), x2, x); + gfc_add_expr_to_block (&block, x); + } + else + { + x = convert (TREE_TYPE (vse.expr), x); + gfc_add_modify (&block, vse.expr, x); + } } return gfc_finish_block (&block); diff --git a/gcc/testsuite/gfortran.dg/gomp/atomic-21.f90 b/gcc/testsuite/gfortran.dg/gomp/atomic-21.f90 new file mode 100644 index 0000000..febcdbb --- /dev/null +++ b/gcc/testsuite/gfortran.dg/gomp/atomic-21.f90 @@ -0,0 +1,93 @@ +! { dg-do compile } +! { dg-additional-options "-fdump-tree-original" } + +module mod +implicit none + +integer i, j, k, l, m, n +contains + +subroutine foo () + !$omp atomic release + i = i + 1 +end +end module + +module m2 +use mod +implicit none +!$omp requires atomic_default_mem_order (acq_rel) + +contains +subroutine bar () + integer v + !$omp atomic + j = j + 1 + !$omp atomic update + k = k + 1 + !$omp atomic read + v = l + !$omp atomic write + m = v + !$omp atomic capture + n = n + 1; v = n +end + +! { dg-final { scan-tree-dump-times "#pragma omp atomic release" 5 "original" } } +! { dg-final { scan-tree-dump-times "v = #pragma omp atomic capture acq_rel" 1 "original" } } +! { dg-final { scan-tree-dump-times "v = #pragma omp atomic read acquire" 1 "original" } } + +subroutine foobar() + integer :: aa, bb, cc, dd, ee, ff, gg, hh, ii, jj, kk, nn, oo, pp, qq + + !$omp atomic compare + if (ii == jj) ii = kk + +! #pragma omp atomic release +! TARGET_EXPR = *TARGET_EXPR == jj \\? kk : *TARGET_EXPR ; +! +! { dg-final { scan-tree-dump-times "TARGET_EXPR = \\*TARGET_EXPR == jj \\? kk : \\*TARGET_EXPR ;" 1 "original" } } + + !$omp atomic compare, capture + if (nn == oo) then + nn = pp + else + qq = nn + endif + +! TARGET_EXPR = #pragma omp atomic capture acq_rel +! TARGET_EXPR = NON_LVALUE_EXPR = *TARGET_EXPR == oo> ? pp : *TARGET_EXPR ;, if (TARGET_EXPR ) +! { +! <<< Unknown tree: void_cst >>> +! } +! else +! { +! qq = TARGET_EXPR ; +! }; +! +! { dg-final { scan-tree-dump-times "TARGET_EXPR = #pragma omp atomic capture acq_rel" 1 "original" } } +! { dg-final { scan-tree-dump-times "TARGET_EXPR = NON_LVALUE_EXPR = \\*TARGET_EXPR == oo> \\? pp : \\*TARGET_EXPR ;, if \\(TARGET_EXPR \\)" 1 "original" } } +! { dg-final { scan-tree-dump-times "<<< Unknown tree: void_cst >>>" 1 "original" } } +! { dg-final { scan-tree-dump-times "qq = TARGET_EXPR ;" 1 "original" } } + + !$omp atomic capture compare + aa = bb + if (bb == cc) bb = dd + +! aa = #pragma omp atomic capture acq_rel +! TARGET_EXPR = *TARGET_EXPR == cc ? dd : *TARGET_EXPR ; +! +! { dg-final { scan-tree-dump-times "aa = #pragma omp atomic capture acq_rel" 1 "original" } } +! { dg-final { scan-tree-dump-times "TARGET_EXPR = \\*TARGET_EXPR == cc \\? dd : \\*TARGET_EXPR ;" 1 "original" } } + + !$omp atomic capture compare + if (ee == ff) ee = gg + hh = ee + +! hh = #pragma omp atomic capture acq_rel +! TARGET_EXPR = *TARGET_EXPR == ff ? gg : *TARGET_EXPR ; +! +! { dg-final { scan-tree-dump-times "hh = #pragma omp atomic capture acq_rel" 1 "original" } } +! { dg-final { scan-tree-dump-times "TARGET_EXPR = \\*TARGET_EXPR == ff \\? gg : \\*TARGET_EXPR ;" 1 "original" } } +end +end module diff --git a/gcc/testsuite/gfortran.dg/gomp/atomic-25.f90 b/gcc/testsuite/gfortran.dg/gomp/atomic-25.f90 index 598ff4e..a501c1f 100644 --- a/gcc/testsuite/gfortran.dg/gomp/atomic-25.f90 +++ b/gcc/testsuite/gfortran.dg/gomp/atomic-25.f90 @@ -19,31 +19,31 @@ subroutine foo (y, e, f) d = max (e, d) !$omp atomic fail(SEQ_CST) d = min (d, f) - !$omp atomic seq_cst compare fail(relaxed) ! { dg-error "Sorry, COMPARE clause in ATOMIC at .1. is not yet supported" } + !$omp atomic seq_cst compare fail(relaxed) if (x == 7) x = 24 - !$omp atomic compare ! { dg-error "Sorry, COMPARE clause in ATOMIC at .1. is not yet supported" } + !$omp atomic compare if (x == 7) x = 24 - !$omp atomic compare ! { dg-error "Sorry, COMPARE clause in ATOMIC at .1. is not yet supported" } + !$omp atomic compare if (x == 123) x = 256 - !$omp atomic compare ! { dg-error "Sorry, COMPARE clause in ATOMIC at .1. is not yet supported" } - if (ld == f) ld = f + 5.0_mrk - !$omp atomic compare ! { dg-error "Sorry, COMPARE clause in ATOMIC at .1. is not yet supported" } + !$omp atomic compare + if (ld == f) ld = 5.0_mrk + !$omp atomic compare if (x == 9) then x = 5 endif - !$omp atomic compare update capture seq_cst fail(acquire) ! { dg-error "Sorry, COMPARE clause in ATOMIC at .1. is not yet supported" } + !$omp atomic compare update capture seq_cst fail(acquire) if (x == 42) then x = f else v = x endif - !$omp atomic capture compare weak ! { dg-error "Sorry, COMPARE clause in ATOMIC at .1. is not yet supported" } + !$omp atomic capture compare weak if (x == 42) then x = f else v = x endif - !$omp atomic capture compare fail(seq_cst) ! { dg-error "Sorry, COMPARE clause in ATOMIC at .1. is not yet supported" } + !$omp atomic capture compare fail(seq_cst) if (d == 8.0) then d = 16.0 else diff --git a/gcc/testsuite/gfortran.dg/gomp/atomic-26.f90 b/gcc/testsuite/gfortran.dg/gomp/atomic-26.f90 index 5f21d3b..6448bd9 100644 --- a/gcc/testsuite/gfortran.dg/gomp/atomic-26.f90 +++ b/gcc/testsuite/gfortran.dg/gomp/atomic-26.f90 @@ -59,7 +59,7 @@ real function bar (y, e, f) !$omp atomic compare fail ! { dg-error "Expected '\\\(' after 'fail'" } if (x == y) x = d !$omp atomic compare fail( ! { dg-error "Expected SEQ_CST, ACQUIRE or RELAXED" } - if (x == y) x = d ! { dg-error "Sorry, COMPARE clause in ATOMIC at .1. is not yet supported" "" { target *-*-* } .-1 } + if (x == y) x = d !$omp atomic compare fail() ! { dg-error "Expected SEQ_CST, ACQUIRE or RELAXED" } if (x == y) x = d !$omp atomic compare fail(foobar) ! { dg-error "Expected SEQ_CST, ACQUIRE or RELAXED" } @@ -72,4 +72,28 @@ real function bar (y, e, f) if (x == y) x = d bar = v end + +subroutine foobar + implicit none + integer :: i, j, k + + !$omp atomic compare write ! { dg-error "COMPARE clause is incompatible with READ or WRITE" } + if (i == 1) i = 5 + + !$omp atomic compare + if (k == 5) i = 7 ! { dg-error "For !.OMP ATOMIC COMPARE, the first operand in comparison at .1. must be the variable 'i' that the update statement writes into at .2." } + + !$omp atomic compare + if (j == i) i = 8 ! { dg-error "For !.OMP ATOMIC COMPARE, the first operand in comparison at .1. must be the variable 'i' that the update statement writes into at .2." } + + !$omp atomic compare + if (i == 5) i = 8 + + !$omp atomic compare + if (5 == i) i = 8 ! { dg-error "Expected scalar intrinsic variable at .1. in atomic comparison" } + + !$omp atomic compare + if (i == 5) i = i + 8 ! { dg-error "20: expr in !.OMP ATOMIC COMPARE assignment var = expr must be scalar and cannot reference var" } + +end subroutine end module -- cgit v1.1 From f3f923e51391d279adace7ae24260d87e94b1108 Mon Sep 17 00:00:00 2001 From: Olivier Hainque Date: Fri, 26 Nov 2021 21:37:46 +0000 Subject: Leverage sysroot for VxWorks The build of a VxWorks toolchain relies a lot on system headers and VxWorks has a few very specific features that require special processing. For example, different sets of headers for the kernel vs the rtp modes, which the compiler knows about by way of -mrtp on the command line. If we manage to avoid the need for fixincludes on recent versions of VxWorks (>= 7), we still need to handle at least VxWorks 6.9 at this stage. We sort of get away with locating the correct headers at run-time thanks to environment variables and various tests for -mrtp in cpp specs, but getting fixincludes to work for old configurations has always been tricky and getting a toolchain to build with c++/libstdc++ support gets trickier with every move to a more recent release. sysroot_headers_suffix_spec is a pretty powerful device to help address such issues, and this patch introduces changes that let us get advantage of it. The general idea is to leverage the assumption that compilations occur with --sysroot=$VSB_DIR on vx7 or --sysroot=$WIND_BASE/target prior to that. For the toolchains we build, this is achieved with a few configure options like: --with-sysroot --with-build-sysroot=${WIND_BASE}/target --with-specs=%{!sysroot=*:--sysroot=%:getenv(WIND_BASE /target)} This also allows simplifying the libgcc compilation flags control and we take the opportunity to merge t-vxworks7 into t-vxworks as the two files were differing only on the libgcc2 flags part. 2021-12-09 Olivier Hainque gcc/ * config/t-vxworks: Clear NATIVE_SYSTEM_HEADER_DIR. * config/vxworks.h (SYSROOT_HEADERS_SUFFIX_SPEC): Define, for VxWorks 7 and earlier. (VXWORKS_ADDITIONAL_CPP_SPEC): Simplify accordingly. (STARTFILE_PREFIX_SPEC): Adjust accordingly. * config/rs6000/vxworks.h (STARTFILE_PREFIX_SPEC): Adjust. libgcc/ * config/t-vxworks (LIBGCC2_INCLUDES): Simplify and handle both VxWorks7 and earlier. * config/t-vxworks7: Remove. * config.host: Remove special case for vxworks7. --- gcc/config/rs6000/vxworks.h | 2 +- gcc/config/t-vxworks | 8 +++++ gcc/config/vxworks.h | 74 ++++++++++++++++++++++++++++++--------------- 3 files changed, 58 insertions(+), 26 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index ca21a3a..fbe0902 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -206,7 +206,7 @@ along with GCC; see the file COPYING3. If not see #undef STARTFILE_PREFIX_SPEC #define STARTFILE_PREFIX_SPEC \ - "%{mrtp:%{!shared:%:getenv(WIND_BASE /target/lib/usr/lib/ppc/PPC32/common)}}" + "%{mrtp:%{!shared:/lib/usr/lib/ppc/PPC32/common}}" /* For aggregates passing, use the same, consistent ABI as Linux. */ #define AGGREGATE_PADDING_FIXED 0 diff --git a/gcc/config/t-vxworks b/gcc/config/t-vxworks index 0175a5f..689de14 100644 --- a/gcc/config/t-vxworks +++ b/gcc/config/t-vxworks @@ -24,6 +24,14 @@ vxworks-c.o: $(srcdir)/config/vxworks-c.c $(COMPILE) $< $(POSTCOMPILE) +# We leverage $sysroot to find target system headers only, distributed +# in a VxWorks (a)typical fashion with a different set of headers for +# rtp vs kernel mode. We setup SYSROOT_HEADERS_SUFFIX_SPEC to handle +# this, and need to clear NATIVE_SYSTEM_HEADER_DIR to prevent it from +# interfering. + +NATIVE_SYSTEM_HEADER_DIR = + # Both the kernel and RTP headers provide limits.h. They embed VxWorks # specificities and are dated on some configurations so we both need to # provide our own version and make sure the system one gets exposed. diff --git a/gcc/config/vxworks.h b/gcc/config/vxworks.h index 8210de4..a89e3d6 100644 --- a/gcc/config/vxworks.h +++ b/gcc/config/vxworks.h @@ -28,45 +28,70 @@ along with GCC; see the file COPYING3. If not see like a traditional Unix, with more external files. Most of our specs must be aware of the difference. */ -/* We look for the VxWorks header files using the environment - variables that are set in VxWorks to indicate the location of the - system header files. We use -idirafter so that the GCC's own - header-file directories (containing , etc.) come before - the VxWorks system header directories. */ +/* Help locate system headers, assuming $sysroot set to $VSB_DIR on vx7 and + $WIND_BASE/target prior to that. Specs allow tailoring for RTP vs kernel, + and -idirafter allows putting system directories after GCC's own directories + for standard headers such as or fixed include. + + Regarding fixed includes, note the effect of sysroot_headers_suffix_spec: + + For the case of VxWorks prior to 7 below, we have: + + #define SYSROOT_HEADERS_SUFFIX_SPEC "%{mrtp:/usr/h;:/h}" + + This results in + + $build_sysroot/h ---> $prefix/include-fixed + $build_sysroot/usr/h ---> $prefix/include-fixed/mrtp for -mrtp + + This is very different from what we'd get without a headers_suffix, + which would be: + + $build_sysroot ---> $prefix/include-fixed/h + /usr/h + + From (say) #include , we would find the fixed version + in the first case, not in the second. */ /* Since we provide a default -isystem, expand -isystem on the command - line early. */ + line early. Then restrict the amount of references we add when compiling + self-tests, as these may be run in contexts where the VxWorks environment + isn't available. */ -/* Self-tests may be run in contexts where the VxWorks environment isn't - available. Prevent attempts at designating the location of runtime header - files, libraries or startfiles, which would fail on unset environment - variables and aren't needed for such tests. */ #if TARGET_VXWORKS7 +/* We arrange not rely on fixed includes for vx7 and the headers spread over + common kernel/rtp directories in addition to specific ones for each mode. + Setup sysroot_headers_suffix_spec to deal with kernel/rtp distinction. */ + +#undef SYSROOT_HEADERS_SUFFIX_SPEC +#define SYSROOT_HEADERS_SUFFIX_SPEC "%{mrtp:/usr/h;:/krnl/h}" + #undef VXWORKS_ADDITIONAL_CPP_SPEC #define VXWORKS_ADDITIONAL_CPP_SPEC \ "%{!nostdinc:%{!fself-test=*: \ %{isystem*} \ - %{mrtp: -idirafter %:getenv(VSB_DIR /h) \ - -idirafter %:getenv(VSB_DIR /share/h) \ - -idirafter %:getenv(VSB_DIR /usr/h/public) \ - -idirafter %:getenv(VSB_DIR /usr/h) \ - ;: -idirafter %:getenv(VSB_DIR /h) \ - -idirafter %:getenv(VSB_DIR /share/h) \ - -idirafter %:getenv(VSB_DIR /krnl/h/system) \ - -idirafter %:getenv(VSB_DIR /krnl/h/public)}}}" + -idirafter %:getenv(VSB_DIR /h) \ + -idirafter %:getenv(VSB_DIR /share/h) \ + -idirafter =/system \ + -idirafter =/public \ + }}" #else /* TARGET_VXWORKS7 */ +/* Prior to vx7, rtp and kernel headers are fairly segregated and fixincludes + is needed on each set of headers to cope with expectations of not so old + libstdc++. A perfect use case for sysroot_headers_suffix. */ + +#undef SYSROOT_HEADERS_SUFFIX_SPEC +#define SYSROOT_HEADERS_SUFFIX_SPEC "%{mrtp:/usr/h;:/h}" + #undef VXWORKS_ADDITIONAL_CPP_SPEC #define VXWORKS_ADDITIONAL_CPP_SPEC \ "%{!nostdinc:%{!fself-test=*: \ %{isystem*} \ - %{mrtp: -idirafter %:getenv(WIND_USR /h) \ - -idirafter %:getenv(WIND_USR /h/wrn/coreip) \ - ;: -idirafter %:getenv(WIND_BASE /target/h) \ - -idirafter %:getenv(WIND_BASE /target/h/wrn/coreip) \ -}}}" + -idirafter =/wrn/coreip \ + }}" #endif @@ -119,8 +144,7 @@ along with GCC; see the file COPYING3. If not see #if TARGET_VXWORKS7 #undef STARTFILE_PREFIX_SPEC -#define STARTFILE_PREFIX_SPEC \ - "%{!fself-test=*:%:getenv(VSB_DIR /usr/lib/common)}" +#define STARTFILE_PREFIX_SPEC "/usr/lib/common" #define TLS_SYM "-u __tls__" #else #define TLS_SYM "" -- cgit v1.1 From b80e6d97a9e2425f2a8b97a436335e0abf9105db Mon Sep 17 00:00:00 2001 From: Olivier Hainque Date: Sat, 11 Dec 2021 08:46:08 +0000 Subject: Ensure VxWorks headers expose C99 features for C++ C++ relies on C99 features since C++11 and libstdc++ down to c++98 checks for C99 features at configure time. Simpler is to request C99 features from system headers unconditionally. 2021-12-11 Olivier Hainque * config/vxworks.h (VXWORKS_OS_CPP_BUILTINS): Define _C99 for C++. --- gcc/config/vxworks.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'gcc') diff --git a/gcc/config/vxworks.h b/gcc/config/vxworks.h index a89e3d6..f76141f 100644 --- a/gcc/config/vxworks.h +++ b/gcc/config/vxworks.h @@ -286,6 +286,12 @@ extern void vxworks_asm_out_destructor (rtx symbol, int priority); if (!flag_isoc99 && !c_dialect_cxx()) \ builtin_define ("_ALLOW_KEYWORD_MACROS"); \ } \ + /* C++ support relies on C99 features from C++11, even C++98 \ + for listdc++ in particular, with corresponding checks at \ + configure time. Make sure C99 features are exposed by the \ + system headers. */ \ + if (c_dialect_cxx()) \ + builtin_define("_C99"); \ } \ while (0) -- cgit v1.1 From 55fb12f12fee7313be1d3fb965e63d4c8580eb95 Mon Sep 17 00:00:00 2001 From: Olivier Hainque Date: Mon, 13 Dec 2021 08:06:46 +0000 Subject: Include yvals.h for VxWorks < 7 RTPs as well For -mrtp on VxWorks 6.9, at least inttypes.h ends up #including system headers checking that _BITS_BYTES is 8, which the system yvals.h defines. We do pre-include _yvals.h ahead of inttypes.h for this kind of purpose, but it currently assumes that only VxWorks >= 7 provides yvals.h. This results in unexpected configure checks failures, complaining about _BITS_BYTES not being 8, spotted while inspecting libstdc++ config.log for unrelated reasons. This change relaxes the guard in _yvals.h to include yvals.h for __RTP__ in addition to version >= 7. 2021-12-13 Olivier Hainque * config/vxworks/_yvals.h: #include yvals.h also if defined(__RTP__). --- gcc/config/vxworks/_yvals.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/config/vxworks/_yvals.h b/gcc/config/vxworks/_yvals.h index f8b0818..0f277e4 100644 --- a/gcc/config/vxworks/_yvals.h +++ b/gcc/config/vxworks/_yvals.h @@ -24,7 +24,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #include <_vxworks-versions.h> -#if _VXWORKS_MAJOR_GE(7) +/* #include the VxWorks yvals.h in setups we expect it to be available. + It is around for both kernel mode and rtps on VxWorks >= 7, only for + rtps prior to that. */ + +#if _VXWORKS_MAJOR_GE(7) || defined(__RTP__) /* We need to deactivate the definitions tailored for the Dinkumware intrinsics, incompatible with a compilation by G++. */ -- cgit v1.1 From 9eb8785b3fa3a180bd216cf68b53f1621628efc6 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Fri, 10 Dec 2021 11:40:54 +0100 Subject: inline: fix ICE with -fprofile-generate PR ipa/103636 gcc/ChangeLog: * ipa-inline.c (can_inline_edge_p): Move logic checking no_profile_instrument_function logic to ... (can_early_inline_edge_p): ... here. --- gcc/ipa-inline.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) (limited to 'gcc') diff --git a/gcc/ipa-inline.c b/gcc/ipa-inline.c index 54cd085..a1c312f1 100644 --- a/gcc/ipa-inline.c +++ b/gcc/ipa-inline.c @@ -396,22 +396,6 @@ can_inline_edge_p (struct cgraph_edge *e, bool report, e->inline_failed = CIF_SANITIZE_ATTRIBUTE_MISMATCH; inlinable = false; } - else if (profile_arc_flag - && (lookup_attribute ("no_profile_instrument_function", - DECL_ATTRIBUTES (caller->decl)) == NULL_TREE) - != (lookup_attribute ("no_profile_instrument_function", - DECL_ATTRIBUTES (callee->decl)) == NULL_TREE)) - { - cgraph_node *origin = caller; - while (origin->clone_of) - origin = origin->clone_of; - - if (!DECL_STRUCT_FUNCTION (origin->decl)->always_inline_functions_inlined) - { - e->inline_failed = CIF_UNSPECIFIED; - inlinable = false; - } - } if (!inlinable && report) report_inline_failed_reason (e); @@ -637,6 +621,8 @@ can_inline_edge_by_limits_p (struct cgraph_edge *e, bool report, static bool can_early_inline_edge_p (struct cgraph_edge *e) { + cgraph_node *caller = (e->caller->inlined_to + ? e->caller->inlined_to : e->caller); struct cgraph_node *callee = e->callee->ultimate_alias_target (); /* Early inliner might get called at WPA stage when IPA pass adds new function. In this case we cannot really do any of early inlining @@ -660,6 +646,13 @@ can_early_inline_edge_p (struct cgraph_edge *e) " edge not inlinable: not in SSA form\n"); return false; } + else if (profile_arc_flag + && ((lookup_attribute ("no_profile_instrument_function", + DECL_ATTRIBUTES (caller->decl)) == NULL_TREE) + != (lookup_attribute ("no_profile_instrument_function", + DECL_ATTRIBUTES (callee->decl)) == NULL_TREE))) + return false; + if (!can_inline_edge_p (e, true, true) || !can_inline_edge_by_limits_p (e, true, false, true)) return false; -- cgit v1.1 From 0caf592d6ae836a99907841fccd31c4c5f180e8d Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Mon, 13 Dec 2021 14:11:59 +0000 Subject: aarch64: Add support for Armv8.8-a memory operations and memcpy expansion This patch adds the +mops architecture extension flag from the 2021 Arm Architecture extensions, Armv8.8-a. The +mops extensions introduce instructions to accelerate the memcpy, memset, memmove standard functions. The first patch here uses the instructions in the inline memcpy expansion. Further patches in the series will use similar instructions to inline memmove and memset. A new param, aarch64-mops-memcpy-size-threshold, is introduced to control the size threshold above which to emit the new sequence. Its default setting is 256 bytes, which is the same as the current threshold above which we'd emit a libcall. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def (mops): Define. * config/aarch64/aarch64.c (aarch64_expand_cpymem_mops): Define. (aarch64_expand_cpymem): Define. * config/aarch64/aarch64.h (AARCH64_FL_MOPS): Define. (AARCH64_ISA_MOPS): Define. (TARGET_MOPS): Define. (MOVE_RATIO): Adjust for TARGET_MOPS. * config/aarch64/aarch64.md ("unspec"): Add UNSPEC_CPYMEM. (aarch64_cpymemdi): New pattern. (cpymemdi): Adjust for TARGET_MOPS. * config/aarch64/aarch64.opt (aarch64-mops-memcpy-size-threshol): New param. * doc/invoke.texi (AArch64 Options): Document +mops. gcc/testsuite/ChangeLog: * gcc.target/aarch64/mops_1.c: New test. --- gcc/config/aarch64/aarch64-option-extensions.def | 3 ++ gcc/config/aarch64/aarch64.c | 62 ++++++++++++++++++++---- gcc/config/aarch64/aarch64.h | 20 +++++--- gcc/config/aarch64/aarch64.md | 17 ++++++- gcc/config/aarch64/aarch64.opt | 4 ++ gcc/doc/invoke.texi | 3 ++ gcc/testsuite/gcc.target/aarch64/mops_1.c | 57 ++++++++++++++++++++++ 7 files changed, 149 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/mops_1.c (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index b61f1df..3f449fb 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -235,4 +235,7 @@ AARCH64_OPT_EXTENSION("pauth", AARCH64_FL_PAUTH, 0, 0, false, "paca pacg") /* Enabling/Disabling "ls64" only changes "ls64". */ AARCH64_OPT_EXTENSION("ls64", AARCH64_FL_LS64, 0, 0, false, "") +/* Enabling/disabling "mops" only changes "mops". */ +AARCH64_OPT_EXTENSION("mops", AARCH64_FL_MOPS, 0, 0, false, "") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index be24b73..bd754e4 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -23568,6 +23568,28 @@ aarch64_copy_one_block_and_progress_pointers (rtx *src, rtx *dst, *dst = aarch64_progress_pointer (*dst); } +/* Expand a cpymem using the MOPS extension. OPERANDS are taken + from the cpymem pattern. Return true iff we succeeded. */ +static bool +aarch64_expand_cpymem_mops (rtx *operands) +{ + if (!TARGET_MOPS) + return false; + rtx addr_dst = XEXP (operands[0], 0); + rtx addr_src = XEXP (operands[1], 0); + rtx sz_reg = operands[2]; + + if (!REG_P (sz_reg)) + sz_reg = force_reg (DImode, sz_reg); + if (!REG_P (addr_dst)) + addr_dst = force_reg (DImode, addr_dst); + if (!REG_P (addr_src)) + addr_src = force_reg (DImode, addr_src); + emit_insn (gen_aarch64_cpymemdi (addr_dst, addr_src, sz_reg)); + + return true; +} + /* Expand cpymem, as if from a __builtin_memcpy. Return true if we succeed, otherwise return false, indicating that a libcall to memcpy should be emitted. */ @@ -23581,19 +23603,25 @@ aarch64_expand_cpymem (rtx *operands) rtx base; machine_mode cur_mode = BLKmode; - /* Only expand fixed-size copies. */ + /* Variable-sized memcpy can go through the MOPS expansion if available. */ if (!CONST_INT_P (operands[2])) - return false; + return aarch64_expand_cpymem_mops (operands); unsigned HOST_WIDE_INT size = INTVAL (operands[2]); - /* Try to inline up to 256 bytes. */ - unsigned HOST_WIDE_INT max_copy_size = 256; + /* Try to inline up to 256 bytes or use the MOPS threshold if available. */ + unsigned HOST_WIDE_INT max_copy_size + = TARGET_MOPS ? aarch64_mops_memcpy_size_threshold : 256; bool size_p = optimize_function_for_size_p (cfun); + /* Large constant-sized cpymem should go through MOPS when possible. + It should be a win even for size optimization in the general case. + For speed optimization the choice between MOPS and the SIMD sequence + depends on the size of the copy, rather than number of instructions, + alignment etc. */ if (size > max_copy_size) - return false; + return aarch64_expand_cpymem_mops (operands); int copy_bits = 256; @@ -23643,9 +23671,9 @@ aarch64_expand_cpymem (rtx *operands) nops += 2; n -= mode_bits; - /* Emit trailing copies using overlapping unaligned accesses - this is - smaller and faster. */ - if (n > 0 && n < copy_bits / 2) + /* Emit trailing copies using overlapping unaligned accesses + (when !STRICT_ALIGNMENT) - this is smaller and faster. */ + if (n > 0 && n < copy_bits / 2 && !STRICT_ALIGNMENT) { machine_mode next_mode = smallest_mode_for_size (n, MODE_INT); int n_bits = GET_MODE_BITSIZE (next_mode).to_constant (); @@ -23657,9 +23685,25 @@ aarch64_expand_cpymem (rtx *operands) } rtx_insn *seq = get_insns (); end_sequence (); + /* MOPS sequence requires 3 instructions for the memory copying + 1 to move + the constant size into a register. */ + unsigned mops_cost = 3 + 1; + + /* If MOPS is available at this point we don't consider the libcall as it's + not a win even on code size. At this point only consider MOPS if + optimizing for size. For speed optimizations we will have chosen between + the two based on copy size already. */ + if (TARGET_MOPS) + { + if (size_p && mops_cost < nops) + return aarch64_expand_cpymem_mops (operands); + emit_insn (seq); + return true; + } /* A memcpy libcall in the worst case takes 3 instructions to prepare the - arguments + 1 for the call. */ + arguments + 1 for the call. When MOPS is not available and we're + optimizing for size a libcall may be preferable. */ unsigned libcall_cost = 4; if (size_p && libcall_cost < nops) return false; diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 2792bb2..79d0bcd 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -231,14 +231,17 @@ extern unsigned aarch64_architecture_version; /* Pointer Authentication (PAUTH) extension. */ #define AARCH64_FL_PAUTH (1ULL << 40) +/* Armv9.0-A. */ +#define AARCH64_FL_V9 (1ULL << 41) /* Armv9.0-A Architecture. */ + /* 64-byte atomic load/store extensions. */ -#define AARCH64_FL_LS64 (1ULL << 41) +#define AARCH64_FL_LS64 (1ULL << 42) /* Armv8.7-a architecture extensions. */ -#define AARCH64_FL_V8_7 (1ULL << 42) +#define AARCH64_FL_V8_7 (1ULL << 43) -/* Armv9.0-A. */ -#define AARCH64_FL_V9 (1ULL << 43) /* Armv9.0-A Architecture. */ +/* Hardware memory operation instructions. */ +#define AARCH64_FL_MOPS (1ULL << 44) /* Has FP and SIMD. */ #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) @@ -310,6 +313,7 @@ extern unsigned aarch64_architecture_version; #define AARCH64_ISA_V8_R (aarch64_isa_flags & AARCH64_FL_V8_R) #define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH) #define AARCH64_ISA_V9 (aarch64_isa_flags & AARCH64_FL_V9) +#define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) /* Crypto is an optional extension to AdvSIMD. */ #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) @@ -401,6 +405,9 @@ extern unsigned aarch64_architecture_version; /* PAUTH instructions are enabled through +pauth. */ #define TARGET_PAUTH (AARCH64_ISA_PAUTH) +/* MOPS instructions are enabled through +mops. */ +#define TARGET_MOPS (AARCH64_ISA_MOPS) + /* Make sure this is always defined so we don't have to check for ifdefs but rather use normal ifs. */ #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT @@ -1046,9 +1053,10 @@ typedef struct 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient for both size and speed of copy, so we will instead use the "cpymem" standard name to implement the copy. This logic does not apply when - targeting -mstrict-align, so keep a sensible default in that case. */ + targeting -mstrict-align or TARGET_MOPS, so keep a sensible default in + that case. */ #define MOVE_RATIO(speed) \ - (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) + ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) /* Like MOVE_RATIO, without -mstrict-align, make decisions in "setmem" when we would use more than 3 scalar instructions. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5297b2d..d623c1b 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -143,6 +143,7 @@ UNSPEC_AUTIBSP UNSPEC_CALLEE_ABI UNSPEC_CASESI + UNSPEC_CPYMEM UNSPEC_CRC32B UNSPEC_CRC32CB UNSPEC_CRC32CH @@ -1572,6 +1573,18 @@ } ) +(define_insn "aarch64_cpymemdi" + [(parallel [ + (set (match_operand:DI 2 "register_operand" "+&r") (const_int 0)) + (clobber (match_operand:DI 0 "register_operand" "+&r")) + (clobber (match_operand:DI 1 "register_operand" "+&r")) + (set (mem:BLK (match_dup 0)) + (unspec:BLK [(mem:BLK (match_dup 1)) (match_dup 2)] UNSPEC_CPYMEM))])] + "TARGET_MOPS" + "cpyfp\t[%x0]!, [%x1]!, %x2!\;cpyfm\t[%x0]!, [%x1]!, %x2!\;cpyfe\t[%x0]!, [%x1]!, %x2!" + [(set_attr "length" "12")] +) + ;; 0 is dst ;; 1 is src ;; 2 is size of copy in bytes @@ -1580,9 +1593,9 @@ (define_expand "cpymemdi" [(match_operand:BLK 0 "memory_operand") (match_operand:BLK 1 "memory_operand") - (match_operand:DI 2 "immediate_operand") + (match_operand:DI 2 "general_operand") (match_operand:DI 3 "immediate_operand")] - "!STRICT_ALIGNMENT" + "!STRICT_ALIGNMENT || TARGET_MOPS" { if (aarch64_expand_cpymem (operands)) DONE; diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 32191cf..7445ed1 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -280,3 +280,7 @@ Target Joined UInteger Var(aarch64_autovec_preference) Init(0) IntegerRange(0, 4 -param=aarch64-loop-vect-issue-rate-niters= Target Joined UInteger Var(aarch64_loop_vect_issue_rate_niters) Init(6) IntegerRange(0, 65536) Param + +-param=aarch64-mops-memcpy-size-threshold= +Target Joined UInteger Var(aarch64_mops_memcpy_size_threshold) Init(256) Param +Constant memcpy size in bytes above which to start using MOPS sequence. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9b4371b..2424a5b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -19144,6 +19144,9 @@ prior to Armv8.2-A is not supported. @item ls64 Enable the 64-byte atomic load and store instructions for accelerators. This option is enabled by default for @option{-march=armv8.7-a}. +@item mops +Enable the instructions to accelerate memory operations like @code{memcpy}, +@code{memmove}, @code{memset}. @item flagm Enable the Flag Manipulation instructions Extension. @item pauth diff --git a/gcc/testsuite/gcc.target/aarch64/mops_1.c b/gcc/testsuite/gcc.target/aarch64/mops_1.c new file mode 100644 index 0000000..661c141 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/mops_1.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.6-a+mops --param=aarch64-mops-memcpy-size-threshold=0" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include + +/* We want to inline variable-sized memcpy. +** do_it_cpy: +** cpyfp \[x1\]\!, \[x0\]\!, x2\! +** cpyfm \[x1\]\!, \[x0\]\!, x2\! +** cpyfe \[x1\]\!, \[x0\]\!, x2\! +** ret +*/ +void do_it_cpy (char * in, char * out, size_t size) +{ + __builtin_memcpy (out, in, size); +} + +/* +** do_it_cpy_large: +** mov x2, 1024 +** cpyfp \[x1\]\!, \[x0\]!, x2\! +** cpyfm \[x1\]\!, \[x0\]!, x2\! +** cpyfe \[x1\]\!, \[x0\]\!, x2\! +** ret +*/ +void do_it_cpy_large (char * in, char * out) +{ + __builtin_memcpy (out, in, 1024); +} + +/* +** do_it_cpy_127: +** mov x2, 127 +** cpyfp \[x1\]\!, \[x0\]!, x2\! +** cpyfm \[x1\]\!, \[x0\]!, x2\! +** cpyfe \[x1\]\!, \[x0\]\!, x2\! +** ret +*/ +void do_it_cpy_127 (char * in, char * out) +{ + __builtin_memcpy (out, in, 127); +} + +/* +** do_it_cpy_128: +** mov x2, 128 +** cpyfp \[x1\]\!, \[x0\]!, x2\! +** cpyfm \[x1\]\!, \[x0\]!, x2\! +** cpyfe \[x1\]\!, \[x0\]\!, x2\! +** ret +*/ +void do_it_cpy_128 (char * in, char * out) +{ + __builtin_memcpy (out, in, 128); +} + -- cgit v1.1 From bb768f8b45aa7ccf12774aa0c00b295032ee7c47 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Mon, 13 Dec 2021 14:13:21 +0000 Subject: aarch64: Add memmove expansion for +mops This second patch in the series adds an inline movmem expansion for TARGET_MOPS that emits the recommended sequence. A new param aarch64-mops-memmove-size-threshold is added to control the memmove size threshold for this expansion. Its default value is zero to be consistent with the current behaviour where we always emit a libcall, as we don't currently have a movmem inline expansion (we should add a compatible-everywhere inline expansion, but that's for the future), so we should always prefer to emit the MOPS sequence when available in lieu of a libcall. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64.md (aarch64_movmemdi): Define. (movmemdi): Define. (unspec): Add UNSPEC_MOVMEM. * config/aarch64/aarch64.opt (aarch64-mops-memmove-size-threshold): New param. gcc/testsuite/ChangeLog: * gcc.target/aarch64/mops_2.c: New test. --- gcc/config/aarch64/aarch64.md | 47 +++++++++++++++++++++++++ gcc/config/aarch64/aarch64.opt | 4 +++ gcc/testsuite/gcc.target/aarch64/mops_2.c | 57 +++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/mops_2.c (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index d623c1b..b71c171 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -189,6 +189,7 @@ UNSPEC_LD3_LANE UNSPEC_LD4_LANE UNSPEC_MB + UNSPEC_MOVMEM UNSPEC_NOP UNSPEC_PACIA1716 UNSPEC_PACIB1716 @@ -1603,6 +1604,52 @@ } ) +(define_insn "aarch64_movmemdi" + [(parallel [ + (set (match_operand:DI 2 "register_operand" "+&r") (const_int 0)) + (clobber (match_operand:DI 0 "register_operand" "+&r")) + (clobber (match_operand:DI 1 "register_operand" "+&r")) + (set (mem:BLK (match_dup 0)) + (unspec:BLK [(mem:BLK (match_dup 1)) (match_dup 2)] UNSPEC_MOVMEM))])] + "TARGET_MOPS" + "cpyp\t[%x0]!, [%x1]!, %x2!\;cpym\t[%x0]!, [%x1]!, %x2!\;cpye\t[%x0]!, [%x1]!, %x2!" + [(set_attr "length" "12")] +) + +;; 0 is dst +;; 1 is src +;; 2 is size of copy in bytes +;; 3 is alignment + +(define_expand "movmemdi" + [(match_operand:BLK 0 "memory_operand") + (match_operand:BLK 1 "memory_operand") + (match_operand:DI 2 "general_operand") + (match_operand:DI 3 "immediate_operand")] + "TARGET_MOPS" +{ + rtx sz_reg = operands[2]; + /* For constant-sized memmoves check the threshold. + FIXME: We should add a non-MOPS memmove expansion for smaller, + constant-sized memmove to avoid going to a libcall. */ + if (CONST_INT_P (sz_reg) + && INTVAL (sz_reg) < aarch64_mops_memmove_size_threshold) + FAIL; + + rtx addr_dst = XEXP (operands[0], 0); + rtx addr_src = XEXP (operands[1], 0); + + if (!REG_P (sz_reg)) + sz_reg = force_reg (DImode, sz_reg); + if (!REG_P (addr_dst)) + addr_dst = force_reg (DImode, addr_dst); + if (!REG_P (addr_src)) + addr_src = force_reg (DImode, addr_src); + emit_insn (gen_aarch64_movmemdi (addr_dst, addr_src, sz_reg)); + DONE; +} +) + ;; 0 is dst ;; 1 is val ;; 2 is size of copy in bytes diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 7445ed1..33788ff 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -284,3 +284,7 @@ Target Joined UInteger Var(aarch64_loop_vect_issue_rate_niters) Init(6) IntegerR -param=aarch64-mops-memcpy-size-threshold= Target Joined UInteger Var(aarch64_mops_memcpy_size_threshold) Init(256) Param Constant memcpy size in bytes above which to start using MOPS sequence. + +-param=aarch64-mops-memmove-size-threshold= +Target Joined UInteger Var(aarch64_mops_memmove_size_threshold) Init(0) Param +Constant memmove size in bytes above which to start using MOPS sequence. diff --git a/gcc/testsuite/gcc.target/aarch64/mops_2.c b/gcc/testsuite/gcc.target/aarch64/mops_2.c new file mode 100644 index 0000000..6fda4dd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/mops_2.c @@ -0,0 +1,57 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.6-a+mops --param=aarch64-mops-memmove-size-threshold=0" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include + +/* We want to inline variable-sized memmove. +** do_it_mov: +** cpyp \[x1\]\!, \[x0\]\!, x2\! +** cpym \[x1\]\!, \[x0\]\!, x2\! +** cpye \[x1\]\!, \[x0\]\!, x2\! +** ret +*/ +void do_it_mov (char * in, char * out, size_t size) +{ + __builtin_memmove (out, in, size); +} + +/* +** do_it_mov_large: +** mov x2, 1024 +** cpyp \[x1\]\!, \[x0\]!, x2\! +** cpym \[x1\]\!, \[x0\]!, x2\! +** cpye \[x1\]\!, \[x0\]\!, x2\! +** ret +*/ +void do_it_mov_large (char * in, char * out) +{ + __builtin_memmove (out, in, 1024); +} + +/* +** do_it_mov_127: +** mov x2, 127 +** cpyp \[x1\]\!, \[x0\]!, x2\! +** cpym \[x1\]\!, \[x0\]!, x2\! +** cpye \[x1\]\!, \[x0\]\!, x2\! +** ret +*/ +void do_it_mov_127 (char * in, char * out) +{ + __builtin_memmove (out, in, 127); +} + +/* +** do_it_mov_128: +** mov x2, 128 +** cpyp \[x1\]\!, \[x0\]!, x2\! +** cpym \[x1\]\!, \[x0\]!, x2\! +** cpye \[x1\]\!, \[x0\]\!, x2\! +** ret +*/ +void do_it_mov_128 (char * in, char * out) +{ + __builtin_memmove (out, in, 128); +} + -- cgit v1.1 From d3bd985e799b63e2133e89870472ac36d06015d3 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Mon, 13 Dec 2021 14:14:21 +0000 Subject: aarch64: Use +mops to inline memset operations This 3rd patch in the series adds an inline sequence for the memset operation. The aarch64-mops-memset-size-threshold param is added to control the size threshold for the sequence. Its default setting is 256, which may seem a bit high, but it is consistent with the current SIMD memset inline sequence limit, and future CPU tunings can override it easily as needed. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64.c (aarch64_expand_setmem_mops): Define. (aarch64_expand_setmem): Adjust for TARGET_MOPS. * config/aarch64/aarch64.h (CLEAR_RATIO): Adjust for TARGET_MOPS. (SET_RATIO): Likewise. * config/aarch64/aarch64.md ("unspec"): Add UNSPEC_SETMEM. (aarch64_setmemdi): Define. (setmemdi): Adjust for TARGET_MOPS. * config/aarch64/aarch64.opt (aarch64-mops-memset-size-threshold): New param. gcc/testsuite/ChangeLog: * gcc.target/aarch64/mops_3.c: New test. --- gcc/config/aarch64/aarch64.c | 93 ++++++++++++++++++++++++------- gcc/config/aarch64/aarch64.h | 4 +- gcc/config/aarch64/aarch64.md | 20 +++++-- gcc/config/aarch64/aarch64.opt | 4 ++ gcc/testsuite/gcc.target/aarch64/mops_3.c | 85 ++++++++++++++++++++++++++++ 5 files changed, 181 insertions(+), 25 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/mops_3.c (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index bd754e4..d11a40c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -23754,6 +23754,28 @@ aarch64_set_one_block_and_progress_pointer (rtx src, rtx *dst, *dst = aarch64_progress_pointer (*dst); } +/* Expand a setmem using the MOPS instructions. OPERANDS are the same + as for the setmem pattern. Return true iff we succeed. */ +static bool +aarch64_expand_setmem_mops (rtx *operands) +{ + if (!TARGET_MOPS) + return false; + + rtx addr_dst = XEXP (operands[0], 0); + rtx sz_reg = operands[1]; + rtx val = operands[2]; + + if (!REG_P (sz_reg)) + sz_reg = force_reg (DImode, sz_reg); + if (!REG_P (addr_dst)) + addr_dst = force_reg (DImode, addr_dst); + if (!REG_P (val) && val != CONST0_RTX (QImode)) + val = force_reg (QImode, val); + emit_insn (gen_aarch64_setmemdi (addr_dst, val, sz_reg)); + return true; +} + /* Expand setmem, as if from a __builtin_memset. Return true if we succeed, otherwise return false. */ @@ -23767,39 +23789,59 @@ aarch64_expand_setmem (rtx *operands) rtx base; machine_mode cur_mode = BLKmode, next_mode; - /* We can't do anything smart if the amount to copy is not constant. */ - if (!CONST_INT_P (operands[1])) - return false; + /* If we don't have SIMD registers or the size is variable use the MOPS + inlined sequence if possible. */ + if (!CONST_INT_P (operands[1]) || !TARGET_SIMD) + return aarch64_expand_setmem_mops (operands); bool size_p = optimize_function_for_size_p (cfun); - /* Default the maximum to 256-bytes. */ + /* Default the maximum to 256-bytes when considering only libcall vs + SIMD broadcast sequence. */ unsigned max_set_size = 256; len = INTVAL (operands[1]); - - /* Upper bound check. */ - if (len > max_set_size) + if (len > max_set_size && !TARGET_MOPS) return false; + int cst_val = !!(CONST_INT_P (val) && (INTVAL (val) != 0)); + /* The MOPS sequence takes: + 3 instructions for the memory storing + + 1 to move the constant size into a reg + + 1 if VAL is a non-zero constant to move into a reg + (zero constants can use XZR directly). */ + unsigned mops_cost = 3 + 1 + cst_val; + /* A libcall to memset in the worst case takes 3 instructions to prepare + the arguments + 1 for the call. */ + unsigned libcall_cost = 4; + + /* Upper bound check. For large constant-sized setmem use the MOPS sequence + when available. */ + if (TARGET_MOPS + && len >= (unsigned HOST_WIDE_INT) aarch64_mops_memset_size_threshold) + return aarch64_expand_setmem_mops (operands); + /* Attempt a sequence with a vector broadcast followed by stores. - Count the number of operations involved to see if it's worth it for - code size. */ + Count the number of operations involved to see if it's worth it + against the alternatives. A simple counter simd_ops on the + algorithmically-relevant operations is used rather than an rtx_insn count + as all the pointer adjusmtents and mode reinterprets will be optimized + away later. */ start_sequence (); - unsigned nops = 0; + unsigned simd_ops = 0; + base = copy_to_mode_reg (Pmode, XEXP (dst, 0)); dst = adjust_automodify_address (dst, VOIDmode, base, 0); /* Prepare the val using a DUP/MOVI v0.16B, val. */ src = expand_vector_broadcast (V16QImode, val); src = force_reg (V16QImode, src); - nops++; + simd_ops++; /* Convert len to bits to make the rest of the code simpler. */ n = len * BITS_PER_UNIT; /* Maximum amount to copy in one go. We allow 256-bit chunks based on the - AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS tuning parameter. setmem expand - pattern is only turned on for TARGET_SIMD. */ + AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS tuning parameter. */ const int copy_limit = (aarch64_tune_params.extra_tuning_flags & AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS) ? GET_MODE_BITSIZE (TImode) : 256; @@ -23817,7 +23859,7 @@ aarch64_expand_setmem (rtx *operands) mode_bits = GET_MODE_BITSIZE (cur_mode).to_constant (); aarch64_set_one_block_and_progress_pointer (src, &dst, cur_mode); - nops++; + simd_ops++; n -= mode_bits; /* Do certain trailing copies as overlapping if it's going to be @@ -23835,12 +23877,25 @@ aarch64_expand_setmem (rtx *operands) } rtx_insn *seq = get_insns (); end_sequence (); - /* A call to memset in the worst case requires 3 instructions to prepare - the arguments + 1 for the call. Prefer the inline sequence for size if - it is no longer than that. */ - if (size_p && nops > 4) - return false; + if (size_p) + { + /* When optimizing for size we have 3 options: the SIMD broadcast sequence, + call to memset or the MOPS expansion. */ + if (TARGET_MOPS + && mops_cost <= libcall_cost + && mops_cost <= simd_ops) + return aarch64_expand_setmem_mops (operands); + /* If MOPS is not available or not shorter pick a libcall if the SIMD + sequence is too long. */ + else if (libcall_cost < simd_ops) + return false; + emit_insn (seq); + return true; + } + + /* At this point the SIMD broadcast sequence is the best choice when + optimizing for speed. */ emit_insn (seq); return true; } diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 79d0bcd..2478d0d 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -1063,14 +1063,14 @@ typedef struct Otherwise follow a sensible default: when optimizing for size, give a better estimate of the length of a memset call, but use the default otherwise. */ #define CLEAR_RATIO(speed) \ - (!STRICT_ALIGNMENT ? 4 : (speed) ? 15 : AARCH64_CALL_RATIO) + (!STRICT_ALIGNMENT ? (TARGET_MOPS ? 0 : 4) : (speed) ? 15 : AARCH64_CALL_RATIO) /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant. Without -mstrict-align, make decisions in "setmem". Otherwise follow a sensible default: when optimizing for size adjust the ratio to account for the overhead of loading the constant. */ #define SET_RATIO(speed) \ - (!STRICT_ALIGNMENT ? 0 : (speed) ? 15 : AARCH64_CALL_RATIO - 2) + ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 0 : (speed) ? 15 : AARCH64_CALL_RATIO - 2) /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is rarely a good idea in straight-line code since it adds an extra address diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index b71c171..9e50a26 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -204,6 +204,7 @@ UNSPEC_SABDL2 UNSPEC_SADALP UNSPEC_SCVTF + UNSPEC_SETMEM UNSPEC_SISD_NEG UNSPEC_SISD_SSHL UNSPEC_SISD_USHL @@ -1650,18 +1651,29 @@ } ) +(define_insn "aarch64_setmemdi" + [(parallel [ + (set (match_operand:DI 2 "register_operand" "+&r") (const_int 0)) + (clobber (match_operand:DI 0 "register_operand" "+&r")) + (set (mem:BLK (match_dup 0)) + (unspec:BLK [(match_operand:QI 1 "aarch64_reg_or_zero" "rZ") + (match_dup 2)] UNSPEC_SETMEM))])] + "TARGET_MOPS" + "setp\t[%x0]!, %x2!, %x1\;setm\t[%x0]!, %x2!, %x1\;sete\t[%x0]!, %x2!, %x1" + [(set_attr "length" "12")] +) + ;; 0 is dst ;; 1 is val ;; 2 is size of copy in bytes ;; 3 is alignment - (define_expand "setmemdi" [(set (match_operand:BLK 0 "memory_operand") ;; Dest (match_operand:QI 2 "nonmemory_operand")) ;; Value - (use (match_operand:DI 1 "immediate_operand")) ;; Length + (use (match_operand:DI 1 "general_operand")) ;; Length (match_operand 3 "immediate_operand")] ;; Align - "TARGET_SIMD" -{ + "TARGET_SIMD || TARGET_MOPS" + { if (aarch64_expand_setmem (operands)) DONE; diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 33788ff..264739e 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -288,3 +288,7 @@ Constant memcpy size in bytes above which to start using MOPS sequence. -param=aarch64-mops-memmove-size-threshold= Target Joined UInteger Var(aarch64_mops_memmove_size_threshold) Init(0) Param Constant memmove size in bytes above which to start using MOPS sequence. + +-param=aarch64-mops-memset-size-threshold= +Target Joined UInteger Var(aarch64_mops_memset_size_threshold) Init(256) Param +Constant memset size in bytes from which to start using MOPS sequence. diff --git a/gcc/testsuite/gcc.target/aarch64/mops_3.c b/gcc/testsuite/gcc.target/aarch64/mops_3.c new file mode 100644 index 0000000..0eda2ff --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/mops_3.c @@ -0,0 +1,85 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.6-a+mops --param=aarch64-mops-memset-size-threshold=0" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include + +/* We want to inline variable-sized memset. +** do_it_set: +** setp \[x0\]\!, x2\!, x1 +** setm \[x0\]\!, x2\!, x1 +** sete \[x0\]\!, x2\!, x1 +** ret +*/ +void do_it_set (char * out, int n, size_t size) +{ + __builtin_memset (out, n, size); +} + +/* +** do_it_set_large: +** mov w2, 1 +** mov x1, 1024 +** setp \[x0\]\!, x1\!, x2 +** setm \[x0\]\!, x1\!, x2 +** sete \[x0\]\!, x1\!, x2 +** ret +*/ +void do_it_set_large (char * out) +{ + __builtin_memset (out, 1, 1024); +} + +/* +** do_it_set_256: +** mov w2, 1 +** mov x1, 256 +** setp \[x0\]\!, x1\!, x2 +** setm \[x0\]\!, x1\!, x2 +** sete \[x0\]\!, x1\!, x2 +** ret +*/ +void do_it_set_256 (char * out) +{ + __builtin_memset (out, 1, 256); +} + +/* +** do_it_set_255: +** mov w2, 1 +** mov x1, 255 +** setp \[x0\]\!, x1\!, x2 +** setm \[x0\]\!, x1\!, x2 +** sete \[x0\]\!, x1\!, x2 +** ret +*/ +void do_it_set_255 (char * out) +{ + __builtin_memset (out, 1, 255); +} + +/* +** do_it_set_0: +** setp \[x0\]\!, x1\!, xzr +** setm \[x0\]\!, x1\!, xzr +** sete \[x0\]\!, x1\!, xzr +** ret +*/ +void do_it_set_0 (char * out, size_t n) +{ + __builtin_memset (out, 0, n); +} + +/* +** do_it_set_0_255: +** mov x1, 255 +** setp \[x0\]\!, x1\!, xzr +** setm \[x0\]\!, x1\!, xzr +** sete \[x0\]\!, x1\!, xzr +** ret +*/ +void do_it_set_0_255 (char * out) +{ + __builtin_memset (out, 0, 255); +} + -- cgit v1.1 From 5954b4d415f6424f1232c6b22a772ce184773f54 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Mon, 13 Dec 2021 14:15:16 +0000 Subject: aarch64: Add command-line support for Armv8.8-a This final patch in the series is much simpler and adds command-line support for -march=armv8.8-a, making use of the +mops features added in the previous patches. Bootstrapped and tested on aarch64-none-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64-arches.def (armv8.8-a): Define. * config/aarch64/aarch64.h (AARCH64_FL_V8_8): Define. (AARCH64_FL_FOR_ARCH8_8): Define. * doc/invoke.texi: Document -march=armv8.8-a. --- gcc/config/aarch64/aarch64-arches.def | 1 + gcc/config/aarch64/aarch64.h | 5 +++++ gcc/doc/invoke.texi | 4 +++- 3 files changed, 9 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def index a3b32e0..1b5f062 100644 --- a/gcc/config/aarch64/aarch64-arches.def +++ b/gcc/config/aarch64/aarch64-arches.def @@ -38,6 +38,7 @@ AARCH64_ARCH("armv8.4-a", generic, 8_4A, 8, AARCH64_FL_FOR_ARCH8_4) AARCH64_ARCH("armv8.5-a", generic, 8_5A, 8, AARCH64_FL_FOR_ARCH8_5) AARCH64_ARCH("armv8.6-a", generic, 8_6A, 8, AARCH64_FL_FOR_ARCH8_6) AARCH64_ARCH("armv8.7-a", generic, 8_7A, 8, AARCH64_FL_FOR_ARCH8_7) +AARCH64_ARCH("armv8.8-a", generic, 8_8A, 8, AARCH64_FL_FOR_ARCH8_8) AARCH64_ARCH("armv8-r", generic, 8R , 8, AARCH64_FL_FOR_ARCH8_R) AARCH64_ARCH("armv9-a", generic, 9A , 9, AARCH64_FL_FOR_ARCH9) diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 2478d0d..5a590aa 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -243,6 +243,9 @@ extern unsigned aarch64_architecture_version; /* Hardware memory operation instructions. */ #define AARCH64_FL_MOPS (1ULL << 44) +/* Armv8.8-a architecture extensions. */ +#define AARCH64_FL_V8_8 (1ULL << 45) + /* Has FP and SIMD. */ #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) @@ -269,6 +272,8 @@ extern unsigned aarch64_architecture_version; | AARCH64_FL_I8MM | AARCH64_FL_BF16) #define AARCH64_FL_FOR_ARCH8_7 \ (AARCH64_FL_FOR_ARCH8_6 | AARCH64_FL_V8_7 | AARCH64_FL_LS64) +#define AARCH64_FL_FOR_ARCH8_8 \ + (AARCH64_FL_FOR_ARCH8_7 | AARCH64_FL_V8_8 | AARCH64_FL_MOPS) #define AARCH64_FL_FOR_ARCH8_R \ (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_R) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2424a5b..221c7c3 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -18853,6 +18853,7 @@ and the features that they enable by default: @item @samp{armv8.5-a} @tab Armv8.5-A @tab @samp{armv8.4-a}, @samp{+sb}, @samp{+ssbs}, @samp{+predres} @item @samp{armv8.6-a} @tab Armv8.6-A @tab @samp{armv8.5-a}, @samp{+bf16}, @samp{+i8mm} @item @samp{armv8.7-a} @tab Armv8.7-A @tab @samp{armv8.6-a}, @samp{+ls64} +@item @samp{armv8.8-a} @tab Armv8.8-a @tab @samp{armv8.7-a}, @samp{+mops} @item @samp{armv9-a} @tab Armv9-A @tab @samp{armv8.5-a}, @samp{+sve}, @samp{+sve2} @item @samp{armv8-r} @tab Armv8-R @tab @samp{armv8-r} @end multitable @@ -19146,7 +19147,8 @@ Enable the 64-byte atomic load and store instructions for accelerators. This option is enabled by default for @option{-march=armv8.7-a}. @item mops Enable the instructions to accelerate memory operations like @code{memcpy}, -@code{memmove}, @code{memset}. +@code{memmove}, @code{memset}. This option is enabled by default for +@option{-march=armv8.8-a} @item flagm Enable the Flag Manipulation instructions Extension. @item pauth -- cgit v1.1 From 16c848090f237c2398930b8c0ef75acebf4fa44d Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Mon, 13 Dec 2021 17:29:26 +0100 Subject: Add -fipa-strict-aliasing gcc/ChangeLog: 2021-12-13 Jan Hubicka * common.opt: Add -fipa-strict-aliasing. * doc/invoke.texi: Document -fipa-strict-aliasing. * ipa-modref.c (modref_access_analysis::record_access): Honor -fipa-strict-aliasing. (modref_access_analysis::record_access_lto): Likewise. --- gcc/common.opt | 4 ++++ gcc/doc/invoke.texi | 12 +++++++++++- gcc/ipa-modref.c | 8 +++++--- 3 files changed, 20 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/common.opt b/gcc/common.opt index 445a53a..8f8fc2f 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -1945,6 +1945,10 @@ fira-algorithm= Common Joined RejectNegative Enum(ira_algorithm) Var(flag_ira_algorithm) Init(IRA_ALGORITHM_CB) Optimization -fira-algorithm=[CB|priority] Set the used IRA algorithm. +fipa-strict-aliasing +Common Var(flag_ipa_strict_aliasing) Init(1) Optimization +Assume strict aliasing rules apply across (uninlined) function boundaries. + Enum Name(ira_algorithm) Type(enum ira_algorithm) UnknownError(unknown IRA algorithm %qs) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 221c7c3..80c36b9 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -570,7 +570,7 @@ Objective-C and Objective-C++ Dialects}. -fsingle-precision-constant -fsplit-ivs-in-unroller -fsplit-loops@gol -fsplit-paths @gol -fsplit-wide-types -fsplit-wide-types-early -fssa-backprop -fssa-phiopt @gol --fstdarg-opt -fstore-merging -fstrict-aliasing @gol +-fstdarg-opt -fstore-merging -fstrict-aliasing -fipa-strict-aliasing @gol -fthread-jumps -ftracer -ftree-bit-ccp @gol -ftree-builtin-call-dce -ftree-ccp -ftree-ch @gol -ftree-coalesce-vars -ftree-copy-prop -ftree-dce -ftree-dominator-opts @gol @@ -12423,6 +12423,16 @@ int f() @{ The @option{-fstrict-aliasing} option is enabled at levels @option{-O2}, @option{-O3}, @option{-Os}. +@item -fipa-strict-aliasing +@opindex fipa-strict-aliasing +Constrols whether rules of @option{-fstrict-aliasing} are applied across +function boundaries. Note that if multiple functions gets inlined into a +signle function the memory accesses are no longer considred to be crossing a +function bounday. + +The @option{-fipa-strict-aliasing} option is enabled by default and is +effective only in combination with @option{-fstrict-aliasing}. + @item -falign-functions @itemx -falign-functions=@var{n} @itemx -falign-functions=@var{n}:@var{m} diff --git a/gcc/ipa-modref.c b/gcc/ipa-modref.c index 2c89c63..d6bd9d3 100644 --- a/gcc/ipa-modref.c +++ b/gcc/ipa-modref.c @@ -999,9 +999,11 @@ modref_access_analysis::record_access (modref_records *tt, ao_ref *ref, modref_access_node &a) { - alias_set_type base_set = !flag_strict_aliasing ? 0 + alias_set_type base_set = !flag_strict_aliasing + || !flag_ipa_strict_aliasing ? 0 : ao_ref_base_alias_set (ref); - alias_set_type ref_set = !flag_strict_aliasing ? 0 + alias_set_type ref_set = !flag_strict_aliasing + || !flag_ipa_strict_aliasing ? 0 : (ao_ref_alias_set (ref)); if (dump_file) { @@ -1021,7 +1023,7 @@ modref_access_analysis::record_access_lto (modref_records_lto *tt, ao_ref *ref, /* get_alias_set sometimes use different type to compute the alias set than TREE_TYPE (base). Do same adjustments. */ tree base_type = NULL_TREE, ref_type = NULL_TREE; - if (flag_strict_aliasing) + if (flag_strict_aliasing && flag_ipa_strict_aliasing) { tree base; -- cgit v1.1 From 0515c95d5fe0a865f688f3ab89572b917e8f0185 Mon Sep 17 00:00:00 2001 From: Frederic Konrad Date: Fri, 6 Nov 2020 19:42:27 +0100 Subject: VxWorks config fixes for shared objects This strengthens the VxWorks configuration files for the support of shared objects, which encompasses a VxWorks specific "non-static" mode for RTPs (in addition to -static and -shared). 2020-11-06 Fred Konrad Olivier Hainque gcc/ * config/vx-common.h: Define REAL_LIBGCC_SPEC since the '-non-static' option is not standard. * config/vxworks.h (VXWORKS_LIBGCC_SPEC): Implement the LIBGCC_SPEC since REAL_LIBGCC_SPEC is used now. (STARTFILE_PREFIX_SPEC): Use the PIC VSB when building shared libraries or non-static binaries. --- gcc/config/vx-common.h | 7 +++++-- gcc/config/vxworks.h | 19 ++++++++++++++++++- 2 files changed, 23 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/config/vx-common.h b/gcc/config/vx-common.h index a436bf1..efa5d5f 100644 --- a/gcc/config/vx-common.h +++ b/gcc/config/vx-common.h @@ -23,8 +23,11 @@ along with GCC; see the file COPYING3. If not see /* Most of these will probably be overridden by subsequent headers. We undefine them here just in case, and define VXWORKS_ versions of each, to be used in port-specific vxworks.h. */ -#undef LIBGCC_SPEC -#define LIBGCC_SPEC VXWORKS_LIBGCC_SPEC + +/* REAL_LIBGCC_SPEC needs to be used since the non-static option is not + handled in gcc.c. */ +#undef REAL_LIBGCC_SPEC +#define REAL_LIBGCC_SPEC VXWORKS_LIBGCC_SPEC #undef STARTFILE_SPEC #undef ENDFILE_SPEC diff --git a/gcc/config/vxworks.h b/gcc/config/vxworks.h index f76141f..96076e3 100644 --- a/gcc/config/vxworks.h +++ b/gcc/config/vxworks.h @@ -143,11 +143,21 @@ along with GCC; see the file COPYING3. If not see tlsLib, responsible for TLS support by the OS. */ #if TARGET_VXWORKS7 + +/* For static links, /usr/lib/common has everything. For dynamic links, + /usr/lib/common/PIC has the static libs and objects that might be needed + in the closure (e.g. crt0.o), while the shared version of standard deps + (e.g. libc.so) are still in /usr/lib/common. */ #undef STARTFILE_PREFIX_SPEC -#define STARTFILE_PREFIX_SPEC "/usr/lib/common" +#define STARTFILE_PREFIX_SPEC \ + "%{shared|non-static:/usr/lib/common/PIC} /usr/lib/common" + #define TLS_SYM "-u __tls__" + #else + #define TLS_SYM "" + #endif #undef VXWORKS_LIB_SPEC @@ -177,7 +187,14 @@ along with GCC; see the file COPYING3. If not see %{non-static:--force-dynamic --export-dynamic}}}" #undef VXWORKS_LIBGCC_SPEC +#if defined(ENABLE_SHARED_LIBGCC) +#define VXWORKS_LIBGCC_SPEC \ +"%{!mrtp:-lgcc -lgcc_eh} \ + %{mrtp:%{!static-libgcc:%{shared|non-static:-lgcc_s;:-lgcc -lgcc_eh}} \ + %{static-libgcc:-lgcc -lgcc_eh}}" +#else #define VXWORKS_LIBGCC_SPEC "-lgcc" +#endif /* Setup the crtstuff begin/end we might need for dwarf EH registration. */ -- cgit v1.1 From 4099d6501e3526ca8d1d01e904f42b83c6824674 Mon Sep 17 00:00:00 2001 From: Frederic Konrad Date: Thu, 5 Nov 2020 11:34:57 +0100 Subject: Tigthen libc_internal and crtstuff for VxWorks shared objects This change tightens and documents the use of libc_internal, then strengthens the VxWorks crtstuff objects for the support of shared libraries. In particular: - Define __dso_handle, which libstdc++.so requires, - Provide _init and _fini functions to run through the init/fini arrays for shared libs in configurations which HAVE_INITFINI_ARRAY_SUPPORT. The init/fini functions are provided by libc_internal.a for static links but with slightly different names and we don't want to risk dragging other libc_internal contents in the closure accidentally so make sure we don't link with it. As for the !vxworks crtstuff, the new shared libs specific bits are conditioned by a CRTSTUFFS_O macro, for which we provide new Makefile fragment. The bits to actually use the fragment and the shared objects will be added by a forthcoming change, as part of a more general configury update for shared libs. The change also adds guards the eh table registration code in vxcrtstuff so the objects can be used for either init/fini or eh tables independently. 2021-12-07 Fred Konrad Olivier Hainque gcc/ * config/vxworks.h (VXWORKS_BASE_LIBS_RTP): Guard -lc_internal on !shared+!non-static and document. (VXWORKS_LIB_SPEC): Remove the bits intended to drag the init/fini functions from libc_internal in the shared lib case. (VX_CRTBEGIN_SPEC/VX_CRTEND_SPEC): Use vxcrtstuff objects also in configurations with shared lib and INITFINI_ARRAY support. libgcc/ * config/t-vxcrtstuffS: New Makefile fragment. * config/vxcrtstuff.c: Provide __dso_handle. Provide _init/_fini functions for INITFINI_ARRAY support in shared libs and guard the definition of eh table registration functions on conditions indicating they are needed. --- gcc/config/vxworks.h | 42 ++++++++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 14 deletions(-) (limited to 'gcc') diff --git a/gcc/config/vxworks.h b/gcc/config/vxworks.h index 96076e3..52d6aa1 100644 --- a/gcc/config/vxworks.h +++ b/gcc/config/vxworks.h @@ -101,11 +101,23 @@ along with GCC; see the file COPYING3. If not see the default CPP spec for C++ as well. */ #undef CPLUSPLUS_CPP_SPEC -/* For VxWorks static rtps, the system provides libc_internal.a, a superset of - libgcc.a that we need to use e.g. to satisfy references to __init and - __fini. We still want our libgcc to prevail for symbols it would provide - (e.g. register save entry points), so re-place it here between libraries - that might reference it and libc_internal. +/* For VxWorks static rtps, the system provides libc_internal.a for a variety + of purposes. Care is needed to include it appropriately. + + - In some configurations, libc_internal fills in possible references from + the static libc that we don't wouldn't satisfy ourselves, say, with + libgcc. An example is the __aeabi_memcpy family of functions on arm, + which have very specific ABI allowances. + + - OTOH, in some configurations the library provides typical libgcc + services, for example register save/restore entry points on powerpc. We + want our libgcc to prevail for symbols it would provide, so place + -lc_internal after -lc -lgcc. + + - libc_internal also contains __init/__fini functions for + USE_INITFINI_ARRAY support. However, the system expects these in + every shared lib as well, with slightly different names, and it is + simpler for us to provide our own versions through vxcrtstuff. In addition, some versions of VxWorks rely on explicit extra libraries for system calls and the set of base network libraries of common use varies @@ -120,7 +132,8 @@ along with GCC; see the file COPYING3. If not see #define VXWORKS_NET_LIBS_RTP "-lnet -ldsi" #endif -#define VXWORKS_BASE_LIBS_RTP "-lc -lgcc -lc_internal" +#define VXWORKS_BASE_LIBS_RTP \ + "-lc -lgcc %{!shared:%{!non-static:-lc_internal}}" #define VXWORKS_EXTRA_LIBS_RTP @@ -161,10 +174,9 @@ along with GCC; see the file COPYING3. If not see #endif #undef VXWORKS_LIB_SPEC -#define VXWORKS_LIB_SPEC \ -"%{mrtp:%{shared:-u " USER_LABEL_PREFIX "__init -u " USER_LABEL_PREFIX "__fini} \ - %{!shared:%{non-static:-u " USER_LABEL_PREFIX "_STI__6__rtld -ldl} \ - " TLS_SYM " \ +#define VXWORKS_LIB_SPEC \ +"%{mrtp:%{!shared:%{non-static:-u " USER_LABEL_PREFIX "_STI__6__rtld -ldl} \ + " TLS_SYM " \ --start-group " VXWORKS_LIBS_RTP " --end-group}}" /* The no-op spec for "-shared" below is present because otherwise GCC @@ -196,11 +208,13 @@ along with GCC; see the file COPYING3. If not see #define VXWORKS_LIBGCC_SPEC "-lgcc" #endif -/* Setup the crtstuff begin/end we might need for dwarf EH registration. */ +/* Setup the crtstuff begin/end we might need for dwarf EH registration + and/or INITFINI_ARRAY support for shared libs. */ -#if !defined(CONFIG_SJLJ_EXCEPTIONS) && DWARF2_UNWIND_INFO -#define VX_CRTBEGIN_SPEC "vx_crtbegin.o%s" -#define VX_CRTEND_SPEC "-l:vx_crtend.o" +#if (HAVE_INITFINI_ARRAY_SUPPORT && defined(ENABLE_SHARED_LIBGCC)) \ + || (DWARF2_UNWIND_INFO && !defined(CONFIG_SJLJ_EXCEPTIONS)) +#define VX_CRTBEGIN_SPEC "%{!shared:vx_crtbegin.o%s;:vx_crtbeginS.o%s}" +#define VX_CRTEND_SPEC "%{!shared:vx_crtend.o%s;:vx_crtendS.o%s}" #else #define VX_CRTBEGIN_SPEC "" #define VX_CRTEND_SPEC "" -- cgit v1.1 From fc4a93eb41243babe3f2ef3a3c6171b48e503138 Mon Sep 17 00:00:00 2001 From: Douglas B Rupp Date: Thu, 8 Apr 2021 11:03:19 -0700 Subject: Rework VXWORKS_LINK_SPEC for shared objects support Split LINK_SPEC as BASE_LINK_SPEC + EXTRA_LINK_SPEC, with an overridable LINK_OS component that cpu ports may redefine. Leverage the latter on powerpc for VxWorks 7, where we incorporate our specific bits in the linux os configuration as the system compiler is now very close to a standard linux one. The split allows supporting shared objects (shared libs and non-static rtps) on recent versions of VxWorks while retaining compatibility with older VxWorks targets which could link with shared libraries but not build them. 2021-12-07 Doug Rupp Olivier Hainque gcc/ * config/vxworks.h (VXWORKS_LINK_OS_SPEC): New spec. (VXWORKS_BASE_LINK_SPEC): New spec, using the former. (VXWORKS_EXTRA_LINK_SPEC): New spec for old and new VxWorks. (VXWORKS_LINK_SPEC): Combo of BASE and EXTRA specs. * config/rs6000/vxworks.h (VXWORKS_LINK_OS_SPEC): Empty. (LINK_OS_EXTRA_SPEC32): Use VXWORKS_LINK_SPEC. (LINK_OS_EXTRA_SPEC64): Likewise. --- gcc/config/rs6000/vxworks.h | 13 ++++++++----- gcc/config/vxworks.h | 35 +++++++++++++++++++++++------------ 2 files changed, 31 insertions(+), 17 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index fbe0902..d2d6585 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -252,15 +252,18 @@ along with GCC; see the file COPYING3. If not see #undef DOT_SYMBOLS #define DOT_SYMBOLS 0 -#undef LINK_OS_VXWORKS_SPEC -#define LINK_OS_VXWORKS_SPEC \ - " %{!mrtp:-r} %{mrtp:-q -static} %{!Xbind-lazy:-z now}" +/* For link specs, we leverage the linux configuration bits through + LINK_OS_EXTRA_SPEC32/64 and need to cancel the default %(link_os) + expansion in VXWORKS_LINK_SPEC. */ + +#undef VXWORKS_LINK_OS_SPEC +#define VXWORKS_LINK_OS_SPEC "" #undef LINK_OS_EXTRA_SPEC32 -#define LINK_OS_EXTRA_SPEC32 LINK_OS_VXWORKS_SPEC " " VXWORKS_RELAX_LINK_SPEC +#define LINK_OS_EXTRA_SPEC32 VXWORKS_LINK_SPEC " " VXWORKS_RELAX_LINK_SPEC #undef LINK_OS_EXTRA_SPEC64 -#define LINK_OS_EXTRA_SPEC64 LINK_OS_VXWORKS_SPEC +#define LINK_OS_EXTRA_SPEC64 VXWORKS_LINK_SPEC /* linux64.h enables this, not supported in vxWorks. */ #undef TARGET_FLOAT128_ENABLE_TYPE diff --git a/gcc/config/vxworks.h b/gcc/config/vxworks.h index 52d6aa1..88bffc4 100644 --- a/gcc/config/vxworks.h +++ b/gcc/config/vxworks.h @@ -132,8 +132,7 @@ along with GCC; see the file COPYING3. If not see #define VXWORKS_NET_LIBS_RTP "-lnet -ldsi" #endif -#define VXWORKS_BASE_LIBS_RTP \ - "-lc -lgcc %{!shared:%{!non-static:-lc_internal}}" +#define VXWORKS_BASE_LIBS_RTP "-lc -lgcc %{!shared:-lc_internal}" #define VXWORKS_EXTRA_LIBS_RTP @@ -179,15 +178,23 @@ along with GCC; see the file COPYING3. If not see " TLS_SYM " \ --start-group " VXWORKS_LIBS_RTP " --end-group}}" -/* The no-op spec for "-shared" below is present because otherwise GCC - will treat it as an unrecognized option. */ -#undef VXWORKS_LINK_SPEC -#define VXWORKS_LINK_SPEC \ +#if TARGET_VXWORKS7 +#define VXWORKS_EXTRA_LINK_SPEC "" +#else +/* Older VxWorks RTPs can only link with shared libs, and + need special switches --force-dynamic --export-dynamic. */ +#define VXWORKS_EXTRA_LINK_SPEC \ +"%{mrtp:%{!shared:%{non-static:--force-dynamic --export-dynamic}}}" +#endif + +/* A default link_os expansion for RTPs, that cpu ports may override. */ +#undef VXWORKS_LINK_OS_SPEC +#define VXWORKS_LINK_OS_SPEC "%(link_os)" + +/* The -B and -X switches are for DIAB based linking. */ +#undef VXWORKS_BASE_LINK_SPEC +#define VXWORKS_BASE_LINK_SPEC \ "%{!mrtp:-r} \ - %{!shared: \ - %{mrtp:-q %{h*} \ - %{R*} %{!T*: %(link_start) } \ - %(link_os)}} \ %{v:-V} \ %{shared:-shared} \ %{Bstatic:-Bstatic} \ @@ -195,8 +202,12 @@ along with GCC; see the file COPYING3. If not see %{!Xbind-lazy:-z now} \ %{Xbind-now:%{Xbind-lazy: \ %e-Xbind-now and -Xbind-lazy are incompatible}} \ - %{mrtp:%{!shared:%{!non-static:-static} \ - %{non-static:--force-dynamic --export-dynamic}}}" + %{mrtp:-q %{!shared:%{!non-static:-static}} \ + %{h*} %{R*} %{!T*: %(link_start)}" \ + VXWORKS_LINK_OS_SPEC "}" + +#undef VXWORKS_LINK_SPEC +#define VXWORKS_LINK_SPEC VXWORKS_BASE_LINK_SPEC " " VXWORKS_EXTRA_LINK_SPEC #undef VXWORKS_LIBGCC_SPEC #if defined(ENABLE_SHARED_LIBGCC) -- cgit v1.1 From 149739c39475f3691e67aa0aee4f205f4e83392f Mon Sep 17 00:00:00 2001 From: Roger Sayle Date: Mon, 13 Dec 2021 18:48:22 +0000 Subject: x86: Avoid generating orb $0, %ah I'll post my proposed fix for PR target/103611 shortly, but this patch fixes another missed optimization opportunity revealed by that PR. Occasionally, reload materializes integer constants during register allocation sometimes resulting in unnecessary instructions such as: (insn 23 31 24 2 (parallel [ (set (reg:SI 0 ax [99]) (ior:SI (reg:SI 0 ax [99]) (const_int 0 [0]))) (clobber (reg:CC 17 flags)) ]) "pr103611.c":18:73 550 {*iorsi_1} (nil)) These then get "optimized" during the split2 pass, which realizes that no bits outside of 0xff00 are set, so this operation can be implemented by operating on just the highpart of a QIreg_operand, i.e. %ah, %bh, %ch etc., which leads to the useless "orb $0, %ah" seen in the reported PR. This fix catches the case of const0_rtx in relevant splitter, either eliminating the instruction or turning it into a simple move. 2021-12-13 Roger Sayle gcc/ChangeLog * config/i386/i386.md (define_split any_or:SWI248 -> orb %?h): Optimize the case where the integer constant operand is zero. gcc/testsuite/ChangeLog * gcc.target/i386/pr103611-1.c: New test case. --- gcc/config/i386/i386.md | 9 +++++++++ gcc/testsuite/gcc.target/i386/pr103611-1.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr103611-1.c (limited to 'gcc') diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9d7d116..f6d9c4b 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10542,6 +10542,15 @@ (match_dup 2)) 0)) (clobber (reg:CC FLAGS_REG))])] { + /* Handle the case where INTVAL (operands[2]) == 0. */ + if (operands[2] == const0_rtx) + { + if (!rtx_equal_p (operands[0], operands[1])) + emit_move_insn (operands[0], operands[1]); + else + emit_note (NOTE_INSN_DELETED); + DONE; + } operands[0] = gen_lowpart (SImode, operands[0]); operands[1] = gen_lowpart (SImode, operands[1]); operands[2] = gen_int_mode (INTVAL (operands[2]) >> 8, QImode); diff --git a/gcc/testsuite/gcc.target/i386/pr103611-1.c b/gcc/testsuite/gcc.target/i386/pr103611-1.c new file mode 100644 index 0000000..7d8ac9d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103611-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O2 -msse4" } */ +typedef int __v4si __attribute__ ((__vector_size__ (16))); + +long long ior_1(__v4si v) { + unsigned int loVal = (unsigned int)v[0]; + unsigned int hiVal = (unsigned int)v[1]; + return (long long)(loVal) | ((long long)(hiVal) << 32); +} + +long long ior_2(__v4si v) { + unsigned int loVal = (unsigned int)v[2]; + unsigned int hiVal = (unsigned int)v[3]; + return (long long)(loVal) | ((long long)(hiVal) << 32); +} + +long long xor_1(__v4si v) { + unsigned int loVal = (unsigned int)v[0]; + unsigned int hiVal = (unsigned int)v[1]; + return (long long)(loVal) ^ ((long long)(hiVal) << 32); +} + +long long xor_2(__v4si v) { + unsigned int loVal = (unsigned int)v[2]; + unsigned int hiVal = (unsigned int)v[3]; + return (long long)(loVal) ^ ((long long)(hiVal) << 32); +} +/* { dg-final { scan-assembler-not "\torb\t\\\$0," } } */ +/* { dg-final { scan-assembler-not "\txorb\t\\\$0," } } */ + -- cgit v1.1 From a7acb6dca941db2b1c135107dac3a34a20650d5c Mon Sep 17 00:00:00 2001 From: "Vladimir N. Makarov" Date: Mon, 13 Dec 2021 13:48:12 -0500 Subject: [PR99531] Modify pseudo class cost calculation when processing move involving the pseudo and a hard register Pseudo class calculated on the 1st iteration should not have a special treatment in cost calculation when processing move involving the pseudo and a hard register. gcc/ChangeLog: PR target/99531 * ira-costs.c (record_operand_costs): Do not take pseudo class calculated on the 1st iteration into account when processing move involving the pseudo and a hard register. gcc/testsuite/ChangeLog: PR target/99531 * gcc.target/i386/pr99531.c: New test. --- gcc/ira-costs.c | 22 +--------------------- gcc/testsuite/gcc.target/i386/pr99531.c | 7 +++++++ 2 files changed, 8 insertions(+), 21 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr99531.c (limited to 'gcc') diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c index cb5ca8b..d7191dc 100644 --- a/gcc/ira-costs.c +++ b/gcc/ira-costs.c @@ -1310,7 +1310,7 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref) machine_mode mode = GET_MODE (SET_SRC (set)); cost_classes_t cost_classes_ptr = regno_cost_classes[regno]; enum reg_class *cost_classes = cost_classes_ptr->classes; - reg_class_t rclass, hard_reg_class, pref_class, bigger_hard_reg_class; + reg_class_t rclass, hard_reg_class, bigger_hard_reg_class; int cost, k; move_table *move_costs; bool dead_p = find_regno_note (insn, REG_DEAD, REGNO (src)); @@ -1336,23 +1336,6 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref) : move_costs[rclass][hard_reg_class]); op_costs[i]->cost[k] = cost * frequency; - /* If we have assigned a class to this allocno in our - first pass, add a cost to this alternative - corresponding to what we would add if this allocno - were not in the appropriate class. */ - if (pref) - { - if ((pref_class = pref[COST_INDEX (regno)]) == NO_REGS) - op_costs[i]->cost[k] - += ((i == 0 ? ira_memory_move_cost[mode][rclass][0] : 0) - + (i == 1 ? ira_memory_move_cost[mode][rclass][1] : 0) - * frequency); - else if (ira_reg_class_intersect[pref_class][rclass] - == NO_REGS) - op_costs[i]->cost[k] - += (move_costs[pref_class][rclass] - * frequency); - } /* If this insn is a single set copying operand 1 to operand 0 and one operand is an allocno with the other a hard reg or an allocno that prefers a hard @@ -1378,9 +1361,6 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref) } op_costs[i]->mem_cost = ira_memory_move_cost[mode][hard_reg_class][i] * frequency; - if (pref && (pref_class = pref[COST_INDEX (regno)]) != NO_REGS) - op_costs[i]->mem_cost - += ira_memory_move_cost[mode][pref_class][i] * frequency; return; } } diff --git a/gcc/testsuite/gcc.target/i386/pr99531.c b/gcc/testsuite/gcc.target/i386/pr99531.c new file mode 100644 index 0000000..0e1a08b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr99531.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { x86_64-*-linux* } } } */ +/* { dg-options "-O2" } */ + +int func(int, int, int, int, int, int); +int caller(int a, int b, int c, int d, int e) { return func(0, a, b, c, d, e); } + +/* { dg-final { scan-assembler-not "push" } } */ -- cgit v1.1 From 7f1239cb43fad3293cf5bcd3678d1cba128d04c6 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Tue, 14 Dec 2021 00:16:25 +0000 Subject: Daily bump. --- gcc/ChangeLog | 144 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/fortran/ChangeLog | 7 +++ gcc/testsuite/ChangeLog | 37 +++++++++++++ 4 files changed, 189 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 890ddae..029d491 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,147 @@ +2021-12-13 Vladimir N. Makarov + + PR target/99531 + * ira-costs.c (record_operand_costs): Do not take pseudo class + calculated on the 1st iteration into account when processing move + involving the pseudo and a hard register. + +2021-12-13 Roger Sayle + + * config/i386/i386.md (define_split any_or:SWI248 -> orb %?h): + Optimize the case where the integer constant operand is zero. + +2021-12-13 Doug Rupp + Olivier Hainque + + * config/vxworks.h (VXWORKS_LINK_OS_SPEC): New spec. + (VXWORKS_BASE_LINK_SPEC): New spec, using the former. + (VXWORKS_EXTRA_LINK_SPEC): New spec for old and new VxWorks. + (VXWORKS_LINK_SPEC): Combo of BASE and EXTRA specs. + * config/rs6000/vxworks.h (VXWORKS_LINK_OS_SPEC): Empty. + (LINK_OS_EXTRA_SPEC32): Use VXWORKS_LINK_SPEC. + (LINK_OS_EXTRA_SPEC64): Likewise. + +2021-12-13 Fred Konrad + Olivier Hainque + + * config/vxworks.h (VXWORKS_BASE_LIBS_RTP): Guard -lc_internal + on !shared+!non-static and document. + (VXWORKS_LIB_SPEC): Remove the bits intended to drag the + init/fini functions from libc_internal in the shared lib case. + (VX_CRTBEGIN_SPEC/VX_CRTEND_SPEC): Use vxcrtstuff objects also in + configurations with shared lib and INITFINI_ARRAY support. + +2021-12-13 Fred Konrad + Olivier Hainque + + * config/vx-common.h: Define REAL_LIBGCC_SPEC since the + '-non-static' option is not standard. + * config/vxworks.h (VXWORKS_LIBGCC_SPEC): Implement the LIBGCC_SPEC + since REAL_LIBGCC_SPEC is used now. + (STARTFILE_PREFIX_SPEC): Use the PIC VSB when building shared libraries + or non-static binaries. + +2021-12-13 Jan Hubicka + + * common.opt: Add -fipa-strict-aliasing. + * doc/invoke.texi: Document -fipa-strict-aliasing. + * ipa-modref.c (modref_access_analysis::record_access): Honor + -fipa-strict-aliasing. + (modref_access_analysis::record_access_lto): Likewise. + +2021-12-13 Kyrylo Tkachov + + * config/aarch64/aarch64-arches.def (armv8.8-a): Define. + * config/aarch64/aarch64.h (AARCH64_FL_V8_8): Define. + (AARCH64_FL_FOR_ARCH8_8): Define. + * doc/invoke.texi: Document -march=armv8.8-a. + +2021-12-13 Kyrylo Tkachov + + * config/aarch64/aarch64.c (aarch64_expand_setmem_mops): Define. + (aarch64_expand_setmem): Adjust for TARGET_MOPS. + * config/aarch64/aarch64.h (CLEAR_RATIO): Adjust for TARGET_MOPS. + (SET_RATIO): Likewise. + * config/aarch64/aarch64.md ("unspec"): Add UNSPEC_SETMEM. + (aarch64_setmemdi): Define. + (setmemdi): Adjust for TARGET_MOPS. + * config/aarch64/aarch64.opt (aarch64-mops-memset-size-threshold): + New param. + +2021-12-13 Kyrylo Tkachov + + * config/aarch64/aarch64.md (aarch64_movmemdi): Define. + (movmemdi): Define. + (unspec): Add UNSPEC_MOVMEM. + * config/aarch64/aarch64.opt (aarch64-mops-memmove-size-threshold): + New param. + +2021-12-13 Kyrylo Tkachov + + * config/aarch64/aarch64-option-extensions.def (mops): Define. + * config/aarch64/aarch64.c (aarch64_expand_cpymem_mops): Define. + (aarch64_expand_cpymem): Define. + * config/aarch64/aarch64.h (AARCH64_FL_MOPS): Define. + (AARCH64_ISA_MOPS): Define. + (TARGET_MOPS): Define. + (MOVE_RATIO): Adjust for TARGET_MOPS. + * config/aarch64/aarch64.md ("unspec"): Add UNSPEC_CPYMEM. + (aarch64_cpymemdi): New pattern. + (cpymemdi): Adjust for TARGET_MOPS. + * config/aarch64/aarch64.opt (aarch64-mops-memcpy-size-threshol): + New param. + * doc/invoke.texi (AArch64 Options): Document +mops. + +2021-12-13 Martin Liska + + PR ipa/103636 + * ipa-inline.c (can_inline_edge_p): Move logic checking + no_profile_instrument_function logic to ... + (can_early_inline_edge_p): ... here. + +2021-12-13 Olivier Hainque + + * config/vxworks/_yvals.h: #include yvals.h also if + defined(__RTP__). + +2021-12-13 Olivier Hainque + + * config/vxworks.h (VXWORKS_OS_CPP_BUILTINS): Define + _C99 for C++. + +2021-12-13 Olivier Hainque + + * config/t-vxworks: Clear NATIVE_SYSTEM_HEADER_DIR. + * config/vxworks.h (SYSROOT_HEADERS_SUFFIX_SPEC): Define, for + VxWorks 7 and earlier. + (VXWORKS_ADDITIONAL_CPP_SPEC): Simplify accordingly. + (STARTFILE_PREFIX_SPEC): Adjust accordingly. + * config/rs6000/vxworks.h (STARTFILE_PREFIX_SPEC): Adjust. + +2021-12-13 Martin Liska + + * doc/extend.texi: Use @item for the first @itemx entry. + +2021-12-13 Jakub Jelinek + + * machmode.h (gt_pch_nx): Use gt_pointer_operator as type of second + argument instead of equivalent void (*) (void *, void *, void *). + * poly-int.h (gt_pch_nx): Likewise. + * wide-int.h (gt_pch_nx): Likewise. + * config/aarch64/aarch64-sve-builtins.cc (gt_pch_nx): Likewise. + +2021-12-13 Jan Hubicka + + PR ipa/103513 + * ipa-fnsummary.c (evaluate_conditions_for_known_args): Do not ICE + on ternary expression. + +2021-12-13 Kewen Lin + + PR target/103515 + * attribs.c (decl_attributes): Check if target options change and + create one node if so. + 2021-12-12 Jonathan Wakely * Makefile.in: Remove unique-ptr-tests.o. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 6fc1d23..e502600 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20211213 +20211214 diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 1e70b9d..fc7bea1 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,10 @@ +2021-12-13 Tobias Burnus + + PR fortran/103576 + * openmp.c (is_scalar_intrinsic_expr): Fix condition. + (resolve_omp_atomic): Fix/update checks, accept compare. + * trans-openmp.c (gfc_trans_omp_atomic): Handle compare. + 2021-12-11 Harald Anlauf PR fortran/103606 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 836fa33..1a61c86 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,40 @@ +2021-12-13 Vladimir N. Makarov + + PR target/99531 + * gcc.target/i386/pr99531.c: New test. + +2021-12-13 Roger Sayle + + * gcc.target/i386/pr103611-1.c: New test case. + +2021-12-13 Kyrylo Tkachov + + * gcc.target/aarch64/mops_3.c: New test. + +2021-12-13 Kyrylo Tkachov + + * gcc.target/aarch64/mops_2.c: New test. + +2021-12-13 Kyrylo Tkachov + + * gcc.target/aarch64/mops_1.c: New test. + +2021-12-13 Tobias Burnus + + * gfortran.dg/gomp/atomic-25.f90: Remove sorry, fix + add checks. + * gfortran.dg/gomp/atomic-26.f90: Likewise. + * gfortran.dg/gomp/atomic-21.f90: New test. + +2021-12-13 Jan Hubicka + + PR ipa/103513 + * gcc.c-torture/compile/pr103513.c: New test. + +2021-12-13 Kewen Lin + + PR target/103515 + * gcc.target/powerpc/pr103515.c: New test. + 2021-12-12 Antoni Boucher PR target/100688 -- cgit v1.1 From 228d64af4e244faabab5c47506920a1bde85d74e Mon Sep 17 00:00:00 2001 From: Thomas Schwinge Date: Tue, 14 Dec 2021 07:03:52 +0100 Subject: Adjust 'gfortran.dg/goacc/privatization-1-*' [PR103576, PR103697] ... for the recent commit 494ebfa7c9aacaeb6ec1fccc47a0e49f31eb2bb8 "Fortran: Handle compare in OpenMP atomic", which changes the GIMPLE IR such that a temporary is no longer used; 'original' dump: x = *a; - { - integer(kind=4) D.4237; - - D.4237 = *a; #pragma omp atomic relaxed - &y = D.4237; - } + &y = *a; } (I'm not familiar to comment whether that's correct; but it appears that the difference again disappears in later compiler passes.) These OpenACC test cases verify behavior re OpenACC privatization levels, and have to be adjusted accordingly. gcc/testsuite/ PR fortran/103576 PR testsuite/103697 * gfortran.dg/goacc/privatization-1-compute-loop.f90: Adjust. * gfortran.dg/goacc/privatization-1-compute.f90: Likewise. * gfortran.dg/goacc/privatization-1-routine_gang-loop.f90: Likewise. * gfortran.dg/goacc/privatization-1-routine_gang.f90: Likewise. --- gcc/testsuite/gfortran.dg/goacc/privatization-1-compute-loop.f90 | 1 - gcc/testsuite/gfortran.dg/goacc/privatization-1-compute.f90 | 1 - gcc/testsuite/gfortran.dg/goacc/privatization-1-routine_gang-loop.f90 | 1 - gcc/testsuite/gfortran.dg/goacc/privatization-1-routine_gang.f90 | 1 - 4 files changed, 4 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gfortran.dg/goacc/privatization-1-compute-loop.f90 b/gcc/testsuite/gfortran.dg/goacc/privatization-1-compute-loop.f90 index bcd7159..47ba5ba 100644 --- a/gcc/testsuite/gfortran.dg/goacc/privatization-1-compute-loop.f90 +++ b/gcc/testsuite/gfortran.dg/goacc/privatization-1-compute-loop.f90 @@ -50,7 +50,6 @@ contains ! { dg-note {variable 'x' in 'private' clause isn't candidate for adjusting OpenACC privatization level: not addressable} "" { target *-*-* } l_loop$c_loop } ! { dg-note {variable 'y' in 'private' clause is candidate for adjusting OpenACC privatization level} "" { target *-*-* } l_loop$c_loop } ! { dg-note {variable 'C\.[0-9]+' declared in block potentially has improper OpenACC privatization level: 'const_decl'} "TODO" { target *-*-* } l_loop$c_loop } - ! { dg-note {variable 'D\.[0-9]+' declared in block isn't candidate for adjusting OpenACC privatization level: not addressable} "" { target *-*-* } l_loop$c_loop } ! { dg-note {variable 'y' ought to be adjusted for OpenACC privatization level: 'vector'} "" { target *-*-* } l_loop$c_loop } !$acc end parallel end subroutine f diff --git a/gcc/testsuite/gfortran.dg/goacc/privatization-1-compute.f90 b/gcc/testsuite/gfortran.dg/goacc/privatization-1-compute.f90 index 31f998d..4813e44 100644 --- a/gcc/testsuite/gfortran.dg/goacc/privatization-1-compute.f90 +++ b/gcc/testsuite/gfortran.dg/goacc/privatization-1-compute.f90 @@ -43,6 +43,5 @@ contains ! { dg-note {variable 'j' in 'private' clause potentially has improper OpenACC privatization level: 'parm_decl'} "TODO3" { xfail *-*-* } l_compute$c_compute } ! { dg-note {variable 'a' in 'private' clause potentially has improper OpenACC privatization level: 'parm_decl'} "TODO4" { xfail *-*-* } l_compute$c_compute } ! { dg-note {variable 'C\.[0-9]+' declared in block potentially has improper OpenACC privatization level: 'const_decl'} "TODO" { target *-*-* } l_compute$c_compute } - ! { dg-note {variable 'D\.[0-9]+' declared in block isn't candidate for adjusting OpenACC privatization level: not addressable} "" { target *-*-* } l_compute$c_compute } end subroutine f end module m diff --git a/gcc/testsuite/gfortran.dg/goacc/privatization-1-routine_gang-loop.f90 b/gcc/testsuite/gfortran.dg/goacc/privatization-1-routine_gang-loop.f90 index db6d822..36f2a88 100644 --- a/gcc/testsuite/gfortran.dg/goacc/privatization-1-routine_gang-loop.f90 +++ b/gcc/testsuite/gfortran.dg/goacc/privatization-1-routine_gang-loop.f90 @@ -50,7 +50,6 @@ contains ! { dg-note {variable 'x' in 'private' clause isn't candidate for adjusting OpenACC privatization level: not addressable} "" { target *-*-* } l_loop$c_loop } ! { dg-note {variable 'y' in 'private' clause is candidate for adjusting OpenACC privatization level} "" { target *-*-* } l_loop$c_loop } ! { dg-note {variable 'C\.[0-9]+' declared in block potentially has improper OpenACC privatization level: 'const_decl'} "TODO" { target *-*-* } l_loop$c_loop } - ! { dg-note {variable 'D\.[0-9]+' declared in block isn't candidate for adjusting OpenACC privatization level: not addressable} "" { target *-*-* } l_loop$c_loop } ! { dg-note {variable 'y' ought to be adjusted for OpenACC privatization level: 'vector'} "" { target *-*-* } l_loop$c_loop } end subroutine f end module m diff --git a/gcc/testsuite/gfortran.dg/goacc/privatization-1-routine_gang.f90 b/gcc/testsuite/gfortran.dg/goacc/privatization-1-routine_gang.f90 index 725bd5e..0615a44 100644 --- a/gcc/testsuite/gfortran.dg/goacc/privatization-1-routine_gang.f90 +++ b/gcc/testsuite/gfortran.dg/goacc/privatization-1-routine_gang.f90 @@ -43,5 +43,4 @@ contains ! { dg-note {variable 'j' in 'private' clause potentially has improper OpenACC privatization level: 'parm_decl'} "TODO" { xfail *-*-* } l_routine$c_routine } ! { dg-note {variable 'a' in 'private' clause potentially has improper OpenACC privatization level: 'parm_decl'} "TODO" { xfail *-*-* } l_routine$c_routine } ! { dg-note {variable 'C\.[0-9]+' declared in block potentially has improper OpenACC privatization level: 'const_decl'} "TODO" { xfail *-*-* } l_routine$c_routine } - ! { dg-note {variable 'D\.[0-9]+' declared in block isn't candidate for adjusting OpenACC privatization level: not addressable} "TODO" { xfail *-*-* } l_routine$c_routine } end module m -- cgit v1.1 From e163dbbc4433e598cad7e6011b255d1d6ad93a3b Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 14 Dec 2021 12:02:55 +0100 Subject: c: Fix ICE on deferred pragma in unknown attribute arguments [PR103587] We ICE on the following testcase, because c_parser_balanced_token_sequence when encountering a deferred pragma will just use c_parser_consume_token which the FE doesn't allow for CPP_PRAGMA tokens (and if that wasn't the case, it could ICE on CPP_PRAGMA_EOL similarly). We don't know in what exact context the pragma appears when we don't know what those arguments semantically mean, so I think we should just skip over them, like e.g. the C++ FE does. And, I think (/[/{ vs. )/]/} from outside of the pragma shouldn't be paired with those inside of the pragma and it doesn't seem to be necessary to check that inside of the pragma line itself all the paren kinds are balanced. 2021-12-14 Jakub Jelinek PR c/103587 * c-parser.c (c_parser_balanced_token_sequence): For CPP_PRAGMA, consume the pragma and silently skip to the pragma eol. * gcc.dg/pr103587.c: New test. --- gcc/c/c-parser.c | 5 +++++ gcc/testsuite/gcc.dg/pr103587.c | 7 +++++++ 2 files changed, 12 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/pr103587.c (limited to 'gcc') diff --git a/gcc/c/c-parser.c b/gcc/c/c-parser.c index e25df4f..d7e5f05 100644 --- a/gcc/c/c-parser.c +++ b/gcc/c/c-parser.c @@ -4846,6 +4846,11 @@ c_parser_balanced_token_sequence (c_parser *parser) case CPP_EOF: return; + case CPP_PRAGMA: + c_parser_consume_pragma (parser); + c_parser_skip_to_pragma_eol (parser, false); + break; + default: c_parser_consume_token (parser); break; diff --git a/gcc/testsuite/gcc.dg/pr103587.c b/gcc/testsuite/gcc.dg/pr103587.c new file mode 100644 index 0000000..1cbc4d5 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr103587.c @@ -0,0 +1,7 @@ +/* PR c/103587 */ +/* { dg-do compile } */ +/* { dg-options "" } */ + +[[foo::bar( +#pragma GCC ivdep +)]]; /* { dg-warning "attribute ignored" } */ -- cgit v1.1 From dff8ae8e839a5102aff266c8246864b610c066c9 Mon Sep 17 00:00:00 2001 From: Frederic Konrad Date: Thu, 12 Nov 2020 12:39:25 +0100 Subject: Drop the fpic multilib for powerpc*-vxworks* The addition of fPIC for shared libraries is performed independently from multilibs and the fpic multilibs have no other particular purpose. They incur extra build time, complexify the install tree and are a bit tricky because -fpic is not supported for kernel mode. 2020-11-06 Fred Konrad gcc/ * config/rs6000/t-vxworks: Drop the fPIC multilib. --- gcc/config/rs6000/t-vxworks | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/t-vxworks b/gcc/config/rs6000/t-vxworks index 68b2415..6da829d 100644 --- a/gcc/config/rs6000/t-vxworks +++ b/gcc/config/rs6000/t-vxworks @@ -19,7 +19,7 @@ # . # The base multilib is -mhard-float. -MULTILIB_OPTIONS = mrtp fPIC msoft-float +MULTILIB_OPTIONS = mrtp msoft-float MULTILIB_DIRNAMES = -MULTILIB_MATCHES = fPIC=fpic -MULTILIB_EXCEPTIONS = fPIC* +MULTILIB_MATCHES = +MULTILIB_EXCEPTIONS = -- cgit v1.1 From c5ef950d0bb7d451e8d831f71351a5db4373aa9a Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Tue, 14 Dec 2021 07:48:05 -0500 Subject: c++: remove COMPOUND_EXPR_OVERLOADED flag This flag is never set because non-dependent COMPOUND_EXPRs that resolve to an overload are expressed as a CALL_EXPR at template definition time (in build_x_compound_expr) ever since r6-5772. gcc/cp/ChangeLog: * cp-tree.h (COMPOUND_EXPR_OVERLOADED): Remove. * pt.c (build_non_dependent_expr): Don't inspect the flag. * tree.c (build_min_non_dep): Don't set the flag. --- gcc/cp/cp-tree.h | 6 ------ gcc/cp/pt.c | 3 +-- gcc/cp/tree.c | 5 ----- 3 files changed, 1 insertion(+), 13 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index b1c3bc5..e4330fb 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -404,7 +404,6 @@ extern GTY(()) tree cp_global_trees[CPTI_MAX]; NEW_EXPR_USE_GLOBAL (in NEW_EXPR). COND_EXPR_IS_VEC_DELETE (in COND_EXPR). DELETE_EXPR_USE_GLOBAL (in DELETE_EXPR). - COMPOUND_EXPR_OVERLOADED (in COMPOUND_EXPR). CLEANUP_P (in TRY_BLOCK) AGGR_INIT_VIA_CTOR_P (in AGGR_INIT_EXPR) PTRMEM_OK_P (in ADDR_EXPR, OFFSET_REF, SCOPE_REF) @@ -4015,11 +4014,6 @@ struct GTY(()) lang_decl { #define CALL_OR_AGGR_INIT_CHECK(NODE) \ TREE_CHECK2 ((NODE), CALL_EXPR, AGGR_INIT_EXPR) -/* Indicates that this is a non-dependent COMPOUND_EXPR which will - resolve to a function call. */ -#define COMPOUND_EXPR_OVERLOADED(NODE) \ - TREE_LANG_FLAG_0 (COMPOUND_EXPR_CHECK (NODE)) - /* In a CALL_EXPR appearing in a template, true if Koenig lookup should be performed at instantiation time. */ #define KOENIG_LOOKUP_P(NODE) TREE_LANG_FLAG_0 (CALL_EXPR_CHECK (NODE)) diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 9834baf..cbdb4b5 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -28373,8 +28373,7 @@ build_non_dependent_expr (tree expr) ? build_non_dependent_expr (TREE_OPERAND (expr, 1)) : build_non_dependent_expr (TREE_OPERAND (expr, 0))), build_non_dependent_expr (TREE_OPERAND (expr, 2))); - if (TREE_CODE (expr) == COMPOUND_EXPR - && !COMPOUND_EXPR_OVERLOADED (expr)) + if (TREE_CODE (expr) == COMPOUND_EXPR) return build2 (COMPOUND_EXPR, TREE_TYPE (expr), TREE_OPERAND (expr, 0), diff --git a/gcc/cp/tree.c b/gcc/cp/tree.c index 52c5683..f6f7927f 100644 --- a/gcc/cp/tree.c +++ b/gcc/cp/tree.c @@ -3577,11 +3577,6 @@ build_min_non_dep (enum tree_code code, tree non_dep, ...) for (i = 0; i < length; i++) TREE_OPERAND (t, i) = va_arg (p, tree); - if (code == COMPOUND_EXPR && TREE_CODE (non_dep) != COMPOUND_EXPR) - /* This should not be considered a COMPOUND_EXPR, because it - resolves to an overload. */ - COMPOUND_EXPR_OVERLOADED (t) = 1; - va_end (p); return convert_from_reference (t); } -- cgit v1.1 From 336dc544ebca867794a8e57c65afe303fd8ecc66 Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Tue, 14 Dec 2021 07:48:54 -0500 Subject: c++: don't leak 'arglist' in build_new_op gcc/cp/ChangeLog: * call.c (build_new_op): Use releasing_vec for arglist. Declare conv in the scope it's used. --- gcc/cp/call.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/call.c b/gcc/cp/call.c index 28bd8e0c..347df5d 100644 --- a/gcc/cp/call.c +++ b/gcc/cp/call.c @@ -6461,13 +6461,12 @@ build_new_op (const op_location_t &loc, enum tree_code code, int flags, tsubst_flags_t complain) { struct z_candidate *candidates = 0, *cand; - vec *arglist; + releasing_vec arglist; tree result = NULL_TREE; bool result_valid_p = false; enum tree_code code2 = ERROR_MARK; enum tree_code code_orig_arg1 = ERROR_MARK; enum tree_code code_orig_arg2 = ERROR_MARK; - conversion *conv; void *p; bool strict_p; bool any_viable_p; @@ -6543,7 +6542,6 @@ build_new_op (const op_location_t &loc, enum tree_code code, int flags, arg2_type = integer_type_node; } - vec_alloc (arglist, 3); arglist->quick_push (arg1); if (arg2 != NULL_TREE) arglist->quick_push (arg2); @@ -6814,7 +6812,7 @@ build_new_op (const op_location_t &loc, enum tree_code code, int flags, corresponding parameters of the selected operation function, except that the second standard conversion sequence of a user-defined conversion sequence (12.3.3.1.2) is not applied." */ - conv = cand->convs[0]; + conversion *conv = cand->convs[0]; if (conv->user_conv_p) { conv = strip_standard_conversion (conv); -- cgit v1.1 From d8eae5abf3d9d1363980342889635ccee1a7090d Mon Sep 17 00:00:00 2001 From: Olivier Hainque Date: Sun, 15 Nov 2020 09:56:51 +0000 Subject: Remove fpic multilib on x86_64-vxworks The addition of fPIC for shared libraries is performed independently from multilibs and fpic multilibs have no other particular purpose for VxWorks at this stage. They incur extra build time, complexify the install tree and are a bit tricky because -fpic is not supported for kernel mode. 2021-12-14 Olivier Hainque gcc/ * config/i386/t-vxworks: Drop the fPIC multilibs. --- gcc/config/i386/t-vxworks | 7 ------- 1 file changed, 7 deletions(-) (limited to 'gcc') diff --git a/gcc/config/i386/t-vxworks b/gcc/config/i386/t-vxworks index 8f5e8c7..debb6b1 100644 --- a/gcc/config/i386/t-vxworks +++ b/gcc/config/i386/t-vxworks @@ -9,11 +9,4 @@ MULTILIB_DIRNAMES = mrtp ifneq (,$(findstring x86_64, $(target))) MULTILIB_OPTIONS += mcmodel=large MULTILIB_DIRNAMES += large -else -MULTILIB_OPTIONS += fPIC -MULTILIB_DIRNAMES += fPIC -MULTILIB_MATCHES = fPIC=fpic - -# -fPIC is only supported in combination with -mrtp -MULTILIB_EXCEPTIONS = fPIC endif -- cgit v1.1 From 561414cdf8ef0d3c1e2da80b3c8aae56de745b1e Mon Sep 17 00:00:00 2001 From: Patrick Palka Date: Tue, 14 Dec 2021 08:15:52 -0500 Subject: c++: processing_template_decl vs template depth [PR103408] We use processing_template_decl in two slightly different ways: as a flag to signal that we're dealing with templated trees, and as a measure of the current syntactic template nesting depth. This overloaded meaning of p_t_d is conceptually confusing and leads to bugs that we end up working around in an ad-hoc fashion. This patch replaces all uses of processing_template_decl that care about its magnitude to instead look at the depth of current_template_parms via a new macro current_template_depth. This allows us to eliminate 3 workarounds in the concepts code: two about non-templated requires-expressions (in constraint.cc) and one about lambdas inside constraints (in cp_parser_requires_clause_expression etc). This also fixes the testcase in PR103408 about auto(x) used inside a non-templated requires-expression. The replacement was mostly mechanical, aside from two issues: * In synthesize_implicit_template_parm, when introducing a new template parameter list for an abbreviated function template, we need to add the new level of current_template_parms sooner, before calling process_template_parm, since this latter function now looks at current_template_depth to determine the level of the new parameter. * In instantiate_class_template_1 after substituting a template friend declaration, we currently increment processing_template_decl around the call to make_friend_class so that the friend_depth computation within this subroutine yields a nonzero value. We could just replace this with an equivalent manipulation of current_template_depth, but this patch instead rewrites the friend_depth calculation within make_friend_class to not depend on p_t_d / c_t_d at all when called from instantiate_class_template_1. PR c++/103408 gcc/cp/ChangeLog: * constraint.cc (type_deducible_p): Remove workaround for non-templated requires-expressions. (normalize_placeholder_type_constraints): Likewise. * cp-tree.h (current_template_depth): Define. (PROCESSING_REAL_TEMPLATE_DECL): Inspect current_template_depth instead of the magnitude of processing_template_decl. * decl.c (start_decl): Likewise. (grokfndecl): Likewise. (grokvardecl): Likewise. (grokdeclarator): Likewise. * friend.c (make_friend_class): Likewise. Calculate friend_depth differently when called at instantiation time instead of parse time. (do_friend): Likewise. * parser.c (cp_parser_requires_clause_expression): Remove workaround for lambdas inside constraints. (cp_parser_constraint_expression): Likewise. (cp_parser_requires_expression): Likewise. (synthesize_implicit_template_parm): Add to current_template_parms before calling process_template_parm. * pt.c (inline_needs_template_parms): Inspect current_template_depth instead of the magnitude of processing_template_decl. (push_inline_template_parms_recursive): Likewise. (maybe_begin_member_template_processing): Likewise. (begin_template_parm_list): Likewise. (process_template_parm): Likewise. (end_template_parm_list): Likewise. (push_template_decl): Likewise. (add_inherited_template_parms): Likewise. (instantiate_class_template_1): Don't adjust processing_template_decl around the call to make_friend_class. adjust_processing_template_decl to adjust_template_depth. Set current_template_parms instead of processing_template_decl when adjust_template_depth. (make_auto_1): Inspect current_template_depth instead of the magnitude of processing_template_decl. (splice_late_return_type): Likewise. * semantics.c (fixup_template_type): Likewise. gcc/testsuite/ChangeLog: * g++.dg/concepts/diagnostic18.C: Expect a "constraints on a non-templated function" error. * g++.dg/cpp23/auto-fncast11.C: New test. --- gcc/cp/constraint.cc | 16 ----------- gcc/cp/cp-tree.h | 4 ++- gcc/cp/decl.c | 10 +++---- gcc/cp/friend.c | 26 ++++++++++++++--- gcc/cp/parser.c | 28 +++++++----------- gcc/cp/pt.c | 43 +++++++++------------------- gcc/cp/semantics.c | 2 +- gcc/testsuite/g++.dg/concepts/diagnostic18.C | 4 +-- gcc/testsuite/g++.dg/cpp23/auto-fncast11.C | 19 ++++++++++++ 9 files changed, 76 insertions(+), 76 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp23/auto-fncast11.C (limited to 'gcc') diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc index 2896efd..566f4e3 100644 --- a/gcc/cp/constraint.cc +++ b/gcc/cp/constraint.cc @@ -2016,14 +2016,6 @@ type_deducible_p (tree expr, tree type, tree placeholder, tree args, references are preserved in the result. */ expr = force_paren_expr_uneval (expr); - /* When args is NULL, we're evaluating a non-templated requires expression, - but even those are parsed under processing_template_decl == 1, and so the - placeholder 'auto' inside this return-type-requirement has level 2. In - order to have all parms and arguments match up for satisfaction, we need - to pass an empty level of OUTER_TARGS in this case. */ - if (!args) - args = make_tree_vec (0); - tree deduced_type = do_auto_deduction (type, expr, placeholder, info.complain, adc_requirement, /*outer_targs=*/args); @@ -3064,14 +3056,6 @@ normalize_placeholder_type_constraints (tree t, bool diag) parameters for normalization. */ tree initial_parms = TREE_PURPOSE (ci); - if (!initial_parms && TEMPLATE_TYPE_LEVEL (t) == 2) - /* This is a return-type-requirement of a non-templated requires-expression, - which are parsed under processing_template_decl == 1 and empty - current_template_parms; hence the 'auto' has level 2 and initial_parms - is empty. Fix up initial_parms to be consistent with the value of - processing_template_decl whence the 'auto' was created. */ - initial_parms = build_tree_list (size_int (1), make_tree_vec (0)); - /* The 'auto' itself is used as the first argument in its own constraints, and its level is one greater than its template depth. So in order to capture all used template parameters, we need to add an extra level of diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index e4330fb..7f32cf5 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -1886,6 +1886,8 @@ extern GTY(()) struct saved_scope *scope_chain; stored in the TREE_VALUE. */ #define current_template_parms scope_chain->template_parms +#define current_template_depth \ + (current_template_parms ? TMPL_PARMS_DEPTH (current_template_parms) : 0) #define processing_template_decl scope_chain->x_processing_template_decl #define processing_specialization scope_chain->x_processing_specialization @@ -5099,7 +5101,7 @@ more_aggr_init_expr_args_p (const aggr_init_expr_arg_iterator *iter) full specialization. */ #define PROCESSING_REAL_TEMPLATE_DECL_P() \ (!processing_template_parmlist \ - && processing_template_decl > template_class_depth (current_scope ())) + && current_template_depth > template_class_depth (current_scope ())) /* Nonzero if this VAR_DECL or FUNCTION_DECL has already been instantiated, i.e. its definition has been generated from the diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index 56f8077..7c2048c 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -5567,7 +5567,7 @@ start_decl (const cp_declarator *declarator, if (TYPE_P (context) && COMPLETE_TYPE_P (complete_type (context))) { - bool this_tmpl = (processing_template_decl + bool this_tmpl = (current_template_depth > template_class_depth (context)); if (VAR_P (decl)) { @@ -9878,7 +9878,7 @@ grokfndecl (tree ctype, tree ctx = friendp ? current_class_type : ctype; bool block_local = TREE_CODE (current_scope ()) == FUNCTION_DECL; bool memtmpl = (!block_local - && (processing_template_decl + && (current_template_depth > template_class_depth (ctx))); if (memtmpl) { @@ -10300,7 +10300,7 @@ grokfndecl (tree ctype, if (ctype != NULL_TREE && check) { tree old_decl = check_classfn (ctype, decl, - (processing_template_decl + (current_template_depth > template_class_depth (ctype)) ? current_template_parms : NULL_TREE); @@ -10576,7 +10576,7 @@ grokvardecl (tree type, } } else if (flag_concepts - && processing_template_decl > template_class_depth (scope)) + && current_template_depth > template_class_depth (scope)) { tree reqs = TEMPLATE_PARMS_CONSTRAINTS (current_template_parms); tree ci = build_constraints (reqs, NULL_TREE); @@ -13975,7 +13975,7 @@ grokdeclarator (const cp_declarator *declarator, } /* Set the constraints on the declaration. */ - bool memtmpl = (processing_template_decl + bool memtmpl = (current_template_depth > template_class_depth (current_class_type)); if (memtmpl) { diff --git a/gcc/cp/friend.c b/gcc/cp/friend.c index 4f62884..e552659 100644 --- a/gcc/cp/friend.c +++ b/gcc/cp/friend.c @@ -261,7 +261,20 @@ make_friend_class (tree type, tree friend_type, bool complain) The friend is a template friend iff FRIEND_DEPTH is nonzero. */ int class_template_depth = template_class_depth (type); - int friend_depth = processing_template_decl - class_template_depth; + int friend_depth = 0; + if (current_template_depth) + /* When processing a friend declaration at parse time, just compare the + current depth to that of the class template. */ + friend_depth = current_template_depth - class_template_depth; + else + { + /* Otherwise, we got here from instantiate_class_template. Determine + the friend depth by looking at the template parameters used within + FRIEND_TYPE. */ + gcc_checking_assert (class_template_depth == 0); + while (uses_template_parms_level (friend_type, friend_depth + 1)) + ++friend_depth; + } if (! MAYBE_CLASS_TYPE_P (friend_type) && TREE_CODE (friend_type) != TEMPLATE_TEMPLATE_PARM) @@ -351,8 +364,13 @@ make_friend_class (tree type, tree friend_type, bool complain) tree name = TYPE_IDENTIFIER (friend_type); tree decl; - if (!uses_template_parms_level (ctype, class_template_depth - + friend_depth)) + /* We need to distinguish a TYPENAME_TYPE for the non-template + class B in + template friend class A::B; + vs for the class template B in + template template friend class A::B; */ + if (current_template_depth + && !uses_template_parms_level (ctype, current_template_depth)) template_member_p = true; if (class_template_depth) @@ -517,7 +535,7 @@ do_friend (tree ctype, tree declarator, tree decl, 3. TEMPLATE_MEMBER_P is true (for `W'). */ int class_template_depth = template_class_depth (current_class_type); - int friend_depth = processing_template_decl - class_template_depth; + int friend_depth = current_template_depth - class_template_depth; /* We will figure this out later. */ bool template_member_p = false; diff --git a/gcc/cp/parser.c b/gcc/cp/parser.c index 52225d4..c2564e5 100644 --- a/gcc/cp/parser.c +++ b/gcc/cp/parser.c @@ -29779,14 +29779,9 @@ static tree cp_parser_requires_clause_expression (cp_parser *parser, bool lambda_p) { processing_constraint_expression_sentinel parsing_constraint; - temp_override ovr (processing_template_decl); - if (!processing_template_decl) - /* Adjust processing_template_decl so that we always obtain template - trees here. We don't do the usual ++processing_template_decl - because that would skew the template parameter depth of a lambda - within if we're already inside a template. */ - processing_template_decl = 1; + ++processing_template_decl; cp_expr expr = cp_parser_constraint_logical_or_expression (parser, lambda_p); + --processing_template_decl; if (check_for_bare_parameter_packs (expr)) expr = error_mark_node; return expr; @@ -29805,12 +29800,10 @@ static tree cp_parser_constraint_expression (cp_parser *parser) { processing_constraint_expression_sentinel parsing_constraint; - temp_override ovr (processing_template_decl); - if (!processing_template_decl) - /* As in cp_parser_requires_clause_expression. */ - processing_template_decl = 1; + ++processing_template_decl; cp_expr expr = cp_parser_binary_expression (parser, false, true, PREC_NOT_OPERATOR, NULL); + --processing_template_decl; if (check_for_bare_parameter_packs (expr)) expr = error_mark_node; expr.maybe_add_location_wrapper (); @@ -29924,11 +29917,9 @@ cp_parser_requires_expression (cp_parser *parser) parms = NULL_TREE; /* Parse the requirement body. */ - temp_override ovr (processing_template_decl); - if (!processing_template_decl) - /* As in cp_parser_requires_clause_expression. */ - processing_template_decl = 1; + ++processing_template_decl; reqs = cp_parser_requirement_body (parser); + --processing_template_decl; if (reqs == error_mark_node) return error_mark_node; } @@ -48091,6 +48082,10 @@ synthesize_implicit_template_parm (cp_parser *parser, tree constr) gcc_assert(!proto || TREE_CODE (proto) == TYPE_DECL); synth_tmpl_parm = finish_template_type_parm (class_type_node, synth_id); + if (become_template) + current_template_parms = tree_cons (size_int (current_template_depth + 1), + NULL_TREE, current_template_parms); + /* Attach the constraint to the parm before processing. */ tree node = build_tree_list (NULL_TREE, synth_tmpl_parm); TREE_TYPE (node) = constr; @@ -48130,8 +48125,7 @@ synthesize_implicit_template_parm (cp_parser *parser, tree constr) tree new_parms = make_tree_vec (1); TREE_VEC_ELT (new_parms, 0) = parser->implicit_template_parms; - current_template_parms = tree_cons (size_int (processing_template_decl), - new_parms, current_template_parms); + TREE_VALUE (current_template_parms) = new_parms; } else { diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index cbdb4b5..42133a3 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -448,7 +448,7 @@ inline_needs_template_parms (tree decl, bool nsdmi) return false; return (TMPL_PARMS_DEPTH (DECL_TEMPLATE_PARMS (most_general_template (decl))) - > (processing_template_decl + DECL_TEMPLATE_SPECIALIZATION (decl))); + > (current_template_depth + DECL_TEMPLATE_SPECIALIZATION (decl))); } /* Subroutine of maybe_begin_member_template_processing. @@ -467,7 +467,7 @@ push_inline_template_parms_recursive (tree parmlist, int levels) ++processing_template_decl; current_template_parms - = tree_cons (size_int (processing_template_decl), + = tree_cons (size_int (current_template_depth + 1), parms, current_template_parms); TEMPLATE_PARMS_FOR_INLINE (current_template_parms) = 1; @@ -523,7 +523,7 @@ maybe_begin_member_template_processing (tree decl) if (inline_needs_template_parms (decl, nsdmi)) { parms = DECL_TEMPLATE_PARMS (most_general_template (decl)); - levels = TMPL_PARMS_DEPTH (parms) - processing_template_decl; + levels = TMPL_PARMS_DEPTH (parms) - current_template_depth; if (DECL_TEMPLATE_SPECIALIZATION (decl)) { @@ -716,7 +716,7 @@ begin_template_parm_list (void) /* Add a dummy parameter level while we process the parameter list. */ current_template_parms - = tree_cons (size_int (processing_template_decl), + = tree_cons (size_int (current_template_depth + 1), make_tree_vec (0), current_template_parms); } @@ -4613,8 +4613,8 @@ process_template_parm (tree list, location_t parm_loc, tree parm, TREE_CONSTANT (decl) = 1; TREE_READONLY (decl) = 1; DECL_INITIAL (parm) = DECL_INITIAL (decl) - = build_template_parm_index (idx, processing_template_decl, - processing_template_decl, + = build_template_parm_index (idx, current_template_depth, + current_template_depth, decl, TREE_TYPE (parm)); TEMPLATE_PARM_PARAMETER_PACK (DECL_INITIAL (parm)) @@ -4655,8 +4655,8 @@ process_template_parm (tree list, location_t parm_loc, tree parm, TYPE_STUB_DECL (t) = decl; parm = decl; TEMPLATE_TYPE_PARM_INDEX (t) - = build_template_parm_index (idx, processing_template_decl, - processing_template_decl, + = build_template_parm_index (idx, current_template_depth, + current_template_depth, decl, TREE_TYPE (parm)); TEMPLATE_TYPE_PARAMETER_PACK (t) = is_parameter_pack; if (TREE_CODE (t) == TEMPLATE_TEMPLATE_PARM) @@ -4705,7 +4705,7 @@ end_template_parm_list (tree parms) current_template_parms = TREE_CHAIN (current_template_parms); current_template_parms - = tree_cons (size_int (processing_template_decl), + = tree_cons (size_int (current_template_depth + 1), saved_parmlist, current_template_parms); for (unsigned ix = 0; parms; ix++) @@ -5747,7 +5747,7 @@ push_template_decl (tree decl, bool is_friend) /* See if this is a primary template. */ bool is_primary = false; if (is_friend && ctx - && uses_template_parms_level (ctx, processing_template_decl)) + && uses_template_parms_level (ctx, current_template_depth)) /* A friend template that specifies a class context, i.e. template friend void A::f(); is not primary. */ @@ -6157,7 +6157,7 @@ add_inherited_template_parms (tree fn, tree inherited) = INNERMOST_TEMPLATE_PARMS (DECL_TEMPLATE_PARMS (inherited)); inner_parms = copy_node (inner_parms); tree parms - = tree_cons (size_int (processing_template_decl + 1), + = tree_cons (size_int (current_template_depth + 1), inner_parms, current_template_parms); tree tmpl = build_template_decl (fn, parms, /*member*/true); tree args = template_parms_to_args (parms); @@ -12165,13 +12165,10 @@ instantiate_class_template_1 (tree type) /* Build new CLASSTYPE_FRIEND_CLASSES. */ tree friend_type = t; - bool adjust_processing_template_decl = false; - if (TREE_CODE (friend_type) == TEMPLATE_DECL) { /* template friend class C; */ friend_type = tsubst_friend_class (friend_type, args); - adjust_processing_template_decl = true; } else if (TREE_CODE (friend_type) == UNBOUND_CLASS_TEMPLATE) { @@ -12180,7 +12177,6 @@ instantiate_class_template_1 (tree type) tf_warning_or_error, NULL_TREE); if (TREE_CODE (friend_type) == TEMPLATE_DECL) friend_type = TREE_TYPE (friend_type); - adjust_processing_template_decl = true; } else if (TREE_CODE (friend_type) == TYPENAME_TYPE || TREE_CODE (friend_type) == TEMPLATE_TYPE_PARM) @@ -12199,8 +12195,6 @@ instantiate_class_template_1 (tree type) ++processing_template_decl; friend_type = tsubst (friend_type, args, tf_warning_or_error, NULL_TREE); - if (dependent_type_p (friend_type)) - adjust_processing_template_decl = true; --processing_template_decl; } else if (uses_template_parms (friend_type)) @@ -12218,19 +12212,8 @@ instantiate_class_template_1 (tree type) We don't have to do anything in these cases. */ - if (adjust_processing_template_decl) - /* Trick make_friend_class into realizing that the friend - we're adding is a template, not an ordinary class. It's - important that we use make_friend_class since it will - perform some error-checking and output cross-reference - information. */ - ++processing_template_decl; - if (friend_type != error_mark_node) make_friend_class (type, friend_type, /*complain=*/false); - - if (adjust_processing_template_decl) - --processing_template_decl; } else { @@ -28416,7 +28399,7 @@ make_auto_1 (tree name, bool set_canonical) TYPE_NAME (au) = build_decl (input_location, TYPE_DECL, name, au); TYPE_STUB_DECL (au) = TYPE_NAME (au); TEMPLATE_TYPE_PARM_INDEX (au) = build_template_parm_index - (0, processing_template_decl + 1, processing_template_decl + 1, + (0, current_template_depth + 1, current_template_depth + 1, TYPE_NAME (au), NULL_TREE); if (set_canonical) TYPE_CANONICAL (au) = canonical_type_parameter (au); @@ -30069,7 +30052,7 @@ splice_late_return_type (tree type, tree late_return_type) } if (tree auto_node = find_type_usage (type, is_auto)) - if (TEMPLATE_TYPE_LEVEL (auto_node) <= processing_template_decl) + if (TEMPLATE_TYPE_LEVEL (auto_node) <= current_template_depth) { /* In an abbreviated function template we didn't know we were dealing with a function template when we saw the auto return type, so rebuild diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c index cdf63c1..d8b20ff 100644 --- a/gcc/cp/semantics.c +++ b/gcc/cp/semantics.c @@ -3629,7 +3629,7 @@ fixup_template_type (tree type) // the scope we're trying to enter. tree parms = current_template_parms; int depth = template_class_depth (type); - for (int n = processing_template_decl; n > depth && parms; --n) + for (int n = current_template_depth; n > depth && parms; --n) parms = TREE_CHAIN (parms); if (!parms) return type; diff --git a/gcc/testsuite/g++.dg/concepts/diagnostic18.C b/gcc/testsuite/g++.dg/concepts/diagnostic18.C index 79f371b..c13b047 100644 --- a/gcc/testsuite/g++.dg/concepts/diagnostic18.C +++ b/gcc/testsuite/g++.dg/concepts/diagnostic18.C @@ -1,7 +1,7 @@ // PR c++/100055 // { dg-do compile { target concepts } } -void foo(auto&& arg) requires({}); // { dg-error "statement-expressions are not allowed|braced-groups" } +void foo(auto&& arg) requires({}); // { dg-error "statement-expressions are not allowed|braced-groups|non-templated" } template requires ([]{}()); // { dg-error "expected unqualified-id" } -auto f() requires ([]{}()); +auto f() requires ([]{}()); // { dg-error "constraints on a non-templated" } diff --git a/gcc/testsuite/g++.dg/cpp23/auto-fncast11.C b/gcc/testsuite/g++.dg/cpp23/auto-fncast11.C new file mode 100644 index 0000000..669dda1 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp23/auto-fncast11.C @@ -0,0 +1,19 @@ +// PR c++/103408 +// { dg-do compile { target c++23 } } + +static_assert(requires { auto(0); }); +static_assert(requires { auto{0}; }); + +static_assert(requires { auto(auto(0)); }); +static_assert(requires { auto{auto{0}}; }); + +static_assert(requires { auto(auto(auto(0))); }); +static_assert(requires { auto{auto{auto{0}}}; }); + +static_assert(requires { requires auto(true); }); +static_assert(requires { requires auto(auto(true)); }); + +static_assert(!requires { requires auto(false); }); +static_assert(!requires { requires auto(auto(false)); }); + +auto f() requires (auto(false)); // { dg-error "constraints on non-templated" } -- cgit v1.1 From 0dfb1bd94454ccae6d3c77799e209fab7711ed93 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Tue, 14 Dec 2021 15:43:16 +0100 Subject: testsuite: fix ASAN errors The tests failed on my machine as they contain out-of-bounds access. gcc/testsuite/ChangeLog: * gcc.target/i386/avx2-psraq-1.c: Use ARRAY_SIZE. * gcc.target/i386/m128-check.h: Move it to the top-level context. * gcc.target/i386/sse2-psraq-1.c: Use ARRAY_SIZE. * gcc.target/i386/sse4_2-check.h: Include the header with ARRAY_SIZE definition. --- gcc/testsuite/gcc.target/i386/avx2-psraq-1.c | 2 +- gcc/testsuite/gcc.target/i386/m128-check.h | 8 ++++---- gcc/testsuite/gcc.target/i386/sse2-psraq-1.c | 2 +- gcc/testsuite/gcc.target/i386/sse4_2-check.h | 1 + 4 files changed, 7 insertions(+), 6 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/i386/avx2-psraq-1.c b/gcc/testsuite/gcc.target/i386/avx2-psraq-1.c index e9051bf..96e5c4c 100644 --- a/gcc/testsuite/gcc.target/i386/avx2-psraq-1.c +++ b/gcc/testsuite/gcc.target/i386/avx2-psraq-1.c @@ -41,7 +41,7 @@ TEST (void) V a = (V) { 0xdeadbeefcafebabeULL, 0x123456789abcdef0ULL, 0x173a74be8a95134cULL, 0x817bae35ac0ebf12ULL }; int i; - for (i = 0; tests[i].n; i++) + for (i = 0; i < ARRAY_SIZE (tests); i++) { V c = tests[i].fn (a); if (c[0] != a[0] >> tests[i].n || c[1] != a[1] >> tests[i].n diff --git a/gcc/testsuite/gcc.target/i386/m128-check.h b/gcc/testsuite/gcc.target/i386/m128-check.h index c468eac..e90e1f0 100644 --- a/gcc/testsuite/gcc.target/i386/m128-check.h +++ b/gcc/testsuite/gcc.target/i386/m128-check.h @@ -1,6 +1,10 @@ #include #include +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(A) (sizeof (A) / sizeof ((A)[0])) +#endif + #ifdef __SSE2__ #include @@ -66,10 +70,6 @@ typedef union float a[4]; } union128; -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(A) (sizeof (A) / sizeof ((A)[0])) -#endif - #ifdef DEBUG #define PRINTF printf #else diff --git a/gcc/testsuite/gcc.target/i386/sse2-psraq-1.c b/gcc/testsuite/gcc.target/i386/sse2-psraq-1.c index 9a08ee4..dfb0bb8 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-psraq-1.c +++ b/gcc/testsuite/gcc.target/i386/sse2-psraq-1.c @@ -41,7 +41,7 @@ TEST (void) V a = (V) { 0xdeadbeefcafebabeULL, 0x123456789abcdef0ULL }; V b = (V) { 0x173a74be8a95134cULL, 0x817bae35ac0ebf12ULL }; int i; - for (i = 0; tests[i].n; i++) + for (i = 0; i < ARRAY_SIZE (tests); i++) { V c = tests[i].fn (a); if (c[0] != a[0] >> tests[i].n || c[1] != a[1] >> tests[i].n) diff --git a/gcc/testsuite/gcc.target/i386/sse4_2-check.h b/gcc/testsuite/gcc.target/i386/sse4_2-check.h index d10e6c7..c33cd1b 100644 --- a/gcc/testsuite/gcc.target/i386/sse4_2-check.h +++ b/gcc/testsuite/gcc.target/i386/sse4_2-check.h @@ -1,6 +1,7 @@ #include #include +#include "m128-check.h" #include "cpuid.h" static void sse4_2_test (void); -- cgit v1.1 From fdcddba8f29ea3878851b8b4cd37d0fd3476d3bf Mon Sep 17 00:00:00 2001 From: Przemyslaw Wirkus Date: Tue, 14 Dec 2021 14:03:38 +0000 Subject: aarch64: Add LS64 extension and intrinsics This patch is adding support for LS64 (Armv8.7-A Load/Store 64 Byte extension) which is part of Armv8.7-A architecture. Changes include missing plumbing for TARGET_LS64, LS64 data structure and intrinsics defined in ACLE. Machine description of intrinsics is using new V8DI mode added in a separate patch. __ARM_FEATURE_LS64 is defined if the Armv8.7-A LS64 instructions for atomic 64-byte access to device memory are supported. New compiler internal type is added wrapping ACLE struct data512_t: typedef struct { uint64_t val[8]; } __arm_data512_t; gcc/ChangeLog: * config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Define AARCH64_LS64_BUILTIN_LD64B, AARCH64_LS64_BUILTIN_ST64B, AARCH64_LS64_BUILTIN_ST64BV, AARCH64_LS64_BUILTIN_ST64BV0. (aarch64_init_ls64_builtin_decl): Helper function. (aarch64_init_ls64_builtins): Helper function. (aarch64_init_ls64_builtins_types): Helper function. (aarch64_general_init_builtins): Init LS64 intrisics for TARGET_LS64. (aarch64_expand_builtin_ls64): LS64 intrinsics expander. (aarch64_general_expand_builtin): Handle aarch64_expand_builtin_ls64. (ls64_builtins_data): New helper struct. (v8di_UP): New define. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define __ARM_FEATURE_LS64. * config/aarch64/aarch64.c (aarch64_classify_address): Enforce the V8DI range (7-bit signed scaled) for both ends of the range. * config/aarch64/aarch64-simd.md (movv8di): New pattern. (aarch64_movv8di): New pattern. * config/aarch64/aarch64.h (AARCH64_ISA_LS64): New define. (TARGET_LS64): New define. * config/aarch64/aarch64.md: Add UNSPEC_LD64B, UNSPEC_ST64B, UNSPEC_ST64BV and UNSPEC_ST64BV0. (ld64b): New define_insn. (st64b): New define_insn. (st64bv): New define_insn. (st64bv0): New define_insn. * config/aarch64/arm_acle.h (data512_t): New type derived from __arm_data512_t. (__arm_data512_t): New internal type. (__arm_ld64b): New intrinsic. (__arm_st64b): New intrinsic. (__arm_st64bv): New intrinsic. (__arm_st64bv0): New intrinsic. * config/arm/types.md: Add new type ls64. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/ls64_asm.c: New test. * gcc.target/aarch64/acle/ls64_ld64b.c: New test. * gcc.target/aarch64/acle/ls64_ld64b-2.c: New test. * gcc.target/aarch64/acle/ls64_ld64b-3.c: New test. * gcc.target/aarch64/acle/ls64_st64b.c: New test. * gcc.target/aarch64/acle/ls64_ld_st_o0.c: New test. * gcc.target/aarch64/acle/ls64_st64b-2.c: New test. * gcc.target/aarch64/acle/ls64_st64bv.c: New test. * gcc.target/aarch64/acle/ls64_st64bv-2.c: New test. * gcc.target/aarch64/acle/ls64_st64bv-3.c: New test. * gcc.target/aarch64/acle/ls64_st64bv0.c: New test. * gcc.target/aarch64/acle/ls64_st64bv0-2.c: New test. * gcc.target/aarch64/acle/ls64_st64bv0-3.c: New test. * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add checks for __ARM_FEATURE_LS64. --- gcc/config/aarch64/aarch64-builtins.c | 130 +++++++++++++++++++++ gcc/config/aarch64/aarch64-c.c | 2 + gcc/config/aarch64/aarch64-simd.md | 48 ++++++++ gcc/config/aarch64/aarch64.c | 4 + gcc/config/aarch64/aarch64.h | 4 + gcc/config/aarch64/aarch64.md | 52 +++++++++ gcc/config/aarch64/arm_acle.h | 37 ++++++ gcc/config/arm/types.md | 1 + gcc/testsuite/gcc.target/aarch64/acle/ls64_asm.c | 58 +++++++++ .../gcc.target/aarch64/acle/ls64_ld64b-2.c | 15 +++ .../gcc.target/aarch64/acle/ls64_ld64b-3.c | 15 +++ gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b.c | 15 +++ .../gcc.target/aarch64/acle/ls64_ld_st_o0.c | 30 +++++ .../gcc.target/aarch64/acle/ls64_st64b-2.c | 15 +++ gcc/testsuite/gcc.target/aarch64/acle/ls64_st64b.c | 15 +++ .../gcc.target/aarch64/acle/ls64_st64bv-2.c | 15 +++ .../gcc.target/aarch64/acle/ls64_st64bv-3.c | 15 +++ .../gcc.target/aarch64/acle/ls64_st64bv.c | 15 +++ .../gcc.target/aarch64/acle/ls64_st64bv0-2.c | 15 +++ .../gcc.target/aarch64/acle/ls64_st64bv0-3.c | 15 +++ .../gcc.target/aarch64/acle/ls64_st64bv0.c | 15 +++ .../gcc.target/aarch64/pragma_cpp_predefs_2.c | 14 +++ 22 files changed, 545 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_asm.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b-3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_ld_st_o0.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_st64b-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_st64b.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv-3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0-3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0.c (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 303e1e5..0d09fe9 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -49,6 +49,7 @@ #include "gimple-fold.h" #define v8qi_UP E_V8QImode +#define v8di_UP E_V8DImode #define v4hi_UP E_V4HImode #define v4hf_UP E_V4HFmode #define v2si_UP E_V2SImode @@ -607,6 +608,11 @@ enum aarch64_builtins AARCH64_MEMTAG_BUILTIN_SET_TAG, AARCH64_MEMTAG_BUILTIN_GET_TAG, AARCH64_MEMTAG_BUILTIN_END, + /* LS64 builtins. */ + AARCH64_LS64_BUILTIN_LD64B, + AARCH64_LS64_BUILTIN_ST64B, + AARCH64_LS64_BUILTIN_ST64BV, + AARCH64_LS64_BUILTIN_ST64BV0, AARCH64_BUILTIN_MAX }; @@ -1571,6 +1577,70 @@ aarch64_init_memtag_builtins (void) #undef AARCH64_INIT_MEMTAG_BUILTINS_DECL } +/* Add builtins for Load/store 64 Byte instructions. */ + +typedef struct +{ + const char *name; + unsigned int code; + tree type; +} ls64_builtins_data; + +static GTY(()) tree ls64_arm_data_t = NULL_TREE; + +static void +aarch64_init_ls64_builtins_types (void) +{ + /* Synthesize: + + typedef struct { + uint64_t val[8]; + } __arm_data512_t; */ + const char *tuple_type_name = "__arm_data512_t"; + tree node_type = get_typenode_from_name (UINT64_TYPE); + tree array_type = build_array_type_nelts (node_type, 8); + SET_TYPE_MODE (array_type, V8DImode); + + gcc_assert (TYPE_MODE_RAW (array_type) == TYPE_MODE (array_type)); + gcc_assert (TYPE_ALIGN (array_type) == 64); + + tree field = build_decl (input_location, FIELD_DECL, + get_identifier ("val"), array_type); + + ls64_arm_data_t = lang_hooks.types.simulate_record_decl (input_location, + tuple_type_name, + make_array_slice (&field, 1)); + + gcc_assert (TYPE_MODE (ls64_arm_data_t) == V8DImode); + gcc_assert (TYPE_MODE_RAW (ls64_arm_data_t) == TYPE_MODE (ls64_arm_data_t)); + gcc_assert (TYPE_ALIGN (ls64_arm_data_t) == 64); +} + +static void +aarch64_init_ls64_builtins (void) +{ + aarch64_init_ls64_builtins_types (); + + ls64_builtins_data data[4] = { + {"__builtin_aarch64_ld64b", AARCH64_LS64_BUILTIN_LD64B, + build_function_type_list (ls64_arm_data_t, + const_ptr_type_node, NULL_TREE)}, + {"__builtin_aarch64_st64b", AARCH64_LS64_BUILTIN_ST64B, + build_function_type_list (void_type_node, ptr_type_node, + ls64_arm_data_t, NULL_TREE)}, + {"__builtin_aarch64_st64bv", AARCH64_LS64_BUILTIN_ST64BV, + build_function_type_list (uint64_type_node, ptr_type_node, + ls64_arm_data_t, NULL_TREE)}, + {"__builtin_aarch64_st64bv0", AARCH64_LS64_BUILTIN_ST64BV0, + build_function_type_list (uint64_type_node, ptr_type_node, + ls64_arm_data_t, NULL_TREE)}, + }; + + for (size_t i = 0; i < ARRAY_SIZE (data); ++i) + aarch64_builtin_decls[data[i].code] + = aarch64_general_add_builtin (data[i].name, data[i].type, data[i].code); +} + /* Initialize fpsr fpcr getters and setters. */ static void @@ -1660,6 +1730,9 @@ aarch64_general_init_builtins (void) if (TARGET_MEMTAG) aarch64_init_memtag_builtins (); + + if (TARGET_LS64) + aarch64_init_ls64_builtins (); } /* Implement TARGET_BUILTIN_DECL for the AARCH64_BUILTIN_GENERAL group. */ @@ -2130,6 +2203,57 @@ aarch64_expand_builtin_tme (int fcode, tree exp, rtx target) return target; } +/* Function to expand an expression EXP which calls one of the Load/Store + 64 Byte extension (LS64) builtins FCODE with the result going to TARGET. */ +static rtx +aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target) +{ + expand_operand ops[3]; + + switch (fcode) + { + case AARCH64_LS64_BUILTIN_LD64B: + { + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + create_output_operand (&ops[0], target, V8DImode); + create_input_operand (&ops[1], op0, DImode); + expand_insn (CODE_FOR_ld64b, 2, ops); + return ops[0].value; + } + case AARCH64_LS64_BUILTIN_ST64B: + { + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); + create_output_operand (&ops[0], op0, DImode); + create_input_operand (&ops[1], op1, V8DImode); + expand_insn (CODE_FOR_st64b, 2, ops); + return const0_rtx; + } + case AARCH64_LS64_BUILTIN_ST64BV: + { + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); + create_output_operand (&ops[0], target, DImode); + create_input_operand (&ops[1], op0, DImode); + create_input_operand (&ops[2], op1, V8DImode); + expand_insn (CODE_FOR_st64bv, 3, ops); + return ops[0].value; + } + case AARCH64_LS64_BUILTIN_ST64BV0: + { + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1)); + create_output_operand (&ops[0], target, DImode); + create_input_operand (&ops[1], op0, DImode); + create_input_operand (&ops[2], op1, V8DImode); + expand_insn (CODE_FOR_st64bv0, 3, ops); + return ops[0].value; + } + } + + gcc_unreachable (); +} + /* Expand a random number builtin EXP with code FCODE, putting the result int TARGET. If IGNORE is true the return value is ignored. */ @@ -2388,6 +2512,12 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target, || fcode == AARCH64_TME_BUILTIN_TCANCEL) return aarch64_expand_builtin_tme (fcode, exp, target); + if (fcode == AARCH64_LS64_BUILTIN_LD64B + || fcode == AARCH64_LS64_BUILTIN_ST64B + || fcode == AARCH64_LS64_BUILTIN_ST64BV + || fcode == AARCH64_LS64_BUILTIN_ST64BV0) + return aarch64_expand_builtin_ls64 (fcode, exp, target); + if (fcode >= AARCH64_MEMTAG_BUILTIN_START && fcode <= AARCH64_MEMTAG_BUILTIN_END) return aarch64_expand_builtin_memtag (fcode, exp, target); diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index d6653e4..3af3e5c 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -200,6 +200,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile); aarch64_def_or_undef (TARGET_BF16_FP, "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC", pfile); + aarch64_def_or_undef (TARGET_LS64, + "__ARM_FEATURE_LS64", pfile); /* Not for ACLE, but required to keep "float.h" correct if we switch target between implementations that do or do not support ARMv8.2-A diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 175a9f0..9ebf795 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -7123,6 +7123,15 @@ } }) +(define_expand "movv8di" + [(set (match_operand:V8DI 0 "nonimmediate_operand") + (match_operand:V8DI 1 "general_operand"))] + "TARGET_SIMD" +{ + if (can_create_pseudo_p () && MEM_P (operands[0])) + operands[1] = force_reg (V8DImode, operands[1]); +}) + (define_expand "aarch64_ld1x3" [(match_operand:VSTRUCT_3QD 0 "register_operand") (match_operand:DI 1 "register_operand")] @@ -7253,6 +7262,17 @@ (set_attr "length" ",4,4")] ) +(define_insn "*aarch64_movv8di" + [(set (match_operand:V8DI 0 "nonimmediate_operand" "=r,m,r") + (match_operand:V8DI 1 "general_operand" " r,r,m"))] + "!BYTES_BIG_ENDIAN + && (register_operand (operands[0], V8DImode) + || register_operand (operands[1], V8DImode))" + "#" + [(set_attr "type" "multiple,multiple,multiple") + (set_attr "length" "32,16,16")] +) + (define_insn "aarch64_be_ld1" [(set (match_operand:VALLDI_F16 0 "register_operand" "=w") (unspec:VALLDI_F16 [(match_operand:VALLDI_F16 1 @@ -7496,6 +7516,34 @@ FAIL; }) +(define_split + [(set (match_operand:V8DI 0 "nonimmediate_operand") + (match_operand:V8DI 1 "general_operand"))] + "TARGET_SIMD && reload_completed" + [(const_int 0)] +{ + if (register_operand (operands[0], V8DImode) + && register_operand (operands[1], V8DImode)) + { + aarch64_simd_emit_reg_reg_move (operands, DImode, 8); + DONE; + } + else if ((register_operand (operands[0], V8DImode) + && memory_operand (operands[1], V8DImode)) + || (memory_operand (operands[0], V8DImode) + && register_operand (operands[1], V8DImode))) + { + for (int offset = 0; offset < 64; offset += 16) + emit_move_insn (simplify_gen_subreg (TImode, operands[0], + V8DImode, offset), + simplify_gen_subreg (TImode, operands[1], + V8DImode, offset)); + DONE; + } + else + FAIL; +}) + (define_expand "aarch64_ldr" [(match_operand:VSTRUCT_QD 0 "register_operand") (match_operand:DI 1 "register_operand")] diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d11a40c..f07330c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -10016,6 +10016,10 @@ aarch64_classify_address (struct aarch64_address_info *info, && (aarch64_offset_9bit_signed_unscaled_p (mode, offset) || offset_12bit_unsigned_scaled_p (mode, offset))); + if (mode == V8DImode) + return (aarch64_offset_7bit_signed_scaled_p (DImode, offset) + && aarch64_offset_7bit_signed_scaled_p (DImode, offset + 48)); + /* A 7bit offset check because OImode will emit a ldp/stp instruction (only big endian will get here). For ldp/stp instructions, the offset is scaled for the size of a diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 5a590aa..fb2d2ed 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -319,6 +319,7 @@ extern unsigned aarch64_architecture_version; #define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH) #define AARCH64_ISA_V9 (aarch64_isa_flags & AARCH64_FL_V9) #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) +#define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64) /* Crypto is an optional extension to AdvSIMD. */ #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) @@ -413,6 +414,9 @@ extern unsigned aarch64_architecture_version; /* MOPS instructions are enabled through +mops. */ #define TARGET_MOPS (AARCH64_ISA_MOPS) +/* LS64 instructions are enabled through +ls64. */ +#define TARGET_LS64 (AARCH64_ISA_LS64) + /* Make sure this is always defined so we don't have to check for ifdefs but rather use normal ifs. */ #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 9e50a26..dcdffc8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -188,6 +188,12 @@ UNSPEC_LD2_LANE UNSPEC_LD3_LANE UNSPEC_LD4_LANE + UNSPEC_LD64B + UNSPEC_ST64B + UNSPEC_ST64BV + UNSPEC_ST64BV_RET + UNSPEC_ST64BV0 + UNSPEC_ST64BV0_RET UNSPEC_MB UNSPEC_MOVMEM UNSPEC_NOP @@ -7571,6 +7577,52 @@ [(set_attr "type" "memtag")] ) +;; Load/Store 64-bit (LS64) instructions. +(define_insn "ld64b" + [(set (match_operand:V8DI 0 "register_operand" "=r") + (unspec_volatile:V8DI + [(mem:V8DI (match_operand:DI 1 "register_operand" "r"))] + UNSPEC_LD64B) + )] + "TARGET_LS64" + "ld64b\\t%0, [%1]" + [(set_attr "type" "ls64")] +) + +(define_insn "st64b" + [(set (mem:V8DI (match_operand:DI 0 "register_operand" "=r")) + (unspec_volatile:V8DI [(match_operand:V8DI 1 "register_operand" "r")] + UNSPEC_ST64B) + )] + "TARGET_LS64" + "st64b\\t%1, [%0]" + [(set_attr "type" "ls64")] +) + +(define_insn "st64bv" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV_RET)) + (set (mem:V8DI (match_operand:DI 1 "register_operand" "r")) + (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] + UNSPEC_ST64BV) + )] + "TARGET_LS64" + "st64bv\\t%0, %2, [%1]" + [(set_attr "type" "ls64")] +) + +(define_insn "st64bv0" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec_volatile:DI [(const_int 0)] UNSPEC_ST64BV0_RET)) + (set (mem:V8DI (match_operand:DI 1 "register_operand" "r")) + (unspec_volatile:V8DI [(match_operand:V8DI 2 "register_operand" "r")] + UNSPEC_ST64BV0) + )] + "TARGET_LS64" + "st64bv0\\t%0, %2, [%1]" + [(set_attr "type" "ls64")] +) + ;; AdvSIMD Stuff (include "aarch64-simd.md") diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index 13f2363..030e343 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -214,6 +214,43 @@ __ttest (void) #pragma GCC pop_options #endif +#ifdef __ARM_FEATURE_LS64 +#pragma GCC push_options +#pragma GCC target ("+nothing+ls64") + +typedef __arm_data512_t data512_t; + +__extension__ extern __inline data512_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_ld64b (const void *__addr) +{ + return __builtin_aarch64_ld64b (__addr); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_st64b (void *__addr, data512_t __value) +{ + __builtin_aarch64_st64b (__addr, __value); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_st64bv (void *__addr, data512_t __value) +{ + return __builtin_aarch64_st64bv (__addr, __value); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_st64bv0 (void *__addr, data512_t __value) +{ + return __builtin_aarch64_st64bv0 (__addr, __value); +} + +#pragma GCC pop_options +#endif + #pragma GCC push_options #pragma GCC target ("+nothing+rng") __extension__ extern __inline int diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index b9514da..6dce71f 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -1122,6 +1122,7 @@ coproc,\ tme,\ memtag,\ + ls64,\ mve_move,\ mve_store,\ mve_load" diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_asm.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_asm.c new file mode 100644 index 0000000..ba9960c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_asm.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +/* Inline assembly for LS64 instructions. */ + +#include + +void +ls64_load (data512_t *output, const void *addr) +{ + __asm__ volatile ("ld64b %0, [%1]" + : "=r" (*output) + : "r" (addr) + : "memory"); +} + +/* { dg-final { scan-assembler-times {ld64b } 1 } } */ + +void +ls64_store (const data512_t *input, void *addr) +{ + __asm__ volatile ("st64b %1, [%0]" + : /* No outputs. */ + : "r" (addr), "r" (*input) + : "memory"); +} + +/* { dg-final { scan-assembler-times {st64b } 1 } } */ + +uint64_t +ls64_store_v (const data512_t *input, void *addr) +{ + uint64_t status; + __asm__ volatile ("st64bv %0, %2, [%1]" + : "=r" (status) + : "r" (addr), "r" (*input) + : "memory"); + return status; +} + +/* { dg-final { scan-assembler-times {st64bv } 1 } } */ + +uint64_t +ls64_store_v0 (const data512_t *input, void *addr) +{ + uint64_t status; + __asm__ volatile ("st64bv0 %0, %2, [%1]" + : "=r" (status) + : "r" (addr), "r" (*input) + : "memory"); + return status; +} + +/* { dg-final { scan-assembler-times {st64bv0 } 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b-2.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b-2.c new file mode 100644 index 0000000..2a94657 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +void +func (const void * addr) { + data512_t ret = __arm_ld64b (addr); +} + +/* { dg-final { scan-assembler-times {ld64b\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b-3.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b-3.c new file mode 100644 index 0000000..155ea40 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +void +func(const void * addr, data512_t *data) { + *data = __arm_ld64b (addr); +} + +/* { dg-final { scan-assembler-times {ld64b\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b.c new file mode 100644 index 0000000..e3fc141 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld64b.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +data512_t +func(const void * addr) { + return __arm_ld64b (addr); +} + +/* { dg-final { scan-assembler-times {ld64b\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld_st_o0.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld_st_o0.c new file mode 100644 index 0000000..550d75c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_ld_st_o0.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O0" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +/* Make sure no issues when compile with -O0. */ + +data512_t +func1 (const void * addr) { + return __arm_ld64b (addr); +} + +void +func2 (void *addr, data512_t value) { + __arm_st64b (addr, value); +} + +uint64_t +func3 (void *addr, data512_t value) { + return __arm_st64bv (addr, value); +} + +uint64_t +func4 (void *addr, data512_t value) { + return __arm_st64bv0 (addr, value); +} diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64b-2.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64b-2.c new file mode 100644 index 0000000..bfd737b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64b-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +void +func(void *addr, data512_t *value) { + __arm_st64b (addr, *value); +} + +/* { dg-final { scan-assembler-times {st64b\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64b.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64b.c new file mode 100644 index 0000000..75b9180 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64b.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +void +func(void *addr, data512_t value) { + __arm_st64b (addr, value); +} + +/* { dg-final { scan-assembler-times {st64b\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv-2.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv-2.c new file mode 100644 index 0000000..c3ef83e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +void +func(void *addr, data512_t value) { + __arm_st64bv (addr, value); +} + +/* { dg-final { scan-assembler-times {st64bv\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv-3.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv-3.c new file mode 100644 index 0000000..370db79 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +void +func(void *addr, data512_t *value) { + __arm_st64bv (addr, *value); +} + +/* { dg-final { scan-assembler-times {st64bv\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv.c new file mode 100644 index 0000000..52ef9c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +uint64_t +func(void *addr, data512_t value) { + return __arm_st64bv (addr, value); +} + +/* { dg-final { scan-assembler-times {st64bv\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0-2.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0-2.c new file mode 100644 index 0000000..c49fa56 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +void +func(void *addr, data512_t value) { + __arm_st64bv0 (addr, value); +} + +/* { dg-final { scan-assembler-times {st64bv0\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0-3.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0-3.c new file mode 100644 index 0000000..af6917c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +void +func(void *addr, data512_t *value) { + __arm_st64bv0 (addr, *value); +} + +/* { dg-final { scan-assembler-times {st64bv0\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0.c b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0.c new file mode 100644 index 0000000..bce10ae --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/ls64_st64bv0.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a+ls64 -O2" } */ + +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif + +#include + +uint64_t +func(void *addr, data512_t value) { + return __arm_st64bv0 (addr, value); +} + +/* { dg-final { scan-assembler-times {st64bv0\t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c index 7244359..2d76bfc 100644 --- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c +++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c @@ -240,6 +240,20 @@ #endif #pragma GCC pop_options +#pragma GCC push_options +#pragma GCC target ("arch=armv8.7-a") +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif +#pragma GCC pop_options + +#pragma GCC push_options +#pragma GCC target ("arch=armv8.7-a+ls64") +#ifndef __ARM_FEATURE_LS64 +#error "__ARM_FEATURE_LS64 is not defined but should be!" +#endif +#pragma GCC pop_options + #pragma GCC pop_options int -- cgit v1.1 From 973f6aedeb6489a9fdc7aeceaed0514348ee1e1a Mon Sep 17 00:00:00 2001 From: "Vladimir N. Makarov" Date: Tue, 14 Dec 2021 08:57:30 -0500 Subject: [PR99531] Do not scan push insn for ia32 in the test The patch prohibits scanning push insn for ia32 as push are expected not to be generated only for x86_64 Linux ABI. gcc/testsuite/ChangeLog: PR target/99531 * gcc.target/i386/pr99531.c: Do not scan for ia32. --- gcc/testsuite/gcc.target/i386/pr99531.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/gcc.target/i386/pr99531.c b/gcc/testsuite/gcc.target/i386/pr99531.c index 0e1a08b..9853645 100644 --- a/gcc/testsuite/gcc.target/i386/pr99531.c +++ b/gcc/testsuite/gcc.target/i386/pr99531.c @@ -4,4 +4,4 @@ int func(int, int, int, int, int, int); int caller(int a, int b, int c, int d, int e) { return func(0, a, b, c, d, e); } -/* { dg-final { scan-assembler-not "push" } } */ +/* { dg-final { scan-assembler-not "push" { target { ! ia32 } } } } */ -- cgit v1.1 From f1215db08126fbd2d69d971d65611508cf83b4ae Mon Sep 17 00:00:00 2001 From: Manfred Schwarb Date: Tue, 14 Dec 2021 16:28:58 +0100 Subject: fortran: Silence conversion warnings for MIN1 and MAX1 gcc/fortran/ChangeLog: PR fortran/91497 * simplify.c (simplify_min_max): Disable conversion warnings for MIN1 and MAX1. --- gcc/fortran/simplify.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'gcc') diff --git a/gcc/fortran/simplify.c b/gcc/fortran/simplify.c index fb7b781..90067b6 100644 --- a/gcc/fortran/simplify.c +++ b/gcc/fortran/simplify.c @@ -5096,6 +5096,7 @@ min_max_choose (gfc_expr *arg, gfc_expr *extremum, int sign, bool back_val) static gfc_expr * simplify_min_max (gfc_expr *expr, int sign) { + int tmp1, tmp2; gfc_actual_arglist *arg, *last, *extremum; gfc_expr *tmp, *ret; const char *fname; @@ -5140,7 +5141,16 @@ simplify_min_max (gfc_expr *expr, int sign) if ((tmp->ts.type != BT_INTEGER || tmp->ts.kind != gfc_integer_4_kind) && (strcmp (fname, "min1") == 0 || strcmp (fname, "max1") == 0)) { + /* Explicit conversion, turn off -Wconversion and -Wconversion-extra + warnings. */ + tmp1 = warn_conversion; + tmp2 = warn_conversion_extra; + warn_conversion = warn_conversion_extra = 0; + ret = gfc_convert_constant (tmp, BT_INTEGER, gfc_integer_4_kind); + + warn_conversion = tmp1; + warn_conversion_extra = tmp2; } else if ((tmp->ts.type != BT_REAL || tmp->ts.kind != gfc_real_4_kind) && (strcmp (fname, "amin0") == 0 || strcmp (fname, "amax0") == 0)) -- cgit v1.1 From 44aa890d8fb4afa843cf6cb7452fd5d6f3dd61fe Mon Sep 17 00:00:00 2001 From: Manfred Schwarb Date: Tue, 14 Dec 2021 16:30:27 +0100 Subject: testsuite: Silence conversion warnings for MIN1 and MAX1 gcc/testsuite/ChangeLog: PR fortran/91497 * gfortran.dg/pr91497.f90: Adjust test to use dg-require-effective-target directive. * gfortran.dg/pr91497_2.f90: New test to cover all targets. Cover MAX1 and MIN1 intrinsics. --- gcc/testsuite/gfortran.dg/pr91497.f90 | 23 +++--- gcc/testsuite/gfortran.dg/pr91497_2.f90 | 124 ++++++++++++++++++++++++++++++++ 2 files changed, 136 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/pr91497_2.f90 (limited to 'gcc') diff --git a/gcc/testsuite/gfortran.dg/pr91497.f90 b/gcc/testsuite/gfortran.dg/pr91497.f90 index d324b3b..f4005e5 100644 --- a/gcc/testsuite/gfortran.dg/pr91497.f90 +++ b/gcc/testsuite/gfortran.dg/pr91497.f90 @@ -1,4 +1,6 @@ -! { dg-do compile { target { i?86-*-* x86_64-*-* } } } +! { dg-do compile } +! { dg-require-effective-target fortran_real_10 } +! { dg-require-effective-target fortran_real_16 } ! { dg-options "-Wall" } ! Code contributed by Manfred Schwarb ! PR fortran/91497 @@ -8,13 +10,13 @@ ! program foo - real*4 a,aa - real*8 b,bb - real*10 c,cc - real*16 d - integer*2 e,ee - integer*4 f,ff - integer*8 g,gg + real(4) a,aa + real(8) b,bb + real(10) c,cc + real(16) d + integer(2) e,ee + integer(4) f,ff + integer(8) g,gg PARAMETER(a=3.1415927_4) PARAMETER(b=3.1415927_8) PARAMETER(c=3.1415927_10) @@ -36,11 +38,10 @@ program foo aa=CEILING(b) aa=CEILING(c) aa=CEILING(d) - !---unknown but documented type conversions: + !---DEC specific type conversions (-fdec): !!aa=FLOATI(e) !!aa=FLOATJ(f) !!aa=FLOATK(g) - !---documentation is wrong for sngl: aa=SNGL(c) aa=SNGL(d) bb=REAL(c, kind=8) @@ -98,7 +99,7 @@ program foo ff=IFIX(a) ff=IDINT(b) ff=IDNINT(b) - !---LONG not allowed anymore in gfortran 10 (?): + !---LONG support got removed: !!ff=LONG(a) !!ff=LONG(b) !!ff=LONG(c) diff --git a/gcc/testsuite/gfortran.dg/pr91497_2.f90 b/gcc/testsuite/gfortran.dg/pr91497_2.f90 new file mode 100644 index 0000000..28aa4bd --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pr91497_2.f90 @@ -0,0 +1,124 @@ +! { dg-do compile } +! { dg-options "-Wall" } +! Code contributed by Manfred Schwarb +! PR fortran/91497 +! +! Prior to applying the patch for this PR, the following code +! would generate numerous conversion warnings. +! Additional test case to cover all targets. +! +program foo + + real(4) a, aa + real(8) b, bb + integer(2) e, ee + integer(4) f, ff + integer(8) g, gg + complex(4) ww + complex(8) xx + PARAMETER(a=3.1415927_4) + PARAMETER(b=3.1415927_8) + PARAMETER(e=123_2) + PARAMETER(f=123_4) + PARAMETER(g=123_8) + + aa=REAL(b) ! was: Change of value in conversion from 'REAL(8)' to 'REAL(4)' + aa=REAL(e) + aa=REAL(f) + aa=REAL(g) + aa=REAL(b, kind=4) ! was: Change of value in conversion from 'REAL(8)' to 'REAL(4)' + bb=REAL(a, kind=8) + + aa=FLOAT(f) + bb=DFLOAT(g) + aa=SNGL(b) ! was: Change of value in conversion from 'REAL(8)' to 'REAL(4)' + aa=AINT(a) + bb=AINT(b) + aa=AINT(b, kind=4) + bb=DINT(b) + aa=ANINT(a) + bb=ANINT(b) + aa=ANINT(b, kind=4) + bb=DNINT(b) + aa=AMAX0(f, f) + aa=AMIN0(f, f) + aa=AMAX0(g, g) + aa=AMIN0(g, g) + + ee=INT(a) + ee=INT(a, kind=2) ! was: Change of value in conversion from 'REAL(4)' to 'INTEGER(2)' + ee=INT(b, kind=2) ! was: Change of value in conversion from 'REAL(8)' to 'INTEGER(2)' + ee=INT(f, kind=2) + ee=INT(g, kind=2) + ff=INT(b) + ff=INT(a, kind=4) ! was: Change of value in conversion from 'REAL(4)' to 'INTEGER(4)' + ff=INT(b, kind=4) ! was: Change of value in conversion from 'REAL(8)' to 'INTEGER(4)' + ff=INT(f, kind=4) + ff=INT(g, kind=4) + gg=INT(a) + gg=INT(a, kind=8) ! was: Change of value in conversion from 'REAL(4)' to 'INTEGER(8)' + gg=INT(b, kind=8) ! was: Change of value in conversion from 'REAL(8)' to 'INTEGER(8)' + gg=INT(f, kind=8) + gg=INT(g, kind=8) + + ee=IFIX(a) + ff=IFIX(a) + gg=IFIX(a) + ee=IDINT(b) + ff=IDINT(b) + gg=IDINT(b) + ee=INT2(a) ! was: Change of value in conversion from 'REAL(4)' to 'INTEGER(2)' + ee=INT2(b) ! was: Change of value in conversion from 'REAL(8)' to 'INTEGER(2)' + ee=INT2(f) + ee=INT2(g) + gg=INT8(a) ! was: Change of value in conversion from 'REAL(4)' to 'INTEGER(8)' + gg=INT8(b) ! was: Change of value in conversion from 'REAL(8)' to 'INTEGER(8)' + gg=INT8(f) + gg=INT8(g) + + ff=FLOOR(b) + ee=FLOOR(b, kind=2) + ff=FLOOR(b, kind=4) + gg=FLOOR(b, kind=8) + ff=CEILING(b) + ee=CEILING(b, kind=2) + ff=CEILING(b, kind=4) + gg=CEILING(b, kind=8) + ff=MAX1(a, a) ! was: Change of value in conversion from 'REAL(4)' to 'INTEGER(4)' + ff=MIN1(a, a) ! was: Change of value in conversion from 'REAL(4)' to 'INTEGER(4)' + gg=MAX1(b, b) ! was: Change of value in conversion from 'REAL(8)' to 'INTEGER(4)' + gg=MIN1(b, b) ! was: Change of value in conversion from 'REAL(8)' to 'INTEGER(4)' + + ee=NINT(a, kind=2) + ee=NINT(b, kind=2) + ff=NINT(a) + ff=NINT(b) + ff=NINT(a, kind=4) + ff=NINT(b, kind=4) + gg=NINT(a, kind=8) + gg=NINT(b, kind=8) + ee=IDNINT(b) + ff=IDNINT(b) + gg=IDNINT(b) + + ww=COMPLEX(a, a) + ww=COMPLEX(e, e) + ww=COMPLEX(g, g) + ww=COMPLEX(a, g) + xx=COMPLEX(b, g) + ww=CMPLX(a, a) + ww=CMPLX(b, b, kind=4) + xx=CMPLX(a, a, kind=8) + + aa=REAL(ww) + bb=REAL(xx) + aa=REALPART(ww) + bb=REALPART(xx) + aa=AIMAG(ww) + bb=AIMAG(xx) + aa=IMAG(ww) + bb=IMAG(xx) + bb=DIMAG(xx) + aa=IMAGPART(ww) + bb=IMAGPART(xx) +end -- cgit v1.1 From 3305135c29e1c3e988bd9bad40aefc01d138aaca Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Tue, 14 Dec 2021 16:50:27 +0100 Subject: Determine global memory accesses in ipa-modref As discussed in PR103585, fatigue2 is now only benchmark from my usual testing set (SPEC2k6, SPEC2k17, CPP benchmarks, polyhedron, Firefox, clang) which sees important regression when inlining functions called once is limited. This prevents us from solving runtime issues in roms benchmarks and elsewhere. The problem is that there is perdida function that takes many arguments and some of them are array descriptors. We constant propagate most of their fields but still keep their initialization. Because perdida is quite fast, the call overhead dominates, since we need over 100 memory stores consuing about 35% of the overall benchmark runtime. The memory stores would be eliminated if perdida did not call fortran I/O which makes modref to thin that the array descriptors could be accessed. We are quite close discovering that they can't becuase they are non-escaping from function. This patch makes modref to distingush between global memory access (only things that escapes) and unkonwn accesss (that may access also nonescaping things reaching the function). This makes disambiguation for functions containing error handling better. Unfortunately the patch hits two semi-latent issues in Fortran frontned. First is wrong code in gfortran.dg/unlimited_polymorphic_3.f03. This can be turned into wrong code testcase on both mainline and gcc11 if the runtime call is removed, so I filled PR 103662 for it. There is TBAA mismatch for structure produced in FE. Second is issue with GOMP where Fortran marks certain parameters as non-escaping and then makes them escape via GOMP_parallel. For this I disabled the use of escape info in verify_arg which also disables the useful transform on perdida but still does useful work for e.g. GCC error handling. I will work on this incrementally. Bootstrapped/regtested x86_64-linux, lto-bootstrapped and also tested with clang build. I plan to commit this tomorrow if there are no complains (the patch is not completely short but conceptualy simple and handles a lot of common cases). gcc/ChangeLog: 2021-12-12 Jan Hubicka PR ipa/103585 * ipa-modref-tree.c (modref_access_node::range_info_useful_p): Handle MODREF_GLOBAL_MEMORY_PARM. (modref_access_node::dump): Likewise. (modref_access_node::get_call_arg): Likewise. * ipa-modref-tree.h (enum modref_special_parms): Add MODREF_GLOBAL_MEMORY_PARM. (modref_access_node::useful_for_kill): Handle MODREF_GLOBAL_MEMORY_PARM. (modref:tree::merge): Add promote_unknown_to_global. * ipa-modref.c (verify_arg):New function. (may_access_nonescaping_parm_p): New function. (modref_access_analysis::record_global_memory_load): New member function. (modref_access_analysis::record_global_memory_store): Likewise. (modref_access_analysis::process_fnspec): Distingush global and local memory. (modref_access_analysis::analyze_call): Likewise. * tree-ssa-alias.c (ref_may_access_global_memory_p): New function. (modref_may_conflict): Use it. gcc/testsuite/ChangeLog: 2021-12-12 Jan Hubicka * gcc.dg/analyzer/data-model-1.c: Disable ipa-modref. * gcc.dg/uninit-38.c: Likewise. * gcc.dg/uninit-pr98578.c: Liewise. --- gcc/ipa-modref-tree.c | 14 ++- gcc/ipa-modref-tree.h | 25 ++++- gcc/ipa-modref.c | 160 ++++++++++++++++++++++++--- gcc/testsuite/gcc.dg/analyzer/data-model-1.c | 1 + gcc/testsuite/gcc.dg/uninit-38.c | 2 +- gcc/testsuite/gcc.dg/uninit-pr98578.c | 2 +- gcc/tree-ssa-alias.c | 36 ++++++ 7 files changed, 214 insertions(+), 26 deletions(-) (limited to 'gcc') diff --git a/gcc/ipa-modref-tree.c b/gcc/ipa-modref-tree.c index a868e3e..64ef077 100644 --- a/gcc/ipa-modref-tree.c +++ b/gcc/ipa-modref-tree.c @@ -36,7 +36,8 @@ modref_access_node::operator == (modref_access_node &a) const { if (parm_index != a.parm_index) return false; - if (parm_index != MODREF_UNKNOWN_PARM) + if (parm_index != MODREF_UNKNOWN_PARM + && parm_index != MODREF_GLOBAL_MEMORY_PARM) { if (parm_offset_known != a.parm_offset_known) return false; @@ -613,7 +614,9 @@ modref_access_node::insert (vec *&accesses, bool modref_access_node::range_info_useful_p () const { - return parm_index != MODREF_UNKNOWN_PARM && parm_offset_known + return parm_index != MODREF_UNKNOWN_PARM + && parm_index != MODREF_GLOBAL_MEMORY_PARM + && parm_offset_known && (known_size_p (size) || known_size_p (max_size) || known_ge (offset, 0)); @@ -625,7 +628,9 @@ modref_access_node::dump (FILE *out) { if (parm_index != MODREF_UNKNOWN_PARM) { - if (parm_index >= 0) + if (parm_index == MODREF_GLOBAL_MEMORY_PARM) + fprintf (out, " Base in global memory"); + else if (parm_index >= 0) fprintf (out, " Parm %i", parm_index); else if (parm_index == MODREF_STATIC_CHAIN_PARM) fprintf (out, " Static chain"); @@ -655,7 +660,8 @@ modref_access_node::dump (FILE *out) tree modref_access_node::get_call_arg (const gcall *stmt) const { - if (parm_index == MODREF_UNKNOWN_PARM) + if (parm_index == MODREF_UNKNOWN_PARM + || parm_index == MODREF_GLOBAL_MEMORY_PARM) return NULL; if (parm_index == MODREF_STATIC_CHAIN_PARM) return gimple_call_chain (stmt); diff --git a/gcc/ipa-modref-tree.h b/gcc/ipa-modref-tree.h index 4ad556f..94fcebd 100644 --- a/gcc/ipa-modref-tree.h +++ b/gcc/ipa-modref-tree.h @@ -48,10 +48,12 @@ enum modref_special_parms { MODREF_UNKNOWN_PARM = -1, MODREF_STATIC_CHAIN_PARM = -2, MODREF_RETSLOT_PARM = -3, + /* Used for bases that points to memory that escapes from function. */ + MODREF_GLOBAL_MEMORY_PARM = -4, /* Used in modref_parm_map to tak references which can be removed from the summary during summary update since they now points to loca memory. */ - MODREF_LOCAL_MEMORY_PARM = -4 + MODREF_LOCAL_MEMORY_PARM = -5 }; /* Modref record accesses relative to function parameters. @@ -86,6 +88,7 @@ struct GTY(()) modref_access_node bool useful_for_kill_p () const { return parm_offset_known && parm_index != MODREF_UNKNOWN_PARM + && parm_index != MODREF_GLOBAL_MEMORY_PARM && parm_index != MODREF_RETSLOT_PARM && known_size_p (size) && known_eq (max_size, size) && known_gt (size, 0); @@ -175,6 +178,7 @@ struct GTY((user)) modref_ref_node in the caller. */ gcc_checking_assert (a.parm_index >= 0 || a.parm_index == MODREF_STATIC_CHAIN_PARM + || a.parm_index == MODREF_GLOBAL_MEMORY_PARM || a.parm_index == MODREF_UNKNOWN_PARM); if (!a.useful_p ()) @@ -524,7 +528,8 @@ struct GTY((user)) modref_tree unsigned int max_accesses, modref_tree *other, vec *parm_map, modref_parm_map *static_chain_map, - bool record_accesses) + bool record_accesses, + bool promote_unknown_to_global = false) { if (!other || every_base) return false; @@ -579,7 +584,9 @@ struct GTY((user)) modref_tree { modref_access_node a = *access_node; - if (a.parm_index != MODREF_UNKNOWN_PARM && parm_map) + if (a.parm_index != MODREF_UNKNOWN_PARM + && a.parm_index != MODREF_GLOBAL_MEMORY_PARM + && parm_map) { if (a.parm_index >= (int)parm_map->length ()) a.parm_index = MODREF_UNKNOWN_PARM; @@ -596,6 +603,9 @@ struct GTY((user)) modref_tree a.parm_index = m.parm_index; } } + if (a.parm_index == MODREF_UNKNOWN_PARM + && promote_unknown_to_global) + a.parm_index = MODREF_GLOBAL_MEMORY_PARM; changed |= insert (max_bases, max_refs, max_accesses, base_node->base, ref_node->ref, a, record_accesses); @@ -614,12 +624,14 @@ struct GTY((user)) modref_tree bool merge (tree fndecl, modref_tree *other, vec *parm_map, modref_parm_map *static_chain_map, - bool record_accesses) + bool record_accesses, + bool promote_unknown_to_global = false) { return merge (opt_for_fn (fndecl, param_modref_max_bases), opt_for_fn (fndecl, param_modref_max_refs), opt_for_fn (fndecl, param_modref_max_accesses), - other, parm_map, static_chain_map, record_accesses); + other, parm_map, static_chain_map, record_accesses, + promote_unknown_to_global); } /* Copy OTHER to THIS. */ @@ -657,7 +669,8 @@ struct GTY((user)) modref_tree if (ref_node->every_access) return true; FOR_EACH_VEC_SAFE_ELT (ref_node->accesses, k, access_node) - if (access_node->parm_index == MODREF_UNKNOWN_PARM) + if (access_node->parm_index == MODREF_UNKNOWN_PARM + || access_node->parm_index == MODREF_GLOBAL_MEMORY_PARM) return true; } } diff --git a/gcc/ipa-modref.c b/gcc/ipa-modref.c index d6bd9d3..d3590f0 100644 --- a/gcc/ipa-modref.c +++ b/gcc/ipa-modref.c @@ -869,6 +869,66 @@ parm_map_for_ptr (tree op) return parm_map; } +/* Return true if ARG with EAF flags FLAGS can not make any caller's parameter + used (if LOAD is true we check loads, otherwise stores). */ + +static bool +verify_arg (tree arg, int flags, bool load) +{ + if (flags & EAF_UNUSED) + return true; + if (load && (flags & EAF_NO_DIRECT_READ)) + return true; + if (!load + && (flags & (EAF_NO_DIRECT_CLOBBER | EAF_NO_INDIRECT_CLOBBER)) + == (EAF_NO_DIRECT_CLOBBER | EAF_NO_INDIRECT_CLOBBER)) + return true; + if (is_gimple_constant (arg)) + return true; + if (DECL_P (arg) && TREE_READONLY (arg)) + return true; + if (TREE_CODE (arg) == ADDR_EXPR) + { + tree t = get_base_address (TREE_OPERAND (arg, 0)); + if (is_gimple_constant (t)) + return true; + if (DECL_P (t) + && (TREE_READONLY (t) || TREE_CODE (t) == FUNCTION_DECL)) + return true; + } + return false; +} + +/* Return true if STMT may access memory that is pointed to by parameters + of caller and which is not seen as an escape by PTA. + CALLEE_ECF_FLAGS are ECF flags of callee. If LOAD is true then by access + we mean load, otherwise we mean store. */ + +static bool +may_access_nonescaping_parm_p (gcall *call, int callee_ecf_flags, bool load) +{ + int implicit_flags = 0; + + if (ignore_stores_p (current_function_decl, callee_ecf_flags)) + implicit_flags |= ignore_stores_eaf_flags; + if (callee_ecf_flags & ECF_PURE) + implicit_flags |= implicit_pure_eaf_flags; + if (callee_ecf_flags & (ECF_CONST | ECF_NOVOPS)) + implicit_flags |= implicit_const_eaf_flags; + if (gimple_call_chain (call) + && !verify_arg (gimple_call_chain (call), + gimple_call_static_chain_flags (call) | implicit_flags, + load)) + return true; + for (unsigned int i = 0; i < gimple_call_num_args (call); i++) + if (!verify_arg (gimple_call_arg (call, i), + gimple_call_arg_flags (call, i) | implicit_flags, + load)) + return true; + return false; +} + + /* Analyze memory accesses (loads, stores and kills) performed by the function. Set also side_effects, calls_interposable and nondeterminism flags. */ @@ -892,6 +952,8 @@ private: bool record_access_p (tree); bool record_unknown_load (); bool record_unknown_store (); + bool record_global_memory_load (); + bool record_global_memory_store (); bool merge_call_side_effects (gimple *, modref_summary *, cgraph_node *, bool); modref_access_node get_access_for_fnspec (gcall *, attr_fnspec &, @@ -1149,6 +1211,41 @@ modref_access_analysis::record_unknown_store () return changed; } +/* Record unknown load from gloal memory. */ + +bool +modref_access_analysis::record_global_memory_load () +{ + bool changed = false; + modref_access_node a = {0, -1, -1, + 0, MODREF_GLOBAL_MEMORY_PARM, false, 0}; + + if (m_summary && !m_summary->loads->every_base) + changed |= m_summary->loads->insert (current_function_decl, 0, 0, a, false); + if (m_summary_lto && !m_summary_lto->loads->every_base) + changed |= m_summary_lto->loads->insert (current_function_decl, + 0, 0, a, false); + return changed; +} + +/* Record unknown store from gloal memory. */ + +bool +modref_access_analysis::record_global_memory_store () +{ + bool changed = false; + modref_access_node a = {0, -1, -1, + 0, MODREF_GLOBAL_MEMORY_PARM, false, 0}; + + if (m_summary && !m_summary->stores->every_base) + changed |= m_summary->stores->insert (current_function_decl, + 0, 0, a, false); + if (m_summary_lto && !m_summary_lto->stores->every_base) + changed |= m_summary_lto->stores->insert (current_function_decl, + 0, 0, a, false); + return changed; +} + /* Merge side effects of call STMT to function with CALLEE_SUMMARY. Return true if something changed. If IGNORE_STORES is true, do not merge stores. @@ -1160,7 +1257,8 @@ modref_access_analysis::merge_call_side_effects (gimple *stmt, modref_summary *callee_summary, cgraph_node *callee_node, bool record_adjustments) { - int flags = gimple_call_flags (stmt); + gcall *call = as_a (stmt); + int flags = gimple_call_flags (call); /* Nothing to do for non-looping cont functions. */ if ((flags & (ECF_CONST | ECF_NOVOPS)) @@ -1223,10 +1321,10 @@ modref_access_analysis::merge_call_side_effects fprintf (dump_file, " Parm map:"); auto_vec parm_map; - parm_map.safe_grow_cleared (gimple_call_num_args (stmt), true); - for (unsigned i = 0; i < gimple_call_num_args (stmt); i++) + parm_map.safe_grow_cleared (gimple_call_num_args (call), true); + for (unsigned i = 0; i < gimple_call_num_args (call); i++) { - parm_map[i] = parm_map_for_ptr (gimple_call_arg (stmt, i)); + parm_map[i] = parm_map_for_ptr (gimple_call_arg (call, i)); if (dump_file) { fprintf (dump_file, " %i", parm_map[i].parm_index); @@ -1240,9 +1338,9 @@ modref_access_analysis::merge_call_side_effects } modref_parm_map chain_map; - if (gimple_call_chain (stmt)) + if (gimple_call_chain (call)) { - chain_map = parm_map_for_ptr (gimple_call_chain (stmt)); + chain_map = parm_map_for_ptr (gimple_call_chain (call)); if (dump_file) { fprintf (dump_file, "static chain %i", chain_map.parm_index); @@ -1262,7 +1360,7 @@ modref_access_analysis::merge_call_side_effects if (m_always_executed && callee_summary->kills.length () && (!cfun->can_throw_non_call_exceptions - || !stmt_could_throw_p (cfun, stmt))) + || !stmt_could_throw_p (cfun, call))) { /* Watch for self recursive updates. */ auto_vec saved_kills; @@ -1295,14 +1393,18 @@ modref_access_analysis::merge_call_side_effects changed |= m_summary->loads->merge (current_function_decl, callee_summary->loads, &parm_map, &chain_map, - record_adjustments); + record_adjustments, + !may_access_nonescaping_parm_p + (call, flags, true)); /* Merge in stores. */ if (!ignore_stores_p (current_function_decl, flags)) { changed |= m_summary->stores->merge (current_function_decl, callee_summary->stores, &parm_map, &chain_map, - record_adjustments); + record_adjustments, + !may_access_nonescaping_parm_p + (call, flags, false)); if (!m_summary->writes_errno && callee_summary->writes_errno) { @@ -1350,7 +1452,6 @@ modref_access_analysis::get_access_for_fnspec (gcall *call, attr_fnspec &fnspec, } return a; } - /* Apply side effects of call STMT to CUR_SUMMARY using FNSPEC. If IGNORE_STORES is true ignore them. Return false if no useful summary can be produced. */ @@ -1383,14 +1484,34 @@ modref_access_analysis::process_fnspec (gcall *call) if (dump_file && gimple_call_builtin_p (call, BUILT_IN_NORMAL)) fprintf (dump_file, " Builtin with no fnspec: %s\n", IDENTIFIER_POINTER (DECL_NAME (gimple_call_fndecl (call)))); - record_unknown_load (); if (!ignore_stores_p (current_function_decl, flags)) - record_unknown_store (); + { + if (!may_access_nonescaping_parm_p (call, flags, false)) + record_global_memory_store (); + else + record_unknown_store (); + if (!may_access_nonescaping_parm_p (call, flags, true)) + record_global_memory_load (); + else + record_unknown_load (); + } + else + { + if (!may_access_nonescaping_parm_p (call, flags, true)) + record_global_memory_load (); + else + record_unknown_load (); + } return; } /* Process fnspec. */ if (fnspec.global_memory_read_p ()) - record_unknown_load (); + { + if (may_access_nonescaping_parm_p (call, flags, true)) + record_unknown_load (); + else + record_global_memory_load (); + } else { for (unsigned int i = 0; i < gimple_call_num_args (call); i++) @@ -1422,7 +1543,12 @@ modref_access_analysis::process_fnspec (gcall *call) if (ignore_stores_p (current_function_decl, flags)) return; if (fnspec.global_memory_written_p ()) - record_unknown_store (); + { + if (may_access_nonescaping_parm_p (call, flags, false)) + record_unknown_store (); + else + record_global_memory_store (); + } else { for (unsigned int i = 0; i < gimple_call_num_args (call); i++) @@ -1470,6 +1596,12 @@ modref_access_analysis::analyze_call (gcall *stmt) simplified. */ int flags = gimple_call_flags (stmt); + if (dump_file) + { + fprintf (dump_file, " - Analyzing call:"); + print_gimple_stmt (dump_file, stmt, 0); + } + if ((flags & (ECF_CONST | ECF_NOVOPS)) && !(flags & ECF_LOOPING_CONST_OR_PURE)) { diff --git a/gcc/testsuite/gcc.dg/analyzer/data-model-1.c b/gcc/testsuite/gcc.dg/analyzer/data-model-1.c index 908d999..511ed4b 100644 --- a/gcc/testsuite/gcc.dg/analyzer/data-model-1.c +++ b/gcc/testsuite/gcc.dg/analyzer/data-model-1.c @@ -1,4 +1,5 @@ /* { dg-require-effective-target alloca } */ +/* { dg-additional-options "-fno-ipa-modref" } */ #include #include diff --git a/gcc/testsuite/gcc.dg/uninit-38.c b/gcc/testsuite/gcc.dg/uninit-38.c index 0d70bcd..ff2aee6 100644 --- a/gcc/testsuite/gcc.dg/uninit-38.c +++ b/gcc/testsuite/gcc.dg/uninit-38.c @@ -6,7 +6,7 @@ be adjusted. Ditto if -Wuninitialized output changes for some other reason. { dg-do compile { target { { lp64 || ilp32 } || llp64 } } } - { dg-options "-O2 -Wall -ftrack-macro-expansion=0" } */ + { dg-options "-O2 -Wall -ftrack-macro-expansion=0 -fno-ipa-modref" } */ #define CONCAT(x, y) x ## y #define CAT(x, y) CONCAT(x, y) diff --git a/gcc/testsuite/gcc.dg/uninit-pr98578.c b/gcc/testsuite/gcc.dg/uninit-pr98578.c index 98d6117..745328b 100644 --- a/gcc/testsuite/gcc.dg/uninit-pr98578.c +++ b/gcc/testsuite/gcc.dg/uninit-pr98578.c @@ -1,6 +1,6 @@ /* PR middle-end/98578 - ICE warning on uninitialized VLA access { dg-do compile } - { dg-options "-O2 -Wall" } */ + { dg-options "-O2 -Wall -fno-ipa-modref" } */ void* malloc (__SIZE_TYPE__); diff --git a/gcc/tree-ssa-alias.c b/gcc/tree-ssa-alias.c index 88fd782..0112989 100644 --- a/gcc/tree-ssa-alias.c +++ b/gcc/tree-ssa-alias.c @@ -2544,6 +2544,30 @@ refs_output_dependent_p (tree store1, tree store2) return refs_may_alias_p_1 (&r1, &r2, false); } +/* Return ture if REF may access global memory. */ + +bool +ref_may_access_global_memory_p (ao_ref *ref) +{ + if (!ref->ref) + return true; + tree base = ao_ref_base (ref); + if (TREE_CODE (base) == MEM_REF + || TREE_CODE (base) == TARGET_MEM_REF) + { + if (ptr_deref_may_alias_global_p (TREE_OPERAND (base, 0))) + return true; + } + else + { + if (!auto_var_in_fn_p (base, current_function_decl) + || pt_solution_includes (&cfun->gimple_df->escaped, + base)) + return true; + } + return false; +} + /* Returns true if and only if REF may alias any access stored in TT. IF TBAA_P is true, use TBAA oracle. */ @@ -2552,6 +2576,7 @@ modref_may_conflict (const gcall *stmt, modref_tree *tt, ao_ref *ref, bool tbaa_p) { alias_set_type base_set, ref_set; + bool global_memory_ok = false; if (tt->every_base) return true; @@ -2602,6 +2627,17 @@ modref_may_conflict (const gcall *stmt, if (num_tests >= max_tests) return true; + if (access_node.parm_index == MODREF_GLOBAL_MEMORY_PARM) + { + if (global_memory_ok) + continue; + if (ref_may_access_global_memory_p (ref)) + return true; + global_memory_ok = true; + num_tests++; + continue; + } + tree arg = access_node.get_call_arg (stmt); if (!arg) return true; -- cgit v1.1 From 1c613165a55b212c59a83796b20a1d555e096504 Mon Sep 17 00:00:00 2001 From: Harald Anlauf Date: Mon, 13 Dec 2021 20:50:19 +0100 Subject: Fortran: PACK intrinsic should not try to read from zero-sized array libgfortran/ChangeLog: PR libfortran/103634 * intrinsics/pack_generic.c (pack_internal): Handle case when the array argument of PACK has one or more extents of size zero to avoid invalid reads. gcc/testsuite/ChangeLog: PR libfortran/103634 * gfortran.dg/intrinsic_pack_6.f90: New test. --- gcc/testsuite/gfortran.dg/intrinsic_pack_6.f90 | 57 ++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 gcc/testsuite/gfortran.dg/intrinsic_pack_6.f90 (limited to 'gcc') diff --git a/gcc/testsuite/gfortran.dg/intrinsic_pack_6.f90 b/gcc/testsuite/gfortran.dg/intrinsic_pack_6.f90 new file mode 100644 index 0000000..917944d --- /dev/null +++ b/gcc/testsuite/gfortran.dg/intrinsic_pack_6.f90 @@ -0,0 +1,57 @@ +! { dg-do run } +! PR libfortran/103634 - Runtime crash with PACK on zero-sized arrays +! Exercise PACK intrinsic for cases when it calls pack_internal + +program p + implicit none + type t + real :: r(24) = -99. + end type + type(t), allocatable :: new(:), old(:), vec(:) + logical, allocatable :: mask(:) + integer :: n, m +! m = 1 ! works + m = 0 ! failed with SIGSEGV in pack_internal + do m = 0, 2 + print *, m + allocate (old(m), mask(m), vec(m)) + if (m > 0) vec(m)% r(1) = 42 + mask(:) = .true. + n = count (mask) + allocate (new(n)) + + mask(:) = .false. + if (size (pack (old, mask)) /= 0) stop 1 + mask(:) = .true. + if (size (pack (old, mask)) /= m) stop 2 + new(:) = pack (old, mask) ! this used to segfault for m=0 + + mask(:) = .false. + if (size (pack (old, mask, vector=vec)) /= m) stop 3 + new(:) = t() + new(:) = pack (old, mask, vector=vec) ! this used to segfault for m=0 + if (m > 0) then + if ( new( m )% r(1) /= 42) stop 4 + if (any (new(:m-1)% r(1) /= -99)) stop 5 + end if + + if (m > 0) mask(m) = .true. + if (size (pack (old, mask, vector=vec)) /= m) stop 6 + new(:) = t() + new(:) = pack (old, mask, vector=vec) ! this used to segfault for m=0 + if (m > 0) then + if (new(1)% r(1) /= -99) stop 7 + end if + if (m > 1) then + if (new(m)% r(1) /= 42) stop 8 + end if + + if (size (pack (old(:0), mask(:0), vector=vec)) /= m) stop 9 + new(:) = t() + new(:) = pack (old(:0), mask(:0), vector=vec) ! did segfault for m=0 + if (m > 0) then + if (new(m)% r(1) /= 42) stop 10 + end if + deallocate (old, mask, new, vec) + end do +end -- cgit v1.1 From 3736837806fdb26daa51300bee1554bef89db9fe Mon Sep 17 00:00:00 2001 From: Petter Tomner Date: Mon, 29 Nov 2021 20:44:07 +0100 Subject: Add support for global rvalue initialization and constructors This patch adds support for initialization of global variables with rvalues and creating constructors for array, struct and union types which can be used as rvalues. Signed-off-by: 2021-12-14 Petter Tomner gcc/jit/ * jit-common.h: New enum * jit-playback.c : Folding an setting intitial (global_new_decl) : Handle const global generation (new_global) : New flag (global_set_init_rvalue) : New (new_ctor) : New (new_global_initialized) : Flag (as_truth_value) : Fold (new_unary_op) : Fold (new_binary_op) : Fold (new_comparison) : Fold (new_array_access) : Fold (new_dereference) : Fold (get_address) : Fold * jit-playback.h : (global_set_init_rvalue) : New (new_ctor) : New * jit-recording.c : * jit-recording.h : (new_global_init_rvalue) : New (new_ctor) : New (ctor) : New, inherits rvalue (global_init_rvalue) : New, inherits memento (type::is_union) : New * libgccjit++.h : New entrypoints, see C-header * libgccjit.c : See .h * libgccjit.h : New entrypoints (gcc_jit_context_new_array_constructor) : New (gcc_jit_context_new_struct_constructor) : New (gcc_jit_context_new_union_constructor) : New (gcc_jit_global_set_initializer_rvalue) : New (LIBGCCJIT_HAVE_CTORS) : New feuture macro * libgccjit.map : New entrypoints added to ABI 19 * docs/topics/expressions.rst : Updated docs gcc/testsuite/ * jit.dg/all-non-failing-tests.h: Added two tests * jit.dg/test-error-ctor-array-wrong-obj.c: New * jit.dg/test-error-ctor-struct-too-big.c: New * jit.dg/test-error-ctor-struct-wrong-field-obj.c: New * jit.dg/test-error-ctor-struct-wrong-type.c: New * jit.dg/test-error-ctor-struct-wrong-type2.c * jit.dg/test-error-ctor-union-wrong-field-name.c: New * jit.dg/test-error-global-already-init.c: New * jit.dg/test-error-global-common-section.c: New * jit.dg/test-error-global-init-too-small-array.c: New * jit.dg/test-error-global-lvalue-init.c: New * jit.dg/test-error-global-nonconst-init.c: New * jit.dg/test-global-init-rvalue.c: New * jit.dg/test-local-init-rvalue.c: New --- gcc/jit/docs/topics/expressions.rst | 173 +++ gcc/jit/jit-common.h | 9 + gcc/jit/jit-playback.c | 223 ++- gcc/jit/jit-playback.h | 20 +- gcc/jit/jit-recording.c | 471 +++++- gcc/jit/jit-recording.h | 94 ++ gcc/jit/libgccjit++.h | 90 ++ gcc/jit/libgccjit.c | 405 ++++- gcc/jit/libgccjit.h | 153 ++ gcc/jit/libgccjit.map | 7 + gcc/testsuite/jit.dg/all-non-failing-tests.h | 20 + .../jit.dg/test-error-ctor-array-wrong-obj.c | 54 + .../jit.dg/test-error-ctor-struct-too-big.c | 71 + .../test-error-ctor-struct-wrong-field-obj.c | 86 + .../jit.dg/test-error-ctor-struct-wrong-type.c | 76 + .../jit.dg/test-error-ctor-struct-wrong-type2.c | 77 + .../test-error-ctor-union-wrong-field-name.c | 76 + .../jit.dg/test-error-global-already-init.c | 46 + .../jit.dg/test-error-global-common-section.c | 54 + .../test-error-global-init-too-small-array.c | 65 + .../jit.dg/test-error-global-lvalue-init.c | 60 + .../jit.dg/test-error-global-nonconst-init.c | 80 + gcc/testsuite/jit.dg/test-global-init-rvalue.c | 1643 ++++++++++++++++++++ gcc/testsuite/jit.dg/test-local-init-rvalue.c | 707 +++++++++ 24 files changed, 4727 insertions(+), 33 deletions(-) create mode 100644 gcc/testsuite/jit.dg/test-error-ctor-array-wrong-obj.c create mode 100644 gcc/testsuite/jit.dg/test-error-ctor-struct-too-big.c create mode 100644 gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-field-obj.c create mode 100644 gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-type.c create mode 100644 gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-type2.c create mode 100644 gcc/testsuite/jit.dg/test-error-ctor-union-wrong-field-name.c create mode 100644 gcc/testsuite/jit.dg/test-error-global-already-init.c create mode 100644 gcc/testsuite/jit.dg/test-error-global-common-section.c create mode 100644 gcc/testsuite/jit.dg/test-error-global-init-too-small-array.c create mode 100644 gcc/testsuite/jit.dg/test-error-global-lvalue-init.c create mode 100644 gcc/testsuite/jit.dg/test-error-global-nonconst-init.c create mode 100644 gcc/testsuite/jit.dg/test-global-init-rvalue.c create mode 100644 gcc/testsuite/jit.dg/test-local-init-rvalue.c (limited to 'gcc') diff --git a/gcc/jit/docs/topics/expressions.rst b/gcc/jit/docs/topics/expressions.rst index 280e0ea..0a96872 100644 --- a/gcc/jit/docs/topics/expressions.rst +++ b/gcc/jit/docs/topics/expressions.rst @@ -126,6 +126,147 @@ Simple expressions underlying string, so it is valid to pass in a pointer to an on-stack buffer. +Constructor expressions +*********************** + + The following functions make constructors for array, struct and union + types. + + The constructor rvalue can be used for assignment to locals. + It can be used to initialize global variables with + :func:`gcc_jit_global_set_initializer_rvalue`. It can also be used as a + temporary value for function calls and return values, but its address + can't be taken. + + Note that arrays in libgccjit do not collapse to pointers like in + C. I.e. if an array constructor is used as e.g. a return value, the whole + array would be returned by value - array constructors can be assigned to + array variables. + + The constructor can contain nested constructors. + + Note that a string literal rvalue can't be used to construct a char array; + the latter needs one rvalue for each char. + + These entrypoints were added in :ref:`LIBGCCJIT_ABI_19`; you can test for + their presence using: + + .. code-block:: c + #ifdef LIBGCCJIT_HAVE_CTORS + +.. function:: gcc_jit_rvalue *\ + gcc_jit_context_new_array_constructor (gcc_jit_context *ctxt,\ + gcc_jit_location *loc,\ + gcc_jit_type *type,\ + size_t num_values,\ + gcc_jit_rvalue **values) + + Create a constructor for an array as an rvalue. + + Returns NULL on error. ``values`` are copied and + do not have to outlive the context. + + ``type`` specifies what the constructor will build and has to be + an array. + + ``num_values`` specifies the number of elements in ``values`` and + it can't have more elements than the array type. + + Each value in ``values`` sets the corresponding value in the array. + If the array type itself has more elements than ``values``, the + left-over elements will be zeroed. + + Each value in ``values`` need to be the same unqualified type as the + array type's element type. + + If ``num_values`` is 0, the ``values`` parameter will be + ignored and zero initialization will be used. + + This entrypoint was added in :ref:`LIBGCCJIT_ABI_19`; you can test for its + presence using: + + .. code-block:: c + #ifdef LIBGCCJIT_HAVE_CTORS + +.. function:: gcc_jit_rvalue *\ + gcc_jit_context_new_struct_constructor (gcc_jit_context *ctxt,\ + gcc_jit_location *loc,\ + gcc_jit_type *type,\ + size_t num_values,\ + gcc_jit_field **fields,\ + gcc_jit_rvalue **value) + + + Create a constructor for a struct as an rvalue. + + Returns NULL on error. The two parameter arrays are copied and + do not have to outlive the context. + + ``type`` specifies what the constructor will build and has to be + a struct. + + ``num_values`` specifies the number of elements in ``values``. + + ``fields`` need to have the same length as ``values``, or be NULL. + + If ``fields`` is null, the values are applied in definition order. + + Otherwise, each field in ``fields`` specifies which field in the struct to + set to the corresponding value in ``values``. ``fields`` and ``values`` + are paired by index. + + The fields in ``fields`` have to be in definition order, but there + can be gaps. Any field in the struct that is not specified in + ``fields`` will be zeroed. + + The fields in ``fields`` need to be the same objects that were used + to create the struct. + + Each value has to have have the same unqualified type as the field + it is applied to. + + A NULL value element in ``values`` is a shorthand for zero initialization + of the corresponding field. + + If ``num_values`` is 0, the array parameters will be + ignored and zero initialization will be used. + + This entrypoint was added in :ref:`LIBGCCJIT_ABI_19`; you can test for its + presence using: + + .. code-block:: c + #ifdef LIBGCCJIT_HAVE_CTORS + +.. function:: gcc_jit_rvalue *\ + gcc_jit_context_new_union_constructor (gcc_jit_context *ctxt,\ + gcc_jit_location *loc,\ + gcc_jit_type *type,\ + gcc_jit_field *field,\ + gcc_jit_rvalue *value) + + Create a constructor for a union as an rvalue. + + Returns NULL on error. + + ``type`` specifies what the constructor will build and has to be + an union. + + ``field`` specifies which field to set. If it is NULL, the first + field in the union will be set.``field`` need to be the same object + that were used to create the union. + + ``value`` specifies what value to set the corresponding field to. + If ``value`` is NULL, zero initialization will be used. + + Each value has to have have the same unqualified type as the field + it is applied to. + + This entrypoint was added in :ref:`LIBGCCJIT_ABI_19`; you can test for its + presence using: + + .. code-block:: c + #ifdef LIBGCCJIT_HAVE_CTORS + Vector expressions ****************** @@ -661,6 +802,38 @@ Global variables #ifdef LIBGCCJIT_HAVE_gcc_jit_global_set_initializer +.. function:: gcc_jit_lvalue *\ + gcc_jit_global_set_initializer_rvalue (gcc_jit_lvalue *global, + gcc_jit_rvalue *init_value) + + Set the initial value of a global with an rvalue. + + The rvalue needs to be a constant expression, e.g. no function calls. + + The global can't have the ``kind`` :ref:`GCC_JIT_GLOBAL_IMPORTED`. + + As a non-comprehensive example it is OK to do the equivalent of: + + .. code-block:: c + + int foo = 3 * 2; /* rvalue from gcc_jit_context_new_binary_op. */ + int arr[] = {1,2,3,4}; /* rvalue from gcc_jit_context_new_constructor. */ + int *bar = &arr[2] + 1; /* rvalue from nested "get address" of "array access". */ + const int baz = 3; /* rvalue from gcc_jit_context_rvalue_from_int. */ + int boz = baz; /* rvalue from gcc_jit_lvalue_as_rvalue. */ + + Use together with :ref:`gcc_jit_context_new_constructor` to + initialize structs, unions and arrays. + + On success, returns the ``global`` parameter unchanged. Otherwise, ``NULL``. + + This entrypoint was added in :ref:`LIBGCCJIT_ABI_19`; you can test for its + presence using: + + .. code-block:: c + + #ifdef LIBGCCJIT_HAVE_CTORS + Working with pointers, structs and unions ----------------------------------------- diff --git a/gcc/jit/jit-common.h b/gcc/jit/jit-common.h index f88e675..2e723c3 100644 --- a/gcc/jit/jit-common.h +++ b/gcc/jit/jit-common.h @@ -202,6 +202,15 @@ enum inner_bool_option NUM_INNER_BOOL_OPTIONS }; +/* Flags for global variables class. For when the playback of the + global need to know what will happen to it later. */ +enum global_var_flags +{ + GLOBAL_VAR_FLAGS_NONE = 0, + GLOBAL_VAR_FLAGS_WILL_BE_RVAL_INIT = 1, + GLOBAL_VAR_FLAGS_WILL_BE_BLOB_INIT = 2, +}; + } // namespace gcc::jit } // namespace gcc diff --git a/gcc/jit/jit-playback.c b/gcc/jit/jit-playback.c index 783a037..64755b6 100644 --- a/gcc/jit/jit-playback.c +++ b/gcc/jit/jit-playback.c @@ -97,6 +97,43 @@ namespace jit { Playback. **********************************************************************/ +/* Fold a readonly non-volatile variable with an initial constant value, + to that value. + + Otherwise return the argument unchanged. + + This fold is needed for setting a variable's DECL_INITIAL to the value + of a const variable. The c-frontend does this in its own special + fold (), so we lift this part out and do it explicitly where there is a + potential for variables to be used as rvalues. */ +static tree +fold_const_var (tree node) +{ + /* See c_fully_fold_internal in c-fold.c and decl_constant_value_1 + in c-typeck.c. */ + if (VAR_P (node) + && TREE_READONLY (node) + && !TREE_THIS_VOLATILE (node) + && DECL_INITIAL (node) != NULL_TREE + /* "This is invalid if initial value is not constant. + If it has either a function call, a memory reference, + or a variable, then re-evaluating it could give different + results." */ + && TREE_CONSTANT (DECL_INITIAL (node))) + { + tree ret = DECL_INITIAL (node); + /* "Avoid unwanted tree sharing between the initializer and current + function's body where the tree can be modified e.g. by the + gimplifier." */ + if (TREE_STATIC (node)) + ret = unshare_expr (ret); + + return ret; + } + + return node; +} + /* Build a STRING_CST tree for STR, or return NULL if it is NULL. The TREE_TYPE is not initialized. */ @@ -538,15 +575,28 @@ playback::context:: global_new_decl (location *loc, enum gcc_jit_global_kind kind, type *type, - const char *name) + const char *name, + enum global_var_flags flags) { gcc_assert (type); gcc_assert (name); + + tree type_tree = type->as_tree (); + tree inner = build_decl (UNKNOWN_LOCATION, VAR_DECL, get_identifier (name), - type->as_tree ()); + type_tree); + TREE_PUBLIC (inner) = (kind != GCC_JIT_GLOBAL_INTERNAL); - DECL_COMMON (inner) = 1; + + + int will_be_init = flags & (GLOBAL_VAR_FLAGS_WILL_BE_RVAL_INIT | + GLOBAL_VAR_FLAGS_WILL_BE_BLOB_INIT); + + /* A VAR_DECL with DECL_INITIAL will not end up in .common section. */ + if (!will_be_init) + DECL_COMMON (inner) = 1; + switch (kind) { default: @@ -565,6 +615,9 @@ global_new_decl (location *loc, break; } + if (TYPE_READONLY (type_tree)) + TREE_READONLY (inner) = 1; + if (loc) set_tree_location (inner, loc); @@ -589,13 +642,121 @@ playback::context:: new_global (location *loc, enum gcc_jit_global_kind kind, type *type, - const char *name) + const char *name, + enum global_var_flags flags) { - tree inner = global_new_decl (loc, kind, type, name); + tree inner = + global_new_decl (loc, kind, type, name, flags); return global_finalize_lvalue (inner); } +void +playback::context:: +global_set_init_rvalue (lvalue* variable, + rvalue* init) +{ + tree inner = variable->as_tree (); + + /* We need to fold all expressions as much as possible. The code + for a DECL_INITIAL only handles some operations, + etc addition, minus, 'address of'. See output_addressed_constants () + in varasm.c. */ + tree init_tree = init->as_tree (); + tree folded = fold_const_var (init_tree); + + if (!TREE_CONSTANT (folded)) + { + tree name = DECL_NAME (inner); + + if (name != NULL_TREE) + add_error (NULL, + "unable to convert initial value for the global variable %s" + " to a compile-time constant", + IDENTIFIER_POINTER (name)); + else + add_error (NULL, + "unable to convert initial value for global variable" + " to a compile-time constant"); + return; + } + + DECL_INITIAL (inner) = folded; +} + +playback::rvalue * +playback::context:: +new_ctor (location *loc, + type *type, + const auto_vec *fields, + const auto_vec *rvalues) +{ + tree type_tree = type->as_tree (); + + /* Handle empty ctors first. I.e. set everything to 0. */ + if (rvalues->length () == 0) + return new rvalue (this, build_constructor (type_tree, NULL)); + + /* Handle arrays (and return). */ + if (TREE_CODE (type_tree) == ARRAY_TYPE) + { + int n = rvalues->length (); + /* The vec for the constructor node. */ + vec *v = NULL; + vec_alloc (v, n); + + for (int i = 0; i < n; i++) + { + rvalue *rv = (*rvalues)[i]; + /* null rvalues indicate that the element should be zeroed. */ + if (rv) + CONSTRUCTOR_APPEND_ELT (v, + build_int_cst (size_type_node, i), + rv->as_tree ()); + else + CONSTRUCTOR_APPEND_ELT (v, + build_int_cst (size_type_node, i), + build_zero_cst (TREE_TYPE (type_tree))); + } + + tree ctor = build_constructor (type_tree, v); + + if (loc) + set_tree_location (ctor, loc); + + return new rvalue (this, ctor); + } + + /* Handle structs and unions. */ + int n = fields->length (); + + /* The vec for the constructor node. */ + vec *v = NULL; + vec_alloc (v, n); + + /* Iterate over the fields, building initializations. */ + for (int i = 0;i < n; i++) + { + tree field = (*fields)[i]->as_tree (); + rvalue *rv = (*rvalues)[i]; + /* If the value is NULL, it means we should zero the field. */ + if (rv) + CONSTRUCTOR_APPEND_ELT (v, field, rv->as_tree ()); + else + { + tree zero_cst = build_zero_cst (TREE_TYPE (field)); + CONSTRUCTOR_APPEND_ELT (v, field, zero_cst); + } + } + + tree ctor = build_constructor (type_tree, v); + + if (loc) + set_tree_location (ctor, loc); + + return new rvalue (this, build_constructor (type_tree, v)); +} + /* Fill 'constructor_elements' with the memory content of 'initializer'. Each element of the initializer is of the size of type T. In use by new_global_initialized.*/ @@ -629,9 +790,10 @@ new_global_initialized (location *loc, size_t element_size, size_t initializer_num_elem, const void *initializer, - const char *name) + const char *name, + enum global_var_flags flags) { - tree inner = global_new_decl (loc, kind, type, name); + tree inner = global_new_decl (loc, kind, type, name, flags); vec *constructor_elements = NULL; @@ -831,7 +993,8 @@ as_truth_value (tree expr, location *loc) if (loc) set_tree_location (typed_zero, loc); - expr = build2 (NE_EXPR, integer_type_node, expr, typed_zero); + expr = fold_build2_loc (UNKNOWN_LOCATION, + NE_EXPR, integer_type_node, expr, typed_zero); if (loc) set_tree_location (expr, loc); @@ -867,6 +1030,8 @@ new_unary_op (location *loc, gcc_assert (a); tree node = a->as_tree (); + node = fold_const_var (node); + tree inner_result = NULL; switch (op) @@ -898,6 +1063,10 @@ new_unary_op (location *loc, inner_result = build1 (inner_op, result_type->as_tree (), node); + + /* Try to fold. */ + inner_result = fold (inner_result); + if (loc) set_tree_location (inner_result, loc); @@ -922,7 +1091,10 @@ new_binary_op (location *loc, gcc_assert (b); tree node_a = a->as_tree (); + node_a = fold_const_var (node_a); + tree node_b = b->as_tree (); + node_b = fold_const_var (node_b); switch (op) { @@ -992,6 +1164,10 @@ new_binary_op (location *loc, result_type->as_tree (), node_a, node_b); + + /* Try to fold the expression. */ + inner_expr = fold (inner_expr); + if (loc) set_tree_location (inner_expr, loc); @@ -1039,10 +1215,19 @@ new_comparison (location *loc, break; } + tree node_a = a->as_tree (); + node_a = fold_const_var (node_a); + tree node_b = b->as_tree (); + node_b = fold_const_var (node_b); + tree inner_expr = build2 (inner_op, boolean_type_node, - a->as_tree (), - b->as_tree ()); + node_a, + node_b); + + /* Try to fold. */ + inner_expr = fold (inner_expr); + if (loc) set_tree_location (inner_expr, loc); return new rvalue (this, inner_expr); @@ -1142,6 +1327,8 @@ playback::context::build_cast (playback::location *loc, Only some kinds of cast are currently supported here. */ tree t_expr = expr->as_tree (); + t_expr = fold_const_var (t_expr); + tree t_dst_type = type_->as_tree (); tree t_ret = NULL; t_ret = targetm.convert_to_type (t_dst_type, t_expr); @@ -1220,7 +1407,10 @@ new_array_access (location *loc, c-family/c-common.c: pointer_int_sum */ tree t_ptr = ptr->as_tree (); + t_ptr = fold_const_var (t_ptr); tree t_index = index->as_tree (); + t_index = fold_const_var (t_index); + tree t_type_ptr = TREE_TYPE (t_ptr); tree t_type_star_ptr = TREE_TYPE (t_type_ptr); @@ -1228,6 +1418,7 @@ new_array_access (location *loc, { tree t_result = build4 (ARRAY_REF, t_type_star_ptr, t_ptr, t_index, NULL_TREE, NULL_TREE); + t_result = fold (t_result); if (loc) set_tree_location (t_result, loc); return new lvalue (this, t_result); @@ -1237,12 +1428,14 @@ new_array_access (location *loc, /* Convert index to an offset in bytes. */ tree t_sizeof = size_in_bytes (t_type_star_ptr); t_index = fold_build1 (CONVERT_EXPR, sizetype, t_index); - tree t_offset = build2 (MULT_EXPR, sizetype, t_index, t_sizeof); + tree t_offset = fold_build2_loc (UNKNOWN_LOCATION, + MULT_EXPR, sizetype, t_index, t_sizeof); /* Locate (ptr + offset). */ - tree t_address = build2 (POINTER_PLUS_EXPR, t_type_ptr, t_ptr, t_offset); + tree t_address = fold_build2_loc (UNKNOWN_LOCATION, + POINTER_PLUS_EXPR, t_type_ptr, t_ptr, t_offset); - tree t_indirection = build1 (INDIRECT_REF, t_type_star_ptr, t_address); + tree t_indirection = fold_build1 (INDIRECT_REF, t_type_star_ptr, t_address); if (loc) { set_tree_location (t_sizeof, loc); @@ -1290,7 +1483,7 @@ new_dereference (tree ptr, gcc_assert (ptr); tree type = TREE_TYPE (TREE_TYPE(ptr)); - tree datum = build1 (INDIRECT_REF, type, ptr); + tree datum = fold_build1 (INDIRECT_REF, type, ptr); if (loc) set_tree_location (datum, loc); return datum; @@ -1444,7 +1637,7 @@ get_address (location *loc) tree t_lvalue = as_tree (); tree t_thistype = TREE_TYPE (t_lvalue); tree t_ptrtype = build_pointer_type (t_thistype); - tree ptr = build1 (ADDR_EXPR, t_ptrtype, t_lvalue); + tree ptr = fold_build1 (ADDR_EXPR, t_ptrtype, t_lvalue); if (loc) get_context ()->set_tree_location (ptr, loc); if (mark_addressable (loc)) diff --git a/gcc/jit/jit-playback.h b/gcc/jit/jit-playback.h index 21ddffb..6ca492c 100644 --- a/gcc/jit/jit-playback.h +++ b/gcc/jit/jit-playback.h @@ -109,7 +109,8 @@ public: new_global (location *loc, enum gcc_jit_global_kind kind, type *type, - const char *name); + const char *name, + enum global_var_flags flags); lvalue * new_global_initialized (location *loc, @@ -118,7 +119,19 @@ public: size_t element_size, size_t initializer_num_elem, const void *initializer, - const char *name); + const char *name, + enum global_var_flags flags); + + rvalue * + new_ctor (location *log, + type *type, + const auto_vec *fields, + const auto_vec *rvalues); + + + void + global_set_init_rvalue (lvalue* variable, + rvalue* init); template rvalue * @@ -286,7 +299,8 @@ private: global_new_decl (location *loc, enum gcc_jit_global_kind kind, type *type, - const char *name); + const char *name, + enum global_var_flags flags); lvalue * global_finalize_lvalue (tree inner); diff --git a/gcc/jit/jit-recording.c b/gcc/jit/jit-recording.c index b424079..764e7a3 100644 --- a/gcc/jit/jit-recording.c +++ b/gcc/jit/jit-recording.c @@ -1062,6 +1062,18 @@ recording::context::new_global (recording::location *loc, return result; } +void +recording::context::new_global_init_rvalue (lvalue *variable, + rvalue *init) +{ + recording::global_init_rvalue *obj = + new recording::global_init_rvalue (this, variable, init); + record (obj); + + global *gbl = (global *) variable; + gbl->set_rvalue_init (init); /* Needed by the global for write dump. */ +} + /* Create a recording::memento_of_new_string_literal instance and add it to this context's list of mementos. @@ -1094,6 +1106,72 @@ recording::context::new_rvalue_from_vector (location *loc, return result; } +recording::rvalue * +recording::context::new_ctor (recording::location *loc, + recording::type *type, + size_t num_values, + field **fields, + rvalue **values) +{ + recording::ctor *result = new ctor (this, loc, type); + + /* Short cut for zero init. */ + if (!num_values) + { + record (result); + return result; + } + + bool is_struct_or_union = type->is_struct () || type->is_union (); + + /* We need to copy fields and values into result's auto_vec:s. + Both for structs and unions and only values for arrays. */ + if (type->is_array () != NULL) + { + result->m_values.reserve (num_values, false); + + for (size_t i = 0; i < num_values; i++) + result->m_values.quick_push (values[i]); + } + else if (is_struct_or_union && fields) + { + /* ctor values are paired with user specified fields. */ + + result->m_values.reserve (num_values, false); + result->m_fields.reserve (num_values, false); + + for (size_t i = 0; i < num_values; i++) + { + result->m_values.quick_push (values[i]); + result->m_fields.quick_push (fields[i]); + } + } + else if (is_struct_or_union && !fields) + { + /* ctor values are in definition order one by one, + so take the fields from the type object. */ + + result->m_values.reserve (num_values, false); + result->m_fields.reserve (num_values, false); + + compound_type *ct = reinterpret_cast(type); + recording::fields *fields = ct->get_fields (); + + /* The entry point checks that num_values is not greater than + the amount of fields in 'fields'. */ + for (size_t i = 0; i < num_values; i++) + { + result->m_values.quick_push (values[i]); + result->m_fields.quick_push (fields->get_field (i)); + } + } + else + gcc_unreachable (); + + record (result); + return result; +} + /* Create a recording::unary_op instance and add it to this context's list of mementos. @@ -4581,11 +4659,13 @@ recording::global::replay_into (replayer *r) m_initializer_num_bytes / m_type->dereference ()->get_size (), m_initializer, - playback_string (m_name)) - : r->new_global (playback_location (r, m_loc), + playback_string (m_name), + m_flags) + : r->new_global (playback_location (r, m_loc), m_kind, m_type->playback_type (), - playback_string (m_name)); + playback_string (m_name), + m_flags); if (m_tls_model != GCC_JIT_TLS_MODEL_NONE) global->set_tls_model (recording::tls_models[m_tls_model]); @@ -4642,21 +4722,30 @@ recording::global::write_to_dump (dump &d) m_type->get_debug_string (), get_debug_string ()); - if (!m_initializer) + if (!m_initializer && !m_rvalue_init) { d.write (";\n"); - return; } - - d.write ("=\n { "); - const unsigned char *p = (const unsigned char *)m_initializer; - for (size_t i = 0; i < m_initializer_num_bytes; i++) + else if (m_initializer) { - d.write ("0x%x, ", p[i]); - if (i && !(i % 64)) - d.write ("\n "); + d.write ("=\n { "); + const unsigned char *p = (const unsigned char *)m_initializer; + for (size_t i = 0; i < m_initializer_num_bytes; i++) + { + d.write ("0x%x, ", p[i]); + if (i && !(i % 64)) + d.write ("\n "); + } + d.write ("};\n"); } - d.write ("};\n"); + else if (m_rvalue_init) + { + d.write (" = "); + d.write (m_rvalue_init->get_debug_string ()); + d.write (";\n"); + } + + return; } /* A table of enum gcc_jit_global_kind values expressed in string @@ -5123,6 +5212,201 @@ recording::memento_of_new_rvalue_from_vector::write_reproducer (reproducer &r) elements_id); } +void +recording::ctor::visit_children (rvalue_visitor *v) +{ + for (unsigned int i = 0; i < m_values.length (); i++) + v->visit (m_values[i]); +} + +recording::string * +recording::ctor::make_debug_string () +{ + //Make a compound literal-ish + pretty_printer pp; + + pp_string (&pp, "("); + pp_string (&pp, m_type->get_debug_string ()); + pp_string (&pp, ") {"); + + size_t field_n = m_fields.length (); + size_t values_n = m_values.length (); + + if (!field_n && !values_n) + ; + else if (!field_n && values_n) + { + for (size_t i = 0; i < values_n; i++) + { + if (m_values[i]) + pp_string (&pp, m_values[i]->get_debug_string ()); + else + pp_string (&pp, "0"); + if (i + 1 != values_n) + pp_string (&pp, ", "); + } + } + else if (field_n && values_n) + { + for (size_t i = 0; i < values_n; i++) + { + pp_string (&pp, "."); + pp_string (&pp, m_fields[i]->get_debug_string ()); + pp_string (&pp, "="); + if (m_values[i]) + pp_string (&pp, m_values[i]->get_debug_string ()); + else + pp_string (&pp, "0"); + if (i + 1 != values_n) + pp_string (&pp, ", "); + } + } + /* m_fields are never populated with m_values empty. */ + + pp_string (&pp, "}"); + + return new_string (pp_formatted_text (&pp)); +} + +void +recording::ctor::write_reproducer (reproducer &r) +{ + const char *id = r.make_identifier (this, "rvalue"); + type *type = get_type (); + + r.write (" gcc_jit_rvalue *%s;\n", id); + r.write (" {\n"); /* Open scope for locals. */ + + if (type->is_union ()) + { + if (m_values.length () == 0) + r.write (" gcc_jit_rvalue *value = NULL;\n"); + else + r.write (" gcc_jit_rvalue *value = %s;\n", + r.get_identifier (m_values[0])); + + if (m_fields.length () == 0) + r.write (" gcc_jit_field *field = NULL;\n"); + else + r.write (" gcc_jit_field *field = %s;\n", + r.get_identifier (m_fields[0])); + } + else + { + /* Write the array of values. */ + if (m_values.length () == 0) + r.write (" gcc_jit_rvalue **values = NULL;\n"); + else + { + r.write (" gcc_jit_rvalue *values[] = {\n"); + for (size_t i = 0; i < m_values.length (); i++) + r.write (" %s,\n", r.get_identifier (m_values[i])); + r.write (" };\n"); + } + /* Write the array of fields. */ + if (m_fields.length () == 0) + r.write (" gcc_jit_field **fields = NULL;\n"); + else + { + r.write (" gcc_jit_field *fields[] = {\n"); + for (size_t i = 0; i < m_fields.length (); i++) + r.write (" %s,\n", r.get_identifier (m_fields[i])); + r.write (" };\n"); + } + } + if (type->is_array ()) + r.write ( +" %s =\n" +" gcc_jit_context_new_array_constructor (%s,\n" +" %s, /* gcc_jit_location *loc */\n" +" %s, /* gcc_jit_type *type */\n" +" %i, /* int num_values */\n" +" values);\n", + id, + r.get_identifier (get_context ()), + r.get_identifier (m_loc), + r.get_identifier_as_type (get_type ()), + m_values.length ()); + else if (type->is_struct ()) + r.write ( +" %s =\n" +" gcc_jit_context_new_struct_constructor (%s,\n" +" %s, /* loc */\n" +" %s, /* gcc_jit_type *type */\n" +" %i, /* int num_values */\n" +" fields,\n" +" values);\n", + id, + r.get_identifier (get_context ()), + r.get_identifier (m_loc), + r.get_identifier_as_type (get_type ()), + m_values.length ()); + else if (type->is_union ()) + r.write ( +" %s =\n" +" gcc_jit_context_new_union_constructor (%s,\n" +" %s, /* loc */\n" +" %s, /* gcc_jit_type *type */\n" +" field,\n" +" value);\n", + id, + r.get_identifier (get_context ()), + r.get_identifier (m_loc), + r.get_identifier_as_type (get_type ())); + else + gcc_unreachable (); + + r.write (" }\n"); /* Close scope for locals. */ +} + +void +recording::ctor::replay_into (replayer *r) +{ + auto_vec playback_values; + auto_vec playback_fields; + + int n = m_values.length (); + + type *type = get_type (); + + /* Handle arrays, and return. */ + if (type->is_array ()) + { + playback_values.reserve (n, false); + + for (int i = 0; i < n; i++) + { + /* null m_values element indicates zero ctor. */ + playback_values.quick_push (m_values[i] ? + m_values[i]->playback_rvalue () : + NULL); + } + set_playback_obj (r->new_ctor (playback_location (r, m_loc), + get_type ()->playback_type (), + NULL, + &playback_values)); + return; + } + /* ... else handle unions and structs. */ + + playback_values.reserve (n, false); + playback_fields.reserve (n, false); + + for (int i = 0; i < n; i++) + { + /* null m_values element indicates zero ctor. */ + playback_values.quick_push (m_values[i] ? + m_values[i]->playback_rvalue () : + NULL); + playback_fields.quick_push (m_fields[i]->playback_field ()); + } + + set_playback_obj (r->new_ctor (playback_location (r, m_loc), + get_type ()->playback_type (), + &playback_fields, + &playback_values)); +} + /* The implementation of class gcc::jit::recording::unary_op. */ /* Implementation of pure virtual hook recording::memento::replay_into @@ -7087,6 +7371,167 @@ recording::top_level_asm::write_reproducer (reproducer &r) m_asm_stmts->get_debug_string ()); } +void +recording::global_init_rvalue::replay_into (replayer *r) +{ + r->global_set_init_rvalue (m_variable->playback_lvalue (), + m_init->playback_rvalue ()); +} + +void +recording::global_init_rvalue::write_reproducer (reproducer &r) +{ + r.write ( + " gcc_jit_global_set_initializer_rvalue (%s, /* lvalue *global */\n" + " %s);/* rvalue *init */\n", + r.get_identifier (m_variable), + r.get_identifier_as_rvalue (m_init)); +} + +void +recording::global_init_rvalue::write_to_dump (dump &d) +{ + d.write ("%s;\n", get_debug_string ()); +} + +recording::string * +recording::global_init_rvalue::make_debug_string () +{ + return string::from_printf (m_ctxt, "%s = %s", + m_variable->get_debug_string (), + m_init->get_debug_string ()); +} + +enum strip_flags { + STRIP_FLAG_NONE, + STRIP_FLAG_ARR, + STRIP_FLAG_VEC +}; + +/* Strips type down to array, vector or base type (whichever comes first) + + Also saves 'ptr_depth' and sets 'flags' for array or vector types. */ +static +recording::type * +strip_and_count (recording::type *type_to_strip, + int &ptr_depth, + strip_flags &flags) +{ + recording::type *t = type_to_strip; + + while (true) + { + if (!t) + gcc_unreachable (); /* Should only happen on corrupt input. */ + + recording::type *pointed_to_type = t->is_pointer (); + if (pointed_to_type != NULL) + { + ptr_depth++; + t = pointed_to_type; + continue; + } + + recording::type *array_el = t->is_array (); + if (array_el != NULL) + { + flags = STRIP_FLAG_ARR; + break; + } + + recording::type *vec = t->dyn_cast_vector_type (); + if (vec != NULL) + { + flags = STRIP_FLAG_VEC; + break; + } + + /* unqualified () returns 'this' on base types. */ + recording::type *next = t->unqualified (); + if (next == t) + { + break; + } + t = next; + } + + return t; +} + +/* Strip qualifiers and count pointer depth, returning true + if the types' base type and pointer depth are + the same, otherwise false. + + For array and vector types the number of element also + has to match. + + Do not call this directly. Call 'types_kinda_same'. */ +bool +types_kinda_same_internal (recording::type *a, recording::type *b) +{ + int ptr_depth_a = 0; + int ptr_depth_b = 0; + recording::type *base_a; + recording::type *base_b; + + strip_flags flags_a = STRIP_FLAG_NONE; + strip_flags flags_b = STRIP_FLAG_NONE; + + base_a = strip_and_count (a, ptr_depth_a, flags_a); + base_b = strip_and_count (b, ptr_depth_b, flags_b); + + if (ptr_depth_a != ptr_depth_b) + return false; + + if (base_a == base_b) + return true; + + if (flags_a != flags_b) + return false; + + /* If the "base type" is an array or vector we might need to + check deeper. */ + if (flags_a == STRIP_FLAG_ARR) + { + recording::array_type *arr_a = + static_cast (base_a); + recording::array_type *arr_b = + static_cast (base_b); + + if (arr_a->num_elements () != arr_b->num_elements ()) + return false; + + /* is_array returns element type. */ + recording::type *el_a = arr_a->is_array (); + recording::type *el_b = arr_b->is_array (); + + if (el_a == el_b) + return true; + + return types_kinda_same_internal (el_a, el_b); + } + if (flags_a == STRIP_FLAG_VEC) + { + recording::vector_type *arr_a = + static_cast (base_a); + recording::vector_type *arr_b = + static_cast (base_b); + + if (arr_a->get_num_units () != arr_b->get_num_units ()) + return false; + + recording::type *el_a = arr_a->get_element_type (); + recording::type *el_b = arr_b->get_element_type (); + + if (el_a == el_b) + return true; + + return types_kinda_same_internal (el_a, el_b); + } + + return false; +} + } // namespace gcc::jit } // namespace gcc diff --git a/gcc/jit/jit-recording.h b/gcc/jit/jit-recording.h index cedb247..e9760c4 100644 --- a/gcc/jit/jit-recording.h +++ b/gcc/jit/jit-recording.h @@ -149,6 +149,17 @@ public: type *type, const char *name); + rvalue * + new_ctor (location *loc, + type *type, + size_t num_values, + field **fields, + rvalue **values); + + void + new_global_init_rvalue (lvalue *variable, + rvalue *init); + template rvalue * new_rvalue_from_const (type *type, @@ -549,6 +560,7 @@ public: virtual type *is_const () { return NULL; } virtual type *is_array () = 0; virtual struct_ *is_struct () { return NULL; } + virtual bool is_union () const { return false; } virtual bool is_void () const { return false; } virtual vector_type *is_vector () { return NULL; } virtual bool has_known_size () const { return true; } @@ -1016,6 +1028,8 @@ public: void replay_into (replayer *r) FINAL OVERRIDE; + virtual bool is_union () const FINAL OVERRIDE { return true; } + private: string * make_debug_string () FINAL OVERRIDE; void write_reproducer (reproducer &r) FINAL OVERRIDE; @@ -1421,6 +1435,23 @@ public: m_initializer_num_bytes = num_bytes; } + void set_flags (int flag_fields) + { + m_flags = (enum global_var_flags)(m_flags | flag_fields); + } + /* Returns true if any of the flags in the argument is set. */ + bool test_flags_anyof (int flag_fields) const + { + return m_flags & flag_fields; + } + + enum gcc_jit_global_kind get_kind () const + { + return m_kind; + } + + void set_rvalue_init (rvalue *val) { m_rvalue_init = val; } + private: string * make_debug_string () FINAL OVERRIDE { return m_name; } template @@ -1433,8 +1464,10 @@ private: private: enum gcc_jit_global_kind m_kind; + enum global_var_flags m_flags = GLOBAL_VAR_FLAGS_NONE; string *m_name; void *m_initializer; + rvalue *m_rvalue_init = nullptr; /* Only needed for write_dump. */ size_t m_initializer_num_bytes; }; @@ -1519,6 +1552,32 @@ private: auto_vec m_elements; }; +class ctor : public rvalue +{ +public: + ctor (context *ctxt, + location *loc, + type *type) + : rvalue (ctxt, loc, type) + { } + + void replay_into (replayer *r) FINAL OVERRIDE; + + void visit_children (rvalue_visitor *) FINAL OVERRIDE; + +private: + string * make_debug_string () FINAL OVERRIDE; + void write_reproducer (reproducer &r) FINAL OVERRIDE; + enum precedence get_precedence () const FINAL OVERRIDE + { + return PRECEDENCE_PRIMARY; + } + +public: + auto_vec m_fields; + auto_vec m_values; +}; + class unary_op : public rvalue { public: @@ -2362,6 +2421,24 @@ private: string *m_asm_stmts; }; +class global_init_rvalue : public memento +{ +public: + global_init_rvalue (context *ctxt, lvalue *variable, rvalue *init) : + memento (ctxt), m_variable (variable), m_init (init) {}; + + void write_to_dump (dump &d) FINAL OVERRIDE; + +private: + void replay_into (replayer *r) FINAL OVERRIDE; + string * make_debug_string () FINAL OVERRIDE; + void write_reproducer (reproducer &r) FINAL OVERRIDE; + +private: + lvalue *m_variable; + rvalue *m_init; +}; + } // namespace gcc::jit::recording /* Create a recording::memento_of_new_rvalue_from_const instance and add @@ -2381,6 +2458,23 @@ recording::context::new_rvalue_from_const (recording::type *type, return result; } +/* Don't call this directly. Call types_kinda_same. */ +bool +types_kinda_same_internal (recording::type *a, + recording::type *b); + +/* Strip all qualifiers and count pointer depth, returning true + if the types and pointer depth are the same, otherwise false. + + For array and vector types the number of element also + has to match, aswell as the element types themself. */ +static inline bool +types_kinda_same (recording::type *a, recording::type *b) +{ + /* Handle trivial case here, to allow for inlining. */ + return a == b || types_kinda_same_internal (a, b); +} + } // namespace gcc::jit } // namespace gcc diff --git a/gcc/jit/libgccjit++.h b/gcc/jit/libgccjit++.h index 82831ff..2541462 100644 --- a/gcc/jit/libgccjit++.h +++ b/gcc/jit/libgccjit++.h @@ -197,6 +197,20 @@ namespace gccjit rvalue new_rvalue (type vector_type, std::vector elements) const; + rvalue new_struct_ctor (type type_, + std::vector &fields, + std::vector &values, + location loc = location ()); + + rvalue new_array_ctor (type type_, + std::vector &values, + location loc = location ()); + + rvalue new_union_ctor (type type_, + field field, + rvalue value, + location loc = location ()); + /* Generic unary operations... */ rvalue new_unary_op (enum gcc_jit_unary_op op, type result_type, @@ -500,6 +514,7 @@ namespace gccjit rvalue get_address (location loc = location ()); lvalue set_initializer (const void *blob, size_t num_bytes); + lvalue set_initializer_rvalue (rvalue init_value); }; class param : public lvalue @@ -1831,6 +1846,81 @@ lvalue::set_initializer (const void *blob, size_t num_bytes) return *this; } +inline lvalue +lvalue::set_initializer_rvalue (rvalue init_value) +{ + return lvalue (gcc_jit_global_set_initializer_rvalue ( + get_inner_lvalue (), + init_value.get_inner_rvalue ())); +} + +inline rvalue +context::new_struct_ctor (type type_, + std::vector &fields, + std::vector &values, + location loc) +{ + field *pfields = nullptr; + if (fields.size ()) + pfields = &fields[0]; + + gcc_jit_field **fields_arr = + reinterpret_cast (pfields); + + rvalue *pvalues = nullptr; + if (values.size ()) + pvalues = &values[0]; + + gcc_jit_rvalue **values_arr = + reinterpret_cast (pvalues); + + return rvalue ( + gcc_jit_context_new_struct_constructor ( + m_inner_ctxt, + loc.get_inner_location (), + type_.get_inner_type (), + (int)values.size (), + fields_arr, + values_arr)); +} + +inline rvalue +context::new_array_ctor (type type_, + std::vector &values, + location loc) +{ + rvalue *pvalues = nullptr; + if (values.size ()) + pvalues = &values[0]; + + gcc_jit_rvalue **values_arr = + reinterpret_cast (pvalues); + + return rvalue ( + gcc_jit_context_new_array_constructor ( + m_inner_ctxt, + loc.get_inner_location (), + type_.get_inner_type (), + (int)values.size (), + values_arr)); +} + +inline rvalue +context::new_union_ctor (type type_, + field field, + rvalue value, + location loc) +{ + return rvalue ( + gcc_jit_context_new_union_constructor ( + m_inner_ctxt, + loc.get_inner_location (), + type_.get_inner_type (), + field.get_inner_field (), + value.get_inner_rvalue ())); +} + + // class param : public lvalue inline param::param () : lvalue () {} inline param::param (gcc_jit_param *inner) diff --git a/gcc/jit/libgccjit.c b/gcc/jit/libgccjit.c index 59cef61..5cb27a2 100644 --- a/gcc/jit/libgccjit.c +++ b/gcc/jit/libgccjit.c @@ -1386,6 +1386,393 @@ gcc_jit_context_new_global (gcc_jit_context *ctxt, return (gcc_jit_lvalue *)ctxt->new_global (loc, kind, type, name); } +extern gcc_jit_rvalue * +gcc_jit_context_new_struct_constructor (gcc_jit_context *ctxt, + gcc_jit_location *loc, + gcc_jit_type *type, + size_t num_values, + gcc_jit_field **fields, + gcc_jit_rvalue **values) +{ + using namespace gcc::jit::recording; + + RETURN_NULL_IF_FAIL (ctxt, NULL, loc, "NULL context"); + JIT_LOG_FUNC (ctxt->get_logger ()); + RETURN_NULL_IF_FAIL (type, ctxt, loc, "NULL type"); + + RETURN_NULL_IF_FAIL_PRINTF1 (type->is_struct (), + ctxt, loc, + "constructor type is not a struct: %s", + type->get_debug_string ()); + + compound_type *ct = reinterpret_cast(type); + gcc::jit::recording::fields *fields_struct = ct->get_fields (); + size_t n_fields = fields_struct->length (); + + RETURN_NULL_IF_FAIL_PRINTF1 (ct->has_known_size (), + ctxt, loc, + "struct can't be opaque: %s", + type->get_debug_string ()); + RETURN_NULL_IF_FAIL_PRINTF1 (n_fields, + ctxt, loc, + "no fields in struct: %s", + type->get_debug_string ()); + + /* If there is no array input we just short circuit to zero the struct. */ + if (!num_values) + return (gcc_jit_rvalue *)ctxt->new_ctor (loc, type, 0, NULL, NULL); + + RETURN_NULL_IF_FAIL_PRINTF3 (n_fields >= num_values, + ctxt, loc, + "more values in constructor (n=%zu) than fields" + " in target %s (n=%zu)", + num_values, + type->get_debug_string (), + n_fields); + + /* It is OK if fields are null here, indicating definiton order, + but there has to be a values array. */ + RETURN_NULL_IF_FAIL (values, + ctxt, loc, + "'values' NULL with non-zero 'num_values'"); + + size_t idx = 0; /* Runner index for fields in the type object. */ + + for (size_t i = 0; i < num_values; i++) + { + gcc::jit::recording::rvalue *rv = values[i]; + + /* rv kan be NULL, which would indicate zero init for the field. */ + gcc::jit::recording::type *rv_type = rv ? rv->get_type () : nullptr; + + /* If fields are specified we need to check that they are in + definition order. */ + if (fields) + { + gcc::jit::recording::field *f = fields[i]; + + RETURN_NULL_IF_FAIL_PRINTF1 ( + f, + ctxt, loc, + "NULL field in 'fields', at index %zu", i); + + RETURN_NULL_IF_FAIL_PRINTF3 ( + f->get_container () == + static_cast(type), + ctxt, loc, + "field object at index %zu (%s), was not used when creating " + "the %s", + i, + f->get_debug_string (), + type->get_debug_string ()); + + /* Fields in the constructor need to be in struct definition + order, but there can be gaps. */ + size_t j; + for (j = idx; j < n_fields; j++) + { + field *fs = fields_struct->get_field (j); + if (fs == f) + { + idx = j; /* Advance runner index for next iteration. */ + break; + } + } + + RETURN_NULL_IF_FAIL_PRINTF3 ( + j != n_fields, + ctxt, loc, + "field at index %zu in 'fields' is not in definition order " + "(struct: %s) (ctor field: %s)", + i, + type->get_debug_string (), + f->get_debug_string ()); + + /* Check that the specified field has the same type as the + value, unless the value is null (a zero value init). */ + RETURN_NULL_IF_FAIL_PRINTF5 ( + !rv || gcc::jit::types_kinda_same (rv_type, + f->get_type ()), + ctxt, loc, + "value and field not the same unqualified type, at index %zu" + " (%s.%s: %s)(value type: %s)", + i, + type->get_debug_string (), + f->get_debug_string (), + f->get_type ()->get_debug_string (), + rv_type->get_debug_string ()); + } + + /* If no fields are specified, check that the value has the same type + as the field in the definition of the struct. */ + if (rv && !fields) + { + RETURN_NULL_IF_FAIL_PRINTF5 ( + gcc::jit::types_kinda_same (rv_type, + fields_struct-> + get_field (i)->get_type ()), + ctxt, loc, + "value and field not the same unqualified type, at index %zu" + " (%s.%s: %s)(value type: %s)", + i, + type->get_debug_string (), + fields_struct->get_field (i)->get_debug_string (), + fields_struct->get_field (i)->get_type ()->get_debug_string (), + rv_type->get_debug_string ()); + } + + if (rv) + { + RETURN_NULL_IF_FAIL_PRINTF1 ( + !rv_type->is_void (), + ctxt, loc, + "can't construct the void type, at index %zu", i); + } + } + + return (gcc_jit_rvalue *)ctxt->new_ctor ( + loc, + type, + num_values, + reinterpret_cast(fields), + reinterpret_cast(values)); +} + +extern gcc_jit_rvalue * +gcc_jit_context_new_union_constructor (gcc_jit_context *ctxt, + gcc_jit_location *loc, + gcc_jit_type *type, + gcc_jit_field *field, + gcc_jit_rvalue *value) +{ + using namespace gcc::jit::recording; + + RETURN_NULL_IF_FAIL (ctxt, NULL, loc, "NULL context"); + JIT_LOG_FUNC (ctxt->get_logger ()); + RETURN_NULL_IF_FAIL (type, ctxt, loc, "NULL type"); + + RETURN_NULL_IF_FAIL_PRINTF1 (type->is_union (), + ctxt, loc, + "constructor type is not an union: %s", + type->get_debug_string ()); + + compound_type *ct = reinterpret_cast(type); + gcc::jit::recording::fields *fields_union = ct->get_fields (); + size_t n_fields = fields_union->length (); + + RETURN_NULL_IF_FAIL_PRINTF1 (ct->has_known_size (), + ctxt, loc, + "union can't be opaque: %s", + type->get_debug_string ()); + RETURN_NULL_IF_FAIL_PRINTF1 (n_fields, + ctxt, loc, + "no fields in union: %s", + type->get_debug_string ()); + + /* If value is NULL we are just supposed to zero the whole union. */ + if (!value) + return (gcc_jit_rvalue *)ctxt->new_ctor (loc, type, 0, NULL, NULL); + + gcc::jit::recording::type *rv_type = value->get_type (); + + RETURN_NULL_IF_FAIL ( + !rv_type->is_void (), + ctxt, loc, + "can't construct the void type"); + + if (field) + { + RETURN_NULL_IF_FAIL_PRINTF2 ( + field->get_container () == + static_cast(type), + ctxt, loc, + "field object (%s) was not used when creating " + "the type %s", + field->get_debug_string (), + type->get_debug_string ()); + + RETURN_NULL_IF_FAIL_PRINTF4 ( + gcc::jit::types_kinda_same (rv_type, + field->get_type ()), + ctxt, loc, + "value and field are not the same unqualified type" + " (%s.%s: %s)(value type: %s)", + type->get_debug_string (), + field->get_debug_string (), + field->get_type ()->get_debug_string (), + rv_type->get_debug_string ()); + } + /* If no field is specified, check that the value has the same type + as the first field in the definition of the union. */ + if (!field) + RETURN_NULL_IF_FAIL_PRINTF2 ( + gcc::jit::types_kinda_same (rv_type, + fields_union-> + get_field (0)->get_type ()), + ctxt, loc, + "value and first union field not the same unqualified type" + " (field type: %s)(value type: %s)", + fields_union->get_field (0)->get_type ()->get_debug_string (), + rv_type->get_debug_string ()); + + + return (gcc_jit_rvalue *)ctxt->new_ctor ( + loc, + type, + 1, + /* A NULL fields array tells new_ctor to take fields from the type obj. */ + reinterpret_cast(field ? &field : NULL), + reinterpret_cast(&value)); +} + +extern gcc_jit_rvalue * +gcc_jit_context_new_array_constructor (gcc_jit_context *ctxt, + gcc_jit_location *loc, + gcc_jit_type *type, + size_t num_values, + gcc_jit_rvalue **values) +{ + using namespace gcc::jit::recording; + + RETURN_NULL_IF_FAIL (ctxt, NULL, loc, "NULL context"); + JIT_LOG_FUNC (ctxt->get_logger ()); + RETURN_NULL_IF_FAIL (type, ctxt, loc, "NULL type"); + + RETURN_NULL_IF_FAIL (type->is_array () != NULL, + ctxt, loc, + "constructor type not an array"); + + if (!num_values) + values = NULL; + + if (num_values) + { + RETURN_NULL_IF_FAIL ( + values, + ctxt, loc, + "'values' NULL with non-zero 'num_values'"); + + gcc::jit::recording::array_type *arr_type = + reinterpret_cast(type); + size_t n_el = arr_type->num_elements (); + + RETURN_NULL_IF_FAIL_PRINTF2 ( + n_el >= num_values, + ctxt, loc, + "array constructor has more values than the array type's length" + " (array type length: %zu, constructor length: %zu)", + n_el, + num_values); + + /* For arrays, all values need to be the same base type. */ + gcc::jit::recording::type *type0 = NULL; + size_t i = 0; + /* Find first non-null value. */ + for (;i < num_values; i++) + { + if (values[i]) + break; + } + + if (i < num_values) /* All values might be null and i == num_values. */ + type0 = values[i]->get_type (); + + /* If we got a type0, check that all other values have + the same type. */ + for (; i < num_values; i++) + { + if (values[i]) + RETURN_NULL_IF_FAIL_PRINTF3 ( + gcc::jit::types_kinda_same (type0, + values[i]->get_type ()), + ctxt, loc, + "value type at index %zu differ from first value type" + " (first type: %s)(different type: %s)", + i, + type0->get_debug_string (), + values[i]->get_type ()->get_debug_string ()); + } + + /* Compare type0 with the element type specified in the + type of the array. */ + if (type0) + { + gcc::jit::recording::type *el_type = + type->is_array (); + + RETURN_NULL_IF_FAIL_PRINTF2 ( + gcc::jit::types_kinda_same (type0, el_type), + ctxt, loc, + "array element value types differ from types in 'values'" + " (element type: %s)('values' type: %s)", + el_type->get_debug_string (), + type0->get_debug_string ()); + } + } + + return (gcc_jit_rvalue *)ctxt->new_ctor ( + loc, + type, + num_values, + NULL, + reinterpret_cast(values)); +} + +/* Public entrypoint. See description in libgccjit.h. */ + +extern gcc_jit_lvalue * +gcc_jit_global_set_initializer_rvalue (gcc_jit_lvalue *global, + gcc_jit_rvalue *init_rvalue) +{ + RETURN_NULL_IF_FAIL (global, NULL, NULL,"NULL global"); + + gcc::jit::recording::context *ctxt = global->get_context (); + RETURN_NULL_IF_FAIL (ctxt, NULL, NULL,"NULL context"); + JIT_LOG_FUNC (ctxt->get_logger ()); + RETURN_NULL_IF_FAIL (init_rvalue, ctxt, NULL,"NULL init_rvalue"); + + RETURN_NULL_IF_FAIL_PRINTF1 (global->is_global (), + ctxt, NULL, + "lvalue \"%s\" not a global", + global->get_debug_string ()); + + gcc::jit::recording::global *gbl = + reinterpret_cast (global); + + RETURN_NULL_IF_FAIL_PRINTF1 (gbl->get_kind () != + GCC_JIT_GLOBAL_IMPORTED, + ctxt, NULL, + "can't initialize \"%s\", it is imported", + global->get_debug_string ()); + + RETURN_NULL_IF_FAIL_PRINTF4 (gcc::jit::types_kinda_same ( + global->get_type (), + init_rvalue->get_type ()), + ctxt, NULL, + "mismatching types:" + " initializing %s (type: %s) with %s (type: %s)", + global->get_debug_string (), + global->get_type ()->get_debug_string (), + init_rvalue->get_debug_string (), + init_rvalue->get_type ()->get_debug_string ()); + + /* Check that there are no initializers set for the global yet. */ + RETURN_NULL_IF_FAIL_PRINTF1 (!gbl->test_flags_anyof ( + gcc::jit::GLOBAL_VAR_FLAGS_WILL_BE_RVAL_INIT | + gcc::jit::GLOBAL_VAR_FLAGS_WILL_BE_BLOB_INIT), + ctxt, NULL, + "global variable already initialized: %s", + global->get_debug_string ()); + + /* The global need to know during playback that it will be + initialized. */ + gbl->set_flags (gcc::jit::GLOBAL_VAR_FLAGS_WILL_BE_RVAL_INIT); + + ctxt->new_global_init_rvalue (global, init_rvalue); + + return global; +} + /* Public entrypoint. See description in libgccjit.h. After error-checking, the real work is done by the @@ -1419,8 +1806,22 @@ gcc_jit_global_set_initializer (gcc_jit_lvalue *global, " global \"%s\" has size %zu whereas initializer has size %zu", global->get_debug_string (), lvalue_size, num_bytes); - reinterpret_cast (global) - ->set_initializer (blob, num_bytes); + /* Check that the rvalue initializer is not set for this global. + Note that we do not check if this blob type initializer is + already set, since that check was not present when the entrypoint + was initially written. */ + gcc::jit::recording::global *gbl = + reinterpret_cast (global); + RETURN_NULL_IF_FAIL_PRINTF1 (!gbl->test_flags_anyof ( + gcc::jit::GLOBAL_VAR_FLAGS_WILL_BE_RVAL_INIT), + NULL, NULL, + "global variable already initialized: %s", + global->get_debug_string ()); + + gbl->set_initializer (blob, num_bytes); + /* The global need to know during playback that it will be + initialized. */ + gbl->set_flags (gcc::jit::GLOBAL_VAR_FLAGS_WILL_BE_BLOB_INIT); return global; } diff --git a/gcc/jit/libgccjit.h b/gcc/jit/libgccjit.h index 024c8d7..80a915f 100644 --- a/gcc/jit/libgccjit.h +++ b/gcc/jit/libgccjit.h @@ -822,6 +822,159 @@ gcc_jit_context_new_global (gcc_jit_context *ctxt, gcc_jit_type *type, const char *name); +#define LIBGCCJIT_HAVE_CTORS + +/* Create a constructor for a struct as an rvalue. + + Returns NULL on error. The two parameter arrays are copied and + do not have to outlive the context. + + `type` specifies what the constructor will build and has to be + a struct. + + `num_values` specifies the number of elements in `values`. + + `fields` need to have the same length as `values`, or be NULL. + + If `fields` is null, the values are applied in definition order. + + Otherwise, each field in `fields` specifies which field in the struct to + set to the corresponding value in `values`. `fields` and `values` + are paired by index. + + Each value has to have have the same unqualified type as the field + it is applied to. + + A NULL value element in `values` is a shorthand for zero initialization + of the corresponding field. + + The fields in `fields` have to be in definition order, but there + can be gaps. Any field in the struct that is not specified in + `fields` will be zeroed. + + The fields in `fields` need to be the same objects that were used + to create the struct. + + If `num_values` is 0, the array parameters will be + ignored and zero initialization will be used. + + The constructor rvalue can be used for assignment to locals. + It can be used to initialize global variables with + gcc_jit_global_set_initializer_rvalue. It can also be used as a + temporary value for function calls and return values. + + The constructor can contain nested constructors. + + This entrypoint was added in LIBGCCJIT_ABI_19; you can test for its + presence using: + #ifdef LIBGCCJIT_HAVE_CTORS +*/ + +extern gcc_jit_rvalue * +gcc_jit_context_new_struct_constructor (gcc_jit_context *ctxt, + gcc_jit_location *loc, + gcc_jit_type *type, + size_t num_values, + gcc_jit_field **fields, + gcc_jit_rvalue **values); + +/* Create a constructor for a union as an rvalue. + + Returns NULL on error. + + `type` specifies what the constructor will build and has to be + an union. + + `field` specifies which field to set. If it is NULL, the first + field in the union will be set. `field` need to be the same + object that were used to create the union. + + `value` specifies what value to set the corresponding field to. + If `value` is NULL, zero initialization will be used. + + Each value has to have have the same unqualified type as the field + it is applied to. + + `field` need to be the same objects that were used + to create the union. + + The constructor rvalue can be used for assignment to locals. + It can be used to initialize global variables with + gcc_jit_global_set_initializer_rvalue. It can also be used as a + temporary value for function calls and return values. + + The constructor can contain nested constructors. + + This entrypoint was added in LIBGCCJIT_ABI_19; you can test for its + presence using: + #ifdef LIBGCCJIT_HAVE_CTORS +*/ + +extern gcc_jit_rvalue * +gcc_jit_context_new_union_constructor (gcc_jit_context *ctxt, + gcc_jit_location *loc, + gcc_jit_type *type, + gcc_jit_field *field, + gcc_jit_rvalue *value); + +/* Create a constructor for an array as an rvalue. + + Returns NULL on error. `values` are copied and + do not have to outlive the context. + + `type` specifies what the constructor will build and has to be + an array. + + `num_values` specifies the number of elements in `values` and + it can't have more elements than the array type. + + Each value in `values` sets the corresponding value in the array. + If the array type itself has more elements than `values`, the + left-over elements will be zeroed. + + Each value in `values` need to be the same unqualified type as the + array type's element type. + + If `num_values` is 0, the `values` parameter will be + ignored and zero initialization will be used. + + Note that a string literal rvalue can't be used to construct a char + array. It needs one rvalue for each char. + + This entrypoint was added in LIBGCCJIT_ABI_19; you can test for its + presence using: + #ifdef LIBGCCJIT_HAVE_CTORS +*/ + +extern gcc_jit_rvalue * +gcc_jit_context_new_array_constructor (gcc_jit_context *ctxt, + gcc_jit_location *loc, + gcc_jit_type *type, + size_t num_values, + gcc_jit_rvalue **values); + +/* Set the initial value of a global of any type with an rvalue. + + The rvalue needs to be a constant expression, e.g. no function calls. + + The global can't have the 'kind' GCC_JIT_GLOBAL_IMPORTED. + + Use together with gcc_jit_context_new_constructor () to + initialize structs, unions and arrays. + + On success, returns the 'global' parameter unchanged. Otherwise, NULL. + + 'values' is copied and does not have to outlive the context. + + This entrypoint was added in LIBGCCJIT_ABI_19; you can test for its + presence using: + #ifdef LIBGCCJIT_HAVE_CTORS +*/ + +extern gcc_jit_lvalue * +gcc_jit_global_set_initializer_rvalue (gcc_jit_lvalue *global, + gcc_jit_rvalue *init_value); + #define LIBGCCJIT_HAVE_gcc_jit_global_set_initializer /* Set an initial value for a global, which must be an array of diff --git a/gcc/jit/libgccjit.map b/gcc/jit/libgccjit.map index b176711..c0135e0 100644 --- a/gcc/jit/libgccjit.map +++ b/gcc/jit/libgccjit.map @@ -236,3 +236,10 @@ LIBGCCJIT_ABI_18 { global: gcc_jit_lvalue_set_link_section; } LIBGCCJIT_ABI_17; + +LIBGCCJIT_ABI_19 { + gcc_jit_context_new_array_constructor; + gcc_jit_context_new_struct_constructor; + gcc_jit_context_new_union_constructor; + gcc_jit_global_set_initializer_rvalue; +} LIBGCCJIT_ABI_18; diff --git a/gcc/testsuite/jit.dg/all-non-failing-tests.h b/gcc/testsuite/jit.dg/all-non-failing-tests.h index 3e8ccbc..29afe06 100644 --- a/gcc/testsuite/jit.dg/all-non-failing-tests.h +++ b/gcc/testsuite/jit.dg/all-non-failing-tests.h @@ -181,6 +181,13 @@ #undef create_code #undef verify_code +/* test-global-init-rvalue.c */ +#define create_code create_code_global_init_rvalue +#define verify_code verify_code_global_init_rvalue +#include "test-global-init-rvalue.c" +#undef create_code +#undef verify_code + /* test-global-set-initializer.c */ #define create_code create_code_global_set_initializer #define verify_code verify_code_global_set_initializer @@ -219,6 +226,13 @@ #undef create_code #undef verify_code +/* test-local-init-rvalue.c */ +#define create_code create_code_local_init_rvalue +#define verify_code verify_code_local_init_rvalue +#include "test-local-init-rvalue.c" +#undef create_code +#undef verify_code + /* test-long-names.c */ #define create_code create_code_long_names #define verify_code verify_code_long_names @@ -431,12 +445,18 @@ const struct testcase testcases[] = { {"builtin-types", create_code_builtin_types, verify_code_builtin_types}, + {"global_rvalue_init", + create_code_global_init_rvalue, + verify_code_global_init_rvalue}, {"hello_world", create_code_hello_world, verify_code_hello_world}, {"linked_list", create_code_linked_list, verify_code_linked_list}, + {"local_rvalue_init", + create_code_local_init_rvalue, + verify_code_local_init_rvalue}, {"long_names", create_code_long_names, verify_code_long_names}, diff --git a/gcc/testsuite/jit.dg/test-error-ctor-array-wrong-obj.c b/gcc/testsuite/jit.dg/test-error-ctor-array-wrong-obj.c new file mode 100644 index 0000000..6b54b85 --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-ctor-array-wrong-obj.c @@ -0,0 +1,54 @@ +/* + + Test that the proper error is triggered when we build a ctor + for an array type, but has the type wrong on an element. + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + gcc_jit_type *float_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_FLOAT); + + gcc_jit_type *arr_type = + gcc_jit_context_new_array_type (ctxt, 0, int_type, 10); + + gcc_jit_rvalue *frv = gcc_jit_context_new_rvalue_from_double (ctxt, + float_type, + 12); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor + (ctxt, 0, + arr_type, + 1, + &frv); + + CHECK_VALUE (ctor, NULL); +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "gcc_jit_context_new_array_constructor: array element " + "value types differ from types in 'values' (element " + "type: int)('values' type: float)"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "gcc_jit_context_new_array_constructor: array element " + "value types differ from types in 'values' (element " + "type: int)('values' type: float)"); +} diff --git a/gcc/testsuite/jit.dg/test-error-ctor-struct-too-big.c b/gcc/testsuite/jit.dg/test-error-ctor-struct-too-big.c new file mode 100644 index 0000000..6bc2045 --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-ctor-struct-too-big.c @@ -0,0 +1,71 @@ +/* + + Test that the proper error is triggered when we build a ctor + for an struct type, but have too many fields and values. + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + + gcc_jit_field *b1 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "a"); + gcc_jit_field *b2 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "b"); + gcc_jit_field *b3 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "c"); + gcc_jit_field *fields_b[] = {b1, b2, b3}; + + gcc_jit_type *struct_bar_type = + gcc_jit_struct_as_type ( + gcc_jit_context_new_struct_type (ctxt, + 0, + "bar", + 3, + fields_b)); + + gcc_jit_field *fields_ctor[] = {b1, b2, b3, b3}; + gcc_jit_rvalue *values[] = {0,0,0,0}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_bar_type, + 4, + fields_ctor, + values); + + CHECK_VALUE (ctor, NULL); +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "gcc_jit_context_new_struct_constructor: more values in " + "constructor (n=4) than fields in target struct " + "bar (n=3)"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "gcc_jit_context_new_struct_constructor: more values in " + "constructor (n=4) than fields in target struct " + "bar (n=3)"); +} diff --git a/gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-field-obj.c b/gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-field-obj.c new file mode 100644 index 0000000..bc191e1 --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-field-obj.c @@ -0,0 +1,86 @@ +/* + + Test that the proper error is triggered when we build a ctor + for an struct type, but try to use a field object that was not + used to create the struct type. + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + + gcc_jit_field *b1 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "a"); + gcc_jit_field *b2 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "b"); + gcc_jit_field *b3 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "c"); + gcc_jit_field *b4 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "d"); + gcc_jit_field *b5 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "d"); + gcc_jit_field *fields_b[] = {b1, b2, b3, b4, b5}; + + gcc_jit_type *struct_bar_type = + gcc_jit_struct_as_type ( + gcc_jit_context_new_struct_type (ctxt, + 0, + "bar", + 5, + fields_b)); + + + gcc_jit_field *b44 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "c"); + + gcc_jit_field *fields_ctor[] = {b1, b2, b44, b5}; + gcc_jit_rvalue *values[] = {0,0,0,0}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_bar_type, + 4, + fields_ctor, + values); + + CHECK_VALUE (ctor, NULL); +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "gcc_jit_context_new_struct_constructor: field object " + "at index 2 (c), was not used when creating the " + "struct bar"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "gcc_jit_context_new_struct_constructor: field object " + "at index 2 (c), was not used when creating the " + "struct bar"); +} diff --git a/gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-type.c b/gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-type.c new file mode 100644 index 0000000..364610b --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-type.c @@ -0,0 +1,76 @@ +/* + + Test that the proper error is triggered when we build a ctor + for an struct type, but has the type wrong on a field. + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + gcc_jit_type *float_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_FLOAT); + + gcc_jit_field *b1 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "a"); + gcc_jit_field *b2 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "b"); + gcc_jit_field *b3 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "c"); + gcc_jit_field *fields_b[] = {b1, b2, b3}; + + gcc_jit_type *struct_bar_type = + gcc_jit_struct_as_type ( + gcc_jit_context_new_struct_type (ctxt, + 0, + "bar", + 3, + fields_b)); + gcc_jit_rvalue *frv = gcc_jit_context_new_rvalue_from_double (ctxt, + float_type, + 12); + + gcc_jit_field *fields_ctor[] = {b2}; + gcc_jit_rvalue *values[] = {frv}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_bar_type, + 1, + fields_ctor, + values); + + CHECK_VALUE (ctor, NULL); +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "gcc_jit_context_new_struct_constructor: value and " + "field not the same unqualified type, at index 0 " + "(struct bar.b: int)(value type: float)"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "gcc_jit_context_new_struct_constructor: value and " + "field not the same unqualified type, at index 0 " + "(struct bar.b: int)(value type: float)"); +} diff --git a/gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-type2.c b/gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-type2.c new file mode 100644 index 0000000..c2309de --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-ctor-struct-wrong-type2.c @@ -0,0 +1,77 @@ +/* + + Test that the proper error is triggered when we build a ctor + for an struct type, but has the type wrong on a field. + + Like test-error-ctor-struct-wrong-type.c, but with implicit fields. + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + gcc_jit_type *float_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_FLOAT); + + gcc_jit_field *b1 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "a"); + gcc_jit_field *b2 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "b"); + gcc_jit_field *b3 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "c"); + gcc_jit_field *fields_b[] = {b1, b2, b3}; + + gcc_jit_type *struct_bar_type = + gcc_jit_struct_as_type ( + gcc_jit_context_new_struct_type (ctxt, + 0, + "bar", + 3, + fields_b)); + gcc_jit_rvalue *frv = gcc_jit_context_new_rvalue_from_double (ctxt, + float_type, + 12); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_bar_type, + 1, + 0, + &frv); + + CHECK_VALUE (ctor, NULL); +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "gcc_jit_context_new_struct_constructor: value and " + "field not " + "the same unqualified type, " + "at index 0 (struct bar.a: int)(value type: float)"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "gcc_jit_context_new_struct_constructor: value and " + "field not " + "the same unqualified type, " + "at index 0 (struct bar.a: int)(value type: float)"); +} diff --git a/gcc/testsuite/jit.dg/test-error-ctor-union-wrong-field-name.c b/gcc/testsuite/jit.dg/test-error-ctor-union-wrong-field-name.c new file mode 100644 index 0000000..2bf8ee4 --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-ctor-union-wrong-field-name.c @@ -0,0 +1,76 @@ +/* + + Test that the proper error is triggered when we build a ctor + for an union type, but don't provide a correct field. + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + gcc_jit_type *float_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_FLOAT); + gcc_jit_type *double_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_DOUBLE); + + gcc_jit_field *b1 = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "a"); + gcc_jit_field *b2 = gcc_jit_context_new_field (ctxt, + 0, + float_type, + "b"); + gcc_jit_field *b3 = gcc_jit_context_new_field (ctxt, + 0, + double_type, + "c"); + gcc_jit_field *fields_b[] = {b1, b2, b3}; + + gcc_jit_type *union_bar_type = + gcc_jit_context_new_union_type (ctxt, + 0, + "bar", + 3, + fields_b); + + gcc_jit_field *b33 = gcc_jit_context_new_field (ctxt, + 0, + double_type, + "c"); + + gcc_jit_rvalue *val = + gcc_jit_context_new_rvalue_from_double (ctxt, double_type, 1); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_union_constructor + (ctxt, 0, + union_bar_type, + b33, + val); + + CHECK_VALUE (ctor, NULL); +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "gcc_jit_context_new_union_constructor: field object (c)" + " was not used when creating the type union bar"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "gcc_jit_context_new_union_constructor: field object (c)" + " was not used when creating the type union bar"); +} diff --git a/gcc/testsuite/jit.dg/test-error-global-already-init.c b/gcc/testsuite/jit.dg/test-error-global-already-init.c new file mode 100644 index 0000000..ecead87 --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-global-already-init.c @@ -0,0 +1,46 @@ +/* + + Test that we can't set the initializer on a global twice. + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, GCC_JIT_TYPE_INT); + + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_lvalueinit_int_0"); + + gcc_jit_global_set_initializer_rvalue ( + bar, + gcc_jit_context_new_rvalue_from_int (ctxt, int_type, 1)); + gcc_jit_global_set_initializer_rvalue ( + bar, + gcc_jit_context_new_rvalue_from_int (ctxt, int_type, 1)); +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "gcc_jit_global_set_initializer_rvalue: global variable " + "already initialized: global_lvalueinit_int_0"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "gcc_jit_global_set_initializer_rvalue: global variable " + "already initialized: global_lvalueinit_int_0"); +} diff --git a/gcc/testsuite/jit.dg/test-error-global-common-section.c b/gcc/testsuite/jit.dg/test-error-global-common-section.c new file mode 100644 index 0000000..2f99454 --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-global-common-section.c @@ -0,0 +1,54 @@ +/* + + Test that the proper error is triggered when we initialize + a global with a global that has no DECL_INITIAL (and is marked + DECL_COMMON(NODE) = 1). + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + + /* const int foo; + int bar = foo; + */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_type_get_const (int_type), + "global_const_int_0"); + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_lvalueinit_int_0"); + gcc_jit_global_set_initializer_rvalue (bar, + gcc_jit_lvalue_as_rvalue (foo)); +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "unable to convert initial value for the global " + "variable global_lvalueinit_int_0 to a compile-time" + " constant"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "unable to convert initial value for the global " + "variable global_lvalueinit_int_0 to a compile-time" + " constant"); +} diff --git a/gcc/testsuite/jit.dg/test-error-global-init-too-small-array.c b/gcc/testsuite/jit.dg/test-error-global-init-too-small-array.c new file mode 100644 index 0000000..2a3db7a --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-global-init-too-small-array.c @@ -0,0 +1,65 @@ +/* + + Test that the proper error is triggered when we initialize + a global array with a ctor with too many values. + + Using gcc_jit_global_set_initializer_rvalue() + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ /* float foo[1] = {1,2}; */ + + gcc_jit_type *float_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_FLOAT); + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + float_type, + 1); + gcc_jit_rvalue *rval_1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 1); + gcc_jit_rvalue *rval_2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 2); + + gcc_jit_rvalue *values[] = {rval_1, rval_2}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 2, + values); + if (!ctor) + return; + + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_floatarr_12"); + gcc_jit_global_set_initializer_rvalue (foo, ctor); +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "gcc_jit_context_new_array_constructor: array " + "constructor has more values than the array type's " + "length (array type length: 1, constructor length: 2)"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "gcc_jit_context_new_array_constructor: array " + "constructor has more values than the array type's " + "length (array type length: 1, constructor length: 2)"); +} diff --git a/gcc/testsuite/jit.dg/test-error-global-lvalue-init.c b/gcc/testsuite/jit.dg/test-error-global-lvalue-init.c new file mode 100644 index 0000000..65aa8a8 --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-global-lvalue-init.c @@ -0,0 +1,60 @@ +/* + + Test that the proper error is triggered when we initialize + a global with another non-const global's rvalue. + + Using gcc_jit_global_set_initializer_rvalue() + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + + gcc_jit_lvalue *foo; + { /* int bar; */ + foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_lvalueinit_int1"); + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_global_set_initializer_rvalue (foo, + rval); + } + { /* int foo = bar; */ + + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_lvalueinit_int2"); + gcc_jit_global_set_initializer_rvalue (bar, + gcc_jit_lvalue_as_rvalue (foo)); + } +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "unable to convert initial value for the global variable" + " global_lvalueinit_int2 to a compile-time constant"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "unable to convert initial value for the global variable" + " global_lvalueinit_int2 to a compile-time constant"); +} diff --git a/gcc/testsuite/jit.dg/test-error-global-nonconst-init.c b/gcc/testsuite/jit.dg/test-error-global-nonconst-init.c new file mode 100644 index 0000000..9dffe06 --- /dev/null +++ b/gcc/testsuite/jit.dg/test-error-global-nonconst-init.c @@ -0,0 +1,80 @@ +/* + + Test that the proper error is triggered when we initialize + a global with a function call. + + Using gcc_jit_global_set_initializer_rvalue() + +*/ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + + gcc_jit_function *fn_int_3; + { /* int foo () { int local = 3; return local;} */ + fn_int_3 = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + int_type, + "fn_int_3", + 0, + 0, + 0); + gcc_jit_block *block = gcc_jit_function_new_block (fn_int_3, "start"); + gcc_jit_lvalue *local = gcc_jit_function_new_local (fn_int_3, + 0, + int_type, + "local"); + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + + gcc_jit_block_add_assignment (block, 0, local, rval); + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_as_rvalue(local)); + + } + + { /* int bar = foo(); */ + gcc_jit_rvalue *rval = + gcc_jit_context_new_call (ctxt, + 0, + fn_int_3, + 0,0); + + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_nonconst_int"); + gcc_jit_global_set_initializer_rvalue (foo, + rval); + } +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + /* Ensure that the bad API usage prevents the API giving a bogus + result back. */ + CHECK_VALUE (result, NULL); + + /* Verify that the correct error message was emitted. */ + CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt), + "unable to convert initial value for the global variable" + " global_nonconst_int to a compile-time constant"); + CHECK_STRING_VALUE (gcc_jit_context_get_last_error (ctxt), + "unable to convert initial value for the global variable" + " global_nonconst_int to a compile-time constant"); +} diff --git a/gcc/testsuite/jit.dg/test-global-init-rvalue.c b/gcc/testsuite/jit.dg/test-global-init-rvalue.c new file mode 100644 index 0000000..4866462 --- /dev/null +++ b/gcc/testsuite/jit.dg/test-global-init-rvalue.c @@ -0,0 +1,1643 @@ +/* This testcase checks that gcc_jit_global_set_initializer_rvalue() works + with rvalues, especially with gcc_jit_context_new_*_constructor() for + struct, unions and arrays. */ + +#include +#include + +#include "libgccjit.h" +#include "harness.h" + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + gcc_jit_type *short_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_SHORT); + gcc_jit_type *pint_type = gcc_jit_type_get_pointer (int_type); + gcc_jit_type *double_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_DOUBLE); + gcc_jit_type *float_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_FLOAT); + gcc_jit_type *bool_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_BOOL); + gcc_jit_type *char_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_CHAR); + gcc_jit_type *cpchar_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_CONST_CHAR_PTR); + gcc_jit_type *size_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_SIZE_T); + + /* Make a struct: struct fi { float f; int i;} */ + gcc_jit_field *fi_f = gcc_jit_context_new_field (ctxt, + 0, + float_type, + "f"); + gcc_jit_field *fi_i = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "i"); + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_type *struct_fi_type = + gcc_jit_struct_as_type ( + gcc_jit_context_new_struct_type (ctxt, + 0, + "fi", + 2, + fields)); + + /* Make a struct: + + struct bar { + int ii; + struct fi fi; + float ff; + } + */ + gcc_jit_field *bar_ff = gcc_jit_context_new_field (ctxt, + 0, + float_type, + "ff"); + gcc_jit_field *bar_ii = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "ii"); + gcc_jit_field *bar_fi = gcc_jit_context_new_field (ctxt, + 0, + struct_fi_type, + "fi"); + gcc_jit_field *fields2[] = {bar_ff, bar_fi, bar_ii}; + + gcc_jit_type *struct_bar_type = + gcc_jit_struct_as_type ( + gcc_jit_context_new_struct_type (ctxt, + 0, + "bar", + 3, + fields2)); + + /* Make an union: + + union ubar { + float ff; + int ii; + }; + */ + gcc_jit_field *ubar_ff = gcc_jit_context_new_field (ctxt, + 0, + float_type, + "ff"); + gcc_jit_field *ubar_ii = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "ii"); + gcc_jit_field *fields3[] = {ubar_ff, ubar_ii}; + + gcc_jit_type *ubar = gcc_jit_context_new_union_type (ctxt, + 0, + "ubar", + 2, + fields3); + + { /* struct bar bar = {.ff=1, .fi={.f=2, .i=3}, .ii=4}; + I.e. nested ctors and with fields specified + */ + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + struct_bar_type, + "global_struct_bar_1234_1"); + + gcc_jit_rvalue *fval = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 2); + gcc_jit_rvalue *ival = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + + gcc_jit_rvalue *vals[] = { fval, ival}; + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + fields, + vals); + + ival = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 4); + fval = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 1); + + gcc_jit_rvalue *vals2[] = {fval, ctor, ival}; + gcc_jit_field *fields2[] = {bar_ff, bar_fi, bar_ii}; + + gcc_jit_rvalue *ctor_bar = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_bar_type, + 3, + fields2, + vals2); + + gcc_jit_global_set_initializer_rvalue (bar, ctor_bar); + } + { /* struct bar bar = {1, {2, 3}, 4}; + I.e. nested ctors and fields implicit in definition order (fields=NULL) + */ + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + struct_bar_type, + "global_struct_bar_1234_2"); + + gcc_jit_rvalue *fval = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 2); + gcc_jit_rvalue *ival = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + + gcc_jit_rvalue *vals[] = { fval, ival}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + 0, + vals); + + ival = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 4); + fval = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 1); + + gcc_jit_rvalue *vals2[] = {fval, ctor, ival}; + + gcc_jit_rvalue *ctor_bar = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_bar_type, + 3, + 0, + vals2); + + gcc_jit_global_set_initializer_rvalue (bar, ctor_bar); + } + { /* struct fi foo = {.f=2, .i=3}; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + struct_fi_type, + "global_struct_fi_23_1"); + + gcc_jit_rvalue *fval = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 2); + gcc_jit_rvalue *ival = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + + gcc_jit_rvalue *vals[] = { fval, ival}; + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + fields, + vals); + + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* struct fi foo = {2, 3}; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + struct_fi_type, + "global_struct_fi_23_2"); + + gcc_jit_rvalue *fval = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 2); + gcc_jit_rvalue *ival = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + + gcc_jit_rvalue *vals[] = { fval, ival}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + 0, + vals); + + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* struct fi foo = {.i=0, .f=0}; (null init) */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + struct_fi_type, + "global_struct_fi_00_1"); + + gcc_jit_rvalue *vals[] = { 0, 0}; + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + fields, + vals); + + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* struct fi foo = {0, 0}; (null fields, null elements in values) */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + struct_fi_type, + "global_struct_fi_00_2"); + + gcc_jit_rvalue *vals[] = { 0, 0}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + 0, + vals); + + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* struct fi foo = {.i = 0} (null init); + + Null init values. */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + struct_fi_type, + "global_struct_fi_0_1"); + + gcc_jit_rvalue *vals[] = {0}; + gcc_jit_field *fields[] = {fi_i}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 1, + fields, + vals); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* struct fi foo = {0}; + + Null init values. */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + struct_fi_type, + "global_struct_fi_0_2"); + + gcc_jit_rvalue *vals[] = {0}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 1, + 0, + vals); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* struct fi foo = {}; (null init) + + Null fields and values. */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + struct_fi_type, + "global_struct_fi_6"); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 0, + 0, + 0); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* struct fi foo = {2 * 2, 3}; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + struct_fi_type, + "global_struct_fi_3"); + + gcc_jit_rvalue *fval = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 2); + gcc_jit_rvalue *fval2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 2); + gcc_jit_rvalue *ival = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_rvalue *rval_mul = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_MULT, + float_type, + fval, + fval2); + + gcc_jit_rvalue *vals[] = { rval_mul, ival}; + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + fields, + vals); + + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* union ubar foo = {.ff = 3}; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + ubar, + "global_union_ufoo_ff3"); + + gcc_jit_rvalue *fval = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 3); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_union_constructor ( + ctxt, + 0, + ubar, + ubar_ff, + fval); + + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* union ubar foo = {.ii = 2}; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + ubar, + "global_union_ufoo_ii2"); + + gcc_jit_rvalue *ival = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 2); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_union_constructor ( + ctxt, + 0, + ubar, + ubar_ii, + ival); + + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* union ubar foo = {1.1f}; should init first field */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + ubar, + "global_union_ufoo_ff1c1"); + + gcc_jit_rvalue *fval = gcc_jit_context_new_rvalue_from_double ( + ctxt, float_type, 1.1); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_union_constructor ( + ctxt, + 0, + ubar, + 0, + fval); + + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* union ubar foo = (union ubar){}; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + ubar, + "global_union_ufoo_0"); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_union_constructor ( + ctxt, + 0, + ubar, + 0, + 0); + + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* int foo = 3; */ + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_int1_3"); + gcc_jit_global_set_initializer_rvalue (foo, + rval); + } + { /* const volatile int foo = 3; */ + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_type_get_const (gcc_jit_type_get_volatile (int_type)), + "global_cvint1_3"); + gcc_jit_global_set_initializer_rvalue (foo, + rval); + } + { /* Try the above, but with opposite order of global and literal calls */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_int2_3"); + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_global_set_initializer_rvalue (foo, + rval); + } + { /* int foo = 3 * (3 + 3) */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_int3_18"); + gcc_jit_rvalue *rval3_0 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_rvalue *rval3_1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_rvalue *rval3_2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_rvalue *rval_plus = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_PLUS, + int_type, + rval3_0, + rval3_1); + gcc_jit_rvalue *rval_mul = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_MULT, + int_type, + rval_plus, + rval3_2); + + gcc_jit_global_set_initializer_rvalue (foo, + rval_mul); + } + { /* int foo = ~(-(((((2 | 8) & 15) ^ 0) << 3 >> 2 - 1) / 2)); */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_int_alotofoperators"); + gcc_jit_rvalue *rval_0 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 2); + gcc_jit_rvalue *rval_1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 8); + gcc_jit_rvalue *rval_2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 15); + gcc_jit_rvalue *rval_3 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 0); + gcc_jit_rvalue *rval_4 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_rvalue *rval_5 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 2); + gcc_jit_rvalue *rval_6 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 1); + gcc_jit_rvalue *rval_7 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 2); + + gcc_jit_rvalue *rval_or = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_BITWISE_OR, + int_type, + rval_0, + rval_1); + gcc_jit_rvalue *rval_and = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_BITWISE_AND, + int_type, + rval_or, + rval_2); + gcc_jit_rvalue *rval_xor = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_BITWISE_XOR, + int_type, + rval_and, + rval_3); + gcc_jit_rvalue *rval_lsh = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_LSHIFT, + int_type, + rval_xor, + rval_4); + gcc_jit_rvalue *rval_rsh = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_RSHIFT, + int_type, + rval_lsh, + rval_5); + gcc_jit_rvalue *rval_min = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_MINUS, + int_type, + rval_rsh, + rval_6); + gcc_jit_rvalue *rval_div = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_DIVIDE, + int_type, + rval_min, + rval_7); + gcc_jit_rvalue *rval_umin = gcc_jit_context_new_unary_op (ctxt, 0, + GCC_JIT_UNARY_OP_MINUS, + int_type, + rval_div); + gcc_jit_rvalue *rval_neg = gcc_jit_context_new_unary_op (ctxt, 0, + GCC_JIT_UNARY_OP_BITWISE_NEGATE, + int_type, + rval_umin); + + gcc_jit_global_set_initializer_rvalue (foo, + rval_neg); + } + { /* int foo = 3; int *pfoo = &foo; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_int4_3"); + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_global_set_initializer_rvalue (foo, + rval); + + gcc_jit_lvalue *pfoo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + pint_type, + "global_pint5"); + gcc_jit_global_set_initializer_rvalue (pfoo, + gcc_jit_lvalue_get_address (foo, 0)); + } + { /* static int foo; int *pfoo = &foo; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_INTERNAL, + int_type, + "global_int5_3"); + + gcc_jit_lvalue *pfoo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + pint_type, + "global_pint6"); + gcc_jit_global_set_initializer_rvalue (pfoo, + gcc_jit_lvalue_get_address (foo, 0)); + + gcc_jit_function *fn = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + gcc_jit_type_get_pointer(int_type), + "fn_pint_0", + 0, + 0, + 0); + + gcc_jit_block *block = gcc_jit_function_new_block (fn, "start"); + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_get_address (foo, 0)); + } + { /* int foo = 3; int *pfoo = &foo + 1; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_int6_3"); + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_global_set_initializer_rvalue (foo, + rval); + + gcc_jit_lvalue *pfoo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + pint_type, + "global_pint7"); + gcc_jit_global_set_initializer_rvalue (pfoo, + gcc_jit_lvalue_get_address ( + gcc_jit_context_new_array_access( + ctxt, + 0, + gcc_jit_lvalue_get_address(foo, 0), + gcc_jit_context_one(ctxt, int_type)), + 0)); + } + { /* double foo = 3; */ + gcc_jit_lvalue *double1 = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + double_type, + "global_double1_3"); + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, double_type, 3); + gcc_jit_global_set_initializer_rvalue (double1, + rval); + } + { /* double foo = 3 * 3 + 3 */ + gcc_jit_lvalue *double1 = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + double_type, + "global_double2_12"); + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, double_type, 3); + gcc_jit_rvalue *rval_mul = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_MULT, + double_type, + rval, + rval); + gcc_jit_rvalue *rval_plus = gcc_jit_context_new_binary_op (ctxt, 0, + GCC_JIT_BINARY_OP_PLUS, + double_type, + rval_mul, + rval); + gcc_jit_global_set_initializer_rvalue (double1, + rval_plus); + } + { /* bool foo = 3 + 3 <= 6; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + bool_type, + "global_bool1_1"); + gcc_jit_rvalue *rval3_0 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_rvalue *rval3_1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_rvalue *rval6 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 6); + gcc_jit_rvalue *rval_plus = gcc_jit_context_new_binary_op (ctxt, + 0, + GCC_JIT_BINARY_OP_PLUS, + int_type, + rval3_0, + rval3_1); + gcc_jit_rvalue *rval_le = gcc_jit_context_new_comparison (ctxt, + 0, + GCC_JIT_COMPARISON_LE, + rval_plus, + rval6); + + gcc_jit_global_set_initializer_rvalue (foo, + rval_le); + } + gcc_jit_lvalue *global_intarr_1234; + { /* int foo[] = {1,2,3,4}; */ + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + int_type, + 4); + gcc_jit_rvalue *rval_1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 1); + gcc_jit_rvalue *rval_2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 2); + gcc_jit_rvalue *rval_3 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_rvalue *rval_4 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 4); + + gcc_jit_rvalue *values[] = {rval_1, rval_2, rval_3, rval_4}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 4, + values); + global_intarr_1234 = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_intarr_1234"); + gcc_jit_global_set_initializer_rvalue (global_intarr_1234, ctor); + } + { /* float foo[4] = {1,2}; */ + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + float_type, + 4); + gcc_jit_rvalue *rval_1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 1); + gcc_jit_rvalue *rval_2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 2); + + gcc_jit_rvalue *values[] = {rval_1, rval_2}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 2, + values); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_floatarr_12"); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* float foo[4] = {1,2}; + With different array objects of same size and type. */ + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + float_type, + 4); + gcc_jit_type *arr_type1 = gcc_jit_context_new_array_type (ctxt, + 0, + float_type, + 4); + gcc_jit_rvalue *rval_1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 1); + gcc_jit_rvalue *rval_2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 2); + + gcc_jit_rvalue *values[] = {rval_1, rval_2}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type1, + 2, + values); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_floatarr_12_2"); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* float foo[4] = {1,2,0}; (null init) */ + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + float_type, + 4); + gcc_jit_rvalue *rval_1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 1); + gcc_jit_rvalue *rval_2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 2); + + gcc_jit_rvalue *values[] = {rval_1, rval_2, 0}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 2, + values); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_floatarr_120"); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* float foo[4] = {}; (null init) */ + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + float_type, + 4); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 0, + 0); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_floatarr_0000"); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* float foo[4] = {NULL , NULL, 3, NULL, 5, 6}; (null init) */ + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + float_type, + 8); + gcc_jit_rvalue *rval3 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 3); + gcc_jit_rvalue *rval5 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 5); + gcc_jit_rvalue *rval6 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 6); + + gcc_jit_rvalue *values[] = {0, 0, rval3, 0, rval5, rval6, 0 }; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 7, + values); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_floatarr_00305600"); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* int *foo[4] = {0, &global_intarr_1234[1], 0}; */ + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + pint_type, + 4); + gcc_jit_rvalue *rval_1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 1); + gcc_jit_lvalue *arr_access = gcc_jit_context_new_array_access ( + ctxt, + 0, + gcc_jit_lvalue_as_rvalue (global_intarr_1234), + rval_1); + gcc_jit_rvalue *rval_2 = gcc_jit_lvalue_get_address (arr_access, 0); + gcc_jit_rvalue *rval_3 = gcc_jit_context_null (ctxt, pint_type); + + gcc_jit_rvalue *values[] = {0, rval_2, rval_3}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 2, + values); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_pintarr_x2xx"); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* char foo[4] = {'q','w','e',0}; */ + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + char_type, + 4); + + + gcc_jit_rvalue *rvals[] = { + gcc_jit_context_new_rvalue_from_int ( ctxt, char_type, 'q'), + gcc_jit_context_new_rvalue_from_int ( ctxt, char_type, 'w'), + gcc_jit_context_new_rvalue_from_int ( ctxt, char_type, 'e'), + gcc_jit_context_new_rvalue_from_int ( ctxt, char_type, 0) + }; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 4, + rvals); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_chararr_qwe"); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* int foo[2][2] = {{1,2},{3,4}}; */ + + gcc_jit_type *row_type = gcc_jit_context_new_array_type (ctxt, + 0, + int_type, + 2); + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + row_type, + 2); + gcc_jit_rvalue *rvals_row0[] = { + gcc_jit_context_new_rvalue_from_int ( ctxt, int_type, 1), + gcc_jit_context_new_rvalue_from_int ( ctxt, int_type, 2) + }; + gcc_jit_rvalue *rvals_row1[] = { + gcc_jit_context_new_rvalue_from_int ( ctxt, int_type, 3), + gcc_jit_context_new_rvalue_from_int ( ctxt, int_type, 4) + }; + + gcc_jit_rvalue *ctor_row0 = + gcc_jit_context_new_array_constructor (ctxt, + 0, + row_type, + 2, + rvals_row0); + gcc_jit_rvalue *ctor_row1 = + gcc_jit_context_new_array_constructor (ctxt, + 0, + row_type, + 2, + rvals_row1); + gcc_jit_rvalue *ctors_row[] = {ctor_row0, ctor_row1}; + + gcc_jit_rvalue *ctor_arr = + gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 2, + ctors_row); + + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_int2x2matrix_1234"); + + gcc_jit_global_set_initializer_rvalue (foo, ctor_arr); + } + { /* const char *foo[4] = {"qwe", "asd"}; */ + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + cpchar_type, + 4); + + + gcc_jit_rvalue *rvals[] = { + gcc_jit_context_new_string_literal (ctxt, "qwe"), + gcc_jit_context_new_string_literal (ctxt, "asd") + }; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 2, + rvals); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_cpchararr_qwe_asd"); + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + { /* const int foo = 3; + int bar = foo; + */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_type_get_const (int_type), + "global_const_int_3"); + gcc_jit_rvalue *rval3 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_global_set_initializer_rvalue (foo, + rval3); + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_lvalueinit_int_3"); + gcc_jit_global_set_initializer_rvalue (bar, + gcc_jit_lvalue_as_rvalue (foo)); + } + { /* int foo = 3 * 2; + int arr[] = {1,2,3,4}; + int *bar = &arr[2] + 1 + + Example in the docs. + */ + + gcc_jit_type *arr_type = gcc_jit_context_new_array_type (ctxt, + 0, + int_type, + 4); + gcc_jit_rvalue *rval_1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 1); + gcc_jit_rvalue *rval_2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 2); + gcc_jit_rvalue *rval_3 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_rvalue *rval_4 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 4); + + gcc_jit_rvalue *values[] = {rval_1, rval_2, rval_3, rval_4}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor (ctxt, + 0, + arr_type, + 4, + values); + gcc_jit_lvalue *global_intarr_1234 = + gcc_jit_context_new_global (ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + arr_type, + "global_intarr_1234_2"); + + gcc_jit_global_set_initializer_rvalue (global_intarr_1234, ctor); + + gcc_jit_lvalue *bar = + gcc_jit_context_new_global (ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_int_6"); + gcc_jit_global_set_initializer_rvalue + (bar, + gcc_jit_context_new_binary_op + (ctxt, 0, GCC_JIT_BINARY_OP_MULT, + int_type, + gcc_jit_context_new_rvalue_from_int (ctxt, int_type, 3), + gcc_jit_context_new_rvalue_from_int (ctxt, int_type, 2))); + + gcc_jit_lvalue *pfoo = + gcc_jit_context_new_global (ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_type_get_pointer (int_type), + "global_pint_4"); + /* int *bar = &arr[2] + 1; + + In practice we could just do &foo[3] + but just prove folding this works. */ + gcc_jit_global_set_initializer_rvalue ( + pfoo, + gcc_jit_lvalue_get_address ( + gcc_jit_context_new_array_access ( + ctxt, 0, + gcc_jit_lvalue_get_address ( + gcc_jit_context_new_array_access ( + ctxt, 0, + gcc_jit_lvalue_as_rvalue (global_intarr_1234), + gcc_jit_context_new_rvalue_from_int (ctxt, int_type, 2)), + 0), + gcc_jit_context_new_rvalue_from_int (ctxt, int_type, 1)), + 0)); + } + { /* static int bar = 11; + int foo () { return bar; } */ + + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_INTERNAL, + int_type, + "global_static_int_11"); + gcc_jit_rvalue *rval1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 11); + gcc_jit_global_set_initializer_rvalue (bar, + rval1); + + gcc_jit_function *fn11 = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + int_type, + "fn_int_11", + 0, + 0, + 0); + gcc_jit_block *block = gcc_jit_function_new_block (fn11, "start"); + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_as_rvalue(bar)); + } + { /* static const int cbar = 11; + int cfoo () { return cbar; } */ + + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_INTERNAL, + gcc_jit_type_get_const (int_type), + "global_static_cint_11"); + gcc_jit_rvalue *rval1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 11); + gcc_jit_global_set_initializer_rvalue (bar, + rval1); + + gcc_jit_function *fn11 = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + int_type, + "fn_cint_11", + 0, + 0, + 0); + gcc_jit_block *block = gcc_jit_function_new_block (fn11, "start"); + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_as_rvalue(bar)); + } + { /* static const int cbar = 12; + const int* cfoo () { return &cbar; } */ + + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_INTERNAL, + gcc_jit_type_get_const (int_type), + "global_static_cint_12"); + gcc_jit_rvalue *rval1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 12); + gcc_jit_global_set_initializer_rvalue (bar, + rval1); + + gcc_jit_function *fn11 = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + gcc_jit_type_get_pointer(int_type), + "fn_cint_12", + 0, + 0, + 0); + + gcc_jit_block *block = gcc_jit_function_new_block (fn11, "start"); + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_get_address (bar, 0)); + } + { /* const int foo = 3; + short bar = (short)foo; + + Assure casts fold + */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_type_get_const (int_type), + "global_const_int_4"); + gcc_jit_rvalue *rval3 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_global_set_initializer_rvalue (foo, + rval3); + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + short_type, + "global_lvalueinit_short_3"); + gcc_jit_global_set_initializer_rvalue ( + bar, + gcc_jit_context_new_cast( ctxt, 0, + gcc_jit_lvalue_as_rvalue (foo), + short_type)); + } + { /* const int foo = 3; + const int const *bar = &foo; */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_type_get_const (int_type), + "global_const_int_6"); + gcc_jit_rvalue *rval3 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + gcc_jit_global_set_initializer_rvalue (foo, + rval3); + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_type_get_const ( + gcc_jit_type_get_pointer ( + gcc_jit_type_get_const ( + int_type))), + "global_lvalueinit_cpcint_3"); + gcc_jit_global_set_initializer_rvalue ( + bar, + gcc_jit_lvalue_get_address (foo, 0)); + } + { /* const int __attribute__ ((aligned (64))) foo = 3; + int bar = foo; + + Assure alignement does not make the constant "miss" + or something strange. + */ + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_type_get_const (gcc_jit_type_get_aligned (int_type, 64)), + "global_const_int_7"); + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 4); + gcc_jit_global_set_initializer_rvalue (foo, + rval); + gcc_jit_lvalue *bar = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + int_type, + "global_lvalueinit_int_4"); + gcc_jit_global_set_initializer_rvalue (bar, + gcc_jit_lvalue_as_rvalue (foo)); + } + { + /* union upintsize { size_t s; int *p } u = {.s = 0xEEEFBEEF}; */ + gcc_jit_field *f1 = gcc_jit_context_new_field (ctxt, + 0, + size_type, + "s"); + gcc_jit_field *f2 = gcc_jit_context_new_field (ctxt, + 0, + pint_type, + "p"); + gcc_jit_field *fields1[] = {f1, f2}; + + gcc_jit_type *ubar = gcc_jit_context_new_union_type (ctxt, + 0, + "upintsize", + 2, + fields1); + gcc_jit_lvalue *foo = gcc_jit_context_new_global ( + ctxt, NULL, + GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_type_get_const (ubar), + "global_const_upintsize_1"); + + gcc_jit_rvalue *val = gcc_jit_context_new_rvalue_from_long ( + ctxt, size_type, 0xEEEFBEEF); + + gcc_jit_rvalue *ctor = + gcc_jit_context_new_union_constructor (ctxt, + 0, + ubar, + f1, + val); + + gcc_jit_global_set_initializer_rvalue (foo, ctor); + } + {/* + struct B; + struct A { B* b; }; + struct B { A* a; }; + extern struct B b; + struct A a = {.b = b}; + struct B b = {.a = a}; + + See that opaque structs and circular pointers works. + */ + + gcc_jit_struct *struct_B = + gcc_jit_context_new_opaque_struct(ctxt, + 0, "B"); + + gcc_jit_field *fields_A[] = + { + gcc_jit_context_new_field (ctxt, 0, + gcc_jit_type_get_pointer ( + gcc_jit_struct_as_type (struct_B)), + "b") + }; + + gcc_jit_struct *struct_A = + gcc_jit_context_new_struct_type(ctxt, 0, "A", 1, fields_A); + + gcc_jit_field *fields_B[] = + { + gcc_jit_context_new_field (ctxt, 0, + gcc_jit_type_get_pointer ( + gcc_jit_struct_as_type (struct_A)), + "a") + }; + + gcc_jit_struct_set_fields (struct_B, 0, 1, fields_B); + + gcc_jit_lvalue *a = + gcc_jit_context_new_global (ctxt, 0, GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_struct_as_type (struct_A), + "a_glb"); + gcc_jit_lvalue *b = + gcc_jit_context_new_global (ctxt, 0, GCC_JIT_GLOBAL_EXPORTED, + gcc_jit_struct_as_type (struct_B), + "b_glb"); + gcc_jit_rvalue *b_addr = gcc_jit_lvalue_get_address( b, 0); + gcc_jit_rvalue *a_ctor = + gcc_jit_context_new_struct_constructor (ctxt, 0, + gcc_jit_struct_as_type (struct_A), + 1, 0, + &b_addr); + gcc_jit_rvalue *a_addr = gcc_jit_lvalue_get_address( a, 0); + gcc_jit_rvalue *b_ctor = + gcc_jit_context_new_struct_constructor (ctxt, 0, + gcc_jit_struct_as_type (struct_B), + 1, 0, + &a_addr); + + gcc_jit_global_set_initializer_rvalue(a, a_ctor); + gcc_jit_global_set_initializer_rvalue(b, b_ctor); + } +} + +struct fi { + float f; + int i; +}; + +struct bar1 { + float ff; + struct fi fi; + int ii; +}; + +union ubar1 { + float ff; + int ii; +}; + +union upintsize { + size_t s; + int *p; +}; + +struct B_glb; +struct A_glb { + struct B_glb *b; +}; +struct B_glb { + struct A_glb *a; +}; + +int test_aligned64_works_in_linker_1 __attribute__ ((aligned (64))) = 0; +int test_aligned64_works_in_linker_2 __attribute__ ((aligned (64))) = 0; + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + CHECK_NON_NULL (result); + + { + struct bar1 *bar = + gcc_jit_result_get_global (result, "global_struct_bar_1234_1"); + + CHECK_VALUE (bar->ff, 1); + CHECK_VALUE (bar->fi.f, 2); + CHECK_VALUE (bar->fi.i, 3); + CHECK_VALUE (bar->ii, 4); + } + { + struct bar1 *bar = + gcc_jit_result_get_global (result, "global_struct_bar_1234_2"); + + CHECK_VALUE (bar->ff, 1); + CHECK_VALUE (bar->fi.f, 2); + CHECK_VALUE (bar->fi.i, 3); + CHECK_VALUE (bar->ii, 4); + } + { + struct fi *fi = gcc_jit_result_get_global (result, "global_struct_fi_23_1"); + + CHECK_VALUE (fi->f, 2); + CHECK_VALUE (fi->i, 3); + } + { + struct fi *fi = gcc_jit_result_get_global (result, "global_struct_fi_23_2"); + + CHECK_VALUE (fi->f, 2); + CHECK_VALUE (fi->i, 3); + } + { + struct fi *fi = gcc_jit_result_get_global (result, "global_struct_fi_00_1"); + + CHECK_VALUE (fi->f, 0); + CHECK_VALUE (fi->i, 0); + } + { + struct fi *fi = gcc_jit_result_get_global (result, "global_struct_fi_00_2"); + + CHECK_VALUE (fi->f, 0); + CHECK_VALUE (fi->i, 0); + } + { + struct fi *fi = gcc_jit_result_get_global (result, "global_struct_fi_0_1"); + + CHECK_VALUE (fi->f, 0); + CHECK_VALUE (fi->i, 0); + } + { + struct fi *fi = gcc_jit_result_get_global (result, "global_struct_fi_0_2"); + + CHECK_VALUE (fi->f, 0); + CHECK_VALUE (fi->i, 0); + } + { + struct fi *fi = gcc_jit_result_get_global (result, "global_struct_fi_6"); + + CHECK_VALUE (fi->f, 0); + CHECK_VALUE (fi->i, 0); + } + { + struct fi *fi = gcc_jit_result_get_global (result, "global_struct_fi_3"); + + CHECK_VALUE (fi->f, 2 * 2); + CHECK_VALUE (fi->i, 3); + } + { + union ubar1 *foo = gcc_jit_result_get_global (result, + "global_union_ufoo_ff3"); + CHECK_VALUE (foo->ff, 3); + } + { + union ubar1 *foo = gcc_jit_result_get_global (result, + "global_union_ufoo_ii2"); + CHECK_VALUE (foo->ii, 2); + } + { + union ubar1 *foo = gcc_jit_result_get_global (result, + "global_union_ufoo_ff1c1"); + CHECK_VALUE (foo->ff, 1.1f); + } + { + union ubar1 *foo = gcc_jit_result_get_global (result, + "global_union_ufoo_0"); + CHECK_VALUE (foo->ii, 0); + } + { + int *foo = gcc_jit_result_get_global (result, "global_int1_3"); + + CHECK_VALUE (*foo, 3); + } + { + int *foo = gcc_jit_result_get_global (result, "global_cvint1_3"); + + CHECK_VALUE (*foo, 3); + } + { + int *foo = gcc_jit_result_get_global (result, "global_int2_3"); + + CHECK_VALUE (*foo, 3); + } + { + int *foo = gcc_jit_result_get_global (result, "global_int3_18"); + + CHECK_VALUE (*foo, 18); + } + { + int *foo = gcc_jit_result_get_global (result, "global_int_alotofoperators"); + + CHECK_VALUE (*foo, ~(-((((((2 | 8) & 15) ^ 0) << 3 >> 2) - 1) / 2))); + } + { + int *foo = gcc_jit_result_get_global (result, "global_int4_3"); + int **pfoo = gcc_jit_result_get_global (result, "global_pint5"); + + CHECK_VALUE (*foo, 3); + CHECK_VALUE (foo, *pfoo); + CHECK_VALUE (**pfoo, 3); + } + { + int * (*foo) (void) = gcc_jit_result_get_code (result, "fn_pint_0"); + int **pfoo = gcc_jit_result_get_global (result, "global_pint6"); + + CHECK_VALUE (*foo (), 0); + CHECK_VALUE (foo (), *pfoo); + CHECK_VALUE (**pfoo, 0); + } + { + int *foo = gcc_jit_result_get_global (result, "global_int6_3"); + int **pfoo = gcc_jit_result_get_global (result, "global_pint7"); + + CHECK_VALUE (*foo, 3); + CHECK_VALUE (foo + 1, *pfoo); + CHECK_VALUE (*(*pfoo - 1), 3); + } + { + double *foo = gcc_jit_result_get_global (result, "global_double1_3"); + + CHECK_VALUE (*foo, 3); + } + { + double *foo = gcc_jit_result_get_global (result, "global_double2_12"); + + CHECK_VALUE (*foo, 12); + } + { + _Bool *foo = gcc_jit_result_get_global (result, "global_bool1_1"); + + CHECK_VALUE (*foo, 1); + } + { + int *foo = gcc_jit_result_get_global (result, "global_intarr_1234"); + + CHECK_VALUE (foo[0], 1); + CHECK_VALUE (foo[1], 2); + CHECK_VALUE (foo[2], 3); + CHECK_VALUE (foo[3], 4); + } + { + float *foo = gcc_jit_result_get_global (result, "global_floatarr_12"); + + CHECK_VALUE (foo[0], 1); + CHECK_VALUE (foo[1], 2); + CHECK_VALUE (foo[2], 0); + CHECK_VALUE (foo[3], 0); + } + { + float *foo = gcc_jit_result_get_global (result, "global_floatarr_12_2"); + + CHECK_VALUE (foo[0], 1); + CHECK_VALUE (foo[1], 2); + CHECK_VALUE (foo[2], 0); + CHECK_VALUE (foo[3], 0); + } + { + float *foo = gcc_jit_result_get_global (result, "global_floatarr_120"); + + CHECK_VALUE (foo[0], 1); + CHECK_VALUE (foo[1], 2); + CHECK_VALUE (foo[2], 0); + CHECK_VALUE (foo[3], 0); + } + { + float *foo = gcc_jit_result_get_global (result, "global_floatarr_0000"); + + CHECK_VALUE (foo[0], 0); + CHECK_VALUE (foo[1], 0); + CHECK_VALUE (foo[2], 0); + CHECK_VALUE (foo[3], 0); + } + { + float *foo = gcc_jit_result_get_global (result, "global_floatarr_00305600"); + + float key[] = {0,0,3,0,5,6,0,0}; + + CHECK_VALUE (memcmp (foo, key, sizeof key), 0); + } + { + int **foo = gcc_jit_result_get_global (result, "global_pintarr_x2xx"); + + CHECK_VALUE (foo[0], 0); + CHECK_VALUE (*foo[1], 2); + } + { + char *foo = gcc_jit_result_get_global (result, "global_chararr_qwe"); + const char *key = "qwe"; + CHECK_VALUE (strcmp (foo, key), 0); + } + { + int *foo = gcc_jit_result_get_global (result, "global_int2x2matrix_1234"); + + for (int i = 0; i < 4; i++) + CHECK_VALUE (foo[i], i + 1); + } + { + const char **foo = + gcc_jit_result_get_global (result, "global_cpchararr_qwe_asd"); + + CHECK_VALUE (strcmp (foo[0], "qwe"), 0); + CHECK_VALUE (strcmp (foo[1], "asd"), 0); + } + { + int *foo = gcc_jit_result_get_global (result, "global_lvalueinit_int_3"); + + CHECK_VALUE (*foo, 3); + } + { + int **pint = + gcc_jit_result_get_global (result, "global_pint_4"); + int *foo = + gcc_jit_result_get_global (result, "global_int_6"); + CHECK_VALUE (**pint, 4); + CHECK_VALUE (*foo, 6); + } + { + int (*fn)(void) = gcc_jit_result_get_code (result, "fn_int_11"); + CHECK_VALUE (fn (), 11); + } + { + int (*fn)(void) = gcc_jit_result_get_code (result, "fn_cint_11"); + CHECK_VALUE (fn (), 11); + } + { + int *(*fn)(void) = gcc_jit_result_get_code (result, "fn_cint_12"); + CHECK_VALUE (*fn (), 12); + } + { + short *foo = + gcc_jit_result_get_code (result, "global_lvalueinit_short_3"); + CHECK_VALUE (*foo, 3); + } + { + int **foo = + gcc_jit_result_get_code (result, "global_lvalueinit_cpcint_3"); + CHECK_VALUE (**foo, 3); + } + { + int *foo = + gcc_jit_result_get_code (result, "global_lvalueinit_int_4"); + CHECK_VALUE (*foo, 4); + + int *bar = + gcc_jit_result_get_code (result, "global_const_int_7"); + CHECK_VALUE (*bar, 4); + /* The linker does not have to support up to 64 alignment, so test that + it does before testing that it works in libgccjit. */ + if ((size_t) &test_aligned64_works_in_linker_1 % 64 == 0 && + (size_t) &test_aligned64_works_in_linker_2 % 64 == 0) + CHECK_VALUE ((size_t) bar % 64, 0); /* __attribute__ ((aligned (64))) */ + } + { + union upintsize *foo = + gcc_jit_result_get_code (result, "global_const_upintsize_1"); + CHECK_VALUE (foo->p, (void*)0xEEEFBEEF); + } + { + struct A_glb *a = + gcc_jit_result_get_code (result, "a_glb"); + struct B_glb *b = + gcc_jit_result_get_code (result, "b_glb"); + + CHECK_VALUE (a->b, b); + CHECK_VALUE (b->a, a); + } +} diff --git a/gcc/testsuite/jit.dg/test-local-init-rvalue.c b/gcc/testsuite/jit.dg/test-local-init-rvalue.c new file mode 100644 index 0000000..1d74679 --- /dev/null +++ b/gcc/testsuite/jit.dg/test-local-init-rvalue.c @@ -0,0 +1,707 @@ +#include +#include "libgccjit.h" +#include "harness.h" + +/* This testcase checks that gcc_jit_context_new_constructor() works + with locals. Tests that constructors can be used as return + values or function call values. Test that constructors can have side + effects and be assigned to locals. + */ + +void +create_code (gcc_jit_context *ctxt, void *user_data) +{ + gcc_jit_type *int_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_INT); + gcc_jit_type *pint_type = gcc_jit_type_get_pointer (int_type); + gcc_jit_type *double_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_DOUBLE); + gcc_jit_type *float_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_FLOAT); + gcc_jit_type *bool_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_BOOL); + gcc_jit_type *char_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_CHAR); + gcc_jit_type *size_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_SIZE_T); + gcc_jit_type *voidptr_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_VOID_PTR); + gcc_jit_type *void_type = gcc_jit_context_get_type (ctxt, + GCC_JIT_TYPE_VOID); + + /* Make a struct: struct fi { float f; int i;} */ + gcc_jit_field *fi_f = gcc_jit_context_new_field (ctxt, + 0, + float_type, + "f"); + gcc_jit_field *fi_i = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "i"); + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_type *struct_fi_type = + gcc_jit_struct_as_type ( + gcc_jit_context_new_struct_type (ctxt, + 0, + "fi", + 2, + fields)); + + /* Make a struct: + + struct bar { + int ii; + int arr[50]; + float ff; + char cc; + } + */ + gcc_jit_field *bar_ff = gcc_jit_context_new_field (ctxt, + 0, + float_type, + "ff"); + gcc_jit_field *bar_ii = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "ii"); + gcc_jit_field *bar_cc = gcc_jit_context_new_field (ctxt, + 0, + char_type, + "cc"); + gcc_jit_type *int50arr_type = + gcc_jit_context_new_array_type (ctxt, + 0, + int_type, + 50); + gcc_jit_field *bar_fi = gcc_jit_context_new_field (ctxt, + 0, + int50arr_type, + "arr"); + gcc_jit_field *fields2[] = {bar_ff, bar_fi, bar_ii, bar_cc}; + + gcc_jit_type *struct_bar_type = + gcc_jit_struct_as_type ( + gcc_jit_context_new_struct_type (ctxt, + 0, + "bar", + 4, + fields2)); + + /* Make an union: + + union ubar { + float ff; + int ii; + }; + */ + gcc_jit_field *ubar_ff = gcc_jit_context_new_field (ctxt, + 0, + float_type, + "ff"); + gcc_jit_field *ubar_ii = gcc_jit_context_new_field (ctxt, + 0, + int_type, + "ii"); + gcc_jit_field *fields3[] = {ubar_ff, ubar_ii}; + gcc_jit_type *ubar = gcc_jit_context_new_union_type (ctxt, + 0, + "ubar", + 2, + fields3); + + (void) ubar; + (void) struct_bar_type; + (void) struct_fi_type; + (void) bool_type; + (void) double_type; + (void) pint_type; + (void) voidptr_type; + (void) size_type; + + gcc_jit_function *fn_int_3; + { /* int foo () { int local = 3; return local;} */ + fn_int_3 = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + int_type, + "fn_int_3", + 0, + 0, + 0); + gcc_jit_block *block = gcc_jit_function_new_block (fn_int_3, "start"); + gcc_jit_lvalue *local = gcc_jit_function_new_local (fn_int_3, + 0, + int_type, + "local"); + gcc_jit_rvalue *rval = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 3); + + gcc_jit_block_add_assignment (block, 0, local, rval); + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_as_rvalue(local)); + } + { /* struct fi foo() { return (struct fi){1,2};} */ + gcc_jit_function *fn = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + struct_fi_type, + "fn_fi_1_2", + 0, + 0, + 0); + gcc_jit_block *block = gcc_jit_function_new_block (fn, "start"); + + gcc_jit_rvalue *rval_f1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 1); + gcc_jit_rvalue *rval_i2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 2); + + gcc_jit_rvalue *vals[] = { rval_f1, rval_i2}; + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + fields, + vals); + + gcc_jit_block_end_with_return (block, + 0, + ctor); + } + { /* + struct fi foo() + { + struct fi local = {1,2}; + local = (struct fi){5,6}; + return local; + } + */ + gcc_jit_function *fn = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + struct_fi_type, + "fn_fi_5_6", + 0, + 0, + 0); + gcc_jit_lvalue *local = gcc_jit_function_new_local (fn, + 0, + struct_fi_type, + "local"); + gcc_jit_block *block = gcc_jit_function_new_block (fn, "start"); + + { + gcc_jit_rvalue *rval_f1 = + gcc_jit_context_new_rvalue_from_int (ctxt, float_type, 1); + gcc_jit_rvalue *rval_i2 = + gcc_jit_context_new_rvalue_from_int (ctxt, int_type, 2); + + gcc_jit_rvalue *vals[] = { rval_f1, rval_i2}; + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + fields, + vals); + gcc_jit_block_add_assignment (block, 0, local, ctor); + } + { + gcc_jit_rvalue *rval_f1 = + gcc_jit_context_new_rvalue_from_int (ctxt, float_type, 5); + gcc_jit_rvalue *rval_i2 = + gcc_jit_context_new_rvalue_from_int (ctxt, int_type, 6); + + gcc_jit_rvalue *vals[] = { rval_f1, rval_i2}; + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + fields, + vals); + gcc_jit_block_add_assignment (block, 0, local, ctor); + } + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_as_rvalue(local)); + } + { /* struct fi foo() { struct fi local = {1, fn_int_3()}; + return local;} + + The ctor has a side effect (funccall) */ + gcc_jit_function *fn = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + struct_fi_type, + "fn_fi_1_3", + 0, + 0, + 0); + gcc_jit_lvalue *local = gcc_jit_function_new_local (fn, + 0, + struct_fi_type, + "local"); + gcc_jit_block *block = gcc_jit_function_new_block (fn, "start"); + + { + gcc_jit_rvalue *rval_f1 = + gcc_jit_context_new_rvalue_from_int (ctxt, float_type, 1); + gcc_jit_rvalue *rval_i2 = + gcc_jit_context_new_call (ctxt, 0, fn_int_3, 0, 0); + + gcc_jit_rvalue *vals[] = { rval_f1, rval_i2}; + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + fields, + vals); + gcc_jit_block_add_assignment (block, 0, local, ctor); + } + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_as_rvalue(local)); + } + { /* struct fi foo(fi) { return fi;} + struct fi bar() { return foo((struct fi){3, 4}); } + */ + + gcc_jit_param *fi_param = + gcc_jit_context_new_param (ctxt, 0, struct_fi_type, "fi"); + + gcc_jit_function *fn0 = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + struct_fi_type, + "fn_fi_x_x", + 1, + &fi_param, + 0); + gcc_jit_block *block0 = gcc_jit_function_new_block (fn0, "start"); + gcc_jit_block_end_with_return (block0, + 0, + gcc_jit_param_as_rvalue ( + gcc_jit_function_get_param (fn0, 0))); + + gcc_jit_function *fn = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + struct_fi_type, + "fn_fi_3_4", + 0, + 0, + 0); + gcc_jit_block *block = gcc_jit_function_new_block (fn, "start"); + + gcc_jit_rvalue *rval_f1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, float_type, 3); + gcc_jit_rvalue *rval_i2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 4); + + gcc_jit_rvalue *vals[] = { rval_f1, rval_i2}; + gcc_jit_field *fields[] = {fi_f, fi_i}; + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_fi_type, + 2, + fields, + vals); + + gcc_jit_rvalue *call = gcc_jit_context_new_call (ctxt, 0, fn0, 1, &ctor); + + gcc_jit_block_end_with_return (block, + 0, + call); + } + { /* + void foo(struct bar *b) { *b = (struct bar) {.arr = {1,2}; } + */ + + gcc_jit_param *param = + gcc_jit_context_new_param (ctxt, 0, + gcc_jit_type_get_pointer (struct_bar_type), + "b"); + + + gcc_jit_function *fn = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + void_type, + "fn_pbar_12", + 1, + ¶m, + 0); + gcc_jit_block *block = gcc_jit_function_new_block (fn, "start"); + + gcc_jit_rvalue *rval_i1 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 1); + gcc_jit_rvalue *rval_i2 = gcc_jit_context_new_rvalue_from_int ( + ctxt, int_type, 2); + + gcc_jit_rvalue *arr_vals[] = { rval_i1, rval_i2}; + + gcc_jit_rvalue *arr_ctor = gcc_jit_context_new_array_constructor + (ctxt, 0, + int50arr_type, + 2, + arr_vals); + + gcc_jit_rvalue *str_ctor = gcc_jit_context_new_struct_constructor + (ctxt, + 0, + struct_bar_type, + 1, + &bar_fi, + &arr_ctor); + + gcc_jit_param *p0 = gcc_jit_function_get_param (fn, 0); + gcc_jit_lvalue *lv0 = gcc_jit_param_as_lvalue (p0); + gcc_jit_lvalue *deref = + gcc_jit_rvalue_dereference (gcc_jit_lvalue_as_rvalue (lv0), 0); + + gcc_jit_block_add_assignment (block, 0, + deref, + str_ctor); + + gcc_jit_block_end_with_void_return (block, 0); + } + { /* struct bar foo() { struct bar local = {}; + return local;} + */ + gcc_jit_function *fn = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + struct_bar_type, + "fn_bar_0s", + 0, + 0, + 0); + gcc_jit_lvalue *local = + gcc_jit_function_new_local (fn, + 0, + struct_bar_type, + "local"); + gcc_jit_block *block = gcc_jit_function_new_block (fn, "start"); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_struct_constructor + (ctxt, 0, + struct_bar_type, + 0, + 0, + 0); + gcc_jit_block_add_assignment (block, 0, local, ctor); + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_as_rvalue(local)); + } + { /* struct bar foo() { struct bar local; + local.arr = (int [50]){1,2,3,4,5,6}; + return local;} + */ + gcc_jit_function *fn = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + struct_bar_type, + "fn_bar_123s", + 0, + 0, + 0); + gcc_jit_lvalue *local = + gcc_jit_function_new_local (fn, + 0, + struct_bar_type, + "local"); + gcc_jit_block *block = gcc_jit_function_new_block (fn, "start"); + + gcc_jit_rvalue *values[6]; + + for (int i = 0; i < 6; i++) + values[i] = gcc_jit_context_new_rvalue_from_int (ctxt, int_type, i + 1); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor + (ctxt, 0, + int50arr_type, + 6, + values); + + gcc_jit_lvalue *arr_lv = gcc_jit_lvalue_access_field (local, + 0, + bar_fi); + gcc_jit_block_add_assignment (block, 0, arr_lv, ctor); + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_as_rvalue(local)); + } + { /* int[50] foo() { int arr[50]; + arr = (int [50]){1,2,3,4,5,6}; + return arr;} + + N.B: Not a typo, returning an array. + */ + gcc_jit_function *fn = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + int50arr_type, + "fn_int50arr_123s", + 0, + 0, + 0); + gcc_jit_lvalue *local = + gcc_jit_function_new_local (fn, + 0, + int50arr_type, + "local"); + gcc_jit_block *block = gcc_jit_function_new_block (fn, "start"); + + gcc_jit_rvalue *values[6]; + + for (int i = 0; i < 6; i++) + values[i] = gcc_jit_context_new_rvalue_from_int (ctxt, int_type, i + 1); + + gcc_jit_rvalue *ctor = gcc_jit_context_new_array_constructor ( + ctxt, + 0, + int50arr_type, + 6, + values); + + gcc_jit_block_add_assignment (block, 0, local, ctor); + + gcc_jit_block_end_with_return (block, + 0, + gcc_jit_lvalue_as_rvalue(local)); + } + { /* + Verify that circular linked lists compiles, .e.g. + that visit_children does not run in circles or something. + + struct llist { struct llist *next; }; + + bool foo (void) + { + volatile struct llist a; + volatile struct llist b; + + a = (struct llist) {.next = &b}; + b = (struct llist) {.next = &a}; + + return a.next == &b; + } + */ + gcc_jit_struct *llist = + gcc_jit_context_new_opaque_struct(ctxt, + 0, "llist_lcl"); + gcc_jit_field *fields[] = + { + gcc_jit_context_new_field (ctxt, 0, + gcc_jit_type_get_pointer ( + gcc_jit_struct_as_type (llist)), + "next") + }; + gcc_jit_struct_set_fields (llist, 0, 1, fields); + gcc_jit_type *t_llist = gcc_jit_struct_as_type (llist); + + gcc_jit_function *fn = + gcc_jit_context_new_function (ctxt, + 0, + GCC_JIT_FUNCTION_EXPORTED, + bool_type, + "fn_llist", + 0, + 0, + 0); + gcc_jit_block *block = gcc_jit_function_new_block (fn, "start"); + + gcc_jit_lvalue *a = + gcc_jit_function_new_local (fn, + 0, + gcc_jit_type_get_volatile (t_llist), + "a"); + gcc_jit_lvalue *b = + gcc_jit_function_new_local (fn, + 0, + gcc_jit_type_get_volatile (t_llist), + "b"); + + gcc_jit_rvalue *a_addr = gcc_jit_lvalue_get_address( a, 0); + gcc_jit_rvalue *b_addr = gcc_jit_lvalue_get_address( b, 0); + + gcc_jit_rvalue *a_ctor = gcc_jit_context_new_struct_constructor ( + ctxt, + 0, + t_llist, + 1, + 0, + &b_addr); + + gcc_jit_rvalue *b_ctor = gcc_jit_context_new_struct_constructor ( + ctxt, + 0, + t_llist, + 1, + 0, + &a_addr); + + gcc_jit_block_add_assignment (block, 0, + a, a_ctor); + gcc_jit_block_add_assignment (block, 0, + b, b_ctor); + + gcc_jit_rvalue *cmp = + gcc_jit_context_new_comparison ( + ctxt, 0, + GCC_JIT_COMPARISON_EQ, + gcc_jit_rvalue_access_field (gcc_jit_lvalue_as_rvalue (a), + 0, fields[0]), + gcc_jit_context_new_cast (ctxt, 0, + gcc_jit_lvalue_get_address (b, 0), + gcc_jit_type_get_pointer (t_llist))); + + gcc_jit_block_end_with_return (block, + 0, cmp); + } +} + +struct fi2 { + float f; + int i; +}; + +struct bar2 { + float ff; + int arr[50]; + int ii; + char c; +}; + +union ubar2 { + float ff; + int ii; +}; + +struct int50arr { + int arr[50]; +}; + +void __attribute__((optimize(0))) +scramble_stack(void) + { + char *p = alloca(100); + for (int i = 0; i < 100; i++) + *p++ = 0xF0; + asm(""); /* Mark for side-effect */ + } + +void __attribute__((optimize(0))) +scramble_arr (char *arr, int len) +{ + for (int i = 0; i < len; i++) + *arr++ = i; + asm(""); /* Mark for side-effect */ +} + +void +verify_code (gcc_jit_context *ctxt, gcc_jit_result *result) +{ + CHECK_NON_NULL (result); + + { + struct fi2 (*fn) (void) = gcc_jit_result_get_code (result, "fn_fi_1_2"); + scramble_stack (); + struct fi2 fi = fn (); + CHECK_VALUE (fi.f, 1); + CHECK_VALUE (fi.i, 2); + } + { + struct fi2 (*fn) (void) = gcc_jit_result_get_code (result, "fn_fi_5_6"); + struct fi2 fi = fn (); + CHECK_VALUE (fi.f, 5); + CHECK_VALUE (fi.i, 6); + } + { + struct fi2 (*fn) (void) = gcc_jit_result_get_code (result, "fn_fi_1_3"); + struct fi2 fi = fn (); + CHECK_VALUE (fi.f, 1); + CHECK_VALUE (fi.i, 3); + } + { + struct fi2 (*fn) (void) = gcc_jit_result_get_code (result, "fn_fi_3_4"); + struct fi2 fi = fn (); + CHECK_VALUE (fi.f, 3); + CHECK_VALUE (fi.i, 4); + } + { + scramble_stack(); + struct bar2 (*fn) (void) = gcc_jit_result_get_code (result, "fn_bar_0s"); + struct bar2 bar = fn (); + struct bar2 key = {}; + + CHECK_VALUE (bar.ff, 0); + CHECK_VALUE (bar.ii, 0); + CHECK_VALUE (memcmp (&bar.arr, &key.arr, sizeof (key.arr)), 0); + } + { + + void (*fn) (struct bar2 *) = gcc_jit_result_get_code (result, "fn_pbar_12"); + + struct bar2 bar = (struct bar2) {}; + + scramble_arr ((char*)&bar, sizeof bar); + scramble_stack(); + + fn (&bar); + + struct bar2 key = {.arr = {1,2}}; + __builtin_clear_padding (&key); + + CHECK_VALUE (memcmp (&bar, &key, sizeof (key)), 0); + } + { + scramble_stack(); + struct bar2 (*fn) (void) = gcc_jit_result_get_code (result, "fn_bar_123s"); + struct bar2 bar = fn (); + struct bar2 key = {.arr = {1,2,3,4,5,6} }; + + CHECK_VALUE (memcmp (&bar.arr, &key.arr, sizeof (key.arr)), 0); + } + { + scramble_stack (); + /* This is abit shady. Lets just pretend that array returns à la Fortran + is the same thing as returning a struct with an array in it in C. */ + struct int50arr (*fn) (void) = + gcc_jit_result_get_code (result, "fn_int50arr_123s"); + struct int50arr ans = fn (); + int key[50] = {1,2,3,4,5,6}; + + CHECK_VALUE (memcmp (ans.arr, key, sizeof (key)), 0); + } + { + _Bool (*fn) (void) = gcc_jit_result_get_code (result, "fn_llist"); + CHECK_VALUE (fn (), 1); + } +} -- cgit v1.1 From 74aeb9726756aa79c21028712c26910866e33026 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 14 Dec 2021 10:09:06 -0600 Subject: rs6000: Some builtins require IBM-128 long double format (PR103623) 2021-12-14 Bill Schmidt gcc/ PR target/103623 * config/rs6000/rs6000-builtin-new.def (__builtin_pack_longdouble): Add ibmld attribute. (__builtin_unpack_longdouble): Likewise. * config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Add special handling for ibmld attribute. * config/rs6000/rs6000-gen-builtins.c (attrinfo): Add isibmld. (parse_bif_attrs): Handle ibmld. (write_decls): Likewise. (write_bif_static_init): Likewise. --- gcc/config/rs6000/rs6000-builtin-new.def | 15 +++++++-------- gcc/config/rs6000/rs6000-call.c | 7 +++++++ gcc/config/rs6000/rs6000-gen-builtins.c | 13 +++++++++++-- 3 files changed, 25 insertions(+), 10 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def index 30556e5..f7f5d2c 100644 --- a/gcc/config/rs6000/rs6000-builtin-new.def +++ b/gcc/config/rs6000/rs6000-builtin-new.def @@ -137,6 +137,7 @@ ; lxvrse Needs special handling for load-rightmost, sign-extended ; lxvrze Needs special handling for load-rightmost, zero-extended ; endian Needs special handling for endianness +; ibmld Restrict usage to the case when TFmode is IBM-128 ; ; Each attribute corresponds to extra processing required when ; the built-in is expanded. All such special processing should @@ -215,13 +216,10 @@ double __builtin_mffsl (); MFFSL rs6000_mffsl {} -; This thing really assumes long double == __ibm128, and I'm told it has -; been used as such within libgcc. Given that __builtin_pack_ibm128 -; exists for the same purpose, this should really not be used at all. -; TODO: Consider adding special handling for this to warn whenever -; long double is not __ibm128. +; This is redundant with __builtin_pack_ibm128, as it requires long +; double to be __ibm128. Should probably be deprecated. const long double __builtin_pack_longdouble (double, double); - PACK_TF packtf {} + PACK_TF packtf {ibmld} unsigned long __builtin_ppc_mftb (); MFTB rs6000_mftb_di {32bit} @@ -244,9 +242,10 @@ const double __builtin_unpack_ibm128 (__ibm128, const int<1>); UNPACK_IF unpackif {} -; See above comments for __builtin_pack_longdouble. +; This is redundant with __builtin_unpack_ibm128, as it requires long +; double to be __ibm128. Should probably be deprecated. const double __builtin_unpack_longdouble (long double, const int<1>); - UNPACK_TF unpacktf {} + UNPACK_TF unpacktf {ibmld} ; Builtins that have been around just about forever, but not quite. diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index d9736ea..3a43a76 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -15741,6 +15741,13 @@ rs6000_expand_new_builtin (tree exp, rtx target, return const0_rtx; } + if (bif_is_ibmld (*bifaddr) && !FLOAT128_2REG_P (TFmode)) + { + error ("%<%s%> requires % to be IBM 128-bit format", + bifaddr->bifname); + return const0_rtx; + } + if (bif_is_cpu (*bifaddr)) return new_cpu_expand_builtin (fcode, exp, target); diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c index 34ab70f..856770c1 100644 --- a/gcc/config/rs6000/rs6000-gen-builtins.c +++ b/gcc/config/rs6000/rs6000-gen-builtins.c @@ -92,6 +92,7 @@ along with GCC; see the file COPYING3. If not see lxvrse Needs special handling for load-rightmost, sign-extended lxvrze Needs special handling for load-rightmost, zero-extended endian Needs special handling for endianness + ibmld Restrict usage to the case when TFmode is IBM-128 An example stanza might look like this: @@ -390,6 +391,7 @@ struct attrinfo bool islxvrse; bool islxvrze; bool isendian; + bool isibmld; }; /* Fields associated with a function prototype (bif or overload). */ @@ -1435,6 +1437,8 @@ parse_bif_attrs (attrinfo *attrptr) attrptr->islxvrze = 1; else if (!strcmp (attrname, "endian")) attrptr->isendian = 1; + else if (!strcmp (attrname, "ibmld")) + attrptr->isibmld = 1; else { diag (oldpos, "unknown attribute.\n"); @@ -1468,14 +1472,14 @@ parse_bif_attrs (attrinfo *attrptr) "ldvec = %d, stvec = %d, reve = %d, pred = %d, htm = %d, " "htmspr = %d, htmcr = %d, mma = %d, quad = %d, pair = %d, " "mmaint = %d, no32bit = %d, 32bit = %d, cpu = %d, ldstmask = %d, " - "lxvrse = %d, lxvrze = %d, endian = %d.\n", + "lxvrse = %d, lxvrze = %d, endian = %d, ibmdld= %d.\n", attrptr->isinit, attrptr->isset, attrptr->isextract, attrptr->isnosoft, attrptr->isldvec, attrptr->isstvec, attrptr->isreve, attrptr->ispred, attrptr->ishtm, attrptr->ishtmspr, attrptr->ishtmcr, attrptr->ismma, attrptr->isquad, attrptr->ispair, attrptr->ismmaint, attrptr->isno32bit, attrptr->is32bit, attrptr->iscpu, attrptr->isldstmask, attrptr->islxvrse, - attrptr->islxvrze, attrptr->isendian); + attrptr->islxvrze, attrptr->isendian, attrptr->isibmld); #endif return PC_OK; @@ -2289,6 +2293,7 @@ write_decls (void) fprintf (header_file, "#define bif_lxvrse_bit\t\t(0x00080000)\n"); fprintf (header_file, "#define bif_lxvrze_bit\t\t(0x00100000)\n"); fprintf (header_file, "#define bif_endian_bit\t\t(0x00200000)\n"); + fprintf (header_file, "#define bif_ibmld_bit\t\t(0x00400000)\n"); fprintf (header_file, "\n"); fprintf (header_file, "#define bif_is_init(x)\t\t((x).bifattrs & bif_init_bit)\n"); @@ -2334,6 +2339,8 @@ write_decls (void) "#define bif_is_lxvrze(x)\t((x).bifattrs & bif_lxvrze_bit)\n"); fprintf (header_file, "#define bif_is_endian(x)\t((x).bifattrs & bif_endian_bit)\n"); + fprintf (header_file, + "#define bif_is_ibmld(x)\t((x).bifattrs & bif_ibmld_bit)\n"); fprintf (header_file, "\n"); /* #### Note that the _x is added for now to avoid conflict with @@ -2568,6 +2575,8 @@ write_bif_static_init (void) fprintf (init_file, " | bif_lxvrze_bit"); if (bifp->attrs.isendian) fprintf (init_file, " | bif_endian_bit"); + if (bifp->attrs.isibmld) + fprintf (init_file, " | bif_ibmld_bit"); fprintf (init_file, ",\n"); fprintf (init_file, " /* restr_opnd */\t{%d, %d, %d},\n", bifp->proto.restr_opnd[0], bifp->proto.restr_opnd[1], -- cgit v1.1 From 936051f9241ee2eafae8f5b8a4ad99fd7ed693bc Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Mon, 13 Dec 2021 09:30:18 -0600 Subject: rs6000: Builtins for doubleword compare should be in [power8-vector] (PR103625) 2021-12-13 Bill Schmidt gcc/ PR target/103625 * config/rs6000/rs6000-builtin-new.def (__builtin_altivec_vcmpequd): Move to power8-vector stanza. (__builtin_altivec_vcmpequd_p): Likewise. (__builtin_altivec_vcmpgtsd): Likewise. (__builtin_altivec_vcmpgtsd_p): Likewise. (__builtin_altivec_vcmpgtud): Likewise. (__builtin_altivec_vcmpgtud_p): Likewise. --- gcc/config/rs6000/rs6000-builtin-new.def | 36 ++++++++++++++++---------------- 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def index f7f5d2c..45ce160 100644 --- a/gcc/config/rs6000/rs6000-builtin-new.def +++ b/gcc/config/rs6000/rs6000-builtin-new.def @@ -1204,24 +1204,6 @@ const vull __builtin_altivec_vandc_v2di_uns (vull, vull); VANDC_V2DI_UNS andcv2di3 {} - const vsll __builtin_altivec_vcmpequd (vull, vull); - VCMPEQUD vector_eqv2di {} - - const int __builtin_altivec_vcmpequd_p (int, vsll, vsll); - VCMPEQUD_P vector_eq_v2di_p {pred} - - const vsll __builtin_altivec_vcmpgtsd (vsll, vsll); - VCMPGTSD vector_gtv2di {} - - const int __builtin_altivec_vcmpgtsd_p (int, vsll, vsll); - VCMPGTSD_P vector_gt_v2di_p {pred} - - const vsll __builtin_altivec_vcmpgtud (vull, vull); - VCMPGTUD vector_gtuv2di {} - - const int __builtin_altivec_vcmpgtud_p (int, vsll, vsll); - VCMPGTUD_P vector_gtu_v2di_p {pred} - const vd __builtin_altivec_vnor_v2df (vd, vd); VNOR_V2DF norv2df3 {} @@ -2225,6 +2207,24 @@ const vsc __builtin_altivec_vbpermq2 (vsc, vsc); VBPERMQ2 altivec_vbpermq2 {} + const vsll __builtin_altivec_vcmpequd (vull, vull); + VCMPEQUD vector_eqv2di {} + + const int __builtin_altivec_vcmpequd_p (int, vsll, vsll); + VCMPEQUD_P vector_eq_v2di_p {pred} + + const vsll __builtin_altivec_vcmpgtsd (vsll, vsll); + VCMPGTSD vector_gtv2di {} + + const int __builtin_altivec_vcmpgtsd_p (int, vsll, vsll); + VCMPGTSD_P vector_gt_v2di_p {pred} + + const vsll __builtin_altivec_vcmpgtud (vull, vull); + VCMPGTUD vector_gtuv2di {} + + const int __builtin_altivec_vcmpgtud_p (int, vsll, vsll); + VCMPGTUD_P vector_gtu_v2di_p {pred} + const vsll __builtin_altivec_vmaxsd (vsll, vsll); VMAXSD smaxv2di3 {} -- cgit v1.1 From 2cf62ef5aa80e3659a8150a48d93a1d333f1d292 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 14 Dec 2021 11:23:32 -0600 Subject: rs6000: Remove new_builtins_are_live and dead code it was guarding To allow for a sane switch-over from the old built-in infrastructure to the new, both sets of code have co-existed, with the enabled one under the control of the boolean variable new_builtins_are_live. As a first step in removing the old code, remove this variable and the now-dead code it was guarding. 2021-12-06 Bill Schmidt gcc/ * config/rs6000/darwin.h (SUBTARGET_INIT_BUILTINS): Remove test for new_builtins_are_live and simplify. * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Remove dead function. (altivec_resolve_overloaded_builtin): Remove test for new_builtins_are_live and simplify. * config/rs6000/rs6000-call.c (altivec_init_builtins): Remove forward declaration. (builtin_function_type): Likewise. (rs6000_common_init_builtins): Likewise. (htm_init_builtins): Likewise. (mma_init_builtins): Likewise. (def_builtin): Remove dead function. (rs6000_expand_zeroop_builtin): Likewise. (rs6000_expand_mtfsf_builtin): Likewise. (rs6000_expand_mtfsb_builtin): Likewise. (rs6000_expand_set_fpscr_rn_builtin): Likewise. (rs6000_expand_set_fpscr_drn_builtin): Likewise. (rs6000_expand_unop_builtin): Likewise. (altivec_expand_abs_builtin): Likewise. (rs6000_expand_binop_builtin): Likewise. (altivec_expand_lxvr_builtin): Likewise. (altivec_expand_lv_builtin): Likewise. (altivec_expand_stxvl_builtin): Likewise. (altivec_expand_stv_builtin): Likewise. (mma_expand_builtin): Likewise. (htm_expand_builtin): Likewise. (cpu_expand_builtin): Likewise. (rs6000_expand_quaternop_builtin): Likewise. (rs6000_expand_ternop_builtin): Likewise. (altivec_expand_dst_builtin): Likewise. (altivec_expand_vec_sel_builtin): Likewise. (altivec_expand_builtin): Likewise. (rs6000_invalid_builtin): Likewise. (rs6000_builtin_valid_without_lhs): Likewise. (rs6000_gimple_fold_builtin): Remove test for new_builtins_are_live and simplify. (rs6000_expand_builtin): Likewise. (rs6000_init_builtins): Remove tests for new_builtins_are_live and simplify. (rs6000_builtin_decl): Likewise. (altivec_init_builtins): Remove dead function. (mma_init_builtins): Likewise. (htm_init_builtins): Likewise. (builtin_quaternary_function_type): Likewise. (builtin_function_type): Likewise. (rs6000_common_init_builtins): Likewise. * config/rs6000/rs6000-gen-builtins.c (write_header_file): Don't declare new_builtins_are_live. (write_init_bif_table): In generated code, remove test for new_builtins_are_live and simplify. (write_init_ovld_table): Likewise. (write_init_file): Don't initialize new_builtins_are_live. * config/rs6000/rs6000.c (rs6000_builtin_vectorized_function): Remove test for new_builtins_are_live and simplify. (rs6000_builtin_md_vectorized_function): Likewise. (rs6000_builtin_reciprocal): Likewise. (add_condition_to_bb): Likewise. (rs6000_atomic_assign_expand_fenv): Likewise. --- gcc/config/rs6000/darwin.h | 8 +- gcc/config/rs6000/rs6000-c.c | 1084 +-- gcc/config/rs6000/rs6000-call.c | 11523 ++++++++---------------------- gcc/config/rs6000/rs6000-gen-builtins.c | 87 +- gcc/config/rs6000/rs6000.c | 256 +- 5 files changed, 3208 insertions(+), 9750 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 120b01f..7bc1009 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -507,12 +507,8 @@ #define SUBTARGET_INIT_BUILTINS \ do { \ darwin_patch_builtins (); \ - if (new_builtins_are_live) \ - rs6000_builtin_decls_x[(unsigned) (RS6000_BIF_CFSTRING)] \ - = darwin_init_cfstring_builtins ((unsigned) (RS6000_BIF_CFSTRING)); \ - else \ - rs6000_builtin_decls[(unsigned) (RS6000_BUILTIN_CFSTRING)] \ - = darwin_init_cfstring_builtins ((unsigned) (RS6000_BUILTIN_CFSTRING)); \ + rs6000_builtin_decls_x[(unsigned) (RS6000_BIF_CFSTRING)] \ + = darwin_init_cfstring_builtins ((unsigned) (RS6000_BIF_CFSTRING)); \ } while(0) /* So far, there is no rs6000_fold_builtin, if one is introduced, then diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 8e83d97..d44edf5 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -873,82 +873,6 @@ fully_fold_convert (tree type, tree expr) return result; } -/* Build a tree for a function call to an Altivec non-overloaded builtin. - The overloaded builtin that matched the types and args is described - by DESC. The N arguments are given in ARGS, respectively. - - Actually the only thing it does is calling fold_convert on ARGS, with - a small exception for vec_{all,any}_{ge,le} predicates. */ - -static tree -altivec_build_resolved_builtin (tree *args, int n, - const struct altivec_builtin_types *desc) -{ - tree impl_fndecl = rs6000_builtin_decls[desc->overloaded_code]; - tree ret_type = rs6000_builtin_type (desc->ret_type); - tree argtypes = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl)); - tree arg_type[4]; - tree call; - - int i; - for (i = 0; i < n; i++) - arg_type[i] = TREE_VALUE (argtypes), argtypes = TREE_CHAIN (argtypes); - - /* The AltiVec overloading implementation is overall gross, but this - is particularly disgusting. The vec_{all,any}_{ge,le} builtins - are completely different for floating-point vs. integer vector - types, because the former has vcmpgefp, but the latter should use - vcmpgtXX. - - In practice, the second and third arguments are swapped, and the - condition (LT vs. EQ, which is recognizable by bit 1 of the first - argument) is reversed. Patch the arguments here before building - the resolved CALL_EXPR. */ - if (n == 3 - && desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P - && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P - && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P) - { - std::swap (args[1], args[2]); - std::swap (arg_type[1], arg_type[2]); - - args[0] = fold_build2 (BIT_XOR_EXPR, TREE_TYPE (args[0]), args[0], - build_int_cst (NULL_TREE, 2)); - } - - switch (n) - { - case 0: - call = build_call_expr (impl_fndecl, 0); - break; - case 1: - call = build_call_expr (impl_fndecl, 1, - fully_fold_convert (arg_type[0], args[0])); - break; - case 2: - call = build_call_expr (impl_fndecl, 2, - fully_fold_convert (arg_type[0], args[0]), - fully_fold_convert (arg_type[1], args[1])); - break; - case 3: - call = build_call_expr (impl_fndecl, 3, - fully_fold_convert (arg_type[0], args[0]), - fully_fold_convert (arg_type[1], args[1]), - fully_fold_convert (arg_type[2], args[2])); - break; - case 4: - call = build_call_expr (impl_fndecl, 4, - fully_fold_convert (arg_type[0], args[0]), - fully_fold_convert (arg_type[1], args[1]), - fully_fold_convert (arg_type[2], args[2]), - fully_fold_convert (arg_type[3], args[3])); - break; - default: - gcc_unreachable (); - } - return fold_convert (ret_type, call); -} - /* Implementation of the resolve_overloaded_builtin target hook, to support Altivec's overloaded builtins. */ @@ -956,1013 +880,7 @@ tree altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, void *passed_arglist) { - if (new_builtins_are_live) - return altivec_resolve_new_overloaded_builtin (loc, fndecl, - passed_arglist); - - vec *arglist = static_cast *> (passed_arglist); - unsigned int nargs = vec_safe_length (arglist); - enum rs6000_builtins fcode - = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); - tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl)); - tree types[4], args[4]; - const struct altivec_builtin_types *desc; - unsigned int n; - - if (!rs6000_overloaded_builtin_p (fcode)) - return NULL_TREE; - - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n", - (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl))); - - /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */ - if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !BYTES_BIG_ENDIAN) - warning (OPT_Wdeprecated, - "% is deprecated for little endian; use " - "assignment for unaligned loads and stores"); - else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !BYTES_BIG_ENDIAN) - warning (OPT_Wdeprecated, - "% is deprecated for little endian; use " - "assignment for unaligned loads and stores"); - - if (fcode == ALTIVEC_BUILTIN_VEC_MUL) - { - /* vec_mul needs to be special cased because there are no instructions - for it for the {un}signed char, {un}signed short, and {un}signed int - types. */ - if (nargs != 2) - { - error ("builtin %qs only accepts 2 arguments", "vec_mul"); - return error_mark_node; - } - - tree arg0 = (*arglist)[0]; - tree arg0_type = TREE_TYPE (arg0); - tree arg1 = (*arglist)[1]; - tree arg1_type = TREE_TYPE (arg1); - - /* Both arguments must be vectors and the types must be compatible. */ - if (TREE_CODE (arg0_type) != VECTOR_TYPE) - goto bad; - if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)) - goto bad; - - switch (TYPE_MODE (TREE_TYPE (arg0_type))) - { - case E_QImode: - case E_HImode: - case E_SImode: - case E_DImode: - case E_TImode: - { - /* For scalar types just use a multiply expression. */ - return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0), arg0, - fold_convert (TREE_TYPE (arg0), arg1)); - } - case E_SFmode: - { - /* For floats use the xvmulsp instruction directly. */ - tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP]; - return build_call_expr (call, 2, arg0, arg1); - } - case E_DFmode: - { - /* For doubles use the xvmuldp instruction directly. */ - tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP]; - return build_call_expr (call, 2, arg0, arg1); - } - /* Other types are errors. */ - default: - goto bad; - } - } - - if (fcode == ALTIVEC_BUILTIN_VEC_CMPNE) - { - /* vec_cmpne needs to be special cased because there are no instructions - for it (prior to power 9). */ - if (nargs != 2) - { - error ("builtin %qs only accepts 2 arguments", "vec_cmpne"); - return error_mark_node; - } - - tree arg0 = (*arglist)[0]; - tree arg0_type = TREE_TYPE (arg0); - tree arg1 = (*arglist)[1]; - tree arg1_type = TREE_TYPE (arg1); - - /* Both arguments must be vectors and the types must be compatible. */ - if (TREE_CODE (arg0_type) != VECTOR_TYPE) - goto bad; - if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)) - goto bad; - - /* Power9 instructions provide the most efficient implementation of - ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode - or SFmode or DFmode. */ - if (!TARGET_P9_VECTOR - || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode) - || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode) - || (TYPE_MODE (TREE_TYPE (arg0_type)) == SFmode) - || (TYPE_MODE (TREE_TYPE (arg0_type)) == DFmode)) - { - switch (TYPE_MODE (TREE_TYPE (arg0_type))) - { - /* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb), - vec_cmpeq (va, vb)). */ - /* Note: vec_nand also works but opt changes vec_nand's - to vec_nor's anyway. */ - case E_QImode: - case E_HImode: - case E_SImode: - case E_DImode: - case E_TImode: - case E_SFmode: - case E_DFmode: - { - /* call = vec_cmpeq (va, vb) - result = vec_nor (call, call). */ - vec *params = make_tree_vector (); - vec_safe_push (params, arg0); - vec_safe_push (params, arg1); - tree call = altivec_resolve_overloaded_builtin - (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ], - params); - /* Use save_expr to ensure that operands used more than once - that may have side effects (like calls) are only evaluated - once. */ - call = save_expr (call); - params = make_tree_vector (); - vec_safe_push (params, call); - vec_safe_push (params, call); - return altivec_resolve_overloaded_builtin - (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params); - } - /* Other types are errors. */ - default: - goto bad; - } - } - /* else, fall through and process the Power9 alternative below */ - } - - if (fcode == ALTIVEC_BUILTIN_VEC_ADDE - || fcode == ALTIVEC_BUILTIN_VEC_SUBE) - { - /* vec_adde needs to be special cased because there is no instruction - for the {un}signed int version. */ - if (nargs != 3) - { - const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDE ? - "vec_adde": "vec_sube"; - error ("builtin %qs only accepts 3 arguments", name); - return error_mark_node; - } - - tree arg0 = (*arglist)[0]; - tree arg0_type = TREE_TYPE (arg0); - tree arg1 = (*arglist)[1]; - tree arg1_type = TREE_TYPE (arg1); - tree arg2 = (*arglist)[2]; - tree arg2_type = TREE_TYPE (arg2); - - /* All 3 arguments must be vectors of (signed or unsigned) (int or - __int128) and the types must be compatible. */ - if (TREE_CODE (arg0_type) != VECTOR_TYPE) - goto bad; - if (!lang_hooks.types_compatible_p (arg0_type, arg1_type) - || !lang_hooks.types_compatible_p (arg1_type, arg2_type)) - goto bad; - - switch (TYPE_MODE (TREE_TYPE (arg0_type))) - { - /* For {un}signed ints, - vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb), - vec_and (carryv, 1)). - vec_sube (va, vb, carryv) == vec_sub (vec_sub (va, vb), - vec_and (carryv, 1)). */ - case E_SImode: - { - tree add_sub_builtin; - - vec *params = make_tree_vector (); - vec_safe_push (params, arg0); - vec_safe_push (params, arg1); - - if (fcode == ALTIVEC_BUILTIN_VEC_ADDE) - add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD]; - else - add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB]; - - tree call = altivec_resolve_overloaded_builtin (loc, - add_sub_builtin, - params); - tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1); - tree ones_vector = build_vector_from_val (arg0_type, const1); - tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type, - arg2, ones_vector); - params = make_tree_vector (); - vec_safe_push (params, call); - vec_safe_push (params, and_expr); - return altivec_resolve_overloaded_builtin (loc, add_sub_builtin, - params); - } - /* For {un}signed __int128s use the vaddeuqm instruction - directly. */ - case E_TImode: - { - tree bii; - - if (fcode == ALTIVEC_BUILTIN_VEC_ADDE) - bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDEUQM]; - - else - bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBEUQM]; - - return altivec_resolve_overloaded_builtin (loc, bii, arglist); - } - - /* Types other than {un}signed int and {un}signed __int128 - are errors. */ - default: - goto bad; - } - } - - if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC - || fcode == ALTIVEC_BUILTIN_VEC_SUBEC) - { - /* vec_addec and vec_subec needs to be special cased because there is - no instruction for the {un}signed int version. */ - if (nargs != 3) - { - const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDEC ? - "vec_addec": "vec_subec"; - error ("builtin %qs only accepts 3 arguments", name); - return error_mark_node; - } - - tree arg0 = (*arglist)[0]; - tree arg0_type = TREE_TYPE (arg0); - tree arg1 = (*arglist)[1]; - tree arg1_type = TREE_TYPE (arg1); - tree arg2 = (*arglist)[2]; - tree arg2_type = TREE_TYPE (arg2); - - /* All 3 arguments must be vectors of (signed or unsigned) (int or - __int128) and the types must be compatible. */ - if (TREE_CODE (arg0_type) != VECTOR_TYPE) - goto bad; - if (!lang_hooks.types_compatible_p (arg0_type, arg1_type) - || !lang_hooks.types_compatible_p (arg1_type, arg2_type)) - goto bad; - - switch (TYPE_MODE (TREE_TYPE (arg0_type))) - { - /* For {un}signed ints, - vec_addec (va, vb, carryv) == - vec_or (vec_addc (va, vb), - vec_addc (vec_add (va, vb), - vec_and (carryv, 0x1))). */ - case E_SImode: - { - /* Use save_expr to ensure that operands used more than once - that may have side effects (like calls) are only evaluated - once. */ - tree as_builtin; - tree as_c_builtin; - - arg0 = save_expr (arg0); - arg1 = save_expr (arg1); - vec *params = make_tree_vector (); - vec_safe_push (params, arg0); - vec_safe_push (params, arg1); - - if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC) - as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADDC]; - else - as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUBC]; - - tree call1 = altivec_resolve_overloaded_builtin (loc, as_c_builtin, - params); - params = make_tree_vector (); - vec_safe_push (params, arg0); - vec_safe_push (params, arg1); - - - if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC) - as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD]; - else - as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB]; - - tree call2 = altivec_resolve_overloaded_builtin (loc, as_builtin, - params); - tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1); - tree ones_vector = build_vector_from_val (arg0_type, const1); - tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type, - arg2, ones_vector); - params = make_tree_vector (); - vec_safe_push (params, call2); - vec_safe_push (params, and_expr); - call2 = altivec_resolve_overloaded_builtin (loc, as_c_builtin, - params); - params = make_tree_vector (); - vec_safe_push (params, call1); - vec_safe_push (params, call2); - tree or_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_OR]; - return altivec_resolve_overloaded_builtin (loc, or_builtin, - params); - } - /* For {un}signed __int128s use the vaddecuq/vsubbecuq - instructions. */ - case E_TImode: - { - tree bii; - - if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC) - bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDECUQ]; - - else - bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBECUQ]; - - return altivec_resolve_overloaded_builtin (loc, bii, arglist); - } - /* Types other than {un}signed int and {un}signed __int128 - are errors. */ - default: - goto bad; - } - } - - /* For now treat vec_splats and vec_promote as the same. */ - if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS - || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE) - { - tree type, arg; - int size; - int i; - bool unsigned_p; - vec *vec; - const char *name = fcode == ALTIVEC_BUILTIN_VEC_SPLATS ? "vec_splats": "vec_promote"; - - if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS && nargs != 1) - { - error ("builtin %qs only accepts 1 argument", name); - return error_mark_node; - } - if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE && nargs != 2) - { - error ("builtin %qs only accepts 2 arguments", name); - return error_mark_node; - } - /* Ignore promote's element argument. */ - if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE - && !INTEGRAL_TYPE_P (TREE_TYPE ((*arglist)[1]))) - goto bad; - - arg = (*arglist)[0]; - type = TREE_TYPE (arg); - if (!SCALAR_FLOAT_TYPE_P (type) - && !INTEGRAL_TYPE_P (type)) - goto bad; - unsigned_p = TYPE_UNSIGNED (type); - switch (TYPE_MODE (type)) - { - case E_TImode: - type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node); - size = 1; - break; - case E_DImode: - type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node); - size = 2; - break; - case E_SImode: - type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); - size = 4; - break; - case E_HImode: - type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); - size = 8; - break; - case E_QImode: - type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); - size = 16; - break; - case E_SFmode: type = V4SF_type_node; size = 4; break; - case E_DFmode: type = V2DF_type_node; size = 2; break; - default: - goto bad; - } - arg = save_expr (fold_convert (TREE_TYPE (type), arg)); - vec_alloc (vec, size); - for(i = 0; i < size; i++) - { - constructor_elt elt = {NULL_TREE, arg}; - vec->quick_push (elt); - } - return build_constructor (type, vec); - } - - /* For now use pointer tricks to do the extraction, unless we are on VSX - extracting a double from a constant offset. */ - if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT) - { - tree arg1; - tree arg1_type; - tree arg2; - tree arg1_inner_type; - tree decl, stmt; - tree innerptrtype; - machine_mode mode; - - /* No second argument. */ - if (nargs != 2) - { - error ("builtin %qs only accepts 2 arguments", "vec_extract"); - return error_mark_node; - } - - arg2 = (*arglist)[1]; - arg1 = (*arglist)[0]; - arg1_type = TREE_TYPE (arg1); - - if (TREE_CODE (arg1_type) != VECTOR_TYPE) - goto bad; - if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) - goto bad; - - /* See if we can optimize vec_extracts with the current VSX instruction - set. */ - mode = TYPE_MODE (arg1_type); - if (VECTOR_MEM_VSX_P (mode)) - - { - tree call = NULL_TREE; - int nunits = GET_MODE_NUNITS (mode); - - arg2 = fold_for_warn (arg2); - - /* If the second argument is an integer constant, generate - the built-in code if we can. We need 64-bit and direct - move to extract the small integer vectors. */ - if (TREE_CODE (arg2) == INTEGER_CST) - { - wide_int selector = wi::to_wide (arg2); - selector = wi::umod_trunc (selector, nunits); - arg2 = wide_int_to_tree (TREE_TYPE (arg2), selector); - switch (mode) - { - default: - break; - - case E_V1TImode: - call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI]; - break; - - case E_V2DFmode: - call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF]; - break; - - case E_V2DImode: - call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI]; - break; - - case E_V4SFmode: - call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF]; - break; - - case E_V4SImode: - if (TARGET_DIRECT_MOVE_64BIT) - call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI]; - break; - - case E_V8HImode: - if (TARGET_DIRECT_MOVE_64BIT) - call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI]; - break; - - case E_V16QImode: - if (TARGET_DIRECT_MOVE_64BIT) - call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI]; - break; - } - } - - /* If the second argument is variable, we can optimize it if we are - generating 64-bit code on a machine with direct move. */ - else if (TREE_CODE (arg2) != INTEGER_CST && TARGET_DIRECT_MOVE_64BIT) - { - switch (mode) - { - default: - break; - - case E_V2DFmode: - call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF]; - break; - - case E_V2DImode: - call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI]; - break; - - case E_V4SFmode: - call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF]; - break; - - case E_V4SImode: - call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI]; - break; - - case E_V8HImode: - call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI]; - break; - - case E_V16QImode: - call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI]; - break; - } - } - - if (call) - { - tree result = build_call_expr (call, 2, arg1, arg2); - /* Coerce the result to vector element type. May be no-op. */ - arg1_inner_type = TREE_TYPE (arg1_type); - result = fold_convert (arg1_inner_type, result); - return result; - } - } - - /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */ - arg1_inner_type = TREE_TYPE (arg1_type); - arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2, - build_int_cst (TREE_TYPE (arg2), - TYPE_VECTOR_SUBPARTS (arg1_type) - - 1), 0); - decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type); - DECL_EXTERNAL (decl) = 0; - TREE_PUBLIC (decl) = 0; - DECL_CONTEXT (decl) = current_function_decl; - TREE_USED (decl) = 1; - TREE_TYPE (decl) = arg1_type; - TREE_READONLY (decl) = TYPE_READONLY (arg1_type); - if (c_dialect_cxx ()) - { - stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1, - NULL_TREE, NULL_TREE); - SET_EXPR_LOCATION (stmt, loc); - } - else - { - DECL_INITIAL (decl) = arg1; - stmt = build1 (DECL_EXPR, arg1_type, decl); - TREE_ADDRESSABLE (decl) = 1; - SET_EXPR_LOCATION (stmt, loc); - stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt); - } - - innerptrtype = build_pointer_type (arg1_inner_type); - - stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0); - stmt = convert (innerptrtype, stmt); - stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); - stmt = build_indirect_ref (loc, stmt, RO_NULL); - - /* PR83660: We mark this as having side effects so that - downstream in fold_build_cleanup_point_expr () it will get a - CLEANUP_POINT_EXPR. If it does not we can run into an ICE - later in gimplify_cleanup_point_expr (). Potentially this - causes missed optimization because the actually is no side - effect. */ - if (c_dialect_cxx ()) - TREE_SIDE_EFFECTS (stmt) = 1; - - return stmt; - } - - /* For now use pointer tricks to do the insertion, unless we are on VSX - inserting a double to a constant offset.. */ - if (fcode == ALTIVEC_BUILTIN_VEC_INSERT) - { - tree arg0; - tree arg1; - tree arg2; - tree arg1_type; - tree decl, stmt; - machine_mode mode; - - /* No second or third arguments. */ - if (nargs != 3) - { - error ("builtin %qs only accepts 3 arguments", "vec_insert"); - return error_mark_node; - } - - arg0 = (*arglist)[0]; - arg1 = (*arglist)[1]; - arg1_type = TREE_TYPE (arg1); - arg2 = fold_for_warn ((*arglist)[2]); - - if (TREE_CODE (arg1_type) != VECTOR_TYPE) - goto bad; - if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) - goto bad; - - /* If we can use the VSX xxpermdi instruction, use that for insert. */ - mode = TYPE_MODE (arg1_type); - if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode) - && TREE_CODE (arg2) == INTEGER_CST) - { - wide_int selector = wi::to_wide (arg2); - selector = wi::umod_trunc (selector, 2); - tree call = NULL_TREE; - - arg2 = wide_int_to_tree (TREE_TYPE (arg2), selector); - if (mode == V2DFmode) - call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DF]; - else if (mode == V2DImode) - call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DI]; - - /* Note, __builtin_vec_insert_ has vector and scalar types - reversed. */ - if (call) - return build_call_expr (call, 3, arg1, arg0, arg2); - } - else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode) - && TREE_CODE (arg2) == INTEGER_CST) - { - tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI]; - wide_int selector = wi::zero(32); - - arg2 = wide_int_to_tree (TREE_TYPE (arg2), selector); - /* Note, __builtin_vec_insert_ has vector and scalar types - reversed. */ - return build_call_expr (call, 3, arg1, arg0, arg2); - } - - /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0 with - VIEW_CONVERT_EXPR. i.e.: - D.3192 = v1; - _1 = n & 3; - VIEW_CONVERT_EXPR(D.3192)[_1] = i; - v1 = D.3192; - D.3194 = v1; */ - if (TYPE_VECTOR_SUBPARTS (arg1_type) == 1) - arg2 = build_int_cst (TREE_TYPE (arg2), 0); - else - arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2, - build_int_cst (TREE_TYPE (arg2), - TYPE_VECTOR_SUBPARTS (arg1_type) - - 1), 0); - decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type); - DECL_EXTERNAL (decl) = 0; - TREE_PUBLIC (decl) = 0; - DECL_CONTEXT (decl) = current_function_decl; - TREE_USED (decl) = 1; - TREE_TYPE (decl) = arg1_type; - TREE_READONLY (decl) = TYPE_READONLY (arg1_type); - TREE_ADDRESSABLE (decl) = 1; - if (c_dialect_cxx ()) - { - stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1, - NULL_TREE, NULL_TREE); - SET_EXPR_LOCATION (stmt, loc); - } - else - { - DECL_INITIAL (decl) = arg1; - stmt = build1 (DECL_EXPR, arg1_type, decl); - SET_EXPR_LOCATION (stmt, loc); - stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt); - } - - if (TARGET_VSX) - { - stmt = build_array_ref (loc, stmt, arg2); - stmt = fold_build2 (MODIFY_EXPR, TREE_TYPE (arg0), stmt, - convert (TREE_TYPE (stmt), arg0)); - stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl); - } - else - { - tree arg1_inner_type; - tree innerptrtype; - arg1_inner_type = TREE_TYPE (arg1_type); - innerptrtype = build_pointer_type (arg1_inner_type); - - stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0); - stmt = convert (innerptrtype, stmt); - stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); - stmt = build_indirect_ref (loc, stmt, RO_NULL); - stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt, - convert (TREE_TYPE (stmt), arg0)); - stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl); - } - return stmt; - } - - for (n = 0; - !VOID_TYPE_P (TREE_VALUE (fnargs)) && n < nargs; - fnargs = TREE_CHAIN (fnargs), n++) - { - tree decl_type = TREE_VALUE (fnargs); - tree arg = (*arglist)[n]; - tree type; - - if (arg == error_mark_node) - return error_mark_node; - - if (n >= 4) - abort (); - - arg = default_conversion (arg); - - /* The C++ front-end converts float * to const void * using - NOP_EXPR (NOP_EXPR (x)). */ - type = TREE_TYPE (arg); - if (POINTER_TYPE_P (type) - && TREE_CODE (arg) == NOP_EXPR - && lang_hooks.types_compatible_p (TREE_TYPE (arg), - const_ptr_type_node) - && lang_hooks.types_compatible_p (TREE_TYPE (TREE_OPERAND (arg, 0)), - ptr_type_node)) - { - arg = TREE_OPERAND (arg, 0); - type = TREE_TYPE (arg); - } - - /* Remove the const from the pointers to simplify the overload - matching further down. */ - if (POINTER_TYPE_P (decl_type) - && POINTER_TYPE_P (type) - && TYPE_QUALS (TREE_TYPE (type)) != 0) - { - if (TYPE_READONLY (TREE_TYPE (type)) - && !TYPE_READONLY (TREE_TYPE (decl_type))) - warning (0, "passing argument %d of %qE discards qualifiers from " - "pointer target type", n + 1, fndecl); - type = build_pointer_type (build_qualified_type (TREE_TYPE (type), - 0)); - arg = fold_convert (type, arg); - } - - /* For P9V_BUILTIN_VEC_LXVL, convert any const * to its non constant - equivalent to simplify the overload matching below. */ - if (fcode == P9V_BUILTIN_VEC_LXVL) - { - if (POINTER_TYPE_P (type) - && TYPE_READONLY (TREE_TYPE (type))) - { - type = build_pointer_type (build_qualified_type ( - TREE_TYPE (type),0)); - arg = fold_convert (type, arg); - } - } - - args[n] = arg; - types[n] = type; - } - - /* If the number of arguments did not match the prototype, return NULL - and the generic code will issue the appropriate error message. */ - if (!VOID_TYPE_P (TREE_VALUE (fnargs)) || n < nargs) - return NULL; - - if (n == 0) - abort (); - - if (fcode == ALTIVEC_BUILTIN_VEC_STEP) - { - if (TREE_CODE (types[0]) != VECTOR_TYPE) - goto bad; - - return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0])); - } - - { - bool unsupported_builtin = false; - enum rs6000_builtins overloaded_code; - tree result = NULL; - for (desc = altivec_overloaded_builtins; - desc->code && desc->code != fcode; desc++) - continue; - - /* Need to special case __builtin_cmp because the overloaded forms - of this function take (unsigned int, unsigned int) or (unsigned - long long int, unsigned long long int). Since C conventions - allow the respective argument types to be implicitly coerced into - each other, the default handling does not provide adequate - discrimination between the desired forms of the function. */ - if (fcode == P6_OV_BUILTIN_CMPB) - { - machine_mode arg1_mode = TYPE_MODE (types[0]); - machine_mode arg2_mode = TYPE_MODE (types[1]); - - if (nargs != 2) - { - error ("builtin %qs only accepts 2 arguments", "__builtin_cmpb"); - return error_mark_node; - } - - /* If any supplied arguments are wider than 32 bits, resolve to - 64-bit variant of built-in function. */ - if ((GET_MODE_PRECISION (arg1_mode) > 32) - || (GET_MODE_PRECISION (arg2_mode) > 32)) - { - /* Assure all argument and result types are compatible with - the built-in function represented by P6_BUILTIN_CMPB. */ - overloaded_code = P6_BUILTIN_CMPB; - } - else - { - /* Assure all argument and result types are compatible with - the built-in function represented by P6_BUILTIN_CMPB_32. */ - overloaded_code = P6_BUILTIN_CMPB_32; - } - - while (desc->code && desc->code == fcode - && desc->overloaded_code != overloaded_code) - desc++; - - if (desc->code && (desc->code == fcode) - && rs6000_builtin_type_compatible (types[0], desc->op1) - && rs6000_builtin_type_compatible (types[1], desc->op2)) - { - if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) - { - result = altivec_build_resolved_builtin (args, n, desc); - /* overloaded_code is set above */ - if (!rs6000_builtin_is_supported_p (overloaded_code)) - unsupported_builtin = true; - else - return result; - } - else - unsupported_builtin = true; - } - } - else if (fcode == P9V_BUILTIN_VEC_VSIEDP) - { - machine_mode arg1_mode = TYPE_MODE (types[0]); - - if (nargs != 2) - { - error ("builtin %qs only accepts 2 arguments", - "scalar_insert_exp"); - return error_mark_node; - } - - /* If supplied first argument is wider than 64 bits, resolve to - 128-bit variant of built-in function. */ - if (GET_MODE_PRECISION (arg1_mode) > 64) - { - /* If first argument is of float variety, choose variant - that expects __ieee128 argument. Otherwise, expect - __int128 argument. */ - if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT) - overloaded_code = P9V_BUILTIN_VSIEQPF; - else - overloaded_code = P9V_BUILTIN_VSIEQP; - } - else - { - /* If first argument is of float variety, choose variant - that expects double argument. Otherwise, expect - long long int argument. */ - if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT) - overloaded_code = P9V_BUILTIN_VSIEDPF; - else - overloaded_code = P9V_BUILTIN_VSIEDP; - } - while (desc->code && desc->code == fcode - && desc->overloaded_code != overloaded_code) - desc++; - - if (desc->code && (desc->code == fcode) - && rs6000_builtin_type_compatible (types[0], desc->op1) - && rs6000_builtin_type_compatible (types[1], desc->op2)) - { - if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) - { - result = altivec_build_resolved_builtin (args, n, desc); - /* overloaded_code is set above. */ - if (!rs6000_builtin_is_supported_p (overloaded_code)) - unsupported_builtin = true; - else - return result; - } - else - unsupported_builtin = true; - } - } - else if ((fcode == P10_BUILTIN_VEC_XXEVAL) - || (fcode == P10V_BUILTIN_VXXPERMX)) - { - signed char op3_type; - - /* Need to special case P10_BUILTIN_VEC_XXEVAL and - P10V_BUILTIN_VXXPERMX because they take 4 arguments and the - existing infrastructure only handles three. */ - if (nargs != 4) - { - const char *name = fcode == P10_BUILTIN_VEC_XXEVAL ? - "__builtin_vec_xxeval":"__builtin_vec_xxpermx"; - - error ("builtin %qs requires 4 arguments", name); - return error_mark_node; - } - - for ( ; desc->code == fcode; desc++) - { - if (fcode == P10_BUILTIN_VEC_XXEVAL) - op3_type = desc->op3; - else /* P10V_BUILTIN_VXXPERMX */ - op3_type = RS6000_BTI_V16QI; - - if (rs6000_builtin_type_compatible (types[0], desc->op1) - && rs6000_builtin_type_compatible (types[1], desc->op2) - && rs6000_builtin_type_compatible (types[2], desc->op3) - && rs6000_builtin_type_compatible (types[2], op3_type) - && rs6000_builtin_type_compatible (types[3], - RS6000_BTI_UINTSI)) - { - if (rs6000_builtin_decls[desc->overloaded_code] == NULL_TREE) - unsupported_builtin = true; - else - { - result = altivec_build_resolved_builtin (args, n, desc); - if (rs6000_builtin_is_supported_p (desc->overloaded_code)) - return result; - /* Allow loop to continue in case a different - definition is supported. */ - overloaded_code = desc->overloaded_code; - unsupported_builtin = true; - } - } - } - } - else - { - /* For arguments after the last, we have RS6000_BTI_NOT_OPAQUE in - the opX fields. */ - for (; desc->code == fcode; desc++) - { - if ((desc->op1 == RS6000_BTI_NOT_OPAQUE - || rs6000_builtin_type_compatible (types[0], desc->op1)) - && (desc->op2 == RS6000_BTI_NOT_OPAQUE - || rs6000_builtin_type_compatible (types[1], desc->op2)) - && (desc->op3 == RS6000_BTI_NOT_OPAQUE - || rs6000_builtin_type_compatible (types[2], desc->op3))) - { - if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) - { - result = altivec_build_resolved_builtin (args, n, desc); - if (!rs6000_builtin_is_supported_p (desc->overloaded_code)) - { - /* Allow loop to continue in case a different - definition is supported. */ - overloaded_code = desc->overloaded_code; - unsupported_builtin = true; - } - else - return result; - } - else - unsupported_builtin = true; - } - } - } - - if (unsupported_builtin) - { - const char *name = rs6000_overloaded_builtin_name (fcode); - if (result != NULL) - { - const char *internal_name - = rs6000_overloaded_builtin_name (overloaded_code); - /* An error message making reference to the name of the - non-overloaded function has already been issued. Add - clarification of the previous message. */ - rich_location richloc (line_table, input_location); - inform (&richloc, - "overloaded builtin %qs is implemented by builtin %qs", - name, internal_name); - } - else - error ("%qs is not supported in this compiler configuration", name); - /* If an error-representing result tree was returned from - altivec_build_resolved_builtin above, use it. */ - return (result != NULL) ? result : error_mark_node; - } - } - bad: - { - const char *name = rs6000_overloaded_builtin_name (fcode); - error ("invalid parameter combination for AltiVec intrinsic %qs", name); - return error_mark_node; - } + return altivec_resolve_new_overloaded_builtin (loc, fndecl, passed_arglist); } /* Build a tree for a function call to an Altivec non-overloaded builtin. diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 3a43a76..85aea9b 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -182,13 +182,6 @@ static const struct { "mma", PPC_FEATURE2_MMA, 1 }, }; -static void altivec_init_builtins (void); -static tree builtin_function_type (machine_mode, machine_mode, - machine_mode, machine_mode, - enum rs6000_builtins, const char *name); -static void rs6000_common_init_builtins (void); -static void htm_init_builtins (void); -static void mma_init_builtins (void); static rtx rs6000_expand_new_builtin (tree, rtx, rtx, machine_mode, int); static bool rs6000_gimple_fold_new_builtin (gimple_stmt_iterator *gsi); @@ -9029,89 +9022,6 @@ const char *rs6000_type_string (tree type_node) return "unknown"; } -static void -def_builtin (const char *name, tree type, enum rs6000_builtins code) -{ - tree t; - unsigned classify = rs6000_builtin_info[(int)code].attr; - const char *attr_string = ""; - - /* Don't define the builtin if it doesn't have a type. See PR92661. */ - if (type == NULL_TREE) - return; - - gcc_assert (name != NULL); - gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT)); - - if (rs6000_builtin_decls[(int)code]) - fatal_error (input_location, - "internal error: builtin function %qs already processed", - name); - - rs6000_builtin_decls[(int)code] = t = - add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE); - - /* Set any special attributes. */ - if ((classify & RS6000_BTC_CONST) != 0) - { - /* const function, function only depends on the inputs. */ - TREE_READONLY (t) = 1; - TREE_NOTHROW (t) = 1; - attr_string = "= const"; - } - else if ((classify & RS6000_BTC_PURE) != 0) - { - /* pure function, function can read global memory, but does not set any - external state. */ - DECL_PURE_P (t) = 1; - TREE_NOTHROW (t) = 1; - attr_string = "= pure"; - } - else if ((classify & RS6000_BTC_FP) != 0) - { - /* Function is a math function. If rounding mode is on, then treat the - function as not reading global memory, but it can have arbitrary side - effects. If it is off, then assume the function is a const function. - This mimics the ATTR_MATHFN_FPROUNDING attribute in - builtin-attribute.def that is used for the math functions. */ - TREE_NOTHROW (t) = 1; - if (flag_rounding_math) - { - DECL_PURE_P (t) = 1; - DECL_IS_NOVOPS (t) = 1; - attr_string = "= fp, pure"; - } - else - { - TREE_READONLY (t) = 1; - attr_string = "= fp, const"; - } - } - else if ((classify & (RS6000_BTC_QUAD | RS6000_BTC_PAIR)) != 0) - /* The function uses a register quad and/or pair. Nothing to do. */ - ; - else if ((classify & RS6000_BTC_ATTR_MASK) != 0) - gcc_unreachable (); - - if (TARGET_DEBUG_BUILTIN) - { - tree t = TREE_TYPE (type); - fprintf (stderr, "%s %s (", rs6000_type_string (t), name); - t = TYPE_ARG_TYPES (type); - gcc_assert (t); - - while (TREE_VALUE (t) != void_type_node) - { - fprintf (stderr, "%s", rs6000_type_string (TREE_VALUE (t))); - t = TREE_CHAIN (t); - gcc_assert (t); - if (TREE_VALUE (t) != void_type_node) - fprintf (stderr, ", "); - } - fprintf (stderr, "); %s [%4d]\n", attr_string, (int) code); - } -} - static const struct builtin_compatibility bdesc_compat[] = { #define RS6000_BUILTIN_COMPAT @@ -9473,8744 +9383,3631 @@ rs6000_overloaded_builtin_name (enum rs6000_builtins fncode) return rs6000_builtin_info[(int)fncode].name; } -/* Expand an expression EXP that calls a builtin without arguments. */ static rtx -rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target) +altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target) { - rtx pat; - machine_mode tmode = insn_data[icode].operand[0].mode; - - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; + rtx pat, scratch; + tree cr6_form = CALL_EXPR_ARG (exp, 0); + tree arg0 = CALL_EXPR_ARG (exp, 1); + tree arg1 = CALL_EXPR_ARG (exp, 2); + rtx op0 = expand_normal (arg0); + rtx op1 = expand_normal (arg1); + machine_mode tmode = SImode; + machine_mode mode0 = insn_data[icode].operand[1].mode; + machine_mode mode1 = insn_data[icode].operand[2].mode; + int cr6_form_int; - if (icode == CODE_FOR_rs6000_mffsl - && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT) + if (TREE_CODE (cr6_form) != INTEGER_CST) { - error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>"); + error ("argument 1 of %qs must be a constant", + "__builtin_altivec_predicate"); return const0_rtx; } + else + cr6_form_int = TREE_INT_CST_LOW (cr6_form); + + gcc_assert (mode0 == mode1); + + /* If we have invalid arguments, bail out before generating bad rtl. */ + if (arg0 == error_mark_node || arg1 == error_mark_node) + return const0_rtx; if (target == 0 || GET_MODE (target) != tmode || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target); + if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) + op1 = copy_to_mode_reg (mode1, op1); + + /* Note that for many of the relevant operations (e.g. cmpne or + cmpeq) with float or double operands, it makes more sense for the + mode of the allocated scratch register to select a vector of + integer. But the choice to copy the mode of operand 0 was made + long ago and there are no plans to change it. */ + scratch = gen_reg_rtx (mode0); + + pat = GEN_FCN (icode) (scratch, op0, op1); if (! pat) return 0; emit_insn (pat); - return target; -} - - -static rtx -rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp) -{ - rtx pat; - tree arg0 = CALL_EXPR_ARG (exp, 0); - tree arg1 = CALL_EXPR_ARG (exp, 1); - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - machine_mode mode0 = insn_data[icode].operand[0].mode; - machine_mode mode1 = insn_data[icode].operand[1].mode; - - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; + /* The vec_any* and vec_all* predicates use the same opcodes for two + different operations, but the bits in CR6 will be different + depending on what information we want. So we have to play tricks + with CR6 to get the right bits out. - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node || arg1 == error_mark_node) - return const0_rtx; + If you think this is disgusting, look at the specs for the + AltiVec predicates. */ - if (!CONST_INT_P (op0) - || INTVAL (op0) > 255 - || INTVAL (op0) < 0) + switch (cr6_form_int) { - error ("argument 1 must be an 8-bit field value"); - return const0_rtx; + case 0: + emit_insn (gen_cr6_test_for_zero (target)); + break; + case 1: + emit_insn (gen_cr6_test_for_zero_reverse (target)); + break; + case 2: + emit_insn (gen_cr6_test_for_lt (target)); + break; + case 3: + emit_insn (gen_cr6_test_for_lt_reverse (target)); + break; + default: + error ("argument 1 of %qs is out of range", + "__builtin_altivec_predicate"); + break; } - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - - pat = GEN_FCN (icode) (op0, op1); - if (!pat) - return const0_rtx; - emit_insn (pat); - - return NULL_RTX; + return target; } -static rtx -rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp) +rtx +swap_endian_selector_for_mode (machine_mode mode) { - rtx pat; - tree arg0 = CALL_EXPR_ARG (exp, 0); - rtx op0 = expand_normal (arg0); + unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0}; + unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8}; + unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12}; + unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14}; - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; + unsigned int *swaparray, i; + rtx perm[16]; - if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT) + switch (mode) { - error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with " - "%<-msoft-float%>"); - return const0_rtx; + case E_V1TImode: + swaparray = swap1; + break; + case E_V2DFmode: + case E_V2DImode: + swaparray = swap2; + break; + case E_V4SFmode: + case E_V4SImode: + swaparray = swap4; + break; + case E_V8HImode: + swaparray = swap8; + break; + default: + gcc_unreachable (); } - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node) - return const0_rtx; + for (i = 0; i < 16; ++i) + perm[i] = GEN_INT (swaparray[i]); - /* Only allow bit numbers 0 to 31. */ - if (!u5bit_cint_operand (op0, VOIDmode)) - { - error ("Argument must be a constant between 0 and 31."); - return const0_rtx; - } + return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, + gen_rtvec_v (16, perm))); +} - pat = GEN_FCN (icode) (op0); - if (!pat) - return const0_rtx; - emit_insn (pat); +/* Return the appropriate SPR number associated with the given builtin. */ +static inline HOST_WIDE_INT +htm_spr_num (enum rs6000_builtins code) +{ + if (code == HTM_BUILTIN_GET_TFHAR + || code == HTM_BUILTIN_SET_TFHAR) + return TFHAR_SPR; + else if (code == HTM_BUILTIN_GET_TFIAR + || code == HTM_BUILTIN_SET_TFIAR) + return TFIAR_SPR; + else if (code == HTM_BUILTIN_GET_TEXASR + || code == HTM_BUILTIN_SET_TEXASR) + return TEXASR_SPR; + gcc_assert (code == HTM_BUILTIN_GET_TEXASRU + || code == HTM_BUILTIN_SET_TEXASRU); + return TEXASRU_SPR; +} - return NULL_RTX; +/* Return the correct ICODE value depending on whether we are + setting or reading the HTM SPRs. */ +static inline enum insn_code +rs6000_htm_spr_icode (bool nonvoid) +{ + if (nonvoid) + return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si; + else + return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si; } +/* Expand vec_init builtin. */ static rtx -rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp) +altivec_expand_vec_init_builtin (tree type, tree exp, rtx target) { - rtx pat; - tree arg0 = CALL_EXPR_ARG (exp, 0); - rtx op0 = expand_normal (arg0); - machine_mode mode0 = insn_data[icode].operand[0].mode; + machine_mode tmode = TYPE_MODE (type); + machine_mode inner_mode = GET_MODE_INNER (tmode); + int i, n_elt = GET_MODE_NUNITS (tmode); - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; + gcc_assert (VECTOR_MODE_P (tmode)); + gcc_assert (n_elt == call_expr_nargs (exp)); + + if (!target || !register_operand (target, tmode)) + target = gen_reg_rtx (tmode); - if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT) + /* If we have a vector compromised of a single element, such as V1TImode, do + the initialization directly. */ + if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode)) { - error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>"); - return const0_rtx; + rtx x = expand_normal (CALL_EXPR_ARG (exp, 0)); + emit_move_insn (target, gen_lowpart (tmode, x)); } + else + { + rtvec v = rtvec_alloc (n_elt); - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node) - return const0_rtx; + for (i = 0; i < n_elt; ++i) + { + rtx x = expand_normal (CALL_EXPR_ARG (exp, i)); + RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x); + } - /* If the argument is a constant, check the range. Argument can only be a - 2-bit value. Unfortunately, can't check the range of the value at - compile time if the argument is a variable. The least significant two - bits of the argument, regardless of type, are used to set the rounding - mode. All other bits are ignored. */ - if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode)) - { - error ("Argument must be a value between 0 and 3."); - return const0_rtx; + rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v)); } - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); + return target; +} - pat = GEN_FCN (icode) (op0); - if (!pat) - return const0_rtx; - emit_insn (pat); +/* Return the integer constant in ARG. Constrain it to be in the range + of the subparts of VEC_TYPE; issue an error if not. */ - return NULL_RTX; -} -static rtx -rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp) +static int +get_element_number (tree vec_type, tree arg) { - rtx pat; - tree arg0 = CALL_EXPR_ARG (exp, 0); - rtx op0 = expand_normal (arg0); - machine_mode mode0 = insn_data[icode].operand[0].mode; - - if (TARGET_32BIT) - /* Builtin not supported in 32-bit mode. */ - fatal_error (input_location, - "%<__builtin_set_fpscr_drn%> is not supported " - "in 32-bit mode"); + unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1; - if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT) + if (!tree_fits_uhwi_p (arg) + || (elt = tree_to_uhwi (arg), elt > max)) { - error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>"); - return const0_rtx; - } - - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; - - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node) - return const0_rtx; - - /* If the argument is a constant, check the range. Agrument can only be a - 3-bit value. Unfortunately, can't check the range of the value at - compile time if the argument is a variable. The least significant two - bits of the argument, regardless of type, are used to set the rounding - mode. All other bits are ignored. */ - if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode)) - { - error ("Argument must be a value between 0 and 7."); - return const0_rtx; + error ("selector must be an integer constant in the range [0, %wi]", max); + return 0; } - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - pat = GEN_FCN (icode) (op0); - if (! pat) - return const0_rtx; - emit_insn (pat); - - return NULL_RTX; + return elt; } +/* Expand vec_set builtin. */ static rtx -rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target) +altivec_expand_vec_set_builtin (tree exp) { - rtx pat; - tree arg0 = CALL_EXPR_ARG (exp, 0); - rtx op0 = expand_normal (arg0); - machine_mode tmode = insn_data[icode].operand[0].mode; - machine_mode mode0 = insn_data[icode].operand[1].mode; - - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; - - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node) - return const0_rtx; - - if (icode == CODE_FOR_altivec_vspltisb - || icode == CODE_FOR_altivec_vspltish - || icode == CODE_FOR_altivec_vspltisw) - { - /* Only allow 5-bit *signed* literals. */ - if (!CONST_INT_P (op0) - || INTVAL (op0) > 15 - || INTVAL (op0) < -16) - { - error ("argument 1 must be a 5-bit signed literal"); - return CONST0_RTX (tmode); - } - } - - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - pat = GEN_FCN (icode) (target, op0); - if (! pat) - return 0; - emit_insn (pat); - - return target; -} + machine_mode tmode, mode1; + tree arg0, arg1, arg2; + int elt; + rtx op0, op1; -static rtx -altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target) -{ - rtx pat, scratch1, scratch2; - tree arg0 = CALL_EXPR_ARG (exp, 0); - rtx op0 = expand_normal (arg0); - machine_mode tmode = insn_data[icode].operand[0].mode; - machine_mode mode0 = insn_data[icode].operand[1].mode; + arg0 = CALL_EXPR_ARG (exp, 0); + arg1 = CALL_EXPR_ARG (exp, 1); + arg2 = CALL_EXPR_ARG (exp, 2); - /* If we have invalid arguments, bail out before generating bad rtl. */ - if (arg0 == error_mark_node) - return const0_rtx; + tmode = TYPE_MODE (TREE_TYPE (arg0)); + mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); + gcc_assert (VECTOR_MODE_P (tmode)); - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); + op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL); + op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL); + elt = get_element_number (TREE_TYPE (arg0), arg2); - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); + if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode) + op1 = convert_modes (mode1, GET_MODE (op1), op1, true); - scratch1 = gen_reg_rtx (mode0); - scratch2 = gen_reg_rtx (mode0); + op0 = force_reg (tmode, op0); + op1 = force_reg (mode1, op1); - pat = GEN_FCN (icode) (target, op0, scratch1, scratch2); - if (! pat) - return 0; - emit_insn (pat); + rs6000_expand_vector_set (op0, op1, GEN_INT (elt)); - return target; + return op0; } +/* Expand vec_ext builtin. */ static rtx -rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target) +altivec_expand_vec_ext_builtin (tree exp, rtx target) { - rtx pat; - tree arg0 = CALL_EXPR_ARG (exp, 0); - tree arg1 = CALL_EXPR_ARG (exp, 1); - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - machine_mode tmode = insn_data[icode].operand[0].mode; - machine_mode mode0 = insn_data[icode].operand[1].mode; - machine_mode mode1 = insn_data[icode].operand[2].mode; + machine_mode tmode, mode0; + tree arg0, arg1; + rtx op0; + rtx op1; - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; + arg0 = CALL_EXPR_ARG (exp, 0); + arg1 = CALL_EXPR_ARG (exp, 1); - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node || arg1 == error_mark_node) - return const0_rtx; + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); - if (icode == CODE_FOR_unpackv1ti - || icode == CODE_FOR_unpackkf - || icode == CODE_FOR_unpacktf - || icode == CODE_FOR_unpackif - || icode == CODE_FOR_unpacktd - || icode == CODE_FOR_vec_cntmb_v16qi - || icode == CODE_FOR_vec_cntmb_v8hi - || icode == CODE_FOR_vec_cntmb_v4si - || icode == CODE_FOR_vec_cntmb_v2di) - { - /* Only allow 1-bit unsigned literals. */ - STRIP_NOPS (arg1); - if (TREE_CODE (arg1) != INTEGER_CST - || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1)) - { - error ("argument 2 must be a 1-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_altivec_vspltw) - { - /* Only allow 2-bit unsigned literals. */ - STRIP_NOPS (arg1); - if (TREE_CODE (arg1) != INTEGER_CST - || TREE_INT_CST_LOW (arg1) & ~3) - { - error ("argument 2 must be a 2-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_vgnb) - { - /* Only allow unsigned literals in range 2..7. */ - /* Note that arg1 is second operand. */ - STRIP_NOPS (arg1); - if (TREE_CODE (arg1) != INTEGER_CST - || (TREE_INT_CST_LOW (arg1) & ~7) - || !IN_RANGE (TREE_INT_CST_LOW (arg1), 2, 7)) - { - error ("argument 2 must be unsigned literal between " - "2 and 7 inclusive"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_altivec_vsplth) - { - /* Only allow 3-bit unsigned literals. */ - STRIP_NOPS (arg1); - if (TREE_CODE (arg1) != INTEGER_CST - || TREE_INT_CST_LOW (arg1) & ~7) - { - error ("argument 2 must be a 3-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_altivec_vspltb) - { - /* Only allow 4-bit unsigned literals. */ - STRIP_NOPS (arg1); - if (TREE_CODE (arg1) != INTEGER_CST - || TREE_INT_CST_LOW (arg1) & ~15) - { - error ("argument 2 must be a 4-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_altivec_vcfux - || icode == CODE_FOR_altivec_vcfsx - || icode == CODE_FOR_altivec_vctsxs - || icode == CODE_FOR_altivec_vctuxs - || icode == CODE_FOR_vsx_xvcvuxddp_scale - || icode == CODE_FOR_vsx_xvcvsxddp_scale) - { - /* Only allow 5-bit unsigned literals. */ - STRIP_NOPS (arg1); - if (TREE_CODE (arg1) != INTEGER_CST - || TREE_INT_CST_LOW (arg1) & ~0x1f) - { - error ("argument 2 must be a 5-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_dfptstsfi_eq_dd - || icode == CODE_FOR_dfptstsfi_lt_dd - || icode == CODE_FOR_dfptstsfi_gt_dd - || icode == CODE_FOR_dfptstsfi_unordered_dd - || icode == CODE_FOR_dfptstsfi_eq_td - || icode == CODE_FOR_dfptstsfi_lt_td - || icode == CODE_FOR_dfptstsfi_gt_td - || icode == CODE_FOR_dfptstsfi_unordered_td) - { - /* Only allow 6-bit unsigned literals. */ - STRIP_NOPS (arg0); - if (TREE_CODE (arg0) != INTEGER_CST - || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63)) - { - error ("argument 1 must be a 6-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_xststdcqp_kf - || icode == CODE_FOR_xststdcqp_tf - || icode == CODE_FOR_xststdcdp - || icode == CODE_FOR_xststdcsp - || icode == CODE_FOR_xvtstdcdp - || icode == CODE_FOR_xvtstdcsp) + if (TREE_CODE (arg1) == INTEGER_CST) { - /* Only allow 7-bit unsigned literals. */ - STRIP_NOPS (arg1); - if (TREE_CODE (arg1) != INTEGER_CST - || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127)) - { - error ("argument 2 must be a 7-bit unsigned literal"); - return CONST0_RTX (tmode); - } + unsigned HOST_WIDE_INT elt; + unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0)); + unsigned int truncated_selector; + /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0) + returns low-order bits of INTEGER_CST for modulo indexing. */ + elt = TREE_INT_CST_LOW (arg1); + truncated_selector = elt % size; + op1 = GEN_INT (truncated_selector); } - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); + tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); + mode0 = TYPE_MODE (TREE_TYPE (arg0)); + gcc_assert (VECTOR_MODE_P (mode0)); - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); + op0 = force_reg (mode0, op0); - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - emit_insn (pat); + if (optimize || !target || !register_operand (target, tmode)) + target = gen_reg_rtx (tmode); + + rs6000_expand_vector_extract (target, op0, op1); return target; } -static rtx -altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target) +/* Check whether a builtin function is supported in this target + configuration. */ +bool +rs6000_builtin_is_supported_p (enum rs6000_builtins fncode) { - rtx pat, scratch; - tree cr6_form = CALL_EXPR_ARG (exp, 0); - tree arg0 = CALL_EXPR_ARG (exp, 1); - tree arg1 = CALL_EXPR_ARG (exp, 2); - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - machine_mode tmode = SImode; - machine_mode mode0 = insn_data[icode].operand[1].mode; - machine_mode mode1 = insn_data[icode].operand[2].mode; - int cr6_form_int; - - if (TREE_CODE (cr6_form) != INTEGER_CST) - { - error ("argument 1 of %qs must be a constant", - "__builtin_altivec_predicate"); - return const0_rtx; - } + HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask; + if ((fnmask & rs6000_builtin_mask) != fnmask) + return false; else - cr6_form_int = TREE_INT_CST_LOW (cr6_form); - - gcc_assert (mode0 == mode1); - - /* If we have invalid arguments, bail out before generating bad rtl. */ - if (arg0 == error_mark_node || arg1 == error_mark_node) - return const0_rtx; - - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - - /* Note that for many of the relevant operations (e.g. cmpne or - cmpeq) with float or double operands, it makes more sense for the - mode of the allocated scratch register to select a vector of - integer. But the choice to copy the mode of operand 0 was made - long ago and there are no plans to change it. */ - scratch = gen_reg_rtx (mode0); - - pat = GEN_FCN (icode) (scratch, op0, op1); - if (! pat) - return 0; - emit_insn (pat); + return true; +} - /* The vec_any* and vec_all* predicates use the same opcodes for two - different operations, but the bits in CR6 will be different - depending on what information we want. So we have to play tricks - with CR6 to get the right bits out. +/* Raise an error message for a builtin function that is called without the + appropriate target options being set. */ - If you think this is disgusting, look at the specs for the - AltiVec predicates. */ +void +rs6000_invalid_new_builtin (enum rs6000_gen_builtins fncode) +{ + size_t j = (size_t) fncode; + const char *name = rs6000_builtin_info_x[j].bifname; - switch (cr6_form_int) + switch (rs6000_builtin_info_x[j].enable) { - case 0: - emit_insn (gen_cr6_test_for_zero (target)); + case ENB_P5: + error ("%qs requires the %qs option", name, "-mcpu=power5"); break; - case 1: - emit_insn (gen_cr6_test_for_zero_reverse (target)); + case ENB_P6: + error ("%qs requires the %qs option", name, "-mcpu=power6"); break; - case 2: - emit_insn (gen_cr6_test_for_lt (target)); + case ENB_P6_64: + error ("%qs requires the %qs option and either the %qs or %qs option", + name, "-mcpu=power6", "-m64", "-mpowerpc64"); break; - case 3: - emit_insn (gen_cr6_test_for_lt_reverse (target)); + case ENB_ALTIVEC: + error ("%qs requires the %qs option", name, "-maltivec"); break; - default: - error ("argument 1 of %qs is out of range", - "__builtin_altivec_predicate"); + case ENB_CELL: + error ("%qs requires the %qs option", name, "-mcpu=cell"); break; - } - - return target; -} - -rtx -swap_endian_selector_for_mode (machine_mode mode) -{ - unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0}; - unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8}; - unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12}; - unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14}; - - unsigned int *swaparray, i; - rtx perm[16]; - - switch (mode) - { - case E_V1TImode: - swaparray = swap1; + case ENB_VSX: + error ("%qs requires the %qs option", name, "-mvsx"); break; - case E_V2DFmode: - case E_V2DImode: - swaparray = swap2; + case ENB_P7: + error ("%qs requires the %qs option", name, "-mcpu=power7"); break; - case E_V4SFmode: - case E_V4SImode: - swaparray = swap4; + case ENB_P7_64: + error ("%qs requires the %qs option and either the %qs or %qs option", + name, "-mcpu=power7", "-m64", "-mpowerpc64"); break; - case E_V8HImode: - swaparray = swap8; + case ENB_P8: + error ("%qs requires the %qs option", name, "-mcpu=power8"); + break; + case ENB_P8V: + error ("%qs requires the %qs and %qs options", name, "-mcpu=power8", + "-mvsx"); + break; + case ENB_P9: + error ("%qs requires the %qs option", name, "-mcpu=power9"); + break; + case ENB_P9_64: + error ("%qs requires the %qs option and either the %qs or %qs option", + name, "-mcpu=power9", "-m64", "-mpowerpc64"); + break; + case ENB_P9V: + error ("%qs requires the %qs and %qs options", name, "-mcpu=power9", + "-mvsx"); + break; + case ENB_IEEE128_HW: + error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name); + break; + case ENB_DFP: + error ("%qs requires the %qs option", name, "-mhard-dfp"); + break; + case ENB_CRYPTO: + error ("%qs requires the %qs option", name, "-mcrypto"); + break; + case ENB_HTM: + error ("%qs requires the %qs option", name, "-mhtm"); + break; + case ENB_P10: + error ("%qs requires the %qs option", name, "-mcpu=power10"); + break; + case ENB_P10_64: + error ("%qs requires the %qs option and either the %qs or %qs option", + name, "-mcpu=power10", "-m64", "-mpowerpc64"); + break; + case ENB_MMA: + error ("%qs requires the %qs option", name, "-mmma"); break; default: + case ENB_ALWAYS: gcc_unreachable (); } +} - for (i = 0; i < 16; ++i) - perm[i] = GEN_INT (swaparray[i]); +/* Target hook for early folding of built-ins, shamelessly stolen + from ia64.c. */ - return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, - gen_rtvec_v (16, perm))); +tree +rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED, + int n_args ATTRIBUTE_UNUSED, + tree *args ATTRIBUTE_UNUSED, + bool ignore ATTRIBUTE_UNUSED) +{ +#ifdef SUBTARGET_FOLD_BUILTIN + return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore); +#else + return NULL_TREE; +#endif } -/* For the load and sign extend rightmost elements; load and zero extend - rightmost element builtins. */ -static rtx -altivec_expand_lxvr_builtin (enum insn_code icode, tree exp, rtx target, bool blk, bool sign_extend) +/* Helper function to handle the gimple folding of a vector compare + operation. This sets up true/false vectors, and uses the + VEC_COND_EXPR operation. + CODE indicates which comparison is to be made. (EQ, GT, ...). + TYPE indicates the type of the result. + Code is inserted before GSI. */ +static tree +fold_build_vec_cmp (tree_code code, tree type, tree arg0, tree arg1, + gimple_stmt_iterator *gsi) { - rtx pat, addr; - tree arg0 = CALL_EXPR_ARG (exp, 0); - tree arg1 = CALL_EXPR_ARG (exp, 1); - machine_mode tmode = insn_data[icode].operand[0].mode; - machine_mode smode = insn_data[icode].operand[1].mode; - machine_mode mode0 = Pmode; - machine_mode mode1 = Pmode; - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; - - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node || arg1 == error_mark_node) - return const0_rtx; - - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); + tree cmp_type = truth_type_for (type); + tree zero_vec = build_zero_cst (type); + tree minus_one_vec = build_minus_one_cst (type); + tree temp = create_tmp_reg_or_ssa_name (cmp_type); + gimple *g = gimple_build_assign (temp, code, arg0, arg1); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + return fold_build3 (VEC_COND_EXPR, type, temp, minus_one_vec, zero_vec); +} - op1 = copy_to_mode_reg (mode1, op1); +/* Helper function to handle the in-between steps for the + vector compare built-ins. */ +static void +fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt) +{ + tree arg0 = gimple_call_arg (stmt, 0); + tree arg1 = gimple_call_arg (stmt, 1); + tree lhs = gimple_call_lhs (stmt); + tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1, gsi); + gimple *g = gimple_build_assign (lhs, cmp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); +} - if (op0 == const0_rtx) - addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1); +/* Helper function to map V2DF and V4SF types to their + integral equivalents (V2DI and V4SI). */ +tree map_to_integral_tree_type (tree input_tree_type) +{ + if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type))) + return input_tree_type; else { - op0 = copy_to_mode_reg (mode0, op0); - addr = gen_rtx_MEM (blk ? BLKmode : smode, - gen_rtx_PLUS (Pmode, op1, op0)); - } - - if (sign_extend) - { - rtx discratch = gen_reg_rtx (V2DImode); - rtx tiscratch = gen_reg_rtx (TImode); - - /* Emit the lxvr*x insn. */ - pat = GEN_FCN (icode) (tiscratch, addr); - if (!pat) - return 0; - emit_insn (pat); - - /* Emit a sign extension from V16QI,V8HI,V4SI to V2DI. */ - rtx temp1, temp2; - if (icode == CODE_FOR_vsx_lxvrbx) - { - temp1 = simplify_gen_subreg (V16QImode, tiscratch, TImode, 0); - emit_insn (gen_vsx_sign_extend_qi_v2di (discratch, temp1)); - } - else if (icode == CODE_FOR_vsx_lxvrhx) - { - temp1 = simplify_gen_subreg (V8HImode, tiscratch, TImode, 0); - emit_insn (gen_vsx_sign_extend_hi_v2di (discratch, temp1)); - } - else if (icode == CODE_FOR_vsx_lxvrwx) - { - temp1 = simplify_gen_subreg (V4SImode, tiscratch, TImode, 0); - emit_insn (gen_vsx_sign_extend_si_v2di (discratch, temp1)); - } - else if (icode == CODE_FOR_vsx_lxvrdx) - discratch = simplify_gen_subreg (V2DImode, tiscratch, TImode, 0); + if (types_compatible_p (TREE_TYPE (input_tree_type), + TREE_TYPE (V2DF_type_node))) + return V2DI_type_node; + else if (types_compatible_p (TREE_TYPE (input_tree_type), + TREE_TYPE (V4SF_type_node))) + return V4SI_type_node; else gcc_unreachable (); - - /* Emit the sign extension from V2DI (double) to TI (quad). */ - temp2 = simplify_gen_subreg (TImode, discratch, V2DImode, 0); - emit_insn (gen_extendditi2_vector (target, temp2)); - - return target; - } - else - { - /* Zero extend. */ - pat = GEN_FCN (icode) (target, addr); - if (!pat) - return 0; - emit_insn (pat); - return target; } - return 0; } -static rtx -altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk) +/* Helper function to handle the vector merge[hl] built-ins. The + implementation difference between h and l versions for this code are in + the values used when building of the permute vector for high word versus + low word merge. The variance is keyed off the use_high parameter. */ +static void +fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high) { - rtx pat, addr; - tree arg0 = CALL_EXPR_ARG (exp, 0); - tree arg1 = CALL_EXPR_ARG (exp, 1); - machine_mode tmode = insn_data[icode].operand[0].mode; - machine_mode mode0 = Pmode; - machine_mode mode1 = Pmode; - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; - - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node || arg1 == error_mark_node) - return const0_rtx; + tree arg0 = gimple_call_arg (stmt, 0); + tree arg1 = gimple_call_arg (stmt, 1); + tree lhs = gimple_call_lhs (stmt); + tree lhs_type = TREE_TYPE (lhs); + int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type); + int midpoint = n_elts / 2; + int offset = 0; - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); + if (use_high == 1) + offset = midpoint; - op1 = copy_to_mode_reg (mode1, op1); + /* The permute_type will match the lhs for integral types. For double and + float types, the permute type needs to map to the V2 or V4 type that + matches size. */ + tree permute_type; + permute_type = map_to_integral_tree_type (lhs_type); + tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1); - /* For LVX, express the RTL accurately by ANDing the address with -16. - LVXL and LVE*X expand to use UNSPECs to hide their special behavior, - so the raw address is fine. */ - if (icode == CODE_FOR_altivec_lvx_v1ti - || icode == CODE_FOR_altivec_lvx_v2df - || icode == CODE_FOR_altivec_lvx_v2di - || icode == CODE_FOR_altivec_lvx_v4sf - || icode == CODE_FOR_altivec_lvx_v4si - || icode == CODE_FOR_altivec_lvx_v8hi - || icode == CODE_FOR_altivec_lvx_v16qi) + for (int i = 0; i < midpoint; i++) { - rtx rawaddr; - if (op0 == const0_rtx) - rawaddr = op1; - else - { - op0 = copy_to_mode_reg (mode0, op0); - rawaddr = gen_rtx_PLUS (Pmode, op1, op0); - } - addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16)); - addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr); - - emit_insn (gen_rtx_SET (target, addr)); + elts.safe_push (build_int_cst (TREE_TYPE (permute_type), + offset + i)); + elts.safe_push (build_int_cst (TREE_TYPE (permute_type), + offset + n_elts + i)); } - else - { - if (op0 == const0_rtx) - addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1); - else - { - op0 = copy_to_mode_reg (mode0, op0); - addr = gen_rtx_MEM (blk ? BLKmode : tmode, - gen_rtx_PLUS (Pmode, op1, op0)); - } - pat = GEN_FCN (icode) (target, addr); - if (! pat) - return 0; - emit_insn (pat); - } + tree permute = elts.build (); - return target; + gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); } -static rtx -altivec_expand_stxvl_builtin (enum insn_code icode, tree exp) +/* Helper function to handle the vector merge[eo] built-ins. */ +static void +fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd) { - rtx pat; - tree arg0 = CALL_EXPR_ARG (exp, 0); - tree arg1 = CALL_EXPR_ARG (exp, 1); - tree arg2 = CALL_EXPR_ARG (exp, 2); - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - rtx op2 = expand_normal (arg2); - machine_mode mode0 = insn_data[icode].operand[0].mode; - machine_mode mode1 = insn_data[icode].operand[1].mode; - machine_mode mode2 = insn_data[icode].operand[2].mode; + tree arg0 = gimple_call_arg (stmt, 0); + tree arg1 = gimple_call_arg (stmt, 1); + tree lhs = gimple_call_lhs (stmt); + tree lhs_type = TREE_TYPE (lhs); + int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type); - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return NULL_RTX; + /* The permute_type will match the lhs for integral types. For double and + float types, the permute type needs to map to the V2 or V4 type that + matches size. */ + tree permute_type; + permute_type = map_to_integral_tree_type (lhs_type); - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node - || arg1 == error_mark_node - || arg2 == error_mark_node) - return NULL_RTX; + tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1); - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) - op2 = copy_to_mode_reg (mode2, op2); + /* Build the permute vector. */ + for (int i = 0; i < n_elts / 2; i++) + { + elts.safe_push (build_int_cst (TREE_TYPE (permute_type), + 2*i + use_odd)); + elts.safe_push (build_int_cst (TREE_TYPE (permute_type), + 2*i + use_odd + n_elts)); + } - pat = GEN_FCN (icode) (op0, op1, op2); - if (pat) - emit_insn (pat); + tree permute = elts.build (); - return NULL_RTX; + gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); } -static rtx -altivec_expand_stv_builtin (enum insn_code icode, tree exp) -{ - tree arg0 = CALL_EXPR_ARG (exp, 0); - tree arg1 = CALL_EXPR_ARG (exp, 1); - tree arg2 = CALL_EXPR_ARG (exp, 2); - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - rtx op2 = expand_normal (arg2); - rtx pat, addr, rawaddr, truncrtx; - machine_mode tmode = insn_data[icode].operand[0].mode; - machine_mode smode = insn_data[icode].operand[1].mode; - machine_mode mode1 = Pmode; - machine_mode mode2 = Pmode; - - /* Invalid arguments. Bail before doing anything stoopid! */ - if (arg0 == error_mark_node - || arg1 == error_mark_node - || arg2 == error_mark_node) - return const0_rtx; - - op2 = copy_to_mode_reg (mode2, op2); +/* Expand the MMA built-ins early, so that we can convert the pass-by-reference + __vector_quad arguments into pass-by-value arguments, leading to more + efficient code generation. */ - /* For STVX, express the RTL accurately by ANDing the address with -16. - STVXL and STVE*X expand to use UNSPECs to hide their special behavior, - so the raw address is fine. */ - if (icode == CODE_FOR_altivec_stvx_v2df - || icode == CODE_FOR_altivec_stvx_v2di - || icode == CODE_FOR_altivec_stvx_v4sf - || icode == CODE_FOR_altivec_stvx_v4si - || icode == CODE_FOR_altivec_stvx_v8hi - || icode == CODE_FOR_altivec_stvx_v16qi) - { - if (op1 == const0_rtx) - rawaddr = op2; - else - { - op1 = copy_to_mode_reg (mode1, op1); - rawaddr = gen_rtx_PLUS (Pmode, op2, op1); - } +bool +rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi) +{ + gimple *stmt = gsi_stmt (*gsi); + tree fndecl = gimple_call_fndecl (stmt); + enum rs6000_builtins fncode + = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); + unsigned attr = rs6000_builtin_info[fncode].attr; - addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16)); - addr = gen_rtx_MEM (tmode, addr); + if ((attr & RS6000_BTC_GIMPLE) == 0) + return false; - op0 = copy_to_mode_reg (tmode, op0); + unsigned nopnds = (attr & RS6000_BTC_OPND_MASK); + gimple_seq new_seq = NULL; + gimple *new_call; + tree new_decl; - emit_insn (gen_rtx_SET (addr, op0)); - } - else if (icode == CODE_FOR_vsx_stxvrbx - || icode == CODE_FOR_vsx_stxvrhx - || icode == CODE_FOR_vsx_stxvrwx - || icode == CODE_FOR_vsx_stxvrdx) + if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC + || fncode == VSX_BUILTIN_DISASSEMBLE_PAIR) { - truncrtx = gen_rtx_TRUNCATE (tmode, op0); - op0 = copy_to_mode_reg (E_TImode, truncrtx); + /* This is an MMA disassemble built-in function. */ + push_gimplify_context (true); + unsigned nvec = (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) ? 4 : 2; + tree dst_ptr = gimple_call_arg (stmt, 0); + tree src_ptr = gimple_call_arg (stmt, 1); + tree src_type = TREE_TYPE (src_ptr); + tree src = create_tmp_reg_or_ssa_name (TREE_TYPE (src_type)); + gimplify_assign (src, build_simple_mem_ref (src_ptr), &new_seq); - if (op1 == const0_rtx) - addr = gen_rtx_MEM (Pmode, op2); - else + /* If we are not disassembling an accumulator/pair or our destination is + another accumulator/pair, then just copy the entire thing as is. */ + if ((fncode == MMA_BUILTIN_DISASSEMBLE_ACC + && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_quad_type_node) + || (fncode == VSX_BUILTIN_DISASSEMBLE_PAIR + && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_pair_type_node)) { - op1 = copy_to_mode_reg (mode1, op1); - addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1)); + tree dst = build_simple_mem_ref (build1 (VIEW_CONVERT_EXPR, + src_type, dst_ptr)); + gimplify_assign (dst, src, &new_seq); + pop_gimplify_context (NULL); + gsi_replace_with_seq (gsi, new_seq, true); + return true; } - pat = GEN_FCN (icode) (addr, op0); - if (pat) - emit_insn (pat); - } - else - { - if (! (*insn_data[icode].operand[1].predicate) (op0, smode)) - op0 = copy_to_mode_reg (smode, op0); - if (op1 == const0_rtx) - addr = gen_rtx_MEM (tmode, op2); - else + /* If we're disassembling an accumulator into a different type, we need + to emit a xxmfacc instruction now, since we cannot do it later. */ + if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) { - op1 = copy_to_mode_reg (mode1, op1); - addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1)); + new_decl = rs6000_builtin_decls[MMA_BUILTIN_XXMFACC_INTERNAL]; + new_call = gimple_build_call (new_decl, 1, src); + src = create_tmp_reg_or_ssa_name (vector_quad_type_node); + gimple_call_set_lhs (new_call, src); + gimple_seq_add_stmt (&new_seq, new_call); } - pat = GEN_FCN (icode) (addr, op0); - if (pat) - emit_insn (pat); + /* Copy the accumulator/pair vector by vector. */ + new_decl = rs6000_builtin_decls[fncode + 1]; + tree dst_type = build_pointer_type_for_mode (unsigned_V16QI_type_node, + ptr_mode, true); + tree dst_base = build1 (VIEW_CONVERT_EXPR, dst_type, dst_ptr); + for (unsigned i = 0; i < nvec; i++) + { + unsigned index = WORDS_BIG_ENDIAN ? i : nvec - 1 - i; + tree dst = build2 (MEM_REF, unsigned_V16QI_type_node, dst_base, + build_int_cst (dst_type, index * 16)); + tree dstssa = create_tmp_reg_or_ssa_name (unsigned_V16QI_type_node); + new_call = gimple_build_call (new_decl, 2, src, + build_int_cstu (uint16_type_node, i)); + gimple_call_set_lhs (new_call, dstssa); + gimple_seq_add_stmt (&new_seq, new_call); + gimplify_assign (dst, dstssa, &new_seq); + } + pop_gimplify_context (NULL); + gsi_replace_with_seq (gsi, new_seq, true); + return true; } - - return NULL_RTX; -} - -/* Expand the MMA built-in in EXP. - Store true in *EXPANDEDP if we found a built-in to expand. */ - -static rtx -mma_expand_builtin (tree exp, rtx target, bool *expandedp) -{ - unsigned i; - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - enum rs6000_builtins fcode - = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); - const struct builtin_description *d = bdesc_mma; - - /* Expand the MMA built-in. */ - for (i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++) - if (d->code == fcode) - break; - - if (i >= ARRAY_SIZE (bdesc_mma)) + else if (fncode == VSX_BUILTIN_LXVP) { - *expandedp = false; - return NULL_RTX; + push_gimplify_context (true); + tree offset = gimple_call_arg (stmt, 0); + tree ptr = gimple_call_arg (stmt, 1); + tree lhs = gimple_call_lhs (stmt); + if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) + ptr = build1 (VIEW_CONVERT_EXPR, + build_pointer_type (vector_pair_type_node), ptr); + tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, + TREE_TYPE (ptr), ptr, offset)); + gimplify_assign (lhs, mem, &new_seq); + pop_gimplify_context (NULL); + gsi_replace_with_seq (gsi, new_seq, true); + return true; + } + else if (fncode == VSX_BUILTIN_STXVP) + { + push_gimplify_context (true); + tree src = gimple_call_arg (stmt, 0); + tree offset = gimple_call_arg (stmt, 1); + tree ptr = gimple_call_arg (stmt, 2); + if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) + ptr = build1 (VIEW_CONVERT_EXPR, + build_pointer_type (vector_pair_type_node), ptr); + tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, + TREE_TYPE (ptr), ptr, offset)); + gimplify_assign (mem, src, &new_seq); + pop_gimplify_context (NULL); + gsi_replace_with_seq (gsi, new_seq, true); + return true; } - *expandedp = true; - - tree arg; - call_expr_arg_iterator iter; - enum insn_code icode = d->icode; - const struct insn_operand_data *insn_op; - rtx op[MAX_MMA_OPERANDS]; - unsigned nopnds = 0; - unsigned attr = rs6000_builtin_info[fcode].attr; - bool void_func = (attr & RS6000_BTC_VOID); - machine_mode tmode = VOIDmode; + /* Convert this built-in into an internal version that uses pass-by-value + arguments. The internal built-in follows immediately after this one. */ + new_decl = rs6000_builtin_decls[fncode + 1]; + tree lhs, op[MAX_MMA_OPERANDS]; + tree acc = gimple_call_arg (stmt, 0); + push_gimplify_context (true); - if (TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node) + if ((attr & RS6000_BTC_QUAD) != 0) { - tmode = insn_data[icode].operand[0].mode; - if (!target - || GET_MODE (target) != tmode - || !(*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - op[nopnds++] = target; + /* This built-in has a pass-by-reference accumulator input, so load it + into a temporary accumulator for use as a pass-by-value input. */ + op[0] = create_tmp_reg_or_ssa_name (vector_quad_type_node); + for (unsigned i = 1; i < nopnds; i++) + op[i] = gimple_call_arg (stmt, i); + gimplify_assign (op[0], build_simple_mem_ref (acc), &new_seq); } else - target = const0_rtx; - - FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) { - if (arg == error_mark_node) - return const0_rtx; - - rtx opnd; - insn_op = &insn_data[icode].operand[nopnds]; - if (TREE_CODE (arg) == ADDR_EXPR - && MEM_P (DECL_RTL (TREE_OPERAND (arg, 0)))) - opnd = DECL_RTL (TREE_OPERAND (arg, 0)); - else - opnd = expand_normal (arg); - - if (!(*insn_op->predicate) (opnd, insn_op->mode)) - { - if (!strcmp (insn_op->constraint, "n")) - { - if (!CONST_INT_P (opnd)) - error ("argument %d must be an unsigned literal", nopnds); - else - error ("argument %d is an unsigned literal that is " - "out of range", nopnds); - return const0_rtx; - } - opnd = copy_to_mode_reg (insn_op->mode, opnd); - } - - /* Some MMA instructions have INOUT accumulator operands, so force - their target register to be the same as their input register. */ - if (!void_func - && nopnds == 1 - && !strcmp (insn_op->constraint, "0") - && insn_op->mode == tmode - && REG_P (opnd) - && (*insn_data[icode].operand[0].predicate) (opnd, tmode)) - target = op[0] = opnd; - - op[nopnds++] = opnd; + /* This built-in does not use its pass-by-reference accumulator argument + as an input argument, so remove it from the input list. */ + nopnds--; + for (unsigned i = 0; i < nopnds; i++) + op[i] = gimple_call_arg (stmt, i + 1); } - unsigned attr_args = attr & RS6000_BTC_OPND_MASK; - if (attr & RS6000_BTC_QUAD - || fcode == VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL) - attr_args++; - - gcc_assert (nopnds == attr_args); - - rtx pat; switch (nopnds) { + case 0: + new_call = gimple_build_call (new_decl, 0); + break; case 1: - pat = GEN_FCN (icode) (op[0]); + new_call = gimple_build_call (new_decl, 1, op[0]); break; case 2: - pat = GEN_FCN (icode) (op[0], op[1]); + new_call = gimple_build_call (new_decl, 2, op[0], op[1]); break; case 3: - /* The ASSEMBLE builtin source operands are reversed in little-endian - mode, so reorder them. */ - if (fcode == VSX_BUILTIN_ASSEMBLE_PAIR_INTERNAL && !WORDS_BIG_ENDIAN) - std::swap (op[1], op[2]); - pat = GEN_FCN (icode) (op[0], op[1], op[2]); + new_call = gimple_build_call (new_decl, 3, op[0], op[1], op[2]); break; case 4: - pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); + new_call = gimple_build_call (new_decl, 4, op[0], op[1], op[2], op[3]); break; case 5: - /* The ASSEMBLE builtin source operands are reversed in little-endian - mode, so reorder them. */ - if (fcode == MMA_BUILTIN_ASSEMBLE_ACC_INTERNAL && !WORDS_BIG_ENDIAN) - { - std::swap (op[1], op[4]); - std::swap (op[2], op[3]); - } - pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); + new_call = gimple_build_call (new_decl, 5, op[0], op[1], op[2], op[3], + op[4]); break; case 6: - pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]); + new_call = gimple_build_call (new_decl, 6, op[0], op[1], op[2], op[3], + op[4], op[5]); break; case 7: - pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5], op[6]); + new_call = gimple_build_call (new_decl, 7, op[0], op[1], op[2], op[3], + op[4], op[5], op[6]); break; default: gcc_unreachable (); } - if (!pat) - return NULL_RTX; - emit_insn (pat); - return target; + if (fncode == VSX_BUILTIN_BUILD_PAIR || fncode == VSX_BUILTIN_ASSEMBLE_PAIR) + lhs = create_tmp_reg_or_ssa_name (vector_pair_type_node); + else + lhs = create_tmp_reg_or_ssa_name (vector_quad_type_node); + gimple_call_set_lhs (new_call, lhs); + gimple_seq_add_stmt (&new_seq, new_call); + gimplify_assign (build_simple_mem_ref (acc), lhs, &new_seq); + pop_gimplify_context (NULL); + gsi_replace_with_seq (gsi, new_seq, true); + + return true; } -/* Return the appropriate SPR number associated with the given builtin. */ -static inline HOST_WIDE_INT -htm_spr_num (enum rs6000_builtins code) -{ - if (code == HTM_BUILTIN_GET_TFHAR - || code == HTM_BUILTIN_SET_TFHAR) - return TFHAR_SPR; - else if (code == HTM_BUILTIN_GET_TFIAR - || code == HTM_BUILTIN_SET_TFIAR) - return TFIAR_SPR; - else if (code == HTM_BUILTIN_GET_TEXASR - || code == HTM_BUILTIN_SET_TEXASR) - return TEXASR_SPR; - gcc_assert (code == HTM_BUILTIN_GET_TEXASRU - || code == HTM_BUILTIN_SET_TEXASRU); - return TEXASRU_SPR; -} +/* Fold a machine-dependent built-in in GIMPLE. (For folding into + a constant, use rs6000_fold_builtin.) */ -/* Return the correct ICODE value depending on whether we are - setting or reading the HTM SPRs. */ -static inline enum insn_code -rs6000_htm_spr_icode (bool nonvoid) +bool +rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) { - if (nonvoid) - return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si; - else - return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si; + return rs6000_gimple_fold_new_builtin (gsi); } -/* Expand the HTM builtin in EXP and store the result in TARGET. - Store true in *EXPANDEDP if we found a builtin to expand. */ -static rtx -htm_expand_builtin (tree exp, rtx target, bool * expandedp) +/* Helper function to sort out which built-ins may be valid without having + a LHS. */ +static bool +rs6000_new_builtin_valid_without_lhs (enum rs6000_gen_builtins fn_code, + tree fndecl) { - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; - enum rs6000_builtins fcode - = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); - const struct builtin_description *d; - size_t i; - - *expandedp = true; + if (TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node) + return true; - if (!TARGET_POWERPC64 - && (fcode == HTM_BUILTIN_TABORTDC - || fcode == HTM_BUILTIN_TABORTDCI)) + switch (fn_code) { - size_t uns_fcode = (size_t)fcode; - const char *name = rs6000_builtin_info[uns_fcode].name; - error ("builtin %qs is only valid in 64-bit mode", name); - return const0_rtx; + case RS6000_BIF_STVX_V16QI: + case RS6000_BIF_STVX_V8HI: + case RS6000_BIF_STVX_V4SI: + case RS6000_BIF_STVX_V4SF: + case RS6000_BIF_STVX_V2DI: + case RS6000_BIF_STVX_V2DF: + case RS6000_BIF_STXVW4X_V16QI: + case RS6000_BIF_STXVW4X_V8HI: + case RS6000_BIF_STXVW4X_V4SF: + case RS6000_BIF_STXVW4X_V4SI: + case RS6000_BIF_STXVD2X_V2DF: + case RS6000_BIF_STXVD2X_V2DI: + return true; + default: + return false; } - - /* Expand the HTM builtins. */ - d = bdesc_htm; - for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++) - if (d->code == fcode) - { - rtx op[MAX_HTM_OPERANDS], pat; - int nopnds = 0; - tree arg; - call_expr_arg_iterator iter; - unsigned attr = rs6000_builtin_info[fcode].attr; - enum insn_code icode = d->icode; - const struct insn_operand_data *insn_op; - bool uses_spr = (attr & RS6000_BTC_SPR); - rtx cr = NULL_RTX; - - if (uses_spr) - icode = rs6000_htm_spr_icode (nonvoid); - insn_op = &insn_data[icode].operand[0]; - - if (nonvoid) - { - machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode; - if (!target - || GET_MODE (target) != tmode - || (uses_spr && !(*insn_op->predicate) (target, tmode))) - target = gen_reg_rtx (tmode); - if (uses_spr) - op[nopnds++] = target; - } - - FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) - { - if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS) - return const0_rtx; - - insn_op = &insn_data[icode].operand[nopnds]; - - op[nopnds] = expand_normal (arg); - - if (!(*insn_op->predicate) (op[nopnds], insn_op->mode)) - { - if (!strcmp (insn_op->constraint, "n")) - { - int arg_num = (nonvoid) ? nopnds : nopnds + 1; - if (!CONST_INT_P (op[nopnds])) - error ("argument %d must be an unsigned literal", arg_num); - else - error ("argument %d is an unsigned literal that is " - "out of range", arg_num); - return const0_rtx; - } - op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]); - } - - nopnds++; - } - - /* Handle the builtins for extended mnemonics. These accept - no arguments, but map to builtins that take arguments. */ - switch (fcode) - { - case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */ - case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */ - op[nopnds++] = GEN_INT (1); - if (flag_checking) - attr |= RS6000_BTC_UNARY; - break; - case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */ - op[nopnds++] = GEN_INT (0); - if (flag_checking) - attr |= RS6000_BTC_UNARY; - break; - default: - break; - } - - /* If this builtin accesses SPRs, then pass in the appropriate - SPR number and SPR regno as the last two operands. */ - if (uses_spr) - { - machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode; - op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode)); - } - /* If this builtin accesses a CR, then pass in a scratch - CR as the last operand. */ - else if (attr & RS6000_BTC_CR) - { cr = gen_reg_rtx (CCmode); - op[nopnds++] = cr; - } - - if (flag_checking) - { - int expected_nopnds = 0; - if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_UNARY) - expected_nopnds = 1; - else if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_BINARY) - expected_nopnds = 2; - else if ((attr & RS6000_BTC_OPND_MASK) == RS6000_BTC_TERNARY) - expected_nopnds = 3; - else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_QUATERNARY) - expected_nopnds = 4; - if (!(attr & RS6000_BTC_VOID)) - expected_nopnds += 1; - if (uses_spr) - expected_nopnds += 1; - - gcc_assert (nopnds == expected_nopnds - && nopnds <= MAX_HTM_OPERANDS); - } - - switch (nopnds) - { - case 1: - pat = GEN_FCN (icode) (op[0]); - break; - case 2: - pat = GEN_FCN (icode) (op[0], op[1]); - break; - case 3: - pat = GEN_FCN (icode) (op[0], op[1], op[2]); - break; - case 4: - pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); - break; - default: - gcc_unreachable (); - } - if (!pat) - return NULL_RTX; - emit_insn (pat); - - if (attr & RS6000_BTC_CR) - { - if (fcode == HTM_BUILTIN_TBEGIN) - { - /* Emit code to set TARGET to true or false depending on - whether the tbegin. instruction successfully or failed - to start a transaction. We do this by placing the 1's - complement of CR's EQ bit into TARGET. */ - rtx scratch = gen_reg_rtx (SImode); - emit_insn (gen_rtx_SET (scratch, - gen_rtx_EQ (SImode, cr, - const0_rtx))); - emit_insn (gen_rtx_SET (target, - gen_rtx_XOR (SImode, scratch, - GEN_INT (1)))); - } - else - { - /* Emit code to copy the 4-bit condition register field - CR into the least significant end of register TARGET. */ - rtx scratch1 = gen_reg_rtx (SImode); - rtx scratch2 = gen_reg_rtx (SImode); - rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0); - emit_insn (gen_movcc (subreg, cr)); - emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28))); - emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf))); - } - } - - if (nonvoid) - return target; - return const0_rtx; - } - - *expandedp = false; - return NULL_RTX; } -/* Expand the CPU builtin in FCODE and store the result in TARGET. */ +/* Check whether a builtin function is supported in this target + configuration. */ +bool +rs6000_new_builtin_is_supported (enum rs6000_gen_builtins fncode) +{ + switch (rs6000_builtin_info_x[(size_t) fncode].enable) + { + case ENB_ALWAYS: + return true; + case ENB_P5: + return TARGET_POPCNTB; + case ENB_P6: + return TARGET_CMPB; + case ENB_P6_64: + return TARGET_CMPB && TARGET_POWERPC64; + case ENB_P7: + return TARGET_POPCNTD; + case ENB_P7_64: + return TARGET_POPCNTD && TARGET_POWERPC64; + case ENB_P8: + return TARGET_DIRECT_MOVE; + case ENB_P8V: + return TARGET_P8_VECTOR; + case ENB_P9: + return TARGET_MODULO; + case ENB_P9_64: + return TARGET_MODULO && TARGET_POWERPC64; + case ENB_P9V: + return TARGET_P9_VECTOR; + case ENB_P10: + return TARGET_POWER10; + case ENB_P10_64: + return TARGET_POWER10 && TARGET_POWERPC64; + case ENB_ALTIVEC: + return TARGET_ALTIVEC; + case ENB_VSX: + return TARGET_VSX; + case ENB_CELL: + return TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL; + case ENB_IEEE128_HW: + return TARGET_FLOAT128_HW; + case ENB_DFP: + return TARGET_DFP; + case ENB_CRYPTO: + return TARGET_CRYPTO; + case ENB_HTM: + return TARGET_HTM; + case ENB_MMA: + return TARGET_MMA; + default: + gcc_unreachable (); + } + gcc_unreachable (); +} -static rtx -cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED, - rtx target) +/* Expand the MMA built-ins early, so that we can convert the pass-by-reference + __vector_quad arguments into pass-by-value arguments, leading to more + efficient code generation. */ +static bool +rs6000_gimple_fold_new_mma_builtin (gimple_stmt_iterator *gsi, + rs6000_gen_builtins fn_code) { - /* __builtin_cpu_init () is a nop, so expand to nothing. */ - if (fcode == RS6000_BUILTIN_CPU_INIT) - return const0_rtx; + gimple *stmt = gsi_stmt (*gsi); + size_t fncode = (size_t) fn_code; - if (target == 0 || GET_MODE (target) != SImode) - target = gen_reg_rtx (SImode); + if (!bif_is_mma (rs6000_builtin_info_x[fncode])) + return false; -#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB - tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0); - /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back - to a STRING_CST. */ - if (TREE_CODE (arg) == ARRAY_REF - && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST - && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST - && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0) - arg = TREE_OPERAND (arg, 0); + /* Each call that can be gimple-expanded has an associated built-in + function that it will expand into. If this one doesn't, we have + already expanded it! Exceptions: lxvp and stxvp. */ + if (rs6000_builtin_info_x[fncode].assoc_bif == RS6000_BIF_NONE + && fncode != RS6000_BIF_LXVP + && fncode != RS6000_BIF_STXVP) + return false; - if (TREE_CODE (arg) != STRING_CST) - { - error ("builtin %qs only accepts a string argument", - rs6000_builtin_info[(size_t) fcode].name); - return const0_rtx; - } + bifdata *bd = &rs6000_builtin_info_x[fncode]; + unsigned nopnds = bd->nargs; + gimple_seq new_seq = NULL; + gimple *new_call; + tree new_decl; + + /* Compatibility built-ins; we used to call these + __builtin_mma_{dis,}assemble_pair, but now we call them + __builtin_vsx_{dis,}assemble_pair. Handle the old versions. */ + if (fncode == RS6000_BIF_ASSEMBLE_PAIR) + fncode = RS6000_BIF_ASSEMBLE_PAIR_V; + else if (fncode == RS6000_BIF_DISASSEMBLE_PAIR) + fncode = RS6000_BIF_DISASSEMBLE_PAIR_V; - if (fcode == RS6000_BUILTIN_CPU_IS) + if (fncode == RS6000_BIF_DISASSEMBLE_ACC + || fncode == RS6000_BIF_DISASSEMBLE_PAIR_V) { - const char *cpu = TREE_STRING_POINTER (arg); - rtx cpuid = NULL_RTX; - for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++) - if (strcmp (cpu, cpu_is_info[i].cpu) == 0) - { - /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */ - cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM); - break; - } - if (cpuid == NULL_RTX) + /* This is an MMA disassemble built-in function. */ + push_gimplify_context (true); + unsigned nvec = (fncode == RS6000_BIF_DISASSEMBLE_ACC) ? 4 : 2; + tree dst_ptr = gimple_call_arg (stmt, 0); + tree src_ptr = gimple_call_arg (stmt, 1); + tree src_type = TREE_TYPE (src_ptr); + tree src = create_tmp_reg_or_ssa_name (TREE_TYPE (src_type)); + gimplify_assign (src, build_simple_mem_ref (src_ptr), &new_seq); + + /* If we are not disassembling an accumulator/pair or our destination is + another accumulator/pair, then just copy the entire thing as is. */ + if ((fncode == RS6000_BIF_DISASSEMBLE_ACC + && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_quad_type_node) + || (fncode == RS6000_BIF_DISASSEMBLE_PAIR_V + && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_pair_type_node)) { - /* Invalid CPU argument. */ - error ("cpu %qs is an invalid argument to builtin %qs", - cpu, rs6000_builtin_info[(size_t) fcode].name); - return const0_rtx; + tree dst = build_simple_mem_ref (build1 (VIEW_CONVERT_EXPR, + src_type, dst_ptr)); + gimplify_assign (dst, src, &new_seq); + pop_gimplify_context (NULL); + gsi_replace_with_seq (gsi, new_seq, true); + return true; } - rtx platform = gen_reg_rtx (SImode); - rtx tcbmem = gen_const_mem (SImode, - gen_rtx_PLUS (Pmode, - gen_rtx_REG (Pmode, TLS_REGNUM), - GEN_INT (TCB_PLATFORM_OFFSET))); - emit_move_insn (platform, tcbmem); - emit_insn (gen_eqsi3 (target, platform, cpuid)); - } - else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS) - { - const char *hwcap = TREE_STRING_POINTER (arg); - rtx mask = NULL_RTX; - int hwcap_offset; - for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++) - if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0) - { - mask = GEN_INT (cpu_supports_info[i].mask); - hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id); - break; - } - if (mask == NULL_RTX) + /* If we're disassembling an accumulator into a different type, we need + to emit a xxmfacc instruction now, since we cannot do it later. */ + if (fncode == RS6000_BIF_DISASSEMBLE_ACC) { - /* Invalid HWCAP argument. */ - error ("%s %qs is an invalid argument to builtin %qs", - "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name); - return const0_rtx; + new_decl = rs6000_builtin_decls_x[RS6000_BIF_XXMFACC_INTERNAL]; + new_call = gimple_build_call (new_decl, 1, src); + src = create_tmp_reg_or_ssa_name (vector_quad_type_node); + gimple_call_set_lhs (new_call, src); + gimple_seq_add_stmt (&new_seq, new_call); } - rtx tcb_hwcap = gen_reg_rtx (SImode); - rtx tcbmem = gen_const_mem (SImode, - gen_rtx_PLUS (Pmode, - gen_rtx_REG (Pmode, TLS_REGNUM), - GEN_INT (hwcap_offset))); - emit_move_insn (tcb_hwcap, tcbmem); - rtx scratch1 = gen_reg_rtx (SImode); - emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask))); - rtx scratch2 = gen_reg_rtx (SImode); - emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx)); - emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx))); + /* Copy the accumulator/pair vector by vector. */ + new_decl + = rs6000_builtin_decls_x[rs6000_builtin_info_x[fncode].assoc_bif]; + tree dst_type = build_pointer_type_for_mode (unsigned_V16QI_type_node, + ptr_mode, true); + tree dst_base = build1 (VIEW_CONVERT_EXPR, dst_type, dst_ptr); + for (unsigned i = 0; i < nvec; i++) + { + unsigned index = WORDS_BIG_ENDIAN ? i : nvec - 1 - i; + tree dst = build2 (MEM_REF, unsigned_V16QI_type_node, dst_base, + build_int_cst (dst_type, index * 16)); + tree dstssa = create_tmp_reg_or_ssa_name (unsigned_V16QI_type_node); + new_call = gimple_build_call (new_decl, 2, src, + build_int_cstu (uint16_type_node, i)); + gimple_call_set_lhs (new_call, dstssa); + gimple_seq_add_stmt (&new_seq, new_call); + gimplify_assign (dst, dstssa, &new_seq); + } + pop_gimplify_context (NULL); + gsi_replace_with_seq (gsi, new_seq, true); + return true; } - else - gcc_unreachable (); - - /* Record that we have expanded a CPU builtin, so that we can later - emit a reference to the special symbol exported by LIBC to ensure we - do not link against an old LIBC that doesn't support this feature. */ - cpu_builtin_p = true; - -#else - warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware " - "capability bits", rs6000_builtin_info[(size_t) fcode].name); - - /* For old LIBCs, always return FALSE. */ - emit_move_insn (target, GEN_INT (0)); -#endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */ - - return target; -} - -static rtx -rs6000_expand_quaternop_builtin (enum insn_code icode, tree exp, rtx target) -{ - rtx pat; - tree arg0 = CALL_EXPR_ARG (exp, 0); - tree arg1 = CALL_EXPR_ARG (exp, 1); - tree arg2 = CALL_EXPR_ARG (exp, 2); - tree arg3 = CALL_EXPR_ARG (exp, 3); - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - rtx op2 = expand_normal (arg2); - rtx op3 = expand_normal (arg3); - machine_mode tmode = insn_data[icode].operand[0].mode; - machine_mode mode0 = insn_data[icode].operand[1].mode; - machine_mode mode1 = insn_data[icode].operand[2].mode; - machine_mode mode2 = insn_data[icode].operand[3].mode; - machine_mode mode3 = insn_data[icode].operand[4].mode; - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; + /* TODO: Do some factoring on these two chunks. */ + if (fncode == RS6000_BIF_LXVP) + { + push_gimplify_context (true); + tree offset = gimple_call_arg (stmt, 0); + tree ptr = gimple_call_arg (stmt, 1); + tree lhs = gimple_call_lhs (stmt); + if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) + ptr = build1 (VIEW_CONVERT_EXPR, + build_pointer_type (vector_pair_type_node), ptr); + tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, + TREE_TYPE (ptr), ptr, offset)); + gimplify_assign (lhs, mem, &new_seq); + pop_gimplify_context (NULL); + gsi_replace_with_seq (gsi, new_seq, true); + return true; + } - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node - || arg1 == error_mark_node - || arg2 == error_mark_node - || arg3 == error_mark_node) - return const0_rtx; + if (fncode == RS6000_BIF_STXVP) + { + push_gimplify_context (true); + tree src = gimple_call_arg (stmt, 0); + tree offset = gimple_call_arg (stmt, 1); + tree ptr = gimple_call_arg (stmt, 2); + if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) + ptr = build1 (VIEW_CONVERT_EXPR, + build_pointer_type (vector_pair_type_node), ptr); + tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, + TREE_TYPE (ptr), ptr, offset)); + gimplify_assign (mem, src, &new_seq); + pop_gimplify_context (NULL); + gsi_replace_with_seq (gsi, new_seq, true); + return true; + } - /* Check and prepare argument depending on the instruction code. + /* Convert this built-in into an internal version that uses pass-by-value + arguments. The internal built-in is found in the assoc_bif field. */ + new_decl = rs6000_builtin_decls_x[rs6000_builtin_info_x[fncode].assoc_bif]; + tree lhs, op[MAX_MMA_OPERANDS]; + tree acc = gimple_call_arg (stmt, 0); + push_gimplify_context (true); - Note that a switch statement instead of the sequence of tests - would be incorrect as many of the CODE_FOR values could be - CODE_FOR_nothing and that would yield multiple alternatives - with identical values. We'd never reach here at runtime in - this case. */ - if (icode == CODE_FOR_xxeval) + if (bif_is_quad (*bd)) { - /* Only allow 8-bit unsigned literals. */ - STRIP_NOPS (arg3); - if (TREE_CODE (arg3) != INTEGER_CST - || TREE_INT_CST_LOW (arg3) & ~0xff) - { - error ("argument 4 must be an 8-bit unsigned literal"); - return CONST0_RTX (tmode); - } + /* This built-in has a pass-by-reference accumulator input, so load it + into a temporary accumulator for use as a pass-by-value input. */ + op[0] = create_tmp_reg_or_ssa_name (vector_quad_type_node); + for (unsigned i = 1; i < nopnds; i++) + op[i] = gimple_call_arg (stmt, i); + gimplify_assign (op[0], build_simple_mem_ref (acc), &new_seq); + } + else + { + /* This built-in does not use its pass-by-reference accumulator argument + as an input argument, so remove it from the input list. */ + nopnds--; + for (unsigned i = 0; i < nopnds; i++) + op[i] = gimple_call_arg (stmt, i + 1); } - else if (icode == CODE_FOR_xxpermx) + switch (nopnds) { - /* Only allow 3-bit unsigned literals. */ - STRIP_NOPS (arg3); - if (TREE_CODE (arg3) != INTEGER_CST - || TREE_INT_CST_LOW (arg3) & ~0x7) - { - error ("argument 4 must be a 3-bit unsigned literal"); - return CONST0_RTX (tmode); - } + case 0: + new_call = gimple_build_call (new_decl, 0); + break; + case 1: + new_call = gimple_build_call (new_decl, 1, op[0]); + break; + case 2: + new_call = gimple_build_call (new_decl, 2, op[0], op[1]); + break; + case 3: + new_call = gimple_build_call (new_decl, 3, op[0], op[1], op[2]); + break; + case 4: + new_call = gimple_build_call (new_decl, 4, op[0], op[1], op[2], op[3]); + break; + case 5: + new_call = gimple_build_call (new_decl, 5, op[0], op[1], op[2], op[3], + op[4]); + break; + case 6: + new_call = gimple_build_call (new_decl, 6, op[0], op[1], op[2], op[3], + op[4], op[5]); + break; + case 7: + new_call = gimple_build_call (new_decl, 7, op[0], op[1], op[2], op[3], + op[4], op[5], op[6]); + break; + default: + gcc_unreachable (); } - else if (icode == CODE_FOR_vreplace_elt_v4si - || icode == CODE_FOR_vreplace_elt_v4sf) - { - /* Check whether the 3rd argument is an integer constant in the range - 0 to 3 inclusive. */ - STRIP_NOPS (arg2); - if (TREE_CODE (arg2) != INTEGER_CST - || !IN_RANGE (TREE_INT_CST_LOW (arg2), 0, 3)) - { - error ("argument 3 must be in the range 0 to 3"); - return CONST0_RTX (tmode); - } - } - - else if (icode == CODE_FOR_vreplace_un_v4si - || icode == CODE_FOR_vreplace_un_v4sf) - { - /* Check whether the 3rd argument is an integer constant in the range - 0 to 12 inclusive. */ - STRIP_NOPS (arg2); - if (TREE_CODE (arg2) != INTEGER_CST - || !IN_RANGE(TREE_INT_CST_LOW (arg2), 0, 12)) - { - error ("argument 3 must be in the range 0 to 12"); - return CONST0_RTX (tmode); - } - } - - else if (icode == CODE_FOR_vsldb_v16qi - || icode == CODE_FOR_vsldb_v8hi - || icode == CODE_FOR_vsldb_v4si - || icode == CODE_FOR_vsldb_v2di - || icode == CODE_FOR_vsrdb_v16qi - || icode == CODE_FOR_vsrdb_v8hi - || icode == CODE_FOR_vsrdb_v4si - || icode == CODE_FOR_vsrdb_v2di) - { - /* Check whether the 3rd argument is an integer constant in the range - 0 to 7 inclusive. */ - STRIP_NOPS (arg2); - if (TREE_CODE (arg2) != INTEGER_CST - || !IN_RANGE (TREE_INT_CST_LOW (arg2), 0, 7)) - { - error ("argument 3 must be a constant in the range 0 to 7"); - return CONST0_RTX (tmode); - } - } + if (fncode == RS6000_BIF_BUILD_PAIR || fncode == RS6000_BIF_ASSEMBLE_PAIR_V) + lhs = create_tmp_reg_or_ssa_name (vector_pair_type_node); + else + lhs = create_tmp_reg_or_ssa_name (vector_quad_type_node); + gimple_call_set_lhs (new_call, lhs); + gimple_seq_add_stmt (&new_seq, new_call); + gimplify_assign (build_simple_mem_ref (acc), lhs, &new_seq); + pop_gimplify_context (NULL); + gsi_replace_with_seq (gsi, new_seq, true); - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); + return true; +} - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) - op2 = copy_to_mode_reg (mode2, op2); - if (! (*insn_data[icode].operand[4].predicate) (op3, mode3)) - op3 = copy_to_mode_reg (mode3, op3); +/* Fold a machine-dependent built-in in GIMPLE. (For folding into + a constant, use rs6000_fold_builtin.) */ +static bool +rs6000_gimple_fold_new_builtin (gimple_stmt_iterator *gsi) +{ + gimple *stmt = gsi_stmt (*gsi); + tree fndecl = gimple_call_fndecl (stmt); + gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD); + enum rs6000_gen_builtins fn_code + = (enum rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl); + tree arg0, arg1, lhs, temp; + enum tree_code bcode; + gimple *g; - pat = GEN_FCN (icode) (target, op0, op1, op2, op3); - if (! pat) - return 0; - emit_insn (pat); + size_t uns_fncode = (size_t) fn_code; + enum insn_code icode = rs6000_builtin_info_x[uns_fncode].icode; + const char *fn_name1 = rs6000_builtin_info_x[uns_fncode].bifname; + const char *fn_name2 = (icode != CODE_FOR_nothing) + ? get_insn_name ((int) icode) + : "nothing"; - return target; -} + if (TARGET_DEBUG_BUILTIN) + fprintf (stderr, "rs6000_gimple_fold_new_builtin %d %s %s\n", + fn_code, fn_name1, fn_name2); -static rtx -rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target) -{ - rtx pat; - tree arg0 = CALL_EXPR_ARG (exp, 0); - tree arg1 = CALL_EXPR_ARG (exp, 1); - tree arg2 = CALL_EXPR_ARG (exp, 2); - rtx op0 = expand_normal (arg0); - rtx op1 = expand_normal (arg1); - rtx op2 = expand_normal (arg2); - machine_mode tmode = insn_data[icode].operand[0].mode; - machine_mode mode0 = insn_data[icode].operand[1].mode; - machine_mode mode1 = insn_data[icode].operand[2].mode; - machine_mode mode2 = insn_data[icode].operand[3].mode; + if (!rs6000_fold_gimple) + return false; - if (icode == CODE_FOR_nothing) - /* Builtin not supported on this processor. */ - return 0; + /* Prevent gimple folding for code that does not have a LHS, unless it is + allowed per the rs6000_new_builtin_valid_without_lhs helper function. */ + if (!gimple_call_lhs (stmt) + && !rs6000_new_builtin_valid_without_lhs (fn_code, fndecl)) + return false; - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node - || arg1 == error_mark_node - || arg2 == error_mark_node) - return const0_rtx; + /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */ + if (!rs6000_new_builtin_is_supported (fn_code)) + return false; - /* Check and prepare argument depending on the instruction code. - - Note that a switch statement instead of the sequence of tests - would be incorrect as many of the CODE_FOR values could be - CODE_FOR_nothing and that would yield multiple alternatives - with identical values. We'd never reach here at runtime in - this case. */ - if (icode == CODE_FOR_altivec_vsldoi_v4sf - || icode == CODE_FOR_altivec_vsldoi_v2df - || icode == CODE_FOR_altivec_vsldoi_v4si - || icode == CODE_FOR_altivec_vsldoi_v8hi - || icode == CODE_FOR_altivec_vsldoi_v16qi) - { - /* Only allow 4-bit unsigned literals. */ - STRIP_NOPS (arg2); - if (TREE_CODE (arg2) != INTEGER_CST - || TREE_INT_CST_LOW (arg2) & ~0xf) - { - error ("argument 3 must be a 4-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_vsx_xxpermdi_v2df - || icode == CODE_FOR_vsx_xxpermdi_v2di - || icode == CODE_FOR_vsx_xxpermdi_v2df_be - || icode == CODE_FOR_vsx_xxpermdi_v2di_be - || icode == CODE_FOR_vsx_xxpermdi_v1ti - || icode == CODE_FOR_vsx_xxpermdi_v4sf - || icode == CODE_FOR_vsx_xxpermdi_v4si - || icode == CODE_FOR_vsx_xxpermdi_v8hi - || icode == CODE_FOR_vsx_xxpermdi_v16qi - || icode == CODE_FOR_vsx_xxsldwi_v16qi - || icode == CODE_FOR_vsx_xxsldwi_v8hi - || icode == CODE_FOR_vsx_xxsldwi_v4si - || icode == CODE_FOR_vsx_xxsldwi_v4sf - || icode == CODE_FOR_vsx_xxsldwi_v2di - || icode == CODE_FOR_vsx_xxsldwi_v2df) + if (rs6000_gimple_fold_new_mma_builtin (gsi, fn_code)) + return true; + + switch (fn_code) { - /* Only allow 2-bit unsigned literals. */ - STRIP_NOPS (arg2); - if (TREE_CODE (arg2) != INTEGER_CST - || TREE_INT_CST_LOW (arg2) & ~0x3) + /* Flavors of vec_add. We deliberately don't expand + RS6000_BIF_VADDUQM as it gets lowered from V1TImode to + TImode, resulting in much poorer code generation. */ + case RS6000_BIF_VADDUBM: + case RS6000_BIF_VADDUHM: + case RS6000_BIF_VADDUWM: + case RS6000_BIF_VADDUDM: + case RS6000_BIF_VADDFP: + case RS6000_BIF_XVADDDP: + case RS6000_BIF_XVADDSP: + bcode = PLUS_EXPR; + do_binary: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs))) + && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs)))) { - error ("argument 3 must be a 2-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_vsx_set_v2df - || icode == CODE_FOR_vsx_set_v2di - || icode == CODE_FOR_bcdadd_v16qi - || icode == CODE_FOR_bcdadd_v1ti - || icode == CODE_FOR_bcdadd_lt_v16qi - || icode == CODE_FOR_bcdadd_lt_v1ti - || icode == CODE_FOR_bcdadd_eq_v16qi - || icode == CODE_FOR_bcdadd_eq_v1ti - || icode == CODE_FOR_bcdadd_gt_v16qi - || icode == CODE_FOR_bcdadd_gt_v1ti - || icode == CODE_FOR_bcdsub_v16qi - || icode == CODE_FOR_bcdsub_v1ti - || icode == CODE_FOR_bcdsub_lt_v16qi - || icode == CODE_FOR_bcdsub_lt_v1ti - || icode == CODE_FOR_bcdsub_eq_v16qi - || icode == CODE_FOR_bcdsub_eq_v1ti - || icode == CODE_FOR_bcdsub_gt_v16qi - || icode == CODE_FOR_bcdsub_gt_v1ti) - { - /* Only allow 1-bit unsigned literals. */ - STRIP_NOPS (arg2); - if (TREE_CODE (arg2) != INTEGER_CST - || TREE_INT_CST_LOW (arg2) & ~0x1) - { - error ("argument 3 must be a 1-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_dfp_ddedpd_dd - || icode == CODE_FOR_dfp_ddedpd_td) - { - /* Only allow 2-bit unsigned literals where the value is 0 or 2. */ - STRIP_NOPS (arg0); - if (TREE_CODE (arg0) != INTEGER_CST - || TREE_INT_CST_LOW (arg2) & ~0x3) - { - error ("argument 1 must be 0 or 2"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_dfp_denbcd_dd - || icode == CODE_FOR_dfp_denbcd_td - || icode == CODE_FOR_dfp_denbcd_v16qi) - { - /* Only allow 1-bit unsigned literals. */ - STRIP_NOPS (arg0); - if (TREE_CODE (arg0) != INTEGER_CST - || TREE_INT_CST_LOW (arg0) & ~0x1) - { - error ("argument 1 must be a 1-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_dfp_dscli_dd - || icode == CODE_FOR_dfp_dscli_td - || icode == CODE_FOR_dfp_dscri_dd - || icode == CODE_FOR_dfp_dscri_td) - { - /* Only allow 6-bit unsigned literals. */ - STRIP_NOPS (arg1); - if (TREE_CODE (arg1) != INTEGER_CST - || TREE_INT_CST_LOW (arg1) & ~0x3f) - { - error ("argument 2 must be a 6-bit unsigned literal"); - return CONST0_RTX (tmode); - } - } - else if (icode == CODE_FOR_crypto_vshasigmaw - || icode == CODE_FOR_crypto_vshasigmad) - { - /* Check whether the 2nd and 3rd arguments are integer constants and in - range and prepare arguments. */ - STRIP_NOPS (arg1); - if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2)) - { - error ("argument 2 must be 0 or 1"); - return CONST0_RTX (tmode); - } - - STRIP_NOPS (arg2); - if (TREE_CODE (arg2) != INTEGER_CST - || wi::geu_p (wi::to_wide (arg2), 16)) - { - error ("argument 3 must be in the range [0, 15]"); - return CONST0_RTX (tmode); - } - } - - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) - op2 = copy_to_mode_reg (mode2, op2); - - pat = GEN_FCN (icode) (target, op0, op1, op2); - if (! pat) - return 0; - emit_insn (pat); - - return target; -} - - -/* Expand the dst builtins. */ -static rtx -altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, - bool *expandedp) -{ - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - enum rs6000_builtins fcode - = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); - tree arg0, arg1, arg2; - machine_mode mode0, mode1; - rtx pat, op0, op1, op2; - const struct builtin_description *d; - size_t i; - - *expandedp = false; - - /* Handle DST variants. */ - d = bdesc_dst; - for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) - if (d->code == fcode) - { - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - arg2 = CALL_EXPR_ARG (exp, 2); - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - op2 = expand_normal (arg2); - mode0 = insn_data[d->icode].operand[0].mode; - mode1 = insn_data[d->icode].operand[1].mode; - - /* Invalid arguments, bail out before generating bad rtl. */ - if (arg0 == error_mark_node - || arg1 == error_mark_node - || arg2 == error_mark_node) - return const0_rtx; - - *expandedp = true; - STRIP_NOPS (arg2); - if (TREE_CODE (arg2) != INTEGER_CST - || TREE_INT_CST_LOW (arg2) & ~0x3) - { - error ("argument to %qs must be a 2-bit unsigned literal", d->name); - return const0_rtx; - } - - if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (Pmode, op0); - if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - - pat = GEN_FCN (d->icode) (op0, op1, op2); - if (pat != 0) - emit_insn (pat); - - return NULL_RTX; - } - - return NULL_RTX; -} - -/* Expand vec_init builtin. */ -static rtx -altivec_expand_vec_init_builtin (tree type, tree exp, rtx target) -{ - machine_mode tmode = TYPE_MODE (type); - machine_mode inner_mode = GET_MODE_INNER (tmode); - int i, n_elt = GET_MODE_NUNITS (tmode); - - gcc_assert (VECTOR_MODE_P (tmode)); - gcc_assert (n_elt == call_expr_nargs (exp)); - - if (!target || !register_operand (target, tmode)) - target = gen_reg_rtx (tmode); - - /* If we have a vector compromised of a single element, such as V1TImode, do - the initialization directly. */ - if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode)) - { - rtx x = expand_normal (CALL_EXPR_ARG (exp, 0)); - emit_move_insn (target, gen_lowpart (tmode, x)); - } - else - { - rtvec v = rtvec_alloc (n_elt); - - for (i = 0; i < n_elt; ++i) - { - rtx x = expand_normal (CALL_EXPR_ARG (exp, i)); - RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x); + /* Ensure the binary operation is performed in a type + that wraps if it is integral type. */ + gimple_seq stmts = NULL; + tree type = unsigned_type_for (TREE_TYPE (lhs)); + tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR, + type, arg0); + tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, + type, arg1); + tree res = gimple_build (&stmts, gimple_location (stmt), bcode, + type, uarg0, uarg1); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, + build1 (VIEW_CONVERT_EXPR, + TREE_TYPE (lhs), res)); + gsi_replace (gsi, g, true); + return true; } - - rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v)); - } - - return target; -} - -/* Return the integer constant in ARG. Constrain it to be in the range - of the subparts of VEC_TYPE; issue an error if not. */ - -static int -get_element_number (tree vec_type, tree arg) -{ - unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1; - - if (!tree_fits_uhwi_p (arg) - || (elt = tree_to_uhwi (arg), elt > max)) - { - error ("selector must be an integer constant in the range [0, %wi]", max); - return 0; - } - - return elt; -} - -/* Expand vec_set builtin. */ -static rtx -altivec_expand_vec_set_builtin (tree exp) -{ - machine_mode tmode, mode1; - tree arg0, arg1, arg2; - int elt; - rtx op0, op1; - - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - arg2 = CALL_EXPR_ARG (exp, 2); - - tmode = TYPE_MODE (TREE_TYPE (arg0)); - mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); - gcc_assert (VECTOR_MODE_P (tmode)); - - op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL); - elt = get_element_number (TREE_TYPE (arg0), arg2); - - if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode) - op1 = convert_modes (mode1, GET_MODE (op1), op1, true); - - op0 = force_reg (tmode, op0); - op1 = force_reg (mode1, op1); - - rs6000_expand_vector_set (op0, op1, GEN_INT (elt)); - - return op0; -} - -/* Expand vec_ext builtin. */ -static rtx -altivec_expand_vec_ext_builtin (tree exp, rtx target) -{ - machine_mode tmode, mode0; - tree arg0, arg1; - rtx op0; - rtx op1; - - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - - op0 = expand_normal (arg0); - op1 = expand_normal (arg1); - - if (TREE_CODE (arg1) == INTEGER_CST) - { - unsigned HOST_WIDE_INT elt; - unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0)); - unsigned int truncated_selector; - /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0) - returns low-order bits of INTEGER_CST for modulo indexing. */ - elt = TREE_INT_CST_LOW (arg1); - truncated_selector = elt % size; - op1 = GEN_INT (truncated_selector); - } - - tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); - mode0 = TYPE_MODE (TREE_TYPE (arg0)); - gcc_assert (VECTOR_MODE_P (mode0)); - - op0 = force_reg (mode0, op0); - - if (optimize || !target || !register_operand (target, tmode)) - target = gen_reg_rtx (tmode); - - rs6000_expand_vector_extract (target, op0, op1); - - return target; -} - -/* Expand vec_sel builtin. */ -static rtx -altivec_expand_vec_sel_builtin (enum insn_code icode, tree exp, rtx target) -{ - rtx op0, op1, op2, pat; - tree arg0, arg1, arg2; - - arg0 = CALL_EXPR_ARG (exp, 0); - op0 = expand_normal (arg0); - arg1 = CALL_EXPR_ARG (exp, 1); - op1 = expand_normal (arg1); - arg2 = CALL_EXPR_ARG (exp, 2); - op2 = expand_normal (arg2); - - machine_mode tmode = insn_data[icode].operand[0].mode; - machine_mode mode0 = insn_data[icode].operand[1].mode; - machine_mode mode1 = insn_data[icode].operand[2].mode; - machine_mode mode2 = insn_data[icode].operand[3].mode; - - if (target == 0 || GET_MODE (target) != tmode - || !(*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - - if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (!(*insn_data[icode].operand[3].predicate) (op2, mode2)) - op2 = copy_to_mode_reg (mode2, op2); - - pat = GEN_FCN (icode) (target, op0, op1, op2, op2); - if (pat) - emit_insn (pat); - else - return NULL_RTX; - - return target; -} - -/* Expand the builtin in EXP and store the result in TARGET. Store - true in *EXPANDEDP if we found a builtin to expand. */ -static rtx -altivec_expand_builtin (tree exp, rtx target, bool *expandedp) -{ - const struct builtin_description *d; - size_t i; - enum insn_code icode; - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - tree arg0, arg1, arg2; - rtx op0, pat; - machine_mode tmode, mode0; - enum rs6000_builtins fcode - = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); - - if (rs6000_overloaded_builtin_p (fcode)) - { - *expandedp = true; - error ("unresolved overload for Altivec builtin %qF", fndecl); - - /* Given it is invalid, just generate a normal call. */ - return expand_call (exp, target, false); - } - - target = altivec_expand_dst_builtin (exp, target, expandedp); - if (*expandedp) - return target; - - *expandedp = true; - - switch (fcode) - { - case ALTIVEC_BUILTIN_STVX_V2DF: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp); - case ALTIVEC_BUILTIN_STVX_V2DI: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp); - case ALTIVEC_BUILTIN_STVX_V4SF: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp); - case ALTIVEC_BUILTIN_STVX: - case ALTIVEC_BUILTIN_STVX_V4SI: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp); - case ALTIVEC_BUILTIN_STVX_V8HI: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp); - case ALTIVEC_BUILTIN_STVX_V16QI: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp); - case ALTIVEC_BUILTIN_STVEBX: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp); - case ALTIVEC_BUILTIN_STVEHX: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp); - case ALTIVEC_BUILTIN_STVEWX: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp); - - case P10_BUILTIN_TR_STXVRBX: - return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrbx, exp); - case P10_BUILTIN_TR_STXVRHX: - return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrhx, exp); - case P10_BUILTIN_TR_STXVRWX: - return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrwx, exp); - case P10_BUILTIN_TR_STXVRDX: - return altivec_expand_stv_builtin (CODE_FOR_vsx_stxvrdx, exp); - - case ALTIVEC_BUILTIN_STVXL_V2DF: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp); - case ALTIVEC_BUILTIN_STVXL_V2DI: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp); - case ALTIVEC_BUILTIN_STVXL_V4SF: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp); - case ALTIVEC_BUILTIN_STVXL: - case ALTIVEC_BUILTIN_STVXL_V4SI: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp); - case ALTIVEC_BUILTIN_STVXL_V8HI: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp); - case ALTIVEC_BUILTIN_STVXL_V16QI: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp); - - case ALTIVEC_BUILTIN_STVLX: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp); - case ALTIVEC_BUILTIN_STVLXL: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp); - case ALTIVEC_BUILTIN_STVRX: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp); - case ALTIVEC_BUILTIN_STVRXL: - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp); - - case P9V_BUILTIN_STXVL: - return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp); - - case P9V_BUILTIN_XST_LEN_R: - return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp); - - case VSX_BUILTIN_STXVD2X_V1TI: - return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp); - case VSX_BUILTIN_STXVD2X_V2DF: - return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp); - case VSX_BUILTIN_STXVD2X_V2DI: - return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp); - case VSX_BUILTIN_STXVW4X_V4SF: - return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp); - case VSX_BUILTIN_STXVW4X_V4SI: - return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp); - case VSX_BUILTIN_STXVW4X_V8HI: - return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp); - case VSX_BUILTIN_STXVW4X_V16QI: - return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp); - - /* For the following on big endian, it's ok to use any appropriate - unaligned-supporting store, so use a generic expander. For - little-endian, the exact element-reversing instruction must - be used. */ - case VSX_BUILTIN_ST_ELEMREV_V1TI: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti - : CODE_FOR_vsx_st_elemrev_v1ti); - return altivec_expand_stv_builtin (code, exp); - } - case VSX_BUILTIN_ST_ELEMREV_V2DF: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df - : CODE_FOR_vsx_st_elemrev_v2df); - return altivec_expand_stv_builtin (code, exp); - } - case VSX_BUILTIN_ST_ELEMREV_V2DI: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di - : CODE_FOR_vsx_st_elemrev_v2di); - return altivec_expand_stv_builtin (code, exp); - } - case VSX_BUILTIN_ST_ELEMREV_V4SF: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf - : CODE_FOR_vsx_st_elemrev_v4sf); - return altivec_expand_stv_builtin (code, exp); - } - case VSX_BUILTIN_ST_ELEMREV_V4SI: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si - : CODE_FOR_vsx_st_elemrev_v4si); - return altivec_expand_stv_builtin (code, exp); - } - case VSX_BUILTIN_ST_ELEMREV_V8HI: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi - : CODE_FOR_vsx_st_elemrev_v8hi); - return altivec_expand_stv_builtin (code, exp); - } - case VSX_BUILTIN_ST_ELEMREV_V16QI: + g = gimple_build_assign (lhs, bcode, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Flavors of vec_sub. We deliberately don't expand + RS6000_BIF_VSUBUQM. */ + case RS6000_BIF_VSUBUBM: + case RS6000_BIF_VSUBUHM: + case RS6000_BIF_VSUBUWM: + case RS6000_BIF_VSUBUDM: + case RS6000_BIF_VSUBFP: + case RS6000_BIF_XVSUBDP: + case RS6000_BIF_XVSUBSP: + bcode = MINUS_EXPR; + goto do_binary; + case RS6000_BIF_XVMULSP: + case RS6000_BIF_XVMULDP: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Even element flavors of vec_mul (signed). */ + case RS6000_BIF_VMULESB: + case RS6000_BIF_VMULESH: + case RS6000_BIF_VMULESW: + /* Even element flavors of vec_mul (unsigned). */ + case RS6000_BIF_VMULEUB: + case RS6000_BIF_VMULEUH: + case RS6000_BIF_VMULEUW: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Odd element flavors of vec_mul (signed). */ + case RS6000_BIF_VMULOSB: + case RS6000_BIF_VMULOSH: + case RS6000_BIF_VMULOSW: + /* Odd element flavors of vec_mul (unsigned). */ + case RS6000_BIF_VMULOUB: + case RS6000_BIF_VMULOUH: + case RS6000_BIF_VMULOUW: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Flavors of vec_div (Integer). */ + case RS6000_BIF_DIV_V2DI: + case RS6000_BIF_UDIV_V2DI: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Flavors of vec_div (Float). */ + case RS6000_BIF_XVDIVSP: + case RS6000_BIF_XVDIVDP: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Flavors of vec_and. */ + case RS6000_BIF_VAND_V16QI_UNS: + case RS6000_BIF_VAND_V16QI: + case RS6000_BIF_VAND_V8HI_UNS: + case RS6000_BIF_VAND_V8HI: + case RS6000_BIF_VAND_V4SI_UNS: + case RS6000_BIF_VAND_V4SI: + case RS6000_BIF_VAND_V2DI_UNS: + case RS6000_BIF_VAND_V2DI: + case RS6000_BIF_VAND_V4SF: + case RS6000_BIF_VAND_V2DF: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Flavors of vec_andc. */ + case RS6000_BIF_VANDC_V16QI_UNS: + case RS6000_BIF_VANDC_V16QI: + case RS6000_BIF_VANDC_V8HI_UNS: + case RS6000_BIF_VANDC_V8HI: + case RS6000_BIF_VANDC_V4SI_UNS: + case RS6000_BIF_VANDC_V4SI: + case RS6000_BIF_VANDC_V2DI_UNS: + case RS6000_BIF_VANDC_V2DI: + case RS6000_BIF_VANDC_V4SF: + case RS6000_BIF_VANDC_V2DF: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); + g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Flavors of vec_nand. */ + case RS6000_BIF_NAND_V16QI_UNS: + case RS6000_BIF_NAND_V16QI: + case RS6000_BIF_NAND_V8HI_UNS: + case RS6000_BIF_NAND_V8HI: + case RS6000_BIF_NAND_V4SI_UNS: + case RS6000_BIF_NAND_V4SI: + case RS6000_BIF_NAND_V2DI_UNS: + case RS6000_BIF_NAND_V2DI: + case RS6000_BIF_NAND_V4SF: + case RS6000_BIF_NAND_V2DF: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); + g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Flavors of vec_or. */ + case RS6000_BIF_VOR_V16QI_UNS: + case RS6000_BIF_VOR_V16QI: + case RS6000_BIF_VOR_V8HI_UNS: + case RS6000_BIF_VOR_V8HI: + case RS6000_BIF_VOR_V4SI_UNS: + case RS6000_BIF_VOR_V4SI: + case RS6000_BIF_VOR_V2DI_UNS: + case RS6000_BIF_VOR_V2DI: + case RS6000_BIF_VOR_V4SF: + case RS6000_BIF_VOR_V2DF: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* flavors of vec_orc. */ + case RS6000_BIF_ORC_V16QI_UNS: + case RS6000_BIF_ORC_V16QI: + case RS6000_BIF_ORC_V8HI_UNS: + case RS6000_BIF_ORC_V8HI: + case RS6000_BIF_ORC_V4SI_UNS: + case RS6000_BIF_ORC_V4SI: + case RS6000_BIF_ORC_V2DI_UNS: + case RS6000_BIF_ORC_V2DI: + case RS6000_BIF_ORC_V4SF: + case RS6000_BIF_ORC_V2DF: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); + g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Flavors of vec_xor. */ + case RS6000_BIF_VXOR_V16QI_UNS: + case RS6000_BIF_VXOR_V16QI: + case RS6000_BIF_VXOR_V8HI_UNS: + case RS6000_BIF_VXOR_V8HI: + case RS6000_BIF_VXOR_V4SI_UNS: + case RS6000_BIF_VXOR_V4SI: + case RS6000_BIF_VXOR_V2DI_UNS: + case RS6000_BIF_VXOR_V2DI: + case RS6000_BIF_VXOR_V4SF: + case RS6000_BIF_VXOR_V2DF: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Flavors of vec_nor. */ + case RS6000_BIF_VNOR_V16QI_UNS: + case RS6000_BIF_VNOR_V16QI: + case RS6000_BIF_VNOR_V8HI_UNS: + case RS6000_BIF_VNOR_V8HI: + case RS6000_BIF_VNOR_V4SI_UNS: + case RS6000_BIF_VNOR_V4SI: + case RS6000_BIF_VNOR_V2DI_UNS: + case RS6000_BIF_VNOR_V2DI: + case RS6000_BIF_VNOR_V4SF: + case RS6000_BIF_VNOR_V2DF: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); + g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* flavors of vec_abs. */ + case RS6000_BIF_ABS_V16QI: + case RS6000_BIF_ABS_V8HI: + case RS6000_BIF_ABS_V4SI: + case RS6000_BIF_ABS_V4SF: + case RS6000_BIF_ABS_V2DI: + case RS6000_BIF_XVABSDP: + case RS6000_BIF_XVABSSP: + arg0 = gimple_call_arg (stmt, 0); + if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0))) + && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0)))) + return false; + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, ABS_EXPR, arg0); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* flavors of vec_min. */ + case RS6000_BIF_XVMINDP: + case RS6000_BIF_XVMINSP: + case RS6000_BIF_VMINFP: { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi - : CODE_FOR_vsx_st_elemrev_v16qi); - return altivec_expand_stv_builtin (code, exp); + lhs = gimple_call_lhs (stmt); + tree type = TREE_TYPE (lhs); + if (HONOR_NANS (type)) + return false; + gcc_fallthrough (); } - - case ALTIVEC_BUILTIN_MFVSCR: - icode = CODE_FOR_altivec_mfvscr; - tmode = insn_data[icode].operand[0].mode; - - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - - pat = GEN_FCN (icode) (target); - if (! pat) - return 0; - emit_insn (pat); - return target; - - case ALTIVEC_BUILTIN_MTVSCR: - icode = CODE_FOR_altivec_mtvscr; - arg0 = CALL_EXPR_ARG (exp, 0); - op0 = expand_normal (arg0); - mode0 = insn_data[icode].operand[0].mode; - - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node) - return const0_rtx; - - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - pat = GEN_FCN (icode) (op0); - if (pat) - emit_insn (pat); - return NULL_RTX; - - case ALTIVEC_BUILTIN_VSEL_2DF: - return altivec_expand_vec_sel_builtin (CODE_FOR_altivec_vselv2df, exp, - target); - case ALTIVEC_BUILTIN_VSEL_2DI: - case ALTIVEC_BUILTIN_VSEL_2DI_UNS: - return altivec_expand_vec_sel_builtin (CODE_FOR_altivec_vselv2di, exp, - target); - case ALTIVEC_BUILTIN_VSEL_4SF: - return altivec_expand_vec_sel_builtin (CODE_FOR_altivec_vselv4sf, exp, - target); - case ALTIVEC_BUILTIN_VSEL_4SI: - case ALTIVEC_BUILTIN_VSEL_4SI_UNS: - return altivec_expand_vec_sel_builtin (CODE_FOR_altivec_vselv4si, exp, - target); - case ALTIVEC_BUILTIN_VSEL_8HI: - case ALTIVEC_BUILTIN_VSEL_8HI_UNS: - return altivec_expand_vec_sel_builtin (CODE_FOR_altivec_vselv8hi, exp, - target); - case ALTIVEC_BUILTIN_VSEL_16QI: - case ALTIVEC_BUILTIN_VSEL_16QI_UNS: - return altivec_expand_vec_sel_builtin (CODE_FOR_altivec_vselv16qi, exp, - target); - - case ALTIVEC_BUILTIN_DSSALL: - emit_insn (gen_altivec_dssall ()); - return NULL_RTX; - - case ALTIVEC_BUILTIN_DSS: - icode = CODE_FOR_altivec_dss; - arg0 = CALL_EXPR_ARG (exp, 0); - STRIP_NOPS (arg0); - op0 = expand_normal (arg0); - mode0 = insn_data[icode].operand[0].mode; - - /* If we got invalid arguments bail out before generating bad rtl. */ - if (arg0 == error_mark_node) - return const0_rtx; - - if (TREE_CODE (arg0) != INTEGER_CST - || TREE_INT_CST_LOW (arg0) & ~0x3) - { - error ("argument to %qs must be a 2-bit unsigned literal", "dss"); - return const0_rtx; - } - - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - emit_insn (gen_altivec_dss (op0)); - return NULL_RTX; - - case ALTIVEC_BUILTIN_VEC_INIT_V4SI: - case ALTIVEC_BUILTIN_VEC_INIT_V8HI: - case ALTIVEC_BUILTIN_VEC_INIT_V16QI: - case ALTIVEC_BUILTIN_VEC_INIT_V4SF: - case VSX_BUILTIN_VEC_INIT_V2DF: - case VSX_BUILTIN_VEC_INIT_V2DI: - case VSX_BUILTIN_VEC_INIT_V1TI: - return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target); - - case ALTIVEC_BUILTIN_VEC_SET_V4SI: - case ALTIVEC_BUILTIN_VEC_SET_V8HI: - case ALTIVEC_BUILTIN_VEC_SET_V16QI: - case ALTIVEC_BUILTIN_VEC_SET_V4SF: - case VSX_BUILTIN_VEC_SET_V2DF: - case VSX_BUILTIN_VEC_SET_V2DI: - case VSX_BUILTIN_VEC_SET_V1TI: - return altivec_expand_vec_set_builtin (exp); - - case ALTIVEC_BUILTIN_VEC_EXT_V4SI: - case ALTIVEC_BUILTIN_VEC_EXT_V8HI: - case ALTIVEC_BUILTIN_VEC_EXT_V16QI: - case ALTIVEC_BUILTIN_VEC_EXT_V4SF: - case VSX_BUILTIN_VEC_EXT_V2DF: - case VSX_BUILTIN_VEC_EXT_V2DI: - case VSX_BUILTIN_VEC_EXT_V1TI: - return altivec_expand_vec_ext_builtin (exp, target); - - case P9V_BUILTIN_VEC_EXTRACT4B: - arg1 = CALL_EXPR_ARG (exp, 1); - STRIP_NOPS (arg1); - - /* Generate a normal call if it is invalid. */ - if (arg1 == error_mark_node) - return expand_call (exp, target, false); - - if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12) - { - error ("second argument to %qs must be [0, 12]", "vec_vextract4b"); - return expand_call (exp, target, false); - } - break; - - case P9V_BUILTIN_VEC_INSERT4B: - arg2 = CALL_EXPR_ARG (exp, 2); - STRIP_NOPS (arg2); - - /* Generate a normal call if it is invalid. */ - if (arg2 == error_mark_node) - return expand_call (exp, target, false); - - if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12) - { - error ("third argument to %qs must be [0, 12]", "vec_vinsert4b"); - return expand_call (exp, target, false); - } - break; - - case P10_BUILTIN_VEC_XXGENPCVM: - arg1 = CALL_EXPR_ARG (exp, 1); - STRIP_NOPS (arg1); - - /* Generate a normal call if it is invalid. */ - if (arg1 == error_mark_node) - return expand_call (exp, target, false); - - if (TREE_CODE (arg1) != INTEGER_CST - || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 3)) - { - size_t uns_fcode = (size_t) fcode; - const char *name = rs6000_builtin_info[uns_fcode].name; - error ("Second argument of %qs must be in the range [0, 3].", name); - return expand_call (exp, target, false); - } - break; - - default: - break; - /* Fall through. */ - } - - /* Expand abs* operations. */ - d = bdesc_abs; - for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) - if (d->code == fcode) - return altivec_expand_abs_builtin (d->icode, exp, target); - - /* Expand the AltiVec predicates. */ - d = bdesc_altivec_preds; - for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++) - if (d->code == fcode) - return altivec_expand_predicate_builtin (d->icode, exp, target); - - /* LV* are funky. We initialized them differently. */ - switch (fcode) - { - case ALTIVEC_BUILTIN_LVSL: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl, - exp, target, false); - case ALTIVEC_BUILTIN_LVSR: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr, - exp, target, false); - case ALTIVEC_BUILTIN_LVEBX: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx, - exp, target, false); - case ALTIVEC_BUILTIN_LVEHX: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx, - exp, target, false); - case ALTIVEC_BUILTIN_LVEWX: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, - exp, target, false); - case P10_BUILTIN_SE_LXVRBX: - return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrbx, - exp, target, false, true); - case P10_BUILTIN_SE_LXVRHX: - return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrhx, - exp, target, false, true); - case P10_BUILTIN_SE_LXVRWX: - return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrwx, - exp, target, false, true); - case P10_BUILTIN_SE_LXVRDX: - return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrdx, - exp, target, false, true); - case P10_BUILTIN_ZE_LXVRBX: - return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrbx, - exp, target, false, false); - case P10_BUILTIN_ZE_LXVRHX: - return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrhx, - exp, target, false, false); - case P10_BUILTIN_ZE_LXVRWX: - return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrwx, - exp, target, false, false); - case P10_BUILTIN_ZE_LXVRDX: - return altivec_expand_lxvr_builtin (CODE_FOR_vsx_lxvrdx, - exp, target, false, false); - case ALTIVEC_BUILTIN_LVXL_V2DF: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df, - exp, target, false); - case ALTIVEC_BUILTIN_LVXL_V2DI: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di, - exp, target, false); - case ALTIVEC_BUILTIN_LVXL_V4SF: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf, - exp, target, false); - case ALTIVEC_BUILTIN_LVXL: - case ALTIVEC_BUILTIN_LVXL_V4SI: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si, - exp, target, false); - case ALTIVEC_BUILTIN_LVXL_V8HI: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi, - exp, target, false); - case ALTIVEC_BUILTIN_LVXL_V16QI: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi, - exp, target, false); - case ALTIVEC_BUILTIN_LVX_V1TI: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti, - exp, target, false); - case ALTIVEC_BUILTIN_LVX_V2DF: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df, - exp, target, false); - case ALTIVEC_BUILTIN_LVX_V2DI: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di, - exp, target, false); - case ALTIVEC_BUILTIN_LVX_V4SF: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf, - exp, target, false); - case ALTIVEC_BUILTIN_LVX: - case ALTIVEC_BUILTIN_LVX_V4SI: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si, - exp, target, false); - case ALTIVEC_BUILTIN_LVX_V8HI: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi, - exp, target, false); - case ALTIVEC_BUILTIN_LVX_V16QI: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi, - exp, target, false); - case ALTIVEC_BUILTIN_LVLX: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx, - exp, target, true); - case ALTIVEC_BUILTIN_LVLXL: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl, - exp, target, true); - case ALTIVEC_BUILTIN_LVRX: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx, - exp, target, true); - case ALTIVEC_BUILTIN_LVRXL: - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl, - exp, target, true); - case VSX_BUILTIN_LXVD2X_V1TI: - return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti, - exp, target, false); - case VSX_BUILTIN_LXVD2X_V2DF: - return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df, - exp, target, false); - case VSX_BUILTIN_LXVD2X_V2DI: - return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di, - exp, target, false); - case VSX_BUILTIN_LXVW4X_V4SF: - return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf, - exp, target, false); - case VSX_BUILTIN_LXVW4X_V4SI: - return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si, - exp, target, false); - case VSX_BUILTIN_LXVW4X_V8HI: - return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi, - exp, target, false); - case VSX_BUILTIN_LXVW4X_V16QI: - return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi, - exp, target, false); - /* For the following on big endian, it's ok to use any appropriate - unaligned-supporting load, so use a generic expander. For - little-endian, the exact element-reversing instruction must - be used. */ - case VSX_BUILTIN_LD_ELEMREV_V2DF: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df - : CODE_FOR_vsx_ld_elemrev_v2df); - return altivec_expand_lv_builtin (code, exp, target, false); - } - case VSX_BUILTIN_LD_ELEMREV_V1TI: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti - : CODE_FOR_vsx_ld_elemrev_v1ti); - return altivec_expand_lv_builtin (code, exp, target, false); - } - case VSX_BUILTIN_LD_ELEMREV_V2DI: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di - : CODE_FOR_vsx_ld_elemrev_v2di); - return altivec_expand_lv_builtin (code, exp, target, false); - } - case VSX_BUILTIN_LD_ELEMREV_V4SF: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf - : CODE_FOR_vsx_ld_elemrev_v4sf); - return altivec_expand_lv_builtin (code, exp, target, false); - } - case VSX_BUILTIN_LD_ELEMREV_V4SI: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si - : CODE_FOR_vsx_ld_elemrev_v4si); - return altivec_expand_lv_builtin (code, exp, target, false); - } - case VSX_BUILTIN_LD_ELEMREV_V8HI: - { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi - : CODE_FOR_vsx_ld_elemrev_v8hi); - return altivec_expand_lv_builtin (code, exp, target, false); - } - case VSX_BUILTIN_LD_ELEMREV_V16QI: + case RS6000_BIF_VMINSD: + case RS6000_BIF_VMINUD: + case RS6000_BIF_VMINSB: + case RS6000_BIF_VMINSH: + case RS6000_BIF_VMINSW: + case RS6000_BIF_VMINUB: + case RS6000_BIF_VMINUH: + case RS6000_BIF_VMINUW: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* flavors of vec_max. */ + case RS6000_BIF_XVMAXDP: + case RS6000_BIF_XVMAXSP: + case RS6000_BIF_VMAXFP: { - enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi - : CODE_FOR_vsx_ld_elemrev_v16qi); - return altivec_expand_lv_builtin (code, exp, target, false); + lhs = gimple_call_lhs (stmt); + tree type = TREE_TYPE (lhs); + if (HONOR_NANS (type)) + return false; + gcc_fallthrough (); } - break; - default: - break; - /* Fall through. */ - } - - *expandedp = false; - return NULL_RTX; -} - -/* Check whether a builtin function is supported in this target - configuration. */ -bool -rs6000_builtin_is_supported_p (enum rs6000_builtins fncode) -{ - HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask; - if ((fnmask & rs6000_builtin_mask) != fnmask) - return false; - else - return true; -} - -/* Raise an error message for a builtin function that is called without the - appropriate target options being set. */ - -static void -rs6000_invalid_builtin (enum rs6000_builtins fncode) -{ - size_t uns_fncode = (size_t) fncode; - const char *name = rs6000_builtin_info[uns_fncode].name; - HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask; - - gcc_assert (name != NULL); - if ((fnmask & RS6000_BTM_CELL) != 0) - error ("%qs is only valid for the cell processor", name); - else if ((fnmask & RS6000_BTM_VSX) != 0) - error ("%qs requires the %qs option", name, "-mvsx"); - else if ((fnmask & RS6000_BTM_HTM) != 0) - error ("%qs requires the %qs option", name, "-mhtm"); - else if ((fnmask & RS6000_BTM_ALTIVEC) != 0) - error ("%qs requires the %qs option", name, "-maltivec"); - else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR)) - == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR)) - error ("%qs requires the %qs and %qs options", name, "-mhard-dfp", - "-mpower8-vector"); - else if ((fnmask & RS6000_BTM_DFP) != 0) - error ("%qs requires the %qs option", name, "-mhard-dfp"); - else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0) - error ("%qs requires the %qs option", name, "-mpower8-vector"); - else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT)) - == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT)) - error ("%qs requires the %qs and %qs options", name, "-mcpu=power9", - "-m64"); - else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0) - error ("%qs requires the %qs option", name, "-mcpu=power9"); - else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT)) - == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT)) - error ("%qs requires the %qs and %qs options", name, "-mcpu=power9", - "-m64"); - else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC) - error ("%qs requires the %qs option", name, "-mcpu=power9"); - else if ((fnmask & RS6000_BTM_P10) != 0) - error ("%qs requires the %qs option", name, "-mcpu=power10"); - else if ((fnmask & RS6000_BTM_MMA) != 0) - error ("%qs requires the %qs option", name, "-mmma"); - else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128) - { - if (!TARGET_HARD_FLOAT) - error ("%qs requires the %qs option", name, "-mhard-float"); - else - error ("%qs requires the %qs option", name, - TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128"); - } - else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0) - error ("%qs requires the %qs option", name, "-mhard-float"); - else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0) - error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name); - else if ((fnmask & RS6000_BTM_FLOAT128) != 0) - error ("%qs requires the %qs option", name, "%<-mfloat128%>"); - else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64)) - == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64)) - error ("%qs requires the %qs (or newer), and %qs or %qs options", - name, "-mcpu=power7", "-m64", "-mpowerpc64"); - else - error ("%qs is not supported with the current options", name); -} - -/* Raise an error message for a builtin function that is called without the - appropriate target options being set. */ - -void -rs6000_invalid_new_builtin (enum rs6000_gen_builtins fncode) -{ - size_t j = (size_t) fncode; - const char *name = rs6000_builtin_info_x[j].bifname; - - switch (rs6000_builtin_info_x[j].enable) - { - case ENB_P5: - error ("%qs requires the %qs option", name, "-mcpu=power5"); - break; - case ENB_P6: - error ("%qs requires the %qs option", name, "-mcpu=power6"); - break; - case ENB_P6_64: - error ("%qs requires the %qs option and either the %qs or %qs option", - name, "-mcpu=power6", "-m64", "-mpowerpc64"); - break; - case ENB_ALTIVEC: - error ("%qs requires the %qs option", name, "-maltivec"); - break; - case ENB_CELL: - error ("%qs requires the %qs option", name, "-mcpu=cell"); - break; - case ENB_VSX: - error ("%qs requires the %qs option", name, "-mvsx"); - break; - case ENB_P7: - error ("%qs requires the %qs option", name, "-mcpu=power7"); - break; - case ENB_P7_64: - error ("%qs requires the %qs option and either the %qs or %qs option", - name, "-mcpu=power7", "-m64", "-mpowerpc64"); - break; - case ENB_P8: - error ("%qs requires the %qs option", name, "-mcpu=power8"); - break; - case ENB_P8V: - error ("%qs requires the %qs and %qs options", name, "-mcpu=power8", - "-mvsx"); - break; - case ENB_P9: - error ("%qs requires the %qs option", name, "-mcpu=power9"); - break; - case ENB_P9_64: - error ("%qs requires the %qs option and either the %qs or %qs option", - name, "-mcpu=power9", "-m64", "-mpowerpc64"); - break; - case ENB_P9V: - error ("%qs requires the %qs and %qs options", name, "-mcpu=power9", - "-mvsx"); - break; - case ENB_IEEE128_HW: - error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name); - break; - case ENB_DFP: - error ("%qs requires the %qs option", name, "-mhard-dfp"); - break; - case ENB_CRYPTO: - error ("%qs requires the %qs option", name, "-mcrypto"); - break; - case ENB_HTM: - error ("%qs requires the %qs option", name, "-mhtm"); - break; - case ENB_P10: - error ("%qs requires the %qs option", name, "-mcpu=power10"); - break; - case ENB_P10_64: - error ("%qs requires the %qs option and either the %qs or %qs option", - name, "-mcpu=power10", "-m64", "-mpowerpc64"); - break; - case ENB_MMA: - error ("%qs requires the %qs option", name, "-mmma"); - break; - default: - case ENB_ALWAYS: - gcc_unreachable (); - } -} - -/* Target hook for early folding of built-ins, shamelessly stolen - from ia64.c. */ - -tree -rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED, - int n_args ATTRIBUTE_UNUSED, - tree *args ATTRIBUTE_UNUSED, - bool ignore ATTRIBUTE_UNUSED) -{ -#ifdef SUBTARGET_FOLD_BUILTIN - return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore); -#else - return NULL_TREE; -#endif -} - -/* Helper function to sort out which built-ins may be valid without having - a LHS. */ -static bool -rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code) -{ - /* Check for built-ins explicitly marked as a void function. */ - if (rs6000_builtin_info[fn_code].attr & RS6000_BTC_VOID) - return true; - - switch (fn_code) - { - case ALTIVEC_BUILTIN_STVX_V16QI: - case ALTIVEC_BUILTIN_STVX_V8HI: - case ALTIVEC_BUILTIN_STVX_V4SI: - case ALTIVEC_BUILTIN_STVX_V4SF: - case ALTIVEC_BUILTIN_STVX_V2DI: - case ALTIVEC_BUILTIN_STVX_V2DF: - case VSX_BUILTIN_STXVW4X_V16QI: - case VSX_BUILTIN_STXVW4X_V8HI: - case VSX_BUILTIN_STXVW4X_V4SF: - case VSX_BUILTIN_STXVW4X_V4SI: - case VSX_BUILTIN_STXVD2X_V2DF: - case VSX_BUILTIN_STXVD2X_V2DI: + case RS6000_BIF_VMAXSD: + case RS6000_BIF_VMAXUD: + case RS6000_BIF_VMAXSB: + case RS6000_BIF_VMAXSH: + case RS6000_BIF_VMAXSW: + case RS6000_BIF_VMAXUB: + case RS6000_BIF_VMAXUH: + case RS6000_BIF_VMAXUW: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); return true; - default: - return false; - } -} - -/* Helper function to handle the gimple folding of a vector compare - operation. This sets up true/false vectors, and uses the - VEC_COND_EXPR operation. - CODE indicates which comparison is to be made. (EQ, GT, ...). - TYPE indicates the type of the result. - Code is inserted before GSI. */ -static tree -fold_build_vec_cmp (tree_code code, tree type, tree arg0, tree arg1, - gimple_stmt_iterator *gsi) -{ - tree cmp_type = truth_type_for (type); - tree zero_vec = build_zero_cst (type); - tree minus_one_vec = build_minus_one_cst (type); - tree temp = create_tmp_reg_or_ssa_name (cmp_type); - gimple *g = gimple_build_assign (temp, code, arg0, arg1); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - return fold_build3 (VEC_COND_EXPR, type, temp, minus_one_vec, zero_vec); -} - -/* Helper function to handle the in-between steps for the - vector compare built-ins. */ -static void -fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt) -{ - tree arg0 = gimple_call_arg (stmt, 0); - tree arg1 = gimple_call_arg (stmt, 1); - tree lhs = gimple_call_lhs (stmt); - tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1, gsi); - gimple *g = gimple_build_assign (lhs, cmp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); -} - -/* Helper function to map V2DF and V4SF types to their - integral equivalents (V2DI and V4SI). */ -tree map_to_integral_tree_type (tree input_tree_type) -{ - if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type))) - return input_tree_type; - else - { - if (types_compatible_p (TREE_TYPE (input_tree_type), - TREE_TYPE (V2DF_type_node))) - return V2DI_type_node; - else if (types_compatible_p (TREE_TYPE (input_tree_type), - TREE_TYPE (V4SF_type_node))) - return V4SI_type_node; - else - gcc_unreachable (); - } -} - -/* Helper function to handle the vector merge[hl] built-ins. The - implementation difference between h and l versions for this code are in - the values used when building of the permute vector for high word versus - low word merge. The variance is keyed off the use_high parameter. */ -static void -fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high) -{ - tree arg0 = gimple_call_arg (stmt, 0); - tree arg1 = gimple_call_arg (stmt, 1); - tree lhs = gimple_call_lhs (stmt); - tree lhs_type = TREE_TYPE (lhs); - int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type); - int midpoint = n_elts / 2; - int offset = 0; - - if (use_high == 1) - offset = midpoint; - - /* The permute_type will match the lhs for integral types. For double and - float types, the permute type needs to map to the V2 or V4 type that - matches size. */ - tree permute_type; - permute_type = map_to_integral_tree_type (lhs_type); - tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1); - - for (int i = 0; i < midpoint; i++) - { - elts.safe_push (build_int_cst (TREE_TYPE (permute_type), - offset + i)); - elts.safe_push (build_int_cst (TREE_TYPE (permute_type), - offset + n_elts + i)); - } - - tree permute = elts.build (); - - gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); -} - -/* Helper function to handle the vector merge[eo] built-ins. */ -static void -fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd) -{ - tree arg0 = gimple_call_arg (stmt, 0); - tree arg1 = gimple_call_arg (stmt, 1); - tree lhs = gimple_call_lhs (stmt); - tree lhs_type = TREE_TYPE (lhs); - int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type); - - /* The permute_type will match the lhs for integral types. For double and - float types, the permute type needs to map to the V2 or V4 type that - matches size. */ - tree permute_type; - permute_type = map_to_integral_tree_type (lhs_type); - - tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1); - - /* Build the permute vector. */ - for (int i = 0; i < n_elts / 2; i++) - { - elts.safe_push (build_int_cst (TREE_TYPE (permute_type), - 2*i + use_odd)); - elts.safe_push (build_int_cst (TREE_TYPE (permute_type), - 2*i + use_odd + n_elts)); - } - - tree permute = elts.build (); - - gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); -} - -/* Expand the MMA built-ins early, so that we can convert the pass-by-reference - __vector_quad arguments into pass-by-value arguments, leading to more - efficient code generation. */ - -bool -rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi) -{ - gimple *stmt = gsi_stmt (*gsi); - tree fndecl = gimple_call_fndecl (stmt); - enum rs6000_builtins fncode - = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); - unsigned attr = rs6000_builtin_info[fncode].attr; - - if ((attr & RS6000_BTC_GIMPLE) == 0) - return false; - - unsigned nopnds = (attr & RS6000_BTC_OPND_MASK); - gimple_seq new_seq = NULL; - gimple *new_call; - tree new_decl; - - if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC - || fncode == VSX_BUILTIN_DISASSEMBLE_PAIR) - { - /* This is an MMA disassemble built-in function. */ - push_gimplify_context (true); - unsigned nvec = (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) ? 4 : 2; - tree dst_ptr = gimple_call_arg (stmt, 0); - tree src_ptr = gimple_call_arg (stmt, 1); - tree src_type = TREE_TYPE (src_ptr); - tree src = create_tmp_reg_or_ssa_name (TREE_TYPE (src_type)); - gimplify_assign (src, build_simple_mem_ref (src_ptr), &new_seq); - - /* If we are not disassembling an accumulator/pair or our destination is - another accumulator/pair, then just copy the entire thing as is. */ - if ((fncode == MMA_BUILTIN_DISASSEMBLE_ACC - && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_quad_type_node) - || (fncode == VSX_BUILTIN_DISASSEMBLE_PAIR - && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_pair_type_node)) - { - tree dst = build_simple_mem_ref (build1 (VIEW_CONVERT_EXPR, - src_type, dst_ptr)); - gimplify_assign (dst, src, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - - /* If we're disassembling an accumulator into a different type, we need - to emit a xxmfacc instruction now, since we cannot do it later. */ - if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) - { - new_decl = rs6000_builtin_decls[MMA_BUILTIN_XXMFACC_INTERNAL]; - new_call = gimple_build_call (new_decl, 1, src); - src = create_tmp_reg_or_ssa_name (vector_quad_type_node); - gimple_call_set_lhs (new_call, src); - gimple_seq_add_stmt (&new_seq, new_call); - } - - /* Copy the accumulator/pair vector by vector. */ - new_decl = rs6000_builtin_decls[fncode + 1]; - tree dst_type = build_pointer_type_for_mode (unsigned_V16QI_type_node, - ptr_mode, true); - tree dst_base = build1 (VIEW_CONVERT_EXPR, dst_type, dst_ptr); - for (unsigned i = 0; i < nvec; i++) - { - unsigned index = WORDS_BIG_ENDIAN ? i : nvec - 1 - i; - tree dst = build2 (MEM_REF, unsigned_V16QI_type_node, dst_base, - build_int_cst (dst_type, index * 16)); - tree dstssa = create_tmp_reg_or_ssa_name (unsigned_V16QI_type_node); - new_call = gimple_build_call (new_decl, 2, src, - build_int_cstu (uint16_type_node, i)); - gimple_call_set_lhs (new_call, dstssa); - gimple_seq_add_stmt (&new_seq, new_call); - gimplify_assign (dst, dstssa, &new_seq); - } - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - else if (fncode == VSX_BUILTIN_LXVP) - { - push_gimplify_context (true); - tree offset = gimple_call_arg (stmt, 0); - tree ptr = gimple_call_arg (stmt, 1); - tree lhs = gimple_call_lhs (stmt); - if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) - ptr = build1 (VIEW_CONVERT_EXPR, - build_pointer_type (vector_pair_type_node), ptr); - tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, - TREE_TYPE (ptr), ptr, offset)); - gimplify_assign (lhs, mem, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - else if (fncode == VSX_BUILTIN_STXVP) - { - push_gimplify_context (true); - tree src = gimple_call_arg (stmt, 0); - tree offset = gimple_call_arg (stmt, 1); - tree ptr = gimple_call_arg (stmt, 2); - if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) - ptr = build1 (VIEW_CONVERT_EXPR, - build_pointer_type (vector_pair_type_node), ptr); - tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, - TREE_TYPE (ptr), ptr, offset)); - gimplify_assign (mem, src, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); + /* Flavors of vec_eqv. */ + case RS6000_BIF_EQV_V16QI: + case RS6000_BIF_EQV_V8HI: + case RS6000_BIF_EQV_V4SI: + case RS6000_BIF_EQV_V4SF: + case RS6000_BIF_EQV_V2DF: + case RS6000_BIF_EQV_V2DI: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); + g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); return true; - } - - /* Convert this built-in into an internal version that uses pass-by-value - arguments. The internal built-in follows immediately after this one. */ - new_decl = rs6000_builtin_decls[fncode + 1]; - tree lhs, op[MAX_MMA_OPERANDS]; - tree acc = gimple_call_arg (stmt, 0); - push_gimplify_context (true); - - if ((attr & RS6000_BTC_QUAD) != 0) - { - /* This built-in has a pass-by-reference accumulator input, so load it - into a temporary accumulator for use as a pass-by-value input. */ - op[0] = create_tmp_reg_or_ssa_name (vector_quad_type_node); - for (unsigned i = 1; i < nopnds; i++) - op[i] = gimple_call_arg (stmt, i); - gimplify_assign (op[0], build_simple_mem_ref (acc), &new_seq); - } - else - { - /* This built-in does not use its pass-by-reference accumulator argument - as an input argument, so remove it from the input list. */ - nopnds--; - for (unsigned i = 0; i < nopnds; i++) - op[i] = gimple_call_arg (stmt, i + 1); - } - - switch (nopnds) - { - case 0: - new_call = gimple_build_call (new_decl, 0); - break; - case 1: - new_call = gimple_build_call (new_decl, 1, op[0]); - break; - case 2: - new_call = gimple_build_call (new_decl, 2, op[0], op[1]); - break; - case 3: - new_call = gimple_build_call (new_decl, 3, op[0], op[1], op[2]); - break; - case 4: - new_call = gimple_build_call (new_decl, 4, op[0], op[1], op[2], op[3]); - break; - case 5: - new_call = gimple_build_call (new_decl, 5, op[0], op[1], op[2], op[3], - op[4]); - break; - case 6: - new_call = gimple_build_call (new_decl, 6, op[0], op[1], op[2], op[3], - op[4], op[5]); - break; - case 7: - new_call = gimple_build_call (new_decl, 7, op[0], op[1], op[2], op[3], - op[4], op[5], op[6]); - break; - default: - gcc_unreachable (); - } - - if (fncode == VSX_BUILTIN_BUILD_PAIR || fncode == VSX_BUILTIN_ASSEMBLE_PAIR) - lhs = create_tmp_reg_or_ssa_name (vector_pair_type_node); - else - lhs = create_tmp_reg_or_ssa_name (vector_quad_type_node); - gimple_call_set_lhs (new_call, lhs); - gimple_seq_add_stmt (&new_seq, new_call); - gimplify_assign (build_simple_mem_ref (acc), lhs, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - - return true; -} - -/* Fold a machine-dependent built-in in GIMPLE. (For folding into - a constant, use rs6000_fold_builtin.) */ - -bool -rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) -{ - if (new_builtins_are_live) - return rs6000_gimple_fold_new_builtin (gsi); - - gimple *stmt = gsi_stmt (*gsi); - tree fndecl = gimple_call_fndecl (stmt); - gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD); - enum rs6000_builtins fn_code - = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); - tree arg0, arg1, lhs, temp; - enum tree_code bcode; - gimple *g; - - size_t uns_fncode = (size_t) fn_code; - enum insn_code icode = rs6000_builtin_info[uns_fncode].icode; - const char *fn_name1 = rs6000_builtin_info[uns_fncode].name; - const char *fn_name2 = (icode != CODE_FOR_nothing) - ? get_insn_name ((int) icode) - : "nothing"; - - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n", - fn_code, fn_name1, fn_name2); - - if (!rs6000_fold_gimple) - return false; - - /* Prevent gimple folding for code that does not have a LHS, unless it is - allowed per the rs6000_builtin_valid_without_lhs helper function. */ - if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code)) - return false; - - /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */ - if (!rs6000_builtin_is_supported_p (fn_code)) - return false; - - if (rs6000_gimple_fold_mma_builtin (gsi)) - return true; - - switch (fn_code) - { - /* Flavors of vec_add. We deliberately don't expand - P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to - TImode, resulting in much poorer code generation. */ - case ALTIVEC_BUILTIN_VADDUBM: - case ALTIVEC_BUILTIN_VADDUHM: - case ALTIVEC_BUILTIN_VADDUWM: - case P8V_BUILTIN_VADDUDM: - case ALTIVEC_BUILTIN_VADDFP: - case VSX_BUILTIN_XVADDDP: - bcode = PLUS_EXPR; - do_binary: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs))) - && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs)))) - { - /* Ensure the binary operation is performed in a type - that wraps if it is integral type. */ - gimple_seq stmts = NULL; - tree type = unsigned_type_for (TREE_TYPE (lhs)); - tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR, - type, arg0); - tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, - type, arg1); - tree res = gimple_build (&stmts, gimple_location (stmt), bcode, - type, uarg0, uarg1); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, - build1 (VIEW_CONVERT_EXPR, - TREE_TYPE (lhs), res)); - gsi_replace (gsi, g, true); - return true; - } - g = gimple_build_assign (lhs, bcode, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_sub. We deliberately don't expand - P8V_BUILTIN_VSUBUQM. */ - case ALTIVEC_BUILTIN_VSUBUBM: - case ALTIVEC_BUILTIN_VSUBUHM: - case ALTIVEC_BUILTIN_VSUBUWM: - case P8V_BUILTIN_VSUBUDM: - case ALTIVEC_BUILTIN_VSUBFP: - case VSX_BUILTIN_XVSUBDP: - bcode = MINUS_EXPR; - goto do_binary; - case VSX_BUILTIN_XVMULSP: - case VSX_BUILTIN_XVMULDP: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Even element flavors of vec_mul (signed). */ - case ALTIVEC_BUILTIN_VMULESB: - case ALTIVEC_BUILTIN_VMULESH: - case P8V_BUILTIN_VMULESW: - /* Even element flavors of vec_mul (unsigned). */ - case ALTIVEC_BUILTIN_VMULEUB: - case ALTIVEC_BUILTIN_VMULEUH: - case P8V_BUILTIN_VMULEUW: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Odd element flavors of vec_mul (signed). */ - case ALTIVEC_BUILTIN_VMULOSB: - case ALTIVEC_BUILTIN_VMULOSH: - case P8V_BUILTIN_VMULOSW: - /* Odd element flavors of vec_mul (unsigned). */ - case ALTIVEC_BUILTIN_VMULOUB: - case ALTIVEC_BUILTIN_VMULOUH: - case P8V_BUILTIN_VMULOUW: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_div (Integer). */ - case VSX_BUILTIN_DIV_V2DI: - case VSX_BUILTIN_UDIV_V2DI: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_div (Float). */ - case VSX_BUILTIN_XVDIVSP: - case VSX_BUILTIN_XVDIVDP: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_and. */ - case ALTIVEC_BUILTIN_VAND_V16QI_UNS: - case ALTIVEC_BUILTIN_VAND_V16QI: - case ALTIVEC_BUILTIN_VAND_V8HI_UNS: - case ALTIVEC_BUILTIN_VAND_V8HI: - case ALTIVEC_BUILTIN_VAND_V4SI_UNS: - case ALTIVEC_BUILTIN_VAND_V4SI: - case ALTIVEC_BUILTIN_VAND_V2DI_UNS: - case ALTIVEC_BUILTIN_VAND_V2DI: - case ALTIVEC_BUILTIN_VAND_V4SF: - case ALTIVEC_BUILTIN_VAND_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_andc. */ - case ALTIVEC_BUILTIN_VANDC_V16QI_UNS: - case ALTIVEC_BUILTIN_VANDC_V16QI: - case ALTIVEC_BUILTIN_VANDC_V8HI_UNS: - case ALTIVEC_BUILTIN_VANDC_V8HI: - case ALTIVEC_BUILTIN_VANDC_V4SI_UNS: - case ALTIVEC_BUILTIN_VANDC_V4SI: - case ALTIVEC_BUILTIN_VANDC_V2DI_UNS: - case ALTIVEC_BUILTIN_VANDC_V2DI: - case ALTIVEC_BUILTIN_VANDC_V4SF: - case ALTIVEC_BUILTIN_VANDC_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); - g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_nand. */ - case P8V_BUILTIN_VEC_NAND: - case P8V_BUILTIN_NAND_V16QI_UNS: - case P8V_BUILTIN_NAND_V16QI: - case P8V_BUILTIN_NAND_V8HI_UNS: - case P8V_BUILTIN_NAND_V8HI: - case P8V_BUILTIN_NAND_V4SI_UNS: - case P8V_BUILTIN_NAND_V4SI: - case P8V_BUILTIN_NAND_V2DI_UNS: - case P8V_BUILTIN_NAND_V2DI: - case P8V_BUILTIN_NAND_V4SF: - case P8V_BUILTIN_NAND_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); - g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_or. */ - case ALTIVEC_BUILTIN_VOR_V16QI_UNS: - case ALTIVEC_BUILTIN_VOR_V16QI: - case ALTIVEC_BUILTIN_VOR_V8HI_UNS: - case ALTIVEC_BUILTIN_VOR_V8HI: - case ALTIVEC_BUILTIN_VOR_V4SI_UNS: - case ALTIVEC_BUILTIN_VOR_V4SI: - case ALTIVEC_BUILTIN_VOR_V2DI_UNS: - case ALTIVEC_BUILTIN_VOR_V2DI: - case ALTIVEC_BUILTIN_VOR_V4SF: - case ALTIVEC_BUILTIN_VOR_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* flavors of vec_orc. */ - case P8V_BUILTIN_ORC_V16QI_UNS: - case P8V_BUILTIN_ORC_V16QI: - case P8V_BUILTIN_ORC_V8HI_UNS: - case P8V_BUILTIN_ORC_V8HI: - case P8V_BUILTIN_ORC_V4SI_UNS: - case P8V_BUILTIN_ORC_V4SI: - case P8V_BUILTIN_ORC_V2DI_UNS: - case P8V_BUILTIN_ORC_V2DI: - case P8V_BUILTIN_ORC_V4SF: - case P8V_BUILTIN_ORC_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); - g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_xor. */ - case ALTIVEC_BUILTIN_VXOR_V16QI_UNS: - case ALTIVEC_BUILTIN_VXOR_V16QI: - case ALTIVEC_BUILTIN_VXOR_V8HI_UNS: - case ALTIVEC_BUILTIN_VXOR_V8HI: - case ALTIVEC_BUILTIN_VXOR_V4SI_UNS: - case ALTIVEC_BUILTIN_VXOR_V4SI: - case ALTIVEC_BUILTIN_VXOR_V2DI_UNS: - case ALTIVEC_BUILTIN_VXOR_V2DI: - case ALTIVEC_BUILTIN_VXOR_V4SF: - case ALTIVEC_BUILTIN_VXOR_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_nor. */ - case ALTIVEC_BUILTIN_VNOR_V16QI_UNS: - case ALTIVEC_BUILTIN_VNOR_V16QI: - case ALTIVEC_BUILTIN_VNOR_V8HI_UNS: - case ALTIVEC_BUILTIN_VNOR_V8HI: - case ALTIVEC_BUILTIN_VNOR_V4SI_UNS: - case ALTIVEC_BUILTIN_VNOR_V4SI: - case ALTIVEC_BUILTIN_VNOR_V2DI_UNS: - case ALTIVEC_BUILTIN_VNOR_V2DI: - case ALTIVEC_BUILTIN_VNOR_V4SF: - case ALTIVEC_BUILTIN_VNOR_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); - g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* flavors of vec_abs. */ - case ALTIVEC_BUILTIN_ABS_V16QI: - case ALTIVEC_BUILTIN_ABS_V8HI: - case ALTIVEC_BUILTIN_ABS_V4SI: - case ALTIVEC_BUILTIN_ABS_V4SF: - case P8V_BUILTIN_ABS_V2DI: - case VSX_BUILTIN_XVABSDP: - arg0 = gimple_call_arg (stmt, 0); - if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0))) - && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0)))) - return false; - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, ABS_EXPR, arg0); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* flavors of vec_min. */ - case VSX_BUILTIN_XVMINDP: - case ALTIVEC_BUILTIN_VMINFP: - { - lhs = gimple_call_lhs (stmt); - tree type = TREE_TYPE (lhs); - if (HONOR_NANS (type)) - return false; - gcc_fallthrough (); - } - case P8V_BUILTIN_VMINSD: - case P8V_BUILTIN_VMINUD: - case ALTIVEC_BUILTIN_VMINSB: - case ALTIVEC_BUILTIN_VMINSH: - case ALTIVEC_BUILTIN_VMINSW: - case ALTIVEC_BUILTIN_VMINUB: - case ALTIVEC_BUILTIN_VMINUH: - case ALTIVEC_BUILTIN_VMINUW: + /* Flavors of vec_rotate_left. */ + case RS6000_BIF_VRLB: + case RS6000_BIF_VRLH: + case RS6000_BIF_VRLW: + case RS6000_BIF_VRLD: arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* flavors of vec_max. */ - case VSX_BUILTIN_XVMAXDP: - case ALTIVEC_BUILTIN_VMAXFP: - { - lhs = gimple_call_lhs (stmt); - tree type = TREE_TYPE (lhs); - if (HONOR_NANS (type)) - return false; - gcc_fallthrough (); - } - case P8V_BUILTIN_VMAXSD: - case P8V_BUILTIN_VMAXUD: - case ALTIVEC_BUILTIN_VMAXSB: - case ALTIVEC_BUILTIN_VMAXSH: - case ALTIVEC_BUILTIN_VMAXSW: - case ALTIVEC_BUILTIN_VMAXUB: - case ALTIVEC_BUILTIN_VMAXUH: - case ALTIVEC_BUILTIN_VMAXUW: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_eqv. */ - case P8V_BUILTIN_EQV_V16QI: - case P8V_BUILTIN_EQV_V8HI: - case P8V_BUILTIN_EQV_V4SI: - case P8V_BUILTIN_EQV_V4SF: - case P8V_BUILTIN_EQV_V2DF: - case P8V_BUILTIN_EQV_V2DI: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); - g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_rotate_left. */ - case ALTIVEC_BUILTIN_VRLB: - case ALTIVEC_BUILTIN_VRLH: - case ALTIVEC_BUILTIN_VRLW: - case P8V_BUILTIN_VRLD: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vector shift right algebraic. - vec_sra{b,h,w} -> vsra{b,h,w}. */ - case ALTIVEC_BUILTIN_VSRAB: - case ALTIVEC_BUILTIN_VSRAH: - case ALTIVEC_BUILTIN_VSRAW: - case P8V_BUILTIN_VSRAD: - { - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - tree arg1_type = TREE_TYPE (arg1); - tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); - tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); - location_t loc = gimple_location (stmt); - /* Force arg1 into the range valid matching the arg0 type. */ - /* Build a vector consisting of the max valid bit-size values. */ - int n_elts = VECTOR_CST_NELTS (arg1); - tree element_size = build_int_cst (unsigned_element_type, - 128 / n_elts); - tree_vector_builder elts (unsigned_arg1_type, n_elts, 1); - for (int i = 0; i < n_elts; i++) - elts.safe_push (element_size); - tree modulo_tree = elts.build (); - /* Modulo the provided shift value against that vector. */ - gimple_seq stmts = NULL; - tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, - unsigned_arg1_type, arg1); - tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, - unsigned_arg1_type, unsigned_arg1, - modulo_tree); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - /* And finally, do the shift. */ - g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - /* Flavors of vector shift left. - builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */ - case ALTIVEC_BUILTIN_VSLB: - case ALTIVEC_BUILTIN_VSLH: - case ALTIVEC_BUILTIN_VSLW: - case P8V_BUILTIN_VSLD: - { - location_t loc; - gimple_seq stmts = NULL; - arg0 = gimple_call_arg (stmt, 0); - tree arg0_type = TREE_TYPE (arg0); - if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type)) - && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type))) - return false; - arg1 = gimple_call_arg (stmt, 1); - tree arg1_type = TREE_TYPE (arg1); - tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); - tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); - loc = gimple_location (stmt); - lhs = gimple_call_lhs (stmt); - /* Force arg1 into the range valid matching the arg0 type. */ - /* Build a vector consisting of the max valid bit-size values. */ - int n_elts = VECTOR_CST_NELTS (arg1); - int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type)) - * BITS_PER_UNIT; - tree element_size = build_int_cst (unsigned_element_type, - tree_size_in_bits / n_elts); - tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1); - for (int i = 0; i < n_elts; i++) - elts.safe_push (element_size); - tree modulo_tree = elts.build (); - /* Modulo the provided shift value against that vector. */ - tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, - unsigned_arg1_type, arg1); - tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, - unsigned_arg1_type, unsigned_arg1, - modulo_tree); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - /* And finally, do the shift. */ - g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - /* Flavors of vector shift right. */ - case ALTIVEC_BUILTIN_VSRB: - case ALTIVEC_BUILTIN_VSRH: - case ALTIVEC_BUILTIN_VSRW: - case P8V_BUILTIN_VSRD: - { - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - tree arg1_type = TREE_TYPE (arg1); - tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); - tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); - location_t loc = gimple_location (stmt); - gimple_seq stmts = NULL; - /* Convert arg0 to unsigned. */ - tree arg0_unsigned - = gimple_build (&stmts, VIEW_CONVERT_EXPR, - unsigned_type_for (TREE_TYPE (arg0)), arg0); - /* Force arg1 into the range valid matching the arg0 type. */ - /* Build a vector consisting of the max valid bit-size values. */ - int n_elts = VECTOR_CST_NELTS (arg1); - tree element_size = build_int_cst (unsigned_element_type, - 128 / n_elts); - tree_vector_builder elts (unsigned_arg1_type, n_elts, 1); - for (int i = 0; i < n_elts; i++) - elts.safe_push (element_size); - tree modulo_tree = elts.build (); - /* Modulo the provided shift value against that vector. */ - tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, - unsigned_arg1_type, arg1); - tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, - unsigned_arg1_type, unsigned_arg1, - modulo_tree); - /* Do the shift. */ - tree res - = gimple_build (&stmts, RSHIFT_EXPR, - TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1); - /* Convert result back to the lhs type. */ - res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - replace_call_with_value (gsi, res); - return true; - } - /* Vector loads. */ - case ALTIVEC_BUILTIN_LVX_V16QI: - case ALTIVEC_BUILTIN_LVX_V8HI: - case ALTIVEC_BUILTIN_LVX_V4SI: - case ALTIVEC_BUILTIN_LVX_V4SF: - case ALTIVEC_BUILTIN_LVX_V2DI: - case ALTIVEC_BUILTIN_LVX_V2DF: - case ALTIVEC_BUILTIN_LVX_V1TI: - { - arg0 = gimple_call_arg (stmt, 0); // offset - arg1 = gimple_call_arg (stmt, 1); // address - lhs = gimple_call_lhs (stmt); - location_t loc = gimple_location (stmt); - /* Since arg1 may be cast to a different type, just use ptr_type_node - here instead of trying to enforce TBAA on pointer types. */ - tree arg1_type = ptr_type_node; - tree lhs_type = TREE_TYPE (lhs); - /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create - the tree using the value from arg0. The resulting type will match - the type of arg1. */ - gimple_seq stmts = NULL; - tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0); - tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, - arg1_type, arg1, temp_offset); - /* Mask off any lower bits from the address. */ - tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR, - arg1_type, temp_addr, - build_int_cst (arg1_type, -16)); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - if (!is_gimple_mem_ref_addr (aligned_addr)) - { - tree t = make_ssa_name (TREE_TYPE (aligned_addr)); - gimple *g = gimple_build_assign (t, aligned_addr); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - aligned_addr = t; - } - /* Use the build2 helper to set up the mem_ref. The MEM_REF could also - take an offset, but since we've already incorporated the offset - above, here we just pass in a zero. */ - gimple *g - = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr, - build_int_cst (arg1_type, 0))); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - /* Vector stores. */ - case ALTIVEC_BUILTIN_STVX_V16QI: - case ALTIVEC_BUILTIN_STVX_V8HI: - case ALTIVEC_BUILTIN_STVX_V4SI: - case ALTIVEC_BUILTIN_STVX_V4SF: - case ALTIVEC_BUILTIN_STVX_V2DI: - case ALTIVEC_BUILTIN_STVX_V2DF: - { - arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */ - arg1 = gimple_call_arg (stmt, 1); /* Offset. */ - tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */ - location_t loc = gimple_location (stmt); - tree arg0_type = TREE_TYPE (arg0); - /* Use ptr_type_node (no TBAA) for the arg2_type. - FIXME: (Richard) "A proper fix would be to transition this type as - seen from the frontend to GIMPLE, for example in a similar way we - do for MEM_REFs by piggy-backing that on an extra argument, a - constant zero pointer of the alias pointer type to use (which would - also serve as a type indicator of the store itself). I'd use a - target specific internal function for this (not sure if we can have - those target specific, but I guess if it's folded away then that's - fine) and get away with the overload set." */ - tree arg2_type = ptr_type_node; - /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create - the tree using the value from arg0. The resulting type will match - the type of arg2. */ - gimple_seq stmts = NULL; - tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1); - tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, - arg2_type, arg2, temp_offset); - /* Mask off any lower bits from the address. */ - tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR, - arg2_type, temp_addr, - build_int_cst (arg2_type, -16)); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - if (!is_gimple_mem_ref_addr (aligned_addr)) - { - tree t = make_ssa_name (TREE_TYPE (aligned_addr)); - gimple *g = gimple_build_assign (t, aligned_addr); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - aligned_addr = t; - } - /* The desired gimple result should be similar to: - MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */ - gimple *g - = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr, - build_int_cst (arg2_type, 0)), arg0); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - - /* unaligned Vector loads. */ - case VSX_BUILTIN_LXVW4X_V16QI: - case VSX_BUILTIN_LXVW4X_V8HI: - case VSX_BUILTIN_LXVW4X_V4SF: - case VSX_BUILTIN_LXVW4X_V4SI: - case VSX_BUILTIN_LXVD2X_V2DF: - case VSX_BUILTIN_LXVD2X_V2DI: - { - arg0 = gimple_call_arg (stmt, 0); // offset - arg1 = gimple_call_arg (stmt, 1); // address - lhs = gimple_call_lhs (stmt); - location_t loc = gimple_location (stmt); - /* Since arg1 may be cast to a different type, just use ptr_type_node - here instead of trying to enforce TBAA on pointer types. */ - tree arg1_type = ptr_type_node; - tree lhs_type = TREE_TYPE (lhs); - /* In GIMPLE the type of the MEM_REF specifies the alignment. The - required alignment (power) is 4 bytes regardless of data type. */ - tree align_ltype = build_aligned_type (lhs_type, 4); - /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create - the tree using the value from arg0. The resulting type will match - the type of arg1. */ - gimple_seq stmts = NULL; - tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0); - tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, - arg1_type, arg1, temp_offset); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - if (!is_gimple_mem_ref_addr (temp_addr)) - { - tree t = make_ssa_name (TREE_TYPE (temp_addr)); - gimple *g = gimple_build_assign (t, temp_addr); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - temp_addr = t; - } - /* Use the build2 helper to set up the mem_ref. The MEM_REF could also - take an offset, but since we've already incorporated the offset - above, here we just pass in a zero. */ - gimple *g; - g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr, - build_int_cst (arg1_type, 0))); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - - /* unaligned Vector stores. */ - case VSX_BUILTIN_STXVW4X_V16QI: - case VSX_BUILTIN_STXVW4X_V8HI: - case VSX_BUILTIN_STXVW4X_V4SF: - case VSX_BUILTIN_STXVW4X_V4SI: - case VSX_BUILTIN_STXVD2X_V2DF: - case VSX_BUILTIN_STXVD2X_V2DI: - { - arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */ - arg1 = gimple_call_arg (stmt, 1); /* Offset. */ - tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */ - location_t loc = gimple_location (stmt); - tree arg0_type = TREE_TYPE (arg0); - /* Use ptr_type_node (no TBAA) for the arg2_type. */ - tree arg2_type = ptr_type_node; - /* In GIMPLE the type of the MEM_REF specifies the alignment. The - required alignment (power) is 4 bytes regardless of data type. */ - tree align_stype = build_aligned_type (arg0_type, 4); - /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create - the tree using the value from arg1. */ - gimple_seq stmts = NULL; - tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1); - tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, - arg2_type, arg2, temp_offset); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - if (!is_gimple_mem_ref_addr (temp_addr)) - { - tree t = make_ssa_name (TREE_TYPE (temp_addr)); - gimple *g = gimple_build_assign (t, temp_addr); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - temp_addr = t; - } - gimple *g; - g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr, - build_int_cst (arg2_type, 0)), arg0); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - - /* Vector Fused multiply-add (fma). */ - case ALTIVEC_BUILTIN_VMADDFP: - case VSX_BUILTIN_XVMADDDP: - case ALTIVEC_BUILTIN_VMLADDUHM: - { - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - tree arg2 = gimple_call_arg (stmt, 2); - lhs = gimple_call_lhs (stmt); - gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2); - gimple_call_set_lhs (g, lhs); - gimple_call_set_nothrow (g, true); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - - /* Vector compares; EQ, NE, GE, GT, LE. */ - case ALTIVEC_BUILTIN_VCMPEQUB: - case ALTIVEC_BUILTIN_VCMPEQUH: - case ALTIVEC_BUILTIN_VCMPEQUW: - case P8V_BUILTIN_VCMPEQUD: - case P10V_BUILTIN_VCMPEQUT: - fold_compare_helper (gsi, EQ_EXPR, stmt); - return true; - - case P9V_BUILTIN_CMPNEB: - case P9V_BUILTIN_CMPNEH: - case P9V_BUILTIN_CMPNEW: - case P10V_BUILTIN_CMPNET: - fold_compare_helper (gsi, NE_EXPR, stmt); - return true; - - case VSX_BUILTIN_CMPGE_16QI: - case VSX_BUILTIN_CMPGE_U16QI: - case VSX_BUILTIN_CMPGE_8HI: - case VSX_BUILTIN_CMPGE_U8HI: - case VSX_BUILTIN_CMPGE_4SI: - case VSX_BUILTIN_CMPGE_U4SI: - case VSX_BUILTIN_CMPGE_2DI: - case VSX_BUILTIN_CMPGE_U2DI: - case P10V_BUILTIN_CMPGE_1TI: - case P10V_BUILTIN_CMPGE_U1TI: - fold_compare_helper (gsi, GE_EXPR, stmt); - return true; - - case ALTIVEC_BUILTIN_VCMPGTSB: - case ALTIVEC_BUILTIN_VCMPGTUB: - case ALTIVEC_BUILTIN_VCMPGTSH: - case ALTIVEC_BUILTIN_VCMPGTUH: - case ALTIVEC_BUILTIN_VCMPGTSW: - case ALTIVEC_BUILTIN_VCMPGTUW: - case P8V_BUILTIN_VCMPGTUD: - case P8V_BUILTIN_VCMPGTSD: - case P10V_BUILTIN_VCMPGTUT: - case P10V_BUILTIN_VCMPGTST: - fold_compare_helper (gsi, GT_EXPR, stmt); - return true; - - case VSX_BUILTIN_CMPLE_16QI: - case VSX_BUILTIN_CMPLE_U16QI: - case VSX_BUILTIN_CMPLE_8HI: - case VSX_BUILTIN_CMPLE_U8HI: - case VSX_BUILTIN_CMPLE_4SI: - case VSX_BUILTIN_CMPLE_U4SI: - case VSX_BUILTIN_CMPLE_2DI: - case VSX_BUILTIN_CMPLE_U2DI: - case P10V_BUILTIN_CMPLE_1TI: - case P10V_BUILTIN_CMPLE_U1TI: - fold_compare_helper (gsi, LE_EXPR, stmt); - return true; - - /* flavors of vec_splat_[us]{8,16,32}. */ - case ALTIVEC_BUILTIN_VSPLTISB: - case ALTIVEC_BUILTIN_VSPLTISH: - case ALTIVEC_BUILTIN_VSPLTISW: - { - arg0 = gimple_call_arg (stmt, 0); - lhs = gimple_call_lhs (stmt); - - /* Only fold the vec_splat_*() if the lower bits of arg 0 is a - 5-bit signed constant in range -16 to +15. */ - if (TREE_CODE (arg0) != INTEGER_CST - || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15)) - return false; - gimple_seq stmts = NULL; - location_t loc = gimple_location (stmt); - tree splat_value = gimple_convert (&stmts, loc, - TREE_TYPE (TREE_TYPE (lhs)), arg0); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value); - g = gimple_build_assign (lhs, splat_tree); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - - /* Flavors of vec_splat. */ - /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */ - case ALTIVEC_BUILTIN_VSPLTB: - case ALTIVEC_BUILTIN_VSPLTH: - case ALTIVEC_BUILTIN_VSPLTW: - case VSX_BUILTIN_XXSPLTD_V2DI: - case VSX_BUILTIN_XXSPLTD_V2DF: - { - arg0 = gimple_call_arg (stmt, 0); /* input vector. */ - arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */ - /* Only fold the vec_splat_*() if arg1 is both a constant value and - is a valid index into the arg0 vector. */ - unsigned int n_elts = VECTOR_CST_NELTS (arg0); - if (TREE_CODE (arg1) != INTEGER_CST - || TREE_INT_CST_LOW (arg1) > (n_elts -1)) - return false; - lhs = gimple_call_lhs (stmt); - tree lhs_type = TREE_TYPE (lhs); - tree arg0_type = TREE_TYPE (arg0); - tree splat; - if (TREE_CODE (arg0) == VECTOR_CST) - splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1)); - else - { - /* Determine (in bits) the length and start location of the - splat value for a call to the tree_vec_extract helper. */ - int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type)) - * BITS_PER_UNIT / n_elts; - int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size; - tree len = build_int_cst (bitsizetype, splat_elem_size); - tree start = build_int_cst (bitsizetype, splat_start_bit); - splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0, - len, start); - } - /* And finally, build the new vector. */ - tree splat_tree = build_vector_from_val (lhs_type, splat); - g = gimple_build_assign (lhs, splat_tree); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - - /* vec_mergel (integrals). */ - case ALTIVEC_BUILTIN_VMRGLH: - case ALTIVEC_BUILTIN_VMRGLW: - case VSX_BUILTIN_XXMRGLW_4SI: - case ALTIVEC_BUILTIN_VMRGLB: - case VSX_BUILTIN_VEC_MERGEL_V2DI: - case VSX_BUILTIN_XXMRGLW_4SF: - case VSX_BUILTIN_VEC_MERGEL_V2DF: - fold_mergehl_helper (gsi, stmt, 1); - return true; - /* vec_mergeh (integrals). */ - case ALTIVEC_BUILTIN_VMRGHH: - case ALTIVEC_BUILTIN_VMRGHW: - case VSX_BUILTIN_XXMRGHW_4SI: - case ALTIVEC_BUILTIN_VMRGHB: - case VSX_BUILTIN_VEC_MERGEH_V2DI: - case VSX_BUILTIN_XXMRGHW_4SF: - case VSX_BUILTIN_VEC_MERGEH_V2DF: - fold_mergehl_helper (gsi, stmt, 0); - return true; - - /* Flavors of vec_mergee. */ - case P8V_BUILTIN_VMRGEW_V4SI: - case P8V_BUILTIN_VMRGEW_V2DI: - case P8V_BUILTIN_VMRGEW_V4SF: - case P8V_BUILTIN_VMRGEW_V2DF: - fold_mergeeo_helper (gsi, stmt, 0); - return true; - /* Flavors of vec_mergeo. */ - case P8V_BUILTIN_VMRGOW_V4SI: - case P8V_BUILTIN_VMRGOW_V2DI: - case P8V_BUILTIN_VMRGOW_V4SF: - case P8V_BUILTIN_VMRGOW_V2DF: - fold_mergeeo_helper (gsi, stmt, 1); - return true; - - /* d = vec_pack (a, b) */ - case P8V_BUILTIN_VPKUDUM: - case ALTIVEC_BUILTIN_VPKUHUM: - case ALTIVEC_BUILTIN_VPKUWUM: - { - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - - /* d = vec_unpackh (a) */ - /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call - in this code is sensitive to endian-ness, and needs to be inverted to - handle both LE and BE targets. */ - case ALTIVEC_BUILTIN_VUPKHSB: - case ALTIVEC_BUILTIN_VUPKHSH: - case P8V_BUILTIN_VUPKHSW: - { - arg0 = gimple_call_arg (stmt, 0); - lhs = gimple_call_lhs (stmt); - if (BYTES_BIG_ENDIAN) - g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0); - else - g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - /* d = vec_unpackl (a) */ - case ALTIVEC_BUILTIN_VUPKLSB: - case ALTIVEC_BUILTIN_VUPKLSH: - case P8V_BUILTIN_VUPKLSW: - { - arg0 = gimple_call_arg (stmt, 0); - lhs = gimple_call_lhs (stmt); - if (BYTES_BIG_ENDIAN) - g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0); - else - g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - /* There is no gimple type corresponding with pixel, so just return. */ - case ALTIVEC_BUILTIN_VUPKHPX: - case ALTIVEC_BUILTIN_VUPKLPX: - return false; - - /* vec_perm. */ - case ALTIVEC_BUILTIN_VPERM_16QI: - case ALTIVEC_BUILTIN_VPERM_8HI: - case ALTIVEC_BUILTIN_VPERM_4SI: - case ALTIVEC_BUILTIN_VPERM_2DI: - case ALTIVEC_BUILTIN_VPERM_4SF: - case ALTIVEC_BUILTIN_VPERM_2DF: - { - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - tree permute = gimple_call_arg (stmt, 2); - lhs = gimple_call_lhs (stmt); - location_t loc = gimple_location (stmt); - gimple_seq stmts = NULL; - // convert arg0 and arg1 to match the type of the permute - // for the VEC_PERM_EXPR operation. - tree permute_type = (TREE_TYPE (permute)); - tree arg0_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, - permute_type, arg0); - tree arg1_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, - permute_type, arg1); - tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR, - permute_type, arg0_ptype, arg1_ptype, - permute); - // Convert the result back to the desired lhs type upon completion. - tree temp = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, - TREE_TYPE (lhs), lhs_ptype); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - g = gimple_build_assign (lhs, temp); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - - default: - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n", - fn_code, fn_name1, fn_name2); - break; - } - - return false; -} - -/* Helper function to sort out which built-ins may be valid without having - a LHS. */ -static bool -rs6000_new_builtin_valid_without_lhs (enum rs6000_gen_builtins fn_code, - tree fndecl) -{ - if (TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node) - return true; - - switch (fn_code) - { - case RS6000_BIF_STVX_V16QI: - case RS6000_BIF_STVX_V8HI: - case RS6000_BIF_STVX_V4SI: - case RS6000_BIF_STVX_V4SF: - case RS6000_BIF_STVX_V2DI: - case RS6000_BIF_STVX_V2DF: - case RS6000_BIF_STXVW4X_V16QI: - case RS6000_BIF_STXVW4X_V8HI: - case RS6000_BIF_STXVW4X_V4SF: - case RS6000_BIF_STXVW4X_V4SI: - case RS6000_BIF_STXVD2X_V2DF: - case RS6000_BIF_STXVD2X_V2DI: - return true; - default: - return false; - } -} - -/* Check whether a builtin function is supported in this target - configuration. */ -bool -rs6000_new_builtin_is_supported (enum rs6000_gen_builtins fncode) -{ - switch (rs6000_builtin_info_x[(size_t) fncode].enable) - { - case ENB_ALWAYS: - return true; - case ENB_P5: - return TARGET_POPCNTB; - case ENB_P6: - return TARGET_CMPB; - case ENB_P6_64: - return TARGET_CMPB && TARGET_POWERPC64; - case ENB_P7: - return TARGET_POPCNTD; - case ENB_P7_64: - return TARGET_POPCNTD && TARGET_POWERPC64; - case ENB_P8: - return TARGET_DIRECT_MOVE; - case ENB_P8V: - return TARGET_P8_VECTOR; - case ENB_P9: - return TARGET_MODULO; - case ENB_P9_64: - return TARGET_MODULO && TARGET_POWERPC64; - case ENB_P9V: - return TARGET_P9_VECTOR; - case ENB_P10: - return TARGET_POWER10; - case ENB_P10_64: - return TARGET_POWER10 && TARGET_POWERPC64; - case ENB_ALTIVEC: - return TARGET_ALTIVEC; - case ENB_VSX: - return TARGET_VSX; - case ENB_CELL: - return TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL; - case ENB_IEEE128_HW: - return TARGET_FLOAT128_HW; - case ENB_DFP: - return TARGET_DFP; - case ENB_CRYPTO: - return TARGET_CRYPTO; - case ENB_HTM: - return TARGET_HTM; - case ENB_MMA: - return TARGET_MMA; - default: - gcc_unreachable (); - } - gcc_unreachable (); -} - -/* Expand the MMA built-ins early, so that we can convert the pass-by-reference - __vector_quad arguments into pass-by-value arguments, leading to more - efficient code generation. */ -static bool -rs6000_gimple_fold_new_mma_builtin (gimple_stmt_iterator *gsi, - rs6000_gen_builtins fn_code) -{ - gimple *stmt = gsi_stmt (*gsi); - size_t fncode = (size_t) fn_code; - - if (!bif_is_mma (rs6000_builtin_info_x[fncode])) - return false; - - /* Each call that can be gimple-expanded has an associated built-in - function that it will expand into. If this one doesn't, we have - already expanded it! Exceptions: lxvp and stxvp. */ - if (rs6000_builtin_info_x[fncode].assoc_bif == RS6000_BIF_NONE - && fncode != RS6000_BIF_LXVP - && fncode != RS6000_BIF_STXVP) - return false; - - bifdata *bd = &rs6000_builtin_info_x[fncode]; - unsigned nopnds = bd->nargs; - gimple_seq new_seq = NULL; - gimple *new_call; - tree new_decl; - - /* Compatibility built-ins; we used to call these - __builtin_mma_{dis,}assemble_pair, but now we call them - __builtin_vsx_{dis,}assemble_pair. Handle the old versions. */ - if (fncode == RS6000_BIF_ASSEMBLE_PAIR) - fncode = RS6000_BIF_ASSEMBLE_PAIR_V; - else if (fncode == RS6000_BIF_DISASSEMBLE_PAIR) - fncode = RS6000_BIF_DISASSEMBLE_PAIR_V; - - if (fncode == RS6000_BIF_DISASSEMBLE_ACC - || fncode == RS6000_BIF_DISASSEMBLE_PAIR_V) - { - /* This is an MMA disassemble built-in function. */ - push_gimplify_context (true); - unsigned nvec = (fncode == RS6000_BIF_DISASSEMBLE_ACC) ? 4 : 2; - tree dst_ptr = gimple_call_arg (stmt, 0); - tree src_ptr = gimple_call_arg (stmt, 1); - tree src_type = TREE_TYPE (src_ptr); - tree src = create_tmp_reg_or_ssa_name (TREE_TYPE (src_type)); - gimplify_assign (src, build_simple_mem_ref (src_ptr), &new_seq); - - /* If we are not disassembling an accumulator/pair or our destination is - another accumulator/pair, then just copy the entire thing as is. */ - if ((fncode == RS6000_BIF_DISASSEMBLE_ACC - && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_quad_type_node) - || (fncode == RS6000_BIF_DISASSEMBLE_PAIR_V - && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_pair_type_node)) - { - tree dst = build_simple_mem_ref (build1 (VIEW_CONVERT_EXPR, - src_type, dst_ptr)); - gimplify_assign (dst, src, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - - /* If we're disassembling an accumulator into a different type, we need - to emit a xxmfacc instruction now, since we cannot do it later. */ - if (fncode == RS6000_BIF_DISASSEMBLE_ACC) - { - new_decl = rs6000_builtin_decls_x[RS6000_BIF_XXMFACC_INTERNAL]; - new_call = gimple_build_call (new_decl, 1, src); - src = create_tmp_reg_or_ssa_name (vector_quad_type_node); - gimple_call_set_lhs (new_call, src); - gimple_seq_add_stmt (&new_seq, new_call); - } - - /* Copy the accumulator/pair vector by vector. */ - new_decl - = rs6000_builtin_decls_x[rs6000_builtin_info_x[fncode].assoc_bif]; - tree dst_type = build_pointer_type_for_mode (unsigned_V16QI_type_node, - ptr_mode, true); - tree dst_base = build1 (VIEW_CONVERT_EXPR, dst_type, dst_ptr); - for (unsigned i = 0; i < nvec; i++) - { - unsigned index = WORDS_BIG_ENDIAN ? i : nvec - 1 - i; - tree dst = build2 (MEM_REF, unsigned_V16QI_type_node, dst_base, - build_int_cst (dst_type, index * 16)); - tree dstssa = create_tmp_reg_or_ssa_name (unsigned_V16QI_type_node); - new_call = gimple_build_call (new_decl, 2, src, - build_int_cstu (uint16_type_node, i)); - gimple_call_set_lhs (new_call, dstssa); - gimple_seq_add_stmt (&new_seq, new_call); - gimplify_assign (dst, dstssa, &new_seq); - } - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - - /* TODO: Do some factoring on these two chunks. */ - if (fncode == RS6000_BIF_LXVP) - { - push_gimplify_context (true); - tree offset = gimple_call_arg (stmt, 0); - tree ptr = gimple_call_arg (stmt, 1); - tree lhs = gimple_call_lhs (stmt); - if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) - ptr = build1 (VIEW_CONVERT_EXPR, - build_pointer_type (vector_pair_type_node), ptr); - tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, - TREE_TYPE (ptr), ptr, offset)); - gimplify_assign (lhs, mem, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - - if (fncode == RS6000_BIF_STXVP) - { - push_gimplify_context (true); - tree src = gimple_call_arg (stmt, 0); - tree offset = gimple_call_arg (stmt, 1); - tree ptr = gimple_call_arg (stmt, 2); - if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) - ptr = build1 (VIEW_CONVERT_EXPR, - build_pointer_type (vector_pair_type_node), ptr); - tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, - TREE_TYPE (ptr), ptr, offset)); - gimplify_assign (mem, src, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - - /* Convert this built-in into an internal version that uses pass-by-value - arguments. The internal built-in is found in the assoc_bif field. */ - new_decl = rs6000_builtin_decls_x[rs6000_builtin_info_x[fncode].assoc_bif]; - tree lhs, op[MAX_MMA_OPERANDS]; - tree acc = gimple_call_arg (stmt, 0); - push_gimplify_context (true); - - if (bif_is_quad (*bd)) - { - /* This built-in has a pass-by-reference accumulator input, so load it - into a temporary accumulator for use as a pass-by-value input. */ - op[0] = create_tmp_reg_or_ssa_name (vector_quad_type_node); - for (unsigned i = 1; i < nopnds; i++) - op[i] = gimple_call_arg (stmt, i); - gimplify_assign (op[0], build_simple_mem_ref (acc), &new_seq); - } - else - { - /* This built-in does not use its pass-by-reference accumulator argument - as an input argument, so remove it from the input list. */ - nopnds--; - for (unsigned i = 0; i < nopnds; i++) - op[i] = gimple_call_arg (stmt, i + 1); - } - - switch (nopnds) - { - case 0: - new_call = gimple_build_call (new_decl, 0); - break; - case 1: - new_call = gimple_build_call (new_decl, 1, op[0]); - break; - case 2: - new_call = gimple_build_call (new_decl, 2, op[0], op[1]); - break; - case 3: - new_call = gimple_build_call (new_decl, 3, op[0], op[1], op[2]); - break; - case 4: - new_call = gimple_build_call (new_decl, 4, op[0], op[1], op[2], op[3]); - break; - case 5: - new_call = gimple_build_call (new_decl, 5, op[0], op[1], op[2], op[3], - op[4]); - break; - case 6: - new_call = gimple_build_call (new_decl, 6, op[0], op[1], op[2], op[3], - op[4], op[5]); - break; - case 7: - new_call = gimple_build_call (new_decl, 7, op[0], op[1], op[2], op[3], - op[4], op[5], op[6]); - break; - default: - gcc_unreachable (); - } - - if (fncode == RS6000_BIF_BUILD_PAIR || fncode == RS6000_BIF_ASSEMBLE_PAIR_V) - lhs = create_tmp_reg_or_ssa_name (vector_pair_type_node); - else - lhs = create_tmp_reg_or_ssa_name (vector_quad_type_node); - gimple_call_set_lhs (new_call, lhs); - gimple_seq_add_stmt (&new_seq, new_call); - gimplify_assign (build_simple_mem_ref (acc), lhs, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - - return true; -} - -/* Fold a machine-dependent built-in in GIMPLE. (For folding into - a constant, use rs6000_fold_builtin.) */ -static bool -rs6000_gimple_fold_new_builtin (gimple_stmt_iterator *gsi) -{ - gimple *stmt = gsi_stmt (*gsi); - tree fndecl = gimple_call_fndecl (stmt); - gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD); - enum rs6000_gen_builtins fn_code - = (enum rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl); - tree arg0, arg1, lhs, temp; - enum tree_code bcode; - gimple *g; - - size_t uns_fncode = (size_t) fn_code; - enum insn_code icode = rs6000_builtin_info_x[uns_fncode].icode; - const char *fn_name1 = rs6000_builtin_info_x[uns_fncode].bifname; - const char *fn_name2 = (icode != CODE_FOR_nothing) - ? get_insn_name ((int) icode) - : "nothing"; - - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_gimple_fold_new_builtin %d %s %s\n", - fn_code, fn_name1, fn_name2); - - if (!rs6000_fold_gimple) - return false; - - /* Prevent gimple folding for code that does not have a LHS, unless it is - allowed per the rs6000_new_builtin_valid_without_lhs helper function. */ - if (!gimple_call_lhs (stmt) - && !rs6000_new_builtin_valid_without_lhs (fn_code, fndecl)) - return false; - - /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */ - if (!rs6000_new_builtin_is_supported (fn_code)) - return false; - - if (rs6000_gimple_fold_new_mma_builtin (gsi, fn_code)) - return true; - - switch (fn_code) - { - /* Flavors of vec_add. We deliberately don't expand - RS6000_BIF_VADDUQM as it gets lowered from V1TImode to - TImode, resulting in much poorer code generation. */ - case RS6000_BIF_VADDUBM: - case RS6000_BIF_VADDUHM: - case RS6000_BIF_VADDUWM: - case RS6000_BIF_VADDUDM: - case RS6000_BIF_VADDFP: - case RS6000_BIF_XVADDDP: - case RS6000_BIF_XVADDSP: - bcode = PLUS_EXPR; - do_binary: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs))) - && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs)))) - { - /* Ensure the binary operation is performed in a type - that wraps if it is integral type. */ - gimple_seq stmts = NULL; - tree type = unsigned_type_for (TREE_TYPE (lhs)); - tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR, - type, arg0); - tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, - type, arg1); - tree res = gimple_build (&stmts, gimple_location (stmt), bcode, - type, uarg0, uarg1); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR, - build1 (VIEW_CONVERT_EXPR, - TREE_TYPE (lhs), res)); - gsi_replace (gsi, g, true); - return true; - } - g = gimple_build_assign (lhs, bcode, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_sub. We deliberately don't expand - RS6000_BIF_VSUBUQM. */ - case RS6000_BIF_VSUBUBM: - case RS6000_BIF_VSUBUHM: - case RS6000_BIF_VSUBUWM: - case RS6000_BIF_VSUBUDM: - case RS6000_BIF_VSUBFP: - case RS6000_BIF_XVSUBDP: - case RS6000_BIF_XVSUBSP: - bcode = MINUS_EXPR; - goto do_binary; - case RS6000_BIF_XVMULSP: - case RS6000_BIF_XVMULDP: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Even element flavors of vec_mul (signed). */ - case RS6000_BIF_VMULESB: - case RS6000_BIF_VMULESH: - case RS6000_BIF_VMULESW: - /* Even element flavors of vec_mul (unsigned). */ - case RS6000_BIF_VMULEUB: - case RS6000_BIF_VMULEUH: - case RS6000_BIF_VMULEUW: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Odd element flavors of vec_mul (signed). */ - case RS6000_BIF_VMULOSB: - case RS6000_BIF_VMULOSH: - case RS6000_BIF_VMULOSW: - /* Odd element flavors of vec_mul (unsigned). */ - case RS6000_BIF_VMULOUB: - case RS6000_BIF_VMULOUH: - case RS6000_BIF_VMULOUW: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_div (Integer). */ - case RS6000_BIF_DIV_V2DI: - case RS6000_BIF_UDIV_V2DI: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_div (Float). */ - case RS6000_BIF_XVDIVSP: - case RS6000_BIF_XVDIVDP: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_and. */ - case RS6000_BIF_VAND_V16QI_UNS: - case RS6000_BIF_VAND_V16QI: - case RS6000_BIF_VAND_V8HI_UNS: - case RS6000_BIF_VAND_V8HI: - case RS6000_BIF_VAND_V4SI_UNS: - case RS6000_BIF_VAND_V4SI: - case RS6000_BIF_VAND_V2DI_UNS: - case RS6000_BIF_VAND_V2DI: - case RS6000_BIF_VAND_V4SF: - case RS6000_BIF_VAND_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_andc. */ - case RS6000_BIF_VANDC_V16QI_UNS: - case RS6000_BIF_VANDC_V16QI: - case RS6000_BIF_VANDC_V8HI_UNS: - case RS6000_BIF_VANDC_V8HI: - case RS6000_BIF_VANDC_V4SI_UNS: - case RS6000_BIF_VANDC_V4SI: - case RS6000_BIF_VANDC_V2DI_UNS: - case RS6000_BIF_VANDC_V2DI: - case RS6000_BIF_VANDC_V4SF: - case RS6000_BIF_VANDC_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); - g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_nand. */ - case RS6000_BIF_NAND_V16QI_UNS: - case RS6000_BIF_NAND_V16QI: - case RS6000_BIF_NAND_V8HI_UNS: - case RS6000_BIF_NAND_V8HI: - case RS6000_BIF_NAND_V4SI_UNS: - case RS6000_BIF_NAND_V4SI: - case RS6000_BIF_NAND_V2DI_UNS: - case RS6000_BIF_NAND_V2DI: - case RS6000_BIF_NAND_V4SF: - case RS6000_BIF_NAND_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); - g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_or. */ - case RS6000_BIF_VOR_V16QI_UNS: - case RS6000_BIF_VOR_V16QI: - case RS6000_BIF_VOR_V8HI_UNS: - case RS6000_BIF_VOR_V8HI: - case RS6000_BIF_VOR_V4SI_UNS: - case RS6000_BIF_VOR_V4SI: - case RS6000_BIF_VOR_V2DI_UNS: - case RS6000_BIF_VOR_V2DI: - case RS6000_BIF_VOR_V4SF: - case RS6000_BIF_VOR_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* flavors of vec_orc. */ - case RS6000_BIF_ORC_V16QI_UNS: - case RS6000_BIF_ORC_V16QI: - case RS6000_BIF_ORC_V8HI_UNS: - case RS6000_BIF_ORC_V8HI: - case RS6000_BIF_ORC_V4SI_UNS: - case RS6000_BIF_ORC_V4SI: - case RS6000_BIF_ORC_V2DI_UNS: - case RS6000_BIF_ORC_V2DI: - case RS6000_BIF_ORC_V4SF: - case RS6000_BIF_ORC_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); - g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_xor. */ - case RS6000_BIF_VXOR_V16QI_UNS: - case RS6000_BIF_VXOR_V16QI: - case RS6000_BIF_VXOR_V8HI_UNS: - case RS6000_BIF_VXOR_V8HI: - case RS6000_BIF_VXOR_V4SI_UNS: - case RS6000_BIF_VXOR_V4SI: - case RS6000_BIF_VXOR_V2DI_UNS: - case RS6000_BIF_VXOR_V2DI: - case RS6000_BIF_VXOR_V4SF: - case RS6000_BIF_VXOR_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_nor. */ - case RS6000_BIF_VNOR_V16QI_UNS: - case RS6000_BIF_VNOR_V16QI: - case RS6000_BIF_VNOR_V8HI_UNS: - case RS6000_BIF_VNOR_V8HI: - case RS6000_BIF_VNOR_V4SI_UNS: - case RS6000_BIF_VNOR_V4SI: - case RS6000_BIF_VNOR_V2DI_UNS: - case RS6000_BIF_VNOR_V2DI: - case RS6000_BIF_VNOR_V4SF: - case RS6000_BIF_VNOR_V2DF: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); - g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* flavors of vec_abs. */ - case RS6000_BIF_ABS_V16QI: - case RS6000_BIF_ABS_V8HI: - case RS6000_BIF_ABS_V4SI: - case RS6000_BIF_ABS_V4SF: - case RS6000_BIF_ABS_V2DI: - case RS6000_BIF_XVABSDP: - case RS6000_BIF_XVABSSP: - arg0 = gimple_call_arg (stmt, 0); - if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0))) - && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0)))) - return false; - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, ABS_EXPR, arg0); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* flavors of vec_min. */ - case RS6000_BIF_XVMINDP: - case RS6000_BIF_XVMINSP: - case RS6000_BIF_VMINFP: - { - lhs = gimple_call_lhs (stmt); - tree type = TREE_TYPE (lhs); - if (HONOR_NANS (type)) - return false; - gcc_fallthrough (); - } - case RS6000_BIF_VMINSD: - case RS6000_BIF_VMINUD: - case RS6000_BIF_VMINSB: - case RS6000_BIF_VMINSH: - case RS6000_BIF_VMINSW: - case RS6000_BIF_VMINUB: - case RS6000_BIF_VMINUH: - case RS6000_BIF_VMINUW: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* flavors of vec_max. */ - case RS6000_BIF_XVMAXDP: - case RS6000_BIF_XVMAXSP: - case RS6000_BIF_VMAXFP: - { - lhs = gimple_call_lhs (stmt); - tree type = TREE_TYPE (lhs); - if (HONOR_NANS (type)) - return false; - gcc_fallthrough (); - } - case RS6000_BIF_VMAXSD: - case RS6000_BIF_VMAXUD: - case RS6000_BIF_VMAXSB: - case RS6000_BIF_VMAXSH: - case RS6000_BIF_VMAXSW: - case RS6000_BIF_VMAXUB: - case RS6000_BIF_VMAXUH: - case RS6000_BIF_VMAXUW: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_eqv. */ - case RS6000_BIF_EQV_V16QI: - case RS6000_BIF_EQV_V8HI: - case RS6000_BIF_EQV_V4SI: - case RS6000_BIF_EQV_V4SF: - case RS6000_BIF_EQV_V2DF: - case RS6000_BIF_EQV_V2DI: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); - g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vec_rotate_left. */ - case RS6000_BIF_VRLB: - case RS6000_BIF_VRLH: - case RS6000_BIF_VRLW: - case RS6000_BIF_VRLD: - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - /* Flavors of vector shift right algebraic. - vec_sra{b,h,w} -> vsra{b,h,w}. */ - case RS6000_BIF_VSRAB: - case RS6000_BIF_VSRAH: - case RS6000_BIF_VSRAW: - case RS6000_BIF_VSRAD: - { - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - tree arg1_type = TREE_TYPE (arg1); - tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); - tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); - location_t loc = gimple_location (stmt); - /* Force arg1 into the range valid matching the arg0 type. */ - /* Build a vector consisting of the max valid bit-size values. */ - int n_elts = VECTOR_CST_NELTS (arg1); - tree element_size = build_int_cst (unsigned_element_type, - 128 / n_elts); - tree_vector_builder elts (unsigned_arg1_type, n_elts, 1); - for (int i = 0; i < n_elts; i++) - elts.safe_push (element_size); - tree modulo_tree = elts.build (); - /* Modulo the provided shift value against that vector. */ - gimple_seq stmts = NULL; - tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, - unsigned_arg1_type, arg1); - tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, - unsigned_arg1_type, unsigned_arg1, - modulo_tree); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - /* And finally, do the shift. */ - g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - /* Flavors of vector shift left. - builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */ - case RS6000_BIF_VSLB: - case RS6000_BIF_VSLH: - case RS6000_BIF_VSLW: - case RS6000_BIF_VSLD: - { - location_t loc; - gimple_seq stmts = NULL; - arg0 = gimple_call_arg (stmt, 0); - tree arg0_type = TREE_TYPE (arg0); - if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type)) - && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type))) - return false; - arg1 = gimple_call_arg (stmt, 1); - tree arg1_type = TREE_TYPE (arg1); - tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); - tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); - loc = gimple_location (stmt); - lhs = gimple_call_lhs (stmt); - /* Force arg1 into the range valid matching the arg0 type. */ - /* Build a vector consisting of the max valid bit-size values. */ - int n_elts = VECTOR_CST_NELTS (arg1); - int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type)) - * BITS_PER_UNIT; - tree element_size = build_int_cst (unsigned_element_type, - tree_size_in_bits / n_elts); - tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1); - for (int i = 0; i < n_elts; i++) - elts.safe_push (element_size); - tree modulo_tree = elts.build (); - /* Modulo the provided shift value against that vector. */ - tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, - unsigned_arg1_type, arg1); - tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, - unsigned_arg1_type, unsigned_arg1, - modulo_tree); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - /* And finally, do the shift. */ - g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - /* Flavors of vector shift right. */ - case RS6000_BIF_VSRB: - case RS6000_BIF_VSRH: - case RS6000_BIF_VSRW: - case RS6000_BIF_VSRD: - { - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - tree arg1_type = TREE_TYPE (arg1); - tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); - tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); - location_t loc = gimple_location (stmt); - gimple_seq stmts = NULL; - /* Convert arg0 to unsigned. */ - tree arg0_unsigned - = gimple_build (&stmts, VIEW_CONVERT_EXPR, - unsigned_type_for (TREE_TYPE (arg0)), arg0); - /* Force arg1 into the range valid matching the arg0 type. */ - /* Build a vector consisting of the max valid bit-size values. */ - int n_elts = VECTOR_CST_NELTS (arg1); - tree element_size = build_int_cst (unsigned_element_type, - 128 / n_elts); - tree_vector_builder elts (unsigned_arg1_type, n_elts, 1); - for (int i = 0; i < n_elts; i++) - elts.safe_push (element_size); - tree modulo_tree = elts.build (); - /* Modulo the provided shift value against that vector. */ - tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, - unsigned_arg1_type, arg1); - tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, - unsigned_arg1_type, unsigned_arg1, - modulo_tree); - /* Do the shift. */ - tree res - = gimple_build (&stmts, RSHIFT_EXPR, - TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1); - /* Convert result back to the lhs type. */ - res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - replace_call_with_value (gsi, res); - return true; - } - /* Vector loads. */ - case RS6000_BIF_LVX_V16QI: - case RS6000_BIF_LVX_V8HI: - case RS6000_BIF_LVX_V4SI: - case RS6000_BIF_LVX_V4SF: - case RS6000_BIF_LVX_V2DI: - case RS6000_BIF_LVX_V2DF: - case RS6000_BIF_LVX_V1TI: - { - arg0 = gimple_call_arg (stmt, 0); // offset - arg1 = gimple_call_arg (stmt, 1); // address - lhs = gimple_call_lhs (stmt); - location_t loc = gimple_location (stmt); - /* Since arg1 may be cast to a different type, just use ptr_type_node - here instead of trying to enforce TBAA on pointer types. */ - tree arg1_type = ptr_type_node; - tree lhs_type = TREE_TYPE (lhs); - /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create - the tree using the value from arg0. The resulting type will match - the type of arg1. */ - gimple_seq stmts = NULL; - tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0); - tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, - arg1_type, arg1, temp_offset); - /* Mask off any lower bits from the address. */ - tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR, - arg1_type, temp_addr, - build_int_cst (arg1_type, -16)); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - if (!is_gimple_mem_ref_addr (aligned_addr)) - { - tree t = make_ssa_name (TREE_TYPE (aligned_addr)); - gimple *g = gimple_build_assign (t, aligned_addr); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - aligned_addr = t; - } - /* Use the build2 helper to set up the mem_ref. The MEM_REF could also - take an offset, but since we've already incorporated the offset - above, here we just pass in a zero. */ - gimple *g - = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr, - build_int_cst (arg1_type, 0))); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - /* Vector stores. */ - case RS6000_BIF_STVX_V16QI: - case RS6000_BIF_STVX_V8HI: - case RS6000_BIF_STVX_V4SI: - case RS6000_BIF_STVX_V4SF: - case RS6000_BIF_STVX_V2DI: - case RS6000_BIF_STVX_V2DF: - { - arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */ - arg1 = gimple_call_arg (stmt, 1); /* Offset. */ - tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */ - location_t loc = gimple_location (stmt); - tree arg0_type = TREE_TYPE (arg0); - /* Use ptr_type_node (no TBAA) for the arg2_type. - FIXME: (Richard) "A proper fix would be to transition this type as - seen from the frontend to GIMPLE, for example in a similar way we - do for MEM_REFs by piggy-backing that on an extra argument, a - constant zero pointer of the alias pointer type to use (which would - also serve as a type indicator of the store itself). I'd use a - target specific internal function for this (not sure if we can have - those target specific, but I guess if it's folded away then that's - fine) and get away with the overload set." */ - tree arg2_type = ptr_type_node; - /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create - the tree using the value from arg0. The resulting type will match - the type of arg2. */ - gimple_seq stmts = NULL; - tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1); - tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, - arg2_type, arg2, temp_offset); - /* Mask off any lower bits from the address. */ - tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR, - arg2_type, temp_addr, - build_int_cst (arg2_type, -16)); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - if (!is_gimple_mem_ref_addr (aligned_addr)) - { - tree t = make_ssa_name (TREE_TYPE (aligned_addr)); - gimple *g = gimple_build_assign (t, aligned_addr); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - aligned_addr = t; - } - /* The desired gimple result should be similar to: - MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */ - gimple *g - = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr, - build_int_cst (arg2_type, 0)), arg0); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - - /* unaligned Vector loads. */ - case RS6000_BIF_LXVW4X_V16QI: - case RS6000_BIF_LXVW4X_V8HI: - case RS6000_BIF_LXVW4X_V4SF: - case RS6000_BIF_LXVW4X_V4SI: - case RS6000_BIF_LXVD2X_V2DF: - case RS6000_BIF_LXVD2X_V2DI: - { - arg0 = gimple_call_arg (stmt, 0); // offset - arg1 = gimple_call_arg (stmt, 1); // address - lhs = gimple_call_lhs (stmt); - location_t loc = gimple_location (stmt); - /* Since arg1 may be cast to a different type, just use ptr_type_node - here instead of trying to enforce TBAA on pointer types. */ - tree arg1_type = ptr_type_node; - tree lhs_type = TREE_TYPE (lhs); - /* In GIMPLE the type of the MEM_REF specifies the alignment. The - required alignment (power) is 4 bytes regardless of data type. */ - tree align_ltype = build_aligned_type (lhs_type, 4); - /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create - the tree using the value from arg0. The resulting type will match - the type of arg1. */ - gimple_seq stmts = NULL; - tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0); - tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, - arg1_type, arg1, temp_offset); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - if (!is_gimple_mem_ref_addr (temp_addr)) - { - tree t = make_ssa_name (TREE_TYPE (temp_addr)); - gimple *g = gimple_build_assign (t, temp_addr); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - temp_addr = t; - } - /* Use the build2 helper to set up the mem_ref. The MEM_REF could also - take an offset, but since we've already incorporated the offset - above, here we just pass in a zero. */ - gimple *g; - g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr, - build_int_cst (arg1_type, 0))); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - - /* unaligned Vector stores. */ - case RS6000_BIF_STXVW4X_V16QI: - case RS6000_BIF_STXVW4X_V8HI: - case RS6000_BIF_STXVW4X_V4SF: - case RS6000_BIF_STXVW4X_V4SI: - case RS6000_BIF_STXVD2X_V2DF: - case RS6000_BIF_STXVD2X_V2DI: - { - arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */ - arg1 = gimple_call_arg (stmt, 1); /* Offset. */ - tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */ - location_t loc = gimple_location (stmt); - tree arg0_type = TREE_TYPE (arg0); - /* Use ptr_type_node (no TBAA) for the arg2_type. */ - tree arg2_type = ptr_type_node; - /* In GIMPLE the type of the MEM_REF specifies the alignment. The - required alignment (power) is 4 bytes regardless of data type. */ - tree align_stype = build_aligned_type (arg0_type, 4); - /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create - the tree using the value from arg1. */ - gimple_seq stmts = NULL; - tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1); - tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, - arg2_type, arg2, temp_offset); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - if (!is_gimple_mem_ref_addr (temp_addr)) - { - tree t = make_ssa_name (TREE_TYPE (temp_addr)); - gimple *g = gimple_build_assign (t, temp_addr); - gsi_insert_before (gsi, g, GSI_SAME_STMT); - temp_addr = t; - } - gimple *g; - g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr, - build_int_cst (arg2_type, 0)), arg0); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - - /* Vector Fused multiply-add (fma). */ - case RS6000_BIF_VMADDFP: - case RS6000_BIF_XVMADDDP: - case RS6000_BIF_XVMADDSP: - case RS6000_BIF_VMLADDUHM: - { - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - tree arg2 = gimple_call_arg (stmt, 2); - lhs = gimple_call_lhs (stmt); - gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2); - gimple_call_set_lhs (g, lhs); - gimple_call_set_nothrow (g, true); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - - /* Vector compares; EQ, NE, GE, GT, LE. */ - case RS6000_BIF_VCMPEQUB: - case RS6000_BIF_VCMPEQUH: - case RS6000_BIF_VCMPEQUW: - case RS6000_BIF_VCMPEQUD: - /* We deliberately omit RS6000_BIF_VCMPEQUT for now, because gimple - folding produces worse code for 128-bit compares. */ - fold_compare_helper (gsi, EQ_EXPR, stmt); - return true; - - case RS6000_BIF_VCMPNEB: - case RS6000_BIF_VCMPNEH: - case RS6000_BIF_VCMPNEW: - /* We deliberately omit RS6000_BIF_VCMPNET for now, because gimple - folding produces worse code for 128-bit compares. */ - fold_compare_helper (gsi, NE_EXPR, stmt); - return true; - - case RS6000_BIF_CMPGE_16QI: - case RS6000_BIF_CMPGE_U16QI: - case RS6000_BIF_CMPGE_8HI: - case RS6000_BIF_CMPGE_U8HI: - case RS6000_BIF_CMPGE_4SI: - case RS6000_BIF_CMPGE_U4SI: - case RS6000_BIF_CMPGE_2DI: - case RS6000_BIF_CMPGE_U2DI: - /* We deliberately omit RS6000_BIF_CMPGE_1TI and RS6000_BIF_CMPGE_U1TI - for now, because gimple folding produces worse code for 128-bit - compares. */ - fold_compare_helper (gsi, GE_EXPR, stmt); - return true; - - case RS6000_BIF_VCMPGTSB: - case RS6000_BIF_VCMPGTUB: - case RS6000_BIF_VCMPGTSH: - case RS6000_BIF_VCMPGTUH: - case RS6000_BIF_VCMPGTSW: - case RS6000_BIF_VCMPGTUW: - case RS6000_BIF_VCMPGTUD: - case RS6000_BIF_VCMPGTSD: - /* We deliberately omit RS6000_BIF_VCMPGTUT and RS6000_BIF_VCMPGTST - for now, because gimple folding produces worse code for 128-bit - compares. */ - fold_compare_helper (gsi, GT_EXPR, stmt); - return true; - - case RS6000_BIF_CMPLE_16QI: - case RS6000_BIF_CMPLE_U16QI: - case RS6000_BIF_CMPLE_8HI: - case RS6000_BIF_CMPLE_U8HI: - case RS6000_BIF_CMPLE_4SI: - case RS6000_BIF_CMPLE_U4SI: - case RS6000_BIF_CMPLE_2DI: - case RS6000_BIF_CMPLE_U2DI: - /* We deliberately omit RS6000_BIF_CMPLE_1TI and RS6000_BIF_CMPLE_U1TI - for now, because gimple folding produces worse code for 128-bit - compares. */ - fold_compare_helper (gsi, LE_EXPR, stmt); - return true; - - /* flavors of vec_splat_[us]{8,16,32}. */ - case RS6000_BIF_VSPLTISB: - case RS6000_BIF_VSPLTISH: - case RS6000_BIF_VSPLTISW: - { - arg0 = gimple_call_arg (stmt, 0); - lhs = gimple_call_lhs (stmt); - - /* Only fold the vec_splat_*() if the lower bits of arg 0 is a - 5-bit signed constant in range -16 to +15. */ - if (TREE_CODE (arg0) != INTEGER_CST - || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15)) - return false; - gimple_seq stmts = NULL; - location_t loc = gimple_location (stmt); - tree splat_value = gimple_convert (&stmts, loc, - TREE_TYPE (TREE_TYPE (lhs)), arg0); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value); - g = gimple_build_assign (lhs, splat_tree); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - - /* Flavors of vec_splat. */ - /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */ - case RS6000_BIF_VSPLTB: - case RS6000_BIF_VSPLTH: - case RS6000_BIF_VSPLTW: - case RS6000_BIF_XXSPLTD_V2DI: - case RS6000_BIF_XXSPLTD_V2DF: - { - arg0 = gimple_call_arg (stmt, 0); /* input vector. */ - arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */ - /* Only fold the vec_splat_*() if arg1 is both a constant value and - is a valid index into the arg0 vector. */ - unsigned int n_elts = VECTOR_CST_NELTS (arg0); - if (TREE_CODE (arg1) != INTEGER_CST - || TREE_INT_CST_LOW (arg1) > (n_elts -1)) - return false; - lhs = gimple_call_lhs (stmt); - tree lhs_type = TREE_TYPE (lhs); - tree arg0_type = TREE_TYPE (arg0); - tree splat; - if (TREE_CODE (arg0) == VECTOR_CST) - splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1)); - else - { - /* Determine (in bits) the length and start location of the - splat value for a call to the tree_vec_extract helper. */ - int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type)) - * BITS_PER_UNIT / n_elts; - int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size; - tree len = build_int_cst (bitsizetype, splat_elem_size); - tree start = build_int_cst (bitsizetype, splat_start_bit); - splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0, - len, start); - } - /* And finally, build the new vector. */ - tree splat_tree = build_vector_from_val (lhs_type, splat); - g = gimple_build_assign (lhs, splat_tree); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - - /* vec_mergel (integrals). */ - case RS6000_BIF_VMRGLH: - case RS6000_BIF_VMRGLW: - case RS6000_BIF_XXMRGLW_4SI: - case RS6000_BIF_VMRGLB: - case RS6000_BIF_VEC_MERGEL_V2DI: - case RS6000_BIF_XXMRGLW_4SF: - case RS6000_BIF_VEC_MERGEL_V2DF: - fold_mergehl_helper (gsi, stmt, 1); - return true; - /* vec_mergeh (integrals). */ - case RS6000_BIF_VMRGHH: - case RS6000_BIF_VMRGHW: - case RS6000_BIF_XXMRGHW_4SI: - case RS6000_BIF_VMRGHB: - case RS6000_BIF_VEC_MERGEH_V2DI: - case RS6000_BIF_XXMRGHW_4SF: - case RS6000_BIF_VEC_MERGEH_V2DF: - fold_mergehl_helper (gsi, stmt, 0); - return true; - - /* Flavors of vec_mergee. */ - case RS6000_BIF_VMRGEW_V4SI: - case RS6000_BIF_VMRGEW_V2DI: - case RS6000_BIF_VMRGEW_V4SF: - case RS6000_BIF_VMRGEW_V2DF: - fold_mergeeo_helper (gsi, stmt, 0); - return true; - /* Flavors of vec_mergeo. */ - case RS6000_BIF_VMRGOW_V4SI: - case RS6000_BIF_VMRGOW_V2DI: - case RS6000_BIF_VMRGOW_V4SF: - case RS6000_BIF_VMRGOW_V2DF: - fold_mergeeo_helper (gsi, stmt, 1); - return true; - - /* d = vec_pack (a, b) */ - case RS6000_BIF_VPKUDUM: - case RS6000_BIF_VPKUHUM: - case RS6000_BIF_VPKUWUM: - { - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - lhs = gimple_call_lhs (stmt); - gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - - /* d = vec_unpackh (a) */ - /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call - in this code is sensitive to endian-ness, and needs to be inverted to - handle both LE and BE targets. */ - case RS6000_BIF_VUPKHSB: - case RS6000_BIF_VUPKHSH: - case RS6000_BIF_VUPKHSW: - { - arg0 = gimple_call_arg (stmt, 0); - lhs = gimple_call_lhs (stmt); - if (BYTES_BIG_ENDIAN) - g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0); - else - g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - /* d = vec_unpackl (a) */ - case RS6000_BIF_VUPKLSB: - case RS6000_BIF_VUPKLSH: - case RS6000_BIF_VUPKLSW: - { - arg0 = gimple_call_arg (stmt, 0); - lhs = gimple_call_lhs (stmt); - if (BYTES_BIG_ENDIAN) - g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0); - else - g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0); - gimple_set_location (g, gimple_location (stmt)); - gsi_replace (gsi, g, true); - return true; - } - /* There is no gimple type corresponding with pixel, so just return. */ - case RS6000_BIF_VUPKHPX: - case RS6000_BIF_VUPKLPX: - return false; - - /* vec_perm. */ - case RS6000_BIF_VPERM_16QI: - case RS6000_BIF_VPERM_8HI: - case RS6000_BIF_VPERM_4SI: - case RS6000_BIF_VPERM_2DI: - case RS6000_BIF_VPERM_4SF: - case RS6000_BIF_VPERM_2DF: - case RS6000_BIF_VPERM_16QI_UNS: - case RS6000_BIF_VPERM_8HI_UNS: - case RS6000_BIF_VPERM_4SI_UNS: - case RS6000_BIF_VPERM_2DI_UNS: - { - arg0 = gimple_call_arg (stmt, 0); - arg1 = gimple_call_arg (stmt, 1); - tree permute = gimple_call_arg (stmt, 2); - lhs = gimple_call_lhs (stmt); - location_t loc = gimple_location (stmt); - gimple_seq stmts = NULL; - // convert arg0 and arg1 to match the type of the permute - // for the VEC_PERM_EXPR operation. - tree permute_type = (TREE_TYPE (permute)); - tree arg0_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, - permute_type, arg0); - tree arg1_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, - permute_type, arg1); - tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR, - permute_type, arg0_ptype, arg1_ptype, - permute); - // Convert the result back to the desired lhs type upon completion. - tree temp = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, - TREE_TYPE (lhs), lhs_ptype); - gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); - g = gimple_build_assign (lhs, temp); - gimple_set_location (g, loc); - gsi_replace (gsi, g, true); - return true; - } - - default: - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n", - fn_code, fn_name1, fn_name2); - break; - } - - return false; -} - -/* Expand an expression EXP that calls a built-in function, - with result going to TARGET if that's convenient - (and in mode MODE if that's convenient). - SUBTARGET may be used as the target for computing one of EXP's operands. - IGNORE is nonzero if the value is to be ignored. */ - -rtx -rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, - machine_mode mode ATTRIBUTE_UNUSED, - int ignore ATTRIBUTE_UNUSED) -{ - if (new_builtins_are_live) - return rs6000_expand_new_builtin (exp, target, subtarget, mode, ignore); - - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - enum rs6000_builtins fcode - = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); - size_t uns_fcode = (size_t)fcode; - const struct builtin_description *d; - size_t i; - rtx ret; - bool success; - HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask; - bool func_valid_p = ((rs6000_builtin_mask & mask) == mask); - enum insn_code icode = rs6000_builtin_info[uns_fcode].icode; - - /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit - floating point type, depending on whether long double is the IBM extended - double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if - we only define one variant of the built-in function, and switch the code - when defining it, rather than defining two built-ins and using the - overload table in rs6000-c.c to switch between the two. If we don't have - the proper assembler, don't do this switch because CODE_FOR_*kf* and - CODE_FOR_*tf* will be CODE_FOR_nothing. */ - if (FLOAT128_IEEE_P (TFmode)) - switch (icode) - { - default: - break; - - case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break; - case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break; - case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break; - case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break; - case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break; - case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break; - case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break; - case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break; - case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break; - case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break; - case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break; - case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break; - case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break; - - case CODE_FOR_xscmpexpqp_eq_kf: - icode = CODE_FOR_xscmpexpqp_eq_tf; - break; - - case CODE_FOR_xscmpexpqp_lt_kf: - icode = CODE_FOR_xscmpexpqp_lt_tf; - break; - - case CODE_FOR_xscmpexpqp_gt_kf: - icode = CODE_FOR_xscmpexpqp_gt_tf; - break; - - case CODE_FOR_xscmpexpqp_unordered_kf: - icode = CODE_FOR_xscmpexpqp_unordered_tf; - break; - } - - if (TARGET_DEBUG_BUILTIN) - { - const char *name1 = rs6000_builtin_info[uns_fcode].name; - const char *name2 = (icode != CODE_FOR_nothing) - ? get_insn_name ((int) icode) - : "nothing"; - const char *name3; - - switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK) - { - default: name3 = "unknown"; break; - case RS6000_BTC_SPECIAL: name3 = "special"; break; - case RS6000_BTC_UNARY: name3 = "unary"; break; - case RS6000_BTC_BINARY: name3 = "binary"; break; - case RS6000_BTC_TERNARY: name3 = "ternary"; break; - case RS6000_BTC_QUATERNARY:name3 = "quaternary";break; - case RS6000_BTC_PREDICATE: name3 = "predicate"; break; - case RS6000_BTC_ABS: name3 = "abs"; break; - case RS6000_BTC_DST: name3 = "dst"; break; - } - - - fprintf (stderr, - "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n", - (name1) ? name1 : "---", fcode, - (name2) ? name2 : "---", (int) icode, - name3, - func_valid_p ? "" : ", not valid"); - } - - if (!func_valid_p) - { - rs6000_invalid_builtin (fcode); - - /* Given it is invalid, just generate a normal call. */ - return expand_call (exp, target, ignore); - } - - switch (fcode) - { - case RS6000_BUILTIN_RECIP: - return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target); - - case RS6000_BUILTIN_RECIPF: - return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target); - - case RS6000_BUILTIN_RSQRTF: - return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target); - - case RS6000_BUILTIN_RSQRT: - return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target); - - case POWER7_BUILTIN_BPERMD: - return rs6000_expand_binop_builtin (((TARGET_64BIT) - ? CODE_FOR_bpermd_di - : CODE_FOR_bpermd_si), exp, target); - - case RS6000_BUILTIN_GET_TB: - return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase, - target); - - case RS6000_BUILTIN_MFTB: - return rs6000_expand_zeroop_builtin (((TARGET_64BIT) - ? CODE_FOR_rs6000_mftb_di - : CODE_FOR_rs6000_mftb_si), - target); - - case RS6000_BUILTIN_MFFS: - return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target); - - case RS6000_BUILTIN_MTFSB0: - return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp); - - case RS6000_BUILTIN_MTFSB1: - return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp); - - case RS6000_BUILTIN_SET_FPSCR_RN: - return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn, - exp); - - case RS6000_BUILTIN_SET_FPSCR_DRN: - return - rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn, - exp); - - case RS6000_BUILTIN_MFFSL: - return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target); - - case RS6000_BUILTIN_MTFSF: - return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp); - - case RS6000_BUILTIN_CPU_INIT: - case RS6000_BUILTIN_CPU_IS: - case RS6000_BUILTIN_CPU_SUPPORTS: - return cpu_expand_builtin (fcode, exp, target); - - case MISC_BUILTIN_SPEC_BARRIER: - { - emit_insn (gen_speculation_barrier ()); - return NULL_RTX; - } - - case ALTIVEC_BUILTIN_MASK_FOR_LOAD: - { - int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct - : (int) CODE_FOR_altivec_lvsl_direct); - machine_mode tmode = insn_data[icode2].operand[0].mode; - machine_mode mode = insn_data[icode2].operand[1].mode; - tree arg; - rtx op, addr, pat; - - gcc_assert (TARGET_ALTIVEC); - - arg = CALL_EXPR_ARG (exp, 0); - gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg))); - op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL); - addr = memory_address (mode, op); - /* We need to negate the address. */ - op = gen_reg_rtx (GET_MODE (addr)); - emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr))); - op = gen_rtx_MEM (mode, op); - - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode2].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - - pat = GEN_FCN (icode2) (target, op); - if (!pat) - return 0; - emit_insn (pat); - - return target; - } - - case ALTIVEC_BUILTIN_VCFUX: - case ALTIVEC_BUILTIN_VCFSX: - case ALTIVEC_BUILTIN_VCTUXS: - case ALTIVEC_BUILTIN_VCTSXS: - /* FIXME: There's got to be a nicer way to handle this case than - constructing a new CALL_EXPR. */ - if (call_expr_nargs (exp) == 1) - { - exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp), - 2, CALL_EXPR_ARG (exp, 0), integer_zero_node); - } - break; - - /* For the pack and unpack int128 routines, fix up the builtin so it - uses the correct IBM128 type. */ - case MISC_BUILTIN_PACK_IF: - if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD) - { - icode = CODE_FOR_packtf; - fcode = MISC_BUILTIN_PACK_TF; - uns_fcode = (size_t)fcode; - } - break; - - case MISC_BUILTIN_UNPACK_IF: - if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD) - { - icode = CODE_FOR_unpacktf; - fcode = MISC_BUILTIN_UNPACK_TF; - uns_fcode = (size_t)fcode; - } - break; - - default: - break; - } - - if (TARGET_MMA) - { - ret = mma_expand_builtin (exp, target, &success); - - if (success) - return ret; - } - if (TARGET_ALTIVEC) - { - ret = altivec_expand_builtin (exp, target, &success); - - if (success) - return ret; - } - if (TARGET_HTM) - { - ret = htm_expand_builtin (exp, target, &success); - - if (success) - return ret; - } - - unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_OPND_MASK; - /* RS6000_BTC_SPECIAL represents no-operand operators. */ - gcc_assert (attr == RS6000_BTC_UNARY - || attr == RS6000_BTC_BINARY - || attr == RS6000_BTC_TERNARY - || attr == RS6000_BTC_QUATERNARY - || attr == RS6000_BTC_SPECIAL); - - /* Handle simple unary operations. */ - d = bdesc_1arg; - for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) - if (d->code == fcode) - return rs6000_expand_unop_builtin (icode, exp, target); - - /* Handle simple binary operations. */ - d = bdesc_2arg; - for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) - if (d->code == fcode) - return rs6000_expand_binop_builtin (icode, exp, target); - - /* Handle simple ternary operations. */ - d = bdesc_3arg; - for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) - if (d->code == fcode) - return rs6000_expand_ternop_builtin (icode, exp, target); - - /* Handle simple quaternary operations. */ - d = bdesc_4arg; - for (i = 0; i < ARRAY_SIZE (bdesc_4arg); i++, d++) - if (d->code == fcode) - return rs6000_expand_quaternop_builtin (icode, exp, target); - - /* Handle simple no-argument operations. */ - d = bdesc_0arg; - for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++) - if (d->code == fcode) - return rs6000_expand_zeroop_builtin (icode, target); - - gcc_unreachable (); -} - -/* Expand ALTIVEC_BUILTIN_MASK_FOR_LOAD. */ -rtx -rs6000_expand_ldst_mask (rtx target, tree arg0) -{ - int icode2 = BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct - : (int) CODE_FOR_altivec_lvsl_direct; - machine_mode tmode = insn_data[icode2].operand[0].mode; - machine_mode mode = insn_data[icode2].operand[1].mode; - - gcc_assert (TARGET_ALTIVEC); - - gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg0))); - rtx op = expand_expr (arg0, NULL_RTX, Pmode, EXPAND_NORMAL); - rtx addr = memory_address (mode, op); - /* We need to negate the address. */ - op = gen_reg_rtx (GET_MODE (addr)); - emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr))); - op = gen_rtx_MEM (mode, op); - - if (target == 0 - || GET_MODE (target) != tmode - || !insn_data[icode2].operand[0].predicate (target, tmode)) - target = gen_reg_rtx (tmode); - - rtx pat = GEN_FCN (icode2) (target, op); - if (!pat) - return 0; - emit_insn (pat); - - return target; -} - -/* Expand the CPU builtin in FCODE and store the result in TARGET. */ -static rtx -new_cpu_expand_builtin (enum rs6000_gen_builtins fcode, - tree exp ATTRIBUTE_UNUSED, rtx target) -{ - /* __builtin_cpu_init () is a nop, so expand to nothing. */ - if (fcode == RS6000_BIF_CPU_INIT) - return const0_rtx; - - if (target == 0 || GET_MODE (target) != SImode) - target = gen_reg_rtx (SImode); - - /* TODO: Factor the #ifdef'd code into a separate function. */ -#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB - tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0); - /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back - to a STRING_CST. */ - if (TREE_CODE (arg) == ARRAY_REF - && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST - && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST - && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0) - arg = TREE_OPERAND (arg, 0); - - if (TREE_CODE (arg) != STRING_CST) - { - error ("builtin %qs only accepts a string argument", - rs6000_builtin_info_x[(size_t) fcode].bifname); - return const0_rtx; - } - - if (fcode == RS6000_BIF_CPU_IS) - { - const char *cpu = TREE_STRING_POINTER (arg); - rtx cpuid = NULL_RTX; - for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++) - if (strcmp (cpu, cpu_is_info[i].cpu) == 0) - { - /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */ - cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM); - break; - } - if (cpuid == NULL_RTX) - { - /* Invalid CPU argument. */ - error ("cpu %qs is an invalid argument to builtin %qs", - cpu, rs6000_builtin_info_x[(size_t) fcode].bifname); - return const0_rtx; - } - - rtx platform = gen_reg_rtx (SImode); - rtx address = gen_rtx_PLUS (Pmode, - gen_rtx_REG (Pmode, TLS_REGNUM), - GEN_INT (TCB_PLATFORM_OFFSET)); - rtx tcbmem = gen_const_mem (SImode, address); - emit_move_insn (platform, tcbmem); - emit_insn (gen_eqsi3 (target, platform, cpuid)); - } - else if (fcode == RS6000_BIF_CPU_SUPPORTS) - { - const char *hwcap = TREE_STRING_POINTER (arg); - rtx mask = NULL_RTX; - int hwcap_offset; - for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++) - if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0) - { - mask = GEN_INT (cpu_supports_info[i].mask); - hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id); - break; - } - if (mask == NULL_RTX) - { - /* Invalid HWCAP argument. */ - error ("%s %qs is an invalid argument to builtin %qs", - "hwcap", hwcap, - rs6000_builtin_info_x[(size_t) fcode].bifname); - return const0_rtx; - } - - rtx tcb_hwcap = gen_reg_rtx (SImode); - rtx address = gen_rtx_PLUS (Pmode, - gen_rtx_REG (Pmode, TLS_REGNUM), - GEN_INT (hwcap_offset)); - rtx tcbmem = gen_const_mem (SImode, address); - emit_move_insn (tcb_hwcap, tcbmem); - rtx scratch1 = gen_reg_rtx (SImode); - emit_insn (gen_rtx_SET (scratch1, - gen_rtx_AND (SImode, tcb_hwcap, mask))); - rtx scratch2 = gen_reg_rtx (SImode); - emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx)); - emit_insn (gen_rtx_SET (target, - gen_rtx_XOR (SImode, scratch2, const1_rtx))); - } - else - gcc_unreachable (); - - /* Record that we have expanded a CPU builtin, so that we can later - emit a reference to the special symbol exported by LIBC to ensure we - do not link against an old LIBC that doesn't support this feature. */ - cpu_builtin_p = true; - -#else - warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware " - "capability bits", rs6000_builtin_info_x[(size_t) fcode].bifname); - - /* For old LIBCs, always return FALSE. */ - emit_move_insn (target, GEN_INT (0)); -#endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */ - - return target; -} - -/* For the element-reversing load/store built-ins, produce the correct - insn_code depending on the target endianness. */ -static insn_code -elemrev_icode (rs6000_gen_builtins fcode) -{ - switch (fcode) - { - case RS6000_BIF_ST_ELEMREV_V1TI: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti - : CODE_FOR_vsx_st_elemrev_v1ti; - - case RS6000_BIF_ST_ELEMREV_V2DF: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df - : CODE_FOR_vsx_st_elemrev_v2df; - - case RS6000_BIF_ST_ELEMREV_V2DI: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di - : CODE_FOR_vsx_st_elemrev_v2di; - - case RS6000_BIF_ST_ELEMREV_V4SF: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf - : CODE_FOR_vsx_st_elemrev_v4sf; - - case RS6000_BIF_ST_ELEMREV_V4SI: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si - : CODE_FOR_vsx_st_elemrev_v4si; - - case RS6000_BIF_ST_ELEMREV_V8HI: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi - : CODE_FOR_vsx_st_elemrev_v8hi; - - case RS6000_BIF_ST_ELEMREV_V16QI: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi - : CODE_FOR_vsx_st_elemrev_v16qi; - - case RS6000_BIF_LD_ELEMREV_V2DF: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df - : CODE_FOR_vsx_ld_elemrev_v2df; - - case RS6000_BIF_LD_ELEMREV_V1TI: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti - : CODE_FOR_vsx_ld_elemrev_v1ti; - - case RS6000_BIF_LD_ELEMREV_V2DI: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di - : CODE_FOR_vsx_ld_elemrev_v2di; - - case RS6000_BIF_LD_ELEMREV_V4SF: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf - : CODE_FOR_vsx_ld_elemrev_v4sf; - - case RS6000_BIF_LD_ELEMREV_V4SI: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si - : CODE_FOR_vsx_ld_elemrev_v4si; - - case RS6000_BIF_LD_ELEMREV_V8HI: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi - : CODE_FOR_vsx_ld_elemrev_v8hi; - - case RS6000_BIF_LD_ELEMREV_V16QI: - return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi - : CODE_FOR_vsx_ld_elemrev_v16qi; - default: - ; - } - - gcc_unreachable (); -} - -/* Expand an AltiVec vector load builtin, and return the expanded rtx. */ -static rtx -ldv_expand_builtin (rtx target, insn_code icode, rtx *op, machine_mode tmode) -{ - if (target == 0 - || GET_MODE (target) != tmode - || !insn_data[icode].operand[0].predicate (target, tmode)) - target = gen_reg_rtx (tmode); - - op[1] = copy_to_mode_reg (Pmode, op[1]); - - /* These CELL built-ins use BLKmode instead of tmode for historical - (i.e., unknown) reasons. TODO: Is this necessary? */ - bool blk = (icode == CODE_FOR_altivec_lvlx - || icode == CODE_FOR_altivec_lvlxl - || icode == CODE_FOR_altivec_lvrx - || icode == CODE_FOR_altivec_lvrxl); - - /* For LVX, express the RTL accurately by ANDing the address with -16. - LVXL and LVE*X expand to use UNSPECs to hide their special behavior, - so the raw address is fine. */ - /* TODO: That statement seems wrong, as the UNSPECs don't surround the - memory expression, so a latent bug may lie here. The &-16 is likely - needed for all VMX-style loads. */ - if (icode == CODE_FOR_altivec_lvx_v1ti - || icode == CODE_FOR_altivec_lvx_v2df - || icode == CODE_FOR_altivec_lvx_v2di - || icode == CODE_FOR_altivec_lvx_v4sf - || icode == CODE_FOR_altivec_lvx_v4si - || icode == CODE_FOR_altivec_lvx_v8hi - || icode == CODE_FOR_altivec_lvx_v16qi) - { - rtx rawaddr; - if (op[0] == const0_rtx) - rawaddr = op[1]; - else - { - op[0] = copy_to_mode_reg (Pmode, op[0]); - rawaddr = gen_rtx_PLUS (Pmode, op[1], op[0]); - } - rtx addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16)); - addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr); - - emit_insn (gen_rtx_SET (target, addr)); - } - else - { - rtx addr; - if (op[0] == const0_rtx) - addr = gen_rtx_MEM (blk ? BLKmode : tmode, op[1]); - else - { - op[0] = copy_to_mode_reg (Pmode, op[0]); - addr = gen_rtx_MEM (blk ? BLKmode : tmode, - gen_rtx_PLUS (Pmode, op[1], op[0])); - } - - rtx pat = GEN_FCN (icode) (target, addr); - if (!pat) - return 0; - emit_insn (pat); - } - - return target; -} - -/* Expand a builtin function that loads a scalar into a vector register - with sign extension, and return the expanded rtx. */ -static rtx -lxvrse_expand_builtin (rtx target, insn_code icode, rtx *op, - machine_mode tmode, machine_mode smode) -{ - rtx pat, addr; - op[1] = copy_to_mode_reg (Pmode, op[1]); - - if (op[0] == const0_rtx) - addr = gen_rtx_MEM (tmode, op[1]); - else - { - op[0] = copy_to_mode_reg (Pmode, op[0]); - addr = gen_rtx_MEM (smode, - gen_rtx_PLUS (Pmode, op[1], op[0])); - } - - rtx discratch = gen_reg_rtx (V2DImode); - rtx tiscratch = gen_reg_rtx (TImode); - - /* Emit the lxvr*x insn. */ - pat = GEN_FCN (icode) (tiscratch, addr); - if (!pat) - return 0; - emit_insn (pat); - - /* Emit a sign extension from V16QI,V8HI,V4SI to V2DI. */ - rtx temp1; - if (icode == CODE_FOR_vsx_lxvrbx) - { - temp1 = simplify_gen_subreg (V16QImode, tiscratch, TImode, 0); - emit_insn (gen_vsx_sign_extend_qi_v2di (discratch, temp1)); - } - else if (icode == CODE_FOR_vsx_lxvrhx) - { - temp1 = simplify_gen_subreg (V8HImode, tiscratch, TImode, 0); - emit_insn (gen_vsx_sign_extend_hi_v2di (discratch, temp1)); - } - else if (icode == CODE_FOR_vsx_lxvrwx) - { - temp1 = simplify_gen_subreg (V4SImode, tiscratch, TImode, 0); - emit_insn (gen_vsx_sign_extend_si_v2di (discratch, temp1)); - } - else if (icode == CODE_FOR_vsx_lxvrdx) - discratch = simplify_gen_subreg (V2DImode, tiscratch, TImode, 0); - else - gcc_unreachable (); - - /* Emit the sign extension from V2DI (double) to TI (quad). */ - rtx temp2 = simplify_gen_subreg (TImode, discratch, V2DImode, 0); - emit_insn (gen_extendditi2_vector (target, temp2)); - - return target; -} - -/* Expand a builtin function that loads a scalar into a vector register - with zero extension, and return the expanded rtx. */ -static rtx -lxvrze_expand_builtin (rtx target, insn_code icode, rtx *op, - machine_mode tmode, machine_mode smode) -{ - rtx pat, addr; - op[1] = copy_to_mode_reg (Pmode, op[1]); - - if (op[0] == const0_rtx) - addr = gen_rtx_MEM (tmode, op[1]); - else - { - op[0] = copy_to_mode_reg (Pmode, op[0]); - addr = gen_rtx_MEM (smode, - gen_rtx_PLUS (Pmode, op[1], op[0])); - } - - pat = GEN_FCN (icode) (target, addr); - if (!pat) - return 0; - emit_insn (pat); - return target; -} - -/* Expand an AltiVec vector store builtin, and return the expanded rtx. */ -static rtx -stv_expand_builtin (insn_code icode, rtx *op, - machine_mode tmode, machine_mode smode) -{ - op[2] = copy_to_mode_reg (Pmode, op[2]); - - /* For STVX, express the RTL accurately by ANDing the address with -16. - STVXL and STVE*X expand to use UNSPECs to hide their special behavior, - so the raw address is fine. */ - /* TODO: That statement seems wrong, as the UNSPECs don't surround the - memory expression, so a latent bug may lie here. The &-16 is likely - needed for all VMX-style stores. */ - if (icode == CODE_FOR_altivec_stvx_v2df - || icode == CODE_FOR_altivec_stvx_v2di - || icode == CODE_FOR_altivec_stvx_v4sf - || icode == CODE_FOR_altivec_stvx_v4si - || icode == CODE_FOR_altivec_stvx_v8hi - || icode == CODE_FOR_altivec_stvx_v16qi) - { - rtx rawaddr; - if (op[1] == const0_rtx) - rawaddr = op[2]; - else - { - op[1] = copy_to_mode_reg (Pmode, op[1]); - rawaddr = gen_rtx_PLUS (Pmode, op[2], op[1]); - } - - rtx addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16)); - addr = gen_rtx_MEM (tmode, addr); - op[0] = copy_to_mode_reg (tmode, op[0]); - emit_insn (gen_rtx_SET (addr, op[0])); - } - else if (icode == CODE_FOR_vsx_stxvrbx - || icode == CODE_FOR_vsx_stxvrhx - || icode == CODE_FOR_vsx_stxvrwx - || icode == CODE_FOR_vsx_stxvrdx) - { - rtx truncrtx = gen_rtx_TRUNCATE (tmode, op[0]); - op[0] = copy_to_mode_reg (E_TImode, truncrtx); - - rtx addr; - if (op[1] == const0_rtx) - addr = gen_rtx_MEM (Pmode, op[2]); - else - { - op[1] = copy_to_mode_reg (Pmode, op[1]); - addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1])); - } - rtx pat = GEN_FCN (icode) (addr, op[0]); - if (pat) - emit_insn (pat); - } - else - { - if (!insn_data[icode].operand[1].predicate (op[0], smode)) - op[0] = copy_to_mode_reg (smode, op[0]); - - rtx addr; - if (op[1] == const0_rtx) - addr = gen_rtx_MEM (tmode, op[2]); - else - { - op[1] = copy_to_mode_reg (Pmode, op[1]); - addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1])); - } - - rtx pat = GEN_FCN (icode) (addr, op[0]); - if (pat) - emit_insn (pat); - } - - return NULL_RTX; -} - -/* Expand the MMA built-in in EXP, and return it. */ -static rtx -new_mma_expand_builtin (tree exp, rtx target, insn_code icode, - rs6000_gen_builtins fcode) -{ - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - bool void_func = TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node; - machine_mode tmode = VOIDmode; - rtx op[MAX_MMA_OPERANDS]; - unsigned nopnds = 0; - - if (!void_func) - { - tmode = insn_data[icode].operand[0].mode; - if (!(target - && GET_MODE (target) == tmode - && insn_data[icode].operand[0].predicate (target, tmode))) - target = gen_reg_rtx (tmode); - op[nopnds++] = target; - } - else - target = const0_rtx; - - call_expr_arg_iterator iter; - tree arg; - FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) - { - if (arg == error_mark_node) - return const0_rtx; - - rtx opnd; - const struct insn_operand_data *insn_op; - insn_op = &insn_data[icode].operand[nopnds]; - if (TREE_CODE (arg) == ADDR_EXPR - && MEM_P (DECL_RTL (TREE_OPERAND (arg, 0)))) - opnd = DECL_RTL (TREE_OPERAND (arg, 0)); - else - opnd = expand_normal (arg); - - if (!insn_op->predicate (opnd, insn_op->mode)) - { - /* TODO: This use of constraints needs explanation. */ - if (!strcmp (insn_op->constraint, "n")) - { - if (!CONST_INT_P (opnd)) - error ("argument %d must be an unsigned literal", nopnds); - else - error ("argument %d is an unsigned literal that is " - "out of range", nopnds); - return const0_rtx; - } - opnd = copy_to_mode_reg (insn_op->mode, opnd); - } - - /* Some MMA instructions have INOUT accumulator operands, so force - their target register to be the same as their input register. */ - if (!void_func - && nopnds == 1 - && !strcmp (insn_op->constraint, "0") - && insn_op->mode == tmode - && REG_P (opnd) - && insn_data[icode].operand[0].predicate (opnd, tmode)) - target = op[0] = opnd; - - op[nopnds++] = opnd; - } - - rtx pat; - switch (nopnds) - { - case 1: - pat = GEN_FCN (icode) (op[0]); - break; - case 2: - pat = GEN_FCN (icode) (op[0], op[1]); - break; - case 3: - /* The ASSEMBLE builtin source operands are reversed in little-endian - mode, so reorder them. */ - if (fcode == RS6000_BIF_ASSEMBLE_PAIR_V_INTERNAL && !WORDS_BIG_ENDIAN) - std::swap (op[1], op[2]); - pat = GEN_FCN (icode) (op[0], op[1], op[2]); - break; - case 4: - pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); - break; - case 5: - /* The ASSEMBLE builtin source operands are reversed in little-endian - mode, so reorder them. */ - if (fcode == RS6000_BIF_ASSEMBLE_ACC_INTERNAL && !WORDS_BIG_ENDIAN) - { - std::swap (op[1], op[4]); - std::swap (op[2], op[3]); - } - pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); - break; - case 6: - pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]); - break; - case 7: - pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5], op[6]); - break; - default: - gcc_unreachable (); - } - - if (!pat) - return NULL_RTX; - - emit_insn (pat); - return target; -} - -/* Return the appropriate SPR number associated with the given builtin. */ -static inline HOST_WIDE_INT -new_htm_spr_num (enum rs6000_gen_builtins code) -{ - if (code == RS6000_BIF_GET_TFHAR - || code == RS6000_BIF_SET_TFHAR) - return TFHAR_SPR; - else if (code == RS6000_BIF_GET_TFIAR - || code == RS6000_BIF_SET_TFIAR) - return TFIAR_SPR; - else if (code == RS6000_BIF_GET_TEXASR - || code == RS6000_BIF_SET_TEXASR) - return TEXASR_SPR; - gcc_assert (code == RS6000_BIF_GET_TEXASRU - || code == RS6000_BIF_SET_TEXASRU); - return TEXASRU_SPR; -} - -/* Expand the HTM builtin in EXP and store the result in TARGET. - Return the expanded rtx. */ -static rtx -new_htm_expand_builtin (bifdata *bifaddr, rs6000_gen_builtins fcode, - tree exp, rtx target) -{ - if (!TARGET_POWERPC64 - && (fcode == RS6000_BIF_TABORTDC - || fcode == RS6000_BIF_TABORTDCI)) - { - error ("builtin %qs is only valid in 64-bit mode", bifaddr->bifname); - return const0_rtx; - } - - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; - bool uses_spr = bif_is_htmspr (*bifaddr); - insn_code icode = bifaddr->icode; - - if (uses_spr) - icode = rs6000_htm_spr_icode (nonvoid); - - rtx op[MAX_HTM_OPERANDS]; - int nopnds = 0; - const insn_operand_data *insn_op = &insn_data[icode].operand[0]; - - if (nonvoid) - { - machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode; - if (!target - || GET_MODE (target) != tmode - || (uses_spr && !insn_op->predicate (target, tmode))) - target = gen_reg_rtx (tmode); - if (uses_spr) - op[nopnds++] = target; - } - - tree arg; - call_expr_arg_iterator iter; - - FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) - { - if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS) - return const0_rtx; - - insn_op = &insn_data[icode].operand[nopnds]; - op[nopnds] = expand_normal (arg); - - if (!insn_op->predicate (op[nopnds], insn_op->mode)) - { - /* TODO: This use of constraints could use explanation. - This happens a couple of places, perhaps make that a - function to document what's happening. */ - if (!strcmp (insn_op->constraint, "n")) - { - int arg_num = nonvoid ? nopnds : nopnds + 1; - if (!CONST_INT_P (op[nopnds])) - error ("argument %d must be an unsigned literal", arg_num); - else - error ("argument %d is an unsigned literal that is " - "out of range", arg_num); - return const0_rtx; - } - op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]); - } - - nopnds++; - } - - /* Handle the builtins for extended mnemonics. These accept - no arguments, but map to builtins that take arguments. */ - switch (fcode) - { - case RS6000_BIF_TENDALL: /* Alias for: tend. 1 */ - case RS6000_BIF_TRESUME: /* Alias for: tsr. 1 */ - op[nopnds++] = GEN_INT (1); - break; - case RS6000_BIF_TSUSPEND: /* Alias for: tsr. 0 */ - op[nopnds++] = GEN_INT (0); - break; - default: - break; - } + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + /* Flavors of vector shift right algebraic. + vec_sra{b,h,w} -> vsra{b,h,w}. */ + case RS6000_BIF_VSRAB: + case RS6000_BIF_VSRAH: + case RS6000_BIF_VSRAW: + case RS6000_BIF_VSRAD: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + tree arg1_type = TREE_TYPE (arg1); + tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); + tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); + location_t loc = gimple_location (stmt); + /* Force arg1 into the range valid matching the arg0 type. */ + /* Build a vector consisting of the max valid bit-size values. */ + int n_elts = VECTOR_CST_NELTS (arg1); + tree element_size = build_int_cst (unsigned_element_type, + 128 / n_elts); + tree_vector_builder elts (unsigned_arg1_type, n_elts, 1); + for (int i = 0; i < n_elts; i++) + elts.safe_push (element_size); + tree modulo_tree = elts.build (); + /* Modulo the provided shift value against that vector. */ + gimple_seq stmts = NULL; + tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, + unsigned_arg1_type, arg1); + tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, + unsigned_arg1_type, unsigned_arg1, + modulo_tree); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + /* And finally, do the shift. */ + g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1); + gimple_set_location (g, loc); + gsi_replace (gsi, g, true); + return true; + } + /* Flavors of vector shift left. + builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */ + case RS6000_BIF_VSLB: + case RS6000_BIF_VSLH: + case RS6000_BIF_VSLW: + case RS6000_BIF_VSLD: + { + location_t loc; + gimple_seq stmts = NULL; + arg0 = gimple_call_arg (stmt, 0); + tree arg0_type = TREE_TYPE (arg0); + if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type)) + && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type))) + return false; + arg1 = gimple_call_arg (stmt, 1); + tree arg1_type = TREE_TYPE (arg1); + tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); + tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); + loc = gimple_location (stmt); + lhs = gimple_call_lhs (stmt); + /* Force arg1 into the range valid matching the arg0 type. */ + /* Build a vector consisting of the max valid bit-size values. */ + int n_elts = VECTOR_CST_NELTS (arg1); + int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type)) + * BITS_PER_UNIT; + tree element_size = build_int_cst (unsigned_element_type, + tree_size_in_bits / n_elts); + tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1); + for (int i = 0; i < n_elts; i++) + elts.safe_push (element_size); + tree modulo_tree = elts.build (); + /* Modulo the provided shift value against that vector. */ + tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, + unsigned_arg1_type, arg1); + tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, + unsigned_arg1_type, unsigned_arg1, + modulo_tree); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + /* And finally, do the shift. */ + g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* Flavors of vector shift right. */ + case RS6000_BIF_VSRB: + case RS6000_BIF_VSRH: + case RS6000_BIF_VSRW: + case RS6000_BIF_VSRD: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + tree arg1_type = TREE_TYPE (arg1); + tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1)); + tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type)); + location_t loc = gimple_location (stmt); + gimple_seq stmts = NULL; + /* Convert arg0 to unsigned. */ + tree arg0_unsigned + = gimple_build (&stmts, VIEW_CONVERT_EXPR, + unsigned_type_for (TREE_TYPE (arg0)), arg0); + /* Force arg1 into the range valid matching the arg0 type. */ + /* Build a vector consisting of the max valid bit-size values. */ + int n_elts = VECTOR_CST_NELTS (arg1); + tree element_size = build_int_cst (unsigned_element_type, + 128 / n_elts); + tree_vector_builder elts (unsigned_arg1_type, n_elts, 1); + for (int i = 0; i < n_elts; i++) + elts.safe_push (element_size); + tree modulo_tree = elts.build (); + /* Modulo the provided shift value against that vector. */ + tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR, + unsigned_arg1_type, arg1); + tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR, + unsigned_arg1_type, unsigned_arg1, + modulo_tree); + /* Do the shift. */ + tree res + = gimple_build (&stmts, RSHIFT_EXPR, + TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1); + /* Convert result back to the lhs type. */ + res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + replace_call_with_value (gsi, res); + return true; + } + /* Vector loads. */ + case RS6000_BIF_LVX_V16QI: + case RS6000_BIF_LVX_V8HI: + case RS6000_BIF_LVX_V4SI: + case RS6000_BIF_LVX_V4SF: + case RS6000_BIF_LVX_V2DI: + case RS6000_BIF_LVX_V2DF: + case RS6000_BIF_LVX_V1TI: + { + arg0 = gimple_call_arg (stmt, 0); // offset + arg1 = gimple_call_arg (stmt, 1); // address + lhs = gimple_call_lhs (stmt); + location_t loc = gimple_location (stmt); + /* Since arg1 may be cast to a different type, just use ptr_type_node + here instead of trying to enforce TBAA on pointer types. */ + tree arg1_type = ptr_type_node; + tree lhs_type = TREE_TYPE (lhs); + /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create + the tree using the value from arg0. The resulting type will match + the type of arg1. */ + gimple_seq stmts = NULL; + tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0); + tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, + arg1_type, arg1, temp_offset); + /* Mask off any lower bits from the address. */ + tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR, + arg1_type, temp_addr, + build_int_cst (arg1_type, -16)); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + if (!is_gimple_mem_ref_addr (aligned_addr)) + { + tree t = make_ssa_name (TREE_TYPE (aligned_addr)); + gimple *g = gimple_build_assign (t, aligned_addr); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + aligned_addr = t; + } + /* Use the build2 helper to set up the mem_ref. The MEM_REF could also + take an offset, but since we've already incorporated the offset + above, here we just pass in a zero. */ + gimple *g + = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr, + build_int_cst (arg1_type, 0))); + gimple_set_location (g, loc); + gsi_replace (gsi, g, true); + return true; + } + /* Vector stores. */ + case RS6000_BIF_STVX_V16QI: + case RS6000_BIF_STVX_V8HI: + case RS6000_BIF_STVX_V4SI: + case RS6000_BIF_STVX_V4SF: + case RS6000_BIF_STVX_V2DI: + case RS6000_BIF_STVX_V2DF: + { + arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */ + arg1 = gimple_call_arg (stmt, 1); /* Offset. */ + tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */ + location_t loc = gimple_location (stmt); + tree arg0_type = TREE_TYPE (arg0); + /* Use ptr_type_node (no TBAA) for the arg2_type. + FIXME: (Richard) "A proper fix would be to transition this type as + seen from the frontend to GIMPLE, for example in a similar way we + do for MEM_REFs by piggy-backing that on an extra argument, a + constant zero pointer of the alias pointer type to use (which would + also serve as a type indicator of the store itself). I'd use a + target specific internal function for this (not sure if we can have + those target specific, but I guess if it's folded away then that's + fine) and get away with the overload set." */ + tree arg2_type = ptr_type_node; + /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create + the tree using the value from arg0. The resulting type will match + the type of arg2. */ + gimple_seq stmts = NULL; + tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1); + tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, + arg2_type, arg2, temp_offset); + /* Mask off any lower bits from the address. */ + tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR, + arg2_type, temp_addr, + build_int_cst (arg2_type, -16)); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + if (!is_gimple_mem_ref_addr (aligned_addr)) + { + tree t = make_ssa_name (TREE_TYPE (aligned_addr)); + gimple *g = gimple_build_assign (t, aligned_addr); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + aligned_addr = t; + } + /* The desired gimple result should be similar to: + MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */ + gimple *g + = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr, + build_int_cst (arg2_type, 0)), arg0); + gimple_set_location (g, loc); + gsi_replace (gsi, g, true); + return true; + } - /* If this builtin accesses SPRs, then pass in the appropriate - SPR number and SPR regno as the last two operands. */ - rtx cr = NULL_RTX; - if (uses_spr) - { - machine_mode mode = TARGET_POWERPC64 ? DImode : SImode; - op[nopnds++] = gen_rtx_CONST_INT (mode, new_htm_spr_num (fcode)); - } - /* If this builtin accesses a CR field, then pass in a scratch - CR field as the last operand. */ - else if (bif_is_htmcr (*bifaddr)) - { - cr = gen_reg_rtx (CCmode); - op[nopnds++] = cr; - } + /* unaligned Vector loads. */ + case RS6000_BIF_LXVW4X_V16QI: + case RS6000_BIF_LXVW4X_V8HI: + case RS6000_BIF_LXVW4X_V4SF: + case RS6000_BIF_LXVW4X_V4SI: + case RS6000_BIF_LXVD2X_V2DF: + case RS6000_BIF_LXVD2X_V2DI: + { + arg0 = gimple_call_arg (stmt, 0); // offset + arg1 = gimple_call_arg (stmt, 1); // address + lhs = gimple_call_lhs (stmt); + location_t loc = gimple_location (stmt); + /* Since arg1 may be cast to a different type, just use ptr_type_node + here instead of trying to enforce TBAA on pointer types. */ + tree arg1_type = ptr_type_node; + tree lhs_type = TREE_TYPE (lhs); + /* In GIMPLE the type of the MEM_REF specifies the alignment. The + required alignment (power) is 4 bytes regardless of data type. */ + tree align_ltype = build_aligned_type (lhs_type, 4); + /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create + the tree using the value from arg0. The resulting type will match + the type of arg1. */ + gimple_seq stmts = NULL; + tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0); + tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, + arg1_type, arg1, temp_offset); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + if (!is_gimple_mem_ref_addr (temp_addr)) + { + tree t = make_ssa_name (TREE_TYPE (temp_addr)); + gimple *g = gimple_build_assign (t, temp_addr); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + temp_addr = t; + } + /* Use the build2 helper to set up the mem_ref. The MEM_REF could also + take an offset, but since we've already incorporated the offset + above, here we just pass in a zero. */ + gimple *g; + g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr, + build_int_cst (arg1_type, 0))); + gimple_set_location (g, loc); + gsi_replace (gsi, g, true); + return true; + } - rtx pat; - switch (nopnds) - { - case 1: - pat = GEN_FCN (icode) (op[0]); - break; - case 2: - pat = GEN_FCN (icode) (op[0], op[1]); - break; - case 3: - pat = GEN_FCN (icode) (op[0], op[1], op[2]); - break; - case 4: - pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); - break; - default: - gcc_unreachable (); - } - if (!pat) - return NULL_RTX; - emit_insn (pat); + /* unaligned Vector stores. */ + case RS6000_BIF_STXVW4X_V16QI: + case RS6000_BIF_STXVW4X_V8HI: + case RS6000_BIF_STXVW4X_V4SF: + case RS6000_BIF_STXVW4X_V4SI: + case RS6000_BIF_STXVD2X_V2DF: + case RS6000_BIF_STXVD2X_V2DI: + { + arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */ + arg1 = gimple_call_arg (stmt, 1); /* Offset. */ + tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */ + location_t loc = gimple_location (stmt); + tree arg0_type = TREE_TYPE (arg0); + /* Use ptr_type_node (no TBAA) for the arg2_type. */ + tree arg2_type = ptr_type_node; + /* In GIMPLE the type of the MEM_REF specifies the alignment. The + required alignment (power) is 4 bytes regardless of data type. */ + tree align_stype = build_aligned_type (arg0_type, 4); + /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create + the tree using the value from arg1. */ + gimple_seq stmts = NULL; + tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1); + tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR, + arg2_type, arg2, temp_offset); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + if (!is_gimple_mem_ref_addr (temp_addr)) + { + tree t = make_ssa_name (TREE_TYPE (temp_addr)); + gimple *g = gimple_build_assign (t, temp_addr); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + temp_addr = t; + } + gimple *g; + g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr, + build_int_cst (arg2_type, 0)), arg0); + gimple_set_location (g, loc); + gsi_replace (gsi, g, true); + return true; + } - if (bif_is_htmcr (*bifaddr)) - { - if (fcode == RS6000_BIF_TBEGIN) - { - /* Emit code to set TARGET to true or false depending on - whether the tbegin. instruction succeeded or failed - to start a transaction. We do this by placing the 1's - complement of CR's EQ bit into TARGET. */ - rtx scratch = gen_reg_rtx (SImode); - emit_insn (gen_rtx_SET (scratch, - gen_rtx_EQ (SImode, cr, - const0_rtx))); - emit_insn (gen_rtx_SET (target, - gen_rtx_XOR (SImode, scratch, - GEN_INT (1)))); - } - else - { - /* Emit code to copy the 4-bit condition register field - CR into the least significant end of register TARGET. */ - rtx scratch1 = gen_reg_rtx (SImode); - rtx scratch2 = gen_reg_rtx (SImode); - rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0); - emit_insn (gen_movcc (subreg, cr)); - emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28))); - emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf))); - } - } + /* Vector Fused multiply-add (fma). */ + case RS6000_BIF_VMADDFP: + case RS6000_BIF_XVMADDDP: + case RS6000_BIF_XVMADDSP: + case RS6000_BIF_VMLADDUHM: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + tree arg2 = gimple_call_arg (stmt, 2); + lhs = gimple_call_lhs (stmt); + gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2); + gimple_call_set_lhs (g, lhs); + gimple_call_set_nothrow (g, true); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } - if (nonvoid) - return target; - return const0_rtx; -} + /* Vector compares; EQ, NE, GE, GT, LE. */ + case RS6000_BIF_VCMPEQUB: + case RS6000_BIF_VCMPEQUH: + case RS6000_BIF_VCMPEQUW: + case RS6000_BIF_VCMPEQUD: + /* We deliberately omit RS6000_BIF_VCMPEQUT for now, because gimple + folding produces worse code for 128-bit compares. */ + fold_compare_helper (gsi, EQ_EXPR, stmt); + return true; -/* Expand an expression EXP that calls a built-in function, - with result going to TARGET if that's convenient - (and in mode MODE if that's convenient). - SUBTARGET may be used as the target for computing one of EXP's operands. - IGNORE is nonzero if the value is to be ignored. - Use the new builtin infrastructure. */ -static rtx -rs6000_expand_new_builtin (tree exp, rtx target, - rtx /* subtarget */, - machine_mode /* mode */, - int ignore) -{ - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - enum rs6000_gen_builtins fcode - = (enum rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl); - size_t uns_fcode = (size_t)fcode; - enum insn_code icode = rs6000_builtin_info_x[uns_fcode].icode; + case RS6000_BIF_VCMPNEB: + case RS6000_BIF_VCMPNEH: + case RS6000_BIF_VCMPNEW: + /* We deliberately omit RS6000_BIF_VCMPNET for now, because gimple + folding produces worse code for 128-bit compares. */ + fold_compare_helper (gsi, NE_EXPR, stmt); + return true; - /* TODO: The following commentary and code is inherited from the original - builtin processing code. The commentary is a bit confusing, with the - intent being that KFmode is always IEEE-128, IFmode is always IBM - double-double, and TFmode is the current long double. The code is - confusing in that it converts from KFmode to TFmode pattern names, - when the other direction is more intuitive. Try to address this. */ + case RS6000_BIF_CMPGE_16QI: + case RS6000_BIF_CMPGE_U16QI: + case RS6000_BIF_CMPGE_8HI: + case RS6000_BIF_CMPGE_U8HI: + case RS6000_BIF_CMPGE_4SI: + case RS6000_BIF_CMPGE_U4SI: + case RS6000_BIF_CMPGE_2DI: + case RS6000_BIF_CMPGE_U2DI: + /* We deliberately omit RS6000_BIF_CMPGE_1TI and RS6000_BIF_CMPGE_U1TI + for now, because gimple folding produces worse code for 128-bit + compares. */ + fold_compare_helper (gsi, GE_EXPR, stmt); + return true; - /* We have two different modes (KFmode, TFmode) that are the IEEE - 128-bit floating point type, depending on whether long double is the - IBM extended double (KFmode) or long double is IEEE 128-bit (TFmode). - It is simpler if we only define one variant of the built-in function, - and switch the code when defining it, rather than defining two built- - ins and using the overload table in rs6000-c.c to switch between the - two. If we don't have the proper assembler, don't do this switch - because CODE_FOR_*kf* and CODE_FOR_*tf* will be CODE_FOR_nothing. */ - if (FLOAT128_IEEE_P (TFmode)) - switch (icode) - { - case CODE_FOR_sqrtkf2_odd: - icode = CODE_FOR_sqrttf2_odd; - break; - case CODE_FOR_trunckfdf2_odd: - icode = CODE_FOR_trunctfdf2_odd; - break; - case CODE_FOR_addkf3_odd: - icode = CODE_FOR_addtf3_odd; - break; - case CODE_FOR_subkf3_odd: - icode = CODE_FOR_subtf3_odd; - break; - case CODE_FOR_mulkf3_odd: - icode = CODE_FOR_multf3_odd; - break; - case CODE_FOR_divkf3_odd: - icode = CODE_FOR_divtf3_odd; - break; - case CODE_FOR_fmakf4_odd: - icode = CODE_FOR_fmatf4_odd; - break; - case CODE_FOR_xsxexpqp_kf: - icode = CODE_FOR_xsxexpqp_tf; - break; - case CODE_FOR_xsxsigqp_kf: - icode = CODE_FOR_xsxsigqp_tf; - break; - case CODE_FOR_xststdcnegqp_kf: - icode = CODE_FOR_xststdcnegqp_tf; - break; - case CODE_FOR_xsiexpqp_kf: - icode = CODE_FOR_xsiexpqp_tf; - break; - case CODE_FOR_xsiexpqpf_kf: - icode = CODE_FOR_xsiexpqpf_tf; - break; - case CODE_FOR_xststdcqp_kf: - icode = CODE_FOR_xststdcqp_tf; - break; - case CODE_FOR_xscmpexpqp_eq_kf: - icode = CODE_FOR_xscmpexpqp_eq_tf; - break; - case CODE_FOR_xscmpexpqp_lt_kf: - icode = CODE_FOR_xscmpexpqp_lt_tf; - break; - case CODE_FOR_xscmpexpqp_gt_kf: - icode = CODE_FOR_xscmpexpqp_gt_tf; - break; - case CODE_FOR_xscmpexpqp_unordered_kf: - icode = CODE_FOR_xscmpexpqp_unordered_tf; - break; - default: - break; + case RS6000_BIF_VCMPGTSB: + case RS6000_BIF_VCMPGTUB: + case RS6000_BIF_VCMPGTSH: + case RS6000_BIF_VCMPGTUH: + case RS6000_BIF_VCMPGTSW: + case RS6000_BIF_VCMPGTUW: + case RS6000_BIF_VCMPGTUD: + case RS6000_BIF_VCMPGTSD: + /* We deliberately omit RS6000_BIF_VCMPGTUT and RS6000_BIF_VCMPGTST + for now, because gimple folding produces worse code for 128-bit + compares. */ + fold_compare_helper (gsi, GT_EXPR, stmt); + return true; + + case RS6000_BIF_CMPLE_16QI: + case RS6000_BIF_CMPLE_U16QI: + case RS6000_BIF_CMPLE_8HI: + case RS6000_BIF_CMPLE_U8HI: + case RS6000_BIF_CMPLE_4SI: + case RS6000_BIF_CMPLE_U4SI: + case RS6000_BIF_CMPLE_2DI: + case RS6000_BIF_CMPLE_U2DI: + /* We deliberately omit RS6000_BIF_CMPLE_1TI and RS6000_BIF_CMPLE_U1TI + for now, because gimple folding produces worse code for 128-bit + compares. */ + fold_compare_helper (gsi, LE_EXPR, stmt); + return true; + + /* flavors of vec_splat_[us]{8,16,32}. */ + case RS6000_BIF_VSPLTISB: + case RS6000_BIF_VSPLTISH: + case RS6000_BIF_VSPLTISW: + { + arg0 = gimple_call_arg (stmt, 0); + lhs = gimple_call_lhs (stmt); + + /* Only fold the vec_splat_*() if the lower bits of arg 0 is a + 5-bit signed constant in range -16 to +15. */ + if (TREE_CODE (arg0) != INTEGER_CST + || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15)) + return false; + gimple_seq stmts = NULL; + location_t loc = gimple_location (stmt); + tree splat_value = gimple_convert (&stmts, loc, + TREE_TYPE (TREE_TYPE (lhs)), arg0); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value); + g = gimple_build_assign (lhs, splat_tree); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; } - /* In case of "#pragma target" changes, we initialize all builtins - but check for actual availability now, during expand time. For - invalid builtins, generate a normal call. */ - bifdata *bifaddr = &rs6000_builtin_info_x[uns_fcode]; - bif_enable e = bifaddr->enable; + /* Flavors of vec_splat. */ + /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */ + case RS6000_BIF_VSPLTB: + case RS6000_BIF_VSPLTH: + case RS6000_BIF_VSPLTW: + case RS6000_BIF_XXSPLTD_V2DI: + case RS6000_BIF_XXSPLTD_V2DF: + { + arg0 = gimple_call_arg (stmt, 0); /* input vector. */ + arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */ + /* Only fold the vec_splat_*() if arg1 is both a constant value and + is a valid index into the arg0 vector. */ + unsigned int n_elts = VECTOR_CST_NELTS (arg0); + if (TREE_CODE (arg1) != INTEGER_CST + || TREE_INT_CST_LOW (arg1) > (n_elts -1)) + return false; + lhs = gimple_call_lhs (stmt); + tree lhs_type = TREE_TYPE (lhs); + tree arg0_type = TREE_TYPE (arg0); + tree splat; + if (TREE_CODE (arg0) == VECTOR_CST) + splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1)); + else + { + /* Determine (in bits) the length and start location of the + splat value for a call to the tree_vec_extract helper. */ + int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type)) + * BITS_PER_UNIT / n_elts; + int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size; + tree len = build_int_cst (bitsizetype, splat_elem_size); + tree start = build_int_cst (bitsizetype, splat_start_bit); + splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0, + len, start); + } + /* And finally, build the new vector. */ + tree splat_tree = build_vector_from_val (lhs_type, splat); + g = gimple_build_assign (lhs, splat_tree); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } - if (!(e == ENB_ALWAYS - || (e == ENB_P5 && TARGET_POPCNTB) - || (e == ENB_P6 && TARGET_CMPB) - || (e == ENB_P6_64 && TARGET_CMPB && TARGET_POWERPC64) - || (e == ENB_ALTIVEC && TARGET_ALTIVEC) - || (e == ENB_CELL && TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL) - || (e == ENB_VSX && TARGET_VSX) - || (e == ENB_P7 && TARGET_POPCNTD) - || (e == ENB_P7_64 && TARGET_POPCNTD && TARGET_POWERPC64) - || (e == ENB_P8 && TARGET_DIRECT_MOVE) - || (e == ENB_P8V && TARGET_P8_VECTOR) - || (e == ENB_P9 && TARGET_MODULO) - || (e == ENB_P9_64 && TARGET_MODULO && TARGET_POWERPC64) - || (e == ENB_P9V && TARGET_P9_VECTOR) - || (e == ENB_IEEE128_HW && TARGET_FLOAT128_HW) - || (e == ENB_DFP && TARGET_DFP) - || (e == ENB_CRYPTO && TARGET_CRYPTO) - || (e == ENB_HTM && TARGET_HTM) - || (e == ENB_P10 && TARGET_POWER10) - || (e == ENB_P10_64 && TARGET_POWER10 && TARGET_POWERPC64) - || (e == ENB_MMA && TARGET_MMA))) - { - rs6000_invalid_new_builtin (fcode); - return expand_call (exp, target, ignore); - } + /* vec_mergel (integrals). */ + case RS6000_BIF_VMRGLH: + case RS6000_BIF_VMRGLW: + case RS6000_BIF_XXMRGLW_4SI: + case RS6000_BIF_VMRGLB: + case RS6000_BIF_VEC_MERGEL_V2DI: + case RS6000_BIF_XXMRGLW_4SF: + case RS6000_BIF_VEC_MERGEL_V2DF: + fold_mergehl_helper (gsi, stmt, 1); + return true; + /* vec_mergeh (integrals). */ + case RS6000_BIF_VMRGHH: + case RS6000_BIF_VMRGHW: + case RS6000_BIF_XXMRGHW_4SI: + case RS6000_BIF_VMRGHB: + case RS6000_BIF_VEC_MERGEH_V2DI: + case RS6000_BIF_XXMRGHW_4SF: + case RS6000_BIF_VEC_MERGEH_V2DF: + fold_mergehl_helper (gsi, stmt, 0); + return true; - if (bif_is_nosoft (*bifaddr) - && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT) - { - error ("%<%s%> not supported with %<-msoft-float%>", - bifaddr->bifname); - return const0_rtx; - } + /* Flavors of vec_mergee. */ + case RS6000_BIF_VMRGEW_V4SI: + case RS6000_BIF_VMRGEW_V2DI: + case RS6000_BIF_VMRGEW_V4SF: + case RS6000_BIF_VMRGEW_V2DF: + fold_mergeeo_helper (gsi, stmt, 0); + return true; + /* Flavors of vec_mergeo. */ + case RS6000_BIF_VMRGOW_V4SI: + case RS6000_BIF_VMRGOW_V2DI: + case RS6000_BIF_VMRGOW_V4SF: + case RS6000_BIF_VMRGOW_V2DF: + fold_mergeeo_helper (gsi, stmt, 1); + return true; - if (bif_is_no32bit (*bifaddr) && TARGET_32BIT) - { - error ("%<%s%> is not supported in 32-bit mode", bifaddr->bifname); - return const0_rtx; - } + /* d = vec_pack (a, b) */ + case RS6000_BIF_VPKUDUM: + case RS6000_BIF_VPKUHUM: + case RS6000_BIF_VPKUWUM: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } - if (bif_is_ibmld (*bifaddr) && !FLOAT128_2REG_P (TFmode)) - { - error ("%<%s%> requires % to be IBM 128-bit format", - bifaddr->bifname); - return const0_rtx; - } + /* d = vec_unpackh (a) */ + /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call + in this code is sensitive to endian-ness, and needs to be inverted to + handle both LE and BE targets. */ + case RS6000_BIF_VUPKHSB: + case RS6000_BIF_VUPKHSH: + case RS6000_BIF_VUPKHSW: + { + arg0 = gimple_call_arg (stmt, 0); + lhs = gimple_call_lhs (stmt); + if (BYTES_BIG_ENDIAN) + g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0); + else + g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* d = vec_unpackl (a) */ + case RS6000_BIF_VUPKLSB: + case RS6000_BIF_VUPKLSH: + case RS6000_BIF_VUPKLSW: + { + arg0 = gimple_call_arg (stmt, 0); + lhs = gimple_call_lhs (stmt); + if (BYTES_BIG_ENDIAN) + g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0); + else + g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } + /* There is no gimple type corresponding with pixel, so just return. */ + case RS6000_BIF_VUPKHPX: + case RS6000_BIF_VUPKLPX: + return false; - if (bif_is_cpu (*bifaddr)) - return new_cpu_expand_builtin (fcode, exp, target); + /* vec_perm. */ + case RS6000_BIF_VPERM_16QI: + case RS6000_BIF_VPERM_8HI: + case RS6000_BIF_VPERM_4SI: + case RS6000_BIF_VPERM_2DI: + case RS6000_BIF_VPERM_4SF: + case RS6000_BIF_VPERM_2DF: + case RS6000_BIF_VPERM_16QI_UNS: + case RS6000_BIF_VPERM_8HI_UNS: + case RS6000_BIF_VPERM_4SI_UNS: + case RS6000_BIF_VPERM_2DI_UNS: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + tree permute = gimple_call_arg (stmt, 2); + lhs = gimple_call_lhs (stmt); + location_t loc = gimple_location (stmt); + gimple_seq stmts = NULL; + // convert arg0 and arg1 to match the type of the permute + // for the VEC_PERM_EXPR operation. + tree permute_type = (TREE_TYPE (permute)); + tree arg0_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, + permute_type, arg0); + tree arg1_ptype = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, + permute_type, arg1); + tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR, + permute_type, arg0_ptype, arg1_ptype, + permute); + // Convert the result back to the desired lhs type upon completion. + tree temp = gimple_build (&stmts, loc, VIEW_CONVERT_EXPR, + TREE_TYPE (lhs), lhs_ptype); + gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); + g = gimple_build_assign (lhs, temp); + gimple_set_location (g, loc); + gsi_replace (gsi, g, true); + return true; + } - if (bif_is_init (*bifaddr)) - return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target); + default: + if (TARGET_DEBUG_BUILTIN) + fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n", + fn_code, fn_name1, fn_name2); + break; + } - if (bif_is_set (*bifaddr)) - return altivec_expand_vec_set_builtin (exp); + return false; +} - if (bif_is_extract (*bifaddr)) - return altivec_expand_vec_ext_builtin (exp, target); +/* Expand an expression EXP that calls a built-in function, + with result going to TARGET if that's convenient + (and in mode MODE if that's convenient). + SUBTARGET may be used as the target for computing one of EXP's operands. + IGNORE is nonzero if the value is to be ignored. */ - if (bif_is_predicate (*bifaddr)) - return altivec_expand_predicate_builtin (icode, exp, target); +rtx +rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, + machine_mode mode ATTRIBUTE_UNUSED, + int ignore ATTRIBUTE_UNUSED) +{ + return rs6000_expand_new_builtin (exp, target, subtarget, mode, ignore); +} - if (bif_is_htm (*bifaddr)) - return new_htm_expand_builtin (bifaddr, fcode, exp, target); +/* Expand ALTIVEC_BUILTIN_MASK_FOR_LOAD. */ +rtx +rs6000_expand_ldst_mask (rtx target, tree arg0) +{ + int icode2 = BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct + : (int) CODE_FOR_altivec_lvsl_direct; + machine_mode tmode = insn_data[icode2].operand[0].mode; + machine_mode mode = insn_data[icode2].operand[1].mode; - if (bif_is_32bit (*bifaddr) && TARGET_32BIT) - { - if (fcode == RS6000_BIF_MFTB) - icode = CODE_FOR_rs6000_mftb_si; - else if (fcode == RS6000_BIF_BPERMD) - icode = CODE_FOR_bpermd_si; - else - gcc_unreachable (); - } + gcc_assert (TARGET_ALTIVEC); - if (bif_is_endian (*bifaddr) && BYTES_BIG_ENDIAN) - { - if (fcode == RS6000_BIF_LD_ELEMREV_V1TI) - icode = CODE_FOR_vsx_load_v1ti; - else if (fcode == RS6000_BIF_LD_ELEMREV_V2DF) - icode = CODE_FOR_vsx_load_v2df; - else if (fcode == RS6000_BIF_LD_ELEMREV_V2DI) - icode = CODE_FOR_vsx_load_v2di; - else if (fcode == RS6000_BIF_LD_ELEMREV_V4SF) - icode = CODE_FOR_vsx_load_v4sf; - else if (fcode == RS6000_BIF_LD_ELEMREV_V4SI) - icode = CODE_FOR_vsx_load_v4si; - else if (fcode == RS6000_BIF_LD_ELEMREV_V8HI) - icode = CODE_FOR_vsx_load_v8hi; - else if (fcode == RS6000_BIF_LD_ELEMREV_V16QI) - icode = CODE_FOR_vsx_load_v16qi; - else if (fcode == RS6000_BIF_ST_ELEMREV_V1TI) - icode = CODE_FOR_vsx_store_v1ti; - else if (fcode == RS6000_BIF_ST_ELEMREV_V2DF) - icode = CODE_FOR_vsx_store_v2df; - else if (fcode == RS6000_BIF_ST_ELEMREV_V2DI) - icode = CODE_FOR_vsx_store_v2di; - else if (fcode == RS6000_BIF_ST_ELEMREV_V4SF) - icode = CODE_FOR_vsx_store_v4sf; - else if (fcode == RS6000_BIF_ST_ELEMREV_V4SI) - icode = CODE_FOR_vsx_store_v4si; - else if (fcode == RS6000_BIF_ST_ELEMREV_V8HI) - icode = CODE_FOR_vsx_store_v8hi; - else if (fcode == RS6000_BIF_ST_ELEMREV_V16QI) - icode = CODE_FOR_vsx_store_v16qi; - else - gcc_unreachable (); - } + gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg0))); + rtx op = expand_expr (arg0, NULL_RTX, Pmode, EXPAND_NORMAL); + rtx addr = memory_address (mode, op); + /* We need to negate the address. */ + op = gen_reg_rtx (GET_MODE (addr)); + emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr))); + op = gen_rtx_MEM (mode, op); + if (target == 0 + || GET_MODE (target) != tmode + || !insn_data[icode2].operand[0].predicate (target, tmode)) + target = gen_reg_rtx (tmode); - /* TRUE iff the built-in function returns void. */ - bool void_func = TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node; - /* Position of first argument (0 for void-returning functions, else 1). */ - int k; - /* Modes for the return value, if any, and arguments. */ - const int MAX_BUILTIN_ARGS = 6; - machine_mode mode[MAX_BUILTIN_ARGS + 1]; + rtx pat = GEN_FCN (icode2) (target, op); + if (!pat) + return 0; + emit_insn (pat); - if (void_func) - k = 0; - else - { - k = 1; - mode[0] = insn_data[icode].operand[0].mode; - } + return target; +} - /* Tree expressions for each argument. */ - tree arg[MAX_BUILTIN_ARGS]; - /* RTL expressions for each argument. */ - rtx op[MAX_BUILTIN_ARGS]; +/* Expand the CPU builtin in FCODE and store the result in TARGET. */ +static rtx +new_cpu_expand_builtin (enum rs6000_gen_builtins fcode, + tree exp ATTRIBUTE_UNUSED, rtx target) +{ + /* __builtin_cpu_init () is a nop, so expand to nothing. */ + if (fcode == RS6000_BIF_CPU_INIT) + return const0_rtx; - int nargs = bifaddr->nargs; - gcc_assert (nargs <= MAX_BUILTIN_ARGS); + if (target == 0 || GET_MODE (target) != SImode) + target = gen_reg_rtx (SImode); + /* TODO: Factor the #ifdef'd code into a separate function. */ +#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB + tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0); + /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back + to a STRING_CST. */ + if (TREE_CODE (arg) == ARRAY_REF + && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST + && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST + && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0) + arg = TREE_OPERAND (arg, 0); - for (int i = 0; i < nargs; i++) + if (TREE_CODE (arg) != STRING_CST) { - arg[i] = CALL_EXPR_ARG (exp, i); - if (arg[i] == error_mark_node) - return const0_rtx; - STRIP_NOPS (arg[i]); - op[i] = expand_normal (arg[i]); - /* We have a couple of pesky patterns that don't specify the mode... */ - mode[i+k] = insn_data[icode].operand[i+k].mode; - if (!mode[i+k]) - mode[i+k] = Pmode; + error ("builtin %qs only accepts a string argument", + rs6000_builtin_info_x[(size_t) fcode].bifname); + return const0_rtx; } - /* Check for restricted constant arguments. */ - for (int i = 0; i < 2; i++) + if (fcode == RS6000_BIF_CPU_IS) { - switch (bifaddr->restr[i]) - { - case RES_BITS: - { - size_t mask = 1; - mask <<= bifaddr->restr_val1[i]; - mask--; - tree restr_arg = arg[bifaddr->restr_opnd[i] - 1]; - STRIP_NOPS (restr_arg); - if (!(TREE_CODE (restr_arg) == INTEGER_CST - && (TREE_INT_CST_LOW (restr_arg) & ~mask) == 0)) - { - error ("argument %d must be a %d-bit unsigned literal", - bifaddr->restr_opnd[i], bifaddr->restr_val1[i]); - return CONST0_RTX (mode[0]); - } - break; - } - case RES_RANGE: - { - tree restr_arg = arg[bifaddr->restr_opnd[i] - 1]; - STRIP_NOPS (restr_arg); - if (!(TREE_CODE (restr_arg) == INTEGER_CST - && IN_RANGE (tree_to_shwi (restr_arg), - bifaddr->restr_val1[i], - bifaddr->restr_val2[i]))) - { - error ("argument %d must be a literal between %d and %d," - " inclusive", - bifaddr->restr_opnd[i], bifaddr->restr_val1[i], - bifaddr->restr_val2[i]); - return CONST0_RTX (mode[0]); - } - break; - } - case RES_VAR_RANGE: + const char *cpu = TREE_STRING_POINTER (arg); + rtx cpuid = NULL_RTX; + for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++) + if (strcmp (cpu, cpu_is_info[i].cpu) == 0) { - tree restr_arg = arg[bifaddr->restr_opnd[i] - 1]; - STRIP_NOPS (restr_arg); - if (TREE_CODE (restr_arg) == INTEGER_CST - && !IN_RANGE (tree_to_shwi (restr_arg), - bifaddr->restr_val1[i], - bifaddr->restr_val2[i])) - { - error ("argument %d must be a variable or a literal " - "between %d and %d, inclusive", - bifaddr->restr_opnd[i], bifaddr->restr_val1[i], - bifaddr->restr_val2[i]); - return CONST0_RTX (mode[0]); - } + /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */ + cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM); break; } - case RES_VALUES: + if (cpuid == NULL_RTX) + { + /* Invalid CPU argument. */ + error ("cpu %qs is an invalid argument to builtin %qs", + cpu, rs6000_builtin_info_x[(size_t) fcode].bifname); + return const0_rtx; + } + + rtx platform = gen_reg_rtx (SImode); + rtx address = gen_rtx_PLUS (Pmode, + gen_rtx_REG (Pmode, TLS_REGNUM), + GEN_INT (TCB_PLATFORM_OFFSET)); + rtx tcbmem = gen_const_mem (SImode, address); + emit_move_insn (platform, tcbmem); + emit_insn (gen_eqsi3 (target, platform, cpuid)); + } + else if (fcode == RS6000_BIF_CPU_SUPPORTS) + { + const char *hwcap = TREE_STRING_POINTER (arg); + rtx mask = NULL_RTX; + int hwcap_offset; + for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++) + if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0) { - tree restr_arg = arg[bifaddr->restr_opnd[i] - 1]; - STRIP_NOPS (restr_arg); - if (!(TREE_CODE (restr_arg) == INTEGER_CST - && (tree_to_shwi (restr_arg) == bifaddr->restr_val1[i] - || tree_to_shwi (restr_arg) == bifaddr->restr_val2[i]))) - { - error ("argument %d must be either a literal %d or a " - "literal %d", - bifaddr->restr_opnd[i], bifaddr->restr_val1[i], - bifaddr->restr_val2[i]); - return CONST0_RTX (mode[0]); - } + mask = GEN_INT (cpu_supports_info[i].mask); + hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id); break; } - default: - case RES_NONE: - break; + if (mask == NULL_RTX) + { + /* Invalid HWCAP argument. */ + error ("%s %qs is an invalid argument to builtin %qs", + "hwcap", hwcap, + rs6000_builtin_info_x[(size_t) fcode].bifname); + return const0_rtx; } + + rtx tcb_hwcap = gen_reg_rtx (SImode); + rtx address = gen_rtx_PLUS (Pmode, + gen_rtx_REG (Pmode, TLS_REGNUM), + GEN_INT (hwcap_offset)); + rtx tcbmem = gen_const_mem (SImode, address); + emit_move_insn (tcb_hwcap, tcbmem); + rtx scratch1 = gen_reg_rtx (SImode); + emit_insn (gen_rtx_SET (scratch1, + gen_rtx_AND (SImode, tcb_hwcap, mask))); + rtx scratch2 = gen_reg_rtx (SImode); + emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx)); + emit_insn (gen_rtx_SET (target, + gen_rtx_XOR (SImode, scratch2, const1_rtx))); } + else + gcc_unreachable (); - if (bif_is_ldstmask (*bifaddr)) - return rs6000_expand_ldst_mask (target, arg[0]); + /* Record that we have expanded a CPU builtin, so that we can later + emit a reference to the special symbol exported by LIBC to ensure we + do not link against an old LIBC that doesn't support this feature. */ + cpu_builtin_p = true; - if (bif_is_stvec (*bifaddr)) - { - if (bif_is_reve (*bifaddr)) - icode = elemrev_icode (fcode); - return stv_expand_builtin (icode, op, mode[0], mode[1]); - } +#else + warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware " + "capability bits", rs6000_builtin_info_x[(size_t) fcode].bifname); - if (bif_is_ldvec (*bifaddr)) + /* For old LIBCs, always return FALSE. */ + emit_move_insn (target, GEN_INT (0)); +#endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */ + + return target; +} + +/* For the element-reversing load/store built-ins, produce the correct + insn_code depending on the target endianness. */ +static insn_code +elemrev_icode (rs6000_gen_builtins fcode) +{ + switch (fcode) { - if (bif_is_reve (*bifaddr)) - icode = elemrev_icode (fcode); - return ldv_expand_builtin (target, icode, op, mode[0]); - } + case RS6000_BIF_ST_ELEMREV_V1TI: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti + : CODE_FOR_vsx_st_elemrev_v1ti; - if (bif_is_lxvrse (*bifaddr)) - return lxvrse_expand_builtin (target, icode, op, mode[0], mode[1]); + case RS6000_BIF_ST_ELEMREV_V2DF: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df + : CODE_FOR_vsx_st_elemrev_v2df; - if (bif_is_lxvrze (*bifaddr)) - return lxvrze_expand_builtin (target, icode, op, mode[0], mode[1]); + case RS6000_BIF_ST_ELEMREV_V2DI: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di + : CODE_FOR_vsx_st_elemrev_v2di; - if (bif_is_mma (*bifaddr)) - return new_mma_expand_builtin (exp, target, icode, fcode); + case RS6000_BIF_ST_ELEMREV_V4SF: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf + : CODE_FOR_vsx_st_elemrev_v4sf; - if (fcode == RS6000_BIF_PACK_IF - && TARGET_LONG_DOUBLE_128 - && !TARGET_IEEEQUAD) - { - icode = CODE_FOR_packtf; - fcode = RS6000_BIF_PACK_TF; - uns_fcode = (size_t) fcode; - } - else if (fcode == RS6000_BIF_UNPACK_IF - && TARGET_LONG_DOUBLE_128 - && !TARGET_IEEEQUAD) - { - icode = CODE_FOR_unpacktf; - fcode = RS6000_BIF_UNPACK_TF; - uns_fcode = (size_t) fcode; - } + case RS6000_BIF_ST_ELEMREV_V4SI: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si + : CODE_FOR_vsx_st_elemrev_v4si; - if (TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node) - target = NULL_RTX; - else if (target == 0 - || GET_MODE (target) != mode[0] - || !insn_data[icode].operand[0].predicate (target, mode[0])) - target = gen_reg_rtx (mode[0]); + case RS6000_BIF_ST_ELEMREV_V8HI: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi + : CODE_FOR_vsx_st_elemrev_v8hi; - for (int i = 0; i < nargs; i++) - if (!insn_data[icode].operand[i+k].predicate (op[i], mode[i+k])) - op[i] = copy_to_mode_reg (mode[i+k], op[i]); + case RS6000_BIF_ST_ELEMREV_V16QI: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi + : CODE_FOR_vsx_st_elemrev_v16qi; - rtx pat; + case RS6000_BIF_LD_ELEMREV_V2DF: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df + : CODE_FOR_vsx_ld_elemrev_v2df; - switch (nargs) - { - case 0: - pat = (void_func - ? GEN_FCN (icode) () - : GEN_FCN (icode) (target)); - break; - case 1: - pat = (void_func - ? GEN_FCN (icode) (op[0]) - : GEN_FCN (icode) (target, op[0])); - break; - case 2: - pat = (void_func - ? GEN_FCN (icode) (op[0], op[1]) - : GEN_FCN (icode) (target, op[0], op[1])); - break; - case 3: - pat = (void_func - ? GEN_FCN (icode) (op[0], op[1], op[2]) - : GEN_FCN (icode) (target, op[0], op[1], op[2])); - break; - case 4: - pat = (void_func - ? GEN_FCN (icode) (op[0], op[1], op[2], op[3]) - : GEN_FCN (icode) (target, op[0], op[1], op[2], op[3])); - break; - case 5: - pat = (void_func - ? GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]) - : GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4])); - break; - case 6: - pat = (void_func - ? GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]) - : GEN_FCN (icode) (target, op[0], op[1], - op[2], op[3], op[4], op[5])); - break; + case RS6000_BIF_LD_ELEMREV_V1TI: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti + : CODE_FOR_vsx_ld_elemrev_v1ti; + + case RS6000_BIF_LD_ELEMREV_V2DI: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di + : CODE_FOR_vsx_ld_elemrev_v2di; + + case RS6000_BIF_LD_ELEMREV_V4SF: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf + : CODE_FOR_vsx_ld_elemrev_v4sf; + + case RS6000_BIF_LD_ELEMREV_V4SI: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si + : CODE_FOR_vsx_ld_elemrev_v4si; + + case RS6000_BIF_LD_ELEMREV_V8HI: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi + : CODE_FOR_vsx_ld_elemrev_v8hi; + + case RS6000_BIF_LD_ELEMREV_V16QI: + return BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi + : CODE_FOR_vsx_ld_elemrev_v16qi; default: - gcc_assert (MAX_BUILTIN_ARGS == 6); - gcc_unreachable (); + ; } - if (!pat) - return 0; - - emit_insn (pat); - return target; + gcc_unreachable (); } -/* Create a builtin vector type with a name. Taking care not to give - the canonical type a name. */ - -static tree -rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts) +/* Expand an AltiVec vector load builtin, and return the expanded rtx. */ +static rtx +ldv_expand_builtin (rtx target, insn_code icode, rtx *op, machine_mode tmode) { - tree result = build_vector_type (elt_type, num_elts); + if (target == 0 + || GET_MODE (target) != tmode + || !insn_data[icode].operand[0].predicate (target, tmode)) + target = gen_reg_rtx (tmode); - /* Copy so we don't give the canonical type a name. */ - result = build_variant_type_copy (result); + op[1] = copy_to_mode_reg (Pmode, op[1]); - add_builtin_type (name, result); + /* These CELL built-ins use BLKmode instead of tmode for historical + (i.e., unknown) reasons. TODO: Is this necessary? */ + bool blk = (icode == CODE_FOR_altivec_lvlx + || icode == CODE_FOR_altivec_lvlxl + || icode == CODE_FOR_altivec_lvrx + || icode == CODE_FOR_altivec_lvrxl); - return result; -} + /* For LVX, express the RTL accurately by ANDing the address with -16. + LVXL and LVE*X expand to use UNSPECs to hide their special behavior, + so the raw address is fine. */ + /* TODO: That statement seems wrong, as the UNSPECs don't surround the + memory expression, so a latent bug may lie here. The &-16 is likely + needed for all VMX-style loads. */ + if (icode == CODE_FOR_altivec_lvx_v1ti + || icode == CODE_FOR_altivec_lvx_v2df + || icode == CODE_FOR_altivec_lvx_v2di + || icode == CODE_FOR_altivec_lvx_v4sf + || icode == CODE_FOR_altivec_lvx_v4si + || icode == CODE_FOR_altivec_lvx_v8hi + || icode == CODE_FOR_altivec_lvx_v16qi) + { + rtx rawaddr; + if (op[0] == const0_rtx) + rawaddr = op[1]; + else + { + op[0] = copy_to_mode_reg (Pmode, op[0]); + rawaddr = gen_rtx_PLUS (Pmode, op[1], op[0]); + } + rtx addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16)); + addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr); -void -rs6000_init_builtins (void) -{ - tree tdecl; - tree ftype; - tree t; - machine_mode mode; - const char *str; + emit_insn (gen_rtx_SET (target, addr)); + } + else + { + rtx addr; + if (op[0] == const0_rtx) + addr = gen_rtx_MEM (blk ? BLKmode : tmode, op[1]); + else + { + op[0] = copy_to_mode_reg (Pmode, op[0]); + addr = gen_rtx_MEM (blk ? BLKmode : tmode, + gen_rtx_PLUS (Pmode, op[1], op[0])); + } + + rtx pat = GEN_FCN (icode) (target, addr); + if (!pat) + return 0; + emit_insn (pat); + } - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_init_builtins%s%s\n", - (TARGET_ALTIVEC) ? ", altivec" : "", - (TARGET_VSX) ? ", vsx" : ""); + return target; +} + +/* Expand a builtin function that loads a scalar into a vector register + with sign extension, and return the expanded rtx. */ +static rtx +lxvrse_expand_builtin (rtx target, insn_code icode, rtx *op, + machine_mode tmode, machine_mode smode) +{ + rtx pat, addr; + op[1] = copy_to_mode_reg (Pmode, op[1]); - if (new_builtins_are_live) - V2DI_type_node = rs6000_vector_type ("__vector long long", - long_long_integer_type_node, 2); + if (op[0] == const0_rtx) + addr = gen_rtx_MEM (tmode, op[1]); else { - str = TARGET_POWERPC64 ? "__vector long" : "__vector long long"; - V2DI_type_node = rs6000_vector_type (str, - long_long_integer_type_node, - 2); + op[0] = copy_to_mode_reg (Pmode, op[0]); + addr = gen_rtx_MEM (smode, + gen_rtx_PLUS (Pmode, op[1], op[0])); } - ptr_V2DI_type_node - = build_pointer_type (build_qualified_type (V2DI_type_node, - TYPE_QUAL_CONST)); - - V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2); - ptr_V2DF_type_node - = build_pointer_type (build_qualified_type (V2DF_type_node, - TYPE_QUAL_CONST)); - - V4SI_type_node = rs6000_vector_type ("__vector signed int", - intSI_type_node, 4); - ptr_V4SI_type_node - = build_pointer_type (build_qualified_type (V4SI_type_node, - TYPE_QUAL_CONST)); - V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4); - ptr_V4SF_type_node - = build_pointer_type (build_qualified_type (V4SF_type_node, - TYPE_QUAL_CONST)); + rtx discratch = gen_reg_rtx (V2DImode); + rtx tiscratch = gen_reg_rtx (TImode); - V8HI_type_node = rs6000_vector_type ("__vector signed short", - intHI_type_node, 8); - ptr_V8HI_type_node - = build_pointer_type (build_qualified_type (V8HI_type_node, - TYPE_QUAL_CONST)); + /* Emit the lxvr*x insn. */ + pat = GEN_FCN (icode) (tiscratch, addr); + if (!pat) + return 0; + emit_insn (pat); - V16QI_type_node = rs6000_vector_type ("__vector signed char", - intQI_type_node, 16); - ptr_V16QI_type_node - = build_pointer_type (build_qualified_type (V16QI_type_node, - TYPE_QUAL_CONST)); + /* Emit a sign extension from V16QI,V8HI,V4SI to V2DI. */ + rtx temp1; + if (icode == CODE_FOR_vsx_lxvrbx) + { + temp1 = simplify_gen_subreg (V16QImode, tiscratch, TImode, 0); + emit_insn (gen_vsx_sign_extend_qi_v2di (discratch, temp1)); + } + else if (icode == CODE_FOR_vsx_lxvrhx) + { + temp1 = simplify_gen_subreg (V8HImode, tiscratch, TImode, 0); + emit_insn (gen_vsx_sign_extend_hi_v2di (discratch, temp1)); + } + else if (icode == CODE_FOR_vsx_lxvrwx) + { + temp1 = simplify_gen_subreg (V4SImode, tiscratch, TImode, 0); + emit_insn (gen_vsx_sign_extend_si_v2di (discratch, temp1)); + } + else if (icode == CODE_FOR_vsx_lxvrdx) + discratch = simplify_gen_subreg (V2DImode, tiscratch, TImode, 0); + else + gcc_unreachable (); - unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char", - unsigned_intQI_type_node, 16); - ptr_unsigned_V16QI_type_node - = build_pointer_type (build_qualified_type (unsigned_V16QI_type_node, - TYPE_QUAL_CONST)); + /* Emit the sign extension from V2DI (double) to TI (quad). */ + rtx temp2 = simplify_gen_subreg (TImode, discratch, V2DImode, 0); + emit_insn (gen_extendditi2_vector (target, temp2)); - unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short", - unsigned_intHI_type_node, 8); - ptr_unsigned_V8HI_type_node - = build_pointer_type (build_qualified_type (unsigned_V8HI_type_node, - TYPE_QUAL_CONST)); + return target; +} - unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int", - unsigned_intSI_type_node, 4); - ptr_unsigned_V4SI_type_node - = build_pointer_type (build_qualified_type (unsigned_V4SI_type_node, - TYPE_QUAL_CONST)); +/* Expand a builtin function that loads a scalar into a vector register + with zero extension, and return the expanded rtx. */ +static rtx +lxvrze_expand_builtin (rtx target, insn_code icode, rtx *op, + machine_mode tmode, machine_mode smode) +{ + rtx pat, addr; + op[1] = copy_to_mode_reg (Pmode, op[1]); - if (new_builtins_are_live) - unsigned_V2DI_type_node - = rs6000_vector_type ("__vector unsigned long long", - long_long_unsigned_type_node, 2); + if (op[0] == const0_rtx) + addr = gen_rtx_MEM (tmode, op[1]); else { - str = TARGET_POWERPC64 - ? "__vector unsigned long" - : "__vector unsigned long long"; - unsigned_V2DI_type_node - = rs6000_vector_type (str, long_long_unsigned_type_node, 2); + op[0] = copy_to_mode_reg (Pmode, op[0]); + addr = gen_rtx_MEM (smode, + gen_rtx_PLUS (Pmode, op[1], op[0])); } - ptr_unsigned_V2DI_type_node - = build_pointer_type (build_qualified_type (unsigned_V2DI_type_node, - TYPE_QUAL_CONST)); - - opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4); + pat = GEN_FCN (icode) (target, addr); + if (!pat) + return 0; + emit_insn (pat); + return target; +} - const_str_type_node - = build_pointer_type (build_qualified_type (char_type_node, - TYPE_QUAL_CONST)); +/* Expand an AltiVec vector store builtin, and return the expanded rtx. */ +static rtx +stv_expand_builtin (insn_code icode, rtx *op, + machine_mode tmode, machine_mode smode) +{ + op[2] = copy_to_mode_reg (Pmode, op[2]); - /* We use V1TI mode as a special container to hold __int128_t items that - must live in VSX registers. */ - if (intTI_type_node) + /* For STVX, express the RTL accurately by ANDing the address with -16. + STVXL and STVE*X expand to use UNSPECs to hide their special behavior, + so the raw address is fine. */ + /* TODO: That statement seems wrong, as the UNSPECs don't surround the + memory expression, so a latent bug may lie here. The &-16 is likely + needed for all VMX-style stores. */ + if (icode == CODE_FOR_altivec_stvx_v2df + || icode == CODE_FOR_altivec_stvx_v2di + || icode == CODE_FOR_altivec_stvx_v4sf + || icode == CODE_FOR_altivec_stvx_v4si + || icode == CODE_FOR_altivec_stvx_v8hi + || icode == CODE_FOR_altivec_stvx_v16qi) { - V1TI_type_node = rs6000_vector_type ("__vector __int128", - intTI_type_node, 1); - ptr_V1TI_type_node - = build_pointer_type (build_qualified_type (V1TI_type_node, - TYPE_QUAL_CONST)); - unsigned_V1TI_type_node - = rs6000_vector_type ("__vector unsigned __int128", - unsigned_intTI_type_node, 1); - ptr_unsigned_V1TI_type_node - = build_pointer_type (build_qualified_type (unsigned_V1TI_type_node, - TYPE_QUAL_CONST)); - } - - /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' - types, especially in C++ land. Similarly, 'vector pixel' is distinct from - 'vector unsigned short'. */ + rtx rawaddr; + if (op[1] == const0_rtx) + rawaddr = op[2]; + else + { + op[1] = copy_to_mode_reg (Pmode, op[1]); + rawaddr = gen_rtx_PLUS (Pmode, op[2], op[1]); + } - bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); - bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); - bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); - bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node); - pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); + rtx addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16)); + addr = gen_rtx_MEM (tmode, addr); + op[0] = copy_to_mode_reg (tmode, op[0]); + emit_insn (gen_rtx_SET (addr, op[0])); + } + else if (icode == CODE_FOR_vsx_stxvrbx + || icode == CODE_FOR_vsx_stxvrhx + || icode == CODE_FOR_vsx_stxvrwx + || icode == CODE_FOR_vsx_stxvrdx) + { + rtx truncrtx = gen_rtx_TRUNCATE (tmode, op[0]); + op[0] = copy_to_mode_reg (E_TImode, truncrtx); - long_integer_type_internal_node = long_integer_type_node; - long_unsigned_type_internal_node = long_unsigned_type_node; - long_long_integer_type_internal_node = long_long_integer_type_node; - long_long_unsigned_type_internal_node = long_long_unsigned_type_node; - intQI_type_internal_node = intQI_type_node; - uintQI_type_internal_node = unsigned_intQI_type_node; - intHI_type_internal_node = intHI_type_node; - uintHI_type_internal_node = unsigned_intHI_type_node; - intSI_type_internal_node = intSI_type_node; - uintSI_type_internal_node = unsigned_intSI_type_node; - intDI_type_internal_node = intDI_type_node; - uintDI_type_internal_node = unsigned_intDI_type_node; - intTI_type_internal_node = intTI_type_node; - uintTI_type_internal_node = unsigned_intTI_type_node; - float_type_internal_node = float_type_node; - double_type_internal_node = double_type_node; - long_double_type_internal_node = long_double_type_node; - dfloat64_type_internal_node = dfloat64_type_node; - dfloat128_type_internal_node = dfloat128_type_node; - void_type_internal_node = void_type_node; + rtx addr; + if (op[1] == const0_rtx) + addr = gen_rtx_MEM (Pmode, op[2]); + else + { + op[1] = copy_to_mode_reg (Pmode, op[1]); + addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1])); + } + rtx pat = GEN_FCN (icode) (addr, op[0]); + if (pat) + emit_insn (pat); + } + else + { + if (!insn_data[icode].operand[1].predicate (op[0], smode)) + op[0] = copy_to_mode_reg (smode, op[0]); - ptr_intQI_type_node - = build_pointer_type (build_qualified_type (intQI_type_internal_node, - TYPE_QUAL_CONST)); - ptr_uintQI_type_node - = build_pointer_type (build_qualified_type (uintQI_type_internal_node, - TYPE_QUAL_CONST)); - ptr_intHI_type_node - = build_pointer_type (build_qualified_type (intHI_type_internal_node, - TYPE_QUAL_CONST)); - ptr_uintHI_type_node - = build_pointer_type (build_qualified_type (uintHI_type_internal_node, - TYPE_QUAL_CONST)); - ptr_intSI_type_node - = build_pointer_type (build_qualified_type (intSI_type_internal_node, - TYPE_QUAL_CONST)); - ptr_uintSI_type_node - = build_pointer_type (build_qualified_type (uintSI_type_internal_node, - TYPE_QUAL_CONST)); - ptr_intDI_type_node - = build_pointer_type (build_qualified_type (intDI_type_internal_node, - TYPE_QUAL_CONST)); - ptr_uintDI_type_node - = build_pointer_type (build_qualified_type (uintDI_type_internal_node, - TYPE_QUAL_CONST)); - ptr_intTI_type_node - = build_pointer_type (build_qualified_type (intTI_type_internal_node, - TYPE_QUAL_CONST)); - ptr_uintTI_type_node - = build_pointer_type (build_qualified_type (uintTI_type_internal_node, - TYPE_QUAL_CONST)); + rtx addr; + if (op[1] == const0_rtx) + addr = gen_rtx_MEM (tmode, op[2]); + else + { + op[1] = copy_to_mode_reg (Pmode, op[1]); + addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op[2], op[1])); + } - t = build_qualified_type (long_integer_type_internal_node, TYPE_QUAL_CONST); - ptr_long_integer_type_node = build_pointer_type (t); + rtx pat = GEN_FCN (icode) (addr, op[0]); + if (pat) + emit_insn (pat); + } - t = build_qualified_type (long_unsigned_type_internal_node, TYPE_QUAL_CONST); - ptr_long_unsigned_type_node = build_pointer_type (t); + return NULL_RTX; +} - ptr_float_type_node - = build_pointer_type (build_qualified_type (float_type_internal_node, - TYPE_QUAL_CONST)); - ptr_double_type_node - = build_pointer_type (build_qualified_type (double_type_internal_node, - TYPE_QUAL_CONST)); - ptr_long_double_type_node - = build_pointer_type (build_qualified_type (long_double_type_internal_node, - TYPE_QUAL_CONST)); - if (dfloat64_type_node) - { - t = build_qualified_type (dfloat64_type_internal_node, TYPE_QUAL_CONST); - ptr_dfloat64_type_node = build_pointer_type (t); - } - else - ptr_dfloat64_type_node = NULL; +/* Expand the MMA built-in in EXP, and return it. */ +static rtx +new_mma_expand_builtin (tree exp, rtx target, insn_code icode, + rs6000_gen_builtins fcode) +{ + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); + bool void_func = TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node; + machine_mode tmode = VOIDmode; + rtx op[MAX_MMA_OPERANDS]; + unsigned nopnds = 0; - if (dfloat128_type_node) + if (!void_func) { - t = build_qualified_type (dfloat128_type_internal_node, TYPE_QUAL_CONST); - ptr_dfloat128_type_node = build_pointer_type (t); + tmode = insn_data[icode].operand[0].mode; + if (!(target + && GET_MODE (target) == tmode + && insn_data[icode].operand[0].predicate (target, tmode))) + target = gen_reg_rtx (tmode); + op[nopnds++] = target; } else - ptr_dfloat128_type_node = NULL; + target = const0_rtx; - t = build_qualified_type (long_long_integer_type_internal_node, - TYPE_QUAL_CONST); - ptr_long_long_integer_type_node = build_pointer_type (t); + call_expr_arg_iterator iter; + tree arg; + FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) + { + if (arg == error_mark_node) + return const0_rtx; - t = build_qualified_type (long_long_unsigned_type_internal_node, - TYPE_QUAL_CONST); - ptr_long_long_unsigned_type_node = build_pointer_type (t); + rtx opnd; + const struct insn_operand_data *insn_op; + insn_op = &insn_data[icode].operand[nopnds]; + if (TREE_CODE (arg) == ADDR_EXPR + && MEM_P (DECL_RTL (TREE_OPERAND (arg, 0)))) + opnd = DECL_RTL (TREE_OPERAND (arg, 0)); + else + opnd = expand_normal (arg); - /* 128-bit floating point support. KFmode is IEEE 128-bit floating point. - IFmode is the IBM extended 128-bit format that is a pair of doubles. - TFmode will be either IEEE 128-bit floating point or the IBM double-double - format that uses a pair of doubles, depending on the switches and - defaults. + if (!insn_op->predicate (opnd, insn_op->mode)) + { + /* TODO: This use of constraints needs explanation. */ + if (!strcmp (insn_op->constraint, "n")) + { + if (!CONST_INT_P (opnd)) + error ("argument %d must be an unsigned literal", nopnds); + else + error ("argument %d is an unsigned literal that is " + "out of range", nopnds); + return const0_rtx; + } + opnd = copy_to_mode_reg (insn_op->mode, opnd); + } - If we don't support for either 128-bit IBM double double or IEEE 128-bit - floating point, we need make sure the type is non-zero or else self-test - fails during bootstrap. + /* Some MMA instructions have INOUT accumulator operands, so force + their target register to be the same as their input register. */ + if (!void_func + && nopnds == 1 + && !strcmp (insn_op->constraint, "0") + && insn_op->mode == tmode + && REG_P (opnd) + && insn_data[icode].operand[0].predicate (opnd, tmode)) + target = op[0] = opnd; - Always create __ibm128 as a separate type, even if the current long double - format is IBM extended double. + op[nopnds++] = opnd; + } - For IEEE 128-bit floating point, always create the type __ieee128. If the - user used -mfloat128, rs6000-c.c will create a define from __float128 to - __ieee128. */ - if (TARGET_FLOAT128_TYPE) + rtx pat; + switch (nopnds) { - if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128) - ibm128_float_type_node = long_double_type_node; - else + case 1: + pat = GEN_FCN (icode) (op[0]); + break; + case 2: + pat = GEN_FCN (icode) (op[0], op[1]); + break; + case 3: + /* The ASSEMBLE builtin source operands are reversed in little-endian + mode, so reorder them. */ + if (fcode == RS6000_BIF_ASSEMBLE_PAIR_V_INTERNAL && !WORDS_BIG_ENDIAN) + std::swap (op[1], op[2]); + pat = GEN_FCN (icode) (op[0], op[1], op[2]); + break; + case 4: + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); + break; + case 5: + /* The ASSEMBLE builtin source operands are reversed in little-endian + mode, so reorder them. */ + if (fcode == RS6000_BIF_ASSEMBLE_ACC_INTERNAL && !WORDS_BIG_ENDIAN) { - ibm128_float_type_node = make_node (REAL_TYPE); - TYPE_PRECISION (ibm128_float_type_node) = 128; - SET_TYPE_MODE (ibm128_float_type_node, IFmode); - layout_type (ibm128_float_type_node); + std::swap (op[1], op[4]); + std::swap (op[2], op[3]); } - t = build_qualified_type (ibm128_float_type_node, TYPE_QUAL_CONST); - ptr_ibm128_float_type_node = build_pointer_type (t); - lang_hooks.types.register_builtin_type (ibm128_float_type_node, - "__ibm128"); - - if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128) - ieee128_float_type_node = long_double_type_node; - else - ieee128_float_type_node = float128_type_node; - t = build_qualified_type (ieee128_float_type_node, TYPE_QUAL_CONST); - ptr_ieee128_float_type_node = build_pointer_type (t); - lang_hooks.types.register_builtin_type (ieee128_float_type_node, - "__ieee128"); + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); + break; + case 6: + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]); + break; + case 7: + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5], op[6]); + break; + default: + gcc_unreachable (); } - else - ieee128_float_type_node = ibm128_float_type_node = long_double_type_node; + if (!pat) + return NULL_RTX; - /* Vector pair and vector quad support. */ - vector_pair_type_node = make_node (OPAQUE_TYPE); - SET_TYPE_MODE (vector_pair_type_node, OOmode); - TYPE_SIZE (vector_pair_type_node) = bitsize_int (GET_MODE_BITSIZE (OOmode)); - TYPE_PRECISION (vector_pair_type_node) = GET_MODE_BITSIZE (OOmode); - TYPE_SIZE_UNIT (vector_pair_type_node) = size_int (GET_MODE_SIZE (OOmode)); - SET_TYPE_ALIGN (vector_pair_type_node, 256); - TYPE_USER_ALIGN (vector_pair_type_node) = 0; - lang_hooks.types.register_builtin_type (vector_pair_type_node, - "__vector_pair"); - t = build_qualified_type (vector_pair_type_node, TYPE_QUAL_CONST); - ptr_vector_pair_type_node = build_pointer_type (t); + emit_insn (pat); + return target; +} - vector_quad_type_node = make_node (OPAQUE_TYPE); - SET_TYPE_MODE (vector_quad_type_node, XOmode); - TYPE_SIZE (vector_quad_type_node) = bitsize_int (GET_MODE_BITSIZE (XOmode)); - TYPE_PRECISION (vector_quad_type_node) = GET_MODE_BITSIZE (XOmode); - TYPE_SIZE_UNIT (vector_quad_type_node) = size_int (GET_MODE_SIZE (XOmode)); - SET_TYPE_ALIGN (vector_quad_type_node, 512); - TYPE_USER_ALIGN (vector_quad_type_node) = 0; - lang_hooks.types.register_builtin_type (vector_quad_type_node, - "__vector_quad"); - t = build_qualified_type (vector_quad_type_node, TYPE_QUAL_CONST); - ptr_vector_quad_type_node = build_pointer_type (t); +/* Return the appropriate SPR number associated with the given builtin. */ +static inline HOST_WIDE_INT +new_htm_spr_num (enum rs6000_gen_builtins code) +{ + if (code == RS6000_BIF_GET_TFHAR + || code == RS6000_BIF_SET_TFHAR) + return TFHAR_SPR; + else if (code == RS6000_BIF_GET_TFIAR + || code == RS6000_BIF_SET_TFIAR) + return TFIAR_SPR; + else if (code == RS6000_BIF_GET_TEXASR + || code == RS6000_BIF_SET_TEXASR) + return TEXASR_SPR; + gcc_assert (code == RS6000_BIF_GET_TEXASRU + || code == RS6000_BIF_SET_TEXASRU); + return TEXASRU_SPR; +} - /* Initialize the modes for builtin_function_type, mapping a machine mode to - tree type node. */ - builtin_mode_to_type[QImode][0] = integer_type_node; - builtin_mode_to_type[QImode][1] = unsigned_intSI_type_node; - builtin_mode_to_type[HImode][0] = integer_type_node; - builtin_mode_to_type[HImode][1] = unsigned_intSI_type_node; - builtin_mode_to_type[SImode][0] = intSI_type_node; - builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node; - builtin_mode_to_type[DImode][0] = intDI_type_node; - builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node; - builtin_mode_to_type[TImode][0] = intTI_type_node; - builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node; - builtin_mode_to_type[SFmode][0] = float_type_node; - builtin_mode_to_type[DFmode][0] = double_type_node; - builtin_mode_to_type[IFmode][0] = ibm128_float_type_node; - builtin_mode_to_type[KFmode][0] = ieee128_float_type_node; - builtin_mode_to_type[TFmode][0] = long_double_type_node; - builtin_mode_to_type[DDmode][0] = dfloat64_type_node; - builtin_mode_to_type[TDmode][0] = dfloat128_type_node; - builtin_mode_to_type[V1TImode][0] = V1TI_type_node; - builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node; - builtin_mode_to_type[V2DImode][0] = V2DI_type_node; - builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node; - builtin_mode_to_type[V2DFmode][0] = V2DF_type_node; - builtin_mode_to_type[V4SImode][0] = V4SI_type_node; - builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node; - builtin_mode_to_type[V4SFmode][0] = V4SF_type_node; - builtin_mode_to_type[V8HImode][0] = V8HI_type_node; - builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node; - builtin_mode_to_type[V16QImode][0] = V16QI_type_node; - builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node; - builtin_mode_to_type[OOmode][1] = vector_pair_type_node; - builtin_mode_to_type[XOmode][1] = vector_quad_type_node; +/* Expand the HTM builtin in EXP and store the result in TARGET. + Return the expanded rtx. */ +static rtx +new_htm_expand_builtin (bifdata *bifaddr, rs6000_gen_builtins fcode, + tree exp, rtx target) +{ + if (!TARGET_POWERPC64 + && (fcode == RS6000_BIF_TABORTDC + || fcode == RS6000_BIF_TABORTDCI)) + { + error ("builtin %qs is only valid in 64-bit mode", bifaddr->bifname); + return const0_rtx; + } - tdecl = add_builtin_type ("__bool char", bool_char_type_node); - TYPE_NAME (bool_char_type_node) = tdecl; + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); + bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; + bool uses_spr = bif_is_htmspr (*bifaddr); + insn_code icode = bifaddr->icode; - tdecl = add_builtin_type ("__bool short", bool_short_type_node); - TYPE_NAME (bool_short_type_node) = tdecl; + if (uses_spr) + icode = rs6000_htm_spr_icode (nonvoid); - tdecl = add_builtin_type ("__bool int", bool_int_type_node); - TYPE_NAME (bool_int_type_node) = tdecl; + rtx op[MAX_HTM_OPERANDS]; + int nopnds = 0; + const insn_operand_data *insn_op = &insn_data[icode].operand[0]; - tdecl = add_builtin_type ("__pixel", pixel_type_node); - TYPE_NAME (pixel_type_node) = tdecl; + if (nonvoid) + { + machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode; + if (!target + || GET_MODE (target) != tmode + || (uses_spr && !insn_op->predicate (target, tmode))) + target = gen_reg_rtx (tmode); + if (uses_spr) + op[nopnds++] = target; + } - bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char", - bool_char_type_node, 16); - ptr_bool_V16QI_type_node - = build_pointer_type (build_qualified_type (bool_V16QI_type_node, - TYPE_QUAL_CONST)); + tree arg; + call_expr_arg_iterator iter; - bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short", - bool_short_type_node, 8); - ptr_bool_V8HI_type_node - = build_pointer_type (build_qualified_type (bool_V8HI_type_node, - TYPE_QUAL_CONST)); + FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) + { + if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS) + return const0_rtx; - bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int", - bool_int_type_node, 4); - ptr_bool_V4SI_type_node - = build_pointer_type (build_qualified_type (bool_V4SI_type_node, - TYPE_QUAL_CONST)); + insn_op = &insn_data[icode].operand[nopnds]; + op[nopnds] = expand_normal (arg); - bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 - ? "__vector __bool long" - : "__vector __bool long long", - bool_long_long_type_node, 2); - ptr_bool_V2DI_type_node - = build_pointer_type (build_qualified_type (bool_V2DI_type_node, - TYPE_QUAL_CONST)); + if (!insn_op->predicate (op[nopnds], insn_op->mode)) + { + /* TODO: This use of constraints could use explanation. + This happens a couple of places, perhaps make that a + function to document what's happening. */ + if (!strcmp (insn_op->constraint, "n")) + { + int arg_num = nonvoid ? nopnds : nopnds + 1; + if (!CONST_INT_P (op[nopnds])) + error ("argument %d must be an unsigned literal", arg_num); + else + error ("argument %d is an unsigned literal that is " + "out of range", arg_num); + return const0_rtx; + } + op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]); + } - bool_V1TI_type_node = rs6000_vector_type ("__vector __bool __int128", - intTI_type_node, 1); - ptr_bool_V1TI_type_node - = build_pointer_type (build_qualified_type (bool_V1TI_type_node, - TYPE_QUAL_CONST)); + nopnds++; + } - pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel", - pixel_type_node, 8); - ptr_pixel_V8HI_type_node - = build_pointer_type (build_qualified_type (pixel_V8HI_type_node, - TYPE_QUAL_CONST)); - pcvoid_type_node - = build_pointer_type (build_qualified_type (void_type_node, - TYPE_QUAL_CONST)); + /* Handle the builtins for extended mnemonics. These accept + no arguments, but map to builtins that take arguments. */ + switch (fcode) + { + case RS6000_BIF_TENDALL: /* Alias for: tend. 1 */ + case RS6000_BIF_TRESUME: /* Alias for: tsr. 1 */ + op[nopnds++] = GEN_INT (1); + break; + case RS6000_BIF_TSUSPEND: /* Alias for: tsr. 0 */ + op[nopnds++] = GEN_INT (0); + break; + default: + break; + } - /* Execute the autogenerated initialization code for builtins. */ - rs6000_init_generated_builtins (); + /* If this builtin accesses SPRs, then pass in the appropriate + SPR number and SPR regno as the last two operands. */ + rtx cr = NULL_RTX; + if (uses_spr) + { + machine_mode mode = TARGET_POWERPC64 ? DImode : SImode; + op[nopnds++] = gen_rtx_CONST_INT (mode, new_htm_spr_num (fcode)); + } + /* If this builtin accesses a CR field, then pass in a scratch + CR field as the last operand. */ + else if (bif_is_htmcr (*bifaddr)) + { + cr = gen_reg_rtx (CCmode); + op[nopnds++] = cr; + } + + rtx pat; + switch (nopnds) + { + case 1: + pat = GEN_FCN (icode) (op[0]); + break; + case 2: + pat = GEN_FCN (icode) (op[0], op[1]); + break; + case 3: + pat = GEN_FCN (icode) (op[0], op[1], op[2]); + break; + case 4: + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); + break; + default: + gcc_unreachable (); + } + if (!pat) + return NULL_RTX; + emit_insn (pat); + + if (bif_is_htmcr (*bifaddr)) + { + if (fcode == RS6000_BIF_TBEGIN) + { + /* Emit code to set TARGET to true or false depending on + whether the tbegin. instruction succeeded or failed + to start a transaction. We do this by placing the 1's + complement of CR's EQ bit into TARGET. */ + rtx scratch = gen_reg_rtx (SImode); + emit_insn (gen_rtx_SET (scratch, + gen_rtx_EQ (SImode, cr, + const0_rtx))); + emit_insn (gen_rtx_SET (target, + gen_rtx_XOR (SImode, scratch, + GEN_INT (1)))); + } + else + { + /* Emit code to copy the 4-bit condition register field + CR into the least significant end of register TARGET. */ + rtx scratch1 = gen_reg_rtx (SImode); + rtx scratch2 = gen_reg_rtx (SImode); + rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0); + emit_insn (gen_movcc (subreg, cr)); + emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28))); + emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf))); + } + } + + if (nonvoid) + return target; + return const0_rtx; +} + +/* Expand an expression EXP that calls a built-in function, + with result going to TARGET if that's convenient + (and in mode MODE if that's convenient). + SUBTARGET may be used as the target for computing one of EXP's operands. + IGNORE is nonzero if the value is to be ignored. + Use the new builtin infrastructure. */ +static rtx +rs6000_expand_new_builtin (tree exp, rtx target, + rtx /* subtarget */, + machine_mode /* mode */, + int ignore) +{ + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); + enum rs6000_gen_builtins fcode + = (enum rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl); + size_t uns_fcode = (size_t)fcode; + enum insn_code icode = rs6000_builtin_info_x[uns_fcode].icode; + + /* TODO: The following commentary and code is inherited from the original + builtin processing code. The commentary is a bit confusing, with the + intent being that KFmode is always IEEE-128, IFmode is always IBM + double-double, and TFmode is the current long double. The code is + confusing in that it converts from KFmode to TFmode pattern names, + when the other direction is more intuitive. Try to address this. */ + + /* We have two different modes (KFmode, TFmode) that are the IEEE + 128-bit floating point type, depending on whether long double is the + IBM extended double (KFmode) or long double is IEEE 128-bit (TFmode). + It is simpler if we only define one variant of the built-in function, + and switch the code when defining it, rather than defining two built- + ins and using the overload table in rs6000-c.c to switch between the + two. If we don't have the proper assembler, don't do this switch + because CODE_FOR_*kf* and CODE_FOR_*tf* will be CODE_FOR_nothing. */ + if (FLOAT128_IEEE_P (TFmode)) + switch (icode) + { + case CODE_FOR_sqrtkf2_odd: + icode = CODE_FOR_sqrttf2_odd; + break; + case CODE_FOR_trunckfdf2_odd: + icode = CODE_FOR_trunctfdf2_odd; + break; + case CODE_FOR_addkf3_odd: + icode = CODE_FOR_addtf3_odd; + break; + case CODE_FOR_subkf3_odd: + icode = CODE_FOR_subtf3_odd; + break; + case CODE_FOR_mulkf3_odd: + icode = CODE_FOR_multf3_odd; + break; + case CODE_FOR_divkf3_odd: + icode = CODE_FOR_divtf3_odd; + break; + case CODE_FOR_fmakf4_odd: + icode = CODE_FOR_fmatf4_odd; + break; + case CODE_FOR_xsxexpqp_kf: + icode = CODE_FOR_xsxexpqp_tf; + break; + case CODE_FOR_xsxsigqp_kf: + icode = CODE_FOR_xsxsigqp_tf; + break; + case CODE_FOR_xststdcnegqp_kf: + icode = CODE_FOR_xststdcnegqp_tf; + break; + case CODE_FOR_xsiexpqp_kf: + icode = CODE_FOR_xsiexpqp_tf; + break; + case CODE_FOR_xsiexpqpf_kf: + icode = CODE_FOR_xsiexpqpf_tf; + break; + case CODE_FOR_xststdcqp_kf: + icode = CODE_FOR_xststdcqp_tf; + break; + case CODE_FOR_xscmpexpqp_eq_kf: + icode = CODE_FOR_xscmpexpqp_eq_tf; + break; + case CODE_FOR_xscmpexpqp_lt_kf: + icode = CODE_FOR_xscmpexpqp_lt_tf; + break; + case CODE_FOR_xscmpexpqp_gt_kf: + icode = CODE_FOR_xscmpexpqp_gt_tf; + break; + case CODE_FOR_xscmpexpqp_unordered_kf: + icode = CODE_FOR_xscmpexpqp_unordered_tf; + break; + default: + break; + } - if (TARGET_DEBUG_BUILTIN) - { - fprintf (stderr, "\nAutogenerated built-in functions:\n\n"); - for (int i = 1; i < (int) RS6000_BIF_MAX; i++) - { - bif_enable e = rs6000_builtin_info_x[i].enable; - if (e == ENB_P5 && !TARGET_POPCNTB) - continue; - if (e == ENB_P6 && !TARGET_CMPB) - continue; - if (e == ENB_P6_64 && !(TARGET_CMPB && TARGET_POWERPC64)) - continue; - if (e == ENB_ALTIVEC && !TARGET_ALTIVEC) - continue; - if (e == ENB_VSX && !TARGET_VSX) - continue; - if (e == ENB_P7 && !TARGET_POPCNTD) - continue; - if (e == ENB_P7_64 && !(TARGET_POPCNTD && TARGET_POWERPC64)) - continue; - if (e == ENB_P8 && !TARGET_DIRECT_MOVE) - continue; - if (e == ENB_P8V && !TARGET_P8_VECTOR) - continue; - if (e == ENB_P9 && !TARGET_MODULO) - continue; - if (e == ENB_P9_64 && !(TARGET_MODULO && TARGET_POWERPC64)) - continue; - if (e == ENB_P9V && !TARGET_P9_VECTOR) - continue; - if (e == ENB_IEEE128_HW && !TARGET_FLOAT128_HW) - continue; - if (e == ENB_DFP && !TARGET_DFP) - continue; - if (e == ENB_CRYPTO && !TARGET_CRYPTO) - continue; - if (e == ENB_HTM && !TARGET_HTM) - continue; - if (e == ENB_P10 && !TARGET_POWER10) - continue; - if (e == ENB_P10_64 && !(TARGET_POWER10 && TARGET_POWERPC64)) - continue; - if (e == ENB_MMA && !TARGET_MMA) - continue; - tree fntype = rs6000_builtin_info_x[i].fntype; - tree t = TREE_TYPE (fntype); - fprintf (stderr, "%s %s (", rs6000_type_string (t), - rs6000_builtin_info_x[i].bifname); - t = TYPE_ARG_TYPES (fntype); - while (t && TREE_VALUE (t) != void_type_node) - { - fprintf (stderr, "%s", - rs6000_type_string (TREE_VALUE (t))); - t = TREE_CHAIN (t); - if (t && TREE_VALUE (t) != void_type_node) - fprintf (stderr, ", "); - } - fprintf (stderr, "); %s [%4d]\n", - rs6000_builtin_info_x[i].attr_string, (int) i); - } - fprintf (stderr, "\nEnd autogenerated built-in functions.\n\n\n"); - } + /* In case of "#pragma target" changes, we initialize all builtins + but check for actual availability now, during expand time. For + invalid builtins, generate a normal call. */ + bifdata *bifaddr = &rs6000_builtin_info_x[uns_fcode]; + bif_enable e = bifaddr->enable; - if (TARGET_XCOFF) + if (!(e == ENB_ALWAYS + || (e == ENB_P5 && TARGET_POPCNTB) + || (e == ENB_P6 && TARGET_CMPB) + || (e == ENB_P6_64 && TARGET_CMPB && TARGET_POWERPC64) + || (e == ENB_ALTIVEC && TARGET_ALTIVEC) + || (e == ENB_CELL && TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL) + || (e == ENB_VSX && TARGET_VSX) + || (e == ENB_P7 && TARGET_POPCNTD) + || (e == ENB_P7_64 && TARGET_POPCNTD && TARGET_POWERPC64) + || (e == ENB_P8 && TARGET_DIRECT_MOVE) + || (e == ENB_P8V && TARGET_P8_VECTOR) + || (e == ENB_P9 && TARGET_MODULO) + || (e == ENB_P9_64 && TARGET_MODULO && TARGET_POWERPC64) + || (e == ENB_P9V && TARGET_P9_VECTOR) + || (e == ENB_IEEE128_HW && TARGET_FLOAT128_HW) + || (e == ENB_DFP && TARGET_DFP) + || (e == ENB_CRYPTO && TARGET_CRYPTO) + || (e == ENB_HTM && TARGET_HTM) + || (e == ENB_P10 && TARGET_POWER10) + || (e == ENB_P10_64 && TARGET_POWER10 && TARGET_POWERPC64) + || (e == ENB_MMA && TARGET_MMA))) { - /* AIX libm provides clog as __clog. */ - if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE) - set_user_assembler_name (tdecl, "__clog"); - - /* When long double is 64 bit, some long double builtins of libc - functions (like __builtin_frexpl) must call the double version - (frexp) not the long double version (frexpl) that expects a 128 bit - argument. */ - if (! TARGET_LONG_DOUBLE_128) - { - if ((tdecl = builtin_decl_explicit (BUILT_IN_FMODL)) != NULL_TREE) - set_user_assembler_name (tdecl, "fmod"); - if ((tdecl = builtin_decl_explicit (BUILT_IN_FREXPL)) != NULL_TREE) - set_user_assembler_name (tdecl, "frexp"); - if ((tdecl = builtin_decl_explicit (BUILT_IN_LDEXPL)) != NULL_TREE) - set_user_assembler_name (tdecl, "ldexp"); - if ((tdecl = builtin_decl_explicit (BUILT_IN_MODFL)) != NULL_TREE) - set_user_assembler_name (tdecl, "modf"); - } + rs6000_invalid_new_builtin (fcode); + return expand_call (exp, target, ignore); } - if (new_builtins_are_live) + if (bif_is_nosoft (*bifaddr) + && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT) { - altivec_builtin_mask_for_load - = rs6000_builtin_decls_x[RS6000_BIF_MASK_FOR_LOAD]; - -#ifdef SUBTARGET_INIT_BUILTINS - SUBTARGET_INIT_BUILTINS; -#endif - return; + error ("%<%s%> not supported with %<-msoft-float%>", + bifaddr->bifname); + return const0_rtx; } - /* Create Altivec, VSX and MMA builtins on machines with at least the - general purpose extensions (970 and newer) to allow the use of - the target attribute. */ - if (TARGET_EXTRA_BUILTINS) + if (bif_is_no32bit (*bifaddr) && TARGET_32BIT) { - altivec_init_builtins (); - mma_init_builtins (); + error ("%<%s%> is not supported in 32-bit mode", bifaddr->bifname); + return const0_rtx; } - if (TARGET_HTM) - htm_init_builtins (); - - if (TARGET_EXTRA_BUILTINS) - rs6000_common_init_builtins (); - - ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode, - RS6000_BUILTIN_RECIP, "__builtin_recipdiv"); - def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP); - - ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode, - RS6000_BUILTIN_RECIPF, "__builtin_recipdivf"); - def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF); - - ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode, - RS6000_BUILTIN_RSQRT, "__builtin_rsqrt"); - def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT); - - ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode, - RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf"); - def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF); - - mode = (TARGET_64BIT) ? DImode : SImode; - ftype = builtin_function_type (mode, mode, mode, VOIDmode, - POWER7_BUILTIN_BPERMD, "__builtin_bpermd"); - def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD); - - ftype = build_function_type_list (unsigned_intDI_type_node, - NULL_TREE); - def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB); - - if (TARGET_64BIT) - ftype = build_function_type_list (unsigned_intDI_type_node, - NULL_TREE); - else - ftype = build_function_type_list (unsigned_intSI_type_node, - NULL_TREE); - def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB); - - ftype = build_function_type_list (double_type_node, NULL_TREE); - def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS); - - ftype = build_function_type_list (double_type_node, NULL_TREE); - def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL); - - ftype = build_function_type_list (void_type_node, - intSI_type_node, - NULL_TREE); - def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0); - - ftype = build_function_type_list (void_type_node, - intSI_type_node, - NULL_TREE); - def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1); - - ftype = build_function_type_list (void_type_node, - intDI_type_node, - NULL_TREE); - def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN); - - ftype = build_function_type_list (void_type_node, - intDI_type_node, - NULL_TREE); - def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN); - - ftype = build_function_type_list (void_type_node, - intSI_type_node, double_type_node, - NULL_TREE); - def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF); - - ftype = build_function_type_list (void_type_node, NULL_TREE); - def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT); - def_builtin ("__builtin_ppc_speculation_barrier", ftype, - MISC_BUILTIN_SPEC_BARRIER); - - ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node, - NULL_TREE); - def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS); - def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS); - -#ifdef SUBTARGET_INIT_BUILTINS - SUBTARGET_INIT_BUILTINS; -#endif - /* Register the compatibility builtins after all of the normal - builtins have been defined. */ - const struct builtin_compatibility *d = bdesc_compat; - unsigned i; - for (i = 0; i < ARRAY_SIZE (bdesc_compat); i++, d++) + if (bif_is_ibmld (*bifaddr) && !FLOAT128_2REG_P (TFmode)) { - tree decl = rs6000_builtin_decls[(int)d->code]; - if (decl != NULL) - add_builtin_function (d->name, TREE_TYPE (decl), (int)d->code, - BUILT_IN_MD, NULL, NULL_TREE); + error ("%<%s%> requires % to be IBM 128-bit format", + bifaddr->bifname); + return const0_rtx; } -} -static tree -rs6000_new_builtin_decl (unsigned code, bool /* initialize_p */) -{ - rs6000_gen_builtins fcode = (rs6000_gen_builtins) code; - - if (fcode >= RS6000_OVLD_MAX) - return error_mark_node; + if (bif_is_cpu (*bifaddr)) + return new_cpu_expand_builtin (fcode, exp, target); - return rs6000_builtin_decls_x[code]; -} + if (bif_is_init (*bifaddr)) + return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target); -/* Returns the rs6000 builtin decl for CODE. Note that we don't check - the builtin mask here since there could be some #pragma/attribute - target functions and the rs6000_builtin_mask could be wrong when - this checking happens, though it will be updated properly later. */ + if (bif_is_set (*bifaddr)) + return altivec_expand_vec_set_builtin (exp); -tree -rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) -{ - if (new_builtins_are_live) - return rs6000_new_builtin_decl (code, initialize_p); + if (bif_is_extract (*bifaddr)) + return altivec_expand_vec_ext_builtin (exp, target); - if (code >= RS6000_BUILTIN_COUNT) - return error_mark_node; + if (bif_is_predicate (*bifaddr)) + return altivec_expand_predicate_builtin (icode, exp, target); - return rs6000_builtin_decls[code]; -} + if (bif_is_htm (*bifaddr)) + return new_htm_expand_builtin (bifaddr, fcode, exp, target); -static void -altivec_init_builtins (void) -{ - const struct builtin_description *d; - size_t i; - tree ftype; - tree decl; - - tree pvoid_type_node = build_pointer_type (void_type_node); - - tree int_ftype_opaque - = build_function_type_list (integer_type_node, - opaque_V4SI_type_node, NULL_TREE); - tree opaque_ftype_opaque - = build_function_type_list (integer_type_node, NULL_TREE); - tree opaque_ftype_opaque_int - = build_function_type_list (opaque_V4SI_type_node, - opaque_V4SI_type_node, integer_type_node, NULL_TREE); - tree opaque_ftype_opaque_opaque_int - = build_function_type_list (opaque_V4SI_type_node, - opaque_V4SI_type_node, opaque_V4SI_type_node, - integer_type_node, NULL_TREE); - tree opaque_ftype_opaque_opaque_opaque - = build_function_type_list (opaque_V4SI_type_node, - opaque_V4SI_type_node, opaque_V4SI_type_node, - opaque_V4SI_type_node, NULL_TREE); - tree opaque_ftype_opaque_opaque - = build_function_type_list (opaque_V4SI_type_node, - opaque_V4SI_type_node, opaque_V4SI_type_node, - NULL_TREE); - tree int_ftype_int_opaque_opaque - = build_function_type_list (integer_type_node, - integer_type_node, opaque_V4SI_type_node, - opaque_V4SI_type_node, NULL_TREE); - tree int_ftype_int_v4si_v4si - = build_function_type_list (integer_type_node, - integer_type_node, V4SI_type_node, - V4SI_type_node, NULL_TREE); - tree int_ftype_int_v2di_v2di - = build_function_type_list (integer_type_node, - integer_type_node, V2DI_type_node, - V2DI_type_node, NULL_TREE); - tree int_ftype_int_v1ti_v1ti - = build_function_type_list (integer_type_node, - integer_type_node, V1TI_type_node, - V1TI_type_node, NULL_TREE); - tree void_ftype_v4si - = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); - tree v8hi_ftype_void - = build_function_type_list (V8HI_type_node, NULL_TREE); - tree void_ftype_void - = build_function_type_list (void_type_node, NULL_TREE); - tree void_ftype_int - = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); - - tree opaque_ftype_long_pcvoid - = build_function_type_list (opaque_V4SI_type_node, - long_integer_type_node, pcvoid_type_node, - NULL_TREE); - tree v16qi_ftype_pcvoid - = build_function_type_list (V16QI_type_node, - pcvoid_type_node, - NULL_TREE); - tree v16qi_ftype_long_pcvoid - = build_function_type_list (V16QI_type_node, - long_integer_type_node, pcvoid_type_node, - NULL_TREE); - tree v8hi_ftype_long_pcvoid - = build_function_type_list (V8HI_type_node, - long_integer_type_node, pcvoid_type_node, - NULL_TREE); - tree v4si_ftype_long_pcvoid - = build_function_type_list (V4SI_type_node, - long_integer_type_node, pcvoid_type_node, - NULL_TREE); - tree v4sf_ftype_long_pcvoid - = build_function_type_list (V4SF_type_node, - long_integer_type_node, pcvoid_type_node, - NULL_TREE); - tree v2df_ftype_long_pcvoid - = build_function_type_list (V2DF_type_node, - long_integer_type_node, pcvoid_type_node, - NULL_TREE); - tree v2di_ftype_long_pcvoid - = build_function_type_list (V2DI_type_node, - long_integer_type_node, pcvoid_type_node, - NULL_TREE); - tree v1ti_ftype_long_pcvoid - = build_function_type_list (V1TI_type_node, - long_integer_type_node, pcvoid_type_node, - NULL_TREE); - - tree void_ftype_opaque_long_pvoid - = build_function_type_list (void_type_node, - opaque_V4SI_type_node, long_integer_type_node, - pvoid_type_node, NULL_TREE); - tree void_ftype_v4si_long_pvoid - = build_function_type_list (void_type_node, - V4SI_type_node, long_integer_type_node, - pvoid_type_node, NULL_TREE); - tree void_ftype_v16qi_long_pvoid - = build_function_type_list (void_type_node, - V16QI_type_node, long_integer_type_node, - pvoid_type_node, NULL_TREE); - - tree void_ftype_v16qi_pvoid_long - = build_function_type_list (void_type_node, - V16QI_type_node, pvoid_type_node, - long_integer_type_node, NULL_TREE); - - tree void_ftype_v8hi_long_pvoid - = build_function_type_list (void_type_node, - V8HI_type_node, long_integer_type_node, - pvoid_type_node, NULL_TREE); - tree void_ftype_v4sf_long_pvoid - = build_function_type_list (void_type_node, - V4SF_type_node, long_integer_type_node, - pvoid_type_node, NULL_TREE); - tree void_ftype_v2df_long_pvoid - = build_function_type_list (void_type_node, - V2DF_type_node, long_integer_type_node, - pvoid_type_node, NULL_TREE); - tree void_ftype_v1ti_long_pvoid - = build_function_type_list (void_type_node, - V1TI_type_node, long_integer_type_node, - pvoid_type_node, NULL_TREE); - tree void_ftype_v2di_long_pvoid - = build_function_type_list (void_type_node, - V2DI_type_node, long_integer_type_node, - pvoid_type_node, NULL_TREE); - tree int_ftype_int_v8hi_v8hi - = build_function_type_list (integer_type_node, - integer_type_node, V8HI_type_node, - V8HI_type_node, NULL_TREE); - tree int_ftype_int_v16qi_v16qi - = build_function_type_list (integer_type_node, - integer_type_node, V16QI_type_node, - V16QI_type_node, NULL_TREE); - tree int_ftype_int_v4sf_v4sf - = build_function_type_list (integer_type_node, - integer_type_node, V4SF_type_node, - V4SF_type_node, NULL_TREE); - tree int_ftype_int_v2df_v2df - = build_function_type_list (integer_type_node, - integer_type_node, V2DF_type_node, - V2DF_type_node, NULL_TREE); - tree v2di_ftype_v2di - = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE); - tree v4si_ftype_v4si - = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); - tree v8hi_ftype_v8hi - = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); - tree v16qi_ftype_v16qi - = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); - tree v4sf_ftype_v4sf - = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); - tree v2df_ftype_v2df - = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE); - tree void_ftype_pcvoid_int_int - = build_function_type_list (void_type_node, - pcvoid_type_node, integer_type_node, - integer_type_node, NULL_TREE); - - def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); - def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); - def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); - def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS); - def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL); - def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR); - def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX); - def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); - def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); - def_builtin ("__builtin_altivec_se_lxvrbx", v16qi_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRBX); - def_builtin ("__builtin_altivec_se_lxvrhx", v8hi_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRHX); - def_builtin ("__builtin_altivec_se_lxvrwx", v4si_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRWX); - def_builtin ("__builtin_altivec_se_lxvrdx", v2di_ftype_long_pcvoid, P10_BUILTIN_SE_LXVRDX); - def_builtin ("__builtin_altivec_ze_lxvrbx", v16qi_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRBX); - def_builtin ("__builtin_altivec_ze_lxvrhx", v8hi_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRHX); - def_builtin ("__builtin_altivec_ze_lxvrwx", v4si_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRWX); - def_builtin ("__builtin_altivec_ze_lxvrdx", v2di_ftype_long_pcvoid, P10_BUILTIN_ZE_LXVRDX); - def_builtin ("__builtin_altivec_tr_stxvrbx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRBX); - def_builtin ("__builtin_altivec_tr_stxvrhx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRHX); - def_builtin ("__builtin_altivec_tr_stxvrwx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRWX); - def_builtin ("__builtin_altivec_tr_stxvrdx", void_ftype_v1ti_long_pvoid, P10_BUILTIN_TR_STXVRDX); - def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); - def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVXL_V2DF); - def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVXL_V2DI); - def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVXL_V4SF); - def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVXL_V4SI); - def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVXL_V8HI); - def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVXL_V16QI); - def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX); - def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVX_V1TI); - def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVX_V2DF); - def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVX_V2DI); - def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVX_V4SF); - def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVX_V4SI); - def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVX_V8HI); - def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid, - ALTIVEC_BUILTIN_LVX_V16QI); - def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX); - def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid, - ALTIVEC_BUILTIN_STVX_V2DF); - def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid, - ALTIVEC_BUILTIN_STVX_V2DI); - def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid, - ALTIVEC_BUILTIN_STVX_V4SF); - def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid, - ALTIVEC_BUILTIN_STVX_V4SI); - def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid, - ALTIVEC_BUILTIN_STVX_V8HI); - def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid, - ALTIVEC_BUILTIN_STVX_V16QI); - def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX); - def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL); - def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid, - ALTIVEC_BUILTIN_STVXL_V2DF); - def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid, - ALTIVEC_BUILTIN_STVXL_V2DI); - def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid, - ALTIVEC_BUILTIN_STVXL_V4SF); - def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid, - ALTIVEC_BUILTIN_STVXL_V4SI); - def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid, - ALTIVEC_BUILTIN_STVXL_V8HI); - def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid, - ALTIVEC_BUILTIN_STVXL_V16QI); - def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); - def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); - def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD); - def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE); - def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL); - def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL); - def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR); - def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX); - def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX); - def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX); - def_builtin ("__builtin_vec_se_lxvrx", v1ti_ftype_long_pcvoid, P10_BUILTIN_VEC_SE_LXVRX); - def_builtin ("__builtin_vec_ze_lxvrx", v1ti_ftype_long_pcvoid, P10_BUILTIN_VEC_ZE_LXVRX); - def_builtin ("__builtin_vec_tr_stxvrx", void_ftype_opaque_long_pvoid, P10_BUILTIN_VEC_TR_STXVRX); - def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST); - def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE); - def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL); - def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX); - def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX); - def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX); - - def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid, - VSX_BUILTIN_LXVD2X_V2DF); - def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid, - VSX_BUILTIN_LXVD2X_V2DI); - def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid, - VSX_BUILTIN_LXVW4X_V4SF); - def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid, - VSX_BUILTIN_LXVW4X_V4SI); - def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid, - VSX_BUILTIN_LXVW4X_V8HI); - def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid, - VSX_BUILTIN_LXVW4X_V16QI); - def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid, - VSX_BUILTIN_STXVD2X_V2DF); - def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid, - VSX_BUILTIN_STXVD2X_V2DI); - def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid, - VSX_BUILTIN_STXVW4X_V4SF); - def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid, - VSX_BUILTIN_STXVW4X_V4SI); - def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid, - VSX_BUILTIN_STXVW4X_V8HI); - def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid, - VSX_BUILTIN_STXVW4X_V16QI); - - def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid, - VSX_BUILTIN_LD_ELEMREV_V2DF); - def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid, - VSX_BUILTIN_LD_ELEMREV_V2DI); - def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid, - VSX_BUILTIN_LD_ELEMREV_V4SF); - def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid, - VSX_BUILTIN_LD_ELEMREV_V4SI); - def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid, - VSX_BUILTIN_LD_ELEMREV_V8HI); - def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid, - VSX_BUILTIN_LD_ELEMREV_V16QI); - def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid, - VSX_BUILTIN_ST_ELEMREV_V2DF); - def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid, - VSX_BUILTIN_ST_ELEMREV_V1TI); - def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid, - VSX_BUILTIN_ST_ELEMREV_V2DI); - def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid, - VSX_BUILTIN_ST_ELEMREV_V4SF); - def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid, - VSX_BUILTIN_ST_ELEMREV_V4SI); - def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid, - VSX_BUILTIN_ST_ELEMREV_V8HI); - def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid, - VSX_BUILTIN_ST_ELEMREV_V16QI); - - def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid, - VSX_BUILTIN_VEC_LD); - def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid, - VSX_BUILTIN_VEC_ST); - def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid, - VSX_BUILTIN_VEC_XL); - def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid, - VSX_BUILTIN_VEC_XL_BE); - def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid, - VSX_BUILTIN_VEC_XST); - def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid, - VSX_BUILTIN_VEC_XST_BE); - - def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP); - def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS); - def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE); - - def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD); - def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT); - def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT); - def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT); - def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW); - def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH); - def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB); - def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF); - def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX); - def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX); - def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS); - def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU); - - def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque, - ALTIVEC_BUILTIN_VEC_ADDE); - def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque, - ALTIVEC_BUILTIN_VEC_ADDEC); - def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque, - ALTIVEC_BUILTIN_VEC_CMPNE); - def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque, - ALTIVEC_BUILTIN_VEC_MUL); - def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque, - ALTIVEC_BUILTIN_VEC_SUBE); - def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque, - ALTIVEC_BUILTIN_VEC_SUBEC); - - /* Cell builtins. */ - def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX); - def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL); - def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX); - def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL); - - def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX); - def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL); - def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX); - def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL); - - def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX); - def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL); - def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX); - def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL); - - def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX); - def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL); - def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX); - def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL); - - if (TARGET_P9_VECTOR) + if (bif_is_32bit (*bifaddr) && TARGET_32BIT) { - def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long, - P9V_BUILTIN_STXVL); - def_builtin ("__builtin_altivec_xst_len_r", void_ftype_v16qi_pvoid_long, - P9V_BUILTIN_XST_LEN_R); + if (fcode == RS6000_BIF_MFTB) + icode = CODE_FOR_rs6000_mftb_si; + else if (fcode == RS6000_BIF_BPERMD) + icode = CODE_FOR_bpermd_si; + else + gcc_unreachable (); } - /* Add the DST variants. */ - d = bdesc_dst; - for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) + if (bif_is_endian (*bifaddr) && BYTES_BIG_ENDIAN) { - /* It is expected that these dst built-in functions may have - d->icode equal to CODE_FOR_nothing. */ - def_builtin (d->name, void_ftype_pcvoid_int_int, d->code); + if (fcode == RS6000_BIF_LD_ELEMREV_V1TI) + icode = CODE_FOR_vsx_load_v1ti; + else if (fcode == RS6000_BIF_LD_ELEMREV_V2DF) + icode = CODE_FOR_vsx_load_v2df; + else if (fcode == RS6000_BIF_LD_ELEMREV_V2DI) + icode = CODE_FOR_vsx_load_v2di; + else if (fcode == RS6000_BIF_LD_ELEMREV_V4SF) + icode = CODE_FOR_vsx_load_v4sf; + else if (fcode == RS6000_BIF_LD_ELEMREV_V4SI) + icode = CODE_FOR_vsx_load_v4si; + else if (fcode == RS6000_BIF_LD_ELEMREV_V8HI) + icode = CODE_FOR_vsx_load_v8hi; + else if (fcode == RS6000_BIF_LD_ELEMREV_V16QI) + icode = CODE_FOR_vsx_load_v16qi; + else if (fcode == RS6000_BIF_ST_ELEMREV_V1TI) + icode = CODE_FOR_vsx_store_v1ti; + else if (fcode == RS6000_BIF_ST_ELEMREV_V2DF) + icode = CODE_FOR_vsx_store_v2df; + else if (fcode == RS6000_BIF_ST_ELEMREV_V2DI) + icode = CODE_FOR_vsx_store_v2di; + else if (fcode == RS6000_BIF_ST_ELEMREV_V4SF) + icode = CODE_FOR_vsx_store_v4sf; + else if (fcode == RS6000_BIF_ST_ELEMREV_V4SI) + icode = CODE_FOR_vsx_store_v4si; + else if (fcode == RS6000_BIF_ST_ELEMREV_V8HI) + icode = CODE_FOR_vsx_store_v8hi; + else if (fcode == RS6000_BIF_ST_ELEMREV_V16QI) + icode = CODE_FOR_vsx_store_v16qi; + else + gcc_unreachable (); } - /* Initialize the predicates. */ - d = bdesc_altivec_preds; - for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++) + + /* TRUE iff the built-in function returns void. */ + bool void_func = TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node; + /* Position of first argument (0 for void-returning functions, else 1). */ + int k; + /* Modes for the return value, if any, and arguments. */ + const int MAX_BUILTIN_ARGS = 6; + machine_mode mode[MAX_BUILTIN_ARGS + 1]; + + if (void_func) + k = 0; + else { - machine_mode mode1; - tree type; + k = 1; + mode[0] = insn_data[icode].operand[0].mode; + } - if (rs6000_overloaded_builtin_p (d->code)) - mode1 = VOIDmode; - else - { - /* Cannot define builtin if the instruction is disabled. */ - gcc_assert (d->icode != CODE_FOR_nothing); - mode1 = insn_data[d->icode].operand[1].mode; - } + /* Tree expressions for each argument. */ + tree arg[MAX_BUILTIN_ARGS]; + /* RTL expressions for each argument. */ + rtx op[MAX_BUILTIN_ARGS]; - switch (mode1) - { - case E_VOIDmode: - type = int_ftype_int_opaque_opaque; - break; - case E_V1TImode: - type = int_ftype_int_v1ti_v1ti; - break; - case E_V2DImode: - type = int_ftype_int_v2di_v2di; - break; - case E_V4SImode: - type = int_ftype_int_v4si_v4si; - break; - case E_V8HImode: - type = int_ftype_int_v8hi_v8hi; - break; - case E_V16QImode: - type = int_ftype_int_v16qi_v16qi; - break; - case E_V4SFmode: - type = int_ftype_int_v4sf_v4sf; - break; - case E_V2DFmode: - type = int_ftype_int_v2df_v2df; - break; - default: - gcc_unreachable (); - } + int nargs = bifaddr->nargs; + gcc_assert (nargs <= MAX_BUILTIN_ARGS); - def_builtin (d->name, type, d->code); - } - /* Initialize the abs* operators. */ - d = bdesc_abs; - for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) + for (int i = 0; i < nargs; i++) { - machine_mode mode0; - tree type; - - /* Cannot define builtin if the instruction is disabled. */ - gcc_assert (d->icode != CODE_FOR_nothing); - mode0 = insn_data[d->icode].operand[0].mode; + arg[i] = CALL_EXPR_ARG (exp, i); + if (arg[i] == error_mark_node) + return const0_rtx; + STRIP_NOPS (arg[i]); + op[i] = expand_normal (arg[i]); + /* We have a couple of pesky patterns that don't specify the mode... */ + mode[i+k] = insn_data[icode].operand[i+k].mode; + if (!mode[i+k]) + mode[i+k] = Pmode; + } - switch (mode0) + /* Check for restricted constant arguments. */ + for (int i = 0; i < 2; i++) + { + switch (bifaddr->restr[i]) { - case E_V2DImode: - type = v2di_ftype_v2di; - break; - case E_V4SImode: - type = v4si_ftype_v4si; - break; - case E_V8HImode: - type = v8hi_ftype_v8hi; - break; - case E_V16QImode: - type = v16qi_ftype_v16qi; - break; - case E_V4SFmode: - type = v4sf_ftype_v4sf; - break; - case E_V2DFmode: - type = v2df_ftype_v2df; - break; + case RES_BITS: + { + size_t mask = 1; + mask <<= bifaddr->restr_val1[i]; + mask--; + tree restr_arg = arg[bifaddr->restr_opnd[i] - 1]; + STRIP_NOPS (restr_arg); + if (!(TREE_CODE (restr_arg) == INTEGER_CST + && (TREE_INT_CST_LOW (restr_arg) & ~mask) == 0)) + { + error ("argument %d must be a %d-bit unsigned literal", + bifaddr->restr_opnd[i], bifaddr->restr_val1[i]); + return CONST0_RTX (mode[0]); + } + break; + } + case RES_RANGE: + { + tree restr_arg = arg[bifaddr->restr_opnd[i] - 1]; + STRIP_NOPS (restr_arg); + if (!(TREE_CODE (restr_arg) == INTEGER_CST + && IN_RANGE (tree_to_shwi (restr_arg), + bifaddr->restr_val1[i], + bifaddr->restr_val2[i]))) + { + error ("argument %d must be a literal between %d and %d," + " inclusive", + bifaddr->restr_opnd[i], bifaddr->restr_val1[i], + bifaddr->restr_val2[i]); + return CONST0_RTX (mode[0]); + } + break; + } + case RES_VAR_RANGE: + { + tree restr_arg = arg[bifaddr->restr_opnd[i] - 1]; + STRIP_NOPS (restr_arg); + if (TREE_CODE (restr_arg) == INTEGER_CST + && !IN_RANGE (tree_to_shwi (restr_arg), + bifaddr->restr_val1[i], + bifaddr->restr_val2[i])) + { + error ("argument %d must be a variable or a literal " + "between %d and %d, inclusive", + bifaddr->restr_opnd[i], bifaddr->restr_val1[i], + bifaddr->restr_val2[i]); + return CONST0_RTX (mode[0]); + } + break; + } + case RES_VALUES: + { + tree restr_arg = arg[bifaddr->restr_opnd[i] - 1]; + STRIP_NOPS (restr_arg); + if (!(TREE_CODE (restr_arg) == INTEGER_CST + && (tree_to_shwi (restr_arg) == bifaddr->restr_val1[i] + || tree_to_shwi (restr_arg) == bifaddr->restr_val2[i]))) + { + error ("argument %d must be either a literal %d or a " + "literal %d", + bifaddr->restr_opnd[i], bifaddr->restr_val1[i], + bifaddr->restr_val2[i]); + return CONST0_RTX (mode[0]); + } + break; + } default: - gcc_unreachable (); + case RES_NONE: + break; } - - def_builtin (d->name, type, d->code); } - /* Initialize target builtin that implements - targetm.vectorize.builtin_mask_for_load. */ + if (bif_is_ldstmask (*bifaddr)) + return rs6000_expand_ldst_mask (target, arg[0]); - decl = add_builtin_function ("__builtin_altivec_mask_for_load", - v16qi_ftype_pcvoid, - ALTIVEC_BUILTIN_MASK_FOR_LOAD, - BUILT_IN_MD, NULL, NULL_TREE); - TREE_READONLY (decl) = 1; - if (TARGET_DEBUG_BUILTIN) - { - tree arg_type = TREE_VALUE (TYPE_ARG_TYPES (v16qi_ftype_pcvoid)); - fprintf (stderr, "%s __builtin_altivec_mask_for_load (%s); [%4d]\n", - rs6000_type_string (TREE_TYPE (v16qi_ftype_pcvoid)), - rs6000_type_string (arg_type), - (int) ALTIVEC_BUILTIN_MASK_FOR_LOAD); - } - /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */ - altivec_builtin_mask_for_load = decl; - - /* Access to the vec_init patterns. */ - ftype = build_function_type_list (V4SI_type_node, integer_type_node, - integer_type_node, integer_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI); - - ftype = build_function_type_list (V8HI_type_node, short_integer_type_node, - short_integer_type_node, - short_integer_type_node, - short_integer_type_node, - short_integer_type_node, - short_integer_type_node, - short_integer_type_node, - short_integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI); - - ftype = build_function_type_list (V16QI_type_node, char_type_node, - char_type_node, char_type_node, - char_type_node, char_type_node, - char_type_node, char_type_node, - char_type_node, char_type_node, - char_type_node, char_type_node, - char_type_node, char_type_node, - char_type_node, char_type_node, - char_type_node, NULL_TREE); - def_builtin ("__builtin_vec_init_v16qi", ftype, - ALTIVEC_BUILTIN_VEC_INIT_V16QI); - - ftype = build_function_type_list (V4SF_type_node, float_type_node, - float_type_node, float_type_node, - float_type_node, NULL_TREE); - def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF); - - /* VSX builtins. */ - ftype = build_function_type_list (V2DF_type_node, double_type_node, - double_type_node, NULL_TREE); - def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF); - - ftype = build_function_type_list (V2DI_type_node, intDI_type_node, - intDI_type_node, NULL_TREE); - def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI); - - /* Access to the vec_set patterns. */ - ftype = build_function_type_list (V4SI_type_node, V4SI_type_node, - intSI_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI); - - ftype = build_function_type_list (V8HI_type_node, V8HI_type_node, - intHI_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI); - - ftype = build_function_type_list (V16QI_type_node, V16QI_type_node, - intQI_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI); - - ftype = build_function_type_list (V4SF_type_node, V4SF_type_node, - float_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF); - - ftype = build_function_type_list (V2DF_type_node, V2DF_type_node, - double_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF); - - ftype = build_function_type_list (V2DI_type_node, V2DI_type_node, - intDI_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI); - - /* Access to the vec_extract patterns. */ - ftype = build_function_type_list (intSI_type_node, V4SI_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI); - - ftype = build_function_type_list (intHI_type_node, V8HI_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI); - - ftype = build_function_type_list (intQI_type_node, V16QI_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI); - - ftype = build_function_type_list (float_type_node, V4SF_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF); - - ftype = build_function_type_list (double_type_node, V2DF_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF); - - ftype = build_function_type_list (intDI_type_node, V2DI_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI); - - - if (V1TI_type_node) + if (bif_is_stvec (*bifaddr)) { - tree v1ti_ftype_long_pcvoid - = build_function_type_list (V1TI_type_node, - long_integer_type_node, pcvoid_type_node, - NULL_TREE); - tree void_ftype_v1ti_long_pvoid - = build_function_type_list (void_type_node, - V1TI_type_node, long_integer_type_node, - pvoid_type_node, NULL_TREE); - def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid, - VSX_BUILTIN_LD_ELEMREV_V1TI); - def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid, - VSX_BUILTIN_LXVD2X_V1TI); - def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid, - VSX_BUILTIN_STXVD2X_V1TI); - ftype = build_function_type_list (V1TI_type_node, intTI_type_node, - NULL_TREE, NULL_TREE); - def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI); - ftype = build_function_type_list (V1TI_type_node, V1TI_type_node, - intTI_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI); - ftype = build_function_type_list (intTI_type_node, V1TI_type_node, - integer_type_node, NULL_TREE); - def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI); + if (bif_is_reve (*bifaddr)) + icode = elemrev_icode (fcode); + return stv_expand_builtin (icode, op, mode[0], mode[1]); } -} - -static void -mma_init_builtins (void) -{ - const struct builtin_description *d = bdesc_mma; - - for (unsigned i = 0; i < ARRAY_SIZE (bdesc_mma); i++, d++) + if (bif_is_ldvec (*bifaddr)) { - tree op[MAX_MMA_OPERANDS], type; - unsigned icode = (unsigned) d->icode; - unsigned attr = rs6000_builtin_info[d->code].attr; - int attr_args = (attr & RS6000_BTC_OPND_MASK); - bool gimple_func = (attr & RS6000_BTC_GIMPLE); - unsigned nopnds = 0; - - if (d->name == 0) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "mma_builtin, bdesc_mma[%ld] no name\n", - (long unsigned) i); - continue; - } - - if (gimple_func) - { - gcc_assert (icode == CODE_FOR_nothing); - /* Some MMA built-ins that are expanded into gimple are converted - into internal MMA built-ins that are expanded into rtl. - The internal built-in follows immediately after this built-in. */ - if (d->code != VSX_BUILTIN_LXVP - && d->code != VSX_BUILTIN_STXVP) - { - op[nopnds++] = void_type_node; - icode = d[1].icode; - } - } - else - { - if (!(d->code == MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL - || d->code == VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL) - && (attr & RS6000_BTC_QUAD) == 0) - attr_args--; + if (bif_is_reve (*bifaddr)) + icode = elemrev_icode (fcode); + return ldv_expand_builtin (target, icode, op, mode[0]); + } - /* Ensure we have the correct number and type of operands. */ - gcc_assert (attr_args == insn_data[icode].n_operands - 1); - } + if (bif_is_lxvrse (*bifaddr)) + return lxvrse_expand_builtin (target, icode, op, mode[0], mode[1]); - /* This is a disassemble pair/acc function. */ - if (d->code == MMA_BUILTIN_DISASSEMBLE_ACC - || d->code == VSX_BUILTIN_DISASSEMBLE_PAIR) - { - op[nopnds++] = build_pointer_type (void_type_node); - if (d->code == MMA_BUILTIN_DISASSEMBLE_ACC) - op[nopnds++] = build_pointer_type (vector_quad_type_node); - else - op[nopnds++] = build_pointer_type (vector_pair_type_node); - } - else if (d->code == VSX_BUILTIN_LXVP) - { - op[nopnds++] = vector_pair_type_node; - op[nopnds++] = sizetype; - op[nopnds++] = build_pointer_type (vector_pair_type_node); - } - else if (d->code == VSX_BUILTIN_STXVP) - { - op[nopnds++] = void_type_node; - op[nopnds++] = vector_pair_type_node; - op[nopnds++] = sizetype; - op[nopnds++] = build_pointer_type (vector_pair_type_node); - } - else - { - /* This is a normal MMA built-in function. */ - unsigned j = 0; - if (attr & RS6000_BTC_QUAD - && d->code != MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL - && d->code != VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL) - j = 1; - for (; j < (unsigned) insn_data[icode].n_operands; j++) - { - machine_mode mode = insn_data[icode].operand[j].mode; - if (gimple_func && mode == XOmode) - op[nopnds++] = build_pointer_type (vector_quad_type_node); - else if (gimple_func - && mode == OOmode - && (d->code == VSX_BUILTIN_BUILD_PAIR - || d->code == VSX_BUILTIN_ASSEMBLE_PAIR)) - op[nopnds++] = build_pointer_type (vector_pair_type_node); - else - /* MMA uses unsigned types. */ - op[nopnds++] = builtin_mode_to_type[mode][1]; - } - } + if (bif_is_lxvrze (*bifaddr)) + return lxvrze_expand_builtin (target, icode, op, mode[0], mode[1]); - switch (nopnds) - { - case 1: - type = build_function_type_list (op[0], NULL_TREE); - break; - case 2: - type = build_function_type_list (op[0], op[1], NULL_TREE); - break; - case 3: - type = build_function_type_list (op[0], op[1], op[2], NULL_TREE); - break; - case 4: - type = build_function_type_list (op[0], op[1], op[2], op[3], - NULL_TREE); - break; - case 5: - type = build_function_type_list (op[0], op[1], op[2], op[3], op[4], - NULL_TREE); - break; - case 6: - type = build_function_type_list (op[0], op[1], op[2], op[3], op[4], - op[5], NULL_TREE); - break; - case 7: - type = build_function_type_list (op[0], op[1], op[2], op[3], op[4], - op[5], op[6], NULL_TREE); - break; - default: - gcc_unreachable (); - } + if (bif_is_mma (*bifaddr)) + return new_mma_expand_builtin (exp, target, icode, fcode); - def_builtin (d->name, type, d->code); + if (fcode == RS6000_BIF_PACK_IF + && TARGET_LONG_DOUBLE_128 + && !TARGET_IEEEQUAD) + { + icode = CODE_FOR_packtf; + fcode = RS6000_BIF_PACK_TF; + uns_fcode = (size_t) fcode; } -} - -static void -htm_init_builtins (void) -{ - HOST_WIDE_INT builtin_mask = rs6000_builtin_mask; - const struct builtin_description *d; - size_t i; - - d = bdesc_htm; - for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++) + else if (fcode == RS6000_BIF_UNPACK_IF + && TARGET_LONG_DOUBLE_128 + && !TARGET_IEEEQUAD) { - tree op[MAX_HTM_OPERANDS], type; - HOST_WIDE_INT mask = d->mask; - unsigned attr = rs6000_builtin_info[d->code].attr; - bool void_func = (attr & RS6000_BTC_VOID); - int attr_args = (attr & RS6000_BTC_OPND_MASK); - int nopnds = 0; - tree gpr_type_node; - tree rettype; - tree argtype; - - /* It is expected that these htm built-in functions may have - d->icode equal to CODE_FOR_nothing. */ - - if (TARGET_32BIT && TARGET_POWERPC64) - gpr_type_node = long_long_unsigned_type_node; - else - gpr_type_node = long_unsigned_type_node; - - if (attr & RS6000_BTC_SPR) - { - rettype = gpr_type_node; - argtype = gpr_type_node; - } - else if (d->code == HTM_BUILTIN_TABORTDC - || d->code == HTM_BUILTIN_TABORTDCI) - { - rettype = unsigned_type_node; - argtype = gpr_type_node; - } - else - { - rettype = unsigned_type_node; - argtype = unsigned_type_node; - } + icode = CODE_FOR_unpacktf; + fcode = RS6000_BIF_UNPACK_TF; + uns_fcode = (size_t) fcode; + } - if ((mask & builtin_mask) != mask) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "htm_builtin, skip binary %s\n", d->name); - continue; - } + if (TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node) + target = NULL_RTX; + else if (target == 0 + || GET_MODE (target) != mode[0] + || !insn_data[icode].operand[0].predicate (target, mode[0])) + target = gen_reg_rtx (mode[0]); - if (d->name == 0) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n", - (long unsigned) i); - continue; - } + for (int i = 0; i < nargs; i++) + if (!insn_data[icode].operand[i+k].predicate (op[i], mode[i+k])) + op[i] = copy_to_mode_reg (mode[i+k], op[i]); - op[nopnds++] = (void_func) ? void_type_node : rettype; + rtx pat; - if (attr_args == RS6000_BTC_UNARY) - op[nopnds++] = argtype; - else if (attr_args == RS6000_BTC_BINARY) - { - op[nopnds++] = argtype; - op[nopnds++] = argtype; - } - else if (attr_args == RS6000_BTC_TERNARY) - { - op[nopnds++] = argtype; - op[nopnds++] = argtype; - op[nopnds++] = argtype; - } + switch (nargs) + { + case 0: + pat = (void_func + ? GEN_FCN (icode) () + : GEN_FCN (icode) (target)); + break; + case 1: + pat = (void_func + ? GEN_FCN (icode) (op[0]) + : GEN_FCN (icode) (target, op[0])); + break; + case 2: + pat = (void_func + ? GEN_FCN (icode) (op[0], op[1]) + : GEN_FCN (icode) (target, op[0], op[1])); + break; + case 3: + pat = (void_func + ? GEN_FCN (icode) (op[0], op[1], op[2]) + : GEN_FCN (icode) (target, op[0], op[1], op[2])); + break; + case 4: + pat = (void_func + ? GEN_FCN (icode) (op[0], op[1], op[2], op[3]) + : GEN_FCN (icode) (target, op[0], op[1], op[2], op[3])); + break; + case 5: + pat = (void_func + ? GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]) + : GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4])); + break; + case 6: + pat = (void_func + ? GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]) + : GEN_FCN (icode) (target, op[0], op[1], + op[2], op[3], op[4], op[5])); + break; + default: + gcc_assert (MAX_BUILTIN_ARGS == 6); + gcc_unreachable (); + } - switch (nopnds) - { - case 1: - type = build_function_type_list (op[0], NULL_TREE); - break; - case 2: - type = build_function_type_list (op[0], op[1], NULL_TREE); - break; - case 3: - type = build_function_type_list (op[0], op[1], op[2], NULL_TREE); - break; - case 4: - type = build_function_type_list (op[0], op[1], op[2], op[3], - NULL_TREE); - break; - default: - gcc_unreachable (); - } + if (!pat) + return 0; - def_builtin (d->name, type, d->code); - } + emit_insn (pat); + return target; } -/* Map types for builtin functions with an explicit return type and - exactly 4 arguments. Functions with fewer than 3 arguments use - builtin_function_type. The number of quaternary built-in - functions is very small. Handle each case specially. */ +/* Create a builtin vector type with a name. Taking care not to give + the canonical type a name. */ + static tree -builtin_quaternary_function_type (machine_mode mode_ret, - machine_mode mode_arg0, - machine_mode mode_arg1, - machine_mode mode_arg2, - machine_mode mode_arg3, - enum rs6000_builtins builtin) +rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts) { - tree function_type = NULL; - - static tree v2udi_type = builtin_mode_to_type[V2DImode][1]; - static tree v16uqi_type = builtin_mode_to_type[V16QImode][1]; - static tree uchar_type = builtin_mode_to_type[QImode][1]; - - static tree xxeval_type = - build_function_type_list (v2udi_type, v2udi_type, v2udi_type, - v2udi_type, uchar_type, NULL_TREE); - - static tree xxpermx_type = - build_function_type_list (v2udi_type, v2udi_type, v2udi_type, - v16uqi_type, uchar_type, NULL_TREE); - - switch (builtin) { - - case P10V_BUILTIN_XXEVAL: - gcc_assert ((mode_ret == V2DImode) - && (mode_arg0 == V2DImode) - && (mode_arg1 == V2DImode) - && (mode_arg2 == V2DImode) - && (mode_arg3 == QImode)); - function_type = xxeval_type; - break; - - case P10V_BUILTIN_VXXPERMX: - gcc_assert ((mode_ret == V2DImode) - && (mode_arg0 == V2DImode) - && (mode_arg1 == V2DImode) - && (mode_arg2 == V16QImode) - && (mode_arg3 == QImode)); - function_type = xxpermx_type; - break; - - default: - /* A case for each quaternary built-in must be provided above. */ - gcc_unreachable (); - } + tree result = build_vector_type (elt_type, num_elts); + + /* Copy so we don't give the canonical type a name. */ + result = build_variant_type_copy (result); + + add_builtin_type (name, result); - return function_type; + return result; } -/* Map types for builtin functions with an explicit return type and up to 3 - arguments. Functions with fewer than 3 arguments use VOIDmode as the type - of the argument. */ -static tree -builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, - machine_mode mode_arg1, machine_mode mode_arg2, - enum rs6000_builtins builtin, const char *name) +void +rs6000_init_builtins (void) { - struct builtin_hash_struct h; - struct builtin_hash_struct *h2; - int num_args = 3; - int i; - tree ret_type = NULL_TREE; - tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE }; - - /* Create builtin_hash_table. */ - if (builtin_hash_table == NULL) - builtin_hash_table = hash_table::create_ggc (1500); - - h.type = NULL_TREE; - h.mode[0] = mode_ret; - h.mode[1] = mode_arg0; - h.mode[2] = mode_arg1; - h.mode[3] = mode_arg2; - h.uns_p[0] = 0; - h.uns_p[1] = 0; - h.uns_p[2] = 0; - h.uns_p[3] = 0; - - /* If the builtin is a type that produces unsigned results or takes unsigned - arguments, and it is returned as a decl for the vectorizer (such as - widening multiplies, permute), make sure the arguments and return value - are type correct. */ - switch (builtin) - { - /* unsigned 1 argument functions. */ - case CRYPTO_BUILTIN_VSBOX: - case CRYPTO_BUILTIN_VSBOX_BE: - case P8V_BUILTIN_VGBBD: - case MISC_BUILTIN_CDTBCD: - case MISC_BUILTIN_CBCDTD: - case P10V_BUILTIN_XVCVSPBF16: - case P10V_BUILTIN_XVCVBF16SPN: - case P10V_BUILTIN_MTVSRBM: - case P10V_BUILTIN_MTVSRHM: - case P10V_BUILTIN_MTVSRWM: - case P10V_BUILTIN_MTVSRDM: - case P10V_BUILTIN_MTVSRQM: - case P10V_BUILTIN_VCNTMBB: - case P10V_BUILTIN_VCNTMBH: - case P10V_BUILTIN_VCNTMBW: - case P10V_BUILTIN_VCNTMBD: - case P10V_BUILTIN_VEXPANDMB: - case P10V_BUILTIN_VEXPANDMH: - case P10V_BUILTIN_VEXPANDMW: - case P10V_BUILTIN_VEXPANDMD: - case P10V_BUILTIN_VEXPANDMQ: - h.uns_p[0] = 1; - h.uns_p[1] = 1; - break; + tree tdecl; + tree t; - /* unsigned 2 argument functions. */ - case ALTIVEC_BUILTIN_VMULEUB: - case ALTIVEC_BUILTIN_VMULEUH: - case P8V_BUILTIN_VMULEUW: - case ALTIVEC_BUILTIN_VMULOUB: - case ALTIVEC_BUILTIN_VMULOUH: - case P8V_BUILTIN_VMULOUW: - case CRYPTO_BUILTIN_VCIPHER: - case CRYPTO_BUILTIN_VCIPHER_BE: - case CRYPTO_BUILTIN_VCIPHERLAST: - case CRYPTO_BUILTIN_VCIPHERLAST_BE: - case CRYPTO_BUILTIN_VNCIPHER: - case CRYPTO_BUILTIN_VNCIPHER_BE: - case CRYPTO_BUILTIN_VNCIPHERLAST: - case CRYPTO_BUILTIN_VNCIPHERLAST_BE: - case CRYPTO_BUILTIN_VPMSUMB: - case CRYPTO_BUILTIN_VPMSUMH: - case CRYPTO_BUILTIN_VPMSUMW: - case CRYPTO_BUILTIN_VPMSUMD: - case CRYPTO_BUILTIN_VPMSUM: - case MISC_BUILTIN_ADDG6S: - case MISC_BUILTIN_DIVWEU: - case MISC_BUILTIN_DIVDEU: - case VSX_BUILTIN_UDIV_V2DI: - case ALTIVEC_BUILTIN_VMAXUB: - case ALTIVEC_BUILTIN_VMINUB: - case ALTIVEC_BUILTIN_VMAXUH: - case ALTIVEC_BUILTIN_VMINUH: - case ALTIVEC_BUILTIN_VMAXUW: - case ALTIVEC_BUILTIN_VMINUW: - case P8V_BUILTIN_VMAXUD: - case P8V_BUILTIN_VMINUD: - case ALTIVEC_BUILTIN_VAND_V16QI_UNS: - case ALTIVEC_BUILTIN_VAND_V8HI_UNS: - case ALTIVEC_BUILTIN_VAND_V4SI_UNS: - case ALTIVEC_BUILTIN_VAND_V2DI_UNS: - case ALTIVEC_BUILTIN_VANDC_V16QI_UNS: - case ALTIVEC_BUILTIN_VANDC_V8HI_UNS: - case ALTIVEC_BUILTIN_VANDC_V4SI_UNS: - case ALTIVEC_BUILTIN_VANDC_V2DI_UNS: - case ALTIVEC_BUILTIN_VNOR_V16QI_UNS: - case ALTIVEC_BUILTIN_VNOR_V8HI_UNS: - case ALTIVEC_BUILTIN_VNOR_V4SI_UNS: - case ALTIVEC_BUILTIN_VNOR_V2DI_UNS: - case ALTIVEC_BUILTIN_VOR_V16QI_UNS: - case ALTIVEC_BUILTIN_VOR_V8HI_UNS: - case ALTIVEC_BUILTIN_VOR_V4SI_UNS: - case ALTIVEC_BUILTIN_VOR_V2DI_UNS: - case ALTIVEC_BUILTIN_VXOR_V16QI_UNS: - case ALTIVEC_BUILTIN_VXOR_V8HI_UNS: - case ALTIVEC_BUILTIN_VXOR_V4SI_UNS: - case ALTIVEC_BUILTIN_VXOR_V2DI_UNS: - case P8V_BUILTIN_EQV_V16QI_UNS: - case P8V_BUILTIN_EQV_V8HI_UNS: - case P8V_BUILTIN_EQV_V4SI_UNS: - case P8V_BUILTIN_EQV_V2DI_UNS: - case P8V_BUILTIN_EQV_V1TI_UNS: - case P8V_BUILTIN_NAND_V16QI_UNS: - case P8V_BUILTIN_NAND_V8HI_UNS: - case P8V_BUILTIN_NAND_V4SI_UNS: - case P8V_BUILTIN_NAND_V2DI_UNS: - case P8V_BUILTIN_NAND_V1TI_UNS: - case P8V_BUILTIN_ORC_V16QI_UNS: - case P8V_BUILTIN_ORC_V8HI_UNS: - case P8V_BUILTIN_ORC_V4SI_UNS: - case P8V_BUILTIN_ORC_V2DI_UNS: - case P8V_BUILTIN_ORC_V1TI_UNS: - case P10_BUILTIN_CFUGED: - case P10_BUILTIN_CNTLZDM: - case P10_BUILTIN_CNTTZDM: - case P10_BUILTIN_PDEPD: - case P10_BUILTIN_PEXTD: - case P10V_BUILTIN_VCFUGED: - case P10V_BUILTIN_VCLZDM: - case P10V_BUILTIN_VCTZDM: - case P10V_BUILTIN_VGNB: - case P10V_BUILTIN_VPDEPD: - case P10V_BUILTIN_VPEXTD: - case P10V_BUILTIN_XXGENPCVM_V16QI: - case P10V_BUILTIN_XXGENPCVM_V8HI: - case P10V_BUILTIN_XXGENPCVM_V4SI: - case P10V_BUILTIN_XXGENPCVM_V2DI: - case P10V_BUILTIN_DIVEU_V4SI: - case P10V_BUILTIN_DIVEU_V2DI: - case P10V_BUILTIN_DIVEU_V1TI: - case P10V_BUILTIN_DIVU_V4SI: - case P10V_BUILTIN_DIVU_V2DI: - case P10V_BUILTIN_MODU_V1TI: - case P10V_BUILTIN_MODU_V2DI: - case P10V_BUILTIN_MODU_V4SI: - case P10V_BUILTIN_MULHU_V2DI: - case P10V_BUILTIN_MULHU_V4SI: - case P10V_BUILTIN_VMULEUD: - case P10V_BUILTIN_VMULOUD: - h.uns_p[0] = 1; - h.uns_p[1] = 1; - h.uns_p[2] = 1; - break; + if (TARGET_DEBUG_BUILTIN) + fprintf (stderr, "rs6000_init_builtins%s%s\n", + (TARGET_ALTIVEC) ? ", altivec" : "", + (TARGET_VSX) ? ", vsx" : ""); - /* unsigned 3 argument functions. */ - case ALTIVEC_BUILTIN_VPERM_16QI_UNS: - case ALTIVEC_BUILTIN_VPERM_8HI_UNS: - case ALTIVEC_BUILTIN_VPERM_4SI_UNS: - case ALTIVEC_BUILTIN_VPERM_2DI_UNS: - case ALTIVEC_BUILTIN_VSEL_16QI_UNS: - case ALTIVEC_BUILTIN_VSEL_8HI_UNS: - case ALTIVEC_BUILTIN_VSEL_4SI_UNS: - case ALTIVEC_BUILTIN_VSEL_2DI_UNS: - case VSX_BUILTIN_VPERM_16QI_UNS: - case VSX_BUILTIN_VPERM_8HI_UNS: - case VSX_BUILTIN_VPERM_4SI_UNS: - case VSX_BUILTIN_VPERM_2DI_UNS: - case VSX_BUILTIN_XXSEL_16QI_UNS: - case VSX_BUILTIN_XXSEL_8HI_UNS: - case VSX_BUILTIN_XXSEL_4SI_UNS: - case VSX_BUILTIN_XXSEL_2DI_UNS: - case CRYPTO_BUILTIN_VPERMXOR: - case CRYPTO_BUILTIN_VPERMXOR_V2DI: - case CRYPTO_BUILTIN_VPERMXOR_V4SI: - case CRYPTO_BUILTIN_VPERMXOR_V8HI: - case CRYPTO_BUILTIN_VPERMXOR_V16QI: - case CRYPTO_BUILTIN_VSHASIGMAW: - case CRYPTO_BUILTIN_VSHASIGMAD: - case CRYPTO_BUILTIN_VSHASIGMA: - case P10V_BUILTIN_VEXTRACTBL: - case P10V_BUILTIN_VEXTRACTHL: - case P10V_BUILTIN_VEXTRACTWL: - case P10V_BUILTIN_VEXTRACTDL: - case P10V_BUILTIN_VEXTRACTBR: - case P10V_BUILTIN_VEXTRACTHR: - case P10V_BUILTIN_VEXTRACTWR: - case P10V_BUILTIN_VEXTRACTDR: - case P10V_BUILTIN_VINSERTGPRBL: - case P10V_BUILTIN_VINSERTGPRHL: - case P10V_BUILTIN_VINSERTGPRWL: - case P10V_BUILTIN_VINSERTGPRDL: - case P10V_BUILTIN_VINSERTVPRBL: - case P10V_BUILTIN_VINSERTVPRHL: - case P10V_BUILTIN_VINSERTVPRWL: - case P10V_BUILTIN_VREPLACE_ELT_UV4SI: - case P10V_BUILTIN_VREPLACE_ELT_UV2DI: - case P10V_BUILTIN_VREPLACE_UN_UV4SI: - case P10V_BUILTIN_VREPLACE_UN_UV2DI: - case P10V_BUILTIN_VXXBLEND_V16QI: - case P10V_BUILTIN_VXXBLEND_V8HI: - case P10V_BUILTIN_VXXBLEND_V4SI: - case P10V_BUILTIN_VXXBLEND_V2DI: - h.uns_p[0] = 1; - h.uns_p[1] = 1; - h.uns_p[2] = 1; - h.uns_p[3] = 1; - break; + V2DI_type_node = rs6000_vector_type ("__vector long long", + long_long_integer_type_node, 2); + ptr_V2DI_type_node + = build_pointer_type (build_qualified_type (V2DI_type_node, + TYPE_QUAL_CONST)); - /* signed permute functions with unsigned char mask. */ - case ALTIVEC_BUILTIN_VPERM_16QI: - case ALTIVEC_BUILTIN_VPERM_8HI: - case ALTIVEC_BUILTIN_VPERM_4SI: - case ALTIVEC_BUILTIN_VPERM_4SF: - case ALTIVEC_BUILTIN_VPERM_2DI: - case ALTIVEC_BUILTIN_VPERM_2DF: - case VSX_BUILTIN_VPERM_16QI: - case VSX_BUILTIN_VPERM_8HI: - case VSX_BUILTIN_VPERM_4SI: - case VSX_BUILTIN_VPERM_4SF: - case VSX_BUILTIN_VPERM_2DI: - case VSX_BUILTIN_VPERM_2DF: - h.uns_p[3] = 1; - break; + V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2); + ptr_V2DF_type_node + = build_pointer_type (build_qualified_type (V2DF_type_node, + TYPE_QUAL_CONST)); - /* unsigned args, signed return. */ - case VSX_BUILTIN_XVCVUXDSP: - case VSX_BUILTIN_XVCVUXDDP_UNS: - case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF: - h.uns_p[1] = 1; - break; + V4SI_type_node = rs6000_vector_type ("__vector signed int", + intSI_type_node, 4); + ptr_V4SI_type_node + = build_pointer_type (build_qualified_type (V4SI_type_node, + TYPE_QUAL_CONST)); - /* signed args, unsigned return. */ - case VSX_BUILTIN_XVCVDPUXDS_UNS: - case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI: - case MISC_BUILTIN_UNPACK_TD: - case MISC_BUILTIN_UNPACK_V1TI: - h.uns_p[0] = 1; - break; + V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4); + ptr_V4SF_type_node + = build_pointer_type (build_qualified_type (V4SF_type_node, + TYPE_QUAL_CONST)); - /* unsigned arguments, bool return (compares). */ - case ALTIVEC_BUILTIN_VCMPEQUB: - case ALTIVEC_BUILTIN_VCMPEQUH: - case ALTIVEC_BUILTIN_VCMPEQUW: - case P8V_BUILTIN_VCMPEQUD: - case VSX_BUILTIN_CMPGE_U16QI: - case VSX_BUILTIN_CMPGE_U8HI: - case VSX_BUILTIN_CMPGE_U4SI: - case VSX_BUILTIN_CMPGE_U2DI: - case P10V_BUILTIN_CMPGE_U1TI: - case ALTIVEC_BUILTIN_VCMPGTUB: - case ALTIVEC_BUILTIN_VCMPGTUH: - case ALTIVEC_BUILTIN_VCMPGTUW: - case P8V_BUILTIN_VCMPGTUD: - case P10V_BUILTIN_VCMPGTUT: - case P10V_BUILTIN_VCMPEQUT: - h.uns_p[1] = 1; - h.uns_p[2] = 1; - break; + V8HI_type_node = rs6000_vector_type ("__vector signed short", + intHI_type_node, 8); + ptr_V8HI_type_node + = build_pointer_type (build_qualified_type (V8HI_type_node, + TYPE_QUAL_CONST)); - /* unsigned arguments for 128-bit pack instructions. */ - case MISC_BUILTIN_PACK_TD: - case MISC_BUILTIN_PACK_V1TI: - h.uns_p[1] = 1; - h.uns_p[2] = 1; - break; + V16QI_type_node = rs6000_vector_type ("__vector signed char", + intQI_type_node, 16); + ptr_V16QI_type_node + = build_pointer_type (build_qualified_type (V16QI_type_node, + TYPE_QUAL_CONST)); - /* unsigned second arguments (vector shift right). */ - case ALTIVEC_BUILTIN_VSRB: - case ALTIVEC_BUILTIN_VSRH: - case ALTIVEC_BUILTIN_VSRW: - case P8V_BUILTIN_VSRD: - /* Vector splat immediate insert */ - case P10V_BUILTIN_VXXSPLTI32DX_V4SI: - case P10V_BUILTIN_VXXSPLTI32DX_V4SF: - h.uns_p[2] = 1; - break; + unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char", + unsigned_intQI_type_node, 16); + ptr_unsigned_V16QI_type_node + = build_pointer_type (build_qualified_type (unsigned_V16QI_type_node, + TYPE_QUAL_CONST)); - case VSX_BUILTIN_LXVP: - h.uns_p[0] = 1; - h.uns_p[2] = 1; - break; + unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short", + unsigned_intHI_type_node, 8); + ptr_unsigned_V8HI_type_node + = build_pointer_type (build_qualified_type (unsigned_V8HI_type_node, + TYPE_QUAL_CONST)); - case VSX_BUILTIN_STXVP: - h.uns_p[1] = 1; - h.uns_p[3] = 1; - break; + unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int", + unsigned_intSI_type_node, 4); + ptr_unsigned_V4SI_type_node + = build_pointer_type (build_qualified_type (unsigned_V4SI_type_node, + TYPE_QUAL_CONST)); - default: - break; + unsigned_V2DI_type_node + = rs6000_vector_type ("__vector unsigned long long", + long_long_unsigned_type_node, 2); + + ptr_unsigned_V2DI_type_node + = build_pointer_type (build_qualified_type (unsigned_V2DI_type_node, + TYPE_QUAL_CONST)); + + opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4); + + const_str_type_node + = build_pointer_type (build_qualified_type (char_type_node, + TYPE_QUAL_CONST)); + + /* We use V1TI mode as a special container to hold __int128_t items that + must live in VSX registers. */ + if (intTI_type_node) + { + V1TI_type_node = rs6000_vector_type ("__vector __int128", + intTI_type_node, 1); + ptr_V1TI_type_node + = build_pointer_type (build_qualified_type (V1TI_type_node, + TYPE_QUAL_CONST)); + unsigned_V1TI_type_node + = rs6000_vector_type ("__vector unsigned __int128", + unsigned_intTI_type_node, 1); + ptr_unsigned_V1TI_type_node + = build_pointer_type (build_qualified_type (unsigned_V1TI_type_node, + TYPE_QUAL_CONST)); } - /* Figure out how many args are present. */ - while (num_args > 0 && h.mode[num_args] == VOIDmode) - num_args--; + /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' + types, especially in C++ land. Similarly, 'vector pixel' is distinct from + 'vector unsigned short'. */ + + bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node); + bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node); + bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node); + bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node); + pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node); - ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]]; - if (!ret_type && h.uns_p[0]) - ret_type = builtin_mode_to_type[h.mode[0]][0]; + long_integer_type_internal_node = long_integer_type_node; + long_unsigned_type_internal_node = long_unsigned_type_node; + long_long_integer_type_internal_node = long_long_integer_type_node; + long_long_unsigned_type_internal_node = long_long_unsigned_type_node; + intQI_type_internal_node = intQI_type_node; + uintQI_type_internal_node = unsigned_intQI_type_node; + intHI_type_internal_node = intHI_type_node; + uintHI_type_internal_node = unsigned_intHI_type_node; + intSI_type_internal_node = intSI_type_node; + uintSI_type_internal_node = unsigned_intSI_type_node; + intDI_type_internal_node = intDI_type_node; + uintDI_type_internal_node = unsigned_intDI_type_node; + intTI_type_internal_node = intTI_type_node; + uintTI_type_internal_node = unsigned_intTI_type_node; + float_type_internal_node = float_type_node; + double_type_internal_node = double_type_node; + long_double_type_internal_node = long_double_type_node; + dfloat64_type_internal_node = dfloat64_type_node; + dfloat128_type_internal_node = dfloat128_type_node; + void_type_internal_node = void_type_node; - /* If the required decimal float type has been disabled, - then return NULL_TREE. */ - if (!ret_type && DECIMAL_FLOAT_MODE_P (h.mode[0])) - return NULL_TREE; + ptr_intQI_type_node + = build_pointer_type (build_qualified_type (intQI_type_internal_node, + TYPE_QUAL_CONST)); + ptr_uintQI_type_node + = build_pointer_type (build_qualified_type (uintQI_type_internal_node, + TYPE_QUAL_CONST)); + ptr_intHI_type_node + = build_pointer_type (build_qualified_type (intHI_type_internal_node, + TYPE_QUAL_CONST)); + ptr_uintHI_type_node + = build_pointer_type (build_qualified_type (uintHI_type_internal_node, + TYPE_QUAL_CONST)); + ptr_intSI_type_node + = build_pointer_type (build_qualified_type (intSI_type_internal_node, + TYPE_QUAL_CONST)); + ptr_uintSI_type_node + = build_pointer_type (build_qualified_type (uintSI_type_internal_node, + TYPE_QUAL_CONST)); + ptr_intDI_type_node + = build_pointer_type (build_qualified_type (intDI_type_internal_node, + TYPE_QUAL_CONST)); + ptr_uintDI_type_node + = build_pointer_type (build_qualified_type (uintDI_type_internal_node, + TYPE_QUAL_CONST)); + ptr_intTI_type_node + = build_pointer_type (build_qualified_type (intTI_type_internal_node, + TYPE_QUAL_CONST)); + ptr_uintTI_type_node + = build_pointer_type (build_qualified_type (uintTI_type_internal_node, + TYPE_QUAL_CONST)); - if (!ret_type) - fatal_error (input_location, - "internal error: builtin function %qs had an unexpected " - "return type %qs", name, GET_MODE_NAME (h.mode[0])); + t = build_qualified_type (long_integer_type_internal_node, TYPE_QUAL_CONST); + ptr_long_integer_type_node = build_pointer_type (t); - for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++) - arg_type[i] = NULL_TREE; + t = build_qualified_type (long_unsigned_type_internal_node, TYPE_QUAL_CONST); + ptr_long_unsigned_type_node = build_pointer_type (t); - for (i = 0; i < num_args; i++) + ptr_float_type_node + = build_pointer_type (build_qualified_type (float_type_internal_node, + TYPE_QUAL_CONST)); + ptr_double_type_node + = build_pointer_type (build_qualified_type (double_type_internal_node, + TYPE_QUAL_CONST)); + ptr_long_double_type_node + = build_pointer_type (build_qualified_type (long_double_type_internal_node, + TYPE_QUAL_CONST)); + if (dfloat64_type_node) { - int m = (int) h.mode[i+1]; - int uns_p = h.uns_p[i+1]; - - arg_type[i] = builtin_mode_to_type[m][uns_p]; - if (!arg_type[i] && uns_p) - arg_type[i] = builtin_mode_to_type[m][0]; - - /* If the required decimal float type has been disabled, - then return NULL_TREE. */ - if (!arg_type[i] && DECIMAL_FLOAT_MODE_P (m)) - return NULL_TREE; - - if (!arg_type[i]) - fatal_error (input_location, - "internal error: builtin function %qs, argument %d " - "had unexpected argument type %qs", name, i, - GET_MODE_NAME (m)); + t = build_qualified_type (dfloat64_type_internal_node, TYPE_QUAL_CONST); + ptr_dfloat64_type_node = build_pointer_type (t); } + else + ptr_dfloat64_type_node = NULL; - builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT); - if (*found == NULL) + if (dfloat128_type_node) { - h2 = ggc_alloc (); - *h2 = h; - *found = h2; - - h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1], - arg_type[2], NULL_TREE); + t = build_qualified_type (dfloat128_type_internal_node, TYPE_QUAL_CONST); + ptr_dfloat128_type_node = build_pointer_type (t); } + else + ptr_dfloat128_type_node = NULL; - return (*found)->type; -} + t = build_qualified_type (long_long_integer_type_internal_node, + TYPE_QUAL_CONST); + ptr_long_long_integer_type_node = build_pointer_type (t); -static void -rs6000_common_init_builtins (void) -{ - const struct builtin_description *d; - size_t i; + t = build_qualified_type (long_long_unsigned_type_internal_node, + TYPE_QUAL_CONST); + ptr_long_long_unsigned_type_node = build_pointer_type (t); - tree opaque_ftype_opaque = NULL_TREE; - tree opaque_ftype_opaque_opaque = NULL_TREE; - tree opaque_ftype_opaque_opaque_opaque = NULL_TREE; - tree opaque_ftype_opaque_opaque_opaque_opaque = NULL_TREE; - HOST_WIDE_INT builtin_mask = rs6000_builtin_mask; + /* 128-bit floating point support. KFmode is IEEE 128-bit floating point. + IFmode is the IBM extended 128-bit format that is a pair of doubles. + TFmode will be either IEEE 128-bit floating point or the IBM double-double + format that uses a pair of doubles, depending on the switches and + defaults. - /* Create Altivec and VSX builtins on machines with at least the - general purpose extensions (970 and newer) to allow the use of - the target attribute. */ + If we don't support for either 128-bit IBM double double or IEEE 128-bit + floating point, we need make sure the type is non-zero or else self-test + fails during bootstrap. - if (TARGET_EXTRA_BUILTINS) - builtin_mask |= RS6000_BTM_COMMON; + Always create __ibm128 as a separate type, even if the current long double + format is IBM extended double. - /* Add the quaternary operators. */ - d = bdesc_4arg; - for (i = 0; i < ARRAY_SIZE (bdesc_4arg); i++, d++) + For IEEE 128-bit floating point, always create the type __ieee128. If the + user used -mfloat128, rs6000-c.c will create a define from __float128 to + __ieee128. */ + if (TARGET_FLOAT128_TYPE) { - tree type; - HOST_WIDE_INT mask = d->mask; + if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128) + ibm128_float_type_node = long_double_type_node; + else + { + ibm128_float_type_node = make_node (REAL_TYPE); + TYPE_PRECISION (ibm128_float_type_node) = 128; + SET_TYPE_MODE (ibm128_float_type_node, IFmode); + layout_type (ibm128_float_type_node); + } + t = build_qualified_type (ibm128_float_type_node, TYPE_QUAL_CONST); + ptr_ibm128_float_type_node = build_pointer_type (t); + lang_hooks.types.register_builtin_type (ibm128_float_type_node, + "__ibm128"); + + if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128) + ieee128_float_type_node = long_double_type_node; + else + ieee128_float_type_node = float128_type_node; + t = build_qualified_type (ieee128_float_type_node, TYPE_QUAL_CONST); + ptr_ieee128_float_type_node = build_pointer_type (t); + lang_hooks.types.register_builtin_type (ieee128_float_type_node, + "__ieee128"); + } + + else + ieee128_float_type_node = ibm128_float_type_node = long_double_type_node; + + /* Vector pair and vector quad support. */ + vector_pair_type_node = make_node (OPAQUE_TYPE); + SET_TYPE_MODE (vector_pair_type_node, OOmode); + TYPE_SIZE (vector_pair_type_node) = bitsize_int (GET_MODE_BITSIZE (OOmode)); + TYPE_PRECISION (vector_pair_type_node) = GET_MODE_BITSIZE (OOmode); + TYPE_SIZE_UNIT (vector_pair_type_node) = size_int (GET_MODE_SIZE (OOmode)); + SET_TYPE_ALIGN (vector_pair_type_node, 256); + TYPE_USER_ALIGN (vector_pair_type_node) = 0; + lang_hooks.types.register_builtin_type (vector_pair_type_node, + "__vector_pair"); + t = build_qualified_type (vector_pair_type_node, TYPE_QUAL_CONST); + ptr_vector_pair_type_node = build_pointer_type (t); + + vector_quad_type_node = make_node (OPAQUE_TYPE); + SET_TYPE_MODE (vector_quad_type_node, XOmode); + TYPE_SIZE (vector_quad_type_node) = bitsize_int (GET_MODE_BITSIZE (XOmode)); + TYPE_PRECISION (vector_quad_type_node) = GET_MODE_BITSIZE (XOmode); + TYPE_SIZE_UNIT (vector_quad_type_node) = size_int (GET_MODE_SIZE (XOmode)); + SET_TYPE_ALIGN (vector_quad_type_node, 512); + TYPE_USER_ALIGN (vector_quad_type_node) = 0; + lang_hooks.types.register_builtin_type (vector_quad_type_node, + "__vector_quad"); + t = build_qualified_type (vector_quad_type_node, TYPE_QUAL_CONST); + ptr_vector_quad_type_node = build_pointer_type (t); - if ((mask & builtin_mask) != mask) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, skip quaternary %s\n", d->name); - continue; - } + /* Initialize the modes for builtin_function_type, mapping a machine mode to + tree type node. */ + builtin_mode_to_type[QImode][0] = integer_type_node; + builtin_mode_to_type[QImode][1] = unsigned_intSI_type_node; + builtin_mode_to_type[HImode][0] = integer_type_node; + builtin_mode_to_type[HImode][1] = unsigned_intSI_type_node; + builtin_mode_to_type[SImode][0] = intSI_type_node; + builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node; + builtin_mode_to_type[DImode][0] = intDI_type_node; + builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node; + builtin_mode_to_type[TImode][0] = intTI_type_node; + builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node; + builtin_mode_to_type[SFmode][0] = float_type_node; + builtin_mode_to_type[DFmode][0] = double_type_node; + builtin_mode_to_type[IFmode][0] = ibm128_float_type_node; + builtin_mode_to_type[KFmode][0] = ieee128_float_type_node; + builtin_mode_to_type[TFmode][0] = long_double_type_node; + builtin_mode_to_type[DDmode][0] = dfloat64_type_node; + builtin_mode_to_type[TDmode][0] = dfloat128_type_node; + builtin_mode_to_type[V1TImode][0] = V1TI_type_node; + builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node; + builtin_mode_to_type[V2DImode][0] = V2DI_type_node; + builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node; + builtin_mode_to_type[V2DFmode][0] = V2DF_type_node; + builtin_mode_to_type[V4SImode][0] = V4SI_type_node; + builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node; + builtin_mode_to_type[V4SFmode][0] = V4SF_type_node; + builtin_mode_to_type[V8HImode][0] = V8HI_type_node; + builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node; + builtin_mode_to_type[V16QImode][0] = V16QI_type_node; + builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node; + builtin_mode_to_type[OOmode][1] = vector_pair_type_node; + builtin_mode_to_type[XOmode][1] = vector_quad_type_node; - if (rs6000_overloaded_builtin_p (d->code)) - { - type = opaque_ftype_opaque_opaque_opaque_opaque; - if (!type) - type = opaque_ftype_opaque_opaque_opaque_opaque - = build_function_type_list (opaque_V4SI_type_node, - opaque_V4SI_type_node, - opaque_V4SI_type_node, - opaque_V4SI_type_node, - opaque_V4SI_type_node, - NULL_TREE); - } - else - { - enum insn_code icode = d->icode; - if (d->name == 0) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, bdesc_4arg[%ld] no name\n", - (long) i); - continue; - } + tdecl = add_builtin_type ("__bool char", bool_char_type_node); + TYPE_NAME (bool_char_type_node) = tdecl; - if (icode == CODE_FOR_nothing) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, - "rs6000_builtin, skip quaternary %s (no code)\n", - d->name); - continue; - } + tdecl = add_builtin_type ("__bool short", bool_short_type_node); + TYPE_NAME (bool_short_type_node) = tdecl; - type = - builtin_quaternary_function_type (insn_data[icode].operand[0].mode, - insn_data[icode].operand[1].mode, - insn_data[icode].operand[2].mode, - insn_data[icode].operand[3].mode, - insn_data[icode].operand[4].mode, - d->code); - } - def_builtin (d->name, type, d->code); - } + tdecl = add_builtin_type ("__bool int", bool_int_type_node); + TYPE_NAME (bool_int_type_node) = tdecl; - /* Add the ternary operators. */ - d = bdesc_3arg; - for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) - { - tree type; - HOST_WIDE_INT mask = d->mask; + tdecl = add_builtin_type ("__pixel", pixel_type_node); + TYPE_NAME (pixel_type_node) = tdecl; - if ((mask & builtin_mask) != mask) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name); - continue; - } + bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char", + bool_char_type_node, 16); + ptr_bool_V16QI_type_node + = build_pointer_type (build_qualified_type (bool_V16QI_type_node, + TYPE_QUAL_CONST)); - if (rs6000_overloaded_builtin_p (d->code)) - { - if (! (type = opaque_ftype_opaque_opaque_opaque)) - type = opaque_ftype_opaque_opaque_opaque - = build_function_type_list (opaque_V4SI_type_node, - opaque_V4SI_type_node, - opaque_V4SI_type_node, - opaque_V4SI_type_node, - NULL_TREE); - } - else - { - enum insn_code icode = d->icode; - if (d->name == 0) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n", - (long unsigned)i); + bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short", + bool_short_type_node, 8); + ptr_bool_V8HI_type_node + = build_pointer_type (build_qualified_type (bool_V8HI_type_node, + TYPE_QUAL_CONST)); - continue; - } + bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int", + bool_int_type_node, 4); + ptr_bool_V4SI_type_node + = build_pointer_type (build_qualified_type (bool_V4SI_type_node, + TYPE_QUAL_CONST)); - if (icode == CODE_FOR_nothing) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n", - d->name); + bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 + ? "__vector __bool long" + : "__vector __bool long long", + bool_long_long_type_node, 2); + ptr_bool_V2DI_type_node + = build_pointer_type (build_qualified_type (bool_V2DI_type_node, + TYPE_QUAL_CONST)); - continue; - } + bool_V1TI_type_node = rs6000_vector_type ("__vector __bool __int128", + intTI_type_node, 1); + ptr_bool_V1TI_type_node + = build_pointer_type (build_qualified_type (bool_V1TI_type_node, + TYPE_QUAL_CONST)); - type = builtin_function_type (insn_data[icode].operand[0].mode, - insn_data[icode].operand[1].mode, - insn_data[icode].operand[2].mode, - insn_data[icode].operand[3].mode, - d->code, d->name); - } + pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel", + pixel_type_node, 8); + ptr_pixel_V8HI_type_node + = build_pointer_type (build_qualified_type (pixel_V8HI_type_node, + TYPE_QUAL_CONST)); + pcvoid_type_node + = build_pointer_type (build_qualified_type (void_type_node, + TYPE_QUAL_CONST)); - def_builtin (d->name, type, d->code); - } + /* Execute the autogenerated initialization code for builtins. */ + rs6000_init_generated_builtins (); - /* Add the binary operators. */ - d = bdesc_2arg; - for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) + if (TARGET_DEBUG_BUILTIN) { - machine_mode mode0, mode1, mode2; - tree type; - HOST_WIDE_INT mask = d->mask; - - if ((mask & builtin_mask) != mask) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name); - continue; - } - - if (rs6000_overloaded_builtin_p (d->code)) - { - const struct altivec_builtin_types *desc; - - /* Verify the builtin we are overloading has already been defined. */ - type = NULL_TREE; - for (desc = altivec_overloaded_builtins; - desc->code != RS6000_BUILTIN_NONE; desc++) - if (desc->code == d->code - && rs6000_builtin_decls[(int)desc->overloaded_code]) - { - if (! (type = opaque_ftype_opaque_opaque)) - type = opaque_ftype_opaque_opaque - = build_function_type_list (opaque_V4SI_type_node, - opaque_V4SI_type_node, - opaque_V4SI_type_node, - NULL_TREE); - break; - } - } - else + fprintf (stderr, "\nAutogenerated built-in functions:\n\n"); + for (int i = 1; i < (int) RS6000_BIF_MAX; i++) { - enum insn_code icode = d->icode; - if (d->name == 0) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n", - (long unsigned)i); - - continue; - } - - if (icode == CODE_FOR_nothing) + bif_enable e = rs6000_builtin_info_x[i].enable; + if (e == ENB_P5 && !TARGET_POPCNTB) + continue; + if (e == ENB_P6 && !TARGET_CMPB) + continue; + if (e == ENB_P6_64 && !(TARGET_CMPB && TARGET_POWERPC64)) + continue; + if (e == ENB_ALTIVEC && !TARGET_ALTIVEC) + continue; + if (e == ENB_VSX && !TARGET_VSX) + continue; + if (e == ENB_P7 && !TARGET_POPCNTD) + continue; + if (e == ENB_P7_64 && !(TARGET_POPCNTD && TARGET_POWERPC64)) + continue; + if (e == ENB_P8 && !TARGET_DIRECT_MOVE) + continue; + if (e == ENB_P8V && !TARGET_P8_VECTOR) + continue; + if (e == ENB_P9 && !TARGET_MODULO) + continue; + if (e == ENB_P9_64 && !(TARGET_MODULO && TARGET_POWERPC64)) + continue; + if (e == ENB_P9V && !TARGET_P9_VECTOR) + continue; + if (e == ENB_IEEE128_HW && !TARGET_FLOAT128_HW) + continue; + if (e == ENB_DFP && !TARGET_DFP) + continue; + if (e == ENB_CRYPTO && !TARGET_CRYPTO) + continue; + if (e == ENB_HTM && !TARGET_HTM) + continue; + if (e == ENB_P10 && !TARGET_POWER10) + continue; + if (e == ENB_P10_64 && !(TARGET_POWER10 && TARGET_POWERPC64)) + continue; + if (e == ENB_MMA && !TARGET_MMA) + continue; + tree fntype = rs6000_builtin_info_x[i].fntype; + tree t = TREE_TYPE (fntype); + fprintf (stderr, "%s %s (", rs6000_type_string (t), + rs6000_builtin_info_x[i].bifname); + t = TYPE_ARG_TYPES (fntype); + while (t && TREE_VALUE (t) != void_type_node) { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n", - d->name); - - continue; + fprintf (stderr, "%s", + rs6000_type_string (TREE_VALUE (t))); + t = TREE_CHAIN (t); + if (t && TREE_VALUE (t) != void_type_node) + fprintf (stderr, ", "); } - - mode0 = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; - mode2 = insn_data[icode].operand[2].mode; - - type = builtin_function_type (mode0, mode1, mode2, VOIDmode, - d->code, d->name); + fprintf (stderr, "); %s [%4d]\n", + rs6000_builtin_info_x[i].attr_string, (int) i); } + fprintf (stderr, "\nEnd autogenerated built-in functions.\n\n\n"); + } - def_builtin (d->name, type, d->code); - } - - /* Add the simple unary operators. */ - d = bdesc_1arg; - for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) + if (TARGET_XCOFF) { - machine_mode mode0, mode1; - tree type; - HOST_WIDE_INT mask = d->mask; - - if ((mask & builtin_mask) != mask) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name); - continue; - } + /* AIX libm provides clog as __clog. */ + if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE) + set_user_assembler_name (tdecl, "__clog"); - if (rs6000_overloaded_builtin_p (d->code)) + /* When long double is 64 bit, some long double builtins of libc + functions (like __builtin_frexpl) must call the double version + (frexp) not the long double version (frexpl) that expects a 128 bit + argument. */ + if (! TARGET_LONG_DOUBLE_128) { - if (! (type = opaque_ftype_opaque)) - type = opaque_ftype_opaque - = build_function_type_list (opaque_V4SI_type_node, - opaque_V4SI_type_node, - NULL_TREE); + if ((tdecl = builtin_decl_explicit (BUILT_IN_FMODL)) != NULL_TREE) + set_user_assembler_name (tdecl, "fmod"); + if ((tdecl = builtin_decl_explicit (BUILT_IN_FREXPL)) != NULL_TREE) + set_user_assembler_name (tdecl, "frexp"); + if ((tdecl = builtin_decl_explicit (BUILT_IN_LDEXPL)) != NULL_TREE) + set_user_assembler_name (tdecl, "ldexp"); + if ((tdecl = builtin_decl_explicit (BUILT_IN_MODFL)) != NULL_TREE) + set_user_assembler_name (tdecl, "modf"); } - else - { - enum insn_code icode = d->icode; - if (d->name == 0) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n", - (long unsigned)i); + } - continue; - } + altivec_builtin_mask_for_load + = rs6000_builtin_decls_x[RS6000_BIF_MASK_FOR_LOAD]; - if (icode == CODE_FOR_nothing) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n", - d->name); +#ifdef SUBTARGET_INIT_BUILTINS + SUBTARGET_INIT_BUILTINS; +#endif - continue; - } + return; +} - mode0 = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; +static tree +rs6000_new_builtin_decl (unsigned code, bool /* initialize_p */) +{ + rs6000_gen_builtins fcode = (rs6000_gen_builtins) code; - type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode, - d->code, d->name); - } + if (fcode >= RS6000_OVLD_MAX) + return error_mark_node; - def_builtin (d->name, type, d->code); - } + return rs6000_builtin_decls_x[code]; +} - /* Add the simple no-argument operators. */ - d = bdesc_0arg; - for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++) - { - machine_mode mode0; - tree type; - HOST_WIDE_INT mask = d->mask; +/* Returns the rs6000 builtin decl for CODE. Note that we don't check + the builtin mask here since there could be some #pragma/attribute + target functions and the rs6000_builtin_mask could be wrong when + this checking happens, though it will be updated properly later. */ - if ((mask & builtin_mask) != mask) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name); - continue; - } - if (rs6000_overloaded_builtin_p (d->code)) - { - if (!opaque_ftype_opaque) - opaque_ftype_opaque - = build_function_type_list (opaque_V4SI_type_node, NULL_TREE); - type = opaque_ftype_opaque; - } - else - { - enum insn_code icode = d->icode; - if (d->name == 0) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n", - (long unsigned) i); - continue; - } - if (icode == CODE_FOR_nothing) - { - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, - "rs6000_builtin, skip no-argument %s (no code)\n", - d->name); - continue; - } - mode0 = insn_data[icode].operand[0].mode; - type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode, - d->code, d->name); - } - def_builtin (d->name, type, d->code); - } +tree +rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) +{ + return rs6000_new_builtin_decl (code, initialize_p); } /* Return the internal arg pointer used for function incoming diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c index 856770c1..0034fe0 100644 --- a/gcc/config/rs6000/rs6000-gen-builtins.c +++ b/gcc/config/rs6000/rs6000-gen-builtins.c @@ -2492,7 +2492,6 @@ write_header_file (void) fprintf (header_file, "#ifndef _RS6000_BUILTINS_H\n"); fprintf (header_file, "#define _RS6000_BUILTINS_H 1\n\n"); - fprintf (header_file, "extern int new_builtins_are_live;\n\n"); write_decls (); @@ -2691,68 +2690,64 @@ write_init_bif_table (void) || strstr (bifs[i].fndecl, "dd") != NULL || strstr (bifs[i].fndecl, "td") != NULL); - fprintf (init_file, - " if (new_builtins_are_live)\n"); - fprintf (init_file, " {\n"); - if (tf_found) { - fprintf (init_file, " if (float128_type_node)\n"); - fprintf (init_file, " {\n"); + fprintf (init_file, " if (float128_type_node)\n"); + fprintf (init_file, " {\n"); } else if (dfp_found) { - fprintf (init_file, " if (dfloat64_type_node)\n"); - fprintf (init_file, " {\n"); + fprintf (init_file, " if (dfloat64_type_node)\n"); + fprintf (init_file, " {\n"); } fprintf (init_file, - " rs6000_builtin_decls_x[(int)RS6000_BIF_%s] = t\n", + " rs6000_builtin_decls_x[(int)RS6000_BIF_%s] = t\n", bifs[i].idname); fprintf (init_file, - " = add_builtin_function (\"%s\",\n", + " = add_builtin_function (\"%s\",\n", bifs[i].proto.bifname); fprintf (init_file, - " %s,\n", + " %s,\n", bifs[i].fndecl); fprintf (init_file, - " (int)RS6000_BIF_%s," + " (int)RS6000_BIF_%s," " BUILT_IN_MD,\n", bifs[i].idname); fprintf (init_file, - " NULL, NULL_TREE);\n"); + " NULL, NULL_TREE);\n"); if (bifs[i].kind == FNK_CONST) { - fprintf (init_file, " TREE_READONLY (t) = 1;\n"); - fprintf (init_file, " TREE_NOTHROW (t) = 1;\n"); + fprintf (init_file, " TREE_READONLY (t) = 1;\n"); + fprintf (init_file, " TREE_NOTHROW (t) = 1;\n"); } else if (bifs[i].kind == FNK_PURE) { - fprintf (init_file, " DECL_PURE_P (t) = 1;\n"); - fprintf (init_file, " TREE_NOTHROW (t) = 1;\n"); + fprintf (init_file, " DECL_PURE_P (t) = 1;\n"); + fprintf (init_file, " TREE_NOTHROW (t) = 1;\n"); } else if (bifs[i].kind == FNK_FPMATH) { - fprintf (init_file, " TREE_NOTHROW (t) = 1;\n"); - fprintf (init_file, " if (flag_rounding_math)\n"); - fprintf (init_file, " {\n"); - fprintf (init_file, " DECL_PURE_P (t) = 1;\n"); - fprintf (init_file, " DECL_IS_NOVOPS (t) = 1;\n"); - fprintf (init_file, " }\n"); - fprintf (init_file, " else\n"); - fprintf (init_file, " TREE_READONLY (t) = 1;\n"); + fprintf (init_file, " TREE_NOTHROW (t) = 1;\n"); + fprintf (init_file, " if (flag_rounding_math)\n"); + fprintf (init_file, " {\n"); + fprintf (init_file, " DECL_PURE_P (t) = 1;\n"); + fprintf (init_file, " DECL_IS_NOVOPS (t) = 1;\n"); + fprintf (init_file, " }\n"); + fprintf (init_file, " else\n"); + fprintf (init_file, " TREE_READONLY (t) = 1;\n"); } if (tf_found || dfp_found) { - fprintf (init_file, " }\n"); - fprintf (init_file, " else\n"); - fprintf (init_file, " {\n"); - fprintf (init_file, " rs6000_builtin_decls_x" + fprintf (init_file, " }\n"); + fprintf (init_file, " else\n"); + fprintf (init_file, " {\n"); + fprintf (init_file, " rs6000_builtin_decls_x" "[(int)RS6000_BIF_%s] = NULL_TREE;\n", bifs[i].idname); - fprintf (init_file, " }\n"); + fprintf (init_file, " }\n"); } - fprintf (init_file, " }\n\n"); + fprintf (init_file, "\n"); } } @@ -2789,41 +2784,37 @@ write_init_ovld_table (void) || strstr (ovlds[i].fndecl, "dd") != NULL || strstr (ovlds[i].fndecl, "td") != NULL); - fprintf (init_file, - " if (new_builtins_are_live)\n"); - fprintf (init_file, " {\n"); - if (tf_found) { - fprintf (init_file, " if (float128_type_node)\n"); - fprintf (init_file, " {\n"); + fprintf (init_file, " if (float128_type_node)\n"); + fprintf (init_file, " {\n"); } else if (dfp_found) { - fprintf (init_file, " if (dfloat64_type_node)\n"); - fprintf (init_file, " {\n"); + fprintf (init_file, " if (dfloat64_type_node)\n"); + fprintf (init_file, " {\n"); } fprintf (init_file, - " rs6000_builtin_decls_x[(int)RS6000_OVLD_%s] = t\n", + " rs6000_builtin_decls_x[(int)RS6000_OVLD_%s] = t\n", stanza->stanza_id); fprintf (init_file, - " = add_builtin_function (\"%s\",\n", + " = add_builtin_function (\"%s\",\n", stanza->intern_name); fprintf (init_file, - " %s,\n", + " %s,\n", ovlds[i].fndecl); fprintf (init_file, - " (int)RS6000_OVLD_%s," + " (int)RS6000_OVLD_%s," " BUILT_IN_MD,\n", stanza->stanza_id); fprintf (init_file, - " NULL, NULL_TREE);\n"); + " NULL, NULL_TREE);\n"); if (tf_found || dfp_found) - fprintf (init_file, " }\n"); + fprintf (init_file, " }\n"); - fprintf (init_file, " }\n\n"); + fprintf (init_file, "\n"); fprintf (init_file, " rs6000_overload_info[RS6000_OVLD_%s - base]" @@ -2854,8 +2845,6 @@ write_init_file (void) fprintf (init_file, "#include \"rs6000-builtins.h\"\n"); fprintf (init_file, "\n"); - fprintf (init_file, "int new_builtins_are_live = 1;\n\n"); - fprintf (init_file, "tree rs6000_builtin_decls_x[RS6000_OVLD_MAX];\n\n"); write_bif_static_init (); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 5e12998..70df511 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -5929,132 +5929,7 @@ static tree rs6000_builtin_vectorized_function (unsigned int fn, tree type_out, tree type_in) { - machine_mode in_mode, out_mode; - int in_n, out_n; - - if (new_builtins_are_live) - return rs6000_new_builtin_vectorized_function (fn, type_out, type_in); - - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n", - combined_fn_name (combined_fn (fn)), - GET_MODE_NAME (TYPE_MODE (type_out)), - GET_MODE_NAME (TYPE_MODE (type_in))); - - if (TREE_CODE (type_out) != VECTOR_TYPE - || TREE_CODE (type_in) != VECTOR_TYPE) - return NULL_TREE; - - out_mode = TYPE_MODE (TREE_TYPE (type_out)); - out_n = TYPE_VECTOR_SUBPARTS (type_out); - in_mode = TYPE_MODE (TREE_TYPE (type_in)); - in_n = TYPE_VECTOR_SUBPARTS (type_in); - - switch (fn) - { - CASE_CFN_COPYSIGN: - if (VECTOR_UNIT_VSX_P (V2DFmode) - && out_mode == DFmode && out_n == 2 - && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP]; - if (VECTOR_UNIT_VSX_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP]; - if (VECTOR_UNIT_ALTIVEC_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF]; - break; - CASE_CFN_CEIL: - if (VECTOR_UNIT_VSX_P (V2DFmode) - && out_mode == DFmode && out_n == 2 - && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP]; - if (VECTOR_UNIT_VSX_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP]; - if (VECTOR_UNIT_ALTIVEC_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP]; - break; - CASE_CFN_FLOOR: - if (VECTOR_UNIT_VSX_P (V2DFmode) - && out_mode == DFmode && out_n == 2 - && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM]; - if (VECTOR_UNIT_VSX_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM]; - if (VECTOR_UNIT_ALTIVEC_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM]; - break; - CASE_CFN_FMA: - if (VECTOR_UNIT_VSX_P (V2DFmode) - && out_mode == DFmode && out_n == 2 - && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP]; - if (VECTOR_UNIT_VSX_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP]; - if (VECTOR_UNIT_ALTIVEC_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP]; - break; - CASE_CFN_TRUNC: - if (VECTOR_UNIT_VSX_P (V2DFmode) - && out_mode == DFmode && out_n == 2 - && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ]; - if (VECTOR_UNIT_VSX_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ]; - if (VECTOR_UNIT_ALTIVEC_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ]; - break; - CASE_CFN_NEARBYINT: - if (VECTOR_UNIT_VSX_P (V2DFmode) - && flag_unsafe_math_optimizations - && out_mode == DFmode && out_n == 2 - && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI]; - if (VECTOR_UNIT_VSX_P (V4SFmode) - && flag_unsafe_math_optimizations - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI]; - break; - CASE_CFN_RINT: - if (VECTOR_UNIT_VSX_P (V2DFmode) - && !flag_trapping_math - && out_mode == DFmode && out_n == 2 - && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC]; - if (VECTOR_UNIT_VSX_P (V4SFmode) - && !flag_trapping_math - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC]; - break; - default: - break; - } - - /* Generate calls to libmass if appropriate. */ - if (rs6000_veclib_handler) - return rs6000_veclib_handler (combined_fn (fn), type_out, type_in); - - return NULL_TREE; + return rs6000_new_builtin_vectorized_function (fn, type_out, type_in); } /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */ @@ -6063,113 +5938,7 @@ static tree rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out, tree type_in) { - machine_mode in_mode, out_mode; - int in_n, out_n; - - if (new_builtins_are_live) - return rs6000_new_builtin_md_vectorized_function (fndecl, type_out, - type_in); - - if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n", - IDENTIFIER_POINTER (DECL_NAME (fndecl)), - GET_MODE_NAME (TYPE_MODE (type_out)), - GET_MODE_NAME (TYPE_MODE (type_in))); - - if (TREE_CODE (type_out) != VECTOR_TYPE - || TREE_CODE (type_in) != VECTOR_TYPE) - return NULL_TREE; - - out_mode = TYPE_MODE (TREE_TYPE (type_out)); - out_n = TYPE_VECTOR_SUBPARTS (type_out); - in_mode = TYPE_MODE (TREE_TYPE (type_in)); - in_n = TYPE_VECTOR_SUBPARTS (type_in); - - enum rs6000_builtins fn - = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); - switch (fn) - { - case RS6000_BUILTIN_RSQRTF: - if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP]; - break; - case RS6000_BUILTIN_RSQRT: - if (VECTOR_UNIT_VSX_P (V2DFmode) - && out_mode == DFmode && out_n == 2 - && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF]; - break; - case RS6000_BUILTIN_RECIPF: - if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) - && out_mode == SFmode && out_n == 4 - && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP]; - break; - case RS6000_BUILTIN_RECIP: - if (VECTOR_UNIT_VSX_P (V2DFmode) - && out_mode == DFmode && out_n == 2 - && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF]; - break; - default: - break; - } - - machine_mode in_vmode = TYPE_MODE (type_in); - machine_mode out_vmode = TYPE_MODE (type_out); - - /* Power10 supported vectorized built-in functions. */ - if (TARGET_POWER10 - && in_vmode == out_vmode - && VECTOR_UNIT_ALTIVEC_OR_VSX_P (in_vmode)) - { - machine_mode exp_mode = DImode; - machine_mode exp_vmode = V2DImode; - enum rs6000_builtins bif; - switch (fn) - { - case MISC_BUILTIN_DIVWE: - case MISC_BUILTIN_DIVWEU: - exp_mode = SImode; - exp_vmode = V4SImode; - if (fn == MISC_BUILTIN_DIVWE) - bif = P10V_BUILTIN_DIVES_V4SI; - else - bif = P10V_BUILTIN_DIVEU_V4SI; - break; - case MISC_BUILTIN_DIVDE: - case MISC_BUILTIN_DIVDEU: - if (fn == MISC_BUILTIN_DIVDE) - bif = P10V_BUILTIN_DIVES_V2DI; - else - bif = P10V_BUILTIN_DIVEU_V2DI; - break; - case P10_BUILTIN_CFUGED: - bif = P10V_BUILTIN_VCFUGED; - break; - case P10_BUILTIN_CNTLZDM: - bif = P10V_BUILTIN_VCLZDM; - break; - case P10_BUILTIN_CNTTZDM: - bif = P10V_BUILTIN_VCTZDM; - break; - case P10_BUILTIN_PDEPD: - bif = P10V_BUILTIN_VPDEPD; - break; - case P10_BUILTIN_PEXTD: - bif = P10V_BUILTIN_VPEXTD; - break; - default: - return NULL_TREE; - } - - if (in_mode == exp_mode && in_vmode == exp_vmode) - return rs6000_builtin_decls[bif]; - } - - return NULL_TREE; + return rs6000_new_builtin_md_vectorized_function (fndecl, type_out, type_in); } /* Default CPU string for rs6000*_file_start functions. */ @@ -22749,17 +22518,13 @@ rs6000_builtin_reciprocal (tree fndecl) if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode)) return NULL_TREE; - if (new_builtins_are_live) - return rs6000_builtin_decls_x[RS6000_BIF_RSQRT_2DF]; - return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF]; + return rs6000_builtin_decls_x[RS6000_BIF_RSQRT_2DF]; case RS6000_BIF_XVSQRTSP: if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode)) return NULL_TREE; - if (new_builtins_are_live) - return rs6000_builtin_decls_x[RS6000_BIF_RSQRT_4SF]; - return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF]; + return rs6000_builtin_decls_x[RS6000_BIF_RSQRT_4SF]; default: return NULL_TREE; @@ -25381,10 +25146,7 @@ add_condition_to_bb (tree function_decl, tree version_decl, tree bool_zero = build_int_cst (bool_int_type_node, 0); tree cond_var = create_tmp_var (bool_int_type_node); - tree predicate_decl - = new_builtins_are_live - ? rs6000_builtin_decls_x[(int) RS6000_BIF_CPU_SUPPORTS] - : rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS]; + tree predicate_decl = rs6000_builtin_decls_x[(int) RS6000_BIF_CPU_SUPPORTS]; const char *arg_str = rs6000_clone_map[clone_isa].name; tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str); gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg); @@ -28024,12 +27786,8 @@ rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) return; } - tree mffs - = new_builtins_are_live ? rs6000_builtin_decls_x[RS6000_BIF_MFFS] - : rs6000_builtin_decls[RS6000_BUILTIN_MFFS]; - tree mtfsf - = new_builtins_are_live ? rs6000_builtin_decls_x[RS6000_BIF_MTFSF] - : rs6000_builtin_decls[RS6000_BUILTIN_MTFSF]; + tree mffs = rs6000_builtin_decls_x[RS6000_BIF_MFFS]; + tree mtfsf = rs6000_builtin_decls_x[RS6000_BIF_MTFSF]; tree call_mffs = build_call_expr (mffs, 0); /* Generates the equivalent of feholdexcept (&fenv_var) -- cgit v1.1 From 7a54d3deecf967029f18aa5ed1fcbdb752e213b9 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Tue, 14 Dec 2021 18:27:22 +0100 Subject: i386: Implement VxHF vector set/insert/extract with lower ABI levels MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a preparation patch that moves VxHF vector set/insert/extract expansions from AVX512FP16 ABI to lower ABIs. There are no functional changes for -mavx512fp16 and a follow-up patch is needed to actually enable VxHF vector modes for lower ABIs. 2021-12-14 Uroš Bizjak gcc/ChangeLog: PR target/103571 * config/i386/i386-expand.c (ix86_expand_vector_init_duplicate) : Implement for TARGET_SSE2. : Implement for TARGET_AVX. : Implement for TARGET_AVX512F. (ix86_expand_vector_set_var): Handle V32HFmode without TARGET_AVX512BW. (ix86_expand_vector_extract) : Implement for TARGET_SSE2. : Implement for TARGET_AVX. : Implement for TARGET_AVX512BW. (expand_vec_perm_broadcast_1) : New. * config/i386/sse.md (VI12HF_AVX512VL): Remove TARGET_AVX512FP16 condition. (V): Ditto. (V_256_512): Ditto. (avx_vbroadcastf128_): Use V_256H mode iterator. --- gcc/config/i386/i386-expand.c | 118 +++++++++++++++++++++++++++++------------- gcc/config/i386/sse.md | 19 +++---- 2 files changed, 91 insertions(+), 46 deletions(-) (limited to 'gcc') diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 2bbb28e5..7013c20 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -14855,6 +14855,7 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode, goto widen; case E_V8HImode: + case E_V8HFmode: if (TARGET_AVX2) return ix86_vector_duplicate_value (mode, target, val); @@ -14871,15 +14872,22 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode, dperm.op0 = dperm.op1 = gen_reg_rtx (mode); dperm.one_operand_p = true; - /* Extend to SImode using a paradoxical SUBREG. */ - tmp1 = gen_reg_rtx (SImode); - emit_move_insn (tmp1, gen_lowpart (SImode, val)); - - /* Insert the SImode value as low element of a V4SImode vector. */ - tmp2 = gen_reg_rtx (V4SImode); - emit_insn (gen_vec_setv4si_0 (tmp2, CONST0_RTX (V4SImode), tmp1)); - emit_move_insn (dperm.op0, gen_lowpart (mode, tmp2)); + if (mode == V8HFmode) + tmp1 = lowpart_subreg (V8HFmode, force_reg (HFmode, val), HFmode); + else + { + /* Extend to SImode using a paradoxical SUBREG. */ + tmp1 = gen_reg_rtx (SImode); + emit_move_insn (tmp1, gen_lowpart (SImode, val)); + + /* Insert the SImode value as + low element of a V4SImode vector. */ + tmp2 = gen_reg_rtx (V4SImode); + emit_insn (gen_vec_setv4si_0 (tmp2, CONST0_RTX (V4SImode), tmp1)); + tmp1 = gen_lowpart (mode, tmp2); + } + emit_move_insn (dperm.op0, tmp1); ok = (expand_vec_perm_1 (&dperm) || expand_vec_perm_broadcast_1 (&dperm)); gcc_assert (ok); @@ -14926,12 +14934,15 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode, } case E_V16HImode: + case E_V16HFmode: case E_V32QImode: if (TARGET_AVX2) return ix86_vector_duplicate_value (mode, target, val); else { - machine_mode hvmode = (mode == V16HImode ? V8HImode : V16QImode); + machine_mode hvmode = (mode == V16HImode ? V8HImode + : mode == V16HFmode ? V8HFmode + : V16QImode); rtx x = gen_reg_rtx (hvmode); ok = ix86_expand_vector_init_duplicate (false, hvmode, x, val); @@ -14942,13 +14953,16 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode, } return true; - case E_V64QImode: case E_V32HImode: + case E_V32HFmode: + case E_V64QImode: if (TARGET_AVX512BW) return ix86_vector_duplicate_value (mode, target, val); else { - machine_mode hvmode = (mode == V32HImode ? V16HImode : V32QImode); + machine_mode hvmode = (mode == V32HImode ? V16HImode + : mode == V32HFmode ? V16HFmode + : V32QImode); rtx x = gen_reg_rtx (hvmode); ok = ix86_expand_vector_init_duplicate (false, hvmode, x, val); @@ -14959,11 +14973,6 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode, } return true; - case E_V8HFmode: - case E_V16HFmode: - case E_V32HFmode: - return ix86_vector_duplicate_value (mode, target, val); - default: return false; } @@ -15912,7 +15921,8 @@ ix86_expand_vector_set_var (rtx target, rtx val, rtx idx) /* 512-bits vector byte/word broadcast and comparison only available under TARGET_AVX512BW, break 512-bits vector into two 256-bits vector when without TARGET_AVX512BW. */ - if ((mode == V32HImode || mode == V64QImode) && !TARGET_AVX512BW) + if ((mode == V32HImode || mode == V32HFmode || mode == V64QImode) + && !TARGET_AVX512BW) { gcc_assert (TARGET_AVX512F); rtx vhi, vlo, idx_hi; @@ -15926,6 +15936,12 @@ ix86_expand_vector_set_var (rtx target, rtx val, rtx idx) extract_hi = gen_vec_extract_hi_v32hi; extract_lo = gen_vec_extract_lo_v32hi; } + else if (mode == V32HFmode) + { + half_mode = V16HFmode; + extract_hi = gen_vec_extract_hi_v32hf; + extract_lo = gen_vec_extract_lo_v32hf; + } else { half_mode = V32QImode; @@ -15973,7 +15989,6 @@ ix86_expand_vector_set_var (rtx target, rtx val, rtx idx) case E_V16SFmode: cmp_mode = V16SImode; break; - /* TARGET_AVX512FP16 implies TARGET_AVX512BW. */ case E_V8HFmode: cmp_mode = V8HImode; break; @@ -16538,6 +16553,7 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt) break; case E_V8HImode: + case E_V8HFmode: case E_V2HImode: use_vec_extr = TARGET_SSE2; break; @@ -16704,25 +16720,29 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt) return; case E_V32HFmode: - tmp = gen_reg_rtx (V16HFmode); - if (elt < 16) - emit_insn (gen_vec_extract_lo_v32hf (tmp, vec)); - else - emit_insn (gen_vec_extract_hi_v32hf (tmp, vec)); - ix86_expand_vector_extract (false, target, tmp, elt & 15); - return; + if (TARGET_AVX512BW) + { + tmp = gen_reg_rtx (V16HFmode); + if (elt < 16) + emit_insn (gen_vec_extract_lo_v32hf (tmp, vec)); + else + emit_insn (gen_vec_extract_hi_v32hf (tmp, vec)); + ix86_expand_vector_extract (false, target, tmp, elt & 15); + return; + } + break; case E_V16HFmode: - tmp = gen_reg_rtx (V8HFmode); - if (elt < 8) - emit_insn (gen_vec_extract_lo_v16hf (tmp, vec)); - else - emit_insn (gen_vec_extract_hi_v16hf (tmp, vec)); - ix86_expand_vector_extract (false, target, tmp, elt & 7); - return; - - case E_V8HFmode: - use_vec_extr = true; + if (TARGET_AVX) + { + tmp = gen_reg_rtx (V8HFmode); + if (elt < 8) + emit_insn (gen_vec_extract_lo_v16hf (tmp, vec)); + else + emit_insn (gen_vec_extract_hi_v16hf (tmp, vec)); + ix86_expand_vector_extract (false, target, tmp, elt & 7); + return; + } break; case E_V8QImode: @@ -21443,6 +21463,34 @@ expand_vec_perm_broadcast_1 (struct expand_vec_perm_d *d) emit_move_insn (d->target, gen_lowpart (d->vmode, dest)); return true; + case E_V8HFmode: + /* This can be implemented via interleave and pshufd. */ + if (d->testing_p) + return true; + + if (elt >= nelt2) + { + gen = gen_vec_interleave_highv8hf; + elt -= nelt2; + } + else + gen = gen_vec_interleave_lowv8hf; + nelt2 /= 2; + + dest = gen_reg_rtx (vmode); + emit_insn (gen (dest, op0, op0)); + + vmode = V4SImode; + op0 = gen_lowpart (vmode, dest); + + memset (perm2, elt, 4); + dest = gen_reg_rtx (vmode); + ok = expand_vselect (dest, op0, perm2, 4, d->testing_p); + gcc_assert (ok); + + emit_move_insn (d->target, gen_lowpart (d->vmode, dest)); + return true; + case E_V32QImode: case E_V16HImode: case E_V8SImode: diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5421fb5..929eef5 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -266,9 +266,7 @@ (define_mode_iterator VI12HF_AVX512VL [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL") - (V32HF "TARGET_AVX512FP16") - (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") - (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL")]) + V32HF (V16HF "TARGET_AVX512VL") (V8HF "TARGET_AVX512VL")]) ;; Same iterator, but without supposed TARGET_AVX512BW (define_mode_iterator VI12_AVX512VLBW @@ -285,8 +283,7 @@ (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI - (V32HF "TARGET_AVX512FP16") (V16HF "TARGET_AVX512FP16") - (V8HF "TARGET_AVX512FP16") + (V32HF "TARGET_AVX512F") (V16HF "TARGET_AVX") V8HF (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) @@ -311,10 +308,10 @@ ;; All 256bit and 512bit vector modes (define_mode_iterator V_256_512 - [V32QI V16HI V8SI V4DI V8SF V4DF - (V64QI "TARGET_AVX512F") (V32HI "TARGET_AVX512F") (V16SI "TARGET_AVX512F") - (V8DI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") (V8DF "TARGET_AVX512F") - (V16HF "TARGET_AVX512FP16") (V32HF "TARGET_AVX512FP16")]) + [V32QI V16HI V16HF V8SI V4DI V8SF V4DF + (V64QI "TARGET_AVX512F") (V32HI "TARGET_AVX512F") (V32HF "TARGET_AVX512F") + (V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") + (V8DF "TARGET_AVX512F")]) ;; All vector float modes (define_mode_iterator VF @@ -24892,8 +24889,8 @@ "operands[2] = gen_lowpart (mode, operands[0]);") (define_insn "avx_vbroadcastf128_" - [(set (match_operand:V_256 0 "register_operand" "=x,x,x,v,v,v,v") - (vec_concat:V_256 + [(set (match_operand:V_256H 0 "register_operand" "=x,x,x,v,v,v,v") + (vec_concat:V_256H (match_operand: 1 "nonimmediate_operand" "m,0,?x,m,0,m,0") (match_dup 1)))] "TARGET_AVX" -- cgit v1.1 From e866e1c92ecf88feeeafd5d55348451c9a181f3c Mon Sep 17 00:00:00 2001 From: Harald Anlauf Date: Tue, 14 Dec 2021 21:02:04 +0100 Subject: Fortran: prevent NULL pointer dereferences checking do-loop contained stuff gcc/fortran/ChangeLog: PR fortran/103718 PR fortran/103719 * frontend-passes.c (doloop_contained_procedure_code): Add several checks to prevent NULL pointer dereferences on valid and invalid code called within do-loops. gcc/testsuite/ChangeLog: PR fortran/103718 PR fortran/103719 * gfortran.dg/do_check_18.f90: New test. --- gcc/fortran/frontend-passes.c | 17 ++++++++++------- gcc/testsuite/gfortran.dg/do_check_18.f90 | 27 +++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/do_check_18.f90 (limited to 'gcc') diff --git a/gcc/fortran/frontend-passes.c b/gcc/fortran/frontend-passes.c index 57b24a1..c106ee0 100644 --- a/gcc/fortran/frontend-passes.c +++ b/gcc/fortran/frontend-passes.c @@ -2390,7 +2390,7 @@ doloop_contained_procedure_code (gfc_code **c, switch (co->op) { case EXEC_ASSIGN: - if (co->expr1->symtree->n.sym == do_var) + if (co->expr1->symtree && co->expr1->symtree->n.sym == do_var) gfc_error_now (errmsg, do_var->name, &co->loc, info->procedure->name, &info->where_do); break; @@ -2411,14 +2411,14 @@ doloop_contained_procedure_code (gfc_code **c, break; case EXEC_OPEN: - if (co->ext.open->iostat + if (co->ext.open && co->ext.open->iostat && co->ext.open->iostat->symtree->n.sym == do_var) gfc_error_now (errmsg, do_var->name, &co->ext.open->iostat->where, info->procedure->name, &info->where_do); break; case EXEC_CLOSE: - if (co->ext.close->iostat + if (co->ext.close && co->ext.close->iostat && co->ext.close->iostat->symtree->n.sym == do_var) gfc_error_now (errmsg, do_var->name, &co->ext.close->iostat->where, info->procedure->name, &info->where_do); @@ -2429,7 +2429,8 @@ doloop_contained_procedure_code (gfc_code **c, { case EXEC_INQUIRE: -#define CHECK_INQ(a) do { if (co->ext.inquire->a && \ +#define CHECK_INQ(a) do { if (co->ext.inquire && \ + co->ext.inquire->a && \ co->ext.inquire->a->symtree->n.sym == do_var) \ gfc_error_now (errmsg, do_var->name, \ &co->ext.inquire->a->where, \ @@ -2448,21 +2449,23 @@ doloop_contained_procedure_code (gfc_code **c, #undef CHECK_INQ case EXEC_READ: - if (co->expr1 && co->expr1->symtree->n.sym == do_var) + if (co->expr1 && co->expr1->symtree + && co->expr1->symtree->n.sym == do_var) gfc_error_now (errmsg, do_var->name, &co->expr1->where, info->procedure->name, &info->where_do); /* Fallthrough. */ case EXEC_WRITE: - if (co->ext.dt->iostat + if (co->ext.dt && co->ext.dt->iostat && co->ext.dt->iostat->symtree && co->ext.dt->iostat->symtree->n.sym == do_var) gfc_error_now (errmsg, do_var->name, &co->ext.dt->iostat->where, info->procedure->name, &info->where_do); break; case EXEC_IOLENGTH: - if (co->expr1 && co->expr1->symtree->n.sym == do_var) + if (co->expr1 && co->expr1->symtree + && co->expr1->symtree->n.sym == do_var) gfc_error_now (errmsg, do_var->name, &co->expr1->where, info->procedure->name, &info->where_do); break; diff --git a/gcc/testsuite/gfortran.dg/do_check_18.f90 b/gcc/testsuite/gfortran.dg/do_check_18.f90 new file mode 100644 index 0000000..b06112a --- /dev/null +++ b/gcc/testsuite/gfortran.dg/do_check_18.f90 @@ -0,0 +1,27 @@ +! { dg-do compile } +! PR103718, +! PR103719 - ICE in doloop_contained_procedure_code +! Contributed by G.Steinmetz + +subroutine s1 + integer :: i + do i = 1, 2 + call s + end do +contains + subroutine s + integer :: n + inquire (iolength=n) 0 ! valid + end +end + +subroutine s2 + integer :: i + do i = 1, 2 + call s + end do +contains + subroutine s + shape(1) = 0 ! { dg-error "Non-variable expression" } + end +end -- cgit v1.1 From ca39102e10643a6b3f07d06934cc0907ba83d9ee Mon Sep 17 00:00:00 2001 From: Harald Anlauf Date: Tue, 14 Dec 2021 21:57:04 +0100 Subject: Fortran: prevent NULL pointer dereference in check of passed do-loop variable gcc/fortran/ChangeLog: PR fortran/103717 * frontend-passes.c (doloop_code): Prevent NULL pointer dereference when checking for passing a do-loop variable to a contained procedure with an interface mismatch. gcc/testsuite/ChangeLog: PR fortran/103717 * gfortran.dg/do_check_19.f90: New test. --- gcc/fortran/frontend-passes.c | 2 +- gcc/testsuite/gfortran.dg/do_check_19.f90 | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gfortran.dg/do_check_19.f90 (limited to 'gcc') diff --git a/gcc/fortran/frontend-passes.c b/gcc/fortran/frontend-passes.c index c106ee0..6ffe072 100644 --- a/gcc/fortran/frontend-passes.c +++ b/gcc/fortran/frontend-passes.c @@ -2653,7 +2653,7 @@ doloop_code (gfc_code **c, int *walk_subtrees ATTRIBUTE_UNUSED, do_sym = cl->ext.iterator->var->symtree->n.sym; - if (a->expr && a->expr->symtree + if (a->expr && a->expr->symtree && f->sym && a->expr->symtree->n.sym == do_sym) { if (f->sym->attr.intent == INTENT_OUT) diff --git a/gcc/testsuite/gfortran.dg/do_check_19.f90 b/gcc/testsuite/gfortran.dg/do_check_19.f90 new file mode 100644 index 0000000..1373a73 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/do_check_19.f90 @@ -0,0 +1,21 @@ +! { dg-do compile } +! { dg-prune-output "Obsolescent feature: Alternate-return argument" } +! PR fortran/103717 - ICE in doloop_code +! Contributed by G.Steinmetz + +program p + integer :: i + do i = 1, 2 + call s(i) ! { dg-error "Missing alternate return specifier" } + end do +contains + subroutine s(*) + end +end + +recursive subroutine s(*) + integer :: i + do i = 1, 2 + call s(i) ! { dg-error "Missing alternate return specifier" } + end do +end -- cgit v1.1 From 15c02ab2569b3c4e27d6f133c013b15a9fa70177 Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Tue, 14 Dec 2021 14:50:41 -0600 Subject: rs6000: Do not allow combining of multiple assemble quads [PR103548] The compiler will gladly CSE the result of two __builtin_mma_build_acc calls with the same four vector arguments, leading to illegal MMA code being generated. The fix here is to make the mma_assemble_acc pattern use a unspec_volatile to stop the CSE from happening. 2021-12-14 Peter Bergner gcc/ PR target/103548 * config/rs6000/mma.md (UNSPEC_MMA_ASSEMBLE): Rename unspec from this... (UNSPEC_VSX_ASSEMBLE): ...to this. (UNSPECV_MMA_ASSEMBLE): New unspecv. (vsx_assemble_pair): Use UNSPEC_VSX_ASSEMBLE. (*vsx_assemble_pair): Likewise. (mma_assemble_acc): Use UNSPECV_MMA_ASSEMBLE. (*mma_assemble_acc): Likewise. * config/rs6000/rs6000.c (rs6000_split_multireg_move): Handle UNSPEC_VOLATILE. Use UNSPEC_VSX_ASSEMBLE and UNSPECV_MMA_ASSEMBLE. gcc/testsuite/ PR target/103548 * gcc.target/powerpc/mma-builtin-10-pair.c: New test. * gcc.target/powerpc/mma-builtin-10-quad.c: New test. --- gcc/config/rs6000/mma.md | 38 ++++++++++++---------- gcc/config/rs6000/rs6000.c | 6 ++-- .../gcc.target/powerpc/mma-builtin-10-pair.c | 21 ++++++++++++ .../gcc.target/powerpc/mma-builtin-10-quad.c | 23 +++++++++++++ 4 files changed, 68 insertions(+), 20 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c create mode 100644 gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c (limited to 'gcc') diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index fa08160..8a26205 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -29,7 +29,7 @@ ;; Constants for creating unspecs (define_c_enum "unspec" - [UNSPEC_MMA_ASSEMBLE + [UNSPEC_VSX_ASSEMBLE UNSPEC_MMA_EXTRACT UNSPEC_MMA_PMXVBF16GER2 UNSPEC_MMA_PMXVBF16GER2NN @@ -94,7 +94,8 @@ ]) (define_c_enum "unspecv" - [UNSPECV_MMA_XXSETACCZ + [UNSPECV_MMA_ASSEMBLE + UNSPECV_MMA_XXSETACCZ ]) ;; MMA instructions with 1 accumulator argument @@ -333,7 +334,7 @@ { rtx src = gen_rtx_UNSPEC (OOmode, gen_rtvec (2, operands[1], operands[2]), - UNSPEC_MMA_ASSEMBLE); + UNSPEC_VSX_ASSEMBLE); emit_move_insn (operands[0], src); DONE; }) @@ -345,7 +346,7 @@ [(set (match_operand:OO 0 "vsx_register_operand" "=&wa") (unspec:OO [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa") (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa")] - UNSPEC_MMA_ASSEMBLE))] + UNSPEC_VSX_ASSEMBLE))] "TARGET_MMA" "#" "&& reload_completed" @@ -353,7 +354,7 @@ { rtx src = gen_rtx_UNSPEC (OOmode, gen_rtvec (2, operands[1], operands[2]), - UNSPEC_MMA_ASSEMBLE); + UNSPEC_VSX_ASSEMBLE); rs6000_split_multireg_move (operands[0], src); DONE; }) @@ -399,10 +400,10 @@ (match_operand:V16QI 4 "mma_assemble_input_operand")] "TARGET_MMA" { - rtx src = gen_rtx_UNSPEC (XOmode, - gen_rtvec (4, operands[1], operands[2], - operands[3], operands[4]), - UNSPEC_MMA_ASSEMBLE); + rtx src = gen_rtx_UNSPEC_VOLATILE (XOmode, + gen_rtvec (4, operands[1], operands[2], + operands[3], operands[4]), + UNSPECV_MMA_ASSEMBLE); emit_move_insn (operands[0], src); DONE; }) @@ -412,21 +413,22 @@ (define_insn_and_split "*mma_assemble_acc" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") - (unspec:XO [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa") - (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa") - (match_operand:V16QI 3 "mma_assemble_input_operand" "mwa") - (match_operand:V16QI 4 "mma_assemble_input_operand" "mwa")] - UNSPEC_MMA_ASSEMBLE))] + (unspec_volatile:XO + [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa") + (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa") + (match_operand:V16QI 3 "mma_assemble_input_operand" "mwa") + (match_operand:V16QI 4 "mma_assemble_input_operand" "mwa")] + UNSPECV_MMA_ASSEMBLE))] "TARGET_MMA && fpr_reg_operand (operands[0], XOmode)" "#" "&& reload_completed" [(const_int 0)] { - rtx src = gen_rtx_UNSPEC (XOmode, - gen_rtvec (4, operands[1], operands[2], - operands[3], operands[4]), - UNSPEC_MMA_ASSEMBLE); + rtx src = gen_rtx_UNSPEC_VOLATILE (XOmode, + gen_rtvec (4, operands[1], operands[2], + operands[3], operands[4]), + UNSPECV_MMA_ASSEMBLE); rs6000_split_multireg_move (operands[0], src); DONE; }) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 70df511..9fc1577 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -27071,9 +27071,11 @@ rs6000_split_multireg_move (rtx dst, rtx src) return; } - if (GET_CODE (src) == UNSPEC) + if (GET_CODE (src) == UNSPEC + || GET_CODE (src) == UNSPEC_VOLATILE) { - gcc_assert (XINT (src, 1) == UNSPEC_MMA_ASSEMBLE); + gcc_assert (XINT (src, 1) == UNSPEC_VSX_ASSEMBLE + || XINT (src, 1) == UNSPECV_MMA_ASSEMBLE); gcc_assert (REG_P (dst)); if (GET_MODE (src) == XOmode) gcc_assert (FP_REGNO_P (REGNO (dst))); diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c new file mode 100644 index 0000000..d8748d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c @@ -0,0 +1,21 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +typedef unsigned char vec_t __attribute__((vector_size(16))); + +void +foo (__vector_pair *dst, vec_t *src) +{ + __vector_pair pair0, pair1; + /* Adjacent loads should be combined into one lxvp instruction + and identical build pairs should be combined. */ + __builtin_vsx_build_pair (&pair0, src[0], src[1]); + __builtin_vsx_build_pair (&pair1, src[0], src[1]); + dst[0] = pair0; + dst[2] = pair1; +} + +/* { dg-final { scan-assembler-not {\mlxv\M} } } */ +/* { dg-final { scan-assembler-not {\mstxv\M} } } */ +/* { dg-final { scan-assembler-times {\mlxvp\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c new file mode 100644 index 0000000..02342c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c @@ -0,0 +1,23 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +typedef unsigned char vec_t __attribute__((vector_size(16))); + +void +foo (__vector_quad *dst, vec_t *src) +{ + __vector_quad quad0, quad1; + /* Adjacent loads should be combined into two lxvp instructions. + and identical build accs should not be combined. */ + __builtin_mma_build_acc (&quad0, src[0], src[1], src[2], src[3]); + __builtin_mma_build_acc (&quad1, src[0], src[1], src[2], src[3]); + dst[0] = quad0; + dst[2] = quad1; +} + +/* { dg-final { scan-assembler-not {\mlxv\M} } } */ +/* { dg-final { scan-assembler-not {\mstxv\M} } } */ +/* { dg-final { scan-assembler-times {\mlxvp\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxmtacc\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxmfacc\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */ -- cgit v1.1 From 84c5516e429647ed5350b3286b06bb34e3acaf3e Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 14 Dec 2021 13:25:12 -0600 Subject: rs6000: Remove altivec_overloaded_builtins array and initialization 2021-12-06 Bill Schmidt gcc/ * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Remove. * config/rs6000/rs6000.h (altivec_overloaded_builtins): Remove. --- gcc/config/rs6000/rs6000-call.c | 5892 --------------------------------------- gcc/config/rs6000/rs6000.h | 1 - 2 files changed, 5893 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 85aea9b..d0fe960 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -305,5898 +305,6 @@ static const struct rs6000_builtin_info_type rs6000_builtin_info[] = #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_X -const struct altivec_builtin_types altivec_overloaded_builtins[] = { - /* Unary AltiVec/VSX builtins. */ - { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, - RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, - RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, - RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, - RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF, - RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB, - RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB, - RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF, - RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB, - RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, - - /* Binary AltiVec/VSX builtins. */ - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, - { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V2DI_UNS, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - - { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP, - RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, - RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, - RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, - RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, - RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, - RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, - RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, P10V_BUILTIN_VCMPEQUT, - RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, P10V_BUILTIN_VCMPEQUT, - RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - - { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW, - RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - - { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH, - RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH, - RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - - { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB, - RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB, - RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - - { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0}, - - { ALTIVEC_BUILTIN_VEC_CMPGE, P10V_BUILTIN_CMPGE_1TI, - RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPGE, P10V_BUILTIN_CMPGE_U1TI, - RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB, - RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB, - RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH, - RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH, - RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW, - RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD, - RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, P10V_BUILTIN_VCMPGTUT, - RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, P10V_BUILTIN_VCMPGTST, - RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW, - RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH, - RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH, - RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB, - RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB, - RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPLE, P10V_BUILTIN_CMPLE_1TI, - RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPLE, P10V_BUILTIN_CMPLE_U1TI, - RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0}, - { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB, - RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB, - RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH, - RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH, - RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW, - RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD, - RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX, - RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX, - RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE, - RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0}, - { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE, - RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0}, - { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX, - RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX, - RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS, - RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE, - RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, - - { P8V_BUILTIN_VEC_BCDADD, MISC_BUILTIN_BCDADD_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDADD, MISC_BUILTIN_BCDADD_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDADD_LT, MISC_BUILTIN_BCDADD_LT_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDADD_LT, MISC_BUILTIN_BCDADD_LT_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDADD_EQ, MISC_BUILTIN_BCDADD_EQ_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDADD_EQ, MISC_BUILTIN_BCDADD_EQ_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDADD_GT, MISC_BUILTIN_BCDADD_GT_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDADD_GT, MISC_BUILTIN_BCDADD_GT_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDADD_OV, MISC_BUILTIN_BCDADD_OV_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDADD_OV, MISC_BUILTIN_BCDADD_OV_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDINVALID, MISC_BUILTIN_BCDINVALID_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, 0, 0 }, - { P8V_BUILTIN_VEC_BCDINVALID, MISC_BUILTIN_BCDINVALID_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { P9V_BUILTIN_VEC_BCDMUL10, P9V_BUILTIN_BCDMUL10_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P9V_BUILTIN_VEC_BCDDIV10, P9V_BUILTIN_BCDDIV10_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { P8V_BUILTIN_VEC_DENBCD, MISC_BUILTIN_DENBCD_V16QI, - RS6000_BTI_dfloat128, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { P8V_BUILTIN_VEC_BCDSUB, MISC_BUILTIN_BCDSUB_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB, MISC_BUILTIN_BCDSUB_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_LT, MISC_BUILTIN_BCDSUB_LT_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_LT, MISC_BUILTIN_BCDSUB_LT_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_LE, MISC_BUILTIN_BCDSUB_LE_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_LE, MISC_BUILTIN_BCDSUB_LE_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_EQ, MISC_BUILTIN_BCDSUB_EQ_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_EQ, MISC_BUILTIN_BCDSUB_EQ_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_GT, MISC_BUILTIN_BCDSUB_GT_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_GT, MISC_BUILTIN_BCDSUB_GT_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_GE, MISC_BUILTIN_BCDSUB_GE_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_GE, MISC_BUILTIN_BCDSUB_GE_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_OV, MISC_BUILTIN_BCDSUB_OV_V1TI, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_INTSI }, - { P8V_BUILTIN_VEC_BCDSUB_OV, MISC_BUILTIN_BCDSUB_OV_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - - - { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - - { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVS_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVU_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVS_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIVU_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_DIV_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { VSX_BUILTIN_VEC_DIV, P10V_BUILTIN_UDIV_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - - { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVES_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVEU_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVES_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVEU_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVES_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { P10_BUILTIN_VEC_DIVE, P10V_BUILTIN_DIVEU_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - - { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODS_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODU_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODS_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODU_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODS_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { P10_BUILTIN_VEC_MOD, P10V_BUILTIN_MODU_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - - { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 }, - { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP, - RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 }, - - { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI, - RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, - { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI, - RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF, - RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, - - { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI, - RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, - { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI, - RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF, - RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, - - { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI, - RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, - { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI, - RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF, - RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, - - { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI, - RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, - { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI, - RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF, - RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, - - { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 }, - { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF, - RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI, - RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI, - RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF, - RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, - { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI, - RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, - { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI, - RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, - { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF, - RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, - { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI, - RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, - { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI, - RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, - - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, - - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_long_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, - RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - - /* vector signed__int128 vec_xl_sext (signed long long, signed char *); - vector signed__int128 vec_xl_sext (signed long long, signed short *); - vector signed__int128 vec_xl_sext (signed long long, signed int *); - vector signed__int128 vec_xl_sext (signed long long, signed longlong *); */ - { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRBX, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRHX, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRWX, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRDX, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, - { P10_BUILTIN_VEC_SE_LXVRX, P10_BUILTIN_SE_LXVRDX, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, - - /* vector unsigned__int128 vec_xl_zext (signed long long, unsigned char *); - vector unsigned__int128 vec_xl_zext (signed long long, unsigned short *); - vector unsigned__int128 vec_xl_zext (signed long long, unsigned int *); - vector unsigned__int128 vec_xl_zext (signed long long, unsigned longlong *); */ - { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRBX, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRHX, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRWX, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRDX, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, - { P10_BUILTIN_VEC_ZE_LXVRX, P10_BUILTIN_ZE_LXVRDX, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 }, - - /* void vec_xst_trunc (vector signed __int128, signed long long, signed char *); - void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *); - void vec_xst_trunc (vector signed __int128, signed long long, signed char *); - void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *); - void vec_xst_trunc (vector signed __int128, signed long long, signed char *); - void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *); - void vec_xst_trunc (vector signed __int128, signed long long, signed char *); - void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *); */ - { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRBX, RS6000_BTI_void, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRBX, RS6000_BTI_void, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRHX, RS6000_BTI_void, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRHX, RS6000_BTI_void, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRWX, RS6000_BTI_void, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRWX, RS6000_BTI_void, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long }, - { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long }, - { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI }, - { P10_BUILTIN_VEC_TR_STXVRX, P10_BUILTIN_TR_STXVRDX, RS6000_BTI_void, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI }, - - /* vector float vec_ldl (int, vector float *); - vector float vec_ldl (int, float *); */ - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - - /* vector bool int vec_ldl (int, vector bool int *); - vector bool int vec_ldl (int, bool int *); - vector int vec_ldl (int, vector int *); - vector int vec_ldl (int, int *); - vector unsigned int vec_ldl (int, vector unsigned int *); - vector unsigned int vec_ldl (int, unsigned int *); */ - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - - /* vector bool short vec_ldl (int, vector bool short *); - vector bool short vec_ldl (int, bool short *); - vector pixel vec_ldl (int, vector pixel *); - vector short vec_ldl (int, vector short *); - vector short vec_ldl (int, short *); - vector unsigned short vec_ldl (int, vector unsigned short *); - vector unsigned short vec_ldl (int, unsigned short *); */ - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, - RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - - /* vector bool char vec_ldl (int, vector bool char *); - vector bool char vec_ldl (int, bool char *); - vector char vec_ldl (int, vector char *); - vector char vec_ldl (int, char *); - vector unsigned char vec_ldl (int, vector unsigned char *); - vector unsigned char vec_ldl (int, unsigned char *); */ - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - - /* vector double vec_ldl (int, vector double *); - vector double vec_ldl (int, double *); */ - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, - - /* vector long long vec_ldl (int, vector long long *); - vector long long vec_ldl (int, long long *); - vector unsigned long long vec_ldl (int, vector unsigned long long *); - vector unsigned long long vec_ldl (int, unsigned long long *); - vector bool long long vec_ldl (int, vector bool long long *); - vector bool long long vec_ldl (int, bool long long *); */ - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_long_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 }, - - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_long_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_long_long, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHS_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHU_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHS_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P10_BUILTIN_VEC_MULH, P10V_BUILTIN_MULHU_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - - { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB, - RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULE, P10V_BUILTIN_VMULESD, - RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULE, P10V_BUILTIN_VMULEUD, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB, - RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB, - RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULO, P10V_BUILTIN_VMULOSD, - RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULO, P10V_BUILTIN_VMULOUD, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB, - RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - - { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_bool_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI_UNS, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI_UNS, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_bool_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, P10V_BUILTIN_VNOR_V1TI_UNS, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V2DI_UNS, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V4SI_UNS, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V8HI_UNS, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR_V16QI_UNS, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V2DI_UNS, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - - { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, - RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, - RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, - RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF, - RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - - { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - - { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { P9V_BUILTIN_VEC_CONVERT_4F32_8F16, P9V_BUILTIN_CONVERT_4F32_8F16, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - - { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI, - RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI, - RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI, - RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI, - RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI, - RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI, - RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI, - RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI, - RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI, - RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - - { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, - P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, - RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, - P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, - P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI, - RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, - P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, - P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI, - RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, - P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI, - RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - - { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, - RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, - RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX, - RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS, - RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS, - RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS, - RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS, - RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS, - RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKUDUS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_RL, P10V_BUILTIN_VRLQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_RL, P10V_BUILTIN_VRLQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, - { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, - { P9V_BUILTIN_VEC_RLMI, P10V_BUILTIN_VRLQMI, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI }, - { P9V_BUILTIN_VEC_RLMI, P10V_BUILTIN_VRLQMI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, - { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P9V_BUILTIN_VEC_RLNM, P10V_BUILTIN_VRLQNM, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - { P9V_BUILTIN_VEC_RLNM, P10V_BUILTIN_VRLQNM, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SL, P10V_BUILTIN_VSLQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_SL, P10V_BUILTIN_VSLQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 }, - - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 }, - { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SR, P10V_BUILTIN_VSRQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_SR, P10V_BUILTIN_VSRQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, P10V_BUILTIN_VSRAQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, P10V_BUILTIN_VSRAQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, - - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - - { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS, - RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS, - RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V2DI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_long_long, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, - - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V16QI, 0 }, - { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V2DI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_long_long, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V16QI, 0 }, - { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V2DI_UNS, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, - - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, - - /* Ternary AltiVec/VSX builtins. */ - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, - RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, - RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, - RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, - RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, - { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, - RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, - { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, - { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, - { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM, - RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, - - { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUDM, - RS6000_BTI_V1TI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V1TI }, - { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUDM, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI }, - - { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM, - RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, - { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, - { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, - { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, - RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, - - { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, - RS6000_BTI_bool_V16QI }, - { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, - { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, - RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, - RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, - RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI }, - - { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, - RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, - RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, - RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, - RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI }, - - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, - RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, - RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, - RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, - RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, - RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, - RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_long_long }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, - RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, - RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_long_long }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, - RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_long_long }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void }, - { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, - { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, - { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, - { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, - { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, - { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, - RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, - RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, - RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, - RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, - RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF, - RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF, - RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, - RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, - RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, - RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V2DI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, - RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_bool_V2DI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF, - RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF, - RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI, - RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI, - RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, - RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, - RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_long_long }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, - RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V2DI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, - RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_long_long }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V4SI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, - ~RS6000_BTI_UINTSI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V8HI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, - ~RS6000_BTI_UINTHI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V16QI }, - { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_UINTQI }, - { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, - - { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_INTSI }, - - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V2DI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V4SI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_long, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, - RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V8HI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V16QI, 0 }, - { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, - - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, - RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, - RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, - RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI, - ~RS6000_BTI_long_long }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, - RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI, - ~RS6000_BTI_unsigned_long_long }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI, - RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI, - RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, - RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, - RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V2DI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, - RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, - ~RS6000_BTI_bool_V2DI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF, - RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V4SI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, - ~RS6000_BTI_UINTSI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, - ~RS6000_BTI_bool_V4SI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, - ~RS6000_BTI_UINTSI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, - RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, - ~RS6000_BTI_INTSI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V8HI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, - ~RS6000_BTI_UINTHI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, - ~RS6000_BTI_bool_V8HI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, - ~RS6000_BTI_UINTHI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, - RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, - ~RS6000_BTI_INTHI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_unsigned_V16QI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_UINTQI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_bool_V16QI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_UINTQI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, - ~RS6000_BTI_INTQI }, - { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, - RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, - ~RS6000_BTI_pixel_V8HI }, - - /* Predicates. */ - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P10V_BUILTIN_VCMPGTUT_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P10V_BUILTIN_VCMPGTST_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, - - - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P10V_BUILTIN_VCMPEQUT_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P10V_BUILTIN_VCMPEQUT_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, - - - /* cmpge is the same as cmpgt for all cases except floating point. - There is further code to deal with this special case in - altivec_build_resolved_builtin. */ - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P10V_BUILTIN_VCMPGTUT_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P10V_BUILTIN_VCMPGTST_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, - { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, - - /* Power8 vector overloaded functions. */ - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI_UNS, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI_UNS, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI_UNS, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI_UNS, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI_UNS, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI_UNS, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI_UNS, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI_UNS, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - - { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - - { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - - { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - - { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, - RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V16QI, 0 }, - - { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - - { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - - { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - - { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - - { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, - { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, - - { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, - { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, - - { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, - { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, - - { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, - { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, - - { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, - { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, - - { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, - { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, - - { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, - { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, - - { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, - { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, - - { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - - { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - - { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - - { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - - { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - - { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - - { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - - { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - - { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, - { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, - - { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, - { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, - - { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, - { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, - - { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, - { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, - - { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, - { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, - - { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, - { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP, - RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, - - { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP, - RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 }, - - { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP, - RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 }, - - { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP, - RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, - { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 }, - - { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP, - RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 }, - - { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP, - RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 }, - { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP, - RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, - { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP, - RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, - - { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP, - RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 }, - { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP, - RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, - { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP, - RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, - - { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP, - RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, - { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP, - RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, - { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP, - RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, - - { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP, - RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, - { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP, - RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, - { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP, - RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, - - { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP, - RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 }, - { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP, - RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 }, - - { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP, - RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 }, - { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP, - RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 }, - - { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP, - RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 }, - { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF, - RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 }, - - { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP, - RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 }, - { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF, - RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 }, - - { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT, - RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, - { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT, - RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, - { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT, - RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, - { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT, - RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, - { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ, - RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, - { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ, - RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, - { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO, - RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, - { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO, - RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, - - { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R, - RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, - RS6000_BTI_unsigned_long_long, 0 }, - - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_V16QI, ~RS6000_BTI_INTQI, - RS6000_BTI_unsigned_long_long, 0 }, - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, - RS6000_BTI_unsigned_long_long, 0 }, - - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_V4SI, ~RS6000_BTI_INTSI, - RS6000_BTI_unsigned_long_long, 0 }, - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_long_long, 0 }, - - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_V1TI, ~RS6000_BTI_INTTI, - RS6000_BTI_unsigned_long_long, 0 }, - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI, - RS6000_BTI_unsigned_long_long, 0 }, - - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_V2DI, ~RS6000_BTI_long_long, - RS6000_BTI_unsigned_long_long, 0 }, - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long, - RS6000_BTI_unsigned_long_long, 0 }, - - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_V8HI, ~RS6000_BTI_INTHI, - RS6000_BTI_unsigned_long_long, 0 }, - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI, - RS6000_BTI_unsigned_long_long, 0 }, - - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_V2DF, ~RS6000_BTI_double, - RS6000_BTI_unsigned_long_long, 0 }, - { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, - RS6000_BTI_V4SF, ~RS6000_BTI_float, - RS6000_BTI_unsigned_long_long, 0 }, - /* At an appropriate future time, add support for the - RS6000_BTI_Float16 (exact name to be determined) type here. */ - - { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, - ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long}, - - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI, - RS6000_BTI_unsigned_long_long }, - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, - RS6000_BTI_unsigned_long_long }, - - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI, - RS6000_BTI_unsigned_long_long }, - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_long_long }, - - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI, - RS6000_BTI_unsigned_long_long }, - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI, - RS6000_BTI_unsigned_long_long }, - - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long, - RS6000_BTI_unsigned_long_long }, - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long, - RS6000_BTI_unsigned_long_long }, - - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI, - RS6000_BTI_unsigned_long_long }, - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI, - RS6000_BTI_unsigned_long_long }, - - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double, - RS6000_BTI_unsigned_long_long }, - { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, - RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float, - RS6000_BTI_unsigned_long_long }, - /* At an appropriate future time, add support for the - RS6000_BTI_Float16 (exact name to be determined) type here. */ - - { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, - RS6000_BTI_bool_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, - RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, - RS6000_BTI_V16QI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, - RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - - { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, - RS6000_BTI_bool_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH, - RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, - RS6000_BTI_V8HI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH, - RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - - { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, - RS6000_BTI_bool_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, - RS6000_BTI_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW, - RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPNE, P10V_BUILTIN_CMPNET, - RS6000_BTI_bool_V1TI, RS6000_BTI_V1TI, - RS6000_BTI_V1TI, 0 }, - { ALTIVEC_BUILTIN_VEC_CMPNE, P10V_BUILTIN_CMPNET, - RS6000_BTI_bool_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_bool_V16QI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, - RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, - RS6000_BTI_INTSI, RS6000_BTI_V16QI, - RS6000_BTI_bool_V16QI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, - RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, - RS6000_BTI_bool_V16QI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_bool_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, - RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, - RS6000_BTI_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, - RS6000_BTI_INTSI, RS6000_BTI_V8HI, - RS6000_BTI_bool_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, - RS6000_BTI_bool_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, - RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, - RS6000_BTI_pixel_V8HI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_bool_V4SI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, - RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, - RS6000_BTI_INTSI, RS6000_BTI_V4SI, - RS6000_BTI_bool_V4SI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, - RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, - RS6000_BTI_bool_V4SI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 - }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, - RS6000_BTI_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, - RS6000_BTI_INTSI, RS6000_BTI_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, - RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P10V_BUILTIN_VCMPNET_P, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P10V_BUILTIN_VCMPNET_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P, - RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P, - RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_bool_V16QI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, - RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, - RS6000_BTI_INTSI, RS6000_BTI_V16QI, - RS6000_BTI_bool_V16QI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, - RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, - RS6000_BTI_bool_V16QI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_bool_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, - RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, - RS6000_BTI_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, - RS6000_BTI_INTSI, RS6000_BTI_V8HI, - RS6000_BTI_bool_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, - RS6000_BTI_bool_V8HI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, - RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, - RS6000_BTI_pixel_V8HI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_bool_V4SI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, - RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, - RS6000_BTI_INTSI, RS6000_BTI_V4SI, - RS6000_BTI_bool_V4SI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, - RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, - RS6000_BTI_bool_V4SI, 0 }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 - }, - - /* The following 2 entries have been deprecated. */ - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, - RS6000_BTI_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, - RS6000_BTI_INTSI, RS6000_BTI_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, - RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, - RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P10V_BUILTIN_VCMPAET_P, - RS6000_BTI_INTSI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P10V_BUILTIN_VCMPAET_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P, - RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P, - RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - - { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI }, - { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, - - { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI }, - { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, - - { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI }, - { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P, - RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, - - { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB, - RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, - RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB, - RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - - { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH, - RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, - RS6000_BTI_V8HI, 0 }, - { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH, - RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - - { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW, - RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, - RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW, - RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - - { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, - { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI, - RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 }, - { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI, - RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 }, - - { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, - - { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH, - RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL, - RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 }, - - { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX, - RS6000_BTI_INTQI, RS6000_BTI_UINTSI, - RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX, - RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_V16QI, 0 }, - - { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX, - RS6000_BTI_INTHI, RS6000_BTI_UINTSI, - RS6000_BTI_V8HI, 0 }, - { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX, - RS6000_BTI_UINTHI, RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_V8HI, 0 }, - - { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, - RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, - RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, - RS6000_BTI_float, RS6000_BTI_UINTSI, - RS6000_BTI_V4SF, 0 }, - - { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX, - RS6000_BTI_INTQI, RS6000_BTI_UINTSI, - RS6000_BTI_V16QI, 0 }, - { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX, - RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_V16QI, 0 }, - - { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX, - RS6000_BTI_INTHI, RS6000_BTI_UINTSI, - RS6000_BTI_V8HI, 0 }, - { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX, - RS6000_BTI_UINTHI, RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_V8HI, 0 }, - - { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, - RS6000_BTI_INTSI, RS6000_BTI_UINTSI, - RS6000_BTI_V4SI, 0 }, - { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, - RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, - RS6000_BTI_float, RS6000_BTI_UINTSI, - RS6000_BTI_V4SF, 0 }, - - { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, - - { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, - { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, - - { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, - { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, - - { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, - { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, - - { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, - { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, - - { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - - { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, - { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, - { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, - - { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - - { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - - { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - - { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - - { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - - { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - - { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - - { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, - RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, - RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 }, - - { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - - { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - - { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, - RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 }, - { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, - RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 }, - - { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 }, - { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, - - { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB, - RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 }, - { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2, - RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 }, - { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB, - RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 }, - - { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, - RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS, - RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - - { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, - { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, - { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - - { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, - { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, 0 }, - - { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32, - RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 }, - { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB, - RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 }, - - { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, - - { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, - - { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI, - RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, - RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, - RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, - RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, - RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF, - RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 }, - { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF, - RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 }, - { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF, - RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, - { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF, - RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, - { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF, - RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, - - { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, - { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, - { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, - { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, - { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, - RS6000_BTI_V2DF, 0 }, - - /* Crypto builtins. */ - { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, - { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, - - { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, 0 }, - { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, 0 }, - { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, 0 }, - { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, 0 }, - - { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_INTSI, RS6000_BTI_INTSI }, - - /* Sign extend builtins that work work on ISA 3.0, not added until ISA 3.1 */ - { P9V_BUILTIN_VEC_VSIGNEXTI, P9V_BUILTIN_VSIGNEXTSB2W, - RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0, 0 }, - { P9V_BUILTIN_VEC_VSIGNEXTI, P9V_BUILTIN_VSIGNEXTSH2W, - RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, - - { P9V_BUILTIN_VEC_VSIGNEXTLL, P9V_BUILTIN_VSIGNEXTSB2D, - RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0, 0 }, - { P9V_BUILTIN_VEC_VSIGNEXTLL, P9V_BUILTIN_VSIGNEXTSH2D, - RS6000_BTI_V2DI, RS6000_BTI_V8HI, 0, 0 }, - { P9V_BUILTIN_VEC_VSIGNEXTLL, P9V_BUILTIN_VSIGNEXTSW2D, - RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, - - /* Overloaded built-in functions for ISA3.1 (power10). */ - { P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 }, - { P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_UINTSI, 0 }, - { P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 }, - { P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_UINTSI, 0 }, - - { P10_BUILTIN_VEC_GNB, P10V_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTQI, 0 }, - { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 }, - { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, - { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 }, - { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_INTSI, 0 }, - - /* The overloaded XXEVAL definitions are handled specially because the - fourth unsigned char operand is not encoded in this table. */ - { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, - { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, - { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, - - /* The overloaded XXPERMX definitions are handled specially because the - fourth unsigned char operand is not encoded in this table. */ - { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, - RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, - RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, - RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, - RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, - RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, - RS6000_BTI_unsigned_V16QI }, - - { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTBL, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTHL, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTWL, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTDL, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI }, - - { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRBL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI }, - { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRHL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI }, - { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRWL, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI }, - { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRDL, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI }, - { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRBL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRHL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRWL, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI }, - - { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTBR, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTHR, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTWR, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTDR, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI }, - - { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRBR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI }, - { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRHR, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI }, - { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRWR, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI }, - { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRDR, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI }, - { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRBR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRHR, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRWR, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI }, - - { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_UINTSI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI }, - { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI }, - { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_UINTDI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI }, - { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI }, - - { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_UINTSI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI }, - { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI }, - { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_UINTDI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI }, - { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI }, - - { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI }, - - { P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0, 0 }, - { P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_float, 0, 0 }, - - { P10_BUILTIN_VEC_XXSPLTID, P10V_BUILTIN_VXXSPLTID, - RS6000_BTI_V2DF, RS6000_BTI_float, 0, 0 }, - - { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_UINTQI, RS6000_BTI_INTSI }, - { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI, - RS6000_BTI_UINTSI }, - { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_UINTQI, RS6000_BTI_float }, - - { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, - RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, - { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, - RS6000_BTI_unsigned_V8HI }, - { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, - { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, - RS6000_BTI_unsigned_V4SI }, - { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, - { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, - RS6000_BTI_unsigned_V2DI }, - { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, - { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SF, - RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, - RS6000_BTI_unsigned_V4SI }, - { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DF, - RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, - RS6000_BTI_unsigned_V2DI }, - - { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, - RS6000_BTI_V16QI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, - RS6000_BTI_V8HI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_V4SI, - RS6000_BTI_V4SI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_V2DI, - RS6000_BTI_V2DI, RS6000_BTI_UINTQI }, - { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI }, - - { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - - { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - - { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P, - RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, - - { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P, - RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 }, - - { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR, - RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, - - { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR, - RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, - - { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P, - RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, - - { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P, - RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 }, - - { P10_BUILTIN_VEC_MTVSRBM, P10V_BUILTIN_MTVSRBM, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI, 0, 0 }, - { P10_BUILTIN_VEC_MTVSRHM, P10V_BUILTIN_MTVSRHM, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTDI, 0, 0 }, - { P10_BUILTIN_VEC_MTVSRWM, P10V_BUILTIN_MTVSRWM, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTDI, 0, 0 }, - { P10_BUILTIN_VEC_MTVSRDM, P10V_BUILTIN_MTVSRDM, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI, 0, 0 }, - { P10_BUILTIN_VEC_MTVSRQM, P10V_BUILTIN_MTVSRQM, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTDI, 0, 0 }, - - { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBB, - RS6000_BTI_unsigned_long_long, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, 0 }, - { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBH, - RS6000_BTI_unsigned_long_long, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI, 0 }, - { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBW, - RS6000_BTI_unsigned_long_long, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI, 0 }, - { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBD, - RS6000_BTI_unsigned_long_long, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI, 0 }, - - { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMB, - RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMH, - RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMW, - RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMD, - RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMQ, - RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, - - { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMB, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMH, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 }, - { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMW, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 0, 0 }, - { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMD, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 0, 0 }, - { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMQ, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, 0, 0 }, - - { P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10V_BUILTIN_XVTLSBB_ZEROS, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - { P10_BUILTIN_VEC_XVTLSBB_ONES, P10V_BUILTIN_XVTLSBB_ONES, - RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, - - { P10_BUILTIN_VEC_SIGNEXT, P10V_BUILTIN_VSIGNEXTSD2Q, - RS6000_BTI_V1TI, RS6000_BTI_V2DI, 0, 0 }, - - { RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 } -}; /* Nonzero if we can use a floating-point register to pass this arg. */ #define USE_FP_FOR_ARG_P(CUM,MODE) \ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 3eba1c0..b12ee8b 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -2399,7 +2399,6 @@ struct altivec_builtin_types signed char op2; signed char op3; }; -extern const struct altivec_builtin_types altivec_overloaded_builtins[]; enum rs6000_builtin_type_index { -- cgit v1.1 From 97912187624f711e905e1b9c4c353b4ae9ddd4d7 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 14 Dec 2021 13:27:58 -0600 Subject: rs6000: Rename rs6000-builtin-new.def to rs6000-builtins.def 2021-12-02 Bill Schmidt gcc/ * config/rs6000/rs6000-builtin-new.def: Rename to... * config/rs6000/rs6000-builtins.def: ...this. * config/rs6000/rs6000-gen-builtins.c: Adjust header commentary. * config/rs6000/t-rs6000 (EXTRA_GTYPE_DEPS): Rename rs6000-builtin-new.def to rs6000-builtins.def. (rs6000-builtins.c): Likewise. --- gcc/config/rs6000/rs6000-builtin-new.def | 4105 ------------------------------ gcc/config/rs6000/rs6000-builtins.def | 4105 ++++++++++++++++++++++++++++++ gcc/config/rs6000/rs6000-gen-builtins.c | 4 +- gcc/config/rs6000/t-rs6000 | 6 +- 4 files changed, 4110 insertions(+), 4110 deletions(-) delete mode 100644 gcc/config/rs6000/rs6000-builtin-new.def create mode 100644 gcc/config/rs6000/rs6000-builtins.def (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def deleted file mode 100644 index 45ce160..0000000 --- a/gcc/config/rs6000/rs6000-builtin-new.def +++ /dev/null @@ -1,4105 +0,0 @@ -; Built-in functions for PowerPC. -; Copyright (C) 2020-2021 Free Software Foundation, Inc. -; Contributed by Bill Schmidt, IBM -; -; This file is part of GCC. -; -; GCC is free software; you can redistribute it and/or modify it under -; the terms of the GNU General Public License as published by the Free -; Software Foundation; either version 3, or (at your option) any later -; version. -; -; GCC is distributed in the hope that it will be useful, but WITHOUT ANY -; WARRANTY; without even the implied warranty of MERCHANTABILITY or -; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -; for more details. -; -; You should have received a copy of the GNU General Public License -; along with GCC; see the file COPYING3. If not see -; . - - -; Built-in functions in this file are organized into "stanzas", where -; all built-ins in a given stanza are enabled together. Each stanza -; starts with a line identifying the circumstances in which the group of -; functions is permitted, with the gating predicate in square brackets. -; For example, this could be -; -; [altivec] -; -; or it could be -; -; [power9] -; -; The bracketed gating predicate is the only information allowed on -; the stanza header line, other than whitespace. -; -; Following the stanza header are two lines for each function: the -; prototype line and the attributes line. The prototype line has -; this format, where the square brackets indicate optional -; information and angle brackets indicate required information: -; -; [kind] (); -; -; Here [kind] can be one of "const", "pure", or "fpmath"; -; is a legal type for a built-in function result; -; is the name by which the function can be called; -; and is a comma-separated list of legal types -; for built-in function arguments. The argument list may be -; empty, but the parentheses and semicolon are required. -; -; A legal type is of the form: -; -; [const] [[signed|unsigned] | ] [*] -; -; where "const" applies only to a of "int". Legal values -; of are (for now): -; -; char -; short -; int -; long -; long double -; long long -; float -; double -; __int128 -; _Float128 -; bool -; string -; _Decimal32 -; _Decimal64 -; _Decimal128 -; __ibm128 -; -; Legal values of are as follows, and are shorthand for -; the associated meaning: -; -; vsc vector signed char -; vuc vector unsigned char -; vbc vector bool char -; vss vector signed short -; vus vector unsigned short -; vbs vector bool short -; vsi vector signed int -; vui vector unsigned int -; vbi vector bool int -; vsll vector signed long long -; vull vector unsigned long long -; vbll vector bool long long -; vsq vector signed __int128 -; vuq vector unsigned __int128 -; vbq vector bool __int128 -; vp vector pixel -; vf vector float -; vd vector double -; v256 __vector_pair -; v512 __vector_quad -; -; For simplicity, We don't support "short int" and "long long int". -; We don't currently support a of "_Float16". "signed" -; and "unsigned" only apply to integral base types. The optional * -; indicates a pointer type. -; -; The attributes line looks like this: -; -; {} -; -; Here is a unique internal identifier for the built-in -; function that will be used as part of an enumeration of all -; built-in functions; is the define_expand or -; define_insn that will be invoked when the call is expanded; -; and is a comma-separated list of special -; conditions that apply to the built-in function. The attribute -; list may be empty, but the braces are required. -; -; Attributes are strings, and the allowed ones are listed below. -; -; init Process as a vec_init function -; set Process as a vec_set function -; extract Process as a vec_extract function -; nosoft Not valid with -msoft-float -; ldvec Needs special handling for vec_ld semantics -; stvec Needs special handling for vec_st semantics -; reve Needs special handling for element reversal -; pred Needs special handling for comparison predicates -; htm Needs special handling for transactional memory -; htmspr HTM function using an SPR -; htmcr HTM function using a CR -; mma Needs special handling for MMA -; quad MMA instruction using a register quad as an input operand -; pair MMA instruction using a register pair as an input operand -; mmaint MMA instruction expanding to internal call at GIMPLE time -; no32bit Not valid for TARGET_32BIT -; 32bit Requires different handling for TARGET_32BIT -; cpu This is a "cpu_is" or "cpu_supports" builtin -; ldstmask Altivec mask for load or store -; lxvrse Needs special handling for load-rightmost, sign-extended -; lxvrze Needs special handling for load-rightmost, zero-extended -; endian Needs special handling for endianness -; ibmld Restrict usage to the case when TFmode is IBM-128 -; -; Each attribute corresponds to extra processing required when -; the built-in is expanded. All such special processing should -; be controlled by an attribute from now on. -; -; It is important to note that each entry's must be -; unique. The code generated from this file will call def_builtin -; for each entry, and this can only happen once per name. -; -; The type signature for the builtin must match the modes of the RTL -; pattern . When a builtin is used only as a basis for -; overloading, you can use an arbitrary type for each mode (for example, -; for V8HImode, you could use vp, vss, vus, or vbs). The overloading -; machinery takes care of adding appropriate casts between vectors to -; satisfy impedance matching. The overloaded prototypes are the ones -; that must match what users expect. Thus you will often have a small -; number of entries in this file that correspond to a much greater -; number of entries in rs6000-overload.def. -; -; However, builtins in this file that are expected to be directly called -; by users must have one version for each expected type combination. -; -; Eventually we want to automatically generate built-in documentation -; from the entries in this file. Documenting of built-ins with more -; than one acceptable prototype can be done by cross-referencing -; against rs6000-overload.def and picking up the allowable prototypes -; from there. -; -; Blank lines may be used as desired in this file between the lines as -; defined above; that is, you can introduce as many extra newlines as you -; like after a required newline, but nowhere else. Lines beginning with -; a semicolon are also treated as blank lines. -; -; A const int argument may be restricted to certain values. This is -; indicated by one of the following occurring after the "int" token: -; -; restricts the constant to x bits, interpreted as unsigned -; restricts the constant to the inclusive range [x,y] -; [x,y] restricts the constant to the inclusive range [x,y], -; but only applies if the argument is constant. -; {x,y} restricts the constant to one of two values, x or y. -; -; Here x and y are integer tokens. Note that the "const" token is a -; lie when the restriction is [x,y], but this simplifies the parsing -; significantly and is hopefully forgivable. - - - -; Builtins that have been around since time immemorial or are just -; considered available everywhere. -[always] -; __builtin_cfstring is for Darwin, which will replace the decl we -; create here with another one during subtarget processing. We just -; need to ensure it has a slot in the builtin enumeration. - void __builtin_cfstring (); - CFSTRING nothing {} - - void __builtin_cpu_init (); - CPU_INIT nothing {cpu} - - bool __builtin_cpu_is (string); - CPU_IS nothing {cpu} - - bool __builtin_cpu_supports (string); - CPU_SUPPORTS nothing {cpu} - - unsigned long long __builtin_ppc_get_timebase (); - GET_TB rs6000_get_timebase {} - - double __builtin_mffs (); - MFFS rs6000_mffs {} - -; Although the mffsl instruction is only available on POWER9 and later -; processors, this builtin automatically falls back to mffs on older -; platforms. Thus it appears here in the [always] stanza. - double __builtin_mffsl (); - MFFSL rs6000_mffsl {} - -; This is redundant with __builtin_pack_ibm128, as it requires long -; double to be __ibm128. Should probably be deprecated. - const long double __builtin_pack_longdouble (double, double); - PACK_TF packtf {ibmld} - - unsigned long __builtin_ppc_mftb (); - MFTB rs6000_mftb_di {32bit} - - void __builtin_mtfsb0 (const int<5>); - MTFSB0 rs6000_mtfsb0 {} - - void __builtin_mtfsb1 (const int<5>); - MTFSB1 rs6000_mtfsb1 {} - - void __builtin_mtfsf (const int<8>, double); - MTFSF rs6000_mtfsf {} - - const __ibm128 __builtin_pack_ibm128 (double, double); - PACK_IF packif {} - - void __builtin_set_fpscr_rn (const int[0,3]); - SET_FPSCR_RN rs6000_set_fpscr_rn {} - - const double __builtin_unpack_ibm128 (__ibm128, const int<1>); - UNPACK_IF unpackif {} - -; This is redundant with __builtin_unpack_ibm128, as it requires long -; double to be __ibm128. Should probably be deprecated. - const double __builtin_unpack_longdouble (long double, const int<1>); - UNPACK_TF unpacktf {ibmld} - - -; Builtins that have been around just about forever, but not quite. -[power5] - fpmath double __builtin_recipdiv (double, double); - RECIP recipdf3 {} - - fpmath float __builtin_recipdivf (float, float); - RECIPF recipsf3 {} - - fpmath double __builtin_rsqrt (double); - RSQRT rsqrtdf2 {} - - fpmath float __builtin_rsqrtf (float); - RSQRTF rsqrtsf2 {} - - -; Power6 builtins (ISA 2.05). -[power6] - const signed int __builtin_p6_cmpb_32 (signed int, signed int); - CMPB_32 cmpbsi3 {} - - -; Power6 builtins requiring 64-bit GPRs (even with 32-bit addressing). -[power6-64] - const signed long __builtin_p6_cmpb (signed long, signed long); - CMPB cmpbdi3 {no32bit} - - -; AltiVec builtins. -[altivec] - const vsc __builtin_altivec_abs_v16qi (vsc); - ABS_V16QI absv16qi2 {} - - const vf __builtin_altivec_abs_v4sf (vf); - ABS_V4SF absv4sf2 {} - - const vsi __builtin_altivec_abs_v4si (vsi); - ABS_V4SI absv4si2 {} - - const vss __builtin_altivec_abs_v8hi (vss); - ABS_V8HI absv8hi2 {} - - const vsc __builtin_altivec_abss_v16qi (vsc); - ABSS_V16QI altivec_abss_v16qi {} - - const vsi __builtin_altivec_abss_v4si (vsi); - ABSS_V4SI altivec_abss_v4si {} - - const vss __builtin_altivec_abss_v8hi (vss); - ABSS_V8HI altivec_abss_v8hi {} - - const vf __builtin_altivec_copysignfp (vf, vf); - COPYSIGN_V4SF vector_copysignv4sf3 {} - - void __builtin_altivec_dss (const int<2>); - DSS altivec_dss {} - - void __builtin_altivec_dssall (); - DSSALL altivec_dssall {} - - void __builtin_altivec_dst (void *, const int, const int<2>); - DST altivec_dst {} - - void __builtin_altivec_dstst (void *, const int, const int<2>); - DSTST altivec_dstst {} - - void __builtin_altivec_dststt (void *, const int, const int<2>); - DSTSTT altivec_dststt {} - - void __builtin_altivec_dstt (void *, const int, const int<2>); - DSTT altivec_dstt {} - - fpmath vsi __builtin_altivec_fix_sfsi (vf); - FIX_V4SF_V4SI fix_truncv4sfv4si2 {} - - fpmath vui __builtin_altivec_fixuns_sfsi (vf); - FIXUNS_V4SF_V4SI fixuns_truncv4sfv4si2 {} - - fpmath vf __builtin_altivec_float_sisf (vsi); - FLOAT_V4SI_V4SF floatv4siv4sf2 {} - - pure vsc __builtin_altivec_lvebx (signed long, const void *); - LVEBX altivec_lvebx {ldvec} - - pure vss __builtin_altivec_lvehx (signed long, const void *); - LVEHX altivec_lvehx {ldvec} - - pure vsi __builtin_altivec_lvewx (signed long, const void *); - LVEWX altivec_lvewx {ldvec} - - pure vuc __builtin_altivec_lvsl (signed long, const void *); - LVSL altivec_lvsl {ldvec} - - pure vuc __builtin_altivec_lvsr (signed long, const void *); - LVSR altivec_lvsr {ldvec} - - pure vsi __builtin_altivec_lvx (signed long, const void *); - LVX altivec_lvx_v4si {ldvec} - - pure vsq __builtin_altivec_lvx_v1ti (signed long, const void *); - LVX_V1TI altivec_lvx_v1ti {ldvec} - - pure vsc __builtin_altivec_lvx_v16qi (signed long, const void *); - LVX_V16QI altivec_lvx_v16qi {ldvec} - - pure vf __builtin_altivec_lvx_v4sf (signed long, const void *); - LVX_V4SF altivec_lvx_v4sf {ldvec} - - pure vsi __builtin_altivec_lvx_v4si (signed long, const void *); - LVX_V4SI altivec_lvx_v4si {ldvec} - - pure vss __builtin_altivec_lvx_v8hi (signed long, const void *); - LVX_V8HI altivec_lvx_v8hi {ldvec} - - pure vsi __builtin_altivec_lvxl (signed long, const void *); - LVXL altivec_lvxl_v4si {ldvec} - - pure vsc __builtin_altivec_lvxl_v16qi (signed long, const void *); - LVXL_V16QI altivec_lvxl_v16qi {ldvec} - - pure vf __builtin_altivec_lvxl_v4sf (signed long, const void *); - LVXL_V4SF altivec_lvxl_v4sf {ldvec} - - pure vsi __builtin_altivec_lvxl_v4si (signed long, const void *); - LVXL_V4SI altivec_lvxl_v4si {ldvec} - - pure vss __builtin_altivec_lvxl_v8hi (signed long, const void *); - LVXL_V8HI altivec_lvxl_v8hi {ldvec} - - const vsc __builtin_altivec_mask_for_load (const void *); - MASK_FOR_LOAD altivec_lvsr_direct {ldstmask} - - vss __builtin_altivec_mfvscr (); - MFVSCR altivec_mfvscr {} - - void __builtin_altivec_mtvscr (vsi); - MTVSCR altivec_mtvscr {} - - const vsll __builtin_altivec_vmulesw (vsi, vsi); - VMULESW vec_widen_smult_even_v4si {} - - const vull __builtin_altivec_vmuleuw (vui, vui); - VMULEUW vec_widen_umult_even_v4si {} - - const vsll __builtin_altivec_vmulosw (vsi, vsi); - VMULOSW vec_widen_smult_odd_v4si {} - - const vull __builtin_altivec_vmulouw (vui, vui); - VMULOUW vec_widen_umult_odd_v4si {} - - const vsc __builtin_altivec_nabs_v16qi (vsc); - NABS_V16QI nabsv16qi2 {} - - const vf __builtin_altivec_nabs_v4sf (vf); - NABS_V4SF vsx_nabsv4sf2 {} - - const vsi __builtin_altivec_nabs_v4si (vsi); - NABS_V4SI nabsv4si2 {} - - const vss __builtin_altivec_nabs_v8hi (vss); - NABS_V8HI nabsv8hi2 {} - - void __builtin_altivec_stvebx (vsc, signed long, void *); - STVEBX altivec_stvebx {stvec} - - void __builtin_altivec_stvehx (vss, signed long, void *); - STVEHX altivec_stvehx {stvec} - - void __builtin_altivec_stvewx (vsi, signed long, void *); - STVEWX altivec_stvewx {stvec} - - void __builtin_altivec_stvx (vsi, signed long, void *); - STVX altivec_stvx_v4si {stvec} - - void __builtin_altivec_stvx_v16qi (vsc, signed long, void *); - STVX_V16QI altivec_stvx_v16qi {stvec} - - void __builtin_altivec_stvx_v4sf (vf, signed long, void *); - STVX_V4SF altivec_stvx_v4sf {stvec} - - void __builtin_altivec_stvx_v4si (vsi, signed long, void *); - STVX_V4SI altivec_stvx_v4si {stvec} - - void __builtin_altivec_stvx_v8hi (vss, signed long, void *); - STVX_V8HI altivec_stvx_v8hi {stvec} - - void __builtin_altivec_stvxl (vsi, signed long, void *); - STVXL altivec_stvxl_v4si {stvec} - - void __builtin_altivec_stvxl_v16qi (vsc, signed long, void *); - STVXL_V16QI altivec_stvxl_v16qi {stvec} - - void __builtin_altivec_stvxl_v4sf (vf, signed long, void *); - STVXL_V4SF altivec_stvxl_v4sf {stvec} - - void __builtin_altivec_stvxl_v4si (vsi, signed long, void *); - STVXL_V4SI altivec_stvxl_v4si {stvec} - - void __builtin_altivec_stvxl_v8hi (vss, signed long, void *); - STVXL_V8HI altivec_stvxl_v8hi {stvec} - - fpmath vf __builtin_altivec_uns_float_sisf (vui); - UNSFLOAT_V4SI_V4SF floatunsv4siv4sf2 {} - - const vui __builtin_altivec_vaddcuw (vui, vui); - VADDCUW altivec_vaddcuw {} - - const vf __builtin_altivec_vaddfp (vf, vf); - VADDFP addv4sf3 {} - - const vsc __builtin_altivec_vaddsbs (vsc, vsc); - VADDSBS altivec_vaddsbs {} - - const vss __builtin_altivec_vaddshs (vss, vss); - VADDSHS altivec_vaddshs {} - - const vsi __builtin_altivec_vaddsws (vsi, vsi); - VADDSWS altivec_vaddsws {} - - const vuc __builtin_altivec_vaddubm (vuc, vuc); - VADDUBM addv16qi3 {} - - const vuc __builtin_altivec_vaddubs (vuc, vuc); - VADDUBS altivec_vaddubs {} - - const vus __builtin_altivec_vadduhm (vus, vus); - VADDUHM addv8hi3 {} - - const vus __builtin_altivec_vadduhs (vus, vus); - VADDUHS altivec_vadduhs {} - - const vsi __builtin_altivec_vadduwm (vsi, vsi); - VADDUWM addv4si3 {} - - const vui __builtin_altivec_vadduws (vui, vui); - VADDUWS altivec_vadduws {} - - const vsc __builtin_altivec_vand_v16qi (vsc, vsc); - VAND_V16QI andv16qi3 {} - - const vuc __builtin_altivec_vand_v16qi_uns (vuc, vuc); - VAND_V16QI_UNS andv16qi3 {} - - const vf __builtin_altivec_vand_v4sf (vf, vf); - VAND_V4SF andv4sf3 {} - - const vsi __builtin_altivec_vand_v4si (vsi, vsi); - VAND_V4SI andv4si3 {} - - const vui __builtin_altivec_vand_v4si_uns (vui, vui); - VAND_V4SI_UNS andv4si3 {} - - const vss __builtin_altivec_vand_v8hi (vss, vss); - VAND_V8HI andv8hi3 {} - - const vus __builtin_altivec_vand_v8hi_uns (vus, vus); - VAND_V8HI_UNS andv8hi3 {} - - const vsc __builtin_altivec_vandc_v16qi (vsc, vsc); - VANDC_V16QI andcv16qi3 {} - - const vuc __builtin_altivec_vandc_v16qi_uns (vuc, vuc); - VANDC_V16QI_UNS andcv16qi3 {} - - const vf __builtin_altivec_vandc_v4sf (vf, vf); - VANDC_V4SF andcv4sf3 {} - - const vsi __builtin_altivec_vandc_v4si (vsi, vsi); - VANDC_V4SI andcv4si3 {} - - const vui __builtin_altivec_vandc_v4si_uns (vui, vui); - VANDC_V4SI_UNS andcv4si3 {} - - const vss __builtin_altivec_vandc_v8hi (vss, vss); - VANDC_V8HI andcv8hi3 {} - - const vus __builtin_altivec_vandc_v8hi_uns (vus, vus); - VANDC_V8HI_UNS andcv8hi3 {} - - const vsc __builtin_altivec_vavgsb (vsc, vsc); - VAVGSB avgv16qi3_ceil {} - - const vss __builtin_altivec_vavgsh (vss, vss); - VAVGSH avgv8hi3_ceil {} - - const vsi __builtin_altivec_vavgsw (vsi, vsi); - VAVGSW avgv4si3_ceil {} - - const vuc __builtin_altivec_vavgub (vuc, vuc); - VAVGUB uavgv16qi3_ceil {} - - const vus __builtin_altivec_vavguh (vus, vus); - VAVGUH uavgv8hi3_ceil {} - - const vui __builtin_altivec_vavguw (vui, vui); - VAVGUW uavgv4si3_ceil {} - - const vf __builtin_altivec_vcfsx (vsi, const int<5>); - VCFSX altivec_vcfsx {} - - const vf __builtin_altivec_vcfux (vui, const int<5>); - VCFUX altivec_vcfux {} - - const vsi __builtin_altivec_vcmpbfp (vf, vf); - VCMPBFP altivec_vcmpbfp {} - - const int __builtin_altivec_vcmpbfp_p (int, vf, vf); - VCMPBFP_P altivec_vcmpbfp_p {pred} - - const vf __builtin_altivec_vcmpeqfp (vf, vf); - VCMPEQFP vector_eqv4sf {} - - const int __builtin_altivec_vcmpeqfp_p (int, vf, vf); - VCMPEQFP_P vector_eq_v4sf_p {pred} - - const vsc __builtin_altivec_vcmpequb (vuc, vuc); - VCMPEQUB vector_eqv16qi {} - - const int __builtin_altivec_vcmpequb_p (int, vsc, vsc); - VCMPEQUB_P vector_eq_v16qi_p {pred} - - const vss __builtin_altivec_vcmpequh (vus, vus); - VCMPEQUH vector_eqv8hi {} - - const int __builtin_altivec_vcmpequh_p (int, vss, vss); - VCMPEQUH_P vector_eq_v8hi_p {pred} - - const vsi __builtin_altivec_vcmpequw (vui, vui); - VCMPEQUW vector_eqv4si {} - - const int __builtin_altivec_vcmpequw_p (int, vsi, vsi); - VCMPEQUW_P vector_eq_v4si_p {pred} - - const vf __builtin_altivec_vcmpgefp (vf, vf); - VCMPGEFP vector_gev4sf {} - - const int __builtin_altivec_vcmpgefp_p (int, vf, vf); - VCMPGEFP_P vector_ge_v4sf_p {pred} - - const vf __builtin_altivec_vcmpgtfp (vf, vf); - VCMPGTFP vector_gtv4sf {} - - const int __builtin_altivec_vcmpgtfp_p (int, vf, vf); - VCMPGTFP_P vector_gt_v4sf_p {pred} - - const vsc __builtin_altivec_vcmpgtsb (vsc, vsc); - VCMPGTSB vector_gtv16qi {} - - const int __builtin_altivec_vcmpgtsb_p (int, vsc, vsc); - VCMPGTSB_P vector_gt_v16qi_p {pred} - - const vss __builtin_altivec_vcmpgtsh (vss, vss); - VCMPGTSH vector_gtv8hi {} - - const int __builtin_altivec_vcmpgtsh_p (int, vss, vss); - VCMPGTSH_P vector_gt_v8hi_p {pred} - - const vsi __builtin_altivec_vcmpgtsw (vsi, vsi); - VCMPGTSW vector_gtv4si {} - - const int __builtin_altivec_vcmpgtsw_p (int, vsi, vsi); - VCMPGTSW_P vector_gt_v4si_p {pred} - - const vsc __builtin_altivec_vcmpgtub (vuc, vuc); - VCMPGTUB vector_gtuv16qi {} - - const int __builtin_altivec_vcmpgtub_p (int, vsc, vsc); - VCMPGTUB_P vector_gtu_v16qi_p {pred} - - const vss __builtin_altivec_vcmpgtuh (vus, vus); - VCMPGTUH vector_gtuv8hi {} - - const int __builtin_altivec_vcmpgtuh_p (int, vss, vss); - VCMPGTUH_P vector_gtu_v8hi_p {pred} - - const vsi __builtin_altivec_vcmpgtuw (vui, vui); - VCMPGTUW vector_gtuv4si {} - - const int __builtin_altivec_vcmpgtuw_p (int, vsi, vsi); - VCMPGTUW_P vector_gtu_v4si_p {pred} - - const vsi __builtin_altivec_vctsxs (vf, const int<5>); - VCTSXS altivec_vctsxs {} - - const vui __builtin_altivec_vctuxs (vf, const int<5>); - VCTUXS altivec_vctuxs {} - - fpmath vf __builtin_altivec_vexptefp (vf); - VEXPTEFP altivec_vexptefp {} - - fpmath vf __builtin_altivec_vlogefp (vf); - VLOGEFP altivec_vlogefp {} - - fpmath vf __builtin_altivec_vmaddfp (vf, vf, vf); - VMADDFP fmav4sf4 {} - - const vf __builtin_altivec_vmaxfp (vf, vf); - VMAXFP smaxv4sf3 {} - - const vsc __builtin_altivec_vmaxsb (vsc, vsc); - VMAXSB smaxv16qi3 {} - - const vuc __builtin_altivec_vmaxub (vuc, vuc); - VMAXUB umaxv16qi3 {} - - const vss __builtin_altivec_vmaxsh (vss, vss); - VMAXSH smaxv8hi3 {} - - const vsi __builtin_altivec_vmaxsw (vsi, vsi); - VMAXSW smaxv4si3 {} - - const vus __builtin_altivec_vmaxuh (vus, vus); - VMAXUH umaxv8hi3 {} - - const vui __builtin_altivec_vmaxuw (vui, vui); - VMAXUW umaxv4si3 {} - - vss __builtin_altivec_vmhaddshs (vss, vss, vss); - VMHADDSHS altivec_vmhaddshs {} - - vss __builtin_altivec_vmhraddshs (vss, vss, vss); - VMHRADDSHS altivec_vmhraddshs {} - - const vf __builtin_altivec_vminfp (vf, vf); - VMINFP sminv4sf3 {} - - const vsc __builtin_altivec_vminsb (vsc, vsc); - VMINSB sminv16qi3 {} - - const vss __builtin_altivec_vminsh (vss, vss); - VMINSH sminv8hi3 {} - - const vsi __builtin_altivec_vminsw (vsi, vsi); - VMINSW sminv4si3 {} - - const vuc __builtin_altivec_vminub (vuc, vuc); - VMINUB uminv16qi3 {} - - const vus __builtin_altivec_vminuh (vus, vus); - VMINUH uminv8hi3 {} - - const vui __builtin_altivec_vminuw (vui, vui); - VMINUW uminv4si3 {} - - const vss __builtin_altivec_vmladduhm (vss, vss, vss); - VMLADDUHM fmav8hi4 {} - - const vsc __builtin_altivec_vmrghb (vsc, vsc); - VMRGHB altivec_vmrghb {} - - const vss __builtin_altivec_vmrghh (vss, vss); - VMRGHH altivec_vmrghh {} - - const vsi __builtin_altivec_vmrghw (vsi, vsi); - VMRGHW altivec_vmrghw {} - - const vsc __builtin_altivec_vmrglb (vsc, vsc); - VMRGLB altivec_vmrglb {} - - const vss __builtin_altivec_vmrglh (vss, vss); - VMRGLH altivec_vmrglh {} - - const vsi __builtin_altivec_vmrglw (vsi, vsi); - VMRGLW altivec_vmrglw {} - - const vsi __builtin_altivec_vmsummbm (vsc, vuc, vsi); - VMSUMMBM altivec_vmsummbm {} - - const vsi __builtin_altivec_vmsumshm (vss, vss, vsi); - VMSUMSHM altivec_vmsumshm {} - - vsi __builtin_altivec_vmsumshs (vss, vss, vsi); - VMSUMSHS altivec_vmsumshs {} - - const vui __builtin_altivec_vmsumubm (vuc, vuc, vui); - VMSUMUBM altivec_vmsumubm {} - - const vui __builtin_altivec_vmsumuhm (vus, vus, vui); - VMSUMUHM altivec_vmsumuhm {} - - vui __builtin_altivec_vmsumuhs (vus, vus, vui); - VMSUMUHS altivec_vmsumuhs {} - - const vss __builtin_altivec_vmulesb (vsc, vsc); - VMULESB vec_widen_smult_even_v16qi {} - - const vsi __builtin_altivec_vmulesh (vss, vss); - VMULESH vec_widen_smult_even_v8hi {} - - const vus __builtin_altivec_vmuleub (vuc, vuc); - VMULEUB vec_widen_umult_even_v16qi {} - - const vui __builtin_altivec_vmuleuh (vus, vus); - VMULEUH vec_widen_umult_even_v8hi {} - - const vss __builtin_altivec_vmulosb (vsc, vsc); - VMULOSB vec_widen_smult_odd_v16qi {} - - const vus __builtin_altivec_vmuloub (vuc, vuc); - VMULOUB vec_widen_umult_odd_v16qi {} - - const vsi __builtin_altivec_vmulosh (vss, vss); - VMULOSH vec_widen_smult_odd_v8hi {} - - const vui __builtin_altivec_vmulouh (vus, vus); - VMULOUH vec_widen_umult_odd_v8hi {} - - fpmath vf __builtin_altivec_vnmsubfp (vf, vf, vf); - VNMSUBFP nfmsv4sf4 {} - - const vsc __builtin_altivec_vnor_v16qi (vsc, vsc); - VNOR_V16QI norv16qi3 {} - - const vuc __builtin_altivec_vnor_v16qi_uns (vuc, vuc); - VNOR_V16QI_UNS norv16qi3 {} - - const vf __builtin_altivec_vnor_v4sf (vf, vf); - VNOR_V4SF norv4sf3 {} - - const vsi __builtin_altivec_vnor_v4si (vsi, vsi); - VNOR_V4SI norv4si3 {} - - const vui __builtin_altivec_vnor_v4si_uns (vui, vui); - VNOR_V4SI_UNS norv4si3 {} - - const vss __builtin_altivec_vnor_v8hi (vss, vss); - VNOR_V8HI norv8hi3 {} - - const vus __builtin_altivec_vnor_v8hi_uns (vus, vus); - VNOR_V8HI_UNS norv8hi3 {} - - const vsc __builtin_altivec_vor_v16qi (vsc, vsc); - VOR_V16QI iorv16qi3 {} - - const vuc __builtin_altivec_vor_v16qi_uns (vuc, vuc); - VOR_V16QI_UNS iorv16qi3 {} - - const vf __builtin_altivec_vor_v4sf (vf, vf); - VOR_V4SF iorv4sf3 {} - - const vsi __builtin_altivec_vor_v4si (vsi, vsi); - VOR_V4SI iorv4si3 {} - - const vui __builtin_altivec_vor_v4si_uns (vui, vui); - VOR_V4SI_UNS iorv4si3 {} - - const vss __builtin_altivec_vor_v8hi (vss, vss); - VOR_V8HI iorv8hi3 {} - - const vus __builtin_altivec_vor_v8hi_uns (vus, vus); - VOR_V8HI_UNS iorv8hi3 {} - - const vsc __builtin_altivec_vperm_16qi (vsc, vsc, vuc); - VPERM_16QI altivec_vperm_v16qi {} - - const vuc __builtin_altivec_vperm_16qi_uns (vuc, vuc, vuc); - VPERM_16QI_UNS altivec_vperm_v16qi_uns {} - - const vsq __builtin_altivec_vperm_1ti (vsq, vsq, vuc); - VPERM_1TI altivec_vperm_v1ti {} - - const vuq __builtin_altivec_vperm_1ti_uns (vuq, vuq, vuc); - VPERM_1TI_UNS altivec_vperm_v1ti_uns {} - - const vf __builtin_altivec_vperm_4sf (vf, vf, vuc); - VPERM_4SF altivec_vperm_v4sf {} - - const vsi __builtin_altivec_vperm_4si (vsi, vsi, vuc); - VPERM_4SI altivec_vperm_v4si {} - - const vui __builtin_altivec_vperm_4si_uns (vui, vui, vuc); - VPERM_4SI_UNS altivec_vperm_v4si_uns {} - - const vss __builtin_altivec_vperm_8hi (vss, vss, vuc); - VPERM_8HI altivec_vperm_v8hi {} - - const vus __builtin_altivec_vperm_8hi_uns (vus, vus, vuc); - VPERM_8HI_UNS altivec_vperm_v8hi_uns {} - - const vp __builtin_altivec_vpkpx (vui, vui); - VPKPX altivec_vpkpx {} - - const vsc __builtin_altivec_vpkshss (vss, vss); - VPKSHSS altivec_vpkshss {} - - const vuc __builtin_altivec_vpkshus (vss, vss); - VPKSHUS altivec_vpkshus {} - - const vss __builtin_altivec_vpkswss (vsi, vsi); - VPKSWSS altivec_vpkswss {} - - const vus __builtin_altivec_vpkswus (vsi, vsi); - VPKSWUS altivec_vpkswus {} - - const vsc __builtin_altivec_vpkuhum (vss, vss); - VPKUHUM altivec_vpkuhum {} - - const vuc __builtin_altivec_vpkuhus (vus, vus); - VPKUHUS altivec_vpkuhus {} - - const vss __builtin_altivec_vpkuwum (vsi, vsi); - VPKUWUM altivec_vpkuwum {} - - const vus __builtin_altivec_vpkuwus (vui, vui); - VPKUWUS altivec_vpkuwus {} - - const vf __builtin_altivec_vrecipdivfp (vf, vf); - VRECIPFP recipv4sf3 {} - - fpmath vf __builtin_altivec_vrefp (vf); - VREFP rev4sf2 {} - - const vsc __builtin_altivec_vreve_v16qi (vsc); - VREVE_V16QI altivec_vrevev16qi2 {} - - const vf __builtin_altivec_vreve_v4sf (vf); - VREVE_V4SF altivec_vrevev4sf2 {} - - const vsi __builtin_altivec_vreve_v4si (vsi); - VREVE_V4SI altivec_vrevev4si2 {} - - const vss __builtin_altivec_vreve_v8hi (vss); - VREVE_V8HI altivec_vrevev8hi2 {} - - fpmath vf __builtin_altivec_vrfim (vf); - VRFIM vector_floorv4sf2 {} - - fpmath vf __builtin_altivec_vrfin (vf); - VRFIN altivec_vrfin {} - - fpmath vf __builtin_altivec_vrfip (vf); - VRFIP vector_ceilv4sf2 {} - - fpmath vf __builtin_altivec_vrfiz (vf); - VRFIZ vector_btruncv4sf2 {} - - const vsc __builtin_altivec_vrlb (vsc, vsc); - VRLB vrotlv16qi3 {} - - const vss __builtin_altivec_vrlh (vss, vss); - VRLH vrotlv8hi3 {} - - const vsi __builtin_altivec_vrlw (vsi, vsi); - VRLW vrotlv4si3 {} - - fpmath vf __builtin_altivec_vrsqrtefp (vf); - VRSQRTEFP rsqrtev4sf2 {} - - fpmath vf __builtin_altivec_vrsqrtfp (vf); - VRSQRTFP rsqrtv4sf2 {} - - const vsc __builtin_altivec_vsel_16qi (vsc, vsc, vuc); - VSEL_16QI vector_select_v16qi {} - - const vuc __builtin_altivec_vsel_16qi_uns (vuc, vuc, vuc); - VSEL_16QI_UNS vector_select_v16qi_uns {} - - const vsq __builtin_altivec_vsel_1ti (vsq, vsq, vuq); - VSEL_1TI vector_select_v1ti {} - - const vuq __builtin_altivec_vsel_1ti_uns (vuq, vuq, vuq); - VSEL_1TI_UNS vector_select_v1ti_uns {} - - const vf __builtin_altivec_vsel_4sf (vf, vf, vf); - VSEL_4SF vector_select_v4sf {} - - const vsi __builtin_altivec_vsel_4si (vsi, vsi, vui); - VSEL_4SI vector_select_v4si {} - - const vui __builtin_altivec_vsel_4si_uns (vui, vui, vui); - VSEL_4SI_UNS vector_select_v4si_uns {} - - const vss __builtin_altivec_vsel_8hi (vss, vss, vus); - VSEL_8HI vector_select_v8hi {} - - const vus __builtin_altivec_vsel_8hi_uns (vus, vus, vus); - VSEL_8HI_UNS vector_select_v8hi_uns {} - - const vsi __builtin_altivec_vsl (vsi, vsi); - VSL altivec_vsl {} - - const vsc __builtin_altivec_vslb (vsc, vuc); - VSLB vashlv16qi3 {} - - const vsc __builtin_altivec_vsldoi_16qi (vsc, vsc, const int<4>); - VSLDOI_16QI altivec_vsldoi_v16qi {} - - const vf __builtin_altivec_vsldoi_4sf (vf, vf, const int<4>); - VSLDOI_4SF altivec_vsldoi_v4sf {} - - const vsi __builtin_altivec_vsldoi_4si (vsi, vsi, const int<4>); - VSLDOI_4SI altivec_vsldoi_v4si {} - - const vss __builtin_altivec_vsldoi_8hi (vss, vss, const int<4>); - VSLDOI_8HI altivec_vsldoi_v8hi {} - - const vss __builtin_altivec_vslh (vss, vus); - VSLH vashlv8hi3 {} - - const vsi __builtin_altivec_vslo (vsi, vsi); - VSLO altivec_vslo {} - - const vsi __builtin_altivec_vslw (vsi, vui); - VSLW vashlv4si3 {} - - const vsc __builtin_altivec_vspltb (vsc, const int<4>); - VSPLTB altivec_vspltb {} - - const vss __builtin_altivec_vsplth (vss, const int<3>); - VSPLTH altivec_vsplth {} - - const vsc __builtin_altivec_vspltisb (const int<-16,15>); - VSPLTISB altivec_vspltisb {} - - const vss __builtin_altivec_vspltish (const int<-16,15>); - VSPLTISH altivec_vspltish {} - - const vsi __builtin_altivec_vspltisw (const int<-16,15>); - VSPLTISW altivec_vspltisw {} - - const vsi __builtin_altivec_vspltw (vsi, const int<2>); - VSPLTW altivec_vspltw {} - - const vsi __builtin_altivec_vsr (vsi, vsi); - VSR altivec_vsr {} - - const vsc __builtin_altivec_vsrab (vsc, vuc); - VSRAB vashrv16qi3 {} - - const vss __builtin_altivec_vsrah (vss, vus); - VSRAH vashrv8hi3 {} - - const vsi __builtin_altivec_vsraw (vsi, vui); - VSRAW vashrv4si3 {} - - const vsc __builtin_altivec_vsrb (vsc, vuc); - VSRB vlshrv16qi3 {} - - const vss __builtin_altivec_vsrh (vss, vus); - VSRH vlshrv8hi3 {} - - const vsi __builtin_altivec_vsro (vsi, vsi); - VSRO altivec_vsro {} - - const vsi __builtin_altivec_vsrw (vsi, vui); - VSRW vlshrv4si3 {} - - const vsi __builtin_altivec_vsubcuw (vsi, vsi); - VSUBCUW altivec_vsubcuw {} - - const vf __builtin_altivec_vsubfp (vf, vf); - VSUBFP subv4sf3 {} - - const vsc __builtin_altivec_vsubsbs (vsc, vsc); - VSUBSBS altivec_vsubsbs {} - - const vss __builtin_altivec_vsubshs (vss, vss); - VSUBSHS altivec_vsubshs {} - - const vsi __builtin_altivec_vsubsws (vsi, vsi); - VSUBSWS altivec_vsubsws {} - - const vuc __builtin_altivec_vsububm (vuc, vuc); - VSUBUBM subv16qi3 {} - - const vuc __builtin_altivec_vsububs (vuc, vuc); - VSUBUBS altivec_vsububs {} - - const vus __builtin_altivec_vsubuhm (vus, vus); - VSUBUHM subv8hi3 {} - - const vus __builtin_altivec_vsubuhs (vus, vus); - VSUBUHS altivec_vsubuhs {} - - const vui __builtin_altivec_vsubuwm (vui, vui); - VSUBUWM subv4si3 {} - - const vui __builtin_altivec_vsubuws (vui, vui); - VSUBUWS altivec_vsubuws {} - - const vsi __builtin_altivec_vsum2sws (vsi, vsi); - VSUM2SWS altivec_vsum2sws {} - - const vsi __builtin_altivec_vsum4sbs (vsc, vsi); - VSUM4SBS altivec_vsum4sbs {} - - const vsi __builtin_altivec_vsum4shs (vss, vsi); - VSUM4SHS altivec_vsum4shs {} - - const vui __builtin_altivec_vsum4ubs (vuc, vui); - VSUM4UBS altivec_vsum4ubs {} - - const vsi __builtin_altivec_vsumsws (vsi, vsi); - VSUMSWS altivec_vsumsws {} - - const vsi __builtin_altivec_vsumsws_be (vsi, vsi); - VSUMSWS_BE altivec_vsumsws_direct {} - - const vui __builtin_altivec_vupkhpx (vp); - VUPKHPX altivec_vupkhpx {} - - const vss __builtin_altivec_vupkhsb (vsc); - VUPKHSB altivec_vupkhsb {} - - const vsi __builtin_altivec_vupkhsh (vss); - VUPKHSH altivec_vupkhsh {} - - const vui __builtin_altivec_vupklpx (vp); - VUPKLPX altivec_vupklpx {} - - const vss __builtin_altivec_vupklsb (vsc); - VUPKLSB altivec_vupklsb {} - - const vsi __builtin_altivec_vupklsh (vss); - VUPKLSH altivec_vupklsh {} - - const vsc __builtin_altivec_vxor_v16qi (vsc, vsc); - VXOR_V16QI xorv16qi3 {} - - const vuc __builtin_altivec_vxor_v16qi_uns (vuc, vuc); - VXOR_V16QI_UNS xorv16qi3 {} - - const vf __builtin_altivec_vxor_v4sf (vf, vf); - VXOR_V4SF xorv4sf3 {} - - const vsi __builtin_altivec_vxor_v4si (vsi, vsi); - VXOR_V4SI xorv4si3 {} - - const vui __builtin_altivec_vxor_v4si_uns (vui, vui); - VXOR_V4SI_UNS xorv4si3 {} - - const vss __builtin_altivec_vxor_v8hi (vss, vss); - VXOR_V8HI xorv8hi3 {} - - const vus __builtin_altivec_vxor_v8hi_uns (vus, vus); - VXOR_V8HI_UNS xorv8hi3 {} - - const signed char __builtin_vec_ext_v16qi (vsc, signed int); - VEC_EXT_V16QI nothing {extract} - - const float __builtin_vec_ext_v4sf (vf, signed int); - VEC_EXT_V4SF nothing {extract} - - const signed int __builtin_vec_ext_v4si (vsi, signed int); - VEC_EXT_V4SI nothing {extract} - - const signed short __builtin_vec_ext_v8hi (vss, signed int); - VEC_EXT_V8HI nothing {extract} - - const vsc __builtin_vec_init_v16qi (signed char, signed char, signed char, \ - signed char, signed char, signed char, signed char, signed char, \ - signed char, signed char, signed char, signed char, signed char, \ - signed char, signed char, signed char); - VEC_INIT_V16QI nothing {init} - - const vf __builtin_vec_init_v4sf (float, float, float, float); - VEC_INIT_V4SF nothing {init} - - const vsi __builtin_vec_init_v4si (signed int, signed int, signed int, \ - signed int); - VEC_INIT_V4SI nothing {init} - - const vss __builtin_vec_init_v8hi (signed short, signed short, signed short,\ - signed short, signed short, signed short, signed short, \ - signed short); - VEC_INIT_V8HI nothing {init} - - const vsc __builtin_vec_set_v16qi (vsc, signed char, const int<4>); - VEC_SET_V16QI nothing {set} - - const vf __builtin_vec_set_v4sf (vf, float, const int<2>); - VEC_SET_V4SF nothing {set} - - const vsi __builtin_vec_set_v4si (vsi, signed int, const int<2>); - VEC_SET_V4SI nothing {set} - - const vss __builtin_vec_set_v8hi (vss, signed short, const int<3>); - VEC_SET_V8HI nothing {set} - - -; Cell builtins. -[cell] - pure vsc __builtin_altivec_lvlx (signed long, const void *); - LVLX altivec_lvlx {ldvec} - - pure vsc __builtin_altivec_lvlxl (signed long, const void *); - LVLXL altivec_lvlxl {ldvec} - - pure vsc __builtin_altivec_lvrx (signed long, const void *); - LVRX altivec_lvrx {ldvec} - - pure vsc __builtin_altivec_lvrxl (signed long, const void *); - LVRXL altivec_lvrxl {ldvec} - - void __builtin_altivec_stvlx (vsc, signed long, void *); - STVLX altivec_stvlx {stvec} - - void __builtin_altivec_stvlxl (vsc, signed long, void *); - STVLXL altivec_stvlxl {stvec} - - void __builtin_altivec_stvrx (vsc, signed long, void *); - STVRX altivec_stvrx {stvec} - - void __builtin_altivec_stvrxl (vsc, signed long, void *); - STVRXL altivec_stvrxl {stvec} - - -; VSX builtins. -[vsx] - pure vd __builtin_altivec_lvx_v2df (signed long, const void *); - LVX_V2DF altivec_lvx_v2df {ldvec} - - pure vsll __builtin_altivec_lvx_v2di (signed long, const void *); - LVX_V2DI altivec_lvx_v2di {ldvec} - - pure vd __builtin_altivec_lvxl_v2df (signed long, const void *); - LVXL_V2DF altivec_lvxl_v2df {ldvec} - - pure vsll __builtin_altivec_lvxl_v2di (signed long, const void *); - LVXL_V2DI altivec_lvxl_v2di {ldvec} - - const vd __builtin_altivec_nabs_v2df (vd); - NABS_V2DF vsx_nabsv2df2 {} - - const vsll __builtin_altivec_nabs_v2di (vsll); - NABS_V2DI nabsv2di2 {} - - void __builtin_altivec_stvx_v2df (vd, signed long, void *); - STVX_V2DF altivec_stvx_v2df {stvec} - - void __builtin_altivec_stvx_v2di (vsll, signed long, void *); - STVX_V2DI altivec_stvx_v2di {stvec} - - void __builtin_altivec_stvxl_v2df (vd, signed long, void *); - STVXL_V2DF altivec_stvxl_v2df {stvec} - - void __builtin_altivec_stvxl_v2di (vsll, signed long, void *); - STVXL_V2DI altivec_stvxl_v2di {stvec} - - const vd __builtin_altivec_vand_v2df (vd, vd); - VAND_V2DF andv2df3 {} - - const vsll __builtin_altivec_vand_v2di (vsll, vsll); - VAND_V2DI andv2di3 {} - - const vull __builtin_altivec_vand_v2di_uns (vull, vull); - VAND_V2DI_UNS andv2di3 {} - - const vd __builtin_altivec_vandc_v2df (vd, vd); - VANDC_V2DF andcv2df3 {} - - const vsll __builtin_altivec_vandc_v2di (vsll, vsll); - VANDC_V2DI andcv2di3 {} - - const vull __builtin_altivec_vandc_v2di_uns (vull, vull); - VANDC_V2DI_UNS andcv2di3 {} - - const vd __builtin_altivec_vnor_v2df (vd, vd); - VNOR_V2DF norv2df3 {} - - const vsll __builtin_altivec_vnor_v2di (vsll, vsll); - VNOR_V2DI norv2di3 {} - - const vull __builtin_altivec_vnor_v2di_uns (vull, vull); - VNOR_V2DI_UNS norv2di3 {} - - const vd __builtin_altivec_vor_v2df (vd, vd); - VOR_V2DF iorv2df3 {} - - const vsll __builtin_altivec_vor_v2di (vsll, vsll); - VOR_V2DI iorv2di3 {} - - const vull __builtin_altivec_vor_v2di_uns (vull, vull); - VOR_V2DI_UNS iorv2di3 {} - - const vd __builtin_altivec_vperm_2df (vd, vd, vuc); - VPERM_2DF altivec_vperm_v2df {} - - const vsll __builtin_altivec_vperm_2di (vsll, vsll, vuc); - VPERM_2DI altivec_vperm_v2di {} - - const vull __builtin_altivec_vperm_2di_uns (vull, vull, vuc); - VPERM_2DI_UNS altivec_vperm_v2di_uns {} - - const vd __builtin_altivec_vreve_v2df (vd); - VREVE_V2DF altivec_vrevev2df2 {} - - const vsll __builtin_altivec_vreve_v2di (vsll); - VREVE_V2DI altivec_vrevev2di2 {} - - const vd __builtin_altivec_vsel_2df (vd, vd, vd); - VSEL_2DF vector_select_v2df {} - - const vsll __builtin_altivec_vsel_2di (vsll, vsll, vsll); - VSEL_2DI_B vector_select_v2di {} - - const vull __builtin_altivec_vsel_2di_uns (vull, vull, vull); - VSEL_2DI_UNS vector_select_v2di_uns {} - - const vd __builtin_altivec_vsldoi_2df (vd, vd, const int<4>); - VSLDOI_2DF altivec_vsldoi_v2df {} - - const vsll __builtin_altivec_vsldoi_2di (vsll, vsll, const int<4>); - VSLDOI_2DI altivec_vsldoi_v2di {} - - const vd __builtin_altivec_vxor_v2df (vd, vd); - VXOR_V2DF xorv2df3 {} - - const vsll __builtin_altivec_vxor_v2di (vsll, vsll); - VXOR_V2DI xorv2di3 {} - - const vull __builtin_altivec_vxor_v2di_uns (vull, vull); - VXOR_V2DI_UNS xorv2di3 {} - - const signed __int128 __builtin_vec_ext_v1ti (vsq, signed int); - VEC_EXT_V1TI nothing {extract} - - const double __builtin_vec_ext_v2df (vd, signed int); - VEC_EXT_V2DF nothing {extract} - - const signed long long __builtin_vec_ext_v2di (vsll, signed int); - VEC_EXT_V2DI nothing {extract} - - const vsq __builtin_vec_init_v1ti (signed __int128); - VEC_INIT_V1TI nothing {init} - - const vd __builtin_vec_init_v2df (double, double); - VEC_INIT_V2DF nothing {init} - - const vsll __builtin_vec_init_v2di (signed long long, signed long long); - VEC_INIT_V2DI nothing {init} - - const vsq __builtin_vec_set_v1ti (vsq, signed __int128, const int<0,0>); - VEC_SET_V1TI nothing {set} - - const vd __builtin_vec_set_v2df (vd, double, const int<1>); - VEC_SET_V2DF nothing {set} - - const vsll __builtin_vec_set_v2di (vsll, signed long long, const int<1>); - VEC_SET_V2DI nothing {set} - - const vsc __builtin_vsx_cmpge_16qi (vsc, vsc); - CMPGE_16QI vector_nltv16qi {} - - const vsll __builtin_vsx_cmpge_2di (vsll, vsll); - CMPGE_2DI vector_nltv2di {} - - const vsi __builtin_vsx_cmpge_4si (vsi, vsi); - CMPGE_4SI vector_nltv4si {} - - const vss __builtin_vsx_cmpge_8hi (vss, vss); - CMPGE_8HI vector_nltv8hi {} - - const vsc __builtin_vsx_cmpge_u16qi (vuc, vuc); - CMPGE_U16QI vector_nltuv16qi {} - - const vsll __builtin_vsx_cmpge_u2di (vull, vull); - CMPGE_U2DI vector_nltuv2di {} - - const vsi __builtin_vsx_cmpge_u4si (vui, vui); - CMPGE_U4SI vector_nltuv4si {} - - const vss __builtin_vsx_cmpge_u8hi (vus, vus); - CMPGE_U8HI vector_nltuv8hi {} - - const vsc __builtin_vsx_cmple_16qi (vsc, vsc); - CMPLE_16QI vector_ngtv16qi {} - - const vsll __builtin_vsx_cmple_2di (vsll, vsll); - CMPLE_2DI vector_ngtv2di {} - - const vsi __builtin_vsx_cmple_4si (vsi, vsi); - CMPLE_4SI vector_ngtv4si {} - - const vss __builtin_vsx_cmple_8hi (vss, vss); - CMPLE_8HI vector_ngtv8hi {} - - const vsc __builtin_vsx_cmple_u16qi (vsc, vsc); - CMPLE_U16QI vector_ngtuv16qi {} - - const vsll __builtin_vsx_cmple_u2di (vsll, vsll); - CMPLE_U2DI vector_ngtuv2di {} - - const vsi __builtin_vsx_cmple_u4si (vsi, vsi); - CMPLE_U4SI vector_ngtuv4si {} - - const vss __builtin_vsx_cmple_u8hi (vss, vss); - CMPLE_U8HI vector_ngtuv8hi {} - - const vd __builtin_vsx_concat_2df (double, double); - CONCAT_2DF vsx_concat_v2df {} - - const vsll __builtin_vsx_concat_2di (signed long long, signed long long); - CONCAT_2DI vsx_concat_v2di {} - - const vd __builtin_vsx_cpsgndp (vd, vd); - CPSGNDP vector_copysignv2df3 {} - - const vf __builtin_vsx_cpsgnsp (vf, vf); - CPSGNSP vector_copysignv4sf3 {} - - const vsll __builtin_vsx_div_2di (vsll, vsll); - DIV_V2DI vsx_div_v2di {} - - const vd __builtin_vsx_doublee_v4sf (vf); - DOUBLEE_V4SF doubleev4sf2 {} - - const vd __builtin_vsx_doublee_v4si (vsi); - DOUBLEE_V4SI doubleev4si2 {} - - const vd __builtin_vsx_doubleh_v4sf (vf); - DOUBLEH_V4SF doublehv4sf2 {} - - const vd __builtin_vsx_doubleh_v4si (vsi); - DOUBLEH_V4SI doublehv4si2 {} - - const vd __builtin_vsx_doublel_v4sf (vf); - DOUBLEL_V4SF doublelv4sf2 {} - - const vd __builtin_vsx_doublel_v4si (vsi); - DOUBLEL_V4SI doublelv4si2 {} - - const vd __builtin_vsx_doubleo_v4sf (vf); - DOUBLEO_V4SF doubleov4sf2 {} - - const vd __builtin_vsx_doubleo_v4si (vsi); - DOUBLEO_V4SI doubleov4si2 {} - - const vf __builtin_vsx_floate_v2df (vd); - FLOATE_V2DF floatev2df {} - - const vf __builtin_vsx_floate_v2di (vsll); - FLOATE_V2DI floatev2di {} - - const vf __builtin_vsx_floato_v2df (vd); - FLOATO_V2DF floatov2df {} - - const vf __builtin_vsx_floato_v2di (vsll); - FLOATO_V2DI floatov2di {} - - pure vsq __builtin_vsx_ld_elemrev_v1ti (signed long, const void *); - LD_ELEMREV_V1TI vsx_ld_elemrev_v1ti {ldvec,endian} - - pure vd __builtin_vsx_ld_elemrev_v2df (signed long, const void *); - LD_ELEMREV_V2DF vsx_ld_elemrev_v2df {ldvec,endian} - - pure vsll __builtin_vsx_ld_elemrev_v2di (signed long, const void *); - LD_ELEMREV_V2DI vsx_ld_elemrev_v2di {ldvec,endian} - - pure vf __builtin_vsx_ld_elemrev_v4sf (signed long, const void *); - LD_ELEMREV_V4SF vsx_ld_elemrev_v4sf {ldvec,endian} - - pure vsi __builtin_vsx_ld_elemrev_v4si (signed long, const void *); - LD_ELEMREV_V4SI vsx_ld_elemrev_v4si {ldvec,endian} - - pure vss __builtin_vsx_ld_elemrev_v8hi (signed long, const void *); - LD_ELEMREV_V8HI vsx_ld_elemrev_v8hi {ldvec,endian} - - pure vsc __builtin_vsx_ld_elemrev_v16qi (signed long, const void *); - LD_ELEMREV_V16QI vsx_ld_elemrev_v16qi {ldvec,endian} - -; TODO: There is apparent intent in rs6000-builtin.def to have -; RS6000_BTC_SPECIAL processing for LXSDX, LXVDSX, and STXSDX, but there are -; no def_builtin calls for any of them. At some point, we may want to add a -; set of built-ins for whichever vector types make sense for these. - - pure vsq __builtin_vsx_lxvd2x_v1ti (signed long, const void *); - LXVD2X_V1TI vsx_load_v1ti {ldvec} - - pure vd __builtin_vsx_lxvd2x_v2df (signed long, const void *); - LXVD2X_V2DF vsx_load_v2df {ldvec} - - pure vsll __builtin_vsx_lxvd2x_v2di (signed long, const void *); - LXVD2X_V2DI vsx_load_v2di {ldvec} - - pure vsc __builtin_vsx_lxvw4x_v16qi (signed long, const void *); - LXVW4X_V16QI vsx_load_v16qi {ldvec} - - pure vf __builtin_vsx_lxvw4x_v4sf (signed long, const void *); - LXVW4X_V4SF vsx_load_v4sf {ldvec} - - pure vsi __builtin_vsx_lxvw4x_v4si (signed long, const void *); - LXVW4X_V4SI vsx_load_v4si {ldvec} - - pure vss __builtin_vsx_lxvw4x_v8hi (signed long, const void *); - LXVW4X_V8HI vsx_load_v8hi {ldvec} - - const vd __builtin_vsx_mergeh_2df (vd, vd); - VEC_MERGEH_V2DF vsx_mergeh_v2df {} - - const vsll __builtin_vsx_mergeh_2di (vsll, vsll); - VEC_MERGEH_V2DI vsx_mergeh_v2di {} - - const vd __builtin_vsx_mergel_2df (vd, vd); - VEC_MERGEL_V2DF vsx_mergel_v2df {} - - const vsll __builtin_vsx_mergel_2di (vsll, vsll); - VEC_MERGEL_V2DI vsx_mergel_v2di {} - - const vsll __builtin_vsx_mul_2di (vsll, vsll); - MUL_V2DI vsx_mul_v2di {} - - const vsq __builtin_vsx_set_1ti (vsq, signed __int128, const int<0,0>); - SET_1TI vsx_set_v1ti {set} - - const vd __builtin_vsx_set_2df (vd, double, const int<0,1>); - SET_2DF vsx_set_v2df {set} - - const vsll __builtin_vsx_set_2di (vsll, signed long long, const int<0,1>); - SET_2DI vsx_set_v2di {set} - - const vd __builtin_vsx_splat_2df (double); - SPLAT_2DF vsx_splat_v2df {} - - const vsll __builtin_vsx_splat_2di (signed long long); - SPLAT_2DI vsx_splat_v2di {} - - void __builtin_vsx_st_elemrev_v1ti (vsq, signed long, void *); - ST_ELEMREV_V1TI vsx_st_elemrev_v1ti {stvec,endian} - - void __builtin_vsx_st_elemrev_v2df (vd, signed long, void *); - ST_ELEMREV_V2DF vsx_st_elemrev_v2df {stvec,endian} - - void __builtin_vsx_st_elemrev_v2di (vsll, signed long, void *); - ST_ELEMREV_V2DI vsx_st_elemrev_v2di {stvec,endian} - - void __builtin_vsx_st_elemrev_v4sf (vf, signed long, void *); - ST_ELEMREV_V4SF vsx_st_elemrev_v4sf {stvec,endian} - - void __builtin_vsx_st_elemrev_v4si (vsi, signed long, void *); - ST_ELEMREV_V4SI vsx_st_elemrev_v4si {stvec,endian} - - void __builtin_vsx_st_elemrev_v8hi (vss, signed long, void *); - ST_ELEMREV_V8HI vsx_st_elemrev_v8hi {stvec,endian} - - void __builtin_vsx_st_elemrev_v16qi (vsc, signed long, void *); - ST_ELEMREV_V16QI vsx_st_elemrev_v16qi {stvec,endian} - - void __builtin_vsx_stxvd2x_v1ti (vsq, signed long, void *); - STXVD2X_V1TI vsx_store_v1ti {stvec} - - void __builtin_vsx_stxvd2x_v2df (vd, signed long, void *); - STXVD2X_V2DF vsx_store_v2df {stvec} - - void __builtin_vsx_stxvd2x_v2di (vsll, signed long, void *); - STXVD2X_V2DI vsx_store_v2di {stvec} - - void __builtin_vsx_stxvw4x_v4sf (vf, signed long, void *); - STXVW4X_V4SF vsx_store_v4sf {stvec} - - void __builtin_vsx_stxvw4x_v4si (vsi, signed long, void *); - STXVW4X_V4SI vsx_store_v4si {stvec} - - void __builtin_vsx_stxvw4x_v8hi (vss, signed long, void *); - STXVW4X_V8HI vsx_store_v8hi {stvec} - - void __builtin_vsx_stxvw4x_v16qi (vsc, signed long, void *); - STXVW4X_V16QI vsx_store_v16qi {stvec} - - const vull __builtin_vsx_udiv_2di (vull, vull); - UDIV_V2DI vsx_udiv_v2di {} - - const vd __builtin_vsx_uns_doublee_v4si (vsi); - UNS_DOUBLEE_V4SI unsdoubleev4si2 {} - - const vd __builtin_vsx_uns_doubleh_v4si (vsi); - UNS_DOUBLEH_V4SI unsdoublehv4si2 {} - - const vd __builtin_vsx_uns_doublel_v4si (vsi); - UNS_DOUBLEL_V4SI unsdoublelv4si2 {} - - const vd __builtin_vsx_uns_doubleo_v4si (vsi); - UNS_DOUBLEO_V4SI unsdoubleov4si2 {} - - const vf __builtin_vsx_uns_floate_v2di (vsll); - UNS_FLOATE_V2DI unsfloatev2di {} - - const vf __builtin_vsx_uns_floato_v2di (vsll); - UNS_FLOATO_V2DI unsfloatov2di {} - -; These are duplicates of __builtin_altivec_* counterparts, and are being -; kept for backwards compatibility. The reason for their existence is -; unclear. TODO: Consider deprecation/removal at some point. - const vsc __builtin_vsx_vperm_16qi (vsc, vsc, vuc); - VPERM_16QI_X altivec_vperm_v16qi {} - - const vuc __builtin_vsx_vperm_16qi_uns (vuc, vuc, vuc); - VPERM_16QI_UNS_X altivec_vperm_v16qi_uns {} - - const vsq __builtin_vsx_vperm_1ti (vsq, vsq, vsc); - VPERM_1TI_X altivec_vperm_v1ti {} - - const vsq __builtin_vsx_vperm_1ti_uns (vsq, vsq, vsc); - VPERM_1TI_UNS_X altivec_vperm_v1ti_uns {} - - const vd __builtin_vsx_vperm_2df (vd, vd, vuc); - VPERM_2DF_X altivec_vperm_v2df {} - - const vsll __builtin_vsx_vperm_2di (vsll, vsll, vuc); - VPERM_2DI_X altivec_vperm_v2di {} - - const vull __builtin_vsx_vperm_2di_uns (vull, vull, vuc); - VPERM_2DI_UNS_X altivec_vperm_v2di_uns {} - - const vf __builtin_vsx_vperm_4sf (vf, vf, vuc); - VPERM_4SF_X altivec_vperm_v4sf {} - - const vsi __builtin_vsx_vperm_4si (vsi, vsi, vuc); - VPERM_4SI_X altivec_vperm_v4si {} - - const vui __builtin_vsx_vperm_4si_uns (vui, vui, vuc); - VPERM_4SI_UNS_X altivec_vperm_v4si_uns {} - - const vss __builtin_vsx_vperm_8hi (vss, vss, vuc); - VPERM_8HI_X altivec_vperm_v8hi {} - - const vus __builtin_vsx_vperm_8hi_uns (vus, vus, vuc); - VPERM_8HI_UNS_X altivec_vperm_v8hi_uns {} - - const vsll __builtin_vsx_vsigned_v2df (vd); - VEC_VSIGNED_V2DF vsx_xvcvdpsxds {} - - const vsi __builtin_vsx_vsigned_v4sf (vf); - VEC_VSIGNED_V4SF vsx_xvcvspsxws {} - - const vsi __builtin_vsx_vsignede_v2df (vd); - VEC_VSIGNEDE_V2DF vsignede_v2df {} - - const vsi __builtin_vsx_vsignedo_v2df (vd); - VEC_VSIGNEDO_V2DF vsignedo_v2df {} - - const vsll __builtin_vsx_vunsigned_v2df (vd); - VEC_VUNSIGNED_V2DF vsx_xvcvdpsxds {} - - const vsi __builtin_vsx_vunsigned_v4sf (vf); - VEC_VUNSIGNED_V4SF vsx_xvcvspsxws {} - - const vsi __builtin_vsx_vunsignede_v2df (vd); - VEC_VUNSIGNEDE_V2DF vunsignede_v2df {} - - const vsi __builtin_vsx_vunsignedo_v2df (vd); - VEC_VUNSIGNEDO_V2DF vunsignedo_v2df {} - - const vf __builtin_vsx_xscvdpsp (double); - XSCVDPSP vsx_xscvdpsp {} - - const double __builtin_vsx_xscvspdp (vf); - XSCVSPDP vsx_xscvspdp {} - - const double __builtin_vsx_xsmaxdp (double, double); - XSMAXDP smaxdf3 {} - - const double __builtin_vsx_xsmindp (double, double); - XSMINDP smindf3 {} - - const double __builtin_vsx_xsrdpi (double); - XSRDPI vsx_xsrdpi {} - - const double __builtin_vsx_xsrdpic (double); - XSRDPIC vsx_xsrdpic {} - - const double __builtin_vsx_xsrdpim (double); - XSRDPIM floordf2 {} - - const double __builtin_vsx_xsrdpip (double); - XSRDPIP ceildf2 {} - - const double __builtin_vsx_xsrdpiz (double); - XSRDPIZ btruncdf2 {} - - const signed int __builtin_vsx_xstdivdp_fe (double, double); - XSTDIVDP_FE vsx_tdivdf3_fe {} - - const signed int __builtin_vsx_xstdivdp_fg (double, double); - XSTDIVDP_FG vsx_tdivdf3_fg {} - - const signed int __builtin_vsx_xstsqrtdp_fe (double); - XSTSQRTDP_FE vsx_tsqrtdf2_fe {} - - const signed int __builtin_vsx_xstsqrtdp_fg (double); - XSTSQRTDP_FG vsx_tsqrtdf2_fg {} - - const vd __builtin_vsx_xvabsdp (vd); - XVABSDP absv2df2 {} - - const vf __builtin_vsx_xvabssp (vf); - XVABSSP absv4sf2 {} - - fpmath vd __builtin_vsx_xvadddp (vd, vd); - XVADDDP addv2df3 {} - - fpmath vf __builtin_vsx_xvaddsp (vf, vf); - XVADDSP addv4sf3 {} - - const vd __builtin_vsx_xvcmpeqdp (vd, vd); - XVCMPEQDP vector_eqv2df {} - - const signed int __builtin_vsx_xvcmpeqdp_p (signed int, vd, vd); - XVCMPEQDP_P vector_eq_v2df_p {pred} - - const vf __builtin_vsx_xvcmpeqsp (vf, vf); - XVCMPEQSP vector_eqv4sf {} - - const signed int __builtin_vsx_xvcmpeqsp_p (signed int, vf, vf); - XVCMPEQSP_P vector_eq_v4sf_p {pred} - - const vd __builtin_vsx_xvcmpgedp (vd, vd); - XVCMPGEDP vector_gev2df {} - - const signed int __builtin_vsx_xvcmpgedp_p (signed int, vd, vd); - XVCMPGEDP_P vector_ge_v2df_p {pred} - - const vf __builtin_vsx_xvcmpgesp (vf, vf); - XVCMPGESP vector_gev4sf {} - - const signed int __builtin_vsx_xvcmpgesp_p (signed int, vf, vf); - XVCMPGESP_P vector_ge_v4sf_p {pred} - - const vd __builtin_vsx_xvcmpgtdp (vd, vd); - XVCMPGTDP vector_gtv2df {} - - const signed int __builtin_vsx_xvcmpgtdp_p (signed int, vd, vd); - XVCMPGTDP_P vector_gt_v2df_p {pred} - - const vf __builtin_vsx_xvcmpgtsp (vf, vf); - XVCMPGTSP vector_gtv4sf {} - - const signed int __builtin_vsx_xvcmpgtsp_p (signed int, vf, vf); - XVCMPGTSP_P vector_gt_v4sf_p {pred} - - const vf __builtin_vsx_xvcvdpsp (vd); - XVCVDPSP vsx_xvcvdpsp {} - - const vsll __builtin_vsx_xvcvdpsxds (vd); - XVCVDPSXDS vsx_fix_truncv2dfv2di2 {} - - const vsll __builtin_vsx_xvcvdpsxds_scale (vd, const int); - XVCVDPSXDS_SCALE vsx_xvcvdpsxds_scale {} - - const vsi __builtin_vsx_xvcvdpsxws (vd); - XVCVDPSXWS vsx_xvcvdpsxws {} - - const vsll __builtin_vsx_xvcvdpuxds (vd); - XVCVDPUXDS vsx_fixuns_truncv2dfv2di2 {} - - const vsll __builtin_vsx_xvcvdpuxds_scale (vd, const int); - XVCVDPUXDS_SCALE vsx_xvcvdpuxds_scale {} - - const vull __builtin_vsx_xvcvdpuxds_uns (vd); - XVCVDPUXDS_UNS vsx_fixuns_truncv2dfv2di2 {} - - const vsi __builtin_vsx_xvcvdpuxws (vd); - XVCVDPUXWS vsx_xvcvdpuxws {} - - const vd __builtin_vsx_xvcvspdp (vf); - XVCVSPDP vsx_xvcvspdp {} - - const vsll __builtin_vsx_xvcvspsxds (vf); - XVCVSPSXDS vsx_xvcvspsxds {} - - const vsi __builtin_vsx_xvcvspsxws (vf); - XVCVSPSXWS vsx_fix_truncv4sfv4si2 {} - - const vsll __builtin_vsx_xvcvspuxds (vf); - XVCVSPUXDS vsx_xvcvspuxds {} - - const vsi __builtin_vsx_xvcvspuxws (vf); - XVCVSPUXWS vsx_fixuns_truncv4sfv4si2 {} - - const vd __builtin_vsx_xvcvsxddp (vsll); - XVCVSXDDP vsx_floatv2div2df2 {} - - const vd __builtin_vsx_xvcvsxddp_scale (vsll, const int<5>); - XVCVSXDDP_SCALE vsx_xvcvsxddp_scale {} - - const vf __builtin_vsx_xvcvsxdsp (vsll); - XVCVSXDSP vsx_xvcvsxdsp {} - - const vd __builtin_vsx_xvcvsxwdp (vsi); - XVCVSXWDP vsx_xvcvsxwdp {} - - const vf __builtin_vsx_xvcvsxwsp (vsi); - XVCVSXWSP vsx_floatv4siv4sf2 {} - - const vd __builtin_vsx_xvcvuxddp (vsll); - XVCVUXDDP vsx_floatunsv2div2df2 {} - - const vd __builtin_vsx_xvcvuxddp_scale (vsll, const int<5>); - XVCVUXDDP_SCALE vsx_xvcvuxddp_scale {} - - const vd __builtin_vsx_xvcvuxddp_uns (vull); - XVCVUXDDP_UNS vsx_floatunsv2div2df2 {} - - const vf __builtin_vsx_xvcvuxdsp (vull); - XVCVUXDSP vsx_xvcvuxdsp {} - - const vd __builtin_vsx_xvcvuxwdp (vsi); - XVCVUXWDP vsx_xvcvuxwdp {} - - const vf __builtin_vsx_xvcvuxwsp (vsi); - XVCVUXWSP vsx_floatunsv4siv4sf2 {} - - fpmath vd __builtin_vsx_xvdivdp (vd, vd); - XVDIVDP divv2df3 {} - - fpmath vf __builtin_vsx_xvdivsp (vf, vf); - XVDIVSP divv4sf3 {} - - const vd __builtin_vsx_xvmadddp (vd, vd, vd); - XVMADDDP fmav2df4 {} - - const vf __builtin_vsx_xvmaddsp (vf, vf, vf); - XVMADDSP fmav4sf4 {} - - const vd __builtin_vsx_xvmaxdp (vd, vd); - XVMAXDP smaxv2df3 {} - - const vf __builtin_vsx_xvmaxsp (vf, vf); - XVMAXSP smaxv4sf3 {} - - const vd __builtin_vsx_xvmindp (vd, vd); - XVMINDP sminv2df3 {} - - const vf __builtin_vsx_xvminsp (vf, vf); - XVMINSP sminv4sf3 {} - - const vd __builtin_vsx_xvmsubdp (vd, vd, vd); - XVMSUBDP fmsv2df4 {} - - const vf __builtin_vsx_xvmsubsp (vf, vf, vf); - XVMSUBSP fmsv4sf4 {} - - fpmath vd __builtin_vsx_xvmuldp (vd, vd); - XVMULDP mulv2df3 {} - - fpmath vf __builtin_vsx_xvmulsp (vf, vf); - XVMULSP mulv4sf3 {} - - const vd __builtin_vsx_xvnabsdp (vd); - XVNABSDP vsx_nabsv2df2 {} - - const vf __builtin_vsx_xvnabssp (vf); - XVNABSSP vsx_nabsv4sf2 {} - - const vd __builtin_vsx_xvnegdp (vd); - XVNEGDP negv2df2 {} - - const vf __builtin_vsx_xvnegsp (vf); - XVNEGSP negv4sf2 {} - - const vd __builtin_vsx_xvnmadddp (vd, vd, vd); - XVNMADDDP nfmav2df4 {} - - const vf __builtin_vsx_xvnmaddsp (vf, vf, vf); - XVNMADDSP nfmav4sf4 {} - - const vd __builtin_vsx_xvnmsubdp (vd, vd, vd); - XVNMSUBDP nfmsv2df4 {} - - const vf __builtin_vsx_xvnmsubsp (vf, vf, vf); - XVNMSUBSP nfmsv4sf4 {} - - const vd __builtin_vsx_xvrdpi (vd); - XVRDPI vsx_xvrdpi {} - - const vd __builtin_vsx_xvrdpic (vd); - XVRDPIC vsx_xvrdpic {} - - const vd __builtin_vsx_xvrdpim (vd); - XVRDPIM vsx_floorv2df2 {} - - const vd __builtin_vsx_xvrdpip (vd); - XVRDPIP vsx_ceilv2df2 {} - - const vd __builtin_vsx_xvrdpiz (vd); - XVRDPIZ vsx_btruncv2df2 {} - - fpmath vd __builtin_vsx_xvrecipdivdp (vd, vd); - RECIP_V2DF recipv2df3 {} - - fpmath vf __builtin_vsx_xvrecipdivsp (vf, vf); - RECIP_V4SF recipv4sf3 {} - - const vd __builtin_vsx_xvredp (vd); - XVREDP vsx_frev2df2 {} - - const vf __builtin_vsx_xvresp (vf); - XVRESP vsx_frev4sf2 {} - - const vf __builtin_vsx_xvrspi (vf); - XVRSPI vsx_xvrspi {} - - const vf __builtin_vsx_xvrspic (vf); - XVRSPIC vsx_xvrspic {} - - const vf __builtin_vsx_xvrspim (vf); - XVRSPIM vsx_floorv4sf2 {} - - const vf __builtin_vsx_xvrspip (vf); - XVRSPIP vsx_ceilv4sf2 {} - - const vf __builtin_vsx_xvrspiz (vf); - XVRSPIZ vsx_btruncv4sf2 {} - - const vd __builtin_vsx_xvrsqrtdp (vd); - RSQRT_2DF rsqrtv2df2 {} - - const vf __builtin_vsx_xvrsqrtsp (vf); - RSQRT_4SF rsqrtv4sf2 {} - - const vd __builtin_vsx_xvrsqrtedp (vd); - XVRSQRTEDP rsqrtev2df2 {} - - const vf __builtin_vsx_xvrsqrtesp (vf); - XVRSQRTESP rsqrtev4sf2 {} - - const vd __builtin_vsx_xvsqrtdp (vd); - XVSQRTDP sqrtv2df2 {} - - const vf __builtin_vsx_xvsqrtsp (vf); - XVSQRTSP sqrtv4sf2 {} - - fpmath vd __builtin_vsx_xvsubdp (vd, vd); - XVSUBDP subv2df3 {} - - fpmath vf __builtin_vsx_xvsubsp (vf, vf); - XVSUBSP subv4sf3 {} - - const signed int __builtin_vsx_xvtdivdp_fe (vd, vd); - XVTDIVDP_FE vsx_tdivv2df3_fe {} - - const signed int __builtin_vsx_xvtdivdp_fg (vd, vd); - XVTDIVDP_FG vsx_tdivv2df3_fg {} - - const signed int __builtin_vsx_xvtdivsp_fe (vf, vf); - XVTDIVSP_FE vsx_tdivv4sf3_fe {} - - const signed int __builtin_vsx_xvtdivsp_fg (vf, vf); - XVTDIVSP_FG vsx_tdivv4sf3_fg {} - - const signed int __builtin_vsx_xvtsqrtdp_fe (vd); - XVTSQRTDP_FE vsx_tsqrtv2df2_fe {} - - const signed int __builtin_vsx_xvtsqrtdp_fg (vd); - XVTSQRTDP_FG vsx_tsqrtv2df2_fg {} - - const signed int __builtin_vsx_xvtsqrtsp_fe (vf); - XVTSQRTSP_FE vsx_tsqrtv4sf2_fe {} - - const signed int __builtin_vsx_xvtsqrtsp_fg (vf); - XVTSQRTSP_FG vsx_tsqrtv4sf2_fg {} - - const vf __builtin_vsx_xxmrghw (vf, vf); - XXMRGHW_4SF vsx_xxmrghw_v4sf {} - - const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi); - XXMRGHW_4SI vsx_xxmrghw_v4si {} - - const vf __builtin_vsx_xxmrglw (vf, vf); - XXMRGLW_4SF vsx_xxmrglw_v4sf {} - - const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi); - XXMRGLW_4SI vsx_xxmrglw_v4si {} - - const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<2>); - XXPERMDI_16QI vsx_xxpermdi_v16qi {} - - const vsq __builtin_vsx_xxpermdi_1ti (vsq, vsq, const int<2>); - XXPERMDI_1TI vsx_xxpermdi_v1ti {} - - const vd __builtin_vsx_xxpermdi_2df (vd, vd, const int<2>); - XXPERMDI_2DF vsx_xxpermdi_v2df {} - - const vsll __builtin_vsx_xxpermdi_2di (vsll, vsll, const int<2>); - XXPERMDI_2DI vsx_xxpermdi_v2di {} - - const vf __builtin_vsx_xxpermdi_4sf (vf, vf, const int<2>); - XXPERMDI_4SF vsx_xxpermdi_v4sf {} - - const vsi __builtin_vsx_xxpermdi_4si (vsi, vsi, const int<2>); - XXPERMDI_4SI vsx_xxpermdi_v4si {} - - const vss __builtin_vsx_xxpermdi_8hi (vss, vss, const int<2>); - XXPERMDI_8HI vsx_xxpermdi_v8hi {} - - const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc); - XXSEL_16QI vector_select_v16qi {} - - const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc); - XXSEL_16QI_UNS vector_select_v16qi_uns {} - - const vsq __builtin_vsx_xxsel_1ti (vsq, vsq, vsq); - XXSEL_1TI vector_select_v1ti {} - - const vsq __builtin_vsx_xxsel_1ti_uns (vsq, vsq, vsq); - XXSEL_1TI_UNS vector_select_v1ti_uns {} - - const vd __builtin_vsx_xxsel_2df (vd, vd, vd); - XXSEL_2DF vector_select_v2df {} - - const vsll __builtin_vsx_xxsel_2di (vsll, vsll, vsll); - XXSEL_2DI vector_select_v2di {} - - const vull __builtin_vsx_xxsel_2di_uns (vull, vull, vull); - XXSEL_2DI_UNS vector_select_v2di_uns {} - - const vf __builtin_vsx_xxsel_4sf (vf, vf, vf); - XXSEL_4SF vector_select_v4sf {} - - const vsi __builtin_vsx_xxsel_4si (vsi, vsi, vsi); - XXSEL_4SI vector_select_v4si {} - - const vui __builtin_vsx_xxsel_4si_uns (vui, vui, vui); - XXSEL_4SI_UNS vector_select_v4si_uns {} - - const vss __builtin_vsx_xxsel_8hi (vss, vss, vss); - XXSEL_8HI vector_select_v8hi {} - - const vus __builtin_vsx_xxsel_8hi_uns (vus, vus, vus); - XXSEL_8HI_UNS vector_select_v8hi_uns {} - - const vsc __builtin_vsx_xxsldwi_16qi (vsc, vsc, const int<2>); - XXSLDWI_16QI vsx_xxsldwi_v16qi {} - - const vd __builtin_vsx_xxsldwi_2df (vd, vd, const int<2>); - XXSLDWI_2DF vsx_xxsldwi_v2df {} - - const vsll __builtin_vsx_xxsldwi_2di (vsll, vsll, const int<2>); - XXSLDWI_2DI vsx_xxsldwi_v2di {} - - const vf __builtin_vsx_xxsldwi_4sf (vf, vf, const int<2>); - XXSLDWI_4SF vsx_xxsldwi_v4sf {} - - const vsi __builtin_vsx_xxsldwi_4si (vsi, vsi, const int<2>); - XXSLDWI_4SI vsx_xxsldwi_v4si {} - - const vss __builtin_vsx_xxsldwi_8hi (vss, vss, const int<2>); - XXSLDWI_8HI vsx_xxsldwi_v8hi {} - - const vd __builtin_vsx_xxspltd_2df (vd, const int<1>); - XXSPLTD_V2DF vsx_xxspltd_v2df {} - - const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>); - XXSPLTD_V2DI vsx_xxspltd_v2di {} - - -; Power7 builtins (ISA 2.06). -[power7] - const unsigned int __builtin_addg6s (unsigned int, unsigned int); - ADDG6S addg6s {} - - const signed long __builtin_bpermd (signed long, signed long); - BPERMD bpermd_di {32bit} - - const unsigned int __builtin_cbcdtd (unsigned int); - CBCDTD cbcdtd {} - - const unsigned int __builtin_cdtbcd (unsigned int); - CDTBCD cdtbcd {} - - const signed int __builtin_divwe (signed int, signed int); - DIVWE dive_si {} - - const unsigned int __builtin_divweu (unsigned int, unsigned int); - DIVWEU diveu_si {} - - const vsq __builtin_pack_vector_int128 (unsigned long long, \ - unsigned long long); - PACK_V1TI packv1ti {} - - void __builtin_ppc_speculation_barrier (); - SPECBARR speculation_barrier {} - - const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); - UNPACK_V1TI unpackv1ti {} - - -; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing). -[power7-64] - const signed long long __builtin_divde (signed long long, signed long long); - DIVDE dive_di {} - - const unsigned long long __builtin_divdeu (unsigned long long, \ - unsigned long long); - DIVDEU diveu_di {} - - -; Power8 vector built-ins. -[power8-vector] - const vsll __builtin_altivec_abs_v2di (vsll); - ABS_V2DI absv2di2 {} - - const vsc __builtin_altivec_bcddiv10_v16qi (vsc); - BCDDIV10_V16QI bcddiv10_v16qi {} - - const vsc __builtin_altivec_bcdmul10_v16qi (vsc); - BCDMUL10_V16QI bcdmul10_v16qi {} - - const vsc __builtin_altivec_eqv_v16qi (vsc, vsc); - EQV_V16QI eqvv16qi3 {} - - const vuc __builtin_altivec_eqv_v16qi_uns (vuc, vuc); - EQV_V16QI_UNS eqvv16qi3 {} - - const vsq __builtin_altivec_eqv_v1ti (vsq, vsq); - EQV_V1TI eqvv1ti3 {} - - const vuq __builtin_altivec_eqv_v1ti_uns (vuq, vuq); - EQV_V1TI_UNS eqvv1ti3 {} - - const vd __builtin_altivec_eqv_v2df (vd, vd); - EQV_V2DF eqvv2df3 {} - - const vsll __builtin_altivec_eqv_v2di (vsll, vsll); - EQV_V2DI eqvv2di3 {} - - const vull __builtin_altivec_eqv_v2di_uns (vull, vull); - EQV_V2DI_UNS eqvv2di3 {} - - const vf __builtin_altivec_eqv_v4sf (vf, vf); - EQV_V4SF eqvv4sf3 {} - - const vsi __builtin_altivec_eqv_v4si (vsi, vsi); - EQV_V4SI eqvv4si3 {} - - const vui __builtin_altivec_eqv_v4si_uns (vui, vui); - EQV_V4SI_UNS eqvv4si3 {} - - const vss __builtin_altivec_eqv_v8hi (vss, vss); - EQV_V8HI eqvv8hi3 {} - - const vus __builtin_altivec_eqv_v8hi_uns (vus, vus); - EQV_V8HI_UNS eqvv8hi3 {} - - const vsc __builtin_altivec_nand_v16qi (vsc, vsc); - NAND_V16QI nandv16qi3 {} - - const vuc __builtin_altivec_nand_v16qi_uns (vuc, vuc); - NAND_V16QI_UNS nandv16qi3 {} - - const vsq __builtin_altivec_nand_v1ti (vsq, vsq); - NAND_V1TI nandv1ti3 {} - - const vuq __builtin_altivec_nand_v1ti_uns (vuq, vuq); - NAND_V1TI_UNS nandv1ti3 {} - - const vd __builtin_altivec_nand_v2df (vd, vd); - NAND_V2DF nandv2df3 {} - - const vsll __builtin_altivec_nand_v2di (vsll, vsll); - NAND_V2DI nandv2di3 {} - - const vull __builtin_altivec_nand_v2di_uns (vull, vull); - NAND_V2DI_UNS nandv2di3 {} - - const vf __builtin_altivec_nand_v4sf (vf, vf); - NAND_V4SF nandv4sf3 {} - - const vsi __builtin_altivec_nand_v4si (vsi, vsi); - NAND_V4SI nandv4si3 {} - - const vui __builtin_altivec_nand_v4si_uns (vui, vui); - NAND_V4SI_UNS nandv4si3 {} - - const vss __builtin_altivec_nand_v8hi (vss, vss); - NAND_V8HI nandv8hi3 {} - - const vus __builtin_altivec_nand_v8hi_uns (vus, vus); - NAND_V8HI_UNS nandv8hi3 {} - - const vsc __builtin_altivec_neg_v16qi (vsc); - NEG_V16QI negv16qi2 {} - - const vd __builtin_altivec_neg_v2df (vd); - NEG_V2DF negv2df2 {} - - const vsll __builtin_altivec_neg_v2di (vsll); - NEG_V2DI negv2di2 {} - - const vf __builtin_altivec_neg_v4sf (vf); - NEG_V4SF negv4sf2 {} - - const vsi __builtin_altivec_neg_v4si (vsi); - NEG_V4SI negv4si2 {} - - const vss __builtin_altivec_neg_v8hi (vss); - NEG_V8HI negv8hi2 {} - - const vsc __builtin_altivec_orc_v16qi (vsc, vsc); - ORC_V16QI orcv16qi3 {} - - const vuc __builtin_altivec_orc_v16qi_uns (vuc, vuc); - ORC_V16QI_UNS orcv16qi3 {} - - const vsq __builtin_altivec_orc_v1ti (vsq, vsq); - ORC_V1TI orcv1ti3 {} - - const vuq __builtin_altivec_orc_v1ti_uns (vuq, vuq); - ORC_V1TI_UNS orcv1ti3 {} - - const vd __builtin_altivec_orc_v2df (vd, vd); - ORC_V2DF orcv2df3 {} - - const vsll __builtin_altivec_orc_v2di (vsll, vsll); - ORC_V2DI orcv2di3 {} - - const vull __builtin_altivec_orc_v2di_uns (vull, vull); - ORC_V2DI_UNS orcv2di3 {} - - const vf __builtin_altivec_orc_v4sf (vf, vf); - ORC_V4SF orcv4sf3 {} - - const vsi __builtin_altivec_orc_v4si (vsi, vsi); - ORC_V4SI orcv4si3 {} - - const vui __builtin_altivec_orc_v4si_uns (vui, vui); - ORC_V4SI_UNS orcv4si3 {} - - const vss __builtin_altivec_orc_v8hi (vss, vss); - ORC_V8HI orcv8hi3 {} - - const vus __builtin_altivec_orc_v8hi_uns (vus, vus); - ORC_V8HI_UNS orcv8hi3 {} - - const vsc __builtin_altivec_vclzb (vsc); - VCLZB clzv16qi2 {} - - const vsll __builtin_altivec_vclzd (vsll); - VCLZD clzv2di2 {} - - const vss __builtin_altivec_vclzh (vss); - VCLZH clzv8hi2 {} - - const vsi __builtin_altivec_vclzw (vsi); - VCLZW clzv4si2 {} - - const vuc __builtin_altivec_vgbbd (vuc); - VGBBD p8v_vgbbd {} - - const vsq __builtin_altivec_vaddcuq (vsq, vsq); - VADDCUQ altivec_vaddcuq {} - - const vsq __builtin_altivec_vaddecuq (vsq, vsq, vsq); - VADDECUQ altivec_vaddecuq {} - - const vsq __builtin_altivec_vaddeuqm (vsq, vsq, vsq); - VADDEUQM altivec_vaddeuqm {} - - const vsll __builtin_altivec_vaddudm (vsll, vsll); - VADDUDM addv2di3 {} - - const vsq __builtin_altivec_vadduqm (vsq, vsq); - VADDUQM altivec_vadduqm {} - - const vsll __builtin_altivec_vbpermq (vsc, vsc); - VBPERMQ altivec_vbpermq {} - - const vsc __builtin_altivec_vbpermq2 (vsc, vsc); - VBPERMQ2 altivec_vbpermq2 {} - - const vsll __builtin_altivec_vcmpequd (vull, vull); - VCMPEQUD vector_eqv2di {} - - const int __builtin_altivec_vcmpequd_p (int, vsll, vsll); - VCMPEQUD_P vector_eq_v2di_p {pred} - - const vsll __builtin_altivec_vcmpgtsd (vsll, vsll); - VCMPGTSD vector_gtv2di {} - - const int __builtin_altivec_vcmpgtsd_p (int, vsll, vsll); - VCMPGTSD_P vector_gt_v2di_p {pred} - - const vsll __builtin_altivec_vcmpgtud (vull, vull); - VCMPGTUD vector_gtuv2di {} - - const int __builtin_altivec_vcmpgtud_p (int, vsll, vsll); - VCMPGTUD_P vector_gtu_v2di_p {pred} - - const vsll __builtin_altivec_vmaxsd (vsll, vsll); - VMAXSD smaxv2di3 {} - - const vull __builtin_altivec_vmaxud (vull, vull); - VMAXUD umaxv2di3 {} - - const vsll __builtin_altivec_vminsd (vsll, vsll); - VMINSD sminv2di3 {} - - const vull __builtin_altivec_vminud (vull, vull); - VMINUD uminv2di3 {} - - const vd __builtin_altivec_vmrgew_v2df (vd, vd); - VMRGEW_V2DF p8_vmrgew_v2df {} - - const vsll __builtin_altivec_vmrgew_v2di (vsll, vsll); - VMRGEW_V2DI p8_vmrgew_v2di {} - - const vf __builtin_altivec_vmrgew_v4sf (vf, vf); - VMRGEW_V4SF p8_vmrgew_v4sf {} - - const vsi __builtin_altivec_vmrgew_v4si (vsi, vsi); - VMRGEW_V4SI p8_vmrgew_v4si {} - - const vd __builtin_altivec_vmrgow_v2df (vd, vd); - VMRGOW_V2DF p8_vmrgow_v2df {} - - const vsll __builtin_altivec_vmrgow_v2di (vsll, vsll); - VMRGOW_V2DI p8_vmrgow_v2di {} - - const vf __builtin_altivec_vmrgow_v4sf (vf, vf); - VMRGOW_V4SF p8_vmrgow_v4sf {} - - const vsi __builtin_altivec_vmrgow_v4si (vsi, vsi); - VMRGOW_V4SI p8_vmrgow_v4si {} - - const vsc __builtin_altivec_vpermxor (vsc, vsc, vsc); - VPERMXOR altivec_vpermxor {} - - const vsi __builtin_altivec_vpksdss (vsll, vsll); - VPKSDSS altivec_vpksdss {} - - const vsi __builtin_altivec_vpksdus (vsll, vsll); - VPKSDUS altivec_vpksdus {} - - const vsi __builtin_altivec_vpkudum (vsll, vsll); - VPKUDUM altivec_vpkudum {} - - const vsi __builtin_altivec_vpkudus (vsll, vsll); - VPKUDUS altivec_vpkudus {} - - const vsc __builtin_altivec_vpmsumb (vsc, vsc); - VPMSUMB_A crypto_vpmsumb {} - - const vsll __builtin_altivec_vpmsumd (vsll, vsll); - VPMSUMD_A crypto_vpmsumd {} - - const vss __builtin_altivec_vpmsumh (vss, vss); - VPMSUMH_A crypto_vpmsumh {} - - const vsi __builtin_altivec_vpmsumw (vsi, vsi); - VPMSUMW_A crypto_vpmsumw {} - - const vsc __builtin_altivec_vpopcntb (vsc); - VPOPCNTB popcountv16qi2 {} - - const vsll __builtin_altivec_vpopcntd (vsll); - VPOPCNTD popcountv2di2 {} - - const vss __builtin_altivec_vpopcnth (vss); - VPOPCNTH popcountv8hi2 {} - - const vsc __builtin_altivec_vpopcntub (vsc); - VPOPCNTUB popcountv16qi2 {} - - const vsll __builtin_altivec_vpopcntud (vsll); - VPOPCNTUD popcountv2di2 {} - - const vss __builtin_altivec_vpopcntuh (vss); - VPOPCNTUH popcountv8hi2 {} - - const vsi __builtin_altivec_vpopcntuw (vsi); - VPOPCNTUW popcountv4si2 {} - - const vsi __builtin_altivec_vpopcntw (vsi); - VPOPCNTW popcountv4si2 {} - - const vsll __builtin_altivec_vrld (vsll, vsll); - VRLD vrotlv2di3 {} - - const vsll __builtin_altivec_vsld (vsll, vsll); - VSLD vashlv2di3 {} - - const vsll __builtin_altivec_vsrad (vsll, vsll); - VSRAD vashrv2di3 {} - - const vsll __builtin_altivec_vsrd (vsll, vull); - VSRD vlshrv2di3 {} - - const vsq __builtin_altivec_vsubcuq (vsq, vsq); - VSUBCUQ altivec_vsubcuq {} - - const vsq __builtin_altivec_vsubecuq (vsq, vsq, vsq); - VSUBECUQ altivec_vsubecuq {} - - const vsq __builtin_altivec_vsubeuqm (vsq, vsq, vsq); - VSUBEUQM altivec_vsubeuqm {} - - const vsll __builtin_altivec_vsubudm (vsll, vsll); - VSUBUDM subv2di3 {} - - const vsq __builtin_altivec_vsubuqm (vsq, vsq); - VSUBUQM altivec_vsubuqm {} - - const vsll __builtin_altivec_vupkhsw (vsi); - VUPKHSW altivec_vupkhsw {} - - const vsll __builtin_altivec_vupklsw (vsi); - VUPKLSW altivec_vupklsw {} - - const vsq __builtin_bcdadd_v1ti (vsq, vsq, const int<1>); - BCDADD_V1TI bcdadd_v1ti {} - - const vsc __builtin_bcdadd_v16qi (vsc, vsc, const int<1>); - BCDADD_V16QI bcdadd_v16qi {} - - const signed int __builtin_bcdadd_eq_v1ti (vsq, vsq, const int<1>); - BCDADD_EQ_V1TI bcdadd_eq_v1ti {} - - const signed int __builtin_bcdadd_eq_v16qi (vsc, vsc, const int<1>); - BCDADD_EQ_V16QI bcdadd_eq_v16qi {} - - const signed int __builtin_bcdadd_gt_v1ti (vsq, vsq, const int<1>); - BCDADD_GT_V1TI bcdadd_gt_v1ti {} - - const signed int __builtin_bcdadd_gt_v16qi (vsc, vsc, const int<1>); - BCDADD_GT_V16QI bcdadd_gt_v16qi {} - - const signed int __builtin_bcdadd_lt_v1ti (vsq, vsq, const int<1>); - BCDADD_LT_V1TI bcdadd_lt_v1ti {} - - const signed int __builtin_bcdadd_lt_v16qi (vsc, vsc, const int<1>); - BCDADD_LT_V16QI bcdadd_lt_v16qi {} - - const signed int __builtin_bcdadd_ov_v1ti (vsq, vsq, const int<1>); - BCDADD_OV_V1TI bcdadd_unordered_v1ti {} - - const signed int __builtin_bcdadd_ov_v16qi (vsc, vsc, const int<1>); - BCDADD_OV_V16QI bcdadd_unordered_v16qi {} - - const signed int __builtin_bcdinvalid_v1ti (vsq); - BCDINVALID_V1TI bcdinvalid_v1ti {} - - const signed int __builtin_bcdinvalid_v16qi (vsc); - BCDINVALID_V16QI bcdinvalid_v16qi {} - - const vsq __builtin_bcdsub_v1ti (vsq, vsq, const int<1>); - BCDSUB_V1TI bcdsub_v1ti {} - - const vsc __builtin_bcdsub_v16qi (vsc, vsc, const int<1>); - BCDSUB_V16QI bcdsub_v16qi {} - - const signed int __builtin_bcdsub_eq_v1ti (vsq, vsq, const int<1>); - BCDSUB_EQ_V1TI bcdsub_eq_v1ti {} - - const signed int __builtin_bcdsub_eq_v16qi (vsc, vsc, const int<1>); - BCDSUB_EQ_V16QI bcdsub_eq_v16qi {} - - const signed int __builtin_bcdsub_ge_v1ti (vsq, vsq, const int<1>); - BCDSUB_GE_V1TI bcdsub_ge_v1ti {} - - const signed int __builtin_bcdsub_ge_v16qi (vsc, vsc, const int<1>); - BCDSUB_GE_V16QI bcdsub_ge_v16qi {} - - const signed int __builtin_bcdsub_gt_v1ti (vsq, vsq, const int<1>); - BCDSUB_GT_V1TI bcdsub_gt_v1ti {} - - const signed int __builtin_bcdsub_gt_v16qi (vsc, vsc, const int<1>); - BCDSUB_GT_V16QI bcdsub_gt_v16qi {} - - const signed int __builtin_bcdsub_le_v1ti (vsq, vsq, const int<1>); - BCDSUB_LE_V1TI bcdsub_le_v1ti {} - - const signed int __builtin_bcdsub_le_v16qi (vsc, vsc, const int<1>); - BCDSUB_LE_V16QI bcdsub_le_v16qi {} - - const signed int __builtin_bcdsub_lt_v1ti (vsq, vsq, const int<1>); - BCDSUB_LT_V1TI bcdsub_lt_v1ti {} - - const signed int __builtin_bcdsub_lt_v16qi (vsc, vsc, const int<1>); - BCDSUB_LT_V16QI bcdsub_lt_v16qi {} - - const signed int __builtin_bcdsub_ov_v1ti (vsq, vsq, const int<1>); - BCDSUB_OV_V1TI bcdsub_unordered_v1ti {} - - const signed int __builtin_bcdsub_ov_v16qi (vsc, vsc, const int<1>); - BCDSUB_OV_V16QI bcdsub_unordered_v16qi {} - - const vuc __builtin_crypto_vpermxor_v16qi (vuc, vuc, vuc); - VPERMXOR_V16QI crypto_vpermxor_v16qi {} - - const vull __builtin_crypto_vpermxor_v2di (vull, vull, vull); - VPERMXOR_V2DI crypto_vpermxor_v2di {} - - const vui __builtin_crypto_vpermxor_v4si (vui, vui, vui); - VPERMXOR_V4SI crypto_vpermxor_v4si {} - - const vus __builtin_crypto_vpermxor_v8hi (vus, vus, vus); - VPERMXOR_V8HI crypto_vpermxor_v8hi {} - - const vuc __builtin_crypto_vpmsumb (vuc, vuc); - VPMSUMB crypto_vpmsumb {} - - const vull __builtin_crypto_vpmsumd (vull, vull); - VPMSUMD crypto_vpmsumd {} - - const vus __builtin_crypto_vpmsumh (vus, vus); - VPMSUMH crypto_vpmsumh {} - - const vui __builtin_crypto_vpmsumw (vui, vui); - VPMSUMW crypto_vpmsumw {} - - const vf __builtin_vsx_float2_v2df (vd, vd); - FLOAT2_V2DF float2_v2df {} - - const vf __builtin_vsx_float2_v2di (vsll, vsll); - FLOAT2_V2DI float2_v2di {} - - const vsc __builtin_vsx_revb_v16qi (vsc); - REVB_V16QI revb_v16qi {} - - const vsq __builtin_vsx_revb_v1ti (vsq); - REVB_V1TI revb_v1ti {} - - const vd __builtin_vsx_revb_v2df (vd); - REVB_V2DF revb_v2df {} - - const vsll __builtin_vsx_revb_v2di (vsll); - REVB_V2DI revb_v2di {} - - const vf __builtin_vsx_revb_v4sf (vf); - REVB_V4SF revb_v4sf {} - - const vsi __builtin_vsx_revb_v4si (vsi); - REVB_V4SI revb_v4si {} - - const vss __builtin_vsx_revb_v8hi (vss); - REVB_V8HI revb_v8hi {} - - const vf __builtin_vsx_uns_float2_v2di (vsll, vsll); - UNS_FLOAT2_V2DI uns_float2_v2di {} - - const vsi __builtin_vsx_vsigned2_v2df (vd, vd); - VEC_VSIGNED2_V2DF vsigned2_v2df {} - - const vsi __builtin_vsx_vunsigned2_v2df (vd, vd); - VEC_VUNSIGNED2_V2DF vunsigned2_v2df {} - - const vf __builtin_vsx_xscvdpspn (double); - XSCVDPSPN vsx_xscvdpspn {} - - const double __builtin_vsx_xscvspdpn (vf); - XSCVSPDPN vsx_xscvspdpn {} - - -; Power9 vector builtins. -[power9-vector] - const vss __builtin_altivec_convert_4f32_8f16 (vf, vf); - CONVERT_4F32_8F16 convert_4f32_8f16 {} - - const vss __builtin_altivec_convert_4f32_8i16 (vf, vf); - CONVERT_4F32_8I16 convert_4f32_8i16 {} - - const signed int __builtin_altivec_first_match_index_v16qi (vsc, vsc); - VFIRSTMATCHINDEX_V16QI first_match_index_v16qi {} - - const signed int __builtin_altivec_first_match_index_v8hi (vss, vss); - VFIRSTMATCHINDEX_V8HI first_match_index_v8hi {} - - const signed int __builtin_altivec_first_match_index_v4si (vsi, vsi); - VFIRSTMATCHINDEX_V4SI first_match_index_v4si {} - - const signed int __builtin_altivec_first_match_or_eos_index_v16qi (vsc, vsc); - VFIRSTMATCHOREOSINDEX_V16QI first_match_or_eos_index_v16qi {} - - const signed int __builtin_altivec_first_match_or_eos_index_v8hi (vss, vss); - VFIRSTMATCHOREOSINDEX_V8HI first_match_or_eos_index_v8hi {} - - const signed int __builtin_altivec_first_match_or_eos_index_v4si (vsi, vsi); - VFIRSTMATCHOREOSINDEX_V4SI first_match_or_eos_index_v4si {} - - const signed int __builtin_altivec_first_mismatch_index_v16qi (vsc, vsc); - VFIRSTMISMATCHINDEX_V16QI first_mismatch_index_v16qi {} - - const signed int __builtin_altivec_first_mismatch_index_v8hi (vss, vss); - VFIRSTMISMATCHINDEX_V8HI first_mismatch_index_v8hi {} - - const signed int __builtin_altivec_first_mismatch_index_v4si (vsi, vsi); - VFIRSTMISMATCHINDEX_V4SI first_mismatch_index_v4si {} - - const signed int \ - __builtin_altivec_first_mismatch_or_eos_index_v16qi (vsc, vsc); - VFIRSTMISMATCHOREOSINDEX_V16QI first_mismatch_or_eos_index_v16qi {} - - const signed int \ - __builtin_altivec_first_mismatch_or_eos_index_v8hi (vss, vss); - VFIRSTMISMATCHOREOSINDEX_V8HI first_mismatch_or_eos_index_v8hi {} - - const signed int \ - __builtin_altivec_first_mismatch_or_eos_index_v4si (vsi, vsi); - VFIRSTMISMATCHOREOSINDEX_V4SI first_mismatch_or_eos_index_v4si {} - - const vsc __builtin_altivec_vadub (vsc, vsc); - VADUB vaduv16qi3 {} - - const vss __builtin_altivec_vaduh (vss, vss); - VADUH vaduv8hi3 {} - - const vsi __builtin_altivec_vaduw (vsi, vsi); - VADUW vaduv4si3 {} - - const vsll __builtin_altivec_vbpermd (vsll, vsc); - VBPERMD altivec_vbpermd {} - - const signed int __builtin_altivec_vclzlsbb_v16qi (vsc); - VCLZLSBB_V16QI vclzlsbb_v16qi {} - - const signed int __builtin_altivec_vclzlsbb_v4si (vsi); - VCLZLSBB_V4SI vclzlsbb_v4si {} - - const signed int __builtin_altivec_vclzlsbb_v8hi (vss); - VCLZLSBB_V8HI vclzlsbb_v8hi {} - - const vsc __builtin_altivec_vctzb (vsc); - VCTZB ctzv16qi2 {} - - const vsll __builtin_altivec_vctzd (vsll); - VCTZD ctzv2di2 {} - - const vss __builtin_altivec_vctzh (vss); - VCTZH ctzv8hi2 {} - - const vsi __builtin_altivec_vctzw (vsi); - VCTZW ctzv4si2 {} - - const signed int __builtin_altivec_vctzlsbb_v16qi (vsc); - VCTZLSBB_V16QI vctzlsbb_v16qi {} - - const signed int __builtin_altivec_vctzlsbb_v4si (vsi); - VCTZLSBB_V4SI vctzlsbb_v4si {} - - const signed int __builtin_altivec_vctzlsbb_v8hi (vss); - VCTZLSBB_V8HI vctzlsbb_v8hi {} - - const signed int __builtin_altivec_vcmpaeb_p (vsc, vsc); - VCMPAEB_P vector_ae_v16qi_p {} - - const signed int __builtin_altivec_vcmpaed_p (vsll, vsll); - VCMPAED_P vector_ae_v2di_p {} - - const signed int __builtin_altivec_vcmpaedp_p (vd, vd); - VCMPAEDP_P vector_ae_v2df_p {} - - const signed int __builtin_altivec_vcmpaefp_p (vf, vf); - VCMPAEFP_P vector_ae_v4sf_p {} - - const signed int __builtin_altivec_vcmpaeh_p (vss, vss); - VCMPAEH_P vector_ae_v8hi_p {} - - const signed int __builtin_altivec_vcmpaew_p (vsi, vsi); - VCMPAEW_P vector_ae_v4si_p {} - - const vsc __builtin_altivec_vcmpneb (vsc, vsc); - VCMPNEB vcmpneb {} - - const signed int __builtin_altivec_vcmpneb_p (vsc, vsc); - VCMPNEB_P vector_ne_v16qi_p {} - - const signed int __builtin_altivec_vcmpned_p (vsll, vsll); - VCMPNED_P vector_ne_v2di_p {} - - const signed int __builtin_altivec_vcmpnedp_p (vd, vd); - VCMPNEDP_P vector_ne_v2df_p {} - - const signed int __builtin_altivec_vcmpnefp_p (vf, vf); - VCMPNEFP_P vector_ne_v4sf_p {} - - const vss __builtin_altivec_vcmpneh (vss, vss); - VCMPNEH vcmpneh {} - - const signed int __builtin_altivec_vcmpneh_p (vss, vss); - VCMPNEH_P vector_ne_v8hi_p {} - - const vsi __builtin_altivec_vcmpnew (vsi, vsi); - VCMPNEW vcmpnew {} - - const signed int __builtin_altivec_vcmpnew_p (vsi, vsi); - VCMPNEW_P vector_ne_v4si_p {} - - const vsc __builtin_altivec_vcmpnezb (vsc, vsc); - CMPNEZB vcmpnezb {} - - const signed int __builtin_altivec_vcmpnezb_p (signed int, vsc, vsc); - VCMPNEZB_P vector_nez_v16qi_p {pred} - - const vss __builtin_altivec_vcmpnezh (vss, vss); - CMPNEZH vcmpnezh {} - - const signed int __builtin_altivec_vcmpnezh_p (signed int, vss, vss); - VCMPNEZH_P vector_nez_v8hi_p {pred} - - const vsi __builtin_altivec_vcmpnezw (vsi, vsi); - CMPNEZW vcmpnezw {} - - const signed int __builtin_altivec_vcmpnezw_p (signed int, vsi, vsi); - VCMPNEZW_P vector_nez_v4si_p {pred} - - const signed int __builtin_altivec_vextublx (signed int, vsc); - VEXTUBLX vextublx {} - - const signed int __builtin_altivec_vextubrx (signed int, vsc); - VEXTUBRX vextubrx {} - - const signed int __builtin_altivec_vextuhlx (signed int, vss); - VEXTUHLX vextuhlx {} - - const signed int __builtin_altivec_vextuhrx (signed int, vss); - VEXTUHRX vextuhrx {} - - const signed int __builtin_altivec_vextuwlx (signed int, vsi); - VEXTUWLX vextuwlx {} - - const signed int __builtin_altivec_vextuwrx (signed int, vsi); - VEXTUWRX vextuwrx {} - - const vsq __builtin_altivec_vmsumudm (vsll, vsll, vsq); - VMSUMUDM altivec_vmsumudm {} - - const vsll __builtin_altivec_vprtybd (vsll); - VPRTYBD parityv2di2 {} - - const vsq __builtin_altivec_vprtybq (vsq); - VPRTYBQ parityv1ti2 {} - - const vsi __builtin_altivec_vprtybw (vsi); - VPRTYBW parityv4si2 {} - - const vsll __builtin_altivec_vrldmi (vsll, vsll, vsll); - VRLDMI altivec_vrldmi {} - - const vsll __builtin_altivec_vrldnm (vsll, vsll); - VRLDNM altivec_vrldnm {} - - const vsi __builtin_altivec_vrlwmi (vsi, vsi, vsi); - VRLWMI altivec_vrlwmi {} - - const vsi __builtin_altivec_vrlwnm (vsi, vsi); - VRLWNM altivec_vrlwnm {} - - const vsll __builtin_altivec_vsignextsb2d (vsc); - VSIGNEXTSB2D vsignextend_qi_v2di {} - - const vsi __builtin_altivec_vsignextsb2w (vsc); - VSIGNEXTSB2W vsignextend_qi_v4si {} - - const vsll __builtin_altivec_visgnextsh2d (vss); - VSIGNEXTSH2D vsignextend_hi_v2di {} - - const vsi __builtin_altivec_vsignextsh2w (vss); - VSIGNEXTSH2W vsignextend_hi_v4si {} - - const vsll __builtin_altivec_vsignextsw2d (vsi); - VSIGNEXTSW2D vsignextend_si_v2di {} - - const vsc __builtin_altivec_vslv (vsc, vsc); - VSLV vslv {} - - const vsc __builtin_altivec_vsrv (vsc, vsc); - VSRV vsrv {} - - const signed int __builtin_scalar_byte_in_range (signed int, signed int); - CMPRB cmprb {} - - const signed int \ - __builtin_scalar_byte_in_either_range (signed int, signed int); - CMPRB2 cmprb2 {} - - const vsll __builtin_vsx_extract4b (vsc, const int[0,12]); - EXTRACT4B extract4b {} - - const vd __builtin_vsx_extract_exp_dp (vd); - VEEDP xvxexpdp {} - - const vf __builtin_vsx_extract_exp_sp (vf); - VEESP xvxexpsp {} - - const vd __builtin_vsx_extract_sig_dp (vd); - VESDP xvxsigdp {} - - const vf __builtin_vsx_extract_sig_sp (vf); - VESSP xvxsigsp {} - - const vsc __builtin_vsx_insert4b (vsi, vsc, const int[0,12]); - INSERT4B insert4b {} - - const vd __builtin_vsx_insert_exp_dp (vd, vd); - VIEDP xviexpdp {} - - const vf __builtin_vsx_insert_exp_sp (vf, vf); - VIESP xviexpsp {} - - const signed int __builtin_vsx_scalar_cmp_exp_dp_eq (double, double); - VSCEDPEQ xscmpexpdp_eq {} - - const signed int __builtin_vsx_scalar_cmp_exp_dp_gt (double, double); - VSCEDPGT xscmpexpdp_gt {} - - const signed int __builtin_vsx_scalar_cmp_exp_dp_lt (double, double); - VSCEDPLT xscmpexpdp_lt {} - - const signed int __builtin_vsx_scalar_cmp_exp_dp_unordered (double, double); - VSCEDPUO xscmpexpdp_unordered {} - - const signed int \ - __builtin_vsx_scalar_test_data_class_dp (double, const int<7>); - VSTDCDP xststdcdp {} - - const signed int \ - __builtin_vsx_scalar_test_data_class_sp (float, const int<7>); - VSTDCSP xststdcsp {} - - const signed int __builtin_vsx_scalar_test_neg_dp (double); - VSTDCNDP xststdcnegdp {} - - const signed int __builtin_vsx_scalar_test_neg_sp (float); - VSTDCNSP xststdcnegsp {} - - const vsll __builtin_vsx_test_data_class_dp (vd, const int<7>); - VTDCDP xvtstdcdp {} - - const vsi __builtin_vsx_test_data_class_sp (vf, const int<7>); - VTDCSP xvtstdcsp {} - - const vf __builtin_vsx_vextract_fp_from_shorth (vss); - VEXTRACT_FP_FROM_SHORTH vextract_fp_from_shorth {} - - const vf __builtin_vsx_vextract_fp_from_shortl (vss); - VEXTRACT_FP_FROM_SHORTL vextract_fp_from_shortl {} - - const vd __builtin_vsx_xxbrd_v2df (vd); - XXBRD_V2DF p9_xxbrd_v2df {} - - const vsll __builtin_vsx_xxbrd_v2di (vsll); - XXBRD_V2DI p9_xxbrd_v2di {} - - const vss __builtin_vsx_xxbrh_v8hi (vss); - XXBRH_V8HI p9_xxbrh_v8hi {} - - const vsc __builtin_vsx_xxbrq_v16qi (vsc); - XXBRQ_V16QI p9_xxbrq_v16qi {} - - const vsq __builtin_vsx_xxbrq_v1ti (vsq); - XXBRQ_V1TI p9_xxbrq_v1ti {} - - const vf __builtin_vsx_xxbrw_v4sf (vf); - XXBRW_V4SF p9_xxbrw_v4sf {} - - const vsi __builtin_vsx_xxbrw_v4si (vsi); - XXBRW_V4SI p9_xxbrw_v4si {} - - -; Miscellaneous P9 functions -[power9] - signed long long __builtin_darn (); - DARN darn {} - - signed int __builtin_darn_32 (); - DARN_32 darn_32 {} - - signed long long __builtin_darn_raw (); - DARN_RAW darn_raw {} - - const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64); - TSTSFI_EQ_DD dfptstsfi_eq_dd {} - - const signed int __builtin_dtstsfi_eq_td (const int<6>, _Decimal128); - TSTSFI_EQ_TD dfptstsfi_eq_td {} - - const signed int __builtin_dtstsfi_gt_dd (const int<6>, _Decimal64); - TSTSFI_GT_DD dfptstsfi_gt_dd {} - - const signed int __builtin_dtstsfi_gt_td (const int<6>, _Decimal128); - TSTSFI_GT_TD dfptstsfi_gt_td {} - - const signed int __builtin_dtstsfi_lt_dd (const int<6>, _Decimal64); - TSTSFI_LT_DD dfptstsfi_lt_dd {} - - const signed int __builtin_dtstsfi_lt_td (const int<6>, _Decimal128); - TSTSFI_LT_TD dfptstsfi_lt_td {} - - const signed int __builtin_dtstsfi_ov_dd (const int<6>, _Decimal64); - TSTSFI_OV_DD dfptstsfi_unordered_dd {} - - const signed int __builtin_dtstsfi_ov_td (const int<6>, _Decimal128); - TSTSFI_OV_TD dfptstsfi_unordered_td {} - - -[power9-64] - void __builtin_altivec_xst_len_r (vsc, void *, long); - XST_LEN_R xst_len_r {} - - void __builtin_altivec_stxvl (vsc, void *, long); - STXVL stxvl {} - - const signed int __builtin_scalar_byte_in_set (signed int, signed long long); - CMPEQB cmpeqb {} - - pure vsc __builtin_vsx_lxvl (const void *, signed long); - LXVL lxvl {} - - const signed long __builtin_vsx_scalar_extract_exp (double); - VSEEDP xsxexpdp {} - - const signed long __builtin_vsx_scalar_extract_sig (double); - VSESDP xsxsigdp {} - - const double __builtin_vsx_scalar_insert_exp (unsigned long long, \ - unsigned long long); - VSIEDP xsiexpdp {} - - const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long); - VSIEDPF xsiexpdpf {} - - pure vsc __builtin_vsx_xl_len_r (void *, signed long); - XL_LEN_R xl_len_r {} - - -; Builtins requiring hardware support for IEEE-128 floating-point. -[ieee128-hw] - fpmath _Float128 __builtin_addf128_round_to_odd (_Float128, _Float128); - ADDF128_ODD addkf3_odd {} - - fpmath _Float128 __builtin_divf128_round_to_odd (_Float128, _Float128); - DIVF128_ODD divkf3_odd {} - - fpmath _Float128 __builtin_fmaf128_round_to_odd (_Float128, _Float128, \ - _Float128); - FMAF128_ODD fmakf4_odd {} - - fpmath _Float128 __builtin_mulf128_round_to_odd (_Float128, _Float128); - MULF128_ODD mulkf3_odd {} - - const signed int __builtin_vsx_scalar_cmp_exp_qp_eq (_Float128, _Float128); - VSCEQPEQ xscmpexpqp_eq_kf {} - - const signed int __builtin_vsx_scalar_cmp_exp_qp_gt (_Float128, _Float128); - VSCEQPGT xscmpexpqp_gt_kf {} - - const signed int __builtin_vsx_scalar_cmp_exp_qp_lt (_Float128, _Float128); - VSCEQPLT xscmpexpqp_lt_kf {} - - const signed int \ - __builtin_vsx_scalar_cmp_exp_qp_unordered (_Float128, _Float128); - VSCEQPUO xscmpexpqp_unordered_kf {} - - fpmath _Float128 __builtin_sqrtf128_round_to_odd (_Float128); - SQRTF128_ODD sqrtkf2_odd {} - - fpmath _Float128 __builtin_subf128_round_to_odd (_Float128, _Float128); - SUBF128_ODD subkf3_odd {} - - fpmath double __builtin_truncf128_round_to_odd (_Float128); - TRUNCF128_ODD trunckfdf2_odd {} - - const signed long long __builtin_vsx_scalar_extract_expq (_Float128); - VSEEQP xsxexpqp_kf {} - - const signed __int128 __builtin_vsx_scalar_extract_sigq (_Float128); - VSESQP xsxsigqp_kf {} - - const _Float128 __builtin_vsx_scalar_insert_exp_q (unsigned __int128, \ - unsigned long long); - VSIEQP xsiexpqp_kf {} - - const _Float128 __builtin_vsx_scalar_insert_exp_qp (_Float128, \ - unsigned long long); - VSIEQPF xsiexpqpf_kf {} - - const signed int __builtin_vsx_scalar_test_data_class_qp (_Float128, \ - const int<7>); - VSTDCQP xststdcqp_kf {} - - const signed int __builtin_vsx_scalar_test_neg_qp (_Float128); - VSTDCNQP xststdcnegqp_kf {} - - - -; Decimal floating-point builtins. -[dfp] - const _Decimal64 __builtin_ddedpd (const int<2>, _Decimal64); - DDEDPD dfp_ddedpd_dd {} - - const _Decimal128 __builtin_ddedpdq (const int<2>, _Decimal128); - DDEDPDQ dfp_ddedpd_td {} - - const _Decimal64 __builtin_denbcd (const int<1>, _Decimal64); - DENBCD dfp_denbcd_dd {} - - const _Decimal128 __builtin_denbcdq (const int<1>, _Decimal128); - DENBCDQ dfp_denbcd_td {} - - const _Decimal128 __builtin_denb2dfp_v16qi (vsc); - DENB2DFP_V16QI dfp_denbcd_v16qi {} - - const _Decimal64 __builtin_diex (signed long long, _Decimal64); - DIEX dfp_diex_dd {} - - const _Decimal128 __builtin_diexq (signed long long, _Decimal128); - DIEXQ dfp_diex_td {} - - const _Decimal64 __builtin_dscli (_Decimal64, const int<6>); - DSCLI dfp_dscli_dd {} - - const _Decimal128 __builtin_dscliq (_Decimal128, const int<6>); - DSCLIQ dfp_dscli_td {} - - const _Decimal64 __builtin_dscri (_Decimal64, const int<6>); - DSCRI dfp_dscri_dd {} - - const _Decimal128 __builtin_dscriq (_Decimal128, const int<6>); - DSCRIQ dfp_dscri_td {} - - const signed long long __builtin_dxex (_Decimal64); - DXEX dfp_dxex_dd {} - - const signed long long __builtin_dxexq (_Decimal128); - DXEXQ dfp_dxex_td {} - - const _Decimal128 __builtin_pack_dec128 (unsigned long long, \ - unsigned long long); - PACK_TD packtd {} - - void __builtin_set_fpscr_drn (const int[0,7]); - SET_FPSCR_DRN rs6000_set_fpscr_drn {} - - const unsigned long long __builtin_unpack_dec128 (_Decimal128, const int<1>); - UNPACK_TD unpacktd {} - - -[crypto] - const vull __builtin_crypto_vcipher (vull, vull); - VCIPHER crypto_vcipher_v2di {} - - const vuc __builtin_crypto_vcipher_be (vuc, vuc); - VCIPHER_BE crypto_vcipher_v16qi {} - - const vull __builtin_crypto_vcipherlast (vull, vull); - VCIPHERLAST crypto_vcipherlast_v2di {} - - const vuc __builtin_crypto_vcipherlast_be (vuc, vuc); - VCIPHERLAST_BE crypto_vcipherlast_v16qi {} - - const vull __builtin_crypto_vncipher (vull, vull); - VNCIPHER crypto_vncipher_v2di {} - - const vuc __builtin_crypto_vncipher_be (vuc, vuc); - VNCIPHER_BE crypto_vncipher_v16qi {} - - const vull __builtin_crypto_vncipherlast (vull, vull); - VNCIPHERLAST crypto_vncipherlast_v2di {} - - const vuc __builtin_crypto_vncipherlast_be (vuc, vuc); - VNCIPHERLAST_BE crypto_vncipherlast_v16qi {} - - const vull __builtin_crypto_vsbox (vull); - VSBOX crypto_vsbox_v2di {} - - const vuc __builtin_crypto_vsbox_be (vuc); - VSBOX_BE crypto_vsbox_v16qi {} - - const vull __builtin_crypto_vshasigmad (vull, const int<1>, const int<4>); - VSHASIGMAD crypto_vshasigmad {} - - const vui __builtin_crypto_vshasigmaw (vui, const int<1>, const int<4>); - VSHASIGMAW crypto_vshasigmaw {} - - -[htm] - unsigned long __builtin_get_texasr (); - GET_TEXASR nothing {htm,htmspr} - - unsigned long __builtin_get_texasru (); - GET_TEXASRU nothing {htm,htmspr} - - unsigned long __builtin_get_tfhar (); - GET_TFHAR nothing {htm,htmspr} - - unsigned long __builtin_get_tfiar (); - GET_TFIAR nothing {htm,htmspr} - - void __builtin_set_texasr (unsigned long); - SET_TEXASR nothing {htm,htmspr} - - void __builtin_set_texasru (unsigned long); - SET_TEXASRU nothing {htm,htmspr} - - void __builtin_set_tfhar (unsigned long); - SET_TFHAR nothing {htm,htmspr} - - void __builtin_set_tfiar (unsigned long); - SET_TFIAR nothing {htm,htmspr} - - unsigned int __builtin_tabort (unsigned int); - TABORT tabort {htm,htmcr} - - unsigned int __builtin_tabortdc (unsigned long, unsigned long, \ - unsigned long); - TABORTDC tabortdc {htm,htmcr} - - unsigned int __builtin_tabortdci (unsigned long, unsigned long, \ - unsigned long); - TABORTDCI tabortdci {htm,htmcr} - - unsigned int __builtin_tabortwc (unsigned int, unsigned int, unsigned int); - TABORTWC tabortwc {htm,htmcr} - - unsigned int __builtin_tabortwci (unsigned int, unsigned int, unsigned int); - TABORTWCI tabortwci {htm,htmcr} - - unsigned int __builtin_tbegin (unsigned int); - TBEGIN tbegin {htm,htmcr} - - unsigned int __builtin_tcheck (); - TCHECK tcheck {htm,htmcr} - - unsigned int __builtin_tend (unsigned int); - TEND tend {htm,htmcr} - - unsigned int __builtin_tendall (); - TENDALL tend {htm,htmcr} - - unsigned int __builtin_trechkpt (); - TRECHKPT trechkpt {htm,htmcr} - - unsigned int __builtin_treclaim (unsigned int); - TRECLAIM treclaim {htm,htmcr} - - unsigned int __builtin_tresume (); - TRESUME tsr {htm,htmcr} - - unsigned int __builtin_tsr (unsigned int); - TSR tsr {htm,htmcr} - - unsigned int __builtin_tsuspend (); - TSUSPEND tsr {htm,htmcr} - - unsigned int __builtin_ttest (); - TTEST ttest {htm,htmcr} - - -[power10] - const vbq __builtin_altivec_cmpge_1ti (vsq, vsq); - CMPGE_1TI vector_nltv1ti {} - - const vbq __builtin_altivec_cmpge_u1ti (vuq, vuq); - CMPGE_U1TI vector_nltuv1ti {} - - const vbq __builtin_altivec_cmple_1ti (vsq, vsq); - CMPLE_1TI vector_ngtv1ti {} - - const vbq __builtin_altivec_cmple_u1ti (vuq, vuq); - CMPLE_U1TI vector_ngtuv1ti {} - - const unsigned long long __builtin_altivec_cntmbb (vuc, const int<1>); - VCNTMBB vec_cntmb_v16qi {} - - const unsigned long long __builtin_altivec_cntmbd (vull, const int<1>); - VCNTMBD vec_cntmb_v2di {} - - const unsigned long long __builtin_altivec_cntmbh (vus, const int<1>); - VCNTMBH vec_cntmb_v8hi {} - - const unsigned long long __builtin_altivec_cntmbw (vui, const int<1>); - VCNTMBW vec_cntmb_v4si {} - - const vsq __builtin_altivec_div_v1ti (vsq, vsq); - DIV_V1TI vsx_div_v1ti {} - - const vsq __builtin_altivec_dives (vsq, vsq); - DIVES_V1TI vsx_dives_v1ti {} - - const vuq __builtin_altivec_diveu (vuq, vuq); - DIVEU_V1TI vsx_diveu_v1ti {} - - const vsq __builtin_altivec_mods (vsq, vsq); - MODS_V1TI vsx_mods_v1ti {} - - const vuq __builtin_altivec_modu (vuq, vuq); - MODU_V1TI vsx_modu_v1ti {} - - const vuc __builtin_altivec_mtvsrbm (unsigned long long); - MTVSRBM vec_mtvsr_v16qi {} - - const vull __builtin_altivec_mtvsrdm (unsigned long long); - MTVSRDM vec_mtvsr_v2di {} - - const vus __builtin_altivec_mtvsrhm (unsigned long long); - MTVSRHM vec_mtvsr_v8hi {} - - const vuq __builtin_altivec_mtvsrqm (unsigned long long); - MTVSRQM vec_mtvsr_v1ti {} - - const vui __builtin_altivec_mtvsrwm (unsigned long long); - MTVSRWM vec_mtvsr_v4si {} - - pure signed __int128 __builtin_altivec_se_lxvrbx (signed long, \ - const signed char *); - SE_LXVRBX vsx_lxvrbx {lxvrse} - - pure signed __int128 __builtin_altivec_se_lxvrhx (signed long, \ - const signed short *); - SE_LXVRHX vsx_lxvrhx {lxvrse} - - pure signed __int128 __builtin_altivec_se_lxvrwx (signed long, \ - const signed int *); - SE_LXVRWX vsx_lxvrwx {lxvrse} - - pure signed __int128 __builtin_altivec_se_lxvrdx (signed long, \ - const signed long long *); - SE_LXVRDX vsx_lxvrdx {lxvrse} - - void __builtin_altivec_tr_stxvrbx (vsq, signed long, signed char *); - TR_STXVRBX vsx_stxvrbx {stvec} - - void __builtin_altivec_tr_stxvrhx (vsq, signed long, signed int *); - TR_STXVRHX vsx_stxvrhx {stvec} - - void __builtin_altivec_tr_stxvrwx (vsq, signed long, signed short *); - TR_STXVRWX vsx_stxvrwx {stvec} - - void __builtin_altivec_tr_stxvrdx (vsq, signed long, signed long long *); - TR_STXVRDX vsx_stxvrdx {stvec} - - const vuq __builtin_altivec_udiv_v1ti (vuq, vuq); - UDIV_V1TI vsx_udiv_v1ti {} - - const vull __builtin_altivec_vcfuged (vull, vull); - VCFUGED vcfuged {} - - const vsc __builtin_altivec_vclrlb (vsc, signed int); - VCLRLB vclrlb {} - - const vsc __builtin_altivec_vclrrb (vsc, signed int); - VCLRRB vclrrb {} - - const signed int __builtin_altivec_vcmpaet_p (vsq, vsq); - VCMPAET_P vector_ae_v1ti_p {} - - const vbq __builtin_altivec_vcmpequt (vsq, vsq); - VCMPEQUT vector_eqv1ti {} - - const signed int __builtin_altivec_vcmpequt_p (signed int, vsq, vsq); - VCMPEQUT_P vector_eq_v1ti_p {pred} - - const vbq __builtin_altivec_vcmpgtst (vsq, vsq); - VCMPGTST vector_gtv1ti {} - - const signed int __builtin_altivec_vcmpgtst_p (signed int, vsq, vsq); - VCMPGTST_P vector_gt_v1ti_p {pred} - - const vbq __builtin_altivec_vcmpgtut (vuq, vuq); - VCMPGTUT vector_gtuv1ti {} - - const signed int __builtin_altivec_vcmpgtut_p (signed int, vuq, vuq); - VCMPGTUT_P vector_gtu_v1ti_p {pred} - - const vbq __builtin_altivec_vcmpnet (vsq, vsq); - VCMPNET vcmpnet {} - - const signed int __builtin_altivec_vcmpnet_p (vsq, vsq); - VCMPNET_P vector_ne_v1ti_p {} - - const vull __builtin_altivec_vclzdm (vull, vull); - VCLZDM vclzdm {} - - const vull __builtin_altivec_vctzdm (vull, vull); - VCTZDM vctzdm {} - - const vsll __builtin_altivec_vdivesd (vsll, vsll); - VDIVESD dives_v2di {} - - const vsi __builtin_altivec_vdivesw (vsi, vsi); - VDIVESW dives_v4si {} - - const vull __builtin_altivec_vdiveud (vull, vull); - VDIVEUD diveu_v2di {} - - const vui __builtin_altivec_vdiveuw (vui, vui); - VDIVEUW diveu_v4si {} - - const vsll __builtin_altivec_vdivsd (vsll, vsll); - VDIVSD divv2di3 {} - - const vsi __builtin_altivec_vdivsw (vsi, vsi); - VDIVSW divv4si3 {} - - const vull __builtin_altivec_vdivud (vull, vull); - VDIVUD udivv2di3 {} - - const vui __builtin_altivec_vdivuw (vui, vui); - VDIVUW udivv4si3 {} - - const vuc __builtin_altivec_vexpandmb (vuc); - VEXPANDMB vec_expand_v16qi {} - - const vull __builtin_altivec_vexpandmd (vull); - VEXPANDMD vec_expand_v2di {} - - const vus __builtin_altivec_vexpandmh (vus); - VEXPANDMH vec_expand_v8hi {} - - const vuq __builtin_altivec_vexpandmq (vuq); - VEXPANDMQ vec_expand_v1ti {} - - const vui __builtin_altivec_vexpandmw (vui); - VEXPANDMW vec_expand_v4si {} - - const vull __builtin_altivec_vextddvhx (vull, vull, unsigned int); - VEXTRACTDR vextractrv2di {} - - const vull __builtin_altivec_vextddvlx (vull, vull, unsigned int); - VEXTRACTDL vextractlv2di {} - - const vull __builtin_altivec_vextdubvhx (vuc, vuc, unsigned int); - VEXTRACTBR vextractrv16qi {} - - const vull __builtin_altivec_vextdubvlx (vuc, vuc, unsigned int); - VEXTRACTBL vextractlv16qi {} - - const vull __builtin_altivec_vextduhvhx (vus, vus, unsigned int); - VEXTRACTHR vextractrv8hi {} - - const vull __builtin_altivec_vextduhvlx (vus, vus, unsigned int); - VEXTRACTHL vextractlv8hi {} - - const vull __builtin_altivec_vextduwvhx (vui, vui, unsigned int); - VEXTRACTWR vextractrv4si {} - - const vull __builtin_altivec_vextduwvlx (vui, vui, unsigned int); - VEXTRACTWL vextractlv4si {} - - const signed int __builtin_altivec_vextractmb (vsc); - VEXTRACTMB vec_extract_v16qi {} - - const signed int __builtin_altivec_vextractmd (vsll); - VEXTRACTMD vec_extract_v2di {} - - const signed int __builtin_altivec_vextractmh (vss); - VEXTRACTMH vec_extract_v8hi {} - - const signed int __builtin_altivec_vextractmq (vsq); - VEXTRACTMQ vec_extract_v1ti {} - - const signed int __builtin_altivec_vextractmw (vsi); - VEXTRACTMW vec_extract_v4si {} - - const unsigned long long __builtin_altivec_vgnb (vull, const int <2,7>); - VGNB vgnb {} - - const vuc __builtin_altivec_vinsgubvlx (unsigned int, vuc, unsigned int); - VINSERTGPRBL vinsertgl_v16qi {} - - const vsc __builtin_altivec_vinsgubvrx (signed int, vsc, signed int); - VINSERTGPRBR vinsertgr_v16qi {} - - const vull __builtin_altivec_vinsgudvlx (unsigned int, vull, unsigned int); - VINSERTGPRDL vinsertgl_v2di {} - - const vsll __builtin_altivec_vinsgudvrx (signed int, vsll, signed int); - VINSERTGPRDR vinsertgr_v2di {} - - const vus __builtin_altivec_vinsguhvlx (unsigned int, vus, unsigned int); - VINSERTGPRHL vinsertgl_v8hi {} - - const vss __builtin_altivec_vinsguhvrx (signed int, vss, signed int); - VINSERTGPRHR vinsertgr_v8hi {} - - const vui __builtin_altivec_vinsguwvlx (unsigned int, vui, unsigned int); - VINSERTGPRWL vinsertgl_v4si {} - - const vsi __builtin_altivec_vinsguwvrx (signed int, vsi, signed int); - VINSERTGPRWR vinsertgr_v4si {} - - const vuc __builtin_altivec_vinsvubvlx (vuc, vuc, unsigned int); - VINSERTVPRBL vinsertvl_v16qi {} - - const vsc __builtin_altivec_vinsvubvrx (vsc, vsc, signed int); - VINSERTVPRBR vinsertvr_v16qi {} - - const vus __builtin_altivec_vinsvuhvlx (vus, vus, unsigned int); - VINSERTVPRHL vinsertvl_v8hi {} - - const vss __builtin_altivec_vinsvuhvrx (vss, vss, signed int); - VINSERTVPRHR vinsertvr_v8hi {} - - const vui __builtin_altivec_vinsvuwvlx (vui, vui, unsigned int); - VINSERTVPRWL vinsertvl_v4si {} - - const vsi __builtin_altivec_vinsvuwvrx (vsi, vsi, signed int); - VINSERTVPRWR vinsertvr_v4si {} - - const vsll __builtin_altivec_vmodsd (vsll, vsll); - VMODSD modv2di3 {} - - const vsi __builtin_altivec_vmodsw (vsi, vsi); - VMODSW modv4si3 {} - - const vull __builtin_altivec_vmodud (vull, vull); - VMODUD umodv2di3 {} - - const vui __builtin_altivec_vmoduw (vui, vui); - VMODUW umodv4si3 {} - - const vsq __builtin_altivec_vmulesd (vsll, vsll); - VMULESD vec_widen_smult_even_v2di {} - - const vuq __builtin_altivec_vmuleud (vull, vull); - VMULEUD vec_widen_umult_even_v2di {} - - const vsll __builtin_altivec_vmulhsd (vsll, vsll); - VMULHSD smulv2di3_highpart {} - - const vsi __builtin_altivec_vmulhsw (vsi, vsi); - VMULHSW smulv4si3_highpart {} - - const vull __builtin_altivec_vmulhud (vull, vull); - VMULHUD umulv2di3_highpart {} - - const vui __builtin_altivec_vmulhuw (vui, vui); - VMULHUW umulv4si3_highpart {} - - const vsll __builtin_altivec_vmulld (vsll, vsll); - VMULLD mulv2di3 {} - - const vsq __builtin_altivec_vmulosd (vsll, vsll); - VMULOSD vec_widen_smult_odd_v2di {} - - const vuq __builtin_altivec_vmuloud (vull, vull); - VMULOUD vec_widen_umult_odd_v2di {} - - const vsq __builtin_altivec_vnor_v1ti (vsq, vsq); - VNOR_V1TI norv1ti3 {} - - const vuq __builtin_altivec_vnor_v1ti_uns (vuq, vuq); - VNOR_V1TI_UNS norv1ti3 {} - - const vull __builtin_altivec_vpdepd (vull, vull); - VPDEPD vpdepd {} - - const vull __builtin_altivec_vpextd (vull, vull); - VPEXTD vpextd {} - - const vull __builtin_altivec_vreplace_un_uv2di (vull, unsigned long long, \ - const int<4>); - VREPLACE_UN_UV2DI vreplace_un_v2di {} - - const vui __builtin_altivec_vreplace_un_uv4si (vui, unsigned int, \ - const int<4>); - VREPLACE_UN_UV4SI vreplace_un_v4si {} - - const vd __builtin_altivec_vreplace_un_v2df (vd, double, const int<4>); - VREPLACE_UN_V2DF vreplace_un_v2df {} - - const vsll __builtin_altivec_vreplace_un_v2di (vsll, signed long long, \ - const int<4>); - VREPLACE_UN_V2DI vreplace_un_v2di {} - - const vf __builtin_altivec_vreplace_un_v4sf (vf, float, const int<4>); - VREPLACE_UN_V4SF vreplace_un_v4sf {} - - const vsi __builtin_altivec_vreplace_un_v4si (vsi, signed int, const int<4>); - VREPLACE_UN_V4SI vreplace_un_v4si {} - - const vull __builtin_altivec_vreplace_uv2di (vull, unsigned long long, \ - const int<1>); - VREPLACE_ELT_UV2DI vreplace_elt_v2di {} - - const vui __builtin_altivec_vreplace_uv4si (vui, unsigned int, const int<2>); - VREPLACE_ELT_UV4SI vreplace_elt_v4si {} - - const vd __builtin_altivec_vreplace_v2df (vd, double, const int<1>); - VREPLACE_ELT_V2DF vreplace_elt_v2df {} - - const vsll __builtin_altivec_vreplace_v2di (vsll, signed long long, \ - const int<1>); - VREPLACE_ELT_V2DI vreplace_elt_v2di {} - - const vf __builtin_altivec_vreplace_v4sf (vf, float, const int<2>); - VREPLACE_ELT_V4SF vreplace_elt_v4sf {} - - const vsi __builtin_altivec_vreplace_v4si (vsi, signed int, const int<2>); - VREPLACE_ELT_V4SI vreplace_elt_v4si {} - - const vsq __builtin_altivec_vrlq (vsq, vuq); - VRLQ vrotlv1ti3 {} - - const vsq __builtin_altivec_vrlqmi (vsq, vsq, vuq); - VRLQMI altivec_vrlqmi {} - - const vsq __builtin_altivec_vrlqnm (vsq, vuq); - VRLQNM altivec_vrlqnm {} - - const vsq __builtin_altivec_vsignext (vsll); - VSIGNEXTSD2Q vsignextend_v2di_v1ti {} - - const vsc __builtin_altivec_vsldb_v16qi (vsc, vsc, const int<3>); - VSLDB_V16QI vsldb_v16qi {} - - const vsll __builtin_altivec_vsldb_v2di (vsll, vsll, const int<3>); - VSLDB_V2DI vsldb_v2di {} - - const vsi __builtin_altivec_vsldb_v4si (vsi, vsi, const int<3>); - VSLDB_V4SI vsldb_v4si {} - - const vss __builtin_altivec_vsldb_v8hi (vss, vss, const int<3>); - VSLDB_V8HI vsldb_v8hi {} - - const vsq __builtin_altivec_vslq (vsq, vuq); - VSLQ vashlv1ti3 {} - - const vsq __builtin_altivec_vsraq (vsq, vuq); - VSRAQ vashrv1ti3 {} - - const vsc __builtin_altivec_vsrdb_v16qi (vsc, vsc, const int<3>); - VSRDB_V16QI vsrdb_v16qi {} - - const vsll __builtin_altivec_vsrdb_v2di (vsll, vsll, const int<3>); - VSRDB_V2DI vsrdb_v2di {} - - const vsi __builtin_altivec_vsrdb_v4si (vsi, vsi, const int<3>); - VSRDB_V4SI vsrdb_v4si {} - - const vss __builtin_altivec_vsrdb_v8hi (vss, vss, const int<3>); - VSRDB_V8HI vsrdb_v8hi {} - - const vsq __builtin_altivec_vsrq (vsq, vuq); - VSRQ vlshrv1ti3 {} - - const vsc __builtin_altivec_vstribl (vsc); - VSTRIBL vstril_v16qi {} - - const signed int __builtin_altivec_vstribl_p (vsc); - VSTRIBL_P vstril_p_v16qi {} - - const vsc __builtin_altivec_vstribr (vsc); - VSTRIBR vstrir_v16qi {} - - const signed int __builtin_altivec_vstribr_p (vsc); - VSTRIBR_P vstrir_p_v16qi {} - - const vss __builtin_altivec_vstrihl (vss); - VSTRIHL vstril_v8hi {} - - const signed int __builtin_altivec_vstrihl_p (vss); - VSTRIHL_P vstril_p_v8hi {} - - const vss __builtin_altivec_vstrihr (vss); - VSTRIHR vstrir_v8hi {} - - const signed int __builtin_altivec_vstrihr_p (vss); - VSTRIHR_P vstrir_p_v8hi {} - - const signed int __builtin_vsx_xvtlsbb_all_ones (vsc); - XVTLSBB_ONES xvtlsbbo {} - - const signed int __builtin_vsx_xvtlsbb_all_zeros (vsc); - XVTLSBB_ZEROS xvtlsbbz {} - - const vf __builtin_vsx_vxxsplti32dx_v4sf (vf, const int<1>, float); - VXXSPLTI32DX_V4SF xxsplti32dx_v4sf {} - - const vsi __builtin_vsx_vxxsplti32dx_v4si (vsi, const int<1>, signed int); - VXXSPLTI32DX_V4SI xxsplti32dx_v4si {} - - const vd __builtin_vsx_vxxspltidp (float); - VXXSPLTIDP xxspltidp_v2df {} - - const vf __builtin_vsx_vxxspltiw_v4sf (float); - VXXSPLTIW_V4SF xxspltiw_v4sf {} - - const vsi __builtin_vsx_vxxspltiw_v4si (signed int); - VXXSPLTIW_V4SI xxspltiw_v4si {} - - const vuc __builtin_vsx_xvcvbf16spn (vuc); - XVCVBF16SPN vsx_xvcvbf16spn {} - - const vuc __builtin_vsx_xvcvspbf16 (vuc); - XVCVSPBF16 vsx_xvcvspbf16 {} - - const vuc __builtin_vsx_xxblend_v16qi (vuc, vuc, vuc); - VXXBLEND_V16QI xxblend_v16qi {} - - const vd __builtin_vsx_xxblend_v2df (vd, vd, vd); - VXXBLEND_V2DF xxblend_v2df {} - - const vull __builtin_vsx_xxblend_v2di (vull, vull, vull); - VXXBLEND_V2DI xxblend_v2di {} - - const vf __builtin_vsx_xxblend_v4sf (vf, vf, vf); - VXXBLEND_V4SF xxblend_v4sf {} - - const vui __builtin_vsx_xxblend_v4si (vui, vui, vui); - VXXBLEND_V4SI xxblend_v4si {} - - const vus __builtin_vsx_xxblend_v8hi (vus, vus, vus); - VXXBLEND_V8HI xxblend_v8hi {} - - const vull __builtin_vsx_xxeval (vull, vull, vull, const int <8>); - XXEVAL xxeval {} - - const vuc __builtin_vsx_xxgenpcvm_v16qi (vuc, const int <2>); - XXGENPCVM_V16QI xxgenpcvm_v16qi {} - - const vull __builtin_vsx_xxgenpcvm_v2di (vull, const int <2>); - XXGENPCVM_V2DI xxgenpcvm_v2di {} - - const vui __builtin_vsx_xxgenpcvm_v4si (vui, const int <2>); - XXGENPCVM_V4SI xxgenpcvm_v4si {} - - const vus __builtin_vsx_xxgenpcvm_v8hi (vus, const int <2>); - XXGENPCVM_V8HI xxgenpcvm_v8hi {} - - const vuc __builtin_vsx_xxpermx_uv16qi (vuc, vuc, vuc, const int<3>); - XXPERMX_UV16QI xxpermx {} - - const vull __builtin_vsx_xxpermx_uv2di (vull, vull, vuc, const int<3>); - XXPERMX_UV2DI xxpermx {} - - const vui __builtin_vsx_xxpermx_uv4si (vui, vui, vuc, const int<3>); - XXPERMX_UV4SI xxpermx {} - - const vus __builtin_vsx_xxpermx_uv8hi (vus, vus, vuc, const int<3>); - XXPERMX_UV8HI xxpermx {} - - const vsc __builtin_vsx_xxpermx_v16qi (vsc, vsc, vuc, const int<3>); - XXPERMX_V16QI xxpermx {} - - const vd __builtin_vsx_xxpermx_v2df (vd, vd, vuc, const int<3>); - XXPERMX_V2DF xxpermx {} - - const vsll __builtin_vsx_xxpermx_v2di (vsll, vsll, vuc, const int<3>); - XXPERMX_V2DI xxpermx {} - - const vf __builtin_vsx_xxpermx_v4sf (vf, vf, vuc, const int<3>); - XXPERMX_V4SF xxpermx {} - - const vsi __builtin_vsx_xxpermx_v4si (vsi, vsi, vuc, const int<3>); - XXPERMX_V4SI xxpermx {} - - const vss __builtin_vsx_xxpermx_v8hi (vss, vss, vuc, const int<3>); - XXPERMX_V8HI xxpermx {} - - pure unsigned __int128 __builtin_altivec_ze_lxvrbx (signed long, \ - const unsigned char *); - ZE_LXVRBX vsx_lxvrbx {lxvrze} - - pure unsigned __int128 __builtin_altivec_ze_lxvrhx (signed long, \ - const unsigned short *); - ZE_LXVRHX vsx_lxvrhx {lxvrze} - - pure unsigned __int128 __builtin_altivec_ze_lxvrwx (signed long, \ - const unsigned int *); - ZE_LXVRWX vsx_lxvrwx {lxvrze} - - pure unsigned __int128 \ - __builtin_altivec_ze_lxvrdx (signed long, const unsigned long long *); - ZE_LXVRDX vsx_lxvrdx {lxvrze} - - -[power10-64] - const unsigned long long __builtin_cfuged (unsigned long long, \ - unsigned long long); - CFUGED cfuged {} - - const unsigned long long __builtin_cntlzdm (unsigned long long, \ - unsigned long long); - CNTLZDM cntlzdm {} - - const unsigned long long __builtin_cnttzdm (unsigned long long, \ - unsigned long long); - CNTTZDM cnttzdm {} - - const unsigned long long __builtin_pdepd (unsigned long long, \ - unsigned long long); - PDEPD pdepd {} - - const unsigned long long __builtin_pextd (unsigned long long, \ - unsigned long long); - PEXTD pextd {} - - -[mma] - void __builtin_mma_assemble_acc (v512 *, vuc, vuc, vuc, vuc); - ASSEMBLE_ACC nothing {mma,mmaint} - - v512 __builtin_mma_assemble_acc_internal (vuc, vuc, vuc, vuc); - ASSEMBLE_ACC_INTERNAL mma_assemble_acc {mma} - - void __builtin_mma_assemble_pair (v256 *, vuc, vuc); - ASSEMBLE_PAIR nothing {mma,mmaint} - - v256 __builtin_mma_assemble_pair_internal (vuc, vuc); - ASSEMBLE_PAIR_INTERNAL vsx_assemble_pair {mma} - - void __builtin_mma_build_acc (v512 *, vuc, vuc, vuc, vuc); - BUILD_ACC nothing {mma,mmaint} - - v512 __builtin_mma_build_acc_internal (vuc, vuc, vuc, vuc); - BUILD_ACC_INTERNAL mma_assemble_acc {mma} - - void __builtin_mma_disassemble_acc (void *, v512 *); - DISASSEMBLE_ACC nothing {mma,quad,mmaint} - - vuc __builtin_mma_disassemble_acc_internal (v512, const int<2>); - DISASSEMBLE_ACC_INTERNAL mma_disassemble_acc {mma} - - void __builtin_mma_disassemble_pair (void *, v256 *); - DISASSEMBLE_PAIR nothing {mma,pair,mmaint} - - vuc __builtin_mma_disassemble_pair_internal (v256, const int<2>); - DISASSEMBLE_PAIR_INTERNAL vsx_disassemble_pair {mma} - - void __builtin_mma_pmxvbf16ger2 (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVBF16GER2 nothing {mma,mmaint} - - v512 __builtin_mma_pmxvbf16ger2_internal (vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVBF16GER2_INTERNAL mma_pmxvbf16ger2 {mma} - - void __builtin_mma_pmxvbf16ger2nn (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVBF16GER2NN nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvbf16ger2nn_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVBF16GER2NN_INTERNAL mma_pmxvbf16ger2nn {mma,quad} - - void __builtin_mma_pmxvbf16ger2np (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVBF16GER2NP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvbf16ger2np_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVBF16GER2NP_INTERNAL mma_pmxvbf16ger2np {mma,quad} - - void __builtin_mma_pmxvbf16ger2pn (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVBF16GER2PN nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvbf16ger2pn_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVBF16GER2PN_INTERNAL mma_pmxvbf16ger2pn {mma,quad} - - void __builtin_mma_pmxvbf16ger2pp (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVBF16GER2PP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvbf16ger2pp_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVBF16GER2PP_INTERNAL mma_pmxvbf16ger2pp {mma,quad} - - void __builtin_mma_pmxvf16ger2 (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVF16GER2 nothing {mma,mmaint} - - v512 __builtin_mma_pmxvf16ger2_internal (vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVF16GER2_INTERNAL mma_pmxvf16ger2 {mma} - - void __builtin_mma_pmxvf16ger2nn (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVF16GER2NN nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvf16ger2nn_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVF16GER2NN_INTERNAL mma_pmxvf16ger2nn {mma,quad} - - void __builtin_mma_pmxvf16ger2np (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVF16GER2NP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvf16ger2np_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVF16GER2NP_INTERNAL mma_pmxvf16ger2np {mma,quad} - - void __builtin_mma_pmxvf16ger2pn (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVF16GER2PN nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvf16ger2pn_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVF16GER2PN_INTERNAL mma_pmxvf16ger2pn {mma,quad} - - void __builtin_mma_pmxvf16ger2pp (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVF16GER2PP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvf16ger2pp_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVF16GER2PP_INTERNAL mma_pmxvf16ger2pp {mma,quad} - - void __builtin_mma_pmxvf32ger (v512 *, vuc, vuc, const int<4>, const int<4>); - PMXVF32GER nothing {mma,mmaint} - - v512 __builtin_mma_pmxvf32ger_internal (vuc, vuc, const int<4>, \ - const int<4>); - PMXVF32GER_INTERNAL mma_pmxvf32ger {mma} - - void __builtin_mma_pmxvf32gernn (v512 *, vuc, vuc, const int<4>, \ - const int<4>); - PMXVF32GERNN nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvf32gernn_internal (v512, vuc, vuc, const int<4>, \ - const int<4>); - PMXVF32GERNN_INTERNAL mma_pmxvf32gernn {mma,quad} - - void __builtin_mma_pmxvf32gernp (v512 *, vuc, vuc, const int<4>, \ - const int<4>); - PMXVF32GERNP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvf32gernp_internal (v512, vuc, vuc, const int<4>, \ - const int<4>); - PMXVF32GERNP_INTERNAL mma_pmxvf32gernp {mma,quad} - - void __builtin_mma_pmxvf32gerpn (v512 *, vuc, vuc, const int<4>, \ - const int<4>); - PMXVF32GERPN nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvf32gerpn_internal (v512, vuc, vuc, const int<4>, \ - const int<4>); - PMXVF32GERPN_INTERNAL mma_pmxvf32gerpn {mma,quad} - - void __builtin_mma_pmxvf32gerpp (v512 *, vuc, vuc, const int<4>, \ - const int<4>); - PMXVF32GERPP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvf32gerpp_internal (v512, vuc, vuc, const int<4>, \ - const int<4>); - PMXVF32GERPP_INTERNAL mma_pmxvf32gerpp {mma,quad} - - void __builtin_mma_pmxvf64ger (v512 *, v256, vuc, const int<4>, \ - const int<2>); - PMXVF64GER nothing {mma,pair,mmaint} - - v512 __builtin_mma_pmxvf64ger_internal (v256, vuc, const int<4>, \ - const int<2>); - PMXVF64GER_INTERNAL mma_pmxvf64ger {mma,pair} - - void __builtin_mma_pmxvf64gernn (v512 *, v256, vuc, const int<4>, \ - const int<2>); - PMXVF64GERNN nothing {mma,pair,quad,mmaint} - - v512 __builtin_mma_pmxvf64gernn_internal (v512, v256, vuc, const int<4>, \ - const int<2>); - PMXVF64GERNN_INTERNAL mma_pmxvf64gernn {mma,pair,quad} - - void __builtin_mma_pmxvf64gernp (v512 *, v256, vuc, const int<4>, \ - const int<2>); - PMXVF64GERNP nothing {mma,pair,quad,mmaint} - - v512 __builtin_mma_pmxvf64gernp_internal (v512, v256, vuc, const int<4>, \ - const int<2>); - PMXVF64GERNP_INTERNAL mma_pmxvf64gernp {mma,pair,quad} - - void __builtin_mma_pmxvf64gerpn (v512 *, v256, vuc, const int<4>, \ - const int<2>); - PMXVF64GERPN nothing {mma,pair,quad,mmaint} - - v512 __builtin_mma_pmxvf64gerpn_internal (v512, v256, vuc, const int<4>, \ - const int<2>); - PMXVF64GERPN_INTERNAL mma_pmxvf64gerpn {mma,pair,quad} - - void __builtin_mma_pmxvf64gerpp (v512 *, v256, vuc, const int<4>, \ - const int<2>); - PMXVF64GERPP nothing {mma,pair,quad,mmaint} - - v512 __builtin_mma_pmxvf64gerpp_internal (v512, v256, vuc, const int<4>, \ - const int<2>); - PMXVF64GERPP_INTERNAL mma_pmxvf64gerpp {mma,pair,quad} - - void __builtin_mma_pmxvi16ger2 (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVI16GER2 nothing {mma,mmaint} - - v512 __builtin_mma_pmxvi16ger2_internal (vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVI16GER2_INTERNAL mma_pmxvi16ger2 {mma} - - void __builtin_mma_pmxvi16ger2pp (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVI16GER2PP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvi16ger2pp_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVI16GER2PP_INTERNAL mma_pmxvi16ger2pp {mma,quad} - - void __builtin_mma_pmxvi16ger2s (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVI16GER2S nothing {mma,mmaint} - - v512 __builtin_mma_pmxvi16ger2s_internal (vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVI16GER2S_INTERNAL mma_pmxvi16ger2s {mma} - - void __builtin_mma_pmxvi16ger2spp (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVI16GER2SPP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvi16ger2spp_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<2>); - PMXVI16GER2SPP_INTERNAL mma_pmxvi16ger2spp {mma,quad} - - void __builtin_mma_pmxvi4ger8 (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<8>); - PMXVI4GER8 nothing {mma,mmaint} - - v512 __builtin_mma_pmxvi4ger8_internal (vuc, vuc, const int<4>, \ - const int<4>, const int<8>); - PMXVI4GER8_INTERNAL mma_pmxvi4ger8 {mma} - - void __builtin_mma_pmxvi4ger8pp (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<4>); - PMXVI4GER8PP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvi4ger8pp_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<4>); - PMXVI4GER8PP_INTERNAL mma_pmxvi4ger8pp {mma,quad} - - void __builtin_mma_pmxvi8ger4 (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<4>); - PMXVI8GER4 nothing {mma,mmaint} - - v512 __builtin_mma_pmxvi8ger4_internal (vuc, vuc, const int<4>, \ - const int<4>, const int<4>); - PMXVI8GER4_INTERNAL mma_pmxvi8ger4 {mma} - - void __builtin_mma_pmxvi8ger4pp (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<4>); - PMXVI8GER4PP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvi8ger4pp_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<4>); - PMXVI8GER4PP_INTERNAL mma_pmxvi8ger4pp {mma,quad} - - void __builtin_mma_pmxvi8ger4spp (v512 *, vuc, vuc, const int<4>, \ - const int<4>, const int<4>); - PMXVI8GER4SPP nothing {mma,quad,mmaint} - - v512 __builtin_mma_pmxvi8ger4spp_internal (v512, vuc, vuc, const int<4>, \ - const int<4>, const int<4>); - PMXVI8GER4SPP_INTERNAL mma_pmxvi8ger4spp {mma,quad} - - void __builtin_mma_xvbf16ger2 (v512 *, vuc, vuc); - XVBF16GER2 nothing {mma,mmaint} - - v512 __builtin_mma_xvbf16ger2_internal (vuc, vuc); - XVBF16GER2_INTERNAL mma_xvbf16ger2 {mma} - - void __builtin_mma_xvbf16ger2nn (v512 *, vuc, vuc); - XVBF16GER2NN nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvbf16ger2nn_internal (v512, vuc, vuc); - XVBF16GER2NN_INTERNAL mma_xvbf16ger2nn {mma,quad} - - void __builtin_mma_xvbf16ger2np (v512 *, vuc, vuc); - XVBF16GER2NP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvbf16ger2np_internal (v512, vuc, vuc); - XVBF16GER2NP_INTERNAL mma_xvbf16ger2np {mma,quad} - - void __builtin_mma_xvbf16ger2pn (v512 *, vuc, vuc); - XVBF16GER2PN nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvbf16ger2pn_internal (v512, vuc, vuc); - XVBF16GER2PN_INTERNAL mma_xvbf16ger2pn {mma,quad} - - void __builtin_mma_xvbf16ger2pp (v512 *, vuc, vuc); - XVBF16GER2PP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvbf16ger2pp_internal (v512, vuc, vuc); - XVBF16GER2PP_INTERNAL mma_xvbf16ger2pp {mma,quad} - - void __builtin_mma_xvf16ger2 (v512 *, vuc, vuc); - XVF16GER2 nothing {mma,mmaint} - - v512 __builtin_mma_xvf16ger2_internal (vuc, vuc); - XVF16GER2_INTERNAL mma_xvf16ger2 {mma} - - void __builtin_mma_xvf16ger2nn (v512 *, vuc, vuc); - XVF16GER2NN nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvf16ger2nn_internal (v512, vuc, vuc); - XVF16GER2NN_INTERNAL mma_xvf16ger2nn {mma,quad} - - void __builtin_mma_xvf16ger2np (v512 *, vuc, vuc); - XVF16GER2NP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvf16ger2np_internal (v512, vuc, vuc); - XVF16GER2NP_INTERNAL mma_xvf16ger2np {mma,quad} - - void __builtin_mma_xvf16ger2pn (v512 *, vuc, vuc); - XVF16GER2PN nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvf16ger2pn_internal (v512, vuc, vuc); - XVF16GER2PN_INTERNAL mma_xvf16ger2pn {mma,quad} - - void __builtin_mma_xvf16ger2pp (v512 *, vuc, vuc); - XVF16GER2PP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvf16ger2pp_internal (v512, vuc, vuc); - XVF16GER2PP_INTERNAL mma_xvf16ger2pp {mma,quad} - - void __builtin_mma_xvf32ger (v512 *, vuc, vuc); - XVF32GER nothing {mma,mmaint} - - v512 __builtin_mma_xvf32ger_internal (vuc, vuc); - XVF32GER_INTERNAL mma_xvf32ger {mma} - - void __builtin_mma_xvf32gernn (v512 *, vuc, vuc); - XVF32GERNN nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvf32gernn_internal (v512, vuc, vuc); - XVF32GERNN_INTERNAL mma_xvf32gernn {mma,quad} - - void __builtin_mma_xvf32gernp (v512 *, vuc, vuc); - XVF32GERNP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvf32gernp_internal (v512, vuc, vuc); - XVF32GERNP_INTERNAL mma_xvf32gernp {mma,quad} - - void __builtin_mma_xvf32gerpn (v512 *, vuc, vuc); - XVF32GERPN nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvf32gerpn_internal (v512, vuc, vuc); - XVF32GERPN_INTERNAL mma_xvf32gerpn {mma,quad} - - void __builtin_mma_xvf32gerpp (v512 *, vuc, vuc); - XVF32GERPP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvf32gerpp_internal (v512, vuc, vuc); - XVF32GERPP_INTERNAL mma_xvf32gerpp {mma,quad} - - void __builtin_mma_xvf64ger (v512 *, v256, vuc); - XVF64GER nothing {mma,pair,mmaint} - - v512 __builtin_mma_xvf64ger_internal (v256, vuc); - XVF64GER_INTERNAL mma_xvf64ger {mma,pair} - - void __builtin_mma_xvf64gernn (v512 *, v256, vuc); - XVF64GERNN nothing {mma,pair,quad,mmaint} - - v512 __builtin_mma_xvf64gernn_internal (v512, v256, vuc); - XVF64GERNN_INTERNAL mma_xvf64gernn {mma,pair,quad} - - void __builtin_mma_xvf64gernp (v512 *, v256, vuc); - XVF64GERNP nothing {mma,pair,quad,mmaint} - - v512 __builtin_mma_xvf64gernp_internal (v512, v256, vuc); - XVF64GERNP_INTERNAL mma_xvf64gernp {mma,pair,quad} - - void __builtin_mma_xvf64gerpn (v512 *, v256, vuc); - XVF64GERPN nothing {mma,pair,quad,mmaint} - - v512 __builtin_mma_xvf64gerpn_internal (v512, v256, vuc); - XVF64GERPN_INTERNAL mma_xvf64gerpn {mma,pair,quad} - - void __builtin_mma_xvf64gerpp (v512 *, v256, vuc); - XVF64GERPP nothing {mma,pair,quad,mmaint} - - v512 __builtin_mma_xvf64gerpp_internal (v512, v256, vuc); - XVF64GERPP_INTERNAL mma_xvf64gerpp {mma,pair,quad} - - void __builtin_mma_xvi16ger2 (v512 *, vuc, vuc); - XVI16GER2 nothing {mma,mmaint} - - v512 __builtin_mma_xvi16ger2_internal (vuc, vuc); - XVI16GER2_INTERNAL mma_xvi16ger2 {mma} - - void __builtin_mma_xvi16ger2pp (v512 *, vuc, vuc); - XVI16GER2PP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvi16ger2pp_internal (v512, vuc, vuc); - XVI16GER2PP_INTERNAL mma_xvi16ger2pp {mma,quad} - - void __builtin_mma_xvi16ger2s (v512 *, vuc, vuc); - XVI16GER2S nothing {mma,mmaint} - - v512 __builtin_mma_xvi16ger2s_internal (vuc, vuc); - XVI16GER2S_INTERNAL mma_xvi16ger2s {mma} - - void __builtin_mma_xvi16ger2spp (v512 *, vuc, vuc); - XVI16GER2SPP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvi16ger2spp_internal (v512, vuc, vuc); - XVI16GER2SPP_INTERNAL mma_xvi16ger2spp {mma,quad} - - void __builtin_mma_xvi4ger8 (v512 *, vuc, vuc); - XVI4GER8 nothing {mma,mmaint} - - v512 __builtin_mma_xvi4ger8_internal (vuc, vuc); - XVI4GER8_INTERNAL mma_xvi4ger8 {mma} - - void __builtin_mma_xvi4ger8pp (v512 *, vuc, vuc); - XVI4GER8PP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvi4ger8pp_internal (v512, vuc, vuc); - XVI4GER8PP_INTERNAL mma_xvi4ger8pp {mma,quad} - - void __builtin_mma_xvi8ger4 (v512 *, vuc, vuc); - XVI8GER4 nothing {mma,mmaint} - - v512 __builtin_mma_xvi8ger4_internal (vuc, vuc); - XVI8GER4_INTERNAL mma_xvi8ger4 {mma} - - void __builtin_mma_xvi8ger4pp (v512 *, vuc, vuc); - XVI8GER4PP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvi8ger4pp_internal (v512, vuc, vuc); - XVI8GER4PP_INTERNAL mma_xvi8ger4pp {mma,quad} - - void __builtin_mma_xvi8ger4spp (v512 *, vuc, vuc); - XVI8GER4SPP nothing {mma,quad,mmaint} - - v512 __builtin_mma_xvi8ger4spp_internal (v512, vuc, vuc); - XVI8GER4SPP_INTERNAL mma_xvi8ger4spp {mma,quad} - - void __builtin_mma_xxmfacc (v512 *); - XXMFACC nothing {mma,quad,mmaint} - - v512 __builtin_mma_xxmfacc_internal (v512); - XXMFACC_INTERNAL mma_xxmfacc {mma,quad} - - void __builtin_mma_xxmtacc (v512 *); - XXMTACC nothing {mma,quad,mmaint} - - v512 __builtin_mma_xxmtacc_internal (v512); - XXMTACC_INTERNAL mma_xxmtacc {mma,quad} - - void __builtin_mma_xxsetaccz (v512 *); - XXSETACCZ nothing {mma,mmaint} - - v512 __builtin_mma_xxsetaccz_internal (); - XXSETACCZ_INTERNAL mma_xxsetaccz {mma} - - void __builtin_vsx_assemble_pair (v256 *, vuc, vuc); - ASSEMBLE_PAIR_V nothing {mma,mmaint} - - v256 __builtin_vsx_assemble_pair_internal (vuc, vuc); - ASSEMBLE_PAIR_V_INTERNAL vsx_assemble_pair {mma} - - void __builtin_vsx_build_pair (v256 *, vuc, vuc); - BUILD_PAIR nothing {mma,mmaint} - - v256 __builtin_vsx_build_pair_internal (vuc, vuc); - BUILD_PAIR_INTERNAL vsx_assemble_pair {mma} - - void __builtin_vsx_disassemble_pair (void *, v256 *); - DISASSEMBLE_PAIR_V nothing {mma,pair,mmaint} - - vuc __builtin_vsx_disassemble_pair_internal (v256, const int<2>); - DISASSEMBLE_PAIR_V_INTERNAL vsx_disassemble_pair {mma} - - v256 __builtin_vsx_lxvp (unsigned long, const v256 *); - LXVP nothing {mma} - - void __builtin_vsx_stxvp (v256, unsigned long, const v256 *); - STXVP nothing {mma,pair} diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def new file mode 100644 index 0000000..45ce160 --- /dev/null +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -0,0 +1,4105 @@ +; Built-in functions for PowerPC. +; Copyright (C) 2020-2021 Free Software Foundation, Inc. +; Contributed by Bill Schmidt, IBM +; +; This file is part of GCC. +; +; GCC is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License as published by the Free +; Software Foundation; either version 3, or (at your option) any later +; version. +; +; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or +; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +; for more details. +; +; You should have received a copy of the GNU General Public License +; along with GCC; see the file COPYING3. If not see +; . + + +; Built-in functions in this file are organized into "stanzas", where +; all built-ins in a given stanza are enabled together. Each stanza +; starts with a line identifying the circumstances in which the group of +; functions is permitted, with the gating predicate in square brackets. +; For example, this could be +; +; [altivec] +; +; or it could be +; +; [power9] +; +; The bracketed gating predicate is the only information allowed on +; the stanza header line, other than whitespace. +; +; Following the stanza header are two lines for each function: the +; prototype line and the attributes line. The prototype line has +; this format, where the square brackets indicate optional +; information and angle brackets indicate required information: +; +; [kind] (); +; +; Here [kind] can be one of "const", "pure", or "fpmath"; +; is a legal type for a built-in function result; +; is the name by which the function can be called; +; and is a comma-separated list of legal types +; for built-in function arguments. The argument list may be +; empty, but the parentheses and semicolon are required. +; +; A legal type is of the form: +; +; [const] [[signed|unsigned] | ] [*] +; +; where "const" applies only to a of "int". Legal values +; of are (for now): +; +; char +; short +; int +; long +; long double +; long long +; float +; double +; __int128 +; _Float128 +; bool +; string +; _Decimal32 +; _Decimal64 +; _Decimal128 +; __ibm128 +; +; Legal values of are as follows, and are shorthand for +; the associated meaning: +; +; vsc vector signed char +; vuc vector unsigned char +; vbc vector bool char +; vss vector signed short +; vus vector unsigned short +; vbs vector bool short +; vsi vector signed int +; vui vector unsigned int +; vbi vector bool int +; vsll vector signed long long +; vull vector unsigned long long +; vbll vector bool long long +; vsq vector signed __int128 +; vuq vector unsigned __int128 +; vbq vector bool __int128 +; vp vector pixel +; vf vector float +; vd vector double +; v256 __vector_pair +; v512 __vector_quad +; +; For simplicity, We don't support "short int" and "long long int". +; We don't currently support a of "_Float16". "signed" +; and "unsigned" only apply to integral base types. The optional * +; indicates a pointer type. +; +; The attributes line looks like this: +; +; {} +; +; Here is a unique internal identifier for the built-in +; function that will be used as part of an enumeration of all +; built-in functions; is the define_expand or +; define_insn that will be invoked when the call is expanded; +; and is a comma-separated list of special +; conditions that apply to the built-in function. The attribute +; list may be empty, but the braces are required. +; +; Attributes are strings, and the allowed ones are listed below. +; +; init Process as a vec_init function +; set Process as a vec_set function +; extract Process as a vec_extract function +; nosoft Not valid with -msoft-float +; ldvec Needs special handling for vec_ld semantics +; stvec Needs special handling for vec_st semantics +; reve Needs special handling for element reversal +; pred Needs special handling for comparison predicates +; htm Needs special handling for transactional memory +; htmspr HTM function using an SPR +; htmcr HTM function using a CR +; mma Needs special handling for MMA +; quad MMA instruction using a register quad as an input operand +; pair MMA instruction using a register pair as an input operand +; mmaint MMA instruction expanding to internal call at GIMPLE time +; no32bit Not valid for TARGET_32BIT +; 32bit Requires different handling for TARGET_32BIT +; cpu This is a "cpu_is" or "cpu_supports" builtin +; ldstmask Altivec mask for load or store +; lxvrse Needs special handling for load-rightmost, sign-extended +; lxvrze Needs special handling for load-rightmost, zero-extended +; endian Needs special handling for endianness +; ibmld Restrict usage to the case when TFmode is IBM-128 +; +; Each attribute corresponds to extra processing required when +; the built-in is expanded. All such special processing should +; be controlled by an attribute from now on. +; +; It is important to note that each entry's must be +; unique. The code generated from this file will call def_builtin +; for each entry, and this can only happen once per name. +; +; The type signature for the builtin must match the modes of the RTL +; pattern . When a builtin is used only as a basis for +; overloading, you can use an arbitrary type for each mode (for example, +; for V8HImode, you could use vp, vss, vus, or vbs). The overloading +; machinery takes care of adding appropriate casts between vectors to +; satisfy impedance matching. The overloaded prototypes are the ones +; that must match what users expect. Thus you will often have a small +; number of entries in this file that correspond to a much greater +; number of entries in rs6000-overload.def. +; +; However, builtins in this file that are expected to be directly called +; by users must have one version for each expected type combination. +; +; Eventually we want to automatically generate built-in documentation +; from the entries in this file. Documenting of built-ins with more +; than one acceptable prototype can be done by cross-referencing +; against rs6000-overload.def and picking up the allowable prototypes +; from there. +; +; Blank lines may be used as desired in this file between the lines as +; defined above; that is, you can introduce as many extra newlines as you +; like after a required newline, but nowhere else. Lines beginning with +; a semicolon are also treated as blank lines. +; +; A const int argument may be restricted to certain values. This is +; indicated by one of the following occurring after the "int" token: +; +; restricts the constant to x bits, interpreted as unsigned +; restricts the constant to the inclusive range [x,y] +; [x,y] restricts the constant to the inclusive range [x,y], +; but only applies if the argument is constant. +; {x,y} restricts the constant to one of two values, x or y. +; +; Here x and y are integer tokens. Note that the "const" token is a +; lie when the restriction is [x,y], but this simplifies the parsing +; significantly and is hopefully forgivable. + + + +; Builtins that have been around since time immemorial or are just +; considered available everywhere. +[always] +; __builtin_cfstring is for Darwin, which will replace the decl we +; create here with another one during subtarget processing. We just +; need to ensure it has a slot in the builtin enumeration. + void __builtin_cfstring (); + CFSTRING nothing {} + + void __builtin_cpu_init (); + CPU_INIT nothing {cpu} + + bool __builtin_cpu_is (string); + CPU_IS nothing {cpu} + + bool __builtin_cpu_supports (string); + CPU_SUPPORTS nothing {cpu} + + unsigned long long __builtin_ppc_get_timebase (); + GET_TB rs6000_get_timebase {} + + double __builtin_mffs (); + MFFS rs6000_mffs {} + +; Although the mffsl instruction is only available on POWER9 and later +; processors, this builtin automatically falls back to mffs on older +; platforms. Thus it appears here in the [always] stanza. + double __builtin_mffsl (); + MFFSL rs6000_mffsl {} + +; This is redundant with __builtin_pack_ibm128, as it requires long +; double to be __ibm128. Should probably be deprecated. + const long double __builtin_pack_longdouble (double, double); + PACK_TF packtf {ibmld} + + unsigned long __builtin_ppc_mftb (); + MFTB rs6000_mftb_di {32bit} + + void __builtin_mtfsb0 (const int<5>); + MTFSB0 rs6000_mtfsb0 {} + + void __builtin_mtfsb1 (const int<5>); + MTFSB1 rs6000_mtfsb1 {} + + void __builtin_mtfsf (const int<8>, double); + MTFSF rs6000_mtfsf {} + + const __ibm128 __builtin_pack_ibm128 (double, double); + PACK_IF packif {} + + void __builtin_set_fpscr_rn (const int[0,3]); + SET_FPSCR_RN rs6000_set_fpscr_rn {} + + const double __builtin_unpack_ibm128 (__ibm128, const int<1>); + UNPACK_IF unpackif {} + +; This is redundant with __builtin_unpack_ibm128, as it requires long +; double to be __ibm128. Should probably be deprecated. + const double __builtin_unpack_longdouble (long double, const int<1>); + UNPACK_TF unpacktf {ibmld} + + +; Builtins that have been around just about forever, but not quite. +[power5] + fpmath double __builtin_recipdiv (double, double); + RECIP recipdf3 {} + + fpmath float __builtin_recipdivf (float, float); + RECIPF recipsf3 {} + + fpmath double __builtin_rsqrt (double); + RSQRT rsqrtdf2 {} + + fpmath float __builtin_rsqrtf (float); + RSQRTF rsqrtsf2 {} + + +; Power6 builtins (ISA 2.05). +[power6] + const signed int __builtin_p6_cmpb_32 (signed int, signed int); + CMPB_32 cmpbsi3 {} + + +; Power6 builtins requiring 64-bit GPRs (even with 32-bit addressing). +[power6-64] + const signed long __builtin_p6_cmpb (signed long, signed long); + CMPB cmpbdi3 {no32bit} + + +; AltiVec builtins. +[altivec] + const vsc __builtin_altivec_abs_v16qi (vsc); + ABS_V16QI absv16qi2 {} + + const vf __builtin_altivec_abs_v4sf (vf); + ABS_V4SF absv4sf2 {} + + const vsi __builtin_altivec_abs_v4si (vsi); + ABS_V4SI absv4si2 {} + + const vss __builtin_altivec_abs_v8hi (vss); + ABS_V8HI absv8hi2 {} + + const vsc __builtin_altivec_abss_v16qi (vsc); + ABSS_V16QI altivec_abss_v16qi {} + + const vsi __builtin_altivec_abss_v4si (vsi); + ABSS_V4SI altivec_abss_v4si {} + + const vss __builtin_altivec_abss_v8hi (vss); + ABSS_V8HI altivec_abss_v8hi {} + + const vf __builtin_altivec_copysignfp (vf, vf); + COPYSIGN_V4SF vector_copysignv4sf3 {} + + void __builtin_altivec_dss (const int<2>); + DSS altivec_dss {} + + void __builtin_altivec_dssall (); + DSSALL altivec_dssall {} + + void __builtin_altivec_dst (void *, const int, const int<2>); + DST altivec_dst {} + + void __builtin_altivec_dstst (void *, const int, const int<2>); + DSTST altivec_dstst {} + + void __builtin_altivec_dststt (void *, const int, const int<2>); + DSTSTT altivec_dststt {} + + void __builtin_altivec_dstt (void *, const int, const int<2>); + DSTT altivec_dstt {} + + fpmath vsi __builtin_altivec_fix_sfsi (vf); + FIX_V4SF_V4SI fix_truncv4sfv4si2 {} + + fpmath vui __builtin_altivec_fixuns_sfsi (vf); + FIXUNS_V4SF_V4SI fixuns_truncv4sfv4si2 {} + + fpmath vf __builtin_altivec_float_sisf (vsi); + FLOAT_V4SI_V4SF floatv4siv4sf2 {} + + pure vsc __builtin_altivec_lvebx (signed long, const void *); + LVEBX altivec_lvebx {ldvec} + + pure vss __builtin_altivec_lvehx (signed long, const void *); + LVEHX altivec_lvehx {ldvec} + + pure vsi __builtin_altivec_lvewx (signed long, const void *); + LVEWX altivec_lvewx {ldvec} + + pure vuc __builtin_altivec_lvsl (signed long, const void *); + LVSL altivec_lvsl {ldvec} + + pure vuc __builtin_altivec_lvsr (signed long, const void *); + LVSR altivec_lvsr {ldvec} + + pure vsi __builtin_altivec_lvx (signed long, const void *); + LVX altivec_lvx_v4si {ldvec} + + pure vsq __builtin_altivec_lvx_v1ti (signed long, const void *); + LVX_V1TI altivec_lvx_v1ti {ldvec} + + pure vsc __builtin_altivec_lvx_v16qi (signed long, const void *); + LVX_V16QI altivec_lvx_v16qi {ldvec} + + pure vf __builtin_altivec_lvx_v4sf (signed long, const void *); + LVX_V4SF altivec_lvx_v4sf {ldvec} + + pure vsi __builtin_altivec_lvx_v4si (signed long, const void *); + LVX_V4SI altivec_lvx_v4si {ldvec} + + pure vss __builtin_altivec_lvx_v8hi (signed long, const void *); + LVX_V8HI altivec_lvx_v8hi {ldvec} + + pure vsi __builtin_altivec_lvxl (signed long, const void *); + LVXL altivec_lvxl_v4si {ldvec} + + pure vsc __builtin_altivec_lvxl_v16qi (signed long, const void *); + LVXL_V16QI altivec_lvxl_v16qi {ldvec} + + pure vf __builtin_altivec_lvxl_v4sf (signed long, const void *); + LVXL_V4SF altivec_lvxl_v4sf {ldvec} + + pure vsi __builtin_altivec_lvxl_v4si (signed long, const void *); + LVXL_V4SI altivec_lvxl_v4si {ldvec} + + pure vss __builtin_altivec_lvxl_v8hi (signed long, const void *); + LVXL_V8HI altivec_lvxl_v8hi {ldvec} + + const vsc __builtin_altivec_mask_for_load (const void *); + MASK_FOR_LOAD altivec_lvsr_direct {ldstmask} + + vss __builtin_altivec_mfvscr (); + MFVSCR altivec_mfvscr {} + + void __builtin_altivec_mtvscr (vsi); + MTVSCR altivec_mtvscr {} + + const vsll __builtin_altivec_vmulesw (vsi, vsi); + VMULESW vec_widen_smult_even_v4si {} + + const vull __builtin_altivec_vmuleuw (vui, vui); + VMULEUW vec_widen_umult_even_v4si {} + + const vsll __builtin_altivec_vmulosw (vsi, vsi); + VMULOSW vec_widen_smult_odd_v4si {} + + const vull __builtin_altivec_vmulouw (vui, vui); + VMULOUW vec_widen_umult_odd_v4si {} + + const vsc __builtin_altivec_nabs_v16qi (vsc); + NABS_V16QI nabsv16qi2 {} + + const vf __builtin_altivec_nabs_v4sf (vf); + NABS_V4SF vsx_nabsv4sf2 {} + + const vsi __builtin_altivec_nabs_v4si (vsi); + NABS_V4SI nabsv4si2 {} + + const vss __builtin_altivec_nabs_v8hi (vss); + NABS_V8HI nabsv8hi2 {} + + void __builtin_altivec_stvebx (vsc, signed long, void *); + STVEBX altivec_stvebx {stvec} + + void __builtin_altivec_stvehx (vss, signed long, void *); + STVEHX altivec_stvehx {stvec} + + void __builtin_altivec_stvewx (vsi, signed long, void *); + STVEWX altivec_stvewx {stvec} + + void __builtin_altivec_stvx (vsi, signed long, void *); + STVX altivec_stvx_v4si {stvec} + + void __builtin_altivec_stvx_v16qi (vsc, signed long, void *); + STVX_V16QI altivec_stvx_v16qi {stvec} + + void __builtin_altivec_stvx_v4sf (vf, signed long, void *); + STVX_V4SF altivec_stvx_v4sf {stvec} + + void __builtin_altivec_stvx_v4si (vsi, signed long, void *); + STVX_V4SI altivec_stvx_v4si {stvec} + + void __builtin_altivec_stvx_v8hi (vss, signed long, void *); + STVX_V8HI altivec_stvx_v8hi {stvec} + + void __builtin_altivec_stvxl (vsi, signed long, void *); + STVXL altivec_stvxl_v4si {stvec} + + void __builtin_altivec_stvxl_v16qi (vsc, signed long, void *); + STVXL_V16QI altivec_stvxl_v16qi {stvec} + + void __builtin_altivec_stvxl_v4sf (vf, signed long, void *); + STVXL_V4SF altivec_stvxl_v4sf {stvec} + + void __builtin_altivec_stvxl_v4si (vsi, signed long, void *); + STVXL_V4SI altivec_stvxl_v4si {stvec} + + void __builtin_altivec_stvxl_v8hi (vss, signed long, void *); + STVXL_V8HI altivec_stvxl_v8hi {stvec} + + fpmath vf __builtin_altivec_uns_float_sisf (vui); + UNSFLOAT_V4SI_V4SF floatunsv4siv4sf2 {} + + const vui __builtin_altivec_vaddcuw (vui, vui); + VADDCUW altivec_vaddcuw {} + + const vf __builtin_altivec_vaddfp (vf, vf); + VADDFP addv4sf3 {} + + const vsc __builtin_altivec_vaddsbs (vsc, vsc); + VADDSBS altivec_vaddsbs {} + + const vss __builtin_altivec_vaddshs (vss, vss); + VADDSHS altivec_vaddshs {} + + const vsi __builtin_altivec_vaddsws (vsi, vsi); + VADDSWS altivec_vaddsws {} + + const vuc __builtin_altivec_vaddubm (vuc, vuc); + VADDUBM addv16qi3 {} + + const vuc __builtin_altivec_vaddubs (vuc, vuc); + VADDUBS altivec_vaddubs {} + + const vus __builtin_altivec_vadduhm (vus, vus); + VADDUHM addv8hi3 {} + + const vus __builtin_altivec_vadduhs (vus, vus); + VADDUHS altivec_vadduhs {} + + const vsi __builtin_altivec_vadduwm (vsi, vsi); + VADDUWM addv4si3 {} + + const vui __builtin_altivec_vadduws (vui, vui); + VADDUWS altivec_vadduws {} + + const vsc __builtin_altivec_vand_v16qi (vsc, vsc); + VAND_V16QI andv16qi3 {} + + const vuc __builtin_altivec_vand_v16qi_uns (vuc, vuc); + VAND_V16QI_UNS andv16qi3 {} + + const vf __builtin_altivec_vand_v4sf (vf, vf); + VAND_V4SF andv4sf3 {} + + const vsi __builtin_altivec_vand_v4si (vsi, vsi); + VAND_V4SI andv4si3 {} + + const vui __builtin_altivec_vand_v4si_uns (vui, vui); + VAND_V4SI_UNS andv4si3 {} + + const vss __builtin_altivec_vand_v8hi (vss, vss); + VAND_V8HI andv8hi3 {} + + const vus __builtin_altivec_vand_v8hi_uns (vus, vus); + VAND_V8HI_UNS andv8hi3 {} + + const vsc __builtin_altivec_vandc_v16qi (vsc, vsc); + VANDC_V16QI andcv16qi3 {} + + const vuc __builtin_altivec_vandc_v16qi_uns (vuc, vuc); + VANDC_V16QI_UNS andcv16qi3 {} + + const vf __builtin_altivec_vandc_v4sf (vf, vf); + VANDC_V4SF andcv4sf3 {} + + const vsi __builtin_altivec_vandc_v4si (vsi, vsi); + VANDC_V4SI andcv4si3 {} + + const vui __builtin_altivec_vandc_v4si_uns (vui, vui); + VANDC_V4SI_UNS andcv4si3 {} + + const vss __builtin_altivec_vandc_v8hi (vss, vss); + VANDC_V8HI andcv8hi3 {} + + const vus __builtin_altivec_vandc_v8hi_uns (vus, vus); + VANDC_V8HI_UNS andcv8hi3 {} + + const vsc __builtin_altivec_vavgsb (vsc, vsc); + VAVGSB avgv16qi3_ceil {} + + const vss __builtin_altivec_vavgsh (vss, vss); + VAVGSH avgv8hi3_ceil {} + + const vsi __builtin_altivec_vavgsw (vsi, vsi); + VAVGSW avgv4si3_ceil {} + + const vuc __builtin_altivec_vavgub (vuc, vuc); + VAVGUB uavgv16qi3_ceil {} + + const vus __builtin_altivec_vavguh (vus, vus); + VAVGUH uavgv8hi3_ceil {} + + const vui __builtin_altivec_vavguw (vui, vui); + VAVGUW uavgv4si3_ceil {} + + const vf __builtin_altivec_vcfsx (vsi, const int<5>); + VCFSX altivec_vcfsx {} + + const vf __builtin_altivec_vcfux (vui, const int<5>); + VCFUX altivec_vcfux {} + + const vsi __builtin_altivec_vcmpbfp (vf, vf); + VCMPBFP altivec_vcmpbfp {} + + const int __builtin_altivec_vcmpbfp_p (int, vf, vf); + VCMPBFP_P altivec_vcmpbfp_p {pred} + + const vf __builtin_altivec_vcmpeqfp (vf, vf); + VCMPEQFP vector_eqv4sf {} + + const int __builtin_altivec_vcmpeqfp_p (int, vf, vf); + VCMPEQFP_P vector_eq_v4sf_p {pred} + + const vsc __builtin_altivec_vcmpequb (vuc, vuc); + VCMPEQUB vector_eqv16qi {} + + const int __builtin_altivec_vcmpequb_p (int, vsc, vsc); + VCMPEQUB_P vector_eq_v16qi_p {pred} + + const vss __builtin_altivec_vcmpequh (vus, vus); + VCMPEQUH vector_eqv8hi {} + + const int __builtin_altivec_vcmpequh_p (int, vss, vss); + VCMPEQUH_P vector_eq_v8hi_p {pred} + + const vsi __builtin_altivec_vcmpequw (vui, vui); + VCMPEQUW vector_eqv4si {} + + const int __builtin_altivec_vcmpequw_p (int, vsi, vsi); + VCMPEQUW_P vector_eq_v4si_p {pred} + + const vf __builtin_altivec_vcmpgefp (vf, vf); + VCMPGEFP vector_gev4sf {} + + const int __builtin_altivec_vcmpgefp_p (int, vf, vf); + VCMPGEFP_P vector_ge_v4sf_p {pred} + + const vf __builtin_altivec_vcmpgtfp (vf, vf); + VCMPGTFP vector_gtv4sf {} + + const int __builtin_altivec_vcmpgtfp_p (int, vf, vf); + VCMPGTFP_P vector_gt_v4sf_p {pred} + + const vsc __builtin_altivec_vcmpgtsb (vsc, vsc); + VCMPGTSB vector_gtv16qi {} + + const int __builtin_altivec_vcmpgtsb_p (int, vsc, vsc); + VCMPGTSB_P vector_gt_v16qi_p {pred} + + const vss __builtin_altivec_vcmpgtsh (vss, vss); + VCMPGTSH vector_gtv8hi {} + + const int __builtin_altivec_vcmpgtsh_p (int, vss, vss); + VCMPGTSH_P vector_gt_v8hi_p {pred} + + const vsi __builtin_altivec_vcmpgtsw (vsi, vsi); + VCMPGTSW vector_gtv4si {} + + const int __builtin_altivec_vcmpgtsw_p (int, vsi, vsi); + VCMPGTSW_P vector_gt_v4si_p {pred} + + const vsc __builtin_altivec_vcmpgtub (vuc, vuc); + VCMPGTUB vector_gtuv16qi {} + + const int __builtin_altivec_vcmpgtub_p (int, vsc, vsc); + VCMPGTUB_P vector_gtu_v16qi_p {pred} + + const vss __builtin_altivec_vcmpgtuh (vus, vus); + VCMPGTUH vector_gtuv8hi {} + + const int __builtin_altivec_vcmpgtuh_p (int, vss, vss); + VCMPGTUH_P vector_gtu_v8hi_p {pred} + + const vsi __builtin_altivec_vcmpgtuw (vui, vui); + VCMPGTUW vector_gtuv4si {} + + const int __builtin_altivec_vcmpgtuw_p (int, vsi, vsi); + VCMPGTUW_P vector_gtu_v4si_p {pred} + + const vsi __builtin_altivec_vctsxs (vf, const int<5>); + VCTSXS altivec_vctsxs {} + + const vui __builtin_altivec_vctuxs (vf, const int<5>); + VCTUXS altivec_vctuxs {} + + fpmath vf __builtin_altivec_vexptefp (vf); + VEXPTEFP altivec_vexptefp {} + + fpmath vf __builtin_altivec_vlogefp (vf); + VLOGEFP altivec_vlogefp {} + + fpmath vf __builtin_altivec_vmaddfp (vf, vf, vf); + VMADDFP fmav4sf4 {} + + const vf __builtin_altivec_vmaxfp (vf, vf); + VMAXFP smaxv4sf3 {} + + const vsc __builtin_altivec_vmaxsb (vsc, vsc); + VMAXSB smaxv16qi3 {} + + const vuc __builtin_altivec_vmaxub (vuc, vuc); + VMAXUB umaxv16qi3 {} + + const vss __builtin_altivec_vmaxsh (vss, vss); + VMAXSH smaxv8hi3 {} + + const vsi __builtin_altivec_vmaxsw (vsi, vsi); + VMAXSW smaxv4si3 {} + + const vus __builtin_altivec_vmaxuh (vus, vus); + VMAXUH umaxv8hi3 {} + + const vui __builtin_altivec_vmaxuw (vui, vui); + VMAXUW umaxv4si3 {} + + vss __builtin_altivec_vmhaddshs (vss, vss, vss); + VMHADDSHS altivec_vmhaddshs {} + + vss __builtin_altivec_vmhraddshs (vss, vss, vss); + VMHRADDSHS altivec_vmhraddshs {} + + const vf __builtin_altivec_vminfp (vf, vf); + VMINFP sminv4sf3 {} + + const vsc __builtin_altivec_vminsb (vsc, vsc); + VMINSB sminv16qi3 {} + + const vss __builtin_altivec_vminsh (vss, vss); + VMINSH sminv8hi3 {} + + const vsi __builtin_altivec_vminsw (vsi, vsi); + VMINSW sminv4si3 {} + + const vuc __builtin_altivec_vminub (vuc, vuc); + VMINUB uminv16qi3 {} + + const vus __builtin_altivec_vminuh (vus, vus); + VMINUH uminv8hi3 {} + + const vui __builtin_altivec_vminuw (vui, vui); + VMINUW uminv4si3 {} + + const vss __builtin_altivec_vmladduhm (vss, vss, vss); + VMLADDUHM fmav8hi4 {} + + const vsc __builtin_altivec_vmrghb (vsc, vsc); + VMRGHB altivec_vmrghb {} + + const vss __builtin_altivec_vmrghh (vss, vss); + VMRGHH altivec_vmrghh {} + + const vsi __builtin_altivec_vmrghw (vsi, vsi); + VMRGHW altivec_vmrghw {} + + const vsc __builtin_altivec_vmrglb (vsc, vsc); + VMRGLB altivec_vmrglb {} + + const vss __builtin_altivec_vmrglh (vss, vss); + VMRGLH altivec_vmrglh {} + + const vsi __builtin_altivec_vmrglw (vsi, vsi); + VMRGLW altivec_vmrglw {} + + const vsi __builtin_altivec_vmsummbm (vsc, vuc, vsi); + VMSUMMBM altivec_vmsummbm {} + + const vsi __builtin_altivec_vmsumshm (vss, vss, vsi); + VMSUMSHM altivec_vmsumshm {} + + vsi __builtin_altivec_vmsumshs (vss, vss, vsi); + VMSUMSHS altivec_vmsumshs {} + + const vui __builtin_altivec_vmsumubm (vuc, vuc, vui); + VMSUMUBM altivec_vmsumubm {} + + const vui __builtin_altivec_vmsumuhm (vus, vus, vui); + VMSUMUHM altivec_vmsumuhm {} + + vui __builtin_altivec_vmsumuhs (vus, vus, vui); + VMSUMUHS altivec_vmsumuhs {} + + const vss __builtin_altivec_vmulesb (vsc, vsc); + VMULESB vec_widen_smult_even_v16qi {} + + const vsi __builtin_altivec_vmulesh (vss, vss); + VMULESH vec_widen_smult_even_v8hi {} + + const vus __builtin_altivec_vmuleub (vuc, vuc); + VMULEUB vec_widen_umult_even_v16qi {} + + const vui __builtin_altivec_vmuleuh (vus, vus); + VMULEUH vec_widen_umult_even_v8hi {} + + const vss __builtin_altivec_vmulosb (vsc, vsc); + VMULOSB vec_widen_smult_odd_v16qi {} + + const vus __builtin_altivec_vmuloub (vuc, vuc); + VMULOUB vec_widen_umult_odd_v16qi {} + + const vsi __builtin_altivec_vmulosh (vss, vss); + VMULOSH vec_widen_smult_odd_v8hi {} + + const vui __builtin_altivec_vmulouh (vus, vus); + VMULOUH vec_widen_umult_odd_v8hi {} + + fpmath vf __builtin_altivec_vnmsubfp (vf, vf, vf); + VNMSUBFP nfmsv4sf4 {} + + const vsc __builtin_altivec_vnor_v16qi (vsc, vsc); + VNOR_V16QI norv16qi3 {} + + const vuc __builtin_altivec_vnor_v16qi_uns (vuc, vuc); + VNOR_V16QI_UNS norv16qi3 {} + + const vf __builtin_altivec_vnor_v4sf (vf, vf); + VNOR_V4SF norv4sf3 {} + + const vsi __builtin_altivec_vnor_v4si (vsi, vsi); + VNOR_V4SI norv4si3 {} + + const vui __builtin_altivec_vnor_v4si_uns (vui, vui); + VNOR_V4SI_UNS norv4si3 {} + + const vss __builtin_altivec_vnor_v8hi (vss, vss); + VNOR_V8HI norv8hi3 {} + + const vus __builtin_altivec_vnor_v8hi_uns (vus, vus); + VNOR_V8HI_UNS norv8hi3 {} + + const vsc __builtin_altivec_vor_v16qi (vsc, vsc); + VOR_V16QI iorv16qi3 {} + + const vuc __builtin_altivec_vor_v16qi_uns (vuc, vuc); + VOR_V16QI_UNS iorv16qi3 {} + + const vf __builtin_altivec_vor_v4sf (vf, vf); + VOR_V4SF iorv4sf3 {} + + const vsi __builtin_altivec_vor_v4si (vsi, vsi); + VOR_V4SI iorv4si3 {} + + const vui __builtin_altivec_vor_v4si_uns (vui, vui); + VOR_V4SI_UNS iorv4si3 {} + + const vss __builtin_altivec_vor_v8hi (vss, vss); + VOR_V8HI iorv8hi3 {} + + const vus __builtin_altivec_vor_v8hi_uns (vus, vus); + VOR_V8HI_UNS iorv8hi3 {} + + const vsc __builtin_altivec_vperm_16qi (vsc, vsc, vuc); + VPERM_16QI altivec_vperm_v16qi {} + + const vuc __builtin_altivec_vperm_16qi_uns (vuc, vuc, vuc); + VPERM_16QI_UNS altivec_vperm_v16qi_uns {} + + const vsq __builtin_altivec_vperm_1ti (vsq, vsq, vuc); + VPERM_1TI altivec_vperm_v1ti {} + + const vuq __builtin_altivec_vperm_1ti_uns (vuq, vuq, vuc); + VPERM_1TI_UNS altivec_vperm_v1ti_uns {} + + const vf __builtin_altivec_vperm_4sf (vf, vf, vuc); + VPERM_4SF altivec_vperm_v4sf {} + + const vsi __builtin_altivec_vperm_4si (vsi, vsi, vuc); + VPERM_4SI altivec_vperm_v4si {} + + const vui __builtin_altivec_vperm_4si_uns (vui, vui, vuc); + VPERM_4SI_UNS altivec_vperm_v4si_uns {} + + const vss __builtin_altivec_vperm_8hi (vss, vss, vuc); + VPERM_8HI altivec_vperm_v8hi {} + + const vus __builtin_altivec_vperm_8hi_uns (vus, vus, vuc); + VPERM_8HI_UNS altivec_vperm_v8hi_uns {} + + const vp __builtin_altivec_vpkpx (vui, vui); + VPKPX altivec_vpkpx {} + + const vsc __builtin_altivec_vpkshss (vss, vss); + VPKSHSS altivec_vpkshss {} + + const vuc __builtin_altivec_vpkshus (vss, vss); + VPKSHUS altivec_vpkshus {} + + const vss __builtin_altivec_vpkswss (vsi, vsi); + VPKSWSS altivec_vpkswss {} + + const vus __builtin_altivec_vpkswus (vsi, vsi); + VPKSWUS altivec_vpkswus {} + + const vsc __builtin_altivec_vpkuhum (vss, vss); + VPKUHUM altivec_vpkuhum {} + + const vuc __builtin_altivec_vpkuhus (vus, vus); + VPKUHUS altivec_vpkuhus {} + + const vss __builtin_altivec_vpkuwum (vsi, vsi); + VPKUWUM altivec_vpkuwum {} + + const vus __builtin_altivec_vpkuwus (vui, vui); + VPKUWUS altivec_vpkuwus {} + + const vf __builtin_altivec_vrecipdivfp (vf, vf); + VRECIPFP recipv4sf3 {} + + fpmath vf __builtin_altivec_vrefp (vf); + VREFP rev4sf2 {} + + const vsc __builtin_altivec_vreve_v16qi (vsc); + VREVE_V16QI altivec_vrevev16qi2 {} + + const vf __builtin_altivec_vreve_v4sf (vf); + VREVE_V4SF altivec_vrevev4sf2 {} + + const vsi __builtin_altivec_vreve_v4si (vsi); + VREVE_V4SI altivec_vrevev4si2 {} + + const vss __builtin_altivec_vreve_v8hi (vss); + VREVE_V8HI altivec_vrevev8hi2 {} + + fpmath vf __builtin_altivec_vrfim (vf); + VRFIM vector_floorv4sf2 {} + + fpmath vf __builtin_altivec_vrfin (vf); + VRFIN altivec_vrfin {} + + fpmath vf __builtin_altivec_vrfip (vf); + VRFIP vector_ceilv4sf2 {} + + fpmath vf __builtin_altivec_vrfiz (vf); + VRFIZ vector_btruncv4sf2 {} + + const vsc __builtin_altivec_vrlb (vsc, vsc); + VRLB vrotlv16qi3 {} + + const vss __builtin_altivec_vrlh (vss, vss); + VRLH vrotlv8hi3 {} + + const vsi __builtin_altivec_vrlw (vsi, vsi); + VRLW vrotlv4si3 {} + + fpmath vf __builtin_altivec_vrsqrtefp (vf); + VRSQRTEFP rsqrtev4sf2 {} + + fpmath vf __builtin_altivec_vrsqrtfp (vf); + VRSQRTFP rsqrtv4sf2 {} + + const vsc __builtin_altivec_vsel_16qi (vsc, vsc, vuc); + VSEL_16QI vector_select_v16qi {} + + const vuc __builtin_altivec_vsel_16qi_uns (vuc, vuc, vuc); + VSEL_16QI_UNS vector_select_v16qi_uns {} + + const vsq __builtin_altivec_vsel_1ti (vsq, vsq, vuq); + VSEL_1TI vector_select_v1ti {} + + const vuq __builtin_altivec_vsel_1ti_uns (vuq, vuq, vuq); + VSEL_1TI_UNS vector_select_v1ti_uns {} + + const vf __builtin_altivec_vsel_4sf (vf, vf, vf); + VSEL_4SF vector_select_v4sf {} + + const vsi __builtin_altivec_vsel_4si (vsi, vsi, vui); + VSEL_4SI vector_select_v4si {} + + const vui __builtin_altivec_vsel_4si_uns (vui, vui, vui); + VSEL_4SI_UNS vector_select_v4si_uns {} + + const vss __builtin_altivec_vsel_8hi (vss, vss, vus); + VSEL_8HI vector_select_v8hi {} + + const vus __builtin_altivec_vsel_8hi_uns (vus, vus, vus); + VSEL_8HI_UNS vector_select_v8hi_uns {} + + const vsi __builtin_altivec_vsl (vsi, vsi); + VSL altivec_vsl {} + + const vsc __builtin_altivec_vslb (vsc, vuc); + VSLB vashlv16qi3 {} + + const vsc __builtin_altivec_vsldoi_16qi (vsc, vsc, const int<4>); + VSLDOI_16QI altivec_vsldoi_v16qi {} + + const vf __builtin_altivec_vsldoi_4sf (vf, vf, const int<4>); + VSLDOI_4SF altivec_vsldoi_v4sf {} + + const vsi __builtin_altivec_vsldoi_4si (vsi, vsi, const int<4>); + VSLDOI_4SI altivec_vsldoi_v4si {} + + const vss __builtin_altivec_vsldoi_8hi (vss, vss, const int<4>); + VSLDOI_8HI altivec_vsldoi_v8hi {} + + const vss __builtin_altivec_vslh (vss, vus); + VSLH vashlv8hi3 {} + + const vsi __builtin_altivec_vslo (vsi, vsi); + VSLO altivec_vslo {} + + const vsi __builtin_altivec_vslw (vsi, vui); + VSLW vashlv4si3 {} + + const vsc __builtin_altivec_vspltb (vsc, const int<4>); + VSPLTB altivec_vspltb {} + + const vss __builtin_altivec_vsplth (vss, const int<3>); + VSPLTH altivec_vsplth {} + + const vsc __builtin_altivec_vspltisb (const int<-16,15>); + VSPLTISB altivec_vspltisb {} + + const vss __builtin_altivec_vspltish (const int<-16,15>); + VSPLTISH altivec_vspltish {} + + const vsi __builtin_altivec_vspltisw (const int<-16,15>); + VSPLTISW altivec_vspltisw {} + + const vsi __builtin_altivec_vspltw (vsi, const int<2>); + VSPLTW altivec_vspltw {} + + const vsi __builtin_altivec_vsr (vsi, vsi); + VSR altivec_vsr {} + + const vsc __builtin_altivec_vsrab (vsc, vuc); + VSRAB vashrv16qi3 {} + + const vss __builtin_altivec_vsrah (vss, vus); + VSRAH vashrv8hi3 {} + + const vsi __builtin_altivec_vsraw (vsi, vui); + VSRAW vashrv4si3 {} + + const vsc __builtin_altivec_vsrb (vsc, vuc); + VSRB vlshrv16qi3 {} + + const vss __builtin_altivec_vsrh (vss, vus); + VSRH vlshrv8hi3 {} + + const vsi __builtin_altivec_vsro (vsi, vsi); + VSRO altivec_vsro {} + + const vsi __builtin_altivec_vsrw (vsi, vui); + VSRW vlshrv4si3 {} + + const vsi __builtin_altivec_vsubcuw (vsi, vsi); + VSUBCUW altivec_vsubcuw {} + + const vf __builtin_altivec_vsubfp (vf, vf); + VSUBFP subv4sf3 {} + + const vsc __builtin_altivec_vsubsbs (vsc, vsc); + VSUBSBS altivec_vsubsbs {} + + const vss __builtin_altivec_vsubshs (vss, vss); + VSUBSHS altivec_vsubshs {} + + const vsi __builtin_altivec_vsubsws (vsi, vsi); + VSUBSWS altivec_vsubsws {} + + const vuc __builtin_altivec_vsububm (vuc, vuc); + VSUBUBM subv16qi3 {} + + const vuc __builtin_altivec_vsububs (vuc, vuc); + VSUBUBS altivec_vsububs {} + + const vus __builtin_altivec_vsubuhm (vus, vus); + VSUBUHM subv8hi3 {} + + const vus __builtin_altivec_vsubuhs (vus, vus); + VSUBUHS altivec_vsubuhs {} + + const vui __builtin_altivec_vsubuwm (vui, vui); + VSUBUWM subv4si3 {} + + const vui __builtin_altivec_vsubuws (vui, vui); + VSUBUWS altivec_vsubuws {} + + const vsi __builtin_altivec_vsum2sws (vsi, vsi); + VSUM2SWS altivec_vsum2sws {} + + const vsi __builtin_altivec_vsum4sbs (vsc, vsi); + VSUM4SBS altivec_vsum4sbs {} + + const vsi __builtin_altivec_vsum4shs (vss, vsi); + VSUM4SHS altivec_vsum4shs {} + + const vui __builtin_altivec_vsum4ubs (vuc, vui); + VSUM4UBS altivec_vsum4ubs {} + + const vsi __builtin_altivec_vsumsws (vsi, vsi); + VSUMSWS altivec_vsumsws {} + + const vsi __builtin_altivec_vsumsws_be (vsi, vsi); + VSUMSWS_BE altivec_vsumsws_direct {} + + const vui __builtin_altivec_vupkhpx (vp); + VUPKHPX altivec_vupkhpx {} + + const vss __builtin_altivec_vupkhsb (vsc); + VUPKHSB altivec_vupkhsb {} + + const vsi __builtin_altivec_vupkhsh (vss); + VUPKHSH altivec_vupkhsh {} + + const vui __builtin_altivec_vupklpx (vp); + VUPKLPX altivec_vupklpx {} + + const vss __builtin_altivec_vupklsb (vsc); + VUPKLSB altivec_vupklsb {} + + const vsi __builtin_altivec_vupklsh (vss); + VUPKLSH altivec_vupklsh {} + + const vsc __builtin_altivec_vxor_v16qi (vsc, vsc); + VXOR_V16QI xorv16qi3 {} + + const vuc __builtin_altivec_vxor_v16qi_uns (vuc, vuc); + VXOR_V16QI_UNS xorv16qi3 {} + + const vf __builtin_altivec_vxor_v4sf (vf, vf); + VXOR_V4SF xorv4sf3 {} + + const vsi __builtin_altivec_vxor_v4si (vsi, vsi); + VXOR_V4SI xorv4si3 {} + + const vui __builtin_altivec_vxor_v4si_uns (vui, vui); + VXOR_V4SI_UNS xorv4si3 {} + + const vss __builtin_altivec_vxor_v8hi (vss, vss); + VXOR_V8HI xorv8hi3 {} + + const vus __builtin_altivec_vxor_v8hi_uns (vus, vus); + VXOR_V8HI_UNS xorv8hi3 {} + + const signed char __builtin_vec_ext_v16qi (vsc, signed int); + VEC_EXT_V16QI nothing {extract} + + const float __builtin_vec_ext_v4sf (vf, signed int); + VEC_EXT_V4SF nothing {extract} + + const signed int __builtin_vec_ext_v4si (vsi, signed int); + VEC_EXT_V4SI nothing {extract} + + const signed short __builtin_vec_ext_v8hi (vss, signed int); + VEC_EXT_V8HI nothing {extract} + + const vsc __builtin_vec_init_v16qi (signed char, signed char, signed char, \ + signed char, signed char, signed char, signed char, signed char, \ + signed char, signed char, signed char, signed char, signed char, \ + signed char, signed char, signed char); + VEC_INIT_V16QI nothing {init} + + const vf __builtin_vec_init_v4sf (float, float, float, float); + VEC_INIT_V4SF nothing {init} + + const vsi __builtin_vec_init_v4si (signed int, signed int, signed int, \ + signed int); + VEC_INIT_V4SI nothing {init} + + const vss __builtin_vec_init_v8hi (signed short, signed short, signed short,\ + signed short, signed short, signed short, signed short, \ + signed short); + VEC_INIT_V8HI nothing {init} + + const vsc __builtin_vec_set_v16qi (vsc, signed char, const int<4>); + VEC_SET_V16QI nothing {set} + + const vf __builtin_vec_set_v4sf (vf, float, const int<2>); + VEC_SET_V4SF nothing {set} + + const vsi __builtin_vec_set_v4si (vsi, signed int, const int<2>); + VEC_SET_V4SI nothing {set} + + const vss __builtin_vec_set_v8hi (vss, signed short, const int<3>); + VEC_SET_V8HI nothing {set} + + +; Cell builtins. +[cell] + pure vsc __builtin_altivec_lvlx (signed long, const void *); + LVLX altivec_lvlx {ldvec} + + pure vsc __builtin_altivec_lvlxl (signed long, const void *); + LVLXL altivec_lvlxl {ldvec} + + pure vsc __builtin_altivec_lvrx (signed long, const void *); + LVRX altivec_lvrx {ldvec} + + pure vsc __builtin_altivec_lvrxl (signed long, const void *); + LVRXL altivec_lvrxl {ldvec} + + void __builtin_altivec_stvlx (vsc, signed long, void *); + STVLX altivec_stvlx {stvec} + + void __builtin_altivec_stvlxl (vsc, signed long, void *); + STVLXL altivec_stvlxl {stvec} + + void __builtin_altivec_stvrx (vsc, signed long, void *); + STVRX altivec_stvrx {stvec} + + void __builtin_altivec_stvrxl (vsc, signed long, void *); + STVRXL altivec_stvrxl {stvec} + + +; VSX builtins. +[vsx] + pure vd __builtin_altivec_lvx_v2df (signed long, const void *); + LVX_V2DF altivec_lvx_v2df {ldvec} + + pure vsll __builtin_altivec_lvx_v2di (signed long, const void *); + LVX_V2DI altivec_lvx_v2di {ldvec} + + pure vd __builtin_altivec_lvxl_v2df (signed long, const void *); + LVXL_V2DF altivec_lvxl_v2df {ldvec} + + pure vsll __builtin_altivec_lvxl_v2di (signed long, const void *); + LVXL_V2DI altivec_lvxl_v2di {ldvec} + + const vd __builtin_altivec_nabs_v2df (vd); + NABS_V2DF vsx_nabsv2df2 {} + + const vsll __builtin_altivec_nabs_v2di (vsll); + NABS_V2DI nabsv2di2 {} + + void __builtin_altivec_stvx_v2df (vd, signed long, void *); + STVX_V2DF altivec_stvx_v2df {stvec} + + void __builtin_altivec_stvx_v2di (vsll, signed long, void *); + STVX_V2DI altivec_stvx_v2di {stvec} + + void __builtin_altivec_stvxl_v2df (vd, signed long, void *); + STVXL_V2DF altivec_stvxl_v2df {stvec} + + void __builtin_altivec_stvxl_v2di (vsll, signed long, void *); + STVXL_V2DI altivec_stvxl_v2di {stvec} + + const vd __builtin_altivec_vand_v2df (vd, vd); + VAND_V2DF andv2df3 {} + + const vsll __builtin_altivec_vand_v2di (vsll, vsll); + VAND_V2DI andv2di3 {} + + const vull __builtin_altivec_vand_v2di_uns (vull, vull); + VAND_V2DI_UNS andv2di3 {} + + const vd __builtin_altivec_vandc_v2df (vd, vd); + VANDC_V2DF andcv2df3 {} + + const vsll __builtin_altivec_vandc_v2di (vsll, vsll); + VANDC_V2DI andcv2di3 {} + + const vull __builtin_altivec_vandc_v2di_uns (vull, vull); + VANDC_V2DI_UNS andcv2di3 {} + + const vd __builtin_altivec_vnor_v2df (vd, vd); + VNOR_V2DF norv2df3 {} + + const vsll __builtin_altivec_vnor_v2di (vsll, vsll); + VNOR_V2DI norv2di3 {} + + const vull __builtin_altivec_vnor_v2di_uns (vull, vull); + VNOR_V2DI_UNS norv2di3 {} + + const vd __builtin_altivec_vor_v2df (vd, vd); + VOR_V2DF iorv2df3 {} + + const vsll __builtin_altivec_vor_v2di (vsll, vsll); + VOR_V2DI iorv2di3 {} + + const vull __builtin_altivec_vor_v2di_uns (vull, vull); + VOR_V2DI_UNS iorv2di3 {} + + const vd __builtin_altivec_vperm_2df (vd, vd, vuc); + VPERM_2DF altivec_vperm_v2df {} + + const vsll __builtin_altivec_vperm_2di (vsll, vsll, vuc); + VPERM_2DI altivec_vperm_v2di {} + + const vull __builtin_altivec_vperm_2di_uns (vull, vull, vuc); + VPERM_2DI_UNS altivec_vperm_v2di_uns {} + + const vd __builtin_altivec_vreve_v2df (vd); + VREVE_V2DF altivec_vrevev2df2 {} + + const vsll __builtin_altivec_vreve_v2di (vsll); + VREVE_V2DI altivec_vrevev2di2 {} + + const vd __builtin_altivec_vsel_2df (vd, vd, vd); + VSEL_2DF vector_select_v2df {} + + const vsll __builtin_altivec_vsel_2di (vsll, vsll, vsll); + VSEL_2DI_B vector_select_v2di {} + + const vull __builtin_altivec_vsel_2di_uns (vull, vull, vull); + VSEL_2DI_UNS vector_select_v2di_uns {} + + const vd __builtin_altivec_vsldoi_2df (vd, vd, const int<4>); + VSLDOI_2DF altivec_vsldoi_v2df {} + + const vsll __builtin_altivec_vsldoi_2di (vsll, vsll, const int<4>); + VSLDOI_2DI altivec_vsldoi_v2di {} + + const vd __builtin_altivec_vxor_v2df (vd, vd); + VXOR_V2DF xorv2df3 {} + + const vsll __builtin_altivec_vxor_v2di (vsll, vsll); + VXOR_V2DI xorv2di3 {} + + const vull __builtin_altivec_vxor_v2di_uns (vull, vull); + VXOR_V2DI_UNS xorv2di3 {} + + const signed __int128 __builtin_vec_ext_v1ti (vsq, signed int); + VEC_EXT_V1TI nothing {extract} + + const double __builtin_vec_ext_v2df (vd, signed int); + VEC_EXT_V2DF nothing {extract} + + const signed long long __builtin_vec_ext_v2di (vsll, signed int); + VEC_EXT_V2DI nothing {extract} + + const vsq __builtin_vec_init_v1ti (signed __int128); + VEC_INIT_V1TI nothing {init} + + const vd __builtin_vec_init_v2df (double, double); + VEC_INIT_V2DF nothing {init} + + const vsll __builtin_vec_init_v2di (signed long long, signed long long); + VEC_INIT_V2DI nothing {init} + + const vsq __builtin_vec_set_v1ti (vsq, signed __int128, const int<0,0>); + VEC_SET_V1TI nothing {set} + + const vd __builtin_vec_set_v2df (vd, double, const int<1>); + VEC_SET_V2DF nothing {set} + + const vsll __builtin_vec_set_v2di (vsll, signed long long, const int<1>); + VEC_SET_V2DI nothing {set} + + const vsc __builtin_vsx_cmpge_16qi (vsc, vsc); + CMPGE_16QI vector_nltv16qi {} + + const vsll __builtin_vsx_cmpge_2di (vsll, vsll); + CMPGE_2DI vector_nltv2di {} + + const vsi __builtin_vsx_cmpge_4si (vsi, vsi); + CMPGE_4SI vector_nltv4si {} + + const vss __builtin_vsx_cmpge_8hi (vss, vss); + CMPGE_8HI vector_nltv8hi {} + + const vsc __builtin_vsx_cmpge_u16qi (vuc, vuc); + CMPGE_U16QI vector_nltuv16qi {} + + const vsll __builtin_vsx_cmpge_u2di (vull, vull); + CMPGE_U2DI vector_nltuv2di {} + + const vsi __builtin_vsx_cmpge_u4si (vui, vui); + CMPGE_U4SI vector_nltuv4si {} + + const vss __builtin_vsx_cmpge_u8hi (vus, vus); + CMPGE_U8HI vector_nltuv8hi {} + + const vsc __builtin_vsx_cmple_16qi (vsc, vsc); + CMPLE_16QI vector_ngtv16qi {} + + const vsll __builtin_vsx_cmple_2di (vsll, vsll); + CMPLE_2DI vector_ngtv2di {} + + const vsi __builtin_vsx_cmple_4si (vsi, vsi); + CMPLE_4SI vector_ngtv4si {} + + const vss __builtin_vsx_cmple_8hi (vss, vss); + CMPLE_8HI vector_ngtv8hi {} + + const vsc __builtin_vsx_cmple_u16qi (vsc, vsc); + CMPLE_U16QI vector_ngtuv16qi {} + + const vsll __builtin_vsx_cmple_u2di (vsll, vsll); + CMPLE_U2DI vector_ngtuv2di {} + + const vsi __builtin_vsx_cmple_u4si (vsi, vsi); + CMPLE_U4SI vector_ngtuv4si {} + + const vss __builtin_vsx_cmple_u8hi (vss, vss); + CMPLE_U8HI vector_ngtuv8hi {} + + const vd __builtin_vsx_concat_2df (double, double); + CONCAT_2DF vsx_concat_v2df {} + + const vsll __builtin_vsx_concat_2di (signed long long, signed long long); + CONCAT_2DI vsx_concat_v2di {} + + const vd __builtin_vsx_cpsgndp (vd, vd); + CPSGNDP vector_copysignv2df3 {} + + const vf __builtin_vsx_cpsgnsp (vf, vf); + CPSGNSP vector_copysignv4sf3 {} + + const vsll __builtin_vsx_div_2di (vsll, vsll); + DIV_V2DI vsx_div_v2di {} + + const vd __builtin_vsx_doublee_v4sf (vf); + DOUBLEE_V4SF doubleev4sf2 {} + + const vd __builtin_vsx_doublee_v4si (vsi); + DOUBLEE_V4SI doubleev4si2 {} + + const vd __builtin_vsx_doubleh_v4sf (vf); + DOUBLEH_V4SF doublehv4sf2 {} + + const vd __builtin_vsx_doubleh_v4si (vsi); + DOUBLEH_V4SI doublehv4si2 {} + + const vd __builtin_vsx_doublel_v4sf (vf); + DOUBLEL_V4SF doublelv4sf2 {} + + const vd __builtin_vsx_doublel_v4si (vsi); + DOUBLEL_V4SI doublelv4si2 {} + + const vd __builtin_vsx_doubleo_v4sf (vf); + DOUBLEO_V4SF doubleov4sf2 {} + + const vd __builtin_vsx_doubleo_v4si (vsi); + DOUBLEO_V4SI doubleov4si2 {} + + const vf __builtin_vsx_floate_v2df (vd); + FLOATE_V2DF floatev2df {} + + const vf __builtin_vsx_floate_v2di (vsll); + FLOATE_V2DI floatev2di {} + + const vf __builtin_vsx_floato_v2df (vd); + FLOATO_V2DF floatov2df {} + + const vf __builtin_vsx_floato_v2di (vsll); + FLOATO_V2DI floatov2di {} + + pure vsq __builtin_vsx_ld_elemrev_v1ti (signed long, const void *); + LD_ELEMREV_V1TI vsx_ld_elemrev_v1ti {ldvec,endian} + + pure vd __builtin_vsx_ld_elemrev_v2df (signed long, const void *); + LD_ELEMREV_V2DF vsx_ld_elemrev_v2df {ldvec,endian} + + pure vsll __builtin_vsx_ld_elemrev_v2di (signed long, const void *); + LD_ELEMREV_V2DI vsx_ld_elemrev_v2di {ldvec,endian} + + pure vf __builtin_vsx_ld_elemrev_v4sf (signed long, const void *); + LD_ELEMREV_V4SF vsx_ld_elemrev_v4sf {ldvec,endian} + + pure vsi __builtin_vsx_ld_elemrev_v4si (signed long, const void *); + LD_ELEMREV_V4SI vsx_ld_elemrev_v4si {ldvec,endian} + + pure vss __builtin_vsx_ld_elemrev_v8hi (signed long, const void *); + LD_ELEMREV_V8HI vsx_ld_elemrev_v8hi {ldvec,endian} + + pure vsc __builtin_vsx_ld_elemrev_v16qi (signed long, const void *); + LD_ELEMREV_V16QI vsx_ld_elemrev_v16qi {ldvec,endian} + +; TODO: There is apparent intent in rs6000-builtin.def to have +; RS6000_BTC_SPECIAL processing for LXSDX, LXVDSX, and STXSDX, but there are +; no def_builtin calls for any of them. At some point, we may want to add a +; set of built-ins for whichever vector types make sense for these. + + pure vsq __builtin_vsx_lxvd2x_v1ti (signed long, const void *); + LXVD2X_V1TI vsx_load_v1ti {ldvec} + + pure vd __builtin_vsx_lxvd2x_v2df (signed long, const void *); + LXVD2X_V2DF vsx_load_v2df {ldvec} + + pure vsll __builtin_vsx_lxvd2x_v2di (signed long, const void *); + LXVD2X_V2DI vsx_load_v2di {ldvec} + + pure vsc __builtin_vsx_lxvw4x_v16qi (signed long, const void *); + LXVW4X_V16QI vsx_load_v16qi {ldvec} + + pure vf __builtin_vsx_lxvw4x_v4sf (signed long, const void *); + LXVW4X_V4SF vsx_load_v4sf {ldvec} + + pure vsi __builtin_vsx_lxvw4x_v4si (signed long, const void *); + LXVW4X_V4SI vsx_load_v4si {ldvec} + + pure vss __builtin_vsx_lxvw4x_v8hi (signed long, const void *); + LXVW4X_V8HI vsx_load_v8hi {ldvec} + + const vd __builtin_vsx_mergeh_2df (vd, vd); + VEC_MERGEH_V2DF vsx_mergeh_v2df {} + + const vsll __builtin_vsx_mergeh_2di (vsll, vsll); + VEC_MERGEH_V2DI vsx_mergeh_v2di {} + + const vd __builtin_vsx_mergel_2df (vd, vd); + VEC_MERGEL_V2DF vsx_mergel_v2df {} + + const vsll __builtin_vsx_mergel_2di (vsll, vsll); + VEC_MERGEL_V2DI vsx_mergel_v2di {} + + const vsll __builtin_vsx_mul_2di (vsll, vsll); + MUL_V2DI vsx_mul_v2di {} + + const vsq __builtin_vsx_set_1ti (vsq, signed __int128, const int<0,0>); + SET_1TI vsx_set_v1ti {set} + + const vd __builtin_vsx_set_2df (vd, double, const int<0,1>); + SET_2DF vsx_set_v2df {set} + + const vsll __builtin_vsx_set_2di (vsll, signed long long, const int<0,1>); + SET_2DI vsx_set_v2di {set} + + const vd __builtin_vsx_splat_2df (double); + SPLAT_2DF vsx_splat_v2df {} + + const vsll __builtin_vsx_splat_2di (signed long long); + SPLAT_2DI vsx_splat_v2di {} + + void __builtin_vsx_st_elemrev_v1ti (vsq, signed long, void *); + ST_ELEMREV_V1TI vsx_st_elemrev_v1ti {stvec,endian} + + void __builtin_vsx_st_elemrev_v2df (vd, signed long, void *); + ST_ELEMREV_V2DF vsx_st_elemrev_v2df {stvec,endian} + + void __builtin_vsx_st_elemrev_v2di (vsll, signed long, void *); + ST_ELEMREV_V2DI vsx_st_elemrev_v2di {stvec,endian} + + void __builtin_vsx_st_elemrev_v4sf (vf, signed long, void *); + ST_ELEMREV_V4SF vsx_st_elemrev_v4sf {stvec,endian} + + void __builtin_vsx_st_elemrev_v4si (vsi, signed long, void *); + ST_ELEMREV_V4SI vsx_st_elemrev_v4si {stvec,endian} + + void __builtin_vsx_st_elemrev_v8hi (vss, signed long, void *); + ST_ELEMREV_V8HI vsx_st_elemrev_v8hi {stvec,endian} + + void __builtin_vsx_st_elemrev_v16qi (vsc, signed long, void *); + ST_ELEMREV_V16QI vsx_st_elemrev_v16qi {stvec,endian} + + void __builtin_vsx_stxvd2x_v1ti (vsq, signed long, void *); + STXVD2X_V1TI vsx_store_v1ti {stvec} + + void __builtin_vsx_stxvd2x_v2df (vd, signed long, void *); + STXVD2X_V2DF vsx_store_v2df {stvec} + + void __builtin_vsx_stxvd2x_v2di (vsll, signed long, void *); + STXVD2X_V2DI vsx_store_v2di {stvec} + + void __builtin_vsx_stxvw4x_v4sf (vf, signed long, void *); + STXVW4X_V4SF vsx_store_v4sf {stvec} + + void __builtin_vsx_stxvw4x_v4si (vsi, signed long, void *); + STXVW4X_V4SI vsx_store_v4si {stvec} + + void __builtin_vsx_stxvw4x_v8hi (vss, signed long, void *); + STXVW4X_V8HI vsx_store_v8hi {stvec} + + void __builtin_vsx_stxvw4x_v16qi (vsc, signed long, void *); + STXVW4X_V16QI vsx_store_v16qi {stvec} + + const vull __builtin_vsx_udiv_2di (vull, vull); + UDIV_V2DI vsx_udiv_v2di {} + + const vd __builtin_vsx_uns_doublee_v4si (vsi); + UNS_DOUBLEE_V4SI unsdoubleev4si2 {} + + const vd __builtin_vsx_uns_doubleh_v4si (vsi); + UNS_DOUBLEH_V4SI unsdoublehv4si2 {} + + const vd __builtin_vsx_uns_doublel_v4si (vsi); + UNS_DOUBLEL_V4SI unsdoublelv4si2 {} + + const vd __builtin_vsx_uns_doubleo_v4si (vsi); + UNS_DOUBLEO_V4SI unsdoubleov4si2 {} + + const vf __builtin_vsx_uns_floate_v2di (vsll); + UNS_FLOATE_V2DI unsfloatev2di {} + + const vf __builtin_vsx_uns_floato_v2di (vsll); + UNS_FLOATO_V2DI unsfloatov2di {} + +; These are duplicates of __builtin_altivec_* counterparts, and are being +; kept for backwards compatibility. The reason for their existence is +; unclear. TODO: Consider deprecation/removal at some point. + const vsc __builtin_vsx_vperm_16qi (vsc, vsc, vuc); + VPERM_16QI_X altivec_vperm_v16qi {} + + const vuc __builtin_vsx_vperm_16qi_uns (vuc, vuc, vuc); + VPERM_16QI_UNS_X altivec_vperm_v16qi_uns {} + + const vsq __builtin_vsx_vperm_1ti (vsq, vsq, vsc); + VPERM_1TI_X altivec_vperm_v1ti {} + + const vsq __builtin_vsx_vperm_1ti_uns (vsq, vsq, vsc); + VPERM_1TI_UNS_X altivec_vperm_v1ti_uns {} + + const vd __builtin_vsx_vperm_2df (vd, vd, vuc); + VPERM_2DF_X altivec_vperm_v2df {} + + const vsll __builtin_vsx_vperm_2di (vsll, vsll, vuc); + VPERM_2DI_X altivec_vperm_v2di {} + + const vull __builtin_vsx_vperm_2di_uns (vull, vull, vuc); + VPERM_2DI_UNS_X altivec_vperm_v2di_uns {} + + const vf __builtin_vsx_vperm_4sf (vf, vf, vuc); + VPERM_4SF_X altivec_vperm_v4sf {} + + const vsi __builtin_vsx_vperm_4si (vsi, vsi, vuc); + VPERM_4SI_X altivec_vperm_v4si {} + + const vui __builtin_vsx_vperm_4si_uns (vui, vui, vuc); + VPERM_4SI_UNS_X altivec_vperm_v4si_uns {} + + const vss __builtin_vsx_vperm_8hi (vss, vss, vuc); + VPERM_8HI_X altivec_vperm_v8hi {} + + const vus __builtin_vsx_vperm_8hi_uns (vus, vus, vuc); + VPERM_8HI_UNS_X altivec_vperm_v8hi_uns {} + + const vsll __builtin_vsx_vsigned_v2df (vd); + VEC_VSIGNED_V2DF vsx_xvcvdpsxds {} + + const vsi __builtin_vsx_vsigned_v4sf (vf); + VEC_VSIGNED_V4SF vsx_xvcvspsxws {} + + const vsi __builtin_vsx_vsignede_v2df (vd); + VEC_VSIGNEDE_V2DF vsignede_v2df {} + + const vsi __builtin_vsx_vsignedo_v2df (vd); + VEC_VSIGNEDO_V2DF vsignedo_v2df {} + + const vsll __builtin_vsx_vunsigned_v2df (vd); + VEC_VUNSIGNED_V2DF vsx_xvcvdpsxds {} + + const vsi __builtin_vsx_vunsigned_v4sf (vf); + VEC_VUNSIGNED_V4SF vsx_xvcvspsxws {} + + const vsi __builtin_vsx_vunsignede_v2df (vd); + VEC_VUNSIGNEDE_V2DF vunsignede_v2df {} + + const vsi __builtin_vsx_vunsignedo_v2df (vd); + VEC_VUNSIGNEDO_V2DF vunsignedo_v2df {} + + const vf __builtin_vsx_xscvdpsp (double); + XSCVDPSP vsx_xscvdpsp {} + + const double __builtin_vsx_xscvspdp (vf); + XSCVSPDP vsx_xscvspdp {} + + const double __builtin_vsx_xsmaxdp (double, double); + XSMAXDP smaxdf3 {} + + const double __builtin_vsx_xsmindp (double, double); + XSMINDP smindf3 {} + + const double __builtin_vsx_xsrdpi (double); + XSRDPI vsx_xsrdpi {} + + const double __builtin_vsx_xsrdpic (double); + XSRDPIC vsx_xsrdpic {} + + const double __builtin_vsx_xsrdpim (double); + XSRDPIM floordf2 {} + + const double __builtin_vsx_xsrdpip (double); + XSRDPIP ceildf2 {} + + const double __builtin_vsx_xsrdpiz (double); + XSRDPIZ btruncdf2 {} + + const signed int __builtin_vsx_xstdivdp_fe (double, double); + XSTDIVDP_FE vsx_tdivdf3_fe {} + + const signed int __builtin_vsx_xstdivdp_fg (double, double); + XSTDIVDP_FG vsx_tdivdf3_fg {} + + const signed int __builtin_vsx_xstsqrtdp_fe (double); + XSTSQRTDP_FE vsx_tsqrtdf2_fe {} + + const signed int __builtin_vsx_xstsqrtdp_fg (double); + XSTSQRTDP_FG vsx_tsqrtdf2_fg {} + + const vd __builtin_vsx_xvabsdp (vd); + XVABSDP absv2df2 {} + + const vf __builtin_vsx_xvabssp (vf); + XVABSSP absv4sf2 {} + + fpmath vd __builtin_vsx_xvadddp (vd, vd); + XVADDDP addv2df3 {} + + fpmath vf __builtin_vsx_xvaddsp (vf, vf); + XVADDSP addv4sf3 {} + + const vd __builtin_vsx_xvcmpeqdp (vd, vd); + XVCMPEQDP vector_eqv2df {} + + const signed int __builtin_vsx_xvcmpeqdp_p (signed int, vd, vd); + XVCMPEQDP_P vector_eq_v2df_p {pred} + + const vf __builtin_vsx_xvcmpeqsp (vf, vf); + XVCMPEQSP vector_eqv4sf {} + + const signed int __builtin_vsx_xvcmpeqsp_p (signed int, vf, vf); + XVCMPEQSP_P vector_eq_v4sf_p {pred} + + const vd __builtin_vsx_xvcmpgedp (vd, vd); + XVCMPGEDP vector_gev2df {} + + const signed int __builtin_vsx_xvcmpgedp_p (signed int, vd, vd); + XVCMPGEDP_P vector_ge_v2df_p {pred} + + const vf __builtin_vsx_xvcmpgesp (vf, vf); + XVCMPGESP vector_gev4sf {} + + const signed int __builtin_vsx_xvcmpgesp_p (signed int, vf, vf); + XVCMPGESP_P vector_ge_v4sf_p {pred} + + const vd __builtin_vsx_xvcmpgtdp (vd, vd); + XVCMPGTDP vector_gtv2df {} + + const signed int __builtin_vsx_xvcmpgtdp_p (signed int, vd, vd); + XVCMPGTDP_P vector_gt_v2df_p {pred} + + const vf __builtin_vsx_xvcmpgtsp (vf, vf); + XVCMPGTSP vector_gtv4sf {} + + const signed int __builtin_vsx_xvcmpgtsp_p (signed int, vf, vf); + XVCMPGTSP_P vector_gt_v4sf_p {pred} + + const vf __builtin_vsx_xvcvdpsp (vd); + XVCVDPSP vsx_xvcvdpsp {} + + const vsll __builtin_vsx_xvcvdpsxds (vd); + XVCVDPSXDS vsx_fix_truncv2dfv2di2 {} + + const vsll __builtin_vsx_xvcvdpsxds_scale (vd, const int); + XVCVDPSXDS_SCALE vsx_xvcvdpsxds_scale {} + + const vsi __builtin_vsx_xvcvdpsxws (vd); + XVCVDPSXWS vsx_xvcvdpsxws {} + + const vsll __builtin_vsx_xvcvdpuxds (vd); + XVCVDPUXDS vsx_fixuns_truncv2dfv2di2 {} + + const vsll __builtin_vsx_xvcvdpuxds_scale (vd, const int); + XVCVDPUXDS_SCALE vsx_xvcvdpuxds_scale {} + + const vull __builtin_vsx_xvcvdpuxds_uns (vd); + XVCVDPUXDS_UNS vsx_fixuns_truncv2dfv2di2 {} + + const vsi __builtin_vsx_xvcvdpuxws (vd); + XVCVDPUXWS vsx_xvcvdpuxws {} + + const vd __builtin_vsx_xvcvspdp (vf); + XVCVSPDP vsx_xvcvspdp {} + + const vsll __builtin_vsx_xvcvspsxds (vf); + XVCVSPSXDS vsx_xvcvspsxds {} + + const vsi __builtin_vsx_xvcvspsxws (vf); + XVCVSPSXWS vsx_fix_truncv4sfv4si2 {} + + const vsll __builtin_vsx_xvcvspuxds (vf); + XVCVSPUXDS vsx_xvcvspuxds {} + + const vsi __builtin_vsx_xvcvspuxws (vf); + XVCVSPUXWS vsx_fixuns_truncv4sfv4si2 {} + + const vd __builtin_vsx_xvcvsxddp (vsll); + XVCVSXDDP vsx_floatv2div2df2 {} + + const vd __builtin_vsx_xvcvsxddp_scale (vsll, const int<5>); + XVCVSXDDP_SCALE vsx_xvcvsxddp_scale {} + + const vf __builtin_vsx_xvcvsxdsp (vsll); + XVCVSXDSP vsx_xvcvsxdsp {} + + const vd __builtin_vsx_xvcvsxwdp (vsi); + XVCVSXWDP vsx_xvcvsxwdp {} + + const vf __builtin_vsx_xvcvsxwsp (vsi); + XVCVSXWSP vsx_floatv4siv4sf2 {} + + const vd __builtin_vsx_xvcvuxddp (vsll); + XVCVUXDDP vsx_floatunsv2div2df2 {} + + const vd __builtin_vsx_xvcvuxddp_scale (vsll, const int<5>); + XVCVUXDDP_SCALE vsx_xvcvuxddp_scale {} + + const vd __builtin_vsx_xvcvuxddp_uns (vull); + XVCVUXDDP_UNS vsx_floatunsv2div2df2 {} + + const vf __builtin_vsx_xvcvuxdsp (vull); + XVCVUXDSP vsx_xvcvuxdsp {} + + const vd __builtin_vsx_xvcvuxwdp (vsi); + XVCVUXWDP vsx_xvcvuxwdp {} + + const vf __builtin_vsx_xvcvuxwsp (vsi); + XVCVUXWSP vsx_floatunsv4siv4sf2 {} + + fpmath vd __builtin_vsx_xvdivdp (vd, vd); + XVDIVDP divv2df3 {} + + fpmath vf __builtin_vsx_xvdivsp (vf, vf); + XVDIVSP divv4sf3 {} + + const vd __builtin_vsx_xvmadddp (vd, vd, vd); + XVMADDDP fmav2df4 {} + + const vf __builtin_vsx_xvmaddsp (vf, vf, vf); + XVMADDSP fmav4sf4 {} + + const vd __builtin_vsx_xvmaxdp (vd, vd); + XVMAXDP smaxv2df3 {} + + const vf __builtin_vsx_xvmaxsp (vf, vf); + XVMAXSP smaxv4sf3 {} + + const vd __builtin_vsx_xvmindp (vd, vd); + XVMINDP sminv2df3 {} + + const vf __builtin_vsx_xvminsp (vf, vf); + XVMINSP sminv4sf3 {} + + const vd __builtin_vsx_xvmsubdp (vd, vd, vd); + XVMSUBDP fmsv2df4 {} + + const vf __builtin_vsx_xvmsubsp (vf, vf, vf); + XVMSUBSP fmsv4sf4 {} + + fpmath vd __builtin_vsx_xvmuldp (vd, vd); + XVMULDP mulv2df3 {} + + fpmath vf __builtin_vsx_xvmulsp (vf, vf); + XVMULSP mulv4sf3 {} + + const vd __builtin_vsx_xvnabsdp (vd); + XVNABSDP vsx_nabsv2df2 {} + + const vf __builtin_vsx_xvnabssp (vf); + XVNABSSP vsx_nabsv4sf2 {} + + const vd __builtin_vsx_xvnegdp (vd); + XVNEGDP negv2df2 {} + + const vf __builtin_vsx_xvnegsp (vf); + XVNEGSP negv4sf2 {} + + const vd __builtin_vsx_xvnmadddp (vd, vd, vd); + XVNMADDDP nfmav2df4 {} + + const vf __builtin_vsx_xvnmaddsp (vf, vf, vf); + XVNMADDSP nfmav4sf4 {} + + const vd __builtin_vsx_xvnmsubdp (vd, vd, vd); + XVNMSUBDP nfmsv2df4 {} + + const vf __builtin_vsx_xvnmsubsp (vf, vf, vf); + XVNMSUBSP nfmsv4sf4 {} + + const vd __builtin_vsx_xvrdpi (vd); + XVRDPI vsx_xvrdpi {} + + const vd __builtin_vsx_xvrdpic (vd); + XVRDPIC vsx_xvrdpic {} + + const vd __builtin_vsx_xvrdpim (vd); + XVRDPIM vsx_floorv2df2 {} + + const vd __builtin_vsx_xvrdpip (vd); + XVRDPIP vsx_ceilv2df2 {} + + const vd __builtin_vsx_xvrdpiz (vd); + XVRDPIZ vsx_btruncv2df2 {} + + fpmath vd __builtin_vsx_xvrecipdivdp (vd, vd); + RECIP_V2DF recipv2df3 {} + + fpmath vf __builtin_vsx_xvrecipdivsp (vf, vf); + RECIP_V4SF recipv4sf3 {} + + const vd __builtin_vsx_xvredp (vd); + XVREDP vsx_frev2df2 {} + + const vf __builtin_vsx_xvresp (vf); + XVRESP vsx_frev4sf2 {} + + const vf __builtin_vsx_xvrspi (vf); + XVRSPI vsx_xvrspi {} + + const vf __builtin_vsx_xvrspic (vf); + XVRSPIC vsx_xvrspic {} + + const vf __builtin_vsx_xvrspim (vf); + XVRSPIM vsx_floorv4sf2 {} + + const vf __builtin_vsx_xvrspip (vf); + XVRSPIP vsx_ceilv4sf2 {} + + const vf __builtin_vsx_xvrspiz (vf); + XVRSPIZ vsx_btruncv4sf2 {} + + const vd __builtin_vsx_xvrsqrtdp (vd); + RSQRT_2DF rsqrtv2df2 {} + + const vf __builtin_vsx_xvrsqrtsp (vf); + RSQRT_4SF rsqrtv4sf2 {} + + const vd __builtin_vsx_xvrsqrtedp (vd); + XVRSQRTEDP rsqrtev2df2 {} + + const vf __builtin_vsx_xvrsqrtesp (vf); + XVRSQRTESP rsqrtev4sf2 {} + + const vd __builtin_vsx_xvsqrtdp (vd); + XVSQRTDP sqrtv2df2 {} + + const vf __builtin_vsx_xvsqrtsp (vf); + XVSQRTSP sqrtv4sf2 {} + + fpmath vd __builtin_vsx_xvsubdp (vd, vd); + XVSUBDP subv2df3 {} + + fpmath vf __builtin_vsx_xvsubsp (vf, vf); + XVSUBSP subv4sf3 {} + + const signed int __builtin_vsx_xvtdivdp_fe (vd, vd); + XVTDIVDP_FE vsx_tdivv2df3_fe {} + + const signed int __builtin_vsx_xvtdivdp_fg (vd, vd); + XVTDIVDP_FG vsx_tdivv2df3_fg {} + + const signed int __builtin_vsx_xvtdivsp_fe (vf, vf); + XVTDIVSP_FE vsx_tdivv4sf3_fe {} + + const signed int __builtin_vsx_xvtdivsp_fg (vf, vf); + XVTDIVSP_FG vsx_tdivv4sf3_fg {} + + const signed int __builtin_vsx_xvtsqrtdp_fe (vd); + XVTSQRTDP_FE vsx_tsqrtv2df2_fe {} + + const signed int __builtin_vsx_xvtsqrtdp_fg (vd); + XVTSQRTDP_FG vsx_tsqrtv2df2_fg {} + + const signed int __builtin_vsx_xvtsqrtsp_fe (vf); + XVTSQRTSP_FE vsx_tsqrtv4sf2_fe {} + + const signed int __builtin_vsx_xvtsqrtsp_fg (vf); + XVTSQRTSP_FG vsx_tsqrtv4sf2_fg {} + + const vf __builtin_vsx_xxmrghw (vf, vf); + XXMRGHW_4SF vsx_xxmrghw_v4sf {} + + const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi); + XXMRGHW_4SI vsx_xxmrghw_v4si {} + + const vf __builtin_vsx_xxmrglw (vf, vf); + XXMRGLW_4SF vsx_xxmrglw_v4sf {} + + const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi); + XXMRGLW_4SI vsx_xxmrglw_v4si {} + + const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<2>); + XXPERMDI_16QI vsx_xxpermdi_v16qi {} + + const vsq __builtin_vsx_xxpermdi_1ti (vsq, vsq, const int<2>); + XXPERMDI_1TI vsx_xxpermdi_v1ti {} + + const vd __builtin_vsx_xxpermdi_2df (vd, vd, const int<2>); + XXPERMDI_2DF vsx_xxpermdi_v2df {} + + const vsll __builtin_vsx_xxpermdi_2di (vsll, vsll, const int<2>); + XXPERMDI_2DI vsx_xxpermdi_v2di {} + + const vf __builtin_vsx_xxpermdi_4sf (vf, vf, const int<2>); + XXPERMDI_4SF vsx_xxpermdi_v4sf {} + + const vsi __builtin_vsx_xxpermdi_4si (vsi, vsi, const int<2>); + XXPERMDI_4SI vsx_xxpermdi_v4si {} + + const vss __builtin_vsx_xxpermdi_8hi (vss, vss, const int<2>); + XXPERMDI_8HI vsx_xxpermdi_v8hi {} + + const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc); + XXSEL_16QI vector_select_v16qi {} + + const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc); + XXSEL_16QI_UNS vector_select_v16qi_uns {} + + const vsq __builtin_vsx_xxsel_1ti (vsq, vsq, vsq); + XXSEL_1TI vector_select_v1ti {} + + const vsq __builtin_vsx_xxsel_1ti_uns (vsq, vsq, vsq); + XXSEL_1TI_UNS vector_select_v1ti_uns {} + + const vd __builtin_vsx_xxsel_2df (vd, vd, vd); + XXSEL_2DF vector_select_v2df {} + + const vsll __builtin_vsx_xxsel_2di (vsll, vsll, vsll); + XXSEL_2DI vector_select_v2di {} + + const vull __builtin_vsx_xxsel_2di_uns (vull, vull, vull); + XXSEL_2DI_UNS vector_select_v2di_uns {} + + const vf __builtin_vsx_xxsel_4sf (vf, vf, vf); + XXSEL_4SF vector_select_v4sf {} + + const vsi __builtin_vsx_xxsel_4si (vsi, vsi, vsi); + XXSEL_4SI vector_select_v4si {} + + const vui __builtin_vsx_xxsel_4si_uns (vui, vui, vui); + XXSEL_4SI_UNS vector_select_v4si_uns {} + + const vss __builtin_vsx_xxsel_8hi (vss, vss, vss); + XXSEL_8HI vector_select_v8hi {} + + const vus __builtin_vsx_xxsel_8hi_uns (vus, vus, vus); + XXSEL_8HI_UNS vector_select_v8hi_uns {} + + const vsc __builtin_vsx_xxsldwi_16qi (vsc, vsc, const int<2>); + XXSLDWI_16QI vsx_xxsldwi_v16qi {} + + const vd __builtin_vsx_xxsldwi_2df (vd, vd, const int<2>); + XXSLDWI_2DF vsx_xxsldwi_v2df {} + + const vsll __builtin_vsx_xxsldwi_2di (vsll, vsll, const int<2>); + XXSLDWI_2DI vsx_xxsldwi_v2di {} + + const vf __builtin_vsx_xxsldwi_4sf (vf, vf, const int<2>); + XXSLDWI_4SF vsx_xxsldwi_v4sf {} + + const vsi __builtin_vsx_xxsldwi_4si (vsi, vsi, const int<2>); + XXSLDWI_4SI vsx_xxsldwi_v4si {} + + const vss __builtin_vsx_xxsldwi_8hi (vss, vss, const int<2>); + XXSLDWI_8HI vsx_xxsldwi_v8hi {} + + const vd __builtin_vsx_xxspltd_2df (vd, const int<1>); + XXSPLTD_V2DF vsx_xxspltd_v2df {} + + const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>); + XXSPLTD_V2DI vsx_xxspltd_v2di {} + + +; Power7 builtins (ISA 2.06). +[power7] + const unsigned int __builtin_addg6s (unsigned int, unsigned int); + ADDG6S addg6s {} + + const signed long __builtin_bpermd (signed long, signed long); + BPERMD bpermd_di {32bit} + + const unsigned int __builtin_cbcdtd (unsigned int); + CBCDTD cbcdtd {} + + const unsigned int __builtin_cdtbcd (unsigned int); + CDTBCD cdtbcd {} + + const signed int __builtin_divwe (signed int, signed int); + DIVWE dive_si {} + + const unsigned int __builtin_divweu (unsigned int, unsigned int); + DIVWEU diveu_si {} + + const vsq __builtin_pack_vector_int128 (unsigned long long, \ + unsigned long long); + PACK_V1TI packv1ti {} + + void __builtin_ppc_speculation_barrier (); + SPECBARR speculation_barrier {} + + const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); + UNPACK_V1TI unpackv1ti {} + + +; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing). +[power7-64] + const signed long long __builtin_divde (signed long long, signed long long); + DIVDE dive_di {} + + const unsigned long long __builtin_divdeu (unsigned long long, \ + unsigned long long); + DIVDEU diveu_di {} + + +; Power8 vector built-ins. +[power8-vector] + const vsll __builtin_altivec_abs_v2di (vsll); + ABS_V2DI absv2di2 {} + + const vsc __builtin_altivec_bcddiv10_v16qi (vsc); + BCDDIV10_V16QI bcddiv10_v16qi {} + + const vsc __builtin_altivec_bcdmul10_v16qi (vsc); + BCDMUL10_V16QI bcdmul10_v16qi {} + + const vsc __builtin_altivec_eqv_v16qi (vsc, vsc); + EQV_V16QI eqvv16qi3 {} + + const vuc __builtin_altivec_eqv_v16qi_uns (vuc, vuc); + EQV_V16QI_UNS eqvv16qi3 {} + + const vsq __builtin_altivec_eqv_v1ti (vsq, vsq); + EQV_V1TI eqvv1ti3 {} + + const vuq __builtin_altivec_eqv_v1ti_uns (vuq, vuq); + EQV_V1TI_UNS eqvv1ti3 {} + + const vd __builtin_altivec_eqv_v2df (vd, vd); + EQV_V2DF eqvv2df3 {} + + const vsll __builtin_altivec_eqv_v2di (vsll, vsll); + EQV_V2DI eqvv2di3 {} + + const vull __builtin_altivec_eqv_v2di_uns (vull, vull); + EQV_V2DI_UNS eqvv2di3 {} + + const vf __builtin_altivec_eqv_v4sf (vf, vf); + EQV_V4SF eqvv4sf3 {} + + const vsi __builtin_altivec_eqv_v4si (vsi, vsi); + EQV_V4SI eqvv4si3 {} + + const vui __builtin_altivec_eqv_v4si_uns (vui, vui); + EQV_V4SI_UNS eqvv4si3 {} + + const vss __builtin_altivec_eqv_v8hi (vss, vss); + EQV_V8HI eqvv8hi3 {} + + const vus __builtin_altivec_eqv_v8hi_uns (vus, vus); + EQV_V8HI_UNS eqvv8hi3 {} + + const vsc __builtin_altivec_nand_v16qi (vsc, vsc); + NAND_V16QI nandv16qi3 {} + + const vuc __builtin_altivec_nand_v16qi_uns (vuc, vuc); + NAND_V16QI_UNS nandv16qi3 {} + + const vsq __builtin_altivec_nand_v1ti (vsq, vsq); + NAND_V1TI nandv1ti3 {} + + const vuq __builtin_altivec_nand_v1ti_uns (vuq, vuq); + NAND_V1TI_UNS nandv1ti3 {} + + const vd __builtin_altivec_nand_v2df (vd, vd); + NAND_V2DF nandv2df3 {} + + const vsll __builtin_altivec_nand_v2di (vsll, vsll); + NAND_V2DI nandv2di3 {} + + const vull __builtin_altivec_nand_v2di_uns (vull, vull); + NAND_V2DI_UNS nandv2di3 {} + + const vf __builtin_altivec_nand_v4sf (vf, vf); + NAND_V4SF nandv4sf3 {} + + const vsi __builtin_altivec_nand_v4si (vsi, vsi); + NAND_V4SI nandv4si3 {} + + const vui __builtin_altivec_nand_v4si_uns (vui, vui); + NAND_V4SI_UNS nandv4si3 {} + + const vss __builtin_altivec_nand_v8hi (vss, vss); + NAND_V8HI nandv8hi3 {} + + const vus __builtin_altivec_nand_v8hi_uns (vus, vus); + NAND_V8HI_UNS nandv8hi3 {} + + const vsc __builtin_altivec_neg_v16qi (vsc); + NEG_V16QI negv16qi2 {} + + const vd __builtin_altivec_neg_v2df (vd); + NEG_V2DF negv2df2 {} + + const vsll __builtin_altivec_neg_v2di (vsll); + NEG_V2DI negv2di2 {} + + const vf __builtin_altivec_neg_v4sf (vf); + NEG_V4SF negv4sf2 {} + + const vsi __builtin_altivec_neg_v4si (vsi); + NEG_V4SI negv4si2 {} + + const vss __builtin_altivec_neg_v8hi (vss); + NEG_V8HI negv8hi2 {} + + const vsc __builtin_altivec_orc_v16qi (vsc, vsc); + ORC_V16QI orcv16qi3 {} + + const vuc __builtin_altivec_orc_v16qi_uns (vuc, vuc); + ORC_V16QI_UNS orcv16qi3 {} + + const vsq __builtin_altivec_orc_v1ti (vsq, vsq); + ORC_V1TI orcv1ti3 {} + + const vuq __builtin_altivec_orc_v1ti_uns (vuq, vuq); + ORC_V1TI_UNS orcv1ti3 {} + + const vd __builtin_altivec_orc_v2df (vd, vd); + ORC_V2DF orcv2df3 {} + + const vsll __builtin_altivec_orc_v2di (vsll, vsll); + ORC_V2DI orcv2di3 {} + + const vull __builtin_altivec_orc_v2di_uns (vull, vull); + ORC_V2DI_UNS orcv2di3 {} + + const vf __builtin_altivec_orc_v4sf (vf, vf); + ORC_V4SF orcv4sf3 {} + + const vsi __builtin_altivec_orc_v4si (vsi, vsi); + ORC_V4SI orcv4si3 {} + + const vui __builtin_altivec_orc_v4si_uns (vui, vui); + ORC_V4SI_UNS orcv4si3 {} + + const vss __builtin_altivec_orc_v8hi (vss, vss); + ORC_V8HI orcv8hi3 {} + + const vus __builtin_altivec_orc_v8hi_uns (vus, vus); + ORC_V8HI_UNS orcv8hi3 {} + + const vsc __builtin_altivec_vclzb (vsc); + VCLZB clzv16qi2 {} + + const vsll __builtin_altivec_vclzd (vsll); + VCLZD clzv2di2 {} + + const vss __builtin_altivec_vclzh (vss); + VCLZH clzv8hi2 {} + + const vsi __builtin_altivec_vclzw (vsi); + VCLZW clzv4si2 {} + + const vuc __builtin_altivec_vgbbd (vuc); + VGBBD p8v_vgbbd {} + + const vsq __builtin_altivec_vaddcuq (vsq, vsq); + VADDCUQ altivec_vaddcuq {} + + const vsq __builtin_altivec_vaddecuq (vsq, vsq, vsq); + VADDECUQ altivec_vaddecuq {} + + const vsq __builtin_altivec_vaddeuqm (vsq, vsq, vsq); + VADDEUQM altivec_vaddeuqm {} + + const vsll __builtin_altivec_vaddudm (vsll, vsll); + VADDUDM addv2di3 {} + + const vsq __builtin_altivec_vadduqm (vsq, vsq); + VADDUQM altivec_vadduqm {} + + const vsll __builtin_altivec_vbpermq (vsc, vsc); + VBPERMQ altivec_vbpermq {} + + const vsc __builtin_altivec_vbpermq2 (vsc, vsc); + VBPERMQ2 altivec_vbpermq2 {} + + const vsll __builtin_altivec_vcmpequd (vull, vull); + VCMPEQUD vector_eqv2di {} + + const int __builtin_altivec_vcmpequd_p (int, vsll, vsll); + VCMPEQUD_P vector_eq_v2di_p {pred} + + const vsll __builtin_altivec_vcmpgtsd (vsll, vsll); + VCMPGTSD vector_gtv2di {} + + const int __builtin_altivec_vcmpgtsd_p (int, vsll, vsll); + VCMPGTSD_P vector_gt_v2di_p {pred} + + const vsll __builtin_altivec_vcmpgtud (vull, vull); + VCMPGTUD vector_gtuv2di {} + + const int __builtin_altivec_vcmpgtud_p (int, vsll, vsll); + VCMPGTUD_P vector_gtu_v2di_p {pred} + + const vsll __builtin_altivec_vmaxsd (vsll, vsll); + VMAXSD smaxv2di3 {} + + const vull __builtin_altivec_vmaxud (vull, vull); + VMAXUD umaxv2di3 {} + + const vsll __builtin_altivec_vminsd (vsll, vsll); + VMINSD sminv2di3 {} + + const vull __builtin_altivec_vminud (vull, vull); + VMINUD uminv2di3 {} + + const vd __builtin_altivec_vmrgew_v2df (vd, vd); + VMRGEW_V2DF p8_vmrgew_v2df {} + + const vsll __builtin_altivec_vmrgew_v2di (vsll, vsll); + VMRGEW_V2DI p8_vmrgew_v2di {} + + const vf __builtin_altivec_vmrgew_v4sf (vf, vf); + VMRGEW_V4SF p8_vmrgew_v4sf {} + + const vsi __builtin_altivec_vmrgew_v4si (vsi, vsi); + VMRGEW_V4SI p8_vmrgew_v4si {} + + const vd __builtin_altivec_vmrgow_v2df (vd, vd); + VMRGOW_V2DF p8_vmrgow_v2df {} + + const vsll __builtin_altivec_vmrgow_v2di (vsll, vsll); + VMRGOW_V2DI p8_vmrgow_v2di {} + + const vf __builtin_altivec_vmrgow_v4sf (vf, vf); + VMRGOW_V4SF p8_vmrgow_v4sf {} + + const vsi __builtin_altivec_vmrgow_v4si (vsi, vsi); + VMRGOW_V4SI p8_vmrgow_v4si {} + + const vsc __builtin_altivec_vpermxor (vsc, vsc, vsc); + VPERMXOR altivec_vpermxor {} + + const vsi __builtin_altivec_vpksdss (vsll, vsll); + VPKSDSS altivec_vpksdss {} + + const vsi __builtin_altivec_vpksdus (vsll, vsll); + VPKSDUS altivec_vpksdus {} + + const vsi __builtin_altivec_vpkudum (vsll, vsll); + VPKUDUM altivec_vpkudum {} + + const vsi __builtin_altivec_vpkudus (vsll, vsll); + VPKUDUS altivec_vpkudus {} + + const vsc __builtin_altivec_vpmsumb (vsc, vsc); + VPMSUMB_A crypto_vpmsumb {} + + const vsll __builtin_altivec_vpmsumd (vsll, vsll); + VPMSUMD_A crypto_vpmsumd {} + + const vss __builtin_altivec_vpmsumh (vss, vss); + VPMSUMH_A crypto_vpmsumh {} + + const vsi __builtin_altivec_vpmsumw (vsi, vsi); + VPMSUMW_A crypto_vpmsumw {} + + const vsc __builtin_altivec_vpopcntb (vsc); + VPOPCNTB popcountv16qi2 {} + + const vsll __builtin_altivec_vpopcntd (vsll); + VPOPCNTD popcountv2di2 {} + + const vss __builtin_altivec_vpopcnth (vss); + VPOPCNTH popcountv8hi2 {} + + const vsc __builtin_altivec_vpopcntub (vsc); + VPOPCNTUB popcountv16qi2 {} + + const vsll __builtin_altivec_vpopcntud (vsll); + VPOPCNTUD popcountv2di2 {} + + const vss __builtin_altivec_vpopcntuh (vss); + VPOPCNTUH popcountv8hi2 {} + + const vsi __builtin_altivec_vpopcntuw (vsi); + VPOPCNTUW popcountv4si2 {} + + const vsi __builtin_altivec_vpopcntw (vsi); + VPOPCNTW popcountv4si2 {} + + const vsll __builtin_altivec_vrld (vsll, vsll); + VRLD vrotlv2di3 {} + + const vsll __builtin_altivec_vsld (vsll, vsll); + VSLD vashlv2di3 {} + + const vsll __builtin_altivec_vsrad (vsll, vsll); + VSRAD vashrv2di3 {} + + const vsll __builtin_altivec_vsrd (vsll, vull); + VSRD vlshrv2di3 {} + + const vsq __builtin_altivec_vsubcuq (vsq, vsq); + VSUBCUQ altivec_vsubcuq {} + + const vsq __builtin_altivec_vsubecuq (vsq, vsq, vsq); + VSUBECUQ altivec_vsubecuq {} + + const vsq __builtin_altivec_vsubeuqm (vsq, vsq, vsq); + VSUBEUQM altivec_vsubeuqm {} + + const vsll __builtin_altivec_vsubudm (vsll, vsll); + VSUBUDM subv2di3 {} + + const vsq __builtin_altivec_vsubuqm (vsq, vsq); + VSUBUQM altivec_vsubuqm {} + + const vsll __builtin_altivec_vupkhsw (vsi); + VUPKHSW altivec_vupkhsw {} + + const vsll __builtin_altivec_vupklsw (vsi); + VUPKLSW altivec_vupklsw {} + + const vsq __builtin_bcdadd_v1ti (vsq, vsq, const int<1>); + BCDADD_V1TI bcdadd_v1ti {} + + const vsc __builtin_bcdadd_v16qi (vsc, vsc, const int<1>); + BCDADD_V16QI bcdadd_v16qi {} + + const signed int __builtin_bcdadd_eq_v1ti (vsq, vsq, const int<1>); + BCDADD_EQ_V1TI bcdadd_eq_v1ti {} + + const signed int __builtin_bcdadd_eq_v16qi (vsc, vsc, const int<1>); + BCDADD_EQ_V16QI bcdadd_eq_v16qi {} + + const signed int __builtin_bcdadd_gt_v1ti (vsq, vsq, const int<1>); + BCDADD_GT_V1TI bcdadd_gt_v1ti {} + + const signed int __builtin_bcdadd_gt_v16qi (vsc, vsc, const int<1>); + BCDADD_GT_V16QI bcdadd_gt_v16qi {} + + const signed int __builtin_bcdadd_lt_v1ti (vsq, vsq, const int<1>); + BCDADD_LT_V1TI bcdadd_lt_v1ti {} + + const signed int __builtin_bcdadd_lt_v16qi (vsc, vsc, const int<1>); + BCDADD_LT_V16QI bcdadd_lt_v16qi {} + + const signed int __builtin_bcdadd_ov_v1ti (vsq, vsq, const int<1>); + BCDADD_OV_V1TI bcdadd_unordered_v1ti {} + + const signed int __builtin_bcdadd_ov_v16qi (vsc, vsc, const int<1>); + BCDADD_OV_V16QI bcdadd_unordered_v16qi {} + + const signed int __builtin_bcdinvalid_v1ti (vsq); + BCDINVALID_V1TI bcdinvalid_v1ti {} + + const signed int __builtin_bcdinvalid_v16qi (vsc); + BCDINVALID_V16QI bcdinvalid_v16qi {} + + const vsq __builtin_bcdsub_v1ti (vsq, vsq, const int<1>); + BCDSUB_V1TI bcdsub_v1ti {} + + const vsc __builtin_bcdsub_v16qi (vsc, vsc, const int<1>); + BCDSUB_V16QI bcdsub_v16qi {} + + const signed int __builtin_bcdsub_eq_v1ti (vsq, vsq, const int<1>); + BCDSUB_EQ_V1TI bcdsub_eq_v1ti {} + + const signed int __builtin_bcdsub_eq_v16qi (vsc, vsc, const int<1>); + BCDSUB_EQ_V16QI bcdsub_eq_v16qi {} + + const signed int __builtin_bcdsub_ge_v1ti (vsq, vsq, const int<1>); + BCDSUB_GE_V1TI bcdsub_ge_v1ti {} + + const signed int __builtin_bcdsub_ge_v16qi (vsc, vsc, const int<1>); + BCDSUB_GE_V16QI bcdsub_ge_v16qi {} + + const signed int __builtin_bcdsub_gt_v1ti (vsq, vsq, const int<1>); + BCDSUB_GT_V1TI bcdsub_gt_v1ti {} + + const signed int __builtin_bcdsub_gt_v16qi (vsc, vsc, const int<1>); + BCDSUB_GT_V16QI bcdsub_gt_v16qi {} + + const signed int __builtin_bcdsub_le_v1ti (vsq, vsq, const int<1>); + BCDSUB_LE_V1TI bcdsub_le_v1ti {} + + const signed int __builtin_bcdsub_le_v16qi (vsc, vsc, const int<1>); + BCDSUB_LE_V16QI bcdsub_le_v16qi {} + + const signed int __builtin_bcdsub_lt_v1ti (vsq, vsq, const int<1>); + BCDSUB_LT_V1TI bcdsub_lt_v1ti {} + + const signed int __builtin_bcdsub_lt_v16qi (vsc, vsc, const int<1>); + BCDSUB_LT_V16QI bcdsub_lt_v16qi {} + + const signed int __builtin_bcdsub_ov_v1ti (vsq, vsq, const int<1>); + BCDSUB_OV_V1TI bcdsub_unordered_v1ti {} + + const signed int __builtin_bcdsub_ov_v16qi (vsc, vsc, const int<1>); + BCDSUB_OV_V16QI bcdsub_unordered_v16qi {} + + const vuc __builtin_crypto_vpermxor_v16qi (vuc, vuc, vuc); + VPERMXOR_V16QI crypto_vpermxor_v16qi {} + + const vull __builtin_crypto_vpermxor_v2di (vull, vull, vull); + VPERMXOR_V2DI crypto_vpermxor_v2di {} + + const vui __builtin_crypto_vpermxor_v4si (vui, vui, vui); + VPERMXOR_V4SI crypto_vpermxor_v4si {} + + const vus __builtin_crypto_vpermxor_v8hi (vus, vus, vus); + VPERMXOR_V8HI crypto_vpermxor_v8hi {} + + const vuc __builtin_crypto_vpmsumb (vuc, vuc); + VPMSUMB crypto_vpmsumb {} + + const vull __builtin_crypto_vpmsumd (vull, vull); + VPMSUMD crypto_vpmsumd {} + + const vus __builtin_crypto_vpmsumh (vus, vus); + VPMSUMH crypto_vpmsumh {} + + const vui __builtin_crypto_vpmsumw (vui, vui); + VPMSUMW crypto_vpmsumw {} + + const vf __builtin_vsx_float2_v2df (vd, vd); + FLOAT2_V2DF float2_v2df {} + + const vf __builtin_vsx_float2_v2di (vsll, vsll); + FLOAT2_V2DI float2_v2di {} + + const vsc __builtin_vsx_revb_v16qi (vsc); + REVB_V16QI revb_v16qi {} + + const vsq __builtin_vsx_revb_v1ti (vsq); + REVB_V1TI revb_v1ti {} + + const vd __builtin_vsx_revb_v2df (vd); + REVB_V2DF revb_v2df {} + + const vsll __builtin_vsx_revb_v2di (vsll); + REVB_V2DI revb_v2di {} + + const vf __builtin_vsx_revb_v4sf (vf); + REVB_V4SF revb_v4sf {} + + const vsi __builtin_vsx_revb_v4si (vsi); + REVB_V4SI revb_v4si {} + + const vss __builtin_vsx_revb_v8hi (vss); + REVB_V8HI revb_v8hi {} + + const vf __builtin_vsx_uns_float2_v2di (vsll, vsll); + UNS_FLOAT2_V2DI uns_float2_v2di {} + + const vsi __builtin_vsx_vsigned2_v2df (vd, vd); + VEC_VSIGNED2_V2DF vsigned2_v2df {} + + const vsi __builtin_vsx_vunsigned2_v2df (vd, vd); + VEC_VUNSIGNED2_V2DF vunsigned2_v2df {} + + const vf __builtin_vsx_xscvdpspn (double); + XSCVDPSPN vsx_xscvdpspn {} + + const double __builtin_vsx_xscvspdpn (vf); + XSCVSPDPN vsx_xscvspdpn {} + + +; Power9 vector builtins. +[power9-vector] + const vss __builtin_altivec_convert_4f32_8f16 (vf, vf); + CONVERT_4F32_8F16 convert_4f32_8f16 {} + + const vss __builtin_altivec_convert_4f32_8i16 (vf, vf); + CONVERT_4F32_8I16 convert_4f32_8i16 {} + + const signed int __builtin_altivec_first_match_index_v16qi (vsc, vsc); + VFIRSTMATCHINDEX_V16QI first_match_index_v16qi {} + + const signed int __builtin_altivec_first_match_index_v8hi (vss, vss); + VFIRSTMATCHINDEX_V8HI first_match_index_v8hi {} + + const signed int __builtin_altivec_first_match_index_v4si (vsi, vsi); + VFIRSTMATCHINDEX_V4SI first_match_index_v4si {} + + const signed int __builtin_altivec_first_match_or_eos_index_v16qi (vsc, vsc); + VFIRSTMATCHOREOSINDEX_V16QI first_match_or_eos_index_v16qi {} + + const signed int __builtin_altivec_first_match_or_eos_index_v8hi (vss, vss); + VFIRSTMATCHOREOSINDEX_V8HI first_match_or_eos_index_v8hi {} + + const signed int __builtin_altivec_first_match_or_eos_index_v4si (vsi, vsi); + VFIRSTMATCHOREOSINDEX_V4SI first_match_or_eos_index_v4si {} + + const signed int __builtin_altivec_first_mismatch_index_v16qi (vsc, vsc); + VFIRSTMISMATCHINDEX_V16QI first_mismatch_index_v16qi {} + + const signed int __builtin_altivec_first_mismatch_index_v8hi (vss, vss); + VFIRSTMISMATCHINDEX_V8HI first_mismatch_index_v8hi {} + + const signed int __builtin_altivec_first_mismatch_index_v4si (vsi, vsi); + VFIRSTMISMATCHINDEX_V4SI first_mismatch_index_v4si {} + + const signed int \ + __builtin_altivec_first_mismatch_or_eos_index_v16qi (vsc, vsc); + VFIRSTMISMATCHOREOSINDEX_V16QI first_mismatch_or_eos_index_v16qi {} + + const signed int \ + __builtin_altivec_first_mismatch_or_eos_index_v8hi (vss, vss); + VFIRSTMISMATCHOREOSINDEX_V8HI first_mismatch_or_eos_index_v8hi {} + + const signed int \ + __builtin_altivec_first_mismatch_or_eos_index_v4si (vsi, vsi); + VFIRSTMISMATCHOREOSINDEX_V4SI first_mismatch_or_eos_index_v4si {} + + const vsc __builtin_altivec_vadub (vsc, vsc); + VADUB vaduv16qi3 {} + + const vss __builtin_altivec_vaduh (vss, vss); + VADUH vaduv8hi3 {} + + const vsi __builtin_altivec_vaduw (vsi, vsi); + VADUW vaduv4si3 {} + + const vsll __builtin_altivec_vbpermd (vsll, vsc); + VBPERMD altivec_vbpermd {} + + const signed int __builtin_altivec_vclzlsbb_v16qi (vsc); + VCLZLSBB_V16QI vclzlsbb_v16qi {} + + const signed int __builtin_altivec_vclzlsbb_v4si (vsi); + VCLZLSBB_V4SI vclzlsbb_v4si {} + + const signed int __builtin_altivec_vclzlsbb_v8hi (vss); + VCLZLSBB_V8HI vclzlsbb_v8hi {} + + const vsc __builtin_altivec_vctzb (vsc); + VCTZB ctzv16qi2 {} + + const vsll __builtin_altivec_vctzd (vsll); + VCTZD ctzv2di2 {} + + const vss __builtin_altivec_vctzh (vss); + VCTZH ctzv8hi2 {} + + const vsi __builtin_altivec_vctzw (vsi); + VCTZW ctzv4si2 {} + + const signed int __builtin_altivec_vctzlsbb_v16qi (vsc); + VCTZLSBB_V16QI vctzlsbb_v16qi {} + + const signed int __builtin_altivec_vctzlsbb_v4si (vsi); + VCTZLSBB_V4SI vctzlsbb_v4si {} + + const signed int __builtin_altivec_vctzlsbb_v8hi (vss); + VCTZLSBB_V8HI vctzlsbb_v8hi {} + + const signed int __builtin_altivec_vcmpaeb_p (vsc, vsc); + VCMPAEB_P vector_ae_v16qi_p {} + + const signed int __builtin_altivec_vcmpaed_p (vsll, vsll); + VCMPAED_P vector_ae_v2di_p {} + + const signed int __builtin_altivec_vcmpaedp_p (vd, vd); + VCMPAEDP_P vector_ae_v2df_p {} + + const signed int __builtin_altivec_vcmpaefp_p (vf, vf); + VCMPAEFP_P vector_ae_v4sf_p {} + + const signed int __builtin_altivec_vcmpaeh_p (vss, vss); + VCMPAEH_P vector_ae_v8hi_p {} + + const signed int __builtin_altivec_vcmpaew_p (vsi, vsi); + VCMPAEW_P vector_ae_v4si_p {} + + const vsc __builtin_altivec_vcmpneb (vsc, vsc); + VCMPNEB vcmpneb {} + + const signed int __builtin_altivec_vcmpneb_p (vsc, vsc); + VCMPNEB_P vector_ne_v16qi_p {} + + const signed int __builtin_altivec_vcmpned_p (vsll, vsll); + VCMPNED_P vector_ne_v2di_p {} + + const signed int __builtin_altivec_vcmpnedp_p (vd, vd); + VCMPNEDP_P vector_ne_v2df_p {} + + const signed int __builtin_altivec_vcmpnefp_p (vf, vf); + VCMPNEFP_P vector_ne_v4sf_p {} + + const vss __builtin_altivec_vcmpneh (vss, vss); + VCMPNEH vcmpneh {} + + const signed int __builtin_altivec_vcmpneh_p (vss, vss); + VCMPNEH_P vector_ne_v8hi_p {} + + const vsi __builtin_altivec_vcmpnew (vsi, vsi); + VCMPNEW vcmpnew {} + + const signed int __builtin_altivec_vcmpnew_p (vsi, vsi); + VCMPNEW_P vector_ne_v4si_p {} + + const vsc __builtin_altivec_vcmpnezb (vsc, vsc); + CMPNEZB vcmpnezb {} + + const signed int __builtin_altivec_vcmpnezb_p (signed int, vsc, vsc); + VCMPNEZB_P vector_nez_v16qi_p {pred} + + const vss __builtin_altivec_vcmpnezh (vss, vss); + CMPNEZH vcmpnezh {} + + const signed int __builtin_altivec_vcmpnezh_p (signed int, vss, vss); + VCMPNEZH_P vector_nez_v8hi_p {pred} + + const vsi __builtin_altivec_vcmpnezw (vsi, vsi); + CMPNEZW vcmpnezw {} + + const signed int __builtin_altivec_vcmpnezw_p (signed int, vsi, vsi); + VCMPNEZW_P vector_nez_v4si_p {pred} + + const signed int __builtin_altivec_vextublx (signed int, vsc); + VEXTUBLX vextublx {} + + const signed int __builtin_altivec_vextubrx (signed int, vsc); + VEXTUBRX vextubrx {} + + const signed int __builtin_altivec_vextuhlx (signed int, vss); + VEXTUHLX vextuhlx {} + + const signed int __builtin_altivec_vextuhrx (signed int, vss); + VEXTUHRX vextuhrx {} + + const signed int __builtin_altivec_vextuwlx (signed int, vsi); + VEXTUWLX vextuwlx {} + + const signed int __builtin_altivec_vextuwrx (signed int, vsi); + VEXTUWRX vextuwrx {} + + const vsq __builtin_altivec_vmsumudm (vsll, vsll, vsq); + VMSUMUDM altivec_vmsumudm {} + + const vsll __builtin_altivec_vprtybd (vsll); + VPRTYBD parityv2di2 {} + + const vsq __builtin_altivec_vprtybq (vsq); + VPRTYBQ parityv1ti2 {} + + const vsi __builtin_altivec_vprtybw (vsi); + VPRTYBW parityv4si2 {} + + const vsll __builtin_altivec_vrldmi (vsll, vsll, vsll); + VRLDMI altivec_vrldmi {} + + const vsll __builtin_altivec_vrldnm (vsll, vsll); + VRLDNM altivec_vrldnm {} + + const vsi __builtin_altivec_vrlwmi (vsi, vsi, vsi); + VRLWMI altivec_vrlwmi {} + + const vsi __builtin_altivec_vrlwnm (vsi, vsi); + VRLWNM altivec_vrlwnm {} + + const vsll __builtin_altivec_vsignextsb2d (vsc); + VSIGNEXTSB2D vsignextend_qi_v2di {} + + const vsi __builtin_altivec_vsignextsb2w (vsc); + VSIGNEXTSB2W vsignextend_qi_v4si {} + + const vsll __builtin_altivec_visgnextsh2d (vss); + VSIGNEXTSH2D vsignextend_hi_v2di {} + + const vsi __builtin_altivec_vsignextsh2w (vss); + VSIGNEXTSH2W vsignextend_hi_v4si {} + + const vsll __builtin_altivec_vsignextsw2d (vsi); + VSIGNEXTSW2D vsignextend_si_v2di {} + + const vsc __builtin_altivec_vslv (vsc, vsc); + VSLV vslv {} + + const vsc __builtin_altivec_vsrv (vsc, vsc); + VSRV vsrv {} + + const signed int __builtin_scalar_byte_in_range (signed int, signed int); + CMPRB cmprb {} + + const signed int \ + __builtin_scalar_byte_in_either_range (signed int, signed int); + CMPRB2 cmprb2 {} + + const vsll __builtin_vsx_extract4b (vsc, const int[0,12]); + EXTRACT4B extract4b {} + + const vd __builtin_vsx_extract_exp_dp (vd); + VEEDP xvxexpdp {} + + const vf __builtin_vsx_extract_exp_sp (vf); + VEESP xvxexpsp {} + + const vd __builtin_vsx_extract_sig_dp (vd); + VESDP xvxsigdp {} + + const vf __builtin_vsx_extract_sig_sp (vf); + VESSP xvxsigsp {} + + const vsc __builtin_vsx_insert4b (vsi, vsc, const int[0,12]); + INSERT4B insert4b {} + + const vd __builtin_vsx_insert_exp_dp (vd, vd); + VIEDP xviexpdp {} + + const vf __builtin_vsx_insert_exp_sp (vf, vf); + VIESP xviexpsp {} + + const signed int __builtin_vsx_scalar_cmp_exp_dp_eq (double, double); + VSCEDPEQ xscmpexpdp_eq {} + + const signed int __builtin_vsx_scalar_cmp_exp_dp_gt (double, double); + VSCEDPGT xscmpexpdp_gt {} + + const signed int __builtin_vsx_scalar_cmp_exp_dp_lt (double, double); + VSCEDPLT xscmpexpdp_lt {} + + const signed int __builtin_vsx_scalar_cmp_exp_dp_unordered (double, double); + VSCEDPUO xscmpexpdp_unordered {} + + const signed int \ + __builtin_vsx_scalar_test_data_class_dp (double, const int<7>); + VSTDCDP xststdcdp {} + + const signed int \ + __builtin_vsx_scalar_test_data_class_sp (float, const int<7>); + VSTDCSP xststdcsp {} + + const signed int __builtin_vsx_scalar_test_neg_dp (double); + VSTDCNDP xststdcnegdp {} + + const signed int __builtin_vsx_scalar_test_neg_sp (float); + VSTDCNSP xststdcnegsp {} + + const vsll __builtin_vsx_test_data_class_dp (vd, const int<7>); + VTDCDP xvtstdcdp {} + + const vsi __builtin_vsx_test_data_class_sp (vf, const int<7>); + VTDCSP xvtstdcsp {} + + const vf __builtin_vsx_vextract_fp_from_shorth (vss); + VEXTRACT_FP_FROM_SHORTH vextract_fp_from_shorth {} + + const vf __builtin_vsx_vextract_fp_from_shortl (vss); + VEXTRACT_FP_FROM_SHORTL vextract_fp_from_shortl {} + + const vd __builtin_vsx_xxbrd_v2df (vd); + XXBRD_V2DF p9_xxbrd_v2df {} + + const vsll __builtin_vsx_xxbrd_v2di (vsll); + XXBRD_V2DI p9_xxbrd_v2di {} + + const vss __builtin_vsx_xxbrh_v8hi (vss); + XXBRH_V8HI p9_xxbrh_v8hi {} + + const vsc __builtin_vsx_xxbrq_v16qi (vsc); + XXBRQ_V16QI p9_xxbrq_v16qi {} + + const vsq __builtin_vsx_xxbrq_v1ti (vsq); + XXBRQ_V1TI p9_xxbrq_v1ti {} + + const vf __builtin_vsx_xxbrw_v4sf (vf); + XXBRW_V4SF p9_xxbrw_v4sf {} + + const vsi __builtin_vsx_xxbrw_v4si (vsi); + XXBRW_V4SI p9_xxbrw_v4si {} + + +; Miscellaneous P9 functions +[power9] + signed long long __builtin_darn (); + DARN darn {} + + signed int __builtin_darn_32 (); + DARN_32 darn_32 {} + + signed long long __builtin_darn_raw (); + DARN_RAW darn_raw {} + + const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64); + TSTSFI_EQ_DD dfptstsfi_eq_dd {} + + const signed int __builtin_dtstsfi_eq_td (const int<6>, _Decimal128); + TSTSFI_EQ_TD dfptstsfi_eq_td {} + + const signed int __builtin_dtstsfi_gt_dd (const int<6>, _Decimal64); + TSTSFI_GT_DD dfptstsfi_gt_dd {} + + const signed int __builtin_dtstsfi_gt_td (const int<6>, _Decimal128); + TSTSFI_GT_TD dfptstsfi_gt_td {} + + const signed int __builtin_dtstsfi_lt_dd (const int<6>, _Decimal64); + TSTSFI_LT_DD dfptstsfi_lt_dd {} + + const signed int __builtin_dtstsfi_lt_td (const int<6>, _Decimal128); + TSTSFI_LT_TD dfptstsfi_lt_td {} + + const signed int __builtin_dtstsfi_ov_dd (const int<6>, _Decimal64); + TSTSFI_OV_DD dfptstsfi_unordered_dd {} + + const signed int __builtin_dtstsfi_ov_td (const int<6>, _Decimal128); + TSTSFI_OV_TD dfptstsfi_unordered_td {} + + +[power9-64] + void __builtin_altivec_xst_len_r (vsc, void *, long); + XST_LEN_R xst_len_r {} + + void __builtin_altivec_stxvl (vsc, void *, long); + STXVL stxvl {} + + const signed int __builtin_scalar_byte_in_set (signed int, signed long long); + CMPEQB cmpeqb {} + + pure vsc __builtin_vsx_lxvl (const void *, signed long); + LXVL lxvl {} + + const signed long __builtin_vsx_scalar_extract_exp (double); + VSEEDP xsxexpdp {} + + const signed long __builtin_vsx_scalar_extract_sig (double); + VSESDP xsxsigdp {} + + const double __builtin_vsx_scalar_insert_exp (unsigned long long, \ + unsigned long long); + VSIEDP xsiexpdp {} + + const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long); + VSIEDPF xsiexpdpf {} + + pure vsc __builtin_vsx_xl_len_r (void *, signed long); + XL_LEN_R xl_len_r {} + + +; Builtins requiring hardware support for IEEE-128 floating-point. +[ieee128-hw] + fpmath _Float128 __builtin_addf128_round_to_odd (_Float128, _Float128); + ADDF128_ODD addkf3_odd {} + + fpmath _Float128 __builtin_divf128_round_to_odd (_Float128, _Float128); + DIVF128_ODD divkf3_odd {} + + fpmath _Float128 __builtin_fmaf128_round_to_odd (_Float128, _Float128, \ + _Float128); + FMAF128_ODD fmakf4_odd {} + + fpmath _Float128 __builtin_mulf128_round_to_odd (_Float128, _Float128); + MULF128_ODD mulkf3_odd {} + + const signed int __builtin_vsx_scalar_cmp_exp_qp_eq (_Float128, _Float128); + VSCEQPEQ xscmpexpqp_eq_kf {} + + const signed int __builtin_vsx_scalar_cmp_exp_qp_gt (_Float128, _Float128); + VSCEQPGT xscmpexpqp_gt_kf {} + + const signed int __builtin_vsx_scalar_cmp_exp_qp_lt (_Float128, _Float128); + VSCEQPLT xscmpexpqp_lt_kf {} + + const signed int \ + __builtin_vsx_scalar_cmp_exp_qp_unordered (_Float128, _Float128); + VSCEQPUO xscmpexpqp_unordered_kf {} + + fpmath _Float128 __builtin_sqrtf128_round_to_odd (_Float128); + SQRTF128_ODD sqrtkf2_odd {} + + fpmath _Float128 __builtin_subf128_round_to_odd (_Float128, _Float128); + SUBF128_ODD subkf3_odd {} + + fpmath double __builtin_truncf128_round_to_odd (_Float128); + TRUNCF128_ODD trunckfdf2_odd {} + + const signed long long __builtin_vsx_scalar_extract_expq (_Float128); + VSEEQP xsxexpqp_kf {} + + const signed __int128 __builtin_vsx_scalar_extract_sigq (_Float128); + VSESQP xsxsigqp_kf {} + + const _Float128 __builtin_vsx_scalar_insert_exp_q (unsigned __int128, \ + unsigned long long); + VSIEQP xsiexpqp_kf {} + + const _Float128 __builtin_vsx_scalar_insert_exp_qp (_Float128, \ + unsigned long long); + VSIEQPF xsiexpqpf_kf {} + + const signed int __builtin_vsx_scalar_test_data_class_qp (_Float128, \ + const int<7>); + VSTDCQP xststdcqp_kf {} + + const signed int __builtin_vsx_scalar_test_neg_qp (_Float128); + VSTDCNQP xststdcnegqp_kf {} + + + +; Decimal floating-point builtins. +[dfp] + const _Decimal64 __builtin_ddedpd (const int<2>, _Decimal64); + DDEDPD dfp_ddedpd_dd {} + + const _Decimal128 __builtin_ddedpdq (const int<2>, _Decimal128); + DDEDPDQ dfp_ddedpd_td {} + + const _Decimal64 __builtin_denbcd (const int<1>, _Decimal64); + DENBCD dfp_denbcd_dd {} + + const _Decimal128 __builtin_denbcdq (const int<1>, _Decimal128); + DENBCDQ dfp_denbcd_td {} + + const _Decimal128 __builtin_denb2dfp_v16qi (vsc); + DENB2DFP_V16QI dfp_denbcd_v16qi {} + + const _Decimal64 __builtin_diex (signed long long, _Decimal64); + DIEX dfp_diex_dd {} + + const _Decimal128 __builtin_diexq (signed long long, _Decimal128); + DIEXQ dfp_diex_td {} + + const _Decimal64 __builtin_dscli (_Decimal64, const int<6>); + DSCLI dfp_dscli_dd {} + + const _Decimal128 __builtin_dscliq (_Decimal128, const int<6>); + DSCLIQ dfp_dscli_td {} + + const _Decimal64 __builtin_dscri (_Decimal64, const int<6>); + DSCRI dfp_dscri_dd {} + + const _Decimal128 __builtin_dscriq (_Decimal128, const int<6>); + DSCRIQ dfp_dscri_td {} + + const signed long long __builtin_dxex (_Decimal64); + DXEX dfp_dxex_dd {} + + const signed long long __builtin_dxexq (_Decimal128); + DXEXQ dfp_dxex_td {} + + const _Decimal128 __builtin_pack_dec128 (unsigned long long, \ + unsigned long long); + PACK_TD packtd {} + + void __builtin_set_fpscr_drn (const int[0,7]); + SET_FPSCR_DRN rs6000_set_fpscr_drn {} + + const unsigned long long __builtin_unpack_dec128 (_Decimal128, const int<1>); + UNPACK_TD unpacktd {} + + +[crypto] + const vull __builtin_crypto_vcipher (vull, vull); + VCIPHER crypto_vcipher_v2di {} + + const vuc __builtin_crypto_vcipher_be (vuc, vuc); + VCIPHER_BE crypto_vcipher_v16qi {} + + const vull __builtin_crypto_vcipherlast (vull, vull); + VCIPHERLAST crypto_vcipherlast_v2di {} + + const vuc __builtin_crypto_vcipherlast_be (vuc, vuc); + VCIPHERLAST_BE crypto_vcipherlast_v16qi {} + + const vull __builtin_crypto_vncipher (vull, vull); + VNCIPHER crypto_vncipher_v2di {} + + const vuc __builtin_crypto_vncipher_be (vuc, vuc); + VNCIPHER_BE crypto_vncipher_v16qi {} + + const vull __builtin_crypto_vncipherlast (vull, vull); + VNCIPHERLAST crypto_vncipherlast_v2di {} + + const vuc __builtin_crypto_vncipherlast_be (vuc, vuc); + VNCIPHERLAST_BE crypto_vncipherlast_v16qi {} + + const vull __builtin_crypto_vsbox (vull); + VSBOX crypto_vsbox_v2di {} + + const vuc __builtin_crypto_vsbox_be (vuc); + VSBOX_BE crypto_vsbox_v16qi {} + + const vull __builtin_crypto_vshasigmad (vull, const int<1>, const int<4>); + VSHASIGMAD crypto_vshasigmad {} + + const vui __builtin_crypto_vshasigmaw (vui, const int<1>, const int<4>); + VSHASIGMAW crypto_vshasigmaw {} + + +[htm] + unsigned long __builtin_get_texasr (); + GET_TEXASR nothing {htm,htmspr} + + unsigned long __builtin_get_texasru (); + GET_TEXASRU nothing {htm,htmspr} + + unsigned long __builtin_get_tfhar (); + GET_TFHAR nothing {htm,htmspr} + + unsigned long __builtin_get_tfiar (); + GET_TFIAR nothing {htm,htmspr} + + void __builtin_set_texasr (unsigned long); + SET_TEXASR nothing {htm,htmspr} + + void __builtin_set_texasru (unsigned long); + SET_TEXASRU nothing {htm,htmspr} + + void __builtin_set_tfhar (unsigned long); + SET_TFHAR nothing {htm,htmspr} + + void __builtin_set_tfiar (unsigned long); + SET_TFIAR nothing {htm,htmspr} + + unsigned int __builtin_tabort (unsigned int); + TABORT tabort {htm,htmcr} + + unsigned int __builtin_tabortdc (unsigned long, unsigned long, \ + unsigned long); + TABORTDC tabortdc {htm,htmcr} + + unsigned int __builtin_tabortdci (unsigned long, unsigned long, \ + unsigned long); + TABORTDCI tabortdci {htm,htmcr} + + unsigned int __builtin_tabortwc (unsigned int, unsigned int, unsigned int); + TABORTWC tabortwc {htm,htmcr} + + unsigned int __builtin_tabortwci (unsigned int, unsigned int, unsigned int); + TABORTWCI tabortwci {htm,htmcr} + + unsigned int __builtin_tbegin (unsigned int); + TBEGIN tbegin {htm,htmcr} + + unsigned int __builtin_tcheck (); + TCHECK tcheck {htm,htmcr} + + unsigned int __builtin_tend (unsigned int); + TEND tend {htm,htmcr} + + unsigned int __builtin_tendall (); + TENDALL tend {htm,htmcr} + + unsigned int __builtin_trechkpt (); + TRECHKPT trechkpt {htm,htmcr} + + unsigned int __builtin_treclaim (unsigned int); + TRECLAIM treclaim {htm,htmcr} + + unsigned int __builtin_tresume (); + TRESUME tsr {htm,htmcr} + + unsigned int __builtin_tsr (unsigned int); + TSR tsr {htm,htmcr} + + unsigned int __builtin_tsuspend (); + TSUSPEND tsr {htm,htmcr} + + unsigned int __builtin_ttest (); + TTEST ttest {htm,htmcr} + + +[power10] + const vbq __builtin_altivec_cmpge_1ti (vsq, vsq); + CMPGE_1TI vector_nltv1ti {} + + const vbq __builtin_altivec_cmpge_u1ti (vuq, vuq); + CMPGE_U1TI vector_nltuv1ti {} + + const vbq __builtin_altivec_cmple_1ti (vsq, vsq); + CMPLE_1TI vector_ngtv1ti {} + + const vbq __builtin_altivec_cmple_u1ti (vuq, vuq); + CMPLE_U1TI vector_ngtuv1ti {} + + const unsigned long long __builtin_altivec_cntmbb (vuc, const int<1>); + VCNTMBB vec_cntmb_v16qi {} + + const unsigned long long __builtin_altivec_cntmbd (vull, const int<1>); + VCNTMBD vec_cntmb_v2di {} + + const unsigned long long __builtin_altivec_cntmbh (vus, const int<1>); + VCNTMBH vec_cntmb_v8hi {} + + const unsigned long long __builtin_altivec_cntmbw (vui, const int<1>); + VCNTMBW vec_cntmb_v4si {} + + const vsq __builtin_altivec_div_v1ti (vsq, vsq); + DIV_V1TI vsx_div_v1ti {} + + const vsq __builtin_altivec_dives (vsq, vsq); + DIVES_V1TI vsx_dives_v1ti {} + + const vuq __builtin_altivec_diveu (vuq, vuq); + DIVEU_V1TI vsx_diveu_v1ti {} + + const vsq __builtin_altivec_mods (vsq, vsq); + MODS_V1TI vsx_mods_v1ti {} + + const vuq __builtin_altivec_modu (vuq, vuq); + MODU_V1TI vsx_modu_v1ti {} + + const vuc __builtin_altivec_mtvsrbm (unsigned long long); + MTVSRBM vec_mtvsr_v16qi {} + + const vull __builtin_altivec_mtvsrdm (unsigned long long); + MTVSRDM vec_mtvsr_v2di {} + + const vus __builtin_altivec_mtvsrhm (unsigned long long); + MTVSRHM vec_mtvsr_v8hi {} + + const vuq __builtin_altivec_mtvsrqm (unsigned long long); + MTVSRQM vec_mtvsr_v1ti {} + + const vui __builtin_altivec_mtvsrwm (unsigned long long); + MTVSRWM vec_mtvsr_v4si {} + + pure signed __int128 __builtin_altivec_se_lxvrbx (signed long, \ + const signed char *); + SE_LXVRBX vsx_lxvrbx {lxvrse} + + pure signed __int128 __builtin_altivec_se_lxvrhx (signed long, \ + const signed short *); + SE_LXVRHX vsx_lxvrhx {lxvrse} + + pure signed __int128 __builtin_altivec_se_lxvrwx (signed long, \ + const signed int *); + SE_LXVRWX vsx_lxvrwx {lxvrse} + + pure signed __int128 __builtin_altivec_se_lxvrdx (signed long, \ + const signed long long *); + SE_LXVRDX vsx_lxvrdx {lxvrse} + + void __builtin_altivec_tr_stxvrbx (vsq, signed long, signed char *); + TR_STXVRBX vsx_stxvrbx {stvec} + + void __builtin_altivec_tr_stxvrhx (vsq, signed long, signed int *); + TR_STXVRHX vsx_stxvrhx {stvec} + + void __builtin_altivec_tr_stxvrwx (vsq, signed long, signed short *); + TR_STXVRWX vsx_stxvrwx {stvec} + + void __builtin_altivec_tr_stxvrdx (vsq, signed long, signed long long *); + TR_STXVRDX vsx_stxvrdx {stvec} + + const vuq __builtin_altivec_udiv_v1ti (vuq, vuq); + UDIV_V1TI vsx_udiv_v1ti {} + + const vull __builtin_altivec_vcfuged (vull, vull); + VCFUGED vcfuged {} + + const vsc __builtin_altivec_vclrlb (vsc, signed int); + VCLRLB vclrlb {} + + const vsc __builtin_altivec_vclrrb (vsc, signed int); + VCLRRB vclrrb {} + + const signed int __builtin_altivec_vcmpaet_p (vsq, vsq); + VCMPAET_P vector_ae_v1ti_p {} + + const vbq __builtin_altivec_vcmpequt (vsq, vsq); + VCMPEQUT vector_eqv1ti {} + + const signed int __builtin_altivec_vcmpequt_p (signed int, vsq, vsq); + VCMPEQUT_P vector_eq_v1ti_p {pred} + + const vbq __builtin_altivec_vcmpgtst (vsq, vsq); + VCMPGTST vector_gtv1ti {} + + const signed int __builtin_altivec_vcmpgtst_p (signed int, vsq, vsq); + VCMPGTST_P vector_gt_v1ti_p {pred} + + const vbq __builtin_altivec_vcmpgtut (vuq, vuq); + VCMPGTUT vector_gtuv1ti {} + + const signed int __builtin_altivec_vcmpgtut_p (signed int, vuq, vuq); + VCMPGTUT_P vector_gtu_v1ti_p {pred} + + const vbq __builtin_altivec_vcmpnet (vsq, vsq); + VCMPNET vcmpnet {} + + const signed int __builtin_altivec_vcmpnet_p (vsq, vsq); + VCMPNET_P vector_ne_v1ti_p {} + + const vull __builtin_altivec_vclzdm (vull, vull); + VCLZDM vclzdm {} + + const vull __builtin_altivec_vctzdm (vull, vull); + VCTZDM vctzdm {} + + const vsll __builtin_altivec_vdivesd (vsll, vsll); + VDIVESD dives_v2di {} + + const vsi __builtin_altivec_vdivesw (vsi, vsi); + VDIVESW dives_v4si {} + + const vull __builtin_altivec_vdiveud (vull, vull); + VDIVEUD diveu_v2di {} + + const vui __builtin_altivec_vdiveuw (vui, vui); + VDIVEUW diveu_v4si {} + + const vsll __builtin_altivec_vdivsd (vsll, vsll); + VDIVSD divv2di3 {} + + const vsi __builtin_altivec_vdivsw (vsi, vsi); + VDIVSW divv4si3 {} + + const vull __builtin_altivec_vdivud (vull, vull); + VDIVUD udivv2di3 {} + + const vui __builtin_altivec_vdivuw (vui, vui); + VDIVUW udivv4si3 {} + + const vuc __builtin_altivec_vexpandmb (vuc); + VEXPANDMB vec_expand_v16qi {} + + const vull __builtin_altivec_vexpandmd (vull); + VEXPANDMD vec_expand_v2di {} + + const vus __builtin_altivec_vexpandmh (vus); + VEXPANDMH vec_expand_v8hi {} + + const vuq __builtin_altivec_vexpandmq (vuq); + VEXPANDMQ vec_expand_v1ti {} + + const vui __builtin_altivec_vexpandmw (vui); + VEXPANDMW vec_expand_v4si {} + + const vull __builtin_altivec_vextddvhx (vull, vull, unsigned int); + VEXTRACTDR vextractrv2di {} + + const vull __builtin_altivec_vextddvlx (vull, vull, unsigned int); + VEXTRACTDL vextractlv2di {} + + const vull __builtin_altivec_vextdubvhx (vuc, vuc, unsigned int); + VEXTRACTBR vextractrv16qi {} + + const vull __builtin_altivec_vextdubvlx (vuc, vuc, unsigned int); + VEXTRACTBL vextractlv16qi {} + + const vull __builtin_altivec_vextduhvhx (vus, vus, unsigned int); + VEXTRACTHR vextractrv8hi {} + + const vull __builtin_altivec_vextduhvlx (vus, vus, unsigned int); + VEXTRACTHL vextractlv8hi {} + + const vull __builtin_altivec_vextduwvhx (vui, vui, unsigned int); + VEXTRACTWR vextractrv4si {} + + const vull __builtin_altivec_vextduwvlx (vui, vui, unsigned int); + VEXTRACTWL vextractlv4si {} + + const signed int __builtin_altivec_vextractmb (vsc); + VEXTRACTMB vec_extract_v16qi {} + + const signed int __builtin_altivec_vextractmd (vsll); + VEXTRACTMD vec_extract_v2di {} + + const signed int __builtin_altivec_vextractmh (vss); + VEXTRACTMH vec_extract_v8hi {} + + const signed int __builtin_altivec_vextractmq (vsq); + VEXTRACTMQ vec_extract_v1ti {} + + const signed int __builtin_altivec_vextractmw (vsi); + VEXTRACTMW vec_extract_v4si {} + + const unsigned long long __builtin_altivec_vgnb (vull, const int <2,7>); + VGNB vgnb {} + + const vuc __builtin_altivec_vinsgubvlx (unsigned int, vuc, unsigned int); + VINSERTGPRBL vinsertgl_v16qi {} + + const vsc __builtin_altivec_vinsgubvrx (signed int, vsc, signed int); + VINSERTGPRBR vinsertgr_v16qi {} + + const vull __builtin_altivec_vinsgudvlx (unsigned int, vull, unsigned int); + VINSERTGPRDL vinsertgl_v2di {} + + const vsll __builtin_altivec_vinsgudvrx (signed int, vsll, signed int); + VINSERTGPRDR vinsertgr_v2di {} + + const vus __builtin_altivec_vinsguhvlx (unsigned int, vus, unsigned int); + VINSERTGPRHL vinsertgl_v8hi {} + + const vss __builtin_altivec_vinsguhvrx (signed int, vss, signed int); + VINSERTGPRHR vinsertgr_v8hi {} + + const vui __builtin_altivec_vinsguwvlx (unsigned int, vui, unsigned int); + VINSERTGPRWL vinsertgl_v4si {} + + const vsi __builtin_altivec_vinsguwvrx (signed int, vsi, signed int); + VINSERTGPRWR vinsertgr_v4si {} + + const vuc __builtin_altivec_vinsvubvlx (vuc, vuc, unsigned int); + VINSERTVPRBL vinsertvl_v16qi {} + + const vsc __builtin_altivec_vinsvubvrx (vsc, vsc, signed int); + VINSERTVPRBR vinsertvr_v16qi {} + + const vus __builtin_altivec_vinsvuhvlx (vus, vus, unsigned int); + VINSERTVPRHL vinsertvl_v8hi {} + + const vss __builtin_altivec_vinsvuhvrx (vss, vss, signed int); + VINSERTVPRHR vinsertvr_v8hi {} + + const vui __builtin_altivec_vinsvuwvlx (vui, vui, unsigned int); + VINSERTVPRWL vinsertvl_v4si {} + + const vsi __builtin_altivec_vinsvuwvrx (vsi, vsi, signed int); + VINSERTVPRWR vinsertvr_v4si {} + + const vsll __builtin_altivec_vmodsd (vsll, vsll); + VMODSD modv2di3 {} + + const vsi __builtin_altivec_vmodsw (vsi, vsi); + VMODSW modv4si3 {} + + const vull __builtin_altivec_vmodud (vull, vull); + VMODUD umodv2di3 {} + + const vui __builtin_altivec_vmoduw (vui, vui); + VMODUW umodv4si3 {} + + const vsq __builtin_altivec_vmulesd (vsll, vsll); + VMULESD vec_widen_smult_even_v2di {} + + const vuq __builtin_altivec_vmuleud (vull, vull); + VMULEUD vec_widen_umult_even_v2di {} + + const vsll __builtin_altivec_vmulhsd (vsll, vsll); + VMULHSD smulv2di3_highpart {} + + const vsi __builtin_altivec_vmulhsw (vsi, vsi); + VMULHSW smulv4si3_highpart {} + + const vull __builtin_altivec_vmulhud (vull, vull); + VMULHUD umulv2di3_highpart {} + + const vui __builtin_altivec_vmulhuw (vui, vui); + VMULHUW umulv4si3_highpart {} + + const vsll __builtin_altivec_vmulld (vsll, vsll); + VMULLD mulv2di3 {} + + const vsq __builtin_altivec_vmulosd (vsll, vsll); + VMULOSD vec_widen_smult_odd_v2di {} + + const vuq __builtin_altivec_vmuloud (vull, vull); + VMULOUD vec_widen_umult_odd_v2di {} + + const vsq __builtin_altivec_vnor_v1ti (vsq, vsq); + VNOR_V1TI norv1ti3 {} + + const vuq __builtin_altivec_vnor_v1ti_uns (vuq, vuq); + VNOR_V1TI_UNS norv1ti3 {} + + const vull __builtin_altivec_vpdepd (vull, vull); + VPDEPD vpdepd {} + + const vull __builtin_altivec_vpextd (vull, vull); + VPEXTD vpextd {} + + const vull __builtin_altivec_vreplace_un_uv2di (vull, unsigned long long, \ + const int<4>); + VREPLACE_UN_UV2DI vreplace_un_v2di {} + + const vui __builtin_altivec_vreplace_un_uv4si (vui, unsigned int, \ + const int<4>); + VREPLACE_UN_UV4SI vreplace_un_v4si {} + + const vd __builtin_altivec_vreplace_un_v2df (vd, double, const int<4>); + VREPLACE_UN_V2DF vreplace_un_v2df {} + + const vsll __builtin_altivec_vreplace_un_v2di (vsll, signed long long, \ + const int<4>); + VREPLACE_UN_V2DI vreplace_un_v2di {} + + const vf __builtin_altivec_vreplace_un_v4sf (vf, float, const int<4>); + VREPLACE_UN_V4SF vreplace_un_v4sf {} + + const vsi __builtin_altivec_vreplace_un_v4si (vsi, signed int, const int<4>); + VREPLACE_UN_V4SI vreplace_un_v4si {} + + const vull __builtin_altivec_vreplace_uv2di (vull, unsigned long long, \ + const int<1>); + VREPLACE_ELT_UV2DI vreplace_elt_v2di {} + + const vui __builtin_altivec_vreplace_uv4si (vui, unsigned int, const int<2>); + VREPLACE_ELT_UV4SI vreplace_elt_v4si {} + + const vd __builtin_altivec_vreplace_v2df (vd, double, const int<1>); + VREPLACE_ELT_V2DF vreplace_elt_v2df {} + + const vsll __builtin_altivec_vreplace_v2di (vsll, signed long long, \ + const int<1>); + VREPLACE_ELT_V2DI vreplace_elt_v2di {} + + const vf __builtin_altivec_vreplace_v4sf (vf, float, const int<2>); + VREPLACE_ELT_V4SF vreplace_elt_v4sf {} + + const vsi __builtin_altivec_vreplace_v4si (vsi, signed int, const int<2>); + VREPLACE_ELT_V4SI vreplace_elt_v4si {} + + const vsq __builtin_altivec_vrlq (vsq, vuq); + VRLQ vrotlv1ti3 {} + + const vsq __builtin_altivec_vrlqmi (vsq, vsq, vuq); + VRLQMI altivec_vrlqmi {} + + const vsq __builtin_altivec_vrlqnm (vsq, vuq); + VRLQNM altivec_vrlqnm {} + + const vsq __builtin_altivec_vsignext (vsll); + VSIGNEXTSD2Q vsignextend_v2di_v1ti {} + + const vsc __builtin_altivec_vsldb_v16qi (vsc, vsc, const int<3>); + VSLDB_V16QI vsldb_v16qi {} + + const vsll __builtin_altivec_vsldb_v2di (vsll, vsll, const int<3>); + VSLDB_V2DI vsldb_v2di {} + + const vsi __builtin_altivec_vsldb_v4si (vsi, vsi, const int<3>); + VSLDB_V4SI vsldb_v4si {} + + const vss __builtin_altivec_vsldb_v8hi (vss, vss, const int<3>); + VSLDB_V8HI vsldb_v8hi {} + + const vsq __builtin_altivec_vslq (vsq, vuq); + VSLQ vashlv1ti3 {} + + const vsq __builtin_altivec_vsraq (vsq, vuq); + VSRAQ vashrv1ti3 {} + + const vsc __builtin_altivec_vsrdb_v16qi (vsc, vsc, const int<3>); + VSRDB_V16QI vsrdb_v16qi {} + + const vsll __builtin_altivec_vsrdb_v2di (vsll, vsll, const int<3>); + VSRDB_V2DI vsrdb_v2di {} + + const vsi __builtin_altivec_vsrdb_v4si (vsi, vsi, const int<3>); + VSRDB_V4SI vsrdb_v4si {} + + const vss __builtin_altivec_vsrdb_v8hi (vss, vss, const int<3>); + VSRDB_V8HI vsrdb_v8hi {} + + const vsq __builtin_altivec_vsrq (vsq, vuq); + VSRQ vlshrv1ti3 {} + + const vsc __builtin_altivec_vstribl (vsc); + VSTRIBL vstril_v16qi {} + + const signed int __builtin_altivec_vstribl_p (vsc); + VSTRIBL_P vstril_p_v16qi {} + + const vsc __builtin_altivec_vstribr (vsc); + VSTRIBR vstrir_v16qi {} + + const signed int __builtin_altivec_vstribr_p (vsc); + VSTRIBR_P vstrir_p_v16qi {} + + const vss __builtin_altivec_vstrihl (vss); + VSTRIHL vstril_v8hi {} + + const signed int __builtin_altivec_vstrihl_p (vss); + VSTRIHL_P vstril_p_v8hi {} + + const vss __builtin_altivec_vstrihr (vss); + VSTRIHR vstrir_v8hi {} + + const signed int __builtin_altivec_vstrihr_p (vss); + VSTRIHR_P vstrir_p_v8hi {} + + const signed int __builtin_vsx_xvtlsbb_all_ones (vsc); + XVTLSBB_ONES xvtlsbbo {} + + const signed int __builtin_vsx_xvtlsbb_all_zeros (vsc); + XVTLSBB_ZEROS xvtlsbbz {} + + const vf __builtin_vsx_vxxsplti32dx_v4sf (vf, const int<1>, float); + VXXSPLTI32DX_V4SF xxsplti32dx_v4sf {} + + const vsi __builtin_vsx_vxxsplti32dx_v4si (vsi, const int<1>, signed int); + VXXSPLTI32DX_V4SI xxsplti32dx_v4si {} + + const vd __builtin_vsx_vxxspltidp (float); + VXXSPLTIDP xxspltidp_v2df {} + + const vf __builtin_vsx_vxxspltiw_v4sf (float); + VXXSPLTIW_V4SF xxspltiw_v4sf {} + + const vsi __builtin_vsx_vxxspltiw_v4si (signed int); + VXXSPLTIW_V4SI xxspltiw_v4si {} + + const vuc __builtin_vsx_xvcvbf16spn (vuc); + XVCVBF16SPN vsx_xvcvbf16spn {} + + const vuc __builtin_vsx_xvcvspbf16 (vuc); + XVCVSPBF16 vsx_xvcvspbf16 {} + + const vuc __builtin_vsx_xxblend_v16qi (vuc, vuc, vuc); + VXXBLEND_V16QI xxblend_v16qi {} + + const vd __builtin_vsx_xxblend_v2df (vd, vd, vd); + VXXBLEND_V2DF xxblend_v2df {} + + const vull __builtin_vsx_xxblend_v2di (vull, vull, vull); + VXXBLEND_V2DI xxblend_v2di {} + + const vf __builtin_vsx_xxblend_v4sf (vf, vf, vf); + VXXBLEND_V4SF xxblend_v4sf {} + + const vui __builtin_vsx_xxblend_v4si (vui, vui, vui); + VXXBLEND_V4SI xxblend_v4si {} + + const vus __builtin_vsx_xxblend_v8hi (vus, vus, vus); + VXXBLEND_V8HI xxblend_v8hi {} + + const vull __builtin_vsx_xxeval (vull, vull, vull, const int <8>); + XXEVAL xxeval {} + + const vuc __builtin_vsx_xxgenpcvm_v16qi (vuc, const int <2>); + XXGENPCVM_V16QI xxgenpcvm_v16qi {} + + const vull __builtin_vsx_xxgenpcvm_v2di (vull, const int <2>); + XXGENPCVM_V2DI xxgenpcvm_v2di {} + + const vui __builtin_vsx_xxgenpcvm_v4si (vui, const int <2>); + XXGENPCVM_V4SI xxgenpcvm_v4si {} + + const vus __builtin_vsx_xxgenpcvm_v8hi (vus, const int <2>); + XXGENPCVM_V8HI xxgenpcvm_v8hi {} + + const vuc __builtin_vsx_xxpermx_uv16qi (vuc, vuc, vuc, const int<3>); + XXPERMX_UV16QI xxpermx {} + + const vull __builtin_vsx_xxpermx_uv2di (vull, vull, vuc, const int<3>); + XXPERMX_UV2DI xxpermx {} + + const vui __builtin_vsx_xxpermx_uv4si (vui, vui, vuc, const int<3>); + XXPERMX_UV4SI xxpermx {} + + const vus __builtin_vsx_xxpermx_uv8hi (vus, vus, vuc, const int<3>); + XXPERMX_UV8HI xxpermx {} + + const vsc __builtin_vsx_xxpermx_v16qi (vsc, vsc, vuc, const int<3>); + XXPERMX_V16QI xxpermx {} + + const vd __builtin_vsx_xxpermx_v2df (vd, vd, vuc, const int<3>); + XXPERMX_V2DF xxpermx {} + + const vsll __builtin_vsx_xxpermx_v2di (vsll, vsll, vuc, const int<3>); + XXPERMX_V2DI xxpermx {} + + const vf __builtin_vsx_xxpermx_v4sf (vf, vf, vuc, const int<3>); + XXPERMX_V4SF xxpermx {} + + const vsi __builtin_vsx_xxpermx_v4si (vsi, vsi, vuc, const int<3>); + XXPERMX_V4SI xxpermx {} + + const vss __builtin_vsx_xxpermx_v8hi (vss, vss, vuc, const int<3>); + XXPERMX_V8HI xxpermx {} + + pure unsigned __int128 __builtin_altivec_ze_lxvrbx (signed long, \ + const unsigned char *); + ZE_LXVRBX vsx_lxvrbx {lxvrze} + + pure unsigned __int128 __builtin_altivec_ze_lxvrhx (signed long, \ + const unsigned short *); + ZE_LXVRHX vsx_lxvrhx {lxvrze} + + pure unsigned __int128 __builtin_altivec_ze_lxvrwx (signed long, \ + const unsigned int *); + ZE_LXVRWX vsx_lxvrwx {lxvrze} + + pure unsigned __int128 \ + __builtin_altivec_ze_lxvrdx (signed long, const unsigned long long *); + ZE_LXVRDX vsx_lxvrdx {lxvrze} + + +[power10-64] + const unsigned long long __builtin_cfuged (unsigned long long, \ + unsigned long long); + CFUGED cfuged {} + + const unsigned long long __builtin_cntlzdm (unsigned long long, \ + unsigned long long); + CNTLZDM cntlzdm {} + + const unsigned long long __builtin_cnttzdm (unsigned long long, \ + unsigned long long); + CNTTZDM cnttzdm {} + + const unsigned long long __builtin_pdepd (unsigned long long, \ + unsigned long long); + PDEPD pdepd {} + + const unsigned long long __builtin_pextd (unsigned long long, \ + unsigned long long); + PEXTD pextd {} + + +[mma] + void __builtin_mma_assemble_acc (v512 *, vuc, vuc, vuc, vuc); + ASSEMBLE_ACC nothing {mma,mmaint} + + v512 __builtin_mma_assemble_acc_internal (vuc, vuc, vuc, vuc); + ASSEMBLE_ACC_INTERNAL mma_assemble_acc {mma} + + void __builtin_mma_assemble_pair (v256 *, vuc, vuc); + ASSEMBLE_PAIR nothing {mma,mmaint} + + v256 __builtin_mma_assemble_pair_internal (vuc, vuc); + ASSEMBLE_PAIR_INTERNAL vsx_assemble_pair {mma} + + void __builtin_mma_build_acc (v512 *, vuc, vuc, vuc, vuc); + BUILD_ACC nothing {mma,mmaint} + + v512 __builtin_mma_build_acc_internal (vuc, vuc, vuc, vuc); + BUILD_ACC_INTERNAL mma_assemble_acc {mma} + + void __builtin_mma_disassemble_acc (void *, v512 *); + DISASSEMBLE_ACC nothing {mma,quad,mmaint} + + vuc __builtin_mma_disassemble_acc_internal (v512, const int<2>); + DISASSEMBLE_ACC_INTERNAL mma_disassemble_acc {mma} + + void __builtin_mma_disassemble_pair (void *, v256 *); + DISASSEMBLE_PAIR nothing {mma,pair,mmaint} + + vuc __builtin_mma_disassemble_pair_internal (v256, const int<2>); + DISASSEMBLE_PAIR_INTERNAL vsx_disassemble_pair {mma} + + void __builtin_mma_pmxvbf16ger2 (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVBF16GER2 nothing {mma,mmaint} + + v512 __builtin_mma_pmxvbf16ger2_internal (vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVBF16GER2_INTERNAL mma_pmxvbf16ger2 {mma} + + void __builtin_mma_pmxvbf16ger2nn (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVBF16GER2NN nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvbf16ger2nn_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVBF16GER2NN_INTERNAL mma_pmxvbf16ger2nn {mma,quad} + + void __builtin_mma_pmxvbf16ger2np (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVBF16GER2NP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvbf16ger2np_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVBF16GER2NP_INTERNAL mma_pmxvbf16ger2np {mma,quad} + + void __builtin_mma_pmxvbf16ger2pn (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVBF16GER2PN nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvbf16ger2pn_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVBF16GER2PN_INTERNAL mma_pmxvbf16ger2pn {mma,quad} + + void __builtin_mma_pmxvbf16ger2pp (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVBF16GER2PP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvbf16ger2pp_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVBF16GER2PP_INTERNAL mma_pmxvbf16ger2pp {mma,quad} + + void __builtin_mma_pmxvf16ger2 (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVF16GER2 nothing {mma,mmaint} + + v512 __builtin_mma_pmxvf16ger2_internal (vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVF16GER2_INTERNAL mma_pmxvf16ger2 {mma} + + void __builtin_mma_pmxvf16ger2nn (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVF16GER2NN nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvf16ger2nn_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVF16GER2NN_INTERNAL mma_pmxvf16ger2nn {mma,quad} + + void __builtin_mma_pmxvf16ger2np (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVF16GER2NP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvf16ger2np_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVF16GER2NP_INTERNAL mma_pmxvf16ger2np {mma,quad} + + void __builtin_mma_pmxvf16ger2pn (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVF16GER2PN nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvf16ger2pn_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVF16GER2PN_INTERNAL mma_pmxvf16ger2pn {mma,quad} + + void __builtin_mma_pmxvf16ger2pp (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVF16GER2PP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvf16ger2pp_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVF16GER2PP_INTERNAL mma_pmxvf16ger2pp {mma,quad} + + void __builtin_mma_pmxvf32ger (v512 *, vuc, vuc, const int<4>, const int<4>); + PMXVF32GER nothing {mma,mmaint} + + v512 __builtin_mma_pmxvf32ger_internal (vuc, vuc, const int<4>, \ + const int<4>); + PMXVF32GER_INTERNAL mma_pmxvf32ger {mma} + + void __builtin_mma_pmxvf32gernn (v512 *, vuc, vuc, const int<4>, \ + const int<4>); + PMXVF32GERNN nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvf32gernn_internal (v512, vuc, vuc, const int<4>, \ + const int<4>); + PMXVF32GERNN_INTERNAL mma_pmxvf32gernn {mma,quad} + + void __builtin_mma_pmxvf32gernp (v512 *, vuc, vuc, const int<4>, \ + const int<4>); + PMXVF32GERNP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvf32gernp_internal (v512, vuc, vuc, const int<4>, \ + const int<4>); + PMXVF32GERNP_INTERNAL mma_pmxvf32gernp {mma,quad} + + void __builtin_mma_pmxvf32gerpn (v512 *, vuc, vuc, const int<4>, \ + const int<4>); + PMXVF32GERPN nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvf32gerpn_internal (v512, vuc, vuc, const int<4>, \ + const int<4>); + PMXVF32GERPN_INTERNAL mma_pmxvf32gerpn {mma,quad} + + void __builtin_mma_pmxvf32gerpp (v512 *, vuc, vuc, const int<4>, \ + const int<4>); + PMXVF32GERPP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvf32gerpp_internal (v512, vuc, vuc, const int<4>, \ + const int<4>); + PMXVF32GERPP_INTERNAL mma_pmxvf32gerpp {mma,quad} + + void __builtin_mma_pmxvf64ger (v512 *, v256, vuc, const int<4>, \ + const int<2>); + PMXVF64GER nothing {mma,pair,mmaint} + + v512 __builtin_mma_pmxvf64ger_internal (v256, vuc, const int<4>, \ + const int<2>); + PMXVF64GER_INTERNAL mma_pmxvf64ger {mma,pair} + + void __builtin_mma_pmxvf64gernn (v512 *, v256, vuc, const int<4>, \ + const int<2>); + PMXVF64GERNN nothing {mma,pair,quad,mmaint} + + v512 __builtin_mma_pmxvf64gernn_internal (v512, v256, vuc, const int<4>, \ + const int<2>); + PMXVF64GERNN_INTERNAL mma_pmxvf64gernn {mma,pair,quad} + + void __builtin_mma_pmxvf64gernp (v512 *, v256, vuc, const int<4>, \ + const int<2>); + PMXVF64GERNP nothing {mma,pair,quad,mmaint} + + v512 __builtin_mma_pmxvf64gernp_internal (v512, v256, vuc, const int<4>, \ + const int<2>); + PMXVF64GERNP_INTERNAL mma_pmxvf64gernp {mma,pair,quad} + + void __builtin_mma_pmxvf64gerpn (v512 *, v256, vuc, const int<4>, \ + const int<2>); + PMXVF64GERPN nothing {mma,pair,quad,mmaint} + + v512 __builtin_mma_pmxvf64gerpn_internal (v512, v256, vuc, const int<4>, \ + const int<2>); + PMXVF64GERPN_INTERNAL mma_pmxvf64gerpn {mma,pair,quad} + + void __builtin_mma_pmxvf64gerpp (v512 *, v256, vuc, const int<4>, \ + const int<2>); + PMXVF64GERPP nothing {mma,pair,quad,mmaint} + + v512 __builtin_mma_pmxvf64gerpp_internal (v512, v256, vuc, const int<4>, \ + const int<2>); + PMXVF64GERPP_INTERNAL mma_pmxvf64gerpp {mma,pair,quad} + + void __builtin_mma_pmxvi16ger2 (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVI16GER2 nothing {mma,mmaint} + + v512 __builtin_mma_pmxvi16ger2_internal (vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVI16GER2_INTERNAL mma_pmxvi16ger2 {mma} + + void __builtin_mma_pmxvi16ger2pp (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVI16GER2PP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvi16ger2pp_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVI16GER2PP_INTERNAL mma_pmxvi16ger2pp {mma,quad} + + void __builtin_mma_pmxvi16ger2s (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVI16GER2S nothing {mma,mmaint} + + v512 __builtin_mma_pmxvi16ger2s_internal (vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVI16GER2S_INTERNAL mma_pmxvi16ger2s {mma} + + void __builtin_mma_pmxvi16ger2spp (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVI16GER2SPP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvi16ger2spp_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<2>); + PMXVI16GER2SPP_INTERNAL mma_pmxvi16ger2spp {mma,quad} + + void __builtin_mma_pmxvi4ger8 (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<8>); + PMXVI4GER8 nothing {mma,mmaint} + + v512 __builtin_mma_pmxvi4ger8_internal (vuc, vuc, const int<4>, \ + const int<4>, const int<8>); + PMXVI4GER8_INTERNAL mma_pmxvi4ger8 {mma} + + void __builtin_mma_pmxvi4ger8pp (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<4>); + PMXVI4GER8PP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvi4ger8pp_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<4>); + PMXVI4GER8PP_INTERNAL mma_pmxvi4ger8pp {mma,quad} + + void __builtin_mma_pmxvi8ger4 (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<4>); + PMXVI8GER4 nothing {mma,mmaint} + + v512 __builtin_mma_pmxvi8ger4_internal (vuc, vuc, const int<4>, \ + const int<4>, const int<4>); + PMXVI8GER4_INTERNAL mma_pmxvi8ger4 {mma} + + void __builtin_mma_pmxvi8ger4pp (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<4>); + PMXVI8GER4PP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvi8ger4pp_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<4>); + PMXVI8GER4PP_INTERNAL mma_pmxvi8ger4pp {mma,quad} + + void __builtin_mma_pmxvi8ger4spp (v512 *, vuc, vuc, const int<4>, \ + const int<4>, const int<4>); + PMXVI8GER4SPP nothing {mma,quad,mmaint} + + v512 __builtin_mma_pmxvi8ger4spp_internal (v512, vuc, vuc, const int<4>, \ + const int<4>, const int<4>); + PMXVI8GER4SPP_INTERNAL mma_pmxvi8ger4spp {mma,quad} + + void __builtin_mma_xvbf16ger2 (v512 *, vuc, vuc); + XVBF16GER2 nothing {mma,mmaint} + + v512 __builtin_mma_xvbf16ger2_internal (vuc, vuc); + XVBF16GER2_INTERNAL mma_xvbf16ger2 {mma} + + void __builtin_mma_xvbf16ger2nn (v512 *, vuc, vuc); + XVBF16GER2NN nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvbf16ger2nn_internal (v512, vuc, vuc); + XVBF16GER2NN_INTERNAL mma_xvbf16ger2nn {mma,quad} + + void __builtin_mma_xvbf16ger2np (v512 *, vuc, vuc); + XVBF16GER2NP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvbf16ger2np_internal (v512, vuc, vuc); + XVBF16GER2NP_INTERNAL mma_xvbf16ger2np {mma,quad} + + void __builtin_mma_xvbf16ger2pn (v512 *, vuc, vuc); + XVBF16GER2PN nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvbf16ger2pn_internal (v512, vuc, vuc); + XVBF16GER2PN_INTERNAL mma_xvbf16ger2pn {mma,quad} + + void __builtin_mma_xvbf16ger2pp (v512 *, vuc, vuc); + XVBF16GER2PP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvbf16ger2pp_internal (v512, vuc, vuc); + XVBF16GER2PP_INTERNAL mma_xvbf16ger2pp {mma,quad} + + void __builtin_mma_xvf16ger2 (v512 *, vuc, vuc); + XVF16GER2 nothing {mma,mmaint} + + v512 __builtin_mma_xvf16ger2_internal (vuc, vuc); + XVF16GER2_INTERNAL mma_xvf16ger2 {mma} + + void __builtin_mma_xvf16ger2nn (v512 *, vuc, vuc); + XVF16GER2NN nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvf16ger2nn_internal (v512, vuc, vuc); + XVF16GER2NN_INTERNAL mma_xvf16ger2nn {mma,quad} + + void __builtin_mma_xvf16ger2np (v512 *, vuc, vuc); + XVF16GER2NP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvf16ger2np_internal (v512, vuc, vuc); + XVF16GER2NP_INTERNAL mma_xvf16ger2np {mma,quad} + + void __builtin_mma_xvf16ger2pn (v512 *, vuc, vuc); + XVF16GER2PN nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvf16ger2pn_internal (v512, vuc, vuc); + XVF16GER2PN_INTERNAL mma_xvf16ger2pn {mma,quad} + + void __builtin_mma_xvf16ger2pp (v512 *, vuc, vuc); + XVF16GER2PP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvf16ger2pp_internal (v512, vuc, vuc); + XVF16GER2PP_INTERNAL mma_xvf16ger2pp {mma,quad} + + void __builtin_mma_xvf32ger (v512 *, vuc, vuc); + XVF32GER nothing {mma,mmaint} + + v512 __builtin_mma_xvf32ger_internal (vuc, vuc); + XVF32GER_INTERNAL mma_xvf32ger {mma} + + void __builtin_mma_xvf32gernn (v512 *, vuc, vuc); + XVF32GERNN nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvf32gernn_internal (v512, vuc, vuc); + XVF32GERNN_INTERNAL mma_xvf32gernn {mma,quad} + + void __builtin_mma_xvf32gernp (v512 *, vuc, vuc); + XVF32GERNP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvf32gernp_internal (v512, vuc, vuc); + XVF32GERNP_INTERNAL mma_xvf32gernp {mma,quad} + + void __builtin_mma_xvf32gerpn (v512 *, vuc, vuc); + XVF32GERPN nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvf32gerpn_internal (v512, vuc, vuc); + XVF32GERPN_INTERNAL mma_xvf32gerpn {mma,quad} + + void __builtin_mma_xvf32gerpp (v512 *, vuc, vuc); + XVF32GERPP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvf32gerpp_internal (v512, vuc, vuc); + XVF32GERPP_INTERNAL mma_xvf32gerpp {mma,quad} + + void __builtin_mma_xvf64ger (v512 *, v256, vuc); + XVF64GER nothing {mma,pair,mmaint} + + v512 __builtin_mma_xvf64ger_internal (v256, vuc); + XVF64GER_INTERNAL mma_xvf64ger {mma,pair} + + void __builtin_mma_xvf64gernn (v512 *, v256, vuc); + XVF64GERNN nothing {mma,pair,quad,mmaint} + + v512 __builtin_mma_xvf64gernn_internal (v512, v256, vuc); + XVF64GERNN_INTERNAL mma_xvf64gernn {mma,pair,quad} + + void __builtin_mma_xvf64gernp (v512 *, v256, vuc); + XVF64GERNP nothing {mma,pair,quad,mmaint} + + v512 __builtin_mma_xvf64gernp_internal (v512, v256, vuc); + XVF64GERNP_INTERNAL mma_xvf64gernp {mma,pair,quad} + + void __builtin_mma_xvf64gerpn (v512 *, v256, vuc); + XVF64GERPN nothing {mma,pair,quad,mmaint} + + v512 __builtin_mma_xvf64gerpn_internal (v512, v256, vuc); + XVF64GERPN_INTERNAL mma_xvf64gerpn {mma,pair,quad} + + void __builtin_mma_xvf64gerpp (v512 *, v256, vuc); + XVF64GERPP nothing {mma,pair,quad,mmaint} + + v512 __builtin_mma_xvf64gerpp_internal (v512, v256, vuc); + XVF64GERPP_INTERNAL mma_xvf64gerpp {mma,pair,quad} + + void __builtin_mma_xvi16ger2 (v512 *, vuc, vuc); + XVI16GER2 nothing {mma,mmaint} + + v512 __builtin_mma_xvi16ger2_internal (vuc, vuc); + XVI16GER2_INTERNAL mma_xvi16ger2 {mma} + + void __builtin_mma_xvi16ger2pp (v512 *, vuc, vuc); + XVI16GER2PP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvi16ger2pp_internal (v512, vuc, vuc); + XVI16GER2PP_INTERNAL mma_xvi16ger2pp {mma,quad} + + void __builtin_mma_xvi16ger2s (v512 *, vuc, vuc); + XVI16GER2S nothing {mma,mmaint} + + v512 __builtin_mma_xvi16ger2s_internal (vuc, vuc); + XVI16GER2S_INTERNAL mma_xvi16ger2s {mma} + + void __builtin_mma_xvi16ger2spp (v512 *, vuc, vuc); + XVI16GER2SPP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvi16ger2spp_internal (v512, vuc, vuc); + XVI16GER2SPP_INTERNAL mma_xvi16ger2spp {mma,quad} + + void __builtin_mma_xvi4ger8 (v512 *, vuc, vuc); + XVI4GER8 nothing {mma,mmaint} + + v512 __builtin_mma_xvi4ger8_internal (vuc, vuc); + XVI4GER8_INTERNAL mma_xvi4ger8 {mma} + + void __builtin_mma_xvi4ger8pp (v512 *, vuc, vuc); + XVI4GER8PP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvi4ger8pp_internal (v512, vuc, vuc); + XVI4GER8PP_INTERNAL mma_xvi4ger8pp {mma,quad} + + void __builtin_mma_xvi8ger4 (v512 *, vuc, vuc); + XVI8GER4 nothing {mma,mmaint} + + v512 __builtin_mma_xvi8ger4_internal (vuc, vuc); + XVI8GER4_INTERNAL mma_xvi8ger4 {mma} + + void __builtin_mma_xvi8ger4pp (v512 *, vuc, vuc); + XVI8GER4PP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvi8ger4pp_internal (v512, vuc, vuc); + XVI8GER4PP_INTERNAL mma_xvi8ger4pp {mma,quad} + + void __builtin_mma_xvi8ger4spp (v512 *, vuc, vuc); + XVI8GER4SPP nothing {mma,quad,mmaint} + + v512 __builtin_mma_xvi8ger4spp_internal (v512, vuc, vuc); + XVI8GER4SPP_INTERNAL mma_xvi8ger4spp {mma,quad} + + void __builtin_mma_xxmfacc (v512 *); + XXMFACC nothing {mma,quad,mmaint} + + v512 __builtin_mma_xxmfacc_internal (v512); + XXMFACC_INTERNAL mma_xxmfacc {mma,quad} + + void __builtin_mma_xxmtacc (v512 *); + XXMTACC nothing {mma,quad,mmaint} + + v512 __builtin_mma_xxmtacc_internal (v512); + XXMTACC_INTERNAL mma_xxmtacc {mma,quad} + + void __builtin_mma_xxsetaccz (v512 *); + XXSETACCZ nothing {mma,mmaint} + + v512 __builtin_mma_xxsetaccz_internal (); + XXSETACCZ_INTERNAL mma_xxsetaccz {mma} + + void __builtin_vsx_assemble_pair (v256 *, vuc, vuc); + ASSEMBLE_PAIR_V nothing {mma,mmaint} + + v256 __builtin_vsx_assemble_pair_internal (vuc, vuc); + ASSEMBLE_PAIR_V_INTERNAL vsx_assemble_pair {mma} + + void __builtin_vsx_build_pair (v256 *, vuc, vuc); + BUILD_PAIR nothing {mma,mmaint} + + v256 __builtin_vsx_build_pair_internal (vuc, vuc); + BUILD_PAIR_INTERNAL vsx_assemble_pair {mma} + + void __builtin_vsx_disassemble_pair (void *, v256 *); + DISASSEMBLE_PAIR_V nothing {mma,pair,mmaint} + + vuc __builtin_vsx_disassemble_pair_internal (v256, const int<2>); + DISASSEMBLE_PAIR_V_INTERNAL vsx_disassemble_pair {mma} + + v256 __builtin_vsx_lxvp (unsigned long, const v256 *); + LXVP nothing {mma} + + void __builtin_vsx_stxvp (v256, unsigned long, const v256 *); + STXVP nothing {mma,pair} diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c index 0034fe0..bc59eb4 100644 --- a/gcc/config/rs6000/rs6000-gen-builtins.c +++ b/gcc/config/rs6000/rs6000-gen-builtins.c @@ -22,7 +22,7 @@ along with GCC; see the file COPYING3. If not see recognition code for Power targets, based on text files that describe the built-in functions and vector overloads: - rs6000-builtin-new.def Table of built-in functions + rs6000-builtins.def Table of built-in functions rs6000-overload.def Table of overload functions Both files group similar functions together in "stanzas," as @@ -126,7 +126,7 @@ along with GCC; see the file COPYING3. If not see The second line contains the that this particular instance of the overloaded function maps to. It must match a token that appears in - rs6000-builtin-new.def. Optionally, a second token may appear. If only + rs6000-builtins.def. Optionally, a second token may appear. If only one token is on the line, it is also used to build the unique identifier for the overloaded function. If a second token is present, the second token is used instead for this purpose. This is necessary in cases diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index d48a4b1..3d3143a 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -22,7 +22,7 @@ TM_H += $(srcdir)/config/rs6000/rs6000-builtin.def TM_H += $(srcdir)/config/rs6000/rs6000-cpus.def TM_H += $(srcdir)/config/rs6000/rs6000-modes.h PASSES_EXTRA += $(srcdir)/config/rs6000/rs6000-passes.def -EXTRA_GTYPE_DEPS += $(srcdir)/config/rs6000/rs6000-builtin-new.def +EXTRA_GTYPE_DEPS += $(srcdir)/config/rs6000/rs6000-builtins.def rs6000-pcrel-opt.o: $(srcdir)/config/rs6000/rs6000-pcrel-opt.c $(COMPILE) $< @@ -59,10 +59,10 @@ build/rs6000-gen-builtins$(build_exeext): build/rs6000-gen-builtins.o \ # For now, the header files depend on rs6000-builtins.c, which avoids # races because the .c file is closed last in rs6000-gen-builtins.c. rs6000-builtins.c: build/rs6000-gen-builtins$(build_exeext) \ - $(srcdir)/config/rs6000/rs6000-builtin-new.def \ + $(srcdir)/config/rs6000/rs6000-builtins.def \ $(srcdir)/config/rs6000/rs6000-overload.def $(RUN_GEN) ./build/rs6000-gen-builtins$(build_exeext) \ - $(srcdir)/config/rs6000/rs6000-builtin-new.def \ + $(srcdir)/config/rs6000/rs6000-builtins.def \ $(srcdir)/config/rs6000/rs6000-overload.def rs6000-builtins.h \ rs6000-builtins.c rs6000-vecdefines.h -- cgit v1.1 From 9e855d235a08ba941f8e5ba398f1c3e8b497ba93 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 14 Dec 2021 13:30:22 -0600 Subject: rs6000: Remove rs6000-builtin.def and associated data and functions 2021-12-02 Bill Schmidt gcc/ * config/rs6000/rs6000-builtin.def: Delete. * config/rs6000/rs6000-call.c (builtin_compatibility): Delete. (builtin_description): Delete. (builtin_hash_struct): Delete. (builtin_hasher): Delete. (builtin_hash_table): Delete. (builtin_hasher::hash): Delete. (builtin_hasher::equal): Delete. (rs6000_builtin_info_type): Delete. (rs6000_builtin_info): Delete. (bdesc_compat): Delete. (bdesc_3arg): Delete. (bdesc_4arg): Delete. (bdesc_dst): Delete. (bdesc_2arg): Delete. (bdesc_altivec_preds): Delete. (bdesc_abs): Delete. (bdesc_1arg): Delete. (bdesc_0arg): Delete. (bdesc_htm): Delete. (bdesc_mma): Delete. (rs6000_overloaded_builtin_p): Delete. (rs6000_overloaded_builtin_name): Delete. (htm_spr_num): Delete. (rs6000_builtin_is_supported_p): Delete. (rs6000_gimple_fold_mma_builtin): Delete. (gt-rs6000-call.h): Remove include directive. * config/rs6000/rs6000-protos.h (rs6000_overloaded_builtin_p): Delete. (rs6000_builtin_is_supported_p): Delete. (rs6000_overloaded_builtin_name): Delete. * config/rs6000/rs6000.c (rs6000_builtin_decls): Delete. (rs6000_debug_reg_global): Remove reference to RS6000_BUILTIN_COUNT. * config/rs6000/rs6000.h (rs6000_builtins): Delete. (altivec_builtin_types): Delete. (rs6000_builtin_decls): Delete. * config/rs6000/t-rs6000 (TM_H): Don't add rs6000-builtin.def. --- gcc/config/rs6000/rs6000-builtin.def | 3350 ---------------------------------- gcc/config/rs6000/rs6000-call.c | 712 -------- gcc/config/rs6000/rs6000-protos.h | 3 - gcc/config/rs6000/rs6000.c | 3 - gcc/config/rs6000/rs6000.h | 57 - gcc/config/rs6000/t-rs6000 | 1 - 6 files changed, 4126 deletions(-) delete mode 100644 gcc/config/rs6000/rs6000-builtin.def (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def deleted file mode 100644 index 9dbf16f..0000000 --- a/gcc/config/rs6000/rs6000-builtin.def +++ /dev/null @@ -1,3350 +0,0 @@ -/* Builtin functions for rs6000/powerpc. - Copyright (C) 2009-2021 Free Software Foundation, Inc. - Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - Under Section 7 of GPL version 3, you are granted additional - permissions described in the GCC Runtime Library Exception, version - 3.1, as published by the Free Software Foundation. - - You should have received a copy of the GNU General Public License and - a copy of the GCC Runtime Library Exception along with this program; - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - . */ - -/* Before including this file, some macros must be defined: - RS6000_BUILTIN_0 -- 0 arg builtins - RS6000_BUILTIN_1 -- 1 arg builtins - RS6000_BUILTIN_2 -- 2 arg builtins - RS6000_BUILTIN_3 -- 3 arg builtins - RS6000_BUILTIN_4 -- 4 arg builtins - RS6000_BUILTIN_A -- ABS builtins - RS6000_BUILTIN_D -- DST builtins - RS6000_BUILTIN_H -- HTM builtins - RS6000_BUILTIN_M -- MMA builtins - RS6000_BUILTIN_P -- Altivec, VSX, ISA 2.07 vector predicate builtins - RS6000_BUILTIN_X -- special builtins - - Each of the above macros takes 4 arguments: - ENUM Enumeration name - NAME String literal for the name - MASK Mask of bits that indicate which options enables the builtin - ATTR builtin attribute information. - ICODE Insn code of the function that implements the builtin. */ - -#ifndef RS6000_BUILTIN_COMPAT - #undef BU_COMPAT - #define BU_COMPAT(ENUM, COMPAT_NAME) - -#ifndef RS6000_BUILTIN_0 - #error "RS6000_BUILTIN_0 is not defined." -#endif - -#ifndef RS6000_BUILTIN_1 - #error "RS6000_BUILTIN_1 is not defined." -#endif - -#ifndef RS6000_BUILTIN_2 - #error "RS6000_BUILTIN_2 is not defined." -#endif - -#ifndef RS6000_BUILTIN_3 - #error "RS6000_BUILTIN_3 is not defined." -#endif - -#ifndef RS6000_BUILTIN_4 - #error "RS6000_BUILTIN_4 is not defined." -#endif - -#ifndef RS6000_BUILTIN_A - #error "RS6000_BUILTIN_A is not defined." -#endif - -#ifndef RS6000_BUILTIN_D - #error "RS6000_BUILTIN_D is not defined." -#endif - -#ifndef RS6000_BUILTIN_H - #error "RS6000_BUILTIN_H is not defined." -#endif - -#ifndef RS6000_BUILTIN_M - #error "RS6000_BUILTIN_M is not defined." -#endif - -#ifndef RS6000_BUILTIN_P - #error "RS6000_BUILTIN_P is not defined." -#endif - -#ifndef RS6000_BUILTIN_X - #error "RS6000_BUILTIN_X is not defined." -#endif - -#else - /* Compatibility builtins. These builtins are simply mapped into - their compatible builtin function identified by ENUM. */ - #undef BU_COMPAT - #define BU_COMPAT(ENUM, COMPAT_NAME) { ENUM, "__builtin_" COMPAT_NAME }, - - #undef RS6000_BUILTIN_0 - #undef RS6000_BUILTIN_1 - #undef RS6000_BUILTIN_2 - #undef RS6000_BUILTIN_3 - #undef RS6000_BUILTIN_4 - #undef RS6000_BUILTIN_A - #undef RS6000_BUILTIN_D - #undef RS6000_BUILTIN_H - #undef RS6000_BUILTIN_M - #undef RS6000_BUILTIN_P - #undef RS6000_BUILTIN_X - #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) - #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) - #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) - #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) - #define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) - #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) - #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) - #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) - #define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) - #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) - #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) -#endif - -#ifndef BU_AV_1 -/* Define convenience macros using token pasting to allow fitting everything in - one line. */ - -/* Altivec convenience macros. */ -#define BU_ALTIVEC_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_ALTIVEC_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_ALTIVEC_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_ALTIVEC_A(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_A (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_ABS), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_ALTIVEC_D(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_D (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_DST), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* All builtins defined with the RS6000_BUILTIN_P macro expect three - arguments, the first of which is an integer constant that clarifies - the implementation's use of CR6 flags. The integer constant - argument may have four values: __CR6_EQ (0) means the predicate is - considered true if the equality-test flag of the CR6 condition - register is true following execution of the code identified by the - ICODE pattern, __CR_EQ_REV (1) means the predicate is considered - true if the equality-test flag is false, __CR6_LT (2) means the - predicate is considered true if the less-than-test flag is true, and - __CR6_LT_REV (3) means the predicate is considered true if the - less-than-test flag is false. For all builtins defined by this - macro, the pattern selected by ICODE expects three operands, a - target and two inputs and is presumed to overwrite the flags of - condition register CR6 as a side effect of computing a result into - the target register. However, the built-in invocation provides - four operands, a target, an integer constant mode, and two inputs. - The second and third operands of the built-in function's invocation - are automatically mapped into operands 1 and 2 of the pattern - identifed by the ICODE argument and additional code is emitted, - depending on the value of the constant integer first argument. - This special processing happens within the implementation of - altivec_expand_predicate_builtin(), which is defined within - rs6000.c. The implementation of altivec_expand_predicate_builtin() - allocates a scratch register having the same mode as operand 0 to hold - the result produced by evaluating ICODE. */ - -#define BU_ALTIVEC_P(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_P (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_PREDICATE), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_ALTIVEC_X(ENUM, NAME, ATTR) \ - RS6000_BUILTIN_X (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_ALTIVEC_C(ENUM, NAME, ATTR) \ - RS6000_BUILTIN_X (ALTIVEC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - (RS6000_BTM_ALTIVEC /* MASK */ \ - | RS6000_BTM_CELL), \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - -/* Altivec overloaded builtin function macros. */ -#define BU_ALTIVEC_OVERLOAD_1(ENUM, NAME) \ - RS6000_BUILTIN_1 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_ALTIVEC_OVERLOAD_2(ENUM, NAME) \ - RS6000_BUILTIN_2 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_ALTIVEC_OVERLOAD_3(ENUM, NAME) \ - RS6000_BUILTIN_3 (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_ALTIVEC_OVERLOAD_A(ENUM, NAME) \ - RS6000_BUILTIN_A (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_ABS), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_ALTIVEC_OVERLOAD_D(ENUM, NAME) \ - RS6000_BUILTIN_D (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_DST), \ - CODE_FOR_nothing) /* ICODE */ - -/* See the comment on BU_ALTIVEC_P. */ -#define BU_ALTIVEC_OVERLOAD_P(ENUM, NAME) \ - RS6000_BUILTIN_P (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_PREDICATE), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_ALTIVEC_OVERLOAD_X(ENUM, NAME) \ - RS6000_BUILTIN_X (ALTIVEC_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - -/* VSX convenience macros. */ -#define BU_VSX_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_VSX_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_VSX_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_VSX_A(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_A (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_ABS), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* See the comment on BU_ALTIVEC_P. */ -#define BU_VSX_P(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_P (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_PREDICATE), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_VSX_X(ENUM, NAME, ATTR) \ - RS6000_BUILTIN_X (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - -/* VSX overloaded builtin function macros. */ -#define BU_VSX_OVERLOAD_1(ENUM, NAME) \ - RS6000_BUILTIN_1 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_VSX_OVERLOAD_2(ENUM, NAME) \ - RS6000_BUILTIN_2 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_VSX_OVERLOAD_3(ENUM, NAME) \ - RS6000_BUILTIN_3 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_nothing) /* ICODE */ - -/* xxpermdi and xxsldwi are overloaded functions, but had __builtin_vsx names - instead of __builtin_vec. */ -#define BU_VSX_OVERLOAD_3V(ENUM, NAME) \ - RS6000_BUILTIN_3 (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_VSX_OVERLOAD_X(ENUM, NAME) \ - RS6000_BUILTIN_X (VSX_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_VSX, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - -/* MMA convenience macros. */ - -#define BU_MMA_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_M (MMA_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_mma_" NAME, /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY \ - | RS6000_BTC_VOID \ - | RS6000_BTC_GIMPLE), \ - CODE_FOR_nothing) /* ICODE */ \ - RS6000_BUILTIN_M (MMA_BUILTIN_ ## ENUM ## _INTERNAL, /* ENUM */ \ - "__builtin_mma_" NAME "_internal", /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_MMA_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_M (MMA_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_mma_" NAME, /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY \ - | RS6000_BTC_VOID \ - | RS6000_BTC_GIMPLE), \ - CODE_FOR_nothing) /* ICODE */ \ - RS6000_BUILTIN_M (MMA_BUILTIN_ ## ENUM ## _INTERNAL, /* ENUM */ \ - "__builtin_mma_" NAME "_internal", /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* Like BU_MMA_2, but uses "vsx" rather than "mma" naming. */ -#define BU_MMA_V2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_M (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY \ - | RS6000_BTC_VOID \ - | RS6000_BTC_GIMPLE), \ - CODE_FOR_nothing) /* ICODE */ \ - RS6000_BUILTIN_M (VSX_BUILTIN_ ## ENUM ## _INTERNAL, /* ENUM */ \ - "__builtin_vsx_" NAME "_internal", /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_MMA_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_M (MMA_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_mma_" NAME, /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY \ - | RS6000_BTC_VOID \ - | RS6000_BTC_GIMPLE), \ - CODE_FOR_nothing) /* ICODE */ \ - RS6000_BUILTIN_M (MMA_BUILTIN_ ## ENUM ## _INTERNAL, /* ENUM */ \ - "__builtin_mma_" NAME "_internal", /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* Like BU_MMA_3, but uses "vsx" rather than "mma" naming. */ -#define BU_MMA_V3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_M (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY \ - | RS6000_BTC_VOID \ - | RS6000_BTC_GIMPLE), \ - CODE_FOR_nothing) /* ICODE */ \ - RS6000_BUILTIN_M (VSX_BUILTIN_ ## ENUM ## _INTERNAL, /* ENUM */ \ - "__builtin_vsx_" NAME "_internal", /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_MMA_5(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_M (MMA_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_mma_" NAME, /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_QUINARY \ - | RS6000_BTC_VOID \ - | RS6000_BTC_GIMPLE), \ - CODE_FOR_nothing) /* ICODE */ \ - RS6000_BUILTIN_M (MMA_BUILTIN_ ## ENUM ## _INTERNAL, /* ENUM */ \ - "__builtin_mma_" NAME "_internal", /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_QUINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_MMA_6(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_M (MMA_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_mma_" NAME, /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SENARY \ - | RS6000_BTC_VOID \ - | RS6000_BTC_GIMPLE), \ - CODE_FOR_nothing) /* ICODE */ \ - RS6000_BUILTIN_M (MMA_BUILTIN_ ## ENUM ## _INTERNAL, /* ENUM */ \ - "__builtin_mma_" NAME "_internal", /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SENARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_MMA_PAIR_LD(ENUM, NAME, ATTR) \ - RS6000_BUILTIN_M (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY \ - | RS6000_BTC_GIMPLE), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_MMA_PAIR_ST(ENUM, NAME, ATTR) \ - RS6000_BUILTIN_M (VSX_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_MMA, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY \ - | RS6000_BTC_VOID \ - | RS6000_BTC_GIMPLE), \ - CODE_FOR_nothing) /* ICODE */ - -/* ISA 2.05 (power6) convenience macros. */ -/* For functions that depend on the CMPB instruction */ -#define BU_P6_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P6_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_p6_" NAME, /* NAME */ \ - RS6000_BTM_CMPB, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* For functions that depend on 64-BIT support and on the CMPB instruction */ -#define BU_P6_64BIT_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P6_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_p6_" NAME, /* NAME */ \ - RS6000_BTM_CMPB \ - | RS6000_BTM_64BIT, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P6_OVERLOAD_2(ENUM, NAME) \ - RS6000_BUILTIN_2 (P6_OV_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_CMPB, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_nothing) /* ICODE */ - -/* ISA 2.07 (power8) vector convenience macros. */ -/* For the instructions that are encoded as altivec instructions use - __builtin_altivec_ as the builtin name. */ -#define BU_P8V_AV_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P8V_AV_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P8V_AV_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* See the comment on BU_ALTIVEC_P. */ -#define BU_P8V_AV_P(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_P (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_PREDICATE), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* For the instructions encoded as VSX instructions use __builtin_vsx as the - builtin name. */ -#define BU_P8V_VSX_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P8V_VSX_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P8V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P8V_OVERLOAD_1(ENUM, NAME) \ - RS6000_BUILTIN_1 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P8V_OVERLOAD_2(ENUM, NAME) \ - RS6000_BUILTIN_2 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P8V_OVERLOAD_3(ENUM, NAME) \ - RS6000_BUILTIN_3 (P8V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_nothing) /* ICODE */ - -/* Crypto convenience macros. */ -#define BU_CRYPTO_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_crypto_" NAME, /* NAME */ \ - RS6000_BTM_CRYPTO, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_CRYPTO_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_crypto_" NAME, /* NAME */ \ - RS6000_BTM_CRYPTO, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_CRYPTO_2A(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_crypto_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_CRYPTO_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_crypto_" NAME, /* NAME */ \ - RS6000_BTM_CRYPTO, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_CRYPTO_3A(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_crypto_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_CRYPTO_OVERLOAD_1(ENUM, NAME) \ - RS6000_BUILTIN_1 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_crypto_" NAME, /* NAME */ \ - RS6000_BTM_CRYPTO, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_CRYPTO_OVERLOAD_2A(ENUM, NAME) \ - RS6000_BUILTIN_2 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_crypto_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_CRYPTO_OVERLOAD_3(ENUM, NAME) \ - RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_crypto_" NAME, /* NAME */ \ - RS6000_BTM_CRYPTO, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_CRYPTO_OVERLOAD_3A(ENUM, NAME) \ - RS6000_BUILTIN_3 (CRYPTO_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_crypto_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_nothing) /* ICODE */ - -/* HTM convenience macros. */ -#define BU_HTM_0(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_HTM, /* MASK */ \ - RS6000_BTC_ ## ATTR, /* ATTR */ \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_HTM_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_HTM, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_HTM_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_HTM, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_HTM_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_HTM, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_HTM_V1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_H (HTM_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_HTM, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY \ - | RS6000_BTC_VOID), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_SPECIAL_X(ENUM, NAME, MASK, ATTR) \ - RS6000_BUILTIN_X (ENUM, /* ENUM */ \ - NAME, /* NAME */ \ - MASK, /* MASK */ \ - (ATTR | RS6000_BTC_SPECIAL), /* ATTR */ \ - CODE_FOR_nothing) /* ICODE */ - - -/* Decimal floating point builtins for instructions. */ -#define BU_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_DFP, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_DFP, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* Miscellaneous builtins for instructions added in ISA 2.06. These - instructions don't require either the DFP or VSX options, just the basic ISA - 2.06 (popcntd) enablement since they operate on general purpose - registers. */ -#define BU_P7_MISC_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_POPCNTD, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P7_MISC_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_POPCNTD, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P7_POWERPC64_MISC_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_POPCNTD \ - | RS6000_BTM_POWERPC64, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P7_MISC_X(ENUM, NAME, ATTR) \ - RS6000_BUILTIN_X (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_POPCNTD, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - - -/* Miscellaneous builtins for instructions added in ISA 2.07. These - instructions do require the ISA 2.07 vector support, but they aren't vector - instructions. */ -#define BU_P8V_MISC_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P8V_MISC_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P8_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* 128-bit long double floating point builtins. */ -#define BU_LDBL128_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - (RS6000_BTM_HARD_FLOAT /* MASK */ \ - | RS6000_BTM_LDBL128), \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* 128-bit __ibm128 floating point builtins (use -mfloat128 to indicate that - __ibm128 is available). */ -#define BU_IBM128_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - (RS6000_BTM_HARD_FLOAT /* MASK */ \ - | RS6000_BTM_FLOAT128), \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* Miscellaneous builtins for instructions added in ISA 3.0. These - instructions don't require either the DFP or VSX options, just the basic - ISA 3.0 enablement since they operate on general purpose registers. */ -#define BU_P9_MISC_0(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P9_MISC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9_MISC_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P9_MISC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* Miscellaneous builtins for instructions added in ISA 3.0. These - instructions don't require either the DFP or VSX options, just the basic - ISA 3.0 enablement since they operate on general purpose registers, - and they require 64-bit addressing. */ -#define BU_P9_64BIT_MISC_0(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P9_MISC \ - | RS6000_BTM_64BIT, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* Miscellaneous builtins for decimal floating point instructions - added in ISA 3.0. These instructions don't require the VSX - options, just the basic ISA 3.0 enablement since they operate on - general purpose registers. */ -#define BU_P9_DFP_MISC_0(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_0 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P9_MISC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P9_MISC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P9_MISC, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* Decimal floating point overloaded functions added in ISA 3.0 */ -#define BU_P9_DFP_OVERLOAD_1(ENUM, NAME) \ - RS6000_BUILTIN_1 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \ - "__builtin_dfp_" NAME, /* NAME */ \ - RS6000_BTM_P9_MISC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P9_DFP_OVERLOAD_2(ENUM, NAME) \ - RS6000_BUILTIN_2 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \ - "__builtin_dfp_" NAME, /* NAME */ \ - RS6000_BTM_P9_MISC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P9_DFP_OVERLOAD_3(ENUM, NAME) \ - RS6000_BUILTIN_3 (P9_BUILTIN_DFP_ ## ENUM, /* ENUM */ \ - "__builtin_dfp_" NAME, /* NAME */ \ - RS6000_BTM_P9_MISC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_nothing) /* ICODE */ - -/* ISA 3.0 (power9) vector convenience macros. */ -/* For the instructions that are encoded as altivec instructions use - __builtin_altivec_ as the builtin name. */ -#define BU_P9V_AV_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9V_AV_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9V_AV_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* See the comment on BU_ALTIVEC_P. */ -#define BU_P9V_AV_P(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_P (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_PREDICATE), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9V_AV_X(ENUM, NAME, ATTR) \ - RS6000_BUILTIN_X (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P9V_64BIT_AV_X(ENUM, NAME, ATTR) \ - RS6000_BUILTIN_X (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - (RS6000_BTM_P9_VECTOR \ - | RS6000_BTM_64BIT), /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - -/* For the instructions encoded as VSX instructions use __builtin_vsx as the - builtin name. */ -#define BU_P9V_VSX_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9V_64BIT_VSX_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - (RS6000_BTM_64BIT \ - | RS6000_BTM_P9_VECTOR), /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9V_VSX_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9V_64BIT_VSX_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - (RS6000_BTM_64BIT \ - | RS6000_BTM_P9_VECTOR), /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9V_VSX_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9V_64BIT_VSX_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - (RS6000_BTM_64BIT \ - | RS6000_BTM_P9_VECTOR), /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* See the comment on BU_ALTIVEC_P. */ -#define BU_P9V_OVERLOAD_P(ENUM, NAME) \ - RS6000_BUILTIN_P (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_ALTIVEC, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_PREDICATE), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P9_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P9_BUILTIN_SCALAR_ ## ENUM, /* ENUM */ \ - "__builtin_scalar_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9_64BIT_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P9_BUILTIN_SCALAR_ ## ENUM, /* ENUM */ \ - "__builtin_scalar_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR \ - | RS6000_BTM_64BIT, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P9V_OVERLOAD_1(ENUM, NAME) \ - RS6000_BUILTIN_1 (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P9V_OVERLOAD_2(ENUM, NAME) \ - RS6000_BUILTIN_2 (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P9V_OVERLOAD_3(ENUM, NAME) \ - RS6000_BUILTIN_3 (P9V_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P9_OVERLOAD_2(ENUM, NAME) \ - RS6000_BUILTIN_2 (P9_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P9_VECTOR, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_nothing) /* ICODE */ - -/* Built-in functions for IEEE 128-bit hardware floating point. IEEE 128-bit - hardware requires p9-vector and 64-bit operation. These functions use just - __builtin_ as the prefix. */ -#define BU_FLOAT128_HW_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (FLOAT128_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_FLOAT128_HW, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_FLOAT128_HW_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (FLOAT128_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_FLOAT128_HW, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_FLOAT128_HW_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (FLOAT128_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_FLOAT128_HW, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* Built-in functions for IEEE 128-bit hardware floating point. These - functions use __builtin_vsx_ as the prefix. */ -#define BU_FLOAT128_HW_VSX_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_FLOAT128_HW, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_FLOAT128_HW_VSX_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P9V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_FLOAT128_HW, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* Power 10 VSX builtins */ - -#define BU_P10V_VSX_0(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_0 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10V_VSX_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10V_VSX_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10V_VSX_4(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_4 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vsx_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_QUATERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10_OVERLOAD_1(ENUM, NAME) \ - RS6000_BUILTIN_1 (P10_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P10_OVERLOAD_2(ENUM, NAME) \ - RS6000_BUILTIN_2 (P10_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P10_OVERLOAD_3(ENUM, NAME) \ - RS6000_BUILTIN_3 (P10_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_nothing) /* ICODE */ - -#define BU_P10_OVERLOAD_4(ENUM, NAME) \ - RS6000_BUILTIN_4 (P10_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_QUATERNARY), \ - CODE_FOR_nothing) /* ICODE */ - -/* Miscellaneous (non-vector) builtins for power10 instructions. */ - -#define BU_P10_MISC_0(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_0 (P10_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10_MISC_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10_POWERPC64_MISC_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P10_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P10 \ - | RS6000_BTM_POWERPC64, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10_MISC_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (P10_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vec" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P10_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_vec" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ -#endif - -#define BU_P10V_OVERLOAD_X(ENUM, NAME) \ - RS6000_BUILTIN_X (P10_BUILTIN_VEC_ ## ENUM, /* ENUM */ \ - "__builtin_vec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_OVERLOADED /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - -/* Power 10 Altivec builtins */ - -#define BU_P10V_AV_0(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_0 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10V_AV_1(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_UNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10V_AV_2(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_2 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_BINARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10V_AV_3(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_3 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_TERNARY), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -/* See the comment on BU_ALTIVEC_P. */ -#define BU_P10V_AV_P(ENUM, NAME, ATTR, ICODE) \ - RS6000_BUILTIN_P (P10V_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_PREDICATE), \ - CODE_FOR_ ## ICODE) /* ICODE */ - -#define BU_P10V_AV_X(ENUM, NAME, ATTR) \ - RS6000_BUILTIN_X (P10_BUILTIN_ ## ENUM, /* ENUM */ \ - "__builtin_altivec_" NAME, /* NAME */ \ - RS6000_BTM_P10, /* MASK */ \ - (RS6000_BTC_ ## ATTR /* ATTR */ \ - | RS6000_BTC_SPECIAL), \ - CODE_FOR_nothing) /* ICODE */ - - - -/* Insure 0 is not a legitimate index. */ -BU_SPECIAL_X (RS6000_BUILTIN_NONE, NULL, 0, RS6000_BTC_MISC) - -/* 3 argument Altivec builtins. */ -BU_ALTIVEC_3 (VMADDFP, "vmaddfp", FP, fmav4sf4) -BU_ALTIVEC_3 (VMHADDSHS, "vmhaddshs", SAT, altivec_vmhaddshs) -BU_ALTIVEC_3 (VMHRADDSHS, "vmhraddshs", SAT, altivec_vmhraddshs) -BU_ALTIVEC_3 (VMLADDUHM, "vmladduhm", CONST, fmav8hi4) -BU_ALTIVEC_3 (VMSUMUBM, "vmsumubm", CONST, altivec_vmsumubm) -BU_ALTIVEC_3 (VMSUMMBM, "vmsummbm", CONST, altivec_vmsummbm) -BU_ALTIVEC_3 (VMSUMUHM, "vmsumuhm", CONST, altivec_vmsumuhm) -BU_ALTIVEC_3 (VMSUMUDM, "vmsumudm", CONST, altivec_vmsumudm) -BU_ALTIVEC_3 (VMSUMSHM, "vmsumshm", CONST, altivec_vmsumshm) -BU_ALTIVEC_3 (VMSUMUHS, "vmsumuhs", SAT, altivec_vmsumuhs) -BU_ALTIVEC_3 (VMSUMSHS, "vmsumshs", SAT, altivec_vmsumshs) -BU_ALTIVEC_3 (VNMSUBFP, "vnmsubfp", FP, nfmsv4sf4) -BU_ALTIVEC_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti) -BU_ALTIVEC_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df) -BU_ALTIVEC_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di) -BU_ALTIVEC_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf) -BU_ALTIVEC_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si) -BU_ALTIVEC_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi) -BU_ALTIVEC_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi_uns) -BU_ALTIVEC_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns) -BU_ALTIVEC_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns) -BU_ALTIVEC_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns) -BU_ALTIVEC_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns) -BU_ALTIVEC_3 (VPERM_16QI_UNS, "vperm_16qi_uns", CONST, altivec_vperm_v16qi_uns) -BU_ALTIVEC_3 (VSEL_4SF, "vsel_4sf", CONST, vector_select_v4sf) -BU_ALTIVEC_3 (VSEL_4SI, "vsel_4si", CONST, vector_select_v4si) -BU_ALTIVEC_3 (VSEL_8HI, "vsel_8hi", CONST, vector_select_v8hi) -BU_ALTIVEC_3 (VSEL_16QI, "vsel_16qi", CONST, vector_select_v16qi) -BU_ALTIVEC_3 (VSEL_2DF, "vsel_2df", CONST, vector_select_v2df) -BU_ALTIVEC_3 (VSEL_2DI, "vsel_2di", CONST, vector_select_v2di) -BU_ALTIVEC_3 (VSEL_1TI, "vsel_1ti", CONST, vector_select_v1ti) -BU_ALTIVEC_3 (VSEL_4SI_UNS, "vsel_4si_uns", CONST, vector_select_v4si_uns) -BU_ALTIVEC_3 (VSEL_8HI_UNS, "vsel_8hi_uns", CONST, vector_select_v8hi_uns) -BU_ALTIVEC_3 (VSEL_16QI_UNS, "vsel_16qi_uns", CONST, vector_select_v16qi_uns) -BU_ALTIVEC_3 (VSEL_2DI_UNS, "vsel_2di_uns", CONST, vector_select_v2di_uns) -BU_ALTIVEC_3 (VSEL_1TI_UNS, "vsel_1ti_uns", CONST, vector_select_v1ti_uns) -BU_ALTIVEC_3 (VSLDOI_16QI, "vsldoi_16qi", CONST, altivec_vsldoi_v16qi) -BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, altivec_vsldoi_v8hi) -BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, altivec_vsldoi_v4si) -BU_ALTIVEC_3 (VSLDOI_2DI, "vsldoi_2di", CONST, altivec_vsldoi_v2di) -BU_ALTIVEC_3 (VSLDOI_4SF, "vsldoi_4sf", CONST, altivec_vsldoi_v4sf) -BU_ALTIVEC_3 (VSLDOI_2DF, "vsldoi_2df", CONST, altivec_vsldoi_v2df) - -/* Altivec DST builtins. */ -BU_ALTIVEC_D (DST, "dst", MISC, altivec_dst) -BU_ALTIVEC_D (DSTT, "dstt", MISC, altivec_dstt) -BU_ALTIVEC_D (DSTST, "dstst", MISC, altivec_dstst) -BU_ALTIVEC_D (DSTSTT, "dststt", MISC, altivec_dststt) - -/* Altivec 2 argument builtin functions. */ -BU_ALTIVEC_2 (VADDUBM, "vaddubm", CONST, addv16qi3) -BU_ALTIVEC_2 (VADDUHM, "vadduhm", CONST, addv8hi3) -BU_ALTIVEC_2 (VADDUWM, "vadduwm", CONST, addv4si3) -BU_ALTIVEC_2 (VADDFP, "vaddfp", CONST, addv4sf3) -BU_ALTIVEC_2 (VADDCUW, "vaddcuw", CONST, altivec_vaddcuw) -BU_ALTIVEC_2 (VADDUBS, "vaddubs", CONST, altivec_vaddubs) -BU_ALTIVEC_2 (VADDSBS, "vaddsbs", CONST, altivec_vaddsbs) -BU_ALTIVEC_2 (VADDUHS, "vadduhs", CONST, altivec_vadduhs) -BU_ALTIVEC_2 (VADDSHS, "vaddshs", CONST, altivec_vaddshs) -BU_ALTIVEC_2 (VADDUWS, "vadduws", CONST, altivec_vadduws) -BU_ALTIVEC_2 (VADDSWS, "vaddsws", CONST, altivec_vaddsws) -BU_ALTIVEC_2 (VAND_V16QI_UNS, "vand_v16qi_uns", CONST, andv16qi3) -BU_ALTIVEC_2 (VAND_V16QI, "vand_v16qi", CONST, andv16qi3) -BU_ALTIVEC_2 (VAND_V8HI_UNS, "vand_v8hi_uns", CONST, andv8hi3) -BU_ALTIVEC_2 (VAND_V8HI, "vand_v8hi", CONST, andv8hi3) -BU_ALTIVEC_2 (VAND_V4SI_UNS, "vand_v4si_uns", CONST, andv4si3) -BU_ALTIVEC_2 (VAND_V4SI, "vand_v4si", CONST, andv4si3) -BU_ALTIVEC_2 (VAND_V2DI_UNS, "vand_v2di_uns", CONST, andv2di3) -BU_ALTIVEC_2 (VAND_V2DI, "vand_v2di", CONST, andv2di3) -BU_ALTIVEC_2 (VAND_V4SF, "vand_v4sf", CONST, andv4sf3) -BU_ALTIVEC_2 (VAND_V2DF, "vand_v2df", CONST, andv2df3) -BU_ALTIVEC_2 (VANDC_V16QI_UNS,"vandc_v16qi_uns",CONST, andcv16qi3) -BU_ALTIVEC_2 (VANDC_V16QI, "vandc_v16qi", CONST, andcv16qi3) -BU_ALTIVEC_2 (VANDC_V8HI_UNS, "vandc_v8hi_uns", CONST, andcv8hi3) -BU_ALTIVEC_2 (VANDC_V8HI, "vandc_v8hi", CONST, andcv8hi3) -BU_ALTIVEC_2 (VANDC_V4SI_UNS, "vandc_v4si_uns", CONST, andcv4si3) -BU_ALTIVEC_2 (VANDC_V4SI, "vandc_v4si", CONST, andcv4si3) -BU_ALTIVEC_2 (VANDC_V2DI_UNS, "vandc_v2di_uns", CONST, andcv2di3) -BU_ALTIVEC_2 (VANDC_V2DI, "vandc_v2di", CONST, andcv2di3) -BU_ALTIVEC_2 (VANDC_V4SF, "vandc_v4sf", CONST, andcv4sf3) -BU_ALTIVEC_2 (VANDC_V2DF, "vandc_v2df", CONST, andcv2df3) -BU_ALTIVEC_2 (VAVGUB, "vavgub", CONST, uavgv16qi3_ceil) -BU_ALTIVEC_2 (VAVGSB, "vavgsb", CONST, avgv16qi3_ceil) -BU_ALTIVEC_2 (VAVGUH, "vavguh", CONST, uavgv8hi3_ceil) -BU_ALTIVEC_2 (VAVGSH, "vavgsh", CONST, avgv8hi3_ceil) -BU_ALTIVEC_2 (VAVGUW, "vavguw", CONST, uavgv4si3_ceil) -BU_ALTIVEC_2 (VAVGSW, "vavgsw", CONST, avgv4si3_ceil) -BU_ALTIVEC_2 (VCFUX, "vcfux", CONST, altivec_vcfux) -BU_ALTIVEC_2 (VCFSX, "vcfsx", CONST, altivec_vcfsx) -BU_ALTIVEC_2 (VCMPBFP, "vcmpbfp", CONST, altivec_vcmpbfp) -BU_ALTIVEC_2 (VCMPEQUB, "vcmpequb", CONST, vector_eqv16qi) -BU_ALTIVEC_2 (VCMPEQUH, "vcmpequh", CONST, vector_eqv8hi) -BU_ALTIVEC_2 (VCMPEQUW, "vcmpequw", CONST, vector_eqv4si) -BU_ALTIVEC_2 (VCMPEQFP, "vcmpeqfp", CONST, vector_eqv4sf) -BU_ALTIVEC_2 (VCMPGEFP, "vcmpgefp", CONST, vector_gev4sf) -BU_ALTIVEC_2 (VCMPGTUB, "vcmpgtub", CONST, vector_gtuv16qi) -BU_ALTIVEC_2 (VCMPGTSB, "vcmpgtsb", CONST, vector_gtv16qi) -BU_ALTIVEC_2 (VCMPGTUH, "vcmpgtuh", CONST, vector_gtuv8hi) -BU_ALTIVEC_2 (VCMPGTSH, "vcmpgtsh", CONST, vector_gtv8hi) -BU_ALTIVEC_2 (VCMPGTUW, "vcmpgtuw", CONST, vector_gtuv4si) -BU_ALTIVEC_2 (VCMPGTSW, "vcmpgtsw", CONST, vector_gtv4si) -BU_ALTIVEC_2 (VCMPGTFP, "vcmpgtfp", CONST, vector_gtv4sf) -BU_ALTIVEC_2 (VCTSXS, "vctsxs", CONST, altivec_vctsxs) -BU_ALTIVEC_2 (VCTUXS, "vctuxs", CONST, altivec_vctuxs) -BU_ALTIVEC_2 (VMAXUB, "vmaxub", CONST, umaxv16qi3) -BU_ALTIVEC_2 (VMAXSB, "vmaxsb", CONST, smaxv16qi3) -BU_ALTIVEC_2 (VMAXUH, "vmaxuh", CONST, umaxv8hi3) -BU_ALTIVEC_2 (VMAXSH, "vmaxsh", CONST, smaxv8hi3) -BU_ALTIVEC_2 (VMAXUW, "vmaxuw", CONST, umaxv4si3) -BU_ALTIVEC_2 (VMAXSW, "vmaxsw", CONST, smaxv4si3) -BU_ALTIVEC_2 (VMAXFP, "vmaxfp", CONST, smaxv4sf3) -BU_ALTIVEC_2 (VMRGHB, "vmrghb", CONST, altivec_vmrghb) -BU_ALTIVEC_2 (VMRGHH, "vmrghh", CONST, altivec_vmrghh) -BU_ALTIVEC_2 (VMRGHW, "vmrghw", CONST, altivec_vmrghw) -BU_ALTIVEC_2 (VMRGLB, "vmrglb", CONST, altivec_vmrglb) -BU_ALTIVEC_2 (VMRGLH, "vmrglh", CONST, altivec_vmrglh) -BU_ALTIVEC_2 (VMRGLW, "vmrglw", CONST, altivec_vmrglw) -BU_ALTIVEC_2 (VMINUB, "vminub", CONST, uminv16qi3) -BU_ALTIVEC_2 (VMINSB, "vminsb", CONST, sminv16qi3) -BU_ALTIVEC_2 (VMINUH, "vminuh", CONST, uminv8hi3) -BU_ALTIVEC_2 (VMINSH, "vminsh", CONST, sminv8hi3) -BU_ALTIVEC_2 (VMINUW, "vminuw", CONST, uminv4si3) -BU_ALTIVEC_2 (VMINSW, "vminsw", CONST, sminv4si3) -BU_ALTIVEC_2 (VMINFP, "vminfp", CONST, sminv4sf3) -BU_ALTIVEC_2 (VMULEUB, "vmuleub", CONST, vec_widen_umult_even_v16qi) -BU_ALTIVEC_2 (VMULESB, "vmulesb", CONST, vec_widen_smult_even_v16qi) -BU_ALTIVEC_2 (VMULEUH, "vmuleuh", CONST, vec_widen_umult_even_v8hi) -BU_ALTIVEC_2 (VMULESH, "vmulesh", CONST, vec_widen_smult_even_v8hi) -BU_P8V_AV_2 (VMULEUW, "vmuleuw", CONST, vec_widen_umult_even_v4si) -BU_P8V_AV_2 (VMULESW, "vmulesw", CONST, vec_widen_smult_even_v4si) -BU_ALTIVEC_2 (VMULOUB, "vmuloub", CONST, vec_widen_umult_odd_v16qi) -BU_ALTIVEC_2 (VMULOSB, "vmulosb", CONST, vec_widen_smult_odd_v16qi) -BU_ALTIVEC_2 (VMULOUH, "vmulouh", CONST, vec_widen_umult_odd_v8hi) -BU_ALTIVEC_2 (VMULOSH, "vmulosh", CONST, vec_widen_smult_odd_v8hi) -BU_P8V_AV_2 (VMULOUW, "vmulouw", CONST, vec_widen_umult_odd_v4si) -BU_P8V_AV_2 (VMULOSW, "vmulosw", CONST, vec_widen_smult_odd_v4si) -BU_ALTIVEC_2 (VNOR_V16QI_UNS, "vnor_v16qi_uns", CONST, norv16qi3) -BU_ALTIVEC_2 (VNOR_V16QI, "vnor_v16qi", CONST, norv16qi3) -BU_ALTIVEC_2 (VNOR_V8HI_UNS, "vnor_v8hi_uns", CONST, norv8hi3) -BU_ALTIVEC_2 (VNOR_V8HI, "vnor_v8hi", CONST, norv8hi3) -BU_ALTIVEC_2 (VNOR_V4SI_UNS, "vnor_v4si_uns", CONST, norv4si3) -BU_ALTIVEC_2 (VNOR_V4SI, "vnor_v4si", CONST, norv4si3) -BU_ALTIVEC_2 (VNOR_V2DI_UNS, "vnor_v2di_uns", CONST, norv2di3) -BU_ALTIVEC_2 (VNOR_V2DI, "vnor_v2di", CONST, norv2di3) -BU_ALTIVEC_2 (VNOR_V4SF, "vnor_v4sf", CONST, norv4sf3) -BU_ALTIVEC_2 (VNOR_V2DF, "vnor_v2df", CONST, norv2df3) -BU_ALTIVEC_2 (VOR_V16QI_UNS, "vor_v16qi_uns", CONST, iorv16qi3) -BU_ALTIVEC_2 (VOR_V16QI, "vor_v16qi", CONST, iorv16qi3) -BU_ALTIVEC_2 (VOR_V8HI_UNS, "vor_v8hi_uns", CONST, iorv8hi3) -BU_ALTIVEC_2 (VOR_V8HI, "vor_v8hi", CONST, iorv8hi3) -BU_ALTIVEC_2 (VOR_V4SI_UNS, "vor_v4si_uns", CONST, iorv4si3) -BU_ALTIVEC_2 (VOR_V4SI, "vor_v4si", CONST, iorv4si3) -BU_ALTIVEC_2 (VOR_V2DI_UNS, "vor_v2di_uns", CONST, iorv2di3) -BU_ALTIVEC_2 (VOR_V2DI, "vor_v2di", CONST, iorv2di3) -BU_ALTIVEC_2 (VOR_V4SF, "vor_v4sf", CONST, iorv4sf3) -BU_ALTIVEC_2 (VOR_V2DF, "vor_v2df", CONST, iorv2df3) - -BU_ALTIVEC_2 (VPKUHUM, "vpkuhum", CONST, altivec_vpkuhum) -BU_ALTIVEC_2 (VPKUWUM, "vpkuwum", CONST, altivec_vpkuwum) -BU_ALTIVEC_2 (VPKPX, "vpkpx", CONST, altivec_vpkpx) -BU_ALTIVEC_2 (VPKSHSS, "vpkshss", CONST, altivec_vpkshss) -BU_ALTIVEC_2 (VPKSWSS, "vpkswss", CONST, altivec_vpkswss) -BU_ALTIVEC_2 (VPKUHUS, "vpkuhus", CONST, altivec_vpkuhus) -BU_ALTIVEC_2 (VPKSHUS, "vpkshus", CONST, altivec_vpkshus) -BU_ALTIVEC_2 (VPKUWUS, "vpkuwus", CONST, altivec_vpkuwus) -BU_ALTIVEC_2 (VPKSWUS, "vpkswus", CONST, altivec_vpkswus) -BU_ALTIVEC_2 (VRECIPFP, "vrecipdivfp", CONST, recipv4sf3) -BU_ALTIVEC_2 (VRLB, "vrlb", CONST, vrotlv16qi3) -BU_ALTIVEC_2 (VRLH, "vrlh", CONST, vrotlv8hi3) -BU_ALTIVEC_2 (VRLW, "vrlw", CONST, vrotlv4si3) -BU_ALTIVEC_2 (VSLB, "vslb", CONST, vashlv16qi3) -BU_ALTIVEC_2 (VSLH, "vslh", CONST, vashlv8hi3) -BU_ALTIVEC_2 (VSLW, "vslw", CONST, vashlv4si3) -BU_ALTIVEC_2 (VSL, "vsl", CONST, altivec_vsl) -BU_ALTIVEC_2 (VSLO, "vslo", CONST, altivec_vslo) -BU_ALTIVEC_2 (VSPLTB, "vspltb", CONST, altivec_vspltb) -BU_ALTIVEC_2 (VSPLTH, "vsplth", CONST, altivec_vsplth) -BU_ALTIVEC_2 (VSPLTW, "vspltw", CONST, altivec_vspltw) -BU_ALTIVEC_2 (VSRB, "vsrb", CONST, vlshrv16qi3) -BU_ALTIVEC_2 (VSRH, "vsrh", CONST, vlshrv8hi3) -BU_ALTIVEC_2 (VSRW, "vsrw", CONST, vlshrv4si3) -BU_ALTIVEC_2 (VSRAB, "vsrab", CONST, vashrv16qi3) -BU_ALTIVEC_2 (VSRAH, "vsrah", CONST, vashrv8hi3) -BU_ALTIVEC_2 (VSRAW, "vsraw", CONST, vashrv4si3) -BU_ALTIVEC_2 (VSR, "vsr", CONST, altivec_vsr) -BU_ALTIVEC_2 (VSRO, "vsro", CONST, altivec_vsro) -BU_ALTIVEC_2 (VSUBUBM, "vsububm", CONST, subv16qi3) -BU_ALTIVEC_2 (VSUBUHM, "vsubuhm", CONST, subv8hi3) -BU_ALTIVEC_2 (VSUBUWM, "vsubuwm", CONST, subv4si3) -BU_ALTIVEC_2 (VSUBFP, "vsubfp", CONST, subv4sf3) -BU_ALTIVEC_2 (VSUBCUW, "vsubcuw", CONST, altivec_vsubcuw) -BU_ALTIVEC_2 (VSUBUBS, "vsububs", CONST, altivec_vsububs) -BU_ALTIVEC_2 (VSUBSBS, "vsubsbs", CONST, altivec_vsubsbs) -BU_ALTIVEC_2 (VSUBUHS, "vsubuhs", CONST, altivec_vsubuhs) -BU_ALTIVEC_2 (VSUBSHS, "vsubshs", CONST, altivec_vsubshs) -BU_ALTIVEC_2 (VSUBUWS, "vsubuws", CONST, altivec_vsubuws) -BU_ALTIVEC_2 (VSUBSWS, "vsubsws", CONST, altivec_vsubsws) -BU_ALTIVEC_2 (VSUM4UBS, "vsum4ubs", CONST, altivec_vsum4ubs) -BU_ALTIVEC_2 (VSUM4SBS, "vsum4sbs", CONST, altivec_vsum4sbs) -BU_ALTIVEC_2 (VSUM4SHS, "vsum4shs", CONST, altivec_vsum4shs) -BU_ALTIVEC_2 (VSUM2SWS, "vsum2sws", CONST, altivec_vsum2sws) -BU_ALTIVEC_2 (VSUMSWS, "vsumsws", CONST, altivec_vsumsws) -BU_ALTIVEC_2 (VSUMSWS_BE, "vsumsws_be", CONST, altivec_vsumsws_direct) -BU_ALTIVEC_2 (VXOR_V16QI_UNS, "vxor_v16qi_uns", CONST, xorv16qi3) -BU_ALTIVEC_2 (VXOR_V16QI, "vxor_v16qi", CONST, xorv16qi3) -BU_ALTIVEC_2 (VXOR_V8HI_UNS, "vxor_v8hi_uns", CONST, xorv8hi3) -BU_ALTIVEC_2 (VXOR_V8HI, "vxor_v8hi", CONST, xorv8hi3) -BU_ALTIVEC_2 (VXOR_V4SI_UNS, "vxor_v4si_uns", CONST, xorv4si3) -BU_ALTIVEC_2 (VXOR_V4SI, "vxor_v4si", CONST, xorv4si3) -BU_ALTIVEC_2 (VXOR_V2DI_UNS, "vxor_v2di_uns", CONST, xorv2di3) -BU_ALTIVEC_2 (VXOR_V2DI, "vxor_v2di", CONST, xorv2di3) -BU_ALTIVEC_2 (VXOR_V4SF, "vxor_v4sf", CONST, xorv4sf3) -BU_ALTIVEC_2 (VXOR_V2DF, "vxor_v2df", CONST, xorv2df3) - -BU_ALTIVEC_2 (COPYSIGN_V4SF, "copysignfp", CONST, vector_copysignv4sf3) - -/* Altivec ABS functions. */ -BU_ALTIVEC_A (ABS_V4SI, "abs_v4si", CONST, absv4si2) -BU_ALTIVEC_A (ABS_V8HI, "abs_v8hi", CONST, absv8hi2) -BU_ALTIVEC_A (ABS_V4SF, "abs_v4sf", CONST, absv4sf2) -BU_ALTIVEC_A (ABS_V16QI, "abs_v16qi", CONST, absv16qi2) -BU_ALTIVEC_A (ABSS_V4SI, "abss_v4si", SAT, altivec_abss_v4si) -BU_ALTIVEC_A (ABSS_V8HI, "abss_v8hi", SAT, altivec_abss_v8hi) -BU_ALTIVEC_A (ABSS_V16QI, "abss_v16qi", SAT, altivec_abss_v16qi) - -/* Altivec NABS functions. */ -BU_ALTIVEC_A (NABS_V2DI, "nabs_v2di", CONST, nabsv2di2) -BU_ALTIVEC_A (NABS_V4SI, "nabs_v4si", CONST, nabsv4si2) -BU_ALTIVEC_A (NABS_V8HI, "nabs_v8hi", CONST, nabsv8hi2) -BU_ALTIVEC_A (NABS_V16QI, "nabs_v16qi", CONST, nabsv16qi2) -BU_ALTIVEC_A (NABS_V4SF, "nabs_v4sf", CONST, vsx_nabsv4sf2) -BU_ALTIVEC_A (NABS_V2DF, "nabs_v2df", CONST, vsx_nabsv2df2) - -/* 1 argument Altivec builtin functions. */ -BU_ALTIVEC_1 (VEXPTEFP, "vexptefp", FP, altivec_vexptefp) -BU_ALTIVEC_1 (VLOGEFP, "vlogefp", FP, altivec_vlogefp) -BU_ALTIVEC_1 (VREFP, "vrefp", FP, rev4sf2) -BU_ALTIVEC_1 (VRFIM, "vrfim", FP, vector_floorv4sf2) -BU_ALTIVEC_1 (VRFIN, "vrfin", FP, altivec_vrfin) -BU_ALTIVEC_1 (VRFIP, "vrfip", FP, vector_ceilv4sf2) -BU_ALTIVEC_1 (VRFIZ, "vrfiz", FP, vector_btruncv4sf2) -BU_ALTIVEC_1 (VRSQRTFP, "vrsqrtfp", FP, rsqrtv4sf2) -BU_ALTIVEC_1 (VRSQRTEFP, "vrsqrtefp", FP, rsqrtev4sf2) -BU_ALTIVEC_1 (VSPLTISB, "vspltisb", CONST, altivec_vspltisb) -BU_ALTIVEC_1 (VSPLTISH, "vspltish", CONST, altivec_vspltish) -BU_ALTIVEC_1 (VSPLTISW, "vspltisw", CONST, altivec_vspltisw) -BU_ALTIVEC_1 (VUPKHSB, "vupkhsb", CONST, altivec_vupkhsb) -BU_ALTIVEC_1 (VUPKHPX, "vupkhpx", CONST, altivec_vupkhpx) -BU_ALTIVEC_1 (VUPKHSH, "vupkhsh", CONST, altivec_vupkhsh) -BU_ALTIVEC_1 (VUPKLSB, "vupklsb", CONST, altivec_vupklsb) -BU_ALTIVEC_1 (VUPKLPX, "vupklpx", CONST, altivec_vupklpx) -BU_ALTIVEC_1 (VUPKLSH, "vupklsh", CONST, altivec_vupklsh) - -BU_ALTIVEC_1 (VREVE_V2DI, "vreve_v2di", CONST, altivec_vrevev2di2) -BU_ALTIVEC_1 (VREVE_V4SI, "vreve_v4si", CONST, altivec_vrevev4si2) -BU_ALTIVEC_1 (VREVE_V8HI, "vreve_v8hi", CONST, altivec_vrevev8hi2) -BU_ALTIVEC_1 (VREVE_V16QI, "vreve_v16qi", CONST, altivec_vrevev16qi2) -BU_ALTIVEC_1 (VREVE_V2DF, "vreve_v2df", CONST, altivec_vrevev2df2) -BU_ALTIVEC_1 (VREVE_V4SF, "vreve_v4sf", CONST, altivec_vrevev4sf2) - -BU_ALTIVEC_1 (FLOAT_V4SI_V4SF, "float_sisf", FP, floatv4siv4sf2) -BU_ALTIVEC_1 (UNSFLOAT_V4SI_V4SF, "uns_float_sisf", FP, floatunsv4siv4sf2) -BU_ALTIVEC_1 (FIX_V4SF_V4SI, "fix_sfsi", FP, fix_truncv4sfv4si2) -BU_ALTIVEC_1 (FIXUNS_V4SF_V4SI, "fixuns_sfsi", FP, fixuns_truncv4sfv4si2) - -/* Altivec predicate functions. */ -BU_ALTIVEC_P (VCMPBFP_P, "vcmpbfp_p", CONST, altivec_vcmpbfp_p) -BU_ALTIVEC_P (VCMPEQFP_P, "vcmpeqfp_p", CONST, vector_eq_v4sf_p) -BU_ALTIVEC_P (VCMPGEFP_P, "vcmpgefp_p", CONST, vector_ge_v4sf_p) -BU_ALTIVEC_P (VCMPGTFP_P, "vcmpgtfp_p", CONST, vector_gt_v4sf_p) -BU_ALTIVEC_P (VCMPEQUW_P, "vcmpequw_p", CONST, vector_eq_v4si_p) -BU_ALTIVEC_P (VCMPGTSW_P, "vcmpgtsw_p", CONST, vector_gt_v4si_p) -BU_ALTIVEC_P (VCMPGTUW_P, "vcmpgtuw_p", CONST, vector_gtu_v4si_p) -BU_ALTIVEC_P (VCMPEQUH_P, "vcmpequh_p", CONST, vector_eq_v8hi_p) -BU_ALTIVEC_P (VCMPGTSH_P, "vcmpgtsh_p", CONST, vector_gt_v8hi_p) -BU_ALTIVEC_P (VCMPGTUH_P, "vcmpgtuh_p", CONST, vector_gtu_v8hi_p) -BU_ALTIVEC_P (VCMPEQUB_P, "vcmpequb_p", CONST, vector_eq_v16qi_p) -BU_ALTIVEC_P (VCMPGTSB_P, "vcmpgtsb_p", CONST, vector_gt_v16qi_p) -BU_ALTIVEC_P (VCMPGTUB_P, "vcmpgtub_p", CONST, vector_gtu_v16qi_p) - -/* AltiVec builtins that are handled as special cases. */ -BU_ALTIVEC_X (MTVSCR, "mtvscr", MISC) -BU_ALTIVEC_X (MFVSCR, "mfvscr", MISC) -BU_ALTIVEC_X (DSSALL, "dssall", MISC) -BU_ALTIVEC_X (DSS, "dss", MISC) -BU_ALTIVEC_X (LVSL, "lvsl", PURE) -BU_ALTIVEC_X (LVSR, "lvsr", PURE) -BU_ALTIVEC_X (LVEBX, "lvebx", PURE) -BU_ALTIVEC_X (LVEHX, "lvehx", PURE) -BU_ALTIVEC_X (LVEWX, "lvewx", PURE) -BU_P10V_AV_X (SE_LXVRBX, "se_lxvrbx", PURE) -BU_P10V_AV_X (SE_LXVRHX, "se_lxvrhx", PURE) -BU_P10V_AV_X (SE_LXVRWX, "se_lxvrwx", PURE) -BU_P10V_AV_X (SE_LXVRDX, "se_lxvrdx", PURE) -BU_P10V_AV_X (ZE_LXVRBX, "ze_lxvrbx", PURE) -BU_P10V_AV_X (ZE_LXVRHX, "ze_lxvrhx", PURE) -BU_P10V_AV_X (ZE_LXVRWX, "ze_lxvrwx", PURE) -BU_P10V_AV_X (ZE_LXVRDX, "ze_lxvrdx", PURE) -BU_P10V_AV_X (TR_STXVRBX, "tr_stxvrbx", MEM) -BU_P10V_AV_X (TR_STXVRHX, "tr_stxvrhx", MEM) -BU_P10V_AV_X (TR_STXVRWX, "tr_stxvrwx", MEM) -BU_P10V_AV_X (TR_STXVRDX, "tr_stxvrdx", MEM) -BU_ALTIVEC_X (LVXL, "lvxl", PURE) -BU_ALTIVEC_X (LVXL_V2DF, "lvxl_v2df", PURE) -BU_ALTIVEC_X (LVXL_V2DI, "lvxl_v2di", PURE) -BU_ALTIVEC_X (LVXL_V4SF, "lvxl_v4sf", PURE) -BU_ALTIVEC_X (LVXL_V4SI, "lvxl_v4si", PURE) -BU_ALTIVEC_X (LVXL_V8HI, "lvxl_v8hi", PURE) -BU_ALTIVEC_X (LVXL_V16QI, "lvxl_v16qi", PURE) -BU_ALTIVEC_X (LVX, "lvx", PURE) -BU_ALTIVEC_X (LVX_V1TI, "lvx_v1ti", PURE) -BU_ALTIVEC_X (LVX_V2DF, "lvx_v2df", PURE) -BU_ALTIVEC_X (LVX_V2DI, "lvx_v2di", PURE) -BU_ALTIVEC_X (LVX_V4SF, "lvx_v4sf", PURE) -BU_ALTIVEC_X (LVX_V4SI, "lvx_v4si", PURE) -BU_ALTIVEC_X (LVX_V8HI, "lvx_v8hi", PURE) -BU_ALTIVEC_X (LVX_V16QI, "lvx_v16qi", PURE) -BU_ALTIVEC_X (STVX, "stvx", MEM) -BU_ALTIVEC_X (STVX_V2DF, "stvx_v2df", MEM) -BU_ALTIVEC_X (STVX_V2DI, "stvx_v2di", MEM) -BU_ALTIVEC_X (STVX_V4SF, "stvx_v4sf", MEM) -BU_ALTIVEC_X (STVX_V4SI, "stvx_v4si", MEM) -BU_ALTIVEC_X (STVX_V8HI, "stvx_v8hi", MEM) -BU_ALTIVEC_X (STVX_V16QI, "stvx_v16qi", MEM) -BU_ALTIVEC_C (LVLX, "lvlx", PURE) -BU_ALTIVEC_C (LVLXL, "lvlxl", PURE) -BU_ALTIVEC_C (LVRX, "lvrx", PURE) -BU_ALTIVEC_C (LVRXL, "lvrxl", PURE) -BU_ALTIVEC_X (STVEBX, "stvebx", MEM) -BU_ALTIVEC_X (STVEHX, "stvehx", MEM) -BU_ALTIVEC_X (STVEWX, "stvewx", MEM) -BU_ALTIVEC_X (STVXL, "stvxl", MEM) -BU_ALTIVEC_X (STVXL_V2DF, "stvxl_v2df", MEM) -BU_ALTIVEC_X (STVXL_V2DI, "stvxl_v2di", MEM) -BU_ALTIVEC_X (STVXL_V4SF, "stvxl_v4sf", MEM) -BU_ALTIVEC_X (STVXL_V4SI, "stvxl_v4si", MEM) -BU_ALTIVEC_X (STVXL_V8HI, "stvxl_v8hi", MEM) -BU_ALTIVEC_X (STVXL_V16QI, "stvxl_v16qi", MEM) -BU_ALTIVEC_C (STVLX, "stvlx", MEM) -BU_ALTIVEC_C (STVLXL, "stvlxl", MEM) -BU_ALTIVEC_C (STVRX, "stvrx", MEM) -BU_ALTIVEC_C (STVRXL, "stvrxl", MEM) -BU_ALTIVEC_X (MASK_FOR_LOAD, "mask_for_load", MISC) -BU_ALTIVEC_X (VEC_INIT_V4SI, "vec_init_v4si", CONST) -BU_ALTIVEC_X (VEC_INIT_V8HI, "vec_init_v8hi", CONST) -BU_ALTIVEC_X (VEC_INIT_V16QI, "vec_init_v16qi", CONST) -BU_ALTIVEC_X (VEC_INIT_V4SF, "vec_init_v4sf", CONST) -BU_ALTIVEC_X (VEC_SET_V4SI, "vec_set_v4si", CONST) -BU_ALTIVEC_X (VEC_SET_V8HI, "vec_set_v8hi", CONST) -BU_ALTIVEC_X (VEC_SET_V16QI, "vec_set_v16qi", CONST) -BU_ALTIVEC_X (VEC_SET_V4SF, "vec_set_v4sf", CONST) -BU_ALTIVEC_X (VEC_EXT_V4SI, "vec_ext_v4si", CONST) -BU_ALTIVEC_X (VEC_EXT_V8HI, "vec_ext_v8hi", CONST) -BU_ALTIVEC_X (VEC_EXT_V16QI, "vec_ext_v16qi", CONST) -BU_ALTIVEC_X (VEC_EXT_V4SF, "vec_ext_v4sf", CONST) - -/* Altivec overloaded builtins. */ -/* For now, don't set the classification for overloaded functions. - The function should be converted to the type specific instruction - before we get to the point about classifying the builtin type. */ - -/* 3 argument Altivec overloaded builtins. */ -BU_ALTIVEC_OVERLOAD_3 (MADD, "madd") -BU_ALTIVEC_OVERLOAD_3 (MADDS, "madds") -BU_ALTIVEC_OVERLOAD_3 (MLADD, "mladd") -BU_ALTIVEC_OVERLOAD_3 (MRADDS, "mradds") -BU_ALTIVEC_OVERLOAD_3 (MSUM, "msum") -BU_ALTIVEC_OVERLOAD_3 (MSUMS, "msums") -BU_ALTIVEC_OVERLOAD_3 (NMSUB, "nmsub") -BU_ALTIVEC_OVERLOAD_3 (PERM, "perm") -BU_ALTIVEC_OVERLOAD_3 (SEL, "sel") -BU_ALTIVEC_OVERLOAD_3 (VMSUMMBM, "vmsummbm") -BU_ALTIVEC_OVERLOAD_3 (VMSUMSHM, "vmsumshm") -BU_ALTIVEC_OVERLOAD_3 (VMSUMSHS, "vmsumshs") -BU_ALTIVEC_OVERLOAD_3 (VMSUMUBM, "vmsumubm") -BU_ALTIVEC_OVERLOAD_3 (VMSUMUHM, "vmsumuhm") -BU_ALTIVEC_OVERLOAD_3 (VMSUMUDM, "vmsumudm") -BU_ALTIVEC_OVERLOAD_3 (VMSUMUHS, "vmsumuhs") - -/* Altivec DST overloaded builtins. */ -BU_ALTIVEC_OVERLOAD_D (DST, "dst") -BU_ALTIVEC_OVERLOAD_D (DSTT, "dstt") -BU_ALTIVEC_OVERLOAD_D (DSTST, "dstst") -BU_ALTIVEC_OVERLOAD_D (DSTSTT, "dststt") - -/* 2 argument Altivec overloaded builtins. */ -BU_ALTIVEC_OVERLOAD_2 (ADD, "add") -BU_ALTIVEC_OVERLOAD_2 (ADDC, "addc") -BU_ALTIVEC_OVERLOAD_2 (ADDS, "adds") -BU_ALTIVEC_OVERLOAD_2 (AND, "and") -BU_ALTIVEC_OVERLOAD_2 (ANDC, "andc") -BU_ALTIVEC_OVERLOAD_2 (AVG, "avg") -BU_ALTIVEC_OVERLOAD_2 (CMPB, "cmpb") -BU_ALTIVEC_OVERLOAD_2 (CMPEQ, "cmpeq") -BU_ALTIVEC_OVERLOAD_2 (CMPGE, "cmpge") -BU_ALTIVEC_OVERLOAD_2 (CMPGT, "cmpgt") -BU_ALTIVEC_OVERLOAD_2 (CMPLE, "cmple") -BU_ALTIVEC_OVERLOAD_2 (CMPLT, "cmplt") -BU_ALTIVEC_OVERLOAD_2 (COPYSIGN, "copysign") -BU_ALTIVEC_OVERLOAD_2 (MAX, "max") -BU_ALTIVEC_OVERLOAD_2 (MERGEH, "mergeh") -BU_ALTIVEC_OVERLOAD_2 (MERGEL, "mergel") -BU_ALTIVEC_OVERLOAD_2 (MIN, "min") -BU_ALTIVEC_OVERLOAD_2 (MULE, "mule") -BU_ALTIVEC_OVERLOAD_2 (MULO, "mulo") -BU_ALTIVEC_OVERLOAD_2 (NOR, "nor") -BU_ALTIVEC_OVERLOAD_2 (OR, "or") -BU_ALTIVEC_OVERLOAD_2 (PACK, "pack") -BU_ALTIVEC_OVERLOAD_2 (PACKPX, "packpx") -BU_ALTIVEC_OVERLOAD_2 (PACKS, "packs") -BU_ALTIVEC_OVERLOAD_2 (PACKSU, "packsu") -BU_ALTIVEC_OVERLOAD_2 (RECIP, "recipdiv") -BU_ALTIVEC_OVERLOAD_2 (RL, "rl") -BU_ALTIVEC_OVERLOAD_2 (SL, "sl") -BU_ALTIVEC_OVERLOAD_2 (SLL, "sll") -BU_ALTIVEC_OVERLOAD_2 (SLO, "slo") -BU_ALTIVEC_OVERLOAD_2 (SR, "sr") -BU_ALTIVEC_OVERLOAD_2 (SRA, "sra") -BU_ALTIVEC_OVERLOAD_2 (SRL, "srl") -BU_ALTIVEC_OVERLOAD_2 (SRO, "sro") -BU_ALTIVEC_OVERLOAD_2 (SUB, "sub") -BU_ALTIVEC_OVERLOAD_2 (SUBC, "subc") -BU_ALTIVEC_OVERLOAD_2 (SUBS, "subs") -BU_ALTIVEC_OVERLOAD_2 (SUM2S, "sum2s") -BU_ALTIVEC_OVERLOAD_2 (SUM4S, "sum4s") -BU_ALTIVEC_OVERLOAD_2 (SUMS, "sums") -BU_ALTIVEC_OVERLOAD_2 (VADDFP, "vaddfp") -BU_ALTIVEC_OVERLOAD_2 (VADDSBS, "vaddsbs") -BU_ALTIVEC_OVERLOAD_2 (VADDSHS, "vaddshs") -BU_ALTIVEC_OVERLOAD_2 (VADDSWS, "vaddsws") -BU_ALTIVEC_OVERLOAD_2 (VADDUBM, "vaddubm") -BU_ALTIVEC_OVERLOAD_2 (VADDUBS, "vaddubs") -BU_ALTIVEC_OVERLOAD_2 (VADDUHM, "vadduhm") -BU_ALTIVEC_OVERLOAD_2 (VADDUHS, "vadduhs") -BU_ALTIVEC_OVERLOAD_2 (VADDUWM, "vadduwm") -BU_ALTIVEC_OVERLOAD_2 (VADDUWS, "vadduws") -BU_ALTIVEC_OVERLOAD_2 (VAVGSB, "vavgsb") -BU_ALTIVEC_OVERLOAD_2 (VAVGSH, "vavgsh") -BU_ALTIVEC_OVERLOAD_2 (VAVGSW, "vavgsw") -BU_ALTIVEC_OVERLOAD_2 (VAVGUB, "vavgub") -BU_ALTIVEC_OVERLOAD_2 (VAVGUH, "vavguh") -BU_ALTIVEC_OVERLOAD_2 (VAVGUW, "vavguw") -BU_ALTIVEC_OVERLOAD_2 (VCMPEQFP, "vcmpeqfp") -BU_ALTIVEC_OVERLOAD_2 (VCMPEQUB, "vcmpequb") -BU_ALTIVEC_OVERLOAD_2 (VCMPEQUH, "vcmpequh") -BU_ALTIVEC_OVERLOAD_2 (VCMPEQUW, "vcmpequw") -BU_ALTIVEC_OVERLOAD_2 (VCMPGTFP, "vcmpgtfp") -BU_ALTIVEC_OVERLOAD_2 (VCMPGTSB, "vcmpgtsb") -BU_ALTIVEC_OVERLOAD_2 (VCMPGTSH, "vcmpgtsh") -BU_ALTIVEC_OVERLOAD_2 (VCMPGTSW, "vcmpgtsw") -BU_ALTIVEC_OVERLOAD_2 (VCMPGTUB, "vcmpgtub") -BU_ALTIVEC_OVERLOAD_2 (VCMPGTUH, "vcmpgtuh") -BU_ALTIVEC_OVERLOAD_2 (VCMPGTUW, "vcmpgtuw") -BU_ALTIVEC_OVERLOAD_2 (VMAXFP, "vmaxfp") -BU_ALTIVEC_OVERLOAD_2 (VMAXSB, "vmaxsb") -BU_ALTIVEC_OVERLOAD_2 (VMAXSH, "vmaxsh") -BU_ALTIVEC_OVERLOAD_2 (VMAXSW, "vmaxsw") -BU_ALTIVEC_OVERLOAD_2 (VMAXUB, "vmaxub") -BU_ALTIVEC_OVERLOAD_2 (VMAXUH, "vmaxuh") -BU_ALTIVEC_OVERLOAD_2 (VMAXUW, "vmaxuw") -BU_ALTIVEC_OVERLOAD_2 (VMINFP, "vminfp") -BU_ALTIVEC_OVERLOAD_2 (VMINSB, "vminsb") -BU_ALTIVEC_OVERLOAD_2 (VMINSH, "vminsh") -BU_ALTIVEC_OVERLOAD_2 (VMINSW, "vminsw") -BU_ALTIVEC_OVERLOAD_2 (VMINUB, "vminub") -BU_ALTIVEC_OVERLOAD_2 (VMINUH, "vminuh") -BU_ALTIVEC_OVERLOAD_2 (VMINUW, "vminuw") -BU_ALTIVEC_OVERLOAD_2 (VMRGHB, "vmrghb") -BU_ALTIVEC_OVERLOAD_2 (VMRGHH, "vmrghh") -BU_ALTIVEC_OVERLOAD_2 (VMRGHW, "vmrghw") -BU_ALTIVEC_OVERLOAD_2 (VMRGLB, "vmrglb") -BU_ALTIVEC_OVERLOAD_2 (VMRGLH, "vmrglh") -BU_ALTIVEC_OVERLOAD_2 (VMRGLW, "vmrglw") -BU_ALTIVEC_OVERLOAD_2 (VMULESB, "vmulesb") -BU_ALTIVEC_OVERLOAD_2 (VMULESH, "vmulesh") -BU_ALTIVEC_OVERLOAD_2 (VMULESW, "vmulesw") -BU_ALTIVEC_OVERLOAD_2 (VMULEUB, "vmuleub") -BU_ALTIVEC_OVERLOAD_2 (VMULEUH, "vmuleuh") -BU_ALTIVEC_OVERLOAD_2 (VMULEUW, "vmuleuw") -BU_ALTIVEC_OVERLOAD_2 (VMULOSB, "vmulosb") -BU_ALTIVEC_OVERLOAD_2 (VMULOSH, "vmulosh") -BU_ALTIVEC_OVERLOAD_2 (VMULOSW, "vmulosw") -BU_ALTIVEC_OVERLOAD_2 (VMULOUB, "vmuloub") -BU_ALTIVEC_OVERLOAD_2 (VMULOUH, "vmulouh") -BU_ALTIVEC_OVERLOAD_2 (VMULOUW, "vmulouw") -BU_ALTIVEC_OVERLOAD_2 (VPKSHSS, "vpkshss") -BU_ALTIVEC_OVERLOAD_2 (VPKSHUS, "vpkshus") -BU_ALTIVEC_OVERLOAD_2 (VPKSWSS, "vpkswss") -BU_ALTIVEC_OVERLOAD_2 (VPKSWUS, "vpkswus") -BU_ALTIVEC_OVERLOAD_2 (VPKUHUM, "vpkuhum") -BU_ALTIVEC_OVERLOAD_2 (VPKUHUS, "vpkuhus") -BU_ALTIVEC_OVERLOAD_2 (VPKUWUM, "vpkuwum") -BU_ALTIVEC_OVERLOAD_2 (VPKUWUS, "vpkuwus") -BU_ALTIVEC_OVERLOAD_2 (VRLB, "vrlb") -BU_ALTIVEC_OVERLOAD_2 (VRLH, "vrlh") -BU_ALTIVEC_OVERLOAD_2 (VRLW, "vrlw") -BU_ALTIVEC_OVERLOAD_2 (VSLB, "vslb") -BU_ALTIVEC_OVERLOAD_2 (VSLH, "vslh") -BU_ALTIVEC_OVERLOAD_2 (VSLW, "vslw") -BU_ALTIVEC_OVERLOAD_2 (VSRAB, "vsrab") -BU_ALTIVEC_OVERLOAD_2 (VSRAH, "vsrah") -BU_ALTIVEC_OVERLOAD_2 (VSRAW, "vsraw") -BU_ALTIVEC_OVERLOAD_2 (VSRB, "vsrb") -BU_ALTIVEC_OVERLOAD_2 (VSRH, "vsrh") -BU_ALTIVEC_OVERLOAD_2 (VSRW, "vsrw") -BU_ALTIVEC_OVERLOAD_2 (VSUBFP, "vsubfp") -BU_ALTIVEC_OVERLOAD_2 (VSUBSBS, "vsubsbs") -BU_ALTIVEC_OVERLOAD_2 (VSUBSHS, "vsubshs") -BU_ALTIVEC_OVERLOAD_2 (VSUBSWS, "vsubsws") -BU_ALTIVEC_OVERLOAD_2 (VSUBUBM, "vsububm") -BU_ALTIVEC_OVERLOAD_2 (VSUBUBS, "vsububs") -BU_ALTIVEC_OVERLOAD_2 (VSUBUHM, "vsubuhm") -BU_ALTIVEC_OVERLOAD_2 (VSUBUHS, "vsubuhs") -BU_ALTIVEC_OVERLOAD_2 (VSUBUWM, "vsubuwm") -BU_ALTIVEC_OVERLOAD_2 (VSUBUWS, "vsubuws") -BU_ALTIVEC_OVERLOAD_2 (VSUM4SBS, "vsum4sbs") -BU_ALTIVEC_OVERLOAD_2 (VSUM4SHS, "vsum4shs") -BU_ALTIVEC_OVERLOAD_2 (VSUM4UBS, "vsum4ubs") -BU_ALTIVEC_OVERLOAD_2 (XOR, "xor") - -/* 1 argument Altivec overloaded functions. */ -BU_ALTIVEC_OVERLOAD_1 (ABS, "abs") -BU_ALTIVEC_OVERLOAD_1 (NABS, "nabs") -BU_ALTIVEC_OVERLOAD_1 (ABSS, "abss") -BU_ALTIVEC_OVERLOAD_1 (CEIL, "ceil") -BU_ALTIVEC_OVERLOAD_1 (EXPTE, "expte") -BU_ALTIVEC_OVERLOAD_1 (FLOOR, "floor") -BU_ALTIVEC_OVERLOAD_1 (LOGE, "loge") -BU_ALTIVEC_OVERLOAD_1 (MTVSCR, "mtvscr") -BU_ALTIVEC_OVERLOAD_1 (NEARBYINT, "nearbyint") -BU_ALTIVEC_OVERLOAD_1 (RE, "re") -BU_ALTIVEC_OVERLOAD_1 (RINT, "rint") -BU_ALTIVEC_OVERLOAD_1 (ROUND, "round") -BU_ALTIVEC_OVERLOAD_1 (RSQRT, "rsqrt") -BU_ALTIVEC_OVERLOAD_1 (RSQRTE, "rsqrte") -BU_ALTIVEC_OVERLOAD_1 (SQRT, "sqrt") -BU_ALTIVEC_OVERLOAD_1 (TRUNC, "trunc") -BU_ALTIVEC_OVERLOAD_1 (UNPACKH, "unpackh") -BU_ALTIVEC_OVERLOAD_1 (UNPACKL, "unpackl") -BU_ALTIVEC_OVERLOAD_1 (VUPKHPX, "vupkhpx") -BU_ALTIVEC_OVERLOAD_1 (VUPKHSB, "vupkhsb") -BU_ALTIVEC_OVERLOAD_1 (VUPKHSH, "vupkhsh") -BU_ALTIVEC_OVERLOAD_1 (VUPKLPX, "vupklpx") -BU_ALTIVEC_OVERLOAD_1 (VUPKLSB, "vupklsb") -BU_ALTIVEC_OVERLOAD_1 (VUPKLSH, "vupklsh") - -BU_ALTIVEC_OVERLOAD_1 (VREVE, "vreve") - -/* Overloaded altivec predicates. */ -BU_ALTIVEC_OVERLOAD_P (VCMPEQ_P, "vcmpeq_p") -BU_ALTIVEC_OVERLOAD_P (VCMPGT_P, "vcmpgt_p") -BU_ALTIVEC_OVERLOAD_P (VCMPGE_P, "vcmpge_p") - -/* Overloaded Altivec builtins that are handled as special cases. */ -BU_ALTIVEC_OVERLOAD_X (ADDE, "adde") -BU_ALTIVEC_OVERLOAD_X (ADDEC, "addec") -BU_ALTIVEC_OVERLOAD_X (CMPNE, "cmpne") -BU_ALTIVEC_OVERLOAD_X (CTF, "ctf") -BU_ALTIVEC_OVERLOAD_X (CTS, "cts") -BU_ALTIVEC_OVERLOAD_X (CTU, "ctu") -BU_ALTIVEC_OVERLOAD_X (EXTRACT, "extract") -BU_ALTIVEC_OVERLOAD_X (INSERT, "insert") -BU_ALTIVEC_OVERLOAD_X (LD, "ld") -BU_ALTIVEC_OVERLOAD_X (LDE, "lde") -BU_ALTIVEC_OVERLOAD_X (LDL, "ldl") -BU_ALTIVEC_OVERLOAD_X (LVEBX, "lvebx") -BU_ALTIVEC_OVERLOAD_X (LVEHX, "lvehx") -BU_ALTIVEC_OVERLOAD_X (LVEWX, "lvewx") -BU_P10V_OVERLOAD_X (SE_LXVRX, "se_lxvrx") -BU_P10V_OVERLOAD_X (ZE_LXVRX, "ze_lxvrx") -BU_P10V_OVERLOAD_X (TR_STXVRX, "tr_stxvrx") -BU_ALTIVEC_OVERLOAD_X (LVLX, "lvlx") -BU_ALTIVEC_OVERLOAD_X (LVLXL, "lvlxl") -BU_ALTIVEC_OVERLOAD_X (LVRX, "lvrx") -BU_ALTIVEC_OVERLOAD_X (LVRXL, "lvrxl") -BU_ALTIVEC_OVERLOAD_X (LVSL, "lvsl") -BU_ALTIVEC_OVERLOAD_X (LVSR, "lvsr") -BU_ALTIVEC_OVERLOAD_X (MUL, "mul") -BU_ALTIVEC_OVERLOAD_X (PROMOTE, "promote") -BU_ALTIVEC_OVERLOAD_X (SLD, "sld") -BU_ALTIVEC_OVERLOAD_X (SLDW, "sldw") -BU_ALTIVEC_OVERLOAD_X (SPLAT, "splat") -BU_ALTIVEC_OVERLOAD_X (SPLATS, "splats") -BU_ALTIVEC_OVERLOAD_X (ST, "st") -BU_ALTIVEC_OVERLOAD_X (STE, "ste") -BU_ALTIVEC_OVERLOAD_X (STEP, "step") -BU_ALTIVEC_OVERLOAD_X (STL, "stl") -BU_ALTIVEC_OVERLOAD_X (STVEBX, "stvebx") -BU_ALTIVEC_OVERLOAD_X (STVEHX, "stvehx") -BU_ALTIVEC_OVERLOAD_X (STVEWX, "stvewx") -BU_ALTIVEC_OVERLOAD_X (STVLX, "stvlx") -BU_ALTIVEC_OVERLOAD_X (STVLXL, "stvlxl") -BU_ALTIVEC_OVERLOAD_X (STVRX, "stvrx") -BU_ALTIVEC_OVERLOAD_X (STVRXL, "stvrxl") -BU_ALTIVEC_OVERLOAD_X (SUBE, "sube") -BU_ALTIVEC_OVERLOAD_X (SUBEC, "subec") -BU_ALTIVEC_OVERLOAD_X (VCFSX, "vcfsx") -BU_ALTIVEC_OVERLOAD_X (VCFUX, "vcfux") -BU_ALTIVEC_OVERLOAD_X (VSPLTB, "vspltb") -BU_ALTIVEC_OVERLOAD_X (VSPLTH, "vsplth") -BU_ALTIVEC_OVERLOAD_X (VSPLTW, "vspltw") - -/* 3 argument VSX builtins. */ -BU_VSX_3 (XVMADDSP, "xvmaddsp", CONST, fmav4sf4) -BU_VSX_3 (XVMSUBSP, "xvmsubsp", CONST, fmsv4sf4) -BU_VSX_3 (XVNMADDSP, "xvnmaddsp", CONST, nfmav4sf4) -BU_VSX_3 (XVNMSUBSP, "xvnmsubsp", CONST, nfmsv4sf4) - -BU_VSX_3 (XVMADDDP, "xvmadddp", CONST, fmav2df4) -BU_VSX_3 (XVMSUBDP, "xvmsubdp", CONST, fmsv2df4) -BU_VSX_3 (XVNMADDDP, "xvnmadddp", CONST, nfmav2df4) -BU_VSX_3 (XVNMSUBDP, "xvnmsubdp", CONST, nfmsv2df4) - -BU_VSX_3 (XXSEL_1TI, "xxsel_1ti", CONST, vector_select_v1ti) -BU_VSX_3 (XXSEL_2DI, "xxsel_2di", CONST, vector_select_v2di) -BU_VSX_3 (XXSEL_2DF, "xxsel_2df", CONST, vector_select_v2df) -BU_VSX_3 (XXSEL_4SF, "xxsel_4sf", CONST, vector_select_v4sf) -BU_VSX_3 (XXSEL_4SI, "xxsel_4si", CONST, vector_select_v4si) -BU_VSX_3 (XXSEL_8HI, "xxsel_8hi", CONST, vector_select_v8hi) -BU_VSX_3 (XXSEL_16QI, "xxsel_16qi", CONST, vector_select_v16qi) -BU_VSX_3 (XXSEL_1TI_UNS, "xxsel_1ti_uns", CONST, vector_select_v1ti_uns) -BU_VSX_3 (XXSEL_2DI_UNS, "xxsel_2di_uns", CONST, vector_select_v2di_uns) -BU_VSX_3 (XXSEL_4SI_UNS, "xxsel_4si_uns", CONST, vector_select_v4si_uns) -BU_VSX_3 (XXSEL_8HI_UNS, "xxsel_8hi_uns", CONST, vector_select_v8hi_uns) -BU_VSX_3 (XXSEL_16QI_UNS, "xxsel_16qi_uns", CONST, vector_select_v16qi_uns) - -BU_VSX_3 (VPERM_1TI, "vperm_1ti", CONST, altivec_vperm_v1ti) -BU_VSX_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di) -BU_VSX_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df) -BU_VSX_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf) -BU_VSX_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si) -BU_VSX_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi) -BU_VSX_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi) -BU_VSX_3 (VPERM_1TI_UNS, "vperm_1ti_uns", CONST, altivec_vperm_v1ti_uns) -BU_VSX_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns) -BU_VSX_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns) -BU_VSX_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns) -BU_VSX_3 (VPERM_16QI_UNS, "vperm_16qi_uns", CONST, altivec_vperm_v16qi_uns) - -BU_VSX_3 (XXPERMDI_1TI, "xxpermdi_1ti", CONST, vsx_xxpermdi_v1ti) -BU_VSX_3 (XXPERMDI_2DF, "xxpermdi_2df", CONST, vsx_xxpermdi_v2df) -BU_VSX_3 (XXPERMDI_2DI, "xxpermdi_2di", CONST, vsx_xxpermdi_v2di) -BU_VSX_3 (XXPERMDI_4SF, "xxpermdi_4sf", CONST, vsx_xxpermdi_v4sf) -BU_VSX_3 (XXPERMDI_4SI, "xxpermdi_4si", CONST, vsx_xxpermdi_v4si) -BU_VSX_3 (XXPERMDI_8HI, "xxpermdi_8hi", CONST, vsx_xxpermdi_v8hi) -BU_VSX_3 (XXPERMDI_16QI, "xxpermdi_16qi", CONST, vsx_xxpermdi_v16qi) -BU_VSX_3 (SET_1TI, "set_1ti", CONST, vsx_set_v1ti) -BU_VSX_3 (SET_2DF, "set_2df", CONST, vsx_set_v2df) -BU_VSX_3 (SET_2DI, "set_2di", CONST, vsx_set_v2di) -BU_VSX_3 (XXSLDWI_2DI, "xxsldwi_2di", CONST, vsx_xxsldwi_v2di) -BU_VSX_3 (XXSLDWI_2DF, "xxsldwi_2df", CONST, vsx_xxsldwi_v2df) -BU_VSX_3 (XXSLDWI_4SF, "xxsldwi_4sf", CONST, vsx_xxsldwi_v4sf) -BU_VSX_3 (XXSLDWI_4SI, "xxsldwi_4si", CONST, vsx_xxsldwi_v4si) -BU_VSX_3 (XXSLDWI_8HI, "xxsldwi_8hi", CONST, vsx_xxsldwi_v8hi) -BU_VSX_3 (XXSLDWI_16QI, "xxsldwi_16qi", CONST, vsx_xxsldwi_v16qi) - -/* 2 argument VSX builtins. */ -BU_VSX_2 (XVADDDP, "xvadddp", FP, addv2df3) -BU_VSX_2 (XVSUBDP, "xvsubdp", FP, subv2df3) -BU_VSX_2 (XVMULDP, "xvmuldp", FP, mulv2df3) -BU_VSX_2 (XVDIVDP, "xvdivdp", FP, divv2df3) -BU_VSX_2 (RECIP_V2DF, "xvrecipdivdp", FP, recipv2df3) -BU_VSX_2 (XVMINDP, "xvmindp", CONST, sminv2df3) -BU_VSX_2 (XVMAXDP, "xvmaxdp", CONST, smaxv2df3) -BU_VSX_2 (XVTDIVDP_FE, "xvtdivdp_fe", CONST, vsx_tdivv2df3_fe) -BU_VSX_2 (XVTDIVDP_FG, "xvtdivdp_fg", CONST, vsx_tdivv2df3_fg) -BU_VSX_2 (XVCMPEQDP, "xvcmpeqdp", CONST, vector_eqv2df) -BU_VSX_2 (XVCMPGTDP, "xvcmpgtdp", CONST, vector_gtv2df) -BU_VSX_2 (XVCMPGEDP, "xvcmpgedp", CONST, vector_gev2df) - -BU_VSX_2 (XVADDSP, "xvaddsp", FP, addv4sf3) -BU_VSX_2 (XVSUBSP, "xvsubsp", FP, subv4sf3) -BU_VSX_2 (XVMULSP, "xvmulsp", FP, mulv4sf3) -BU_VSX_2 (XVDIVSP, "xvdivsp", FP, divv4sf3) -BU_VSX_2 (RECIP_V4SF, "xvrecipdivsp", FP, recipv4sf3) -BU_VSX_2 (XVMINSP, "xvminsp", CONST, sminv4sf3) -BU_VSX_2 (XVMAXSP, "xvmaxsp", CONST, smaxv4sf3) -BU_VSX_2 (XVTDIVSP_FE, "xvtdivsp_fe", CONST, vsx_tdivv4sf3_fe) -BU_VSX_2 (XVTDIVSP_FG, "xvtdivsp_fg", CONST, vsx_tdivv4sf3_fg) -BU_VSX_2 (XVCMPEQSP, "xvcmpeqsp", CONST, vector_eqv4sf) -BU_VSX_2 (XVCMPGTSP, "xvcmpgtsp", CONST, vector_gtv4sf) -BU_VSX_2 (XVCMPGESP, "xvcmpgesp", CONST, vector_gev4sf) - -BU_VSX_2 (XSMINDP, "xsmindp", CONST, smindf3) -BU_VSX_2 (XSMAXDP, "xsmaxdp", CONST, smaxdf3) -BU_VSX_2 (XSTDIVDP_FE, "xstdivdp_fe", CONST, vsx_tdivdf3_fe) -BU_VSX_2 (XSTDIVDP_FG, "xstdivdp_fg", CONST, vsx_tdivdf3_fg) -BU_VSX_2 (CPSGNDP, "cpsgndp", CONST, vector_copysignv2df3) -BU_VSX_2 (CPSGNSP, "cpsgnsp", CONST, vector_copysignv4sf3) - -BU_VSX_2 (CONCAT_2DF, "concat_2df", CONST, vsx_concat_v2df) -BU_VSX_2 (CONCAT_2DI, "concat_2di", CONST, vsx_concat_v2di) -BU_VSX_2 (SPLAT_2DF, "splat_2df", CONST, vsx_splat_v2df) -BU_VSX_2 (SPLAT_2DI, "splat_2di", CONST, vsx_splat_v2di) -BU_VSX_2 (XXMRGHW_4SF, "xxmrghw", CONST, vsx_xxmrghw_v4sf) -BU_VSX_2 (XXMRGHW_4SI, "xxmrghw_4si", CONST, vsx_xxmrghw_v4si) -BU_VSX_2 (XXMRGLW_4SF, "xxmrglw", CONST, vsx_xxmrglw_v4sf) -BU_VSX_2 (XXMRGLW_4SI, "xxmrglw_4si", CONST, vsx_xxmrglw_v4si) -BU_VSX_2 (VEC_MERGEL_V2DF, "mergel_2df", CONST, vsx_mergel_v2df) -BU_VSX_2 (VEC_MERGEL_V2DI, "mergel_2di", CONST, vsx_mergel_v2di) -BU_VSX_2 (VEC_MERGEH_V2DF, "mergeh_2df", CONST, vsx_mergeh_v2df) -BU_VSX_2 (VEC_MERGEH_V2DI, "mergeh_2di", CONST, vsx_mergeh_v2di) -BU_VSX_2 (XXSPLTD_V2DF, "xxspltd_2df", CONST, vsx_xxspltd_v2df) -BU_VSX_2 (XXSPLTD_V2DI, "xxspltd_2di", CONST, vsx_xxspltd_v2di) -BU_VSX_2 (DIV_V2DI, "div_2di", CONST, vsx_div_v2di) -BU_VSX_2 (UDIV_V2DI, "udiv_2di", CONST, vsx_udiv_v2di) -BU_VSX_2 (MUL_V2DI, "mul_2di", CONST, vsx_mul_v2di) - -BU_VSX_2 (XVCVSXDDP_SCALE, "xvcvsxddp_scale", CONST, vsx_xvcvsxddp_scale) -BU_VSX_2 (XVCVUXDDP_SCALE, "xvcvuxddp_scale", CONST, vsx_xvcvuxddp_scale) -BU_VSX_2 (XVCVDPSXDS_SCALE, "xvcvdpsxds_scale", CONST, vsx_xvcvdpsxds_scale) -BU_VSX_2 (XVCVDPUXDS_SCALE, "xvcvdpuxds_scale", CONST, vsx_xvcvdpuxds_scale) - -BU_VSX_2 (CMPGE_16QI, "cmpge_16qi", CONST, vector_nltv16qi) -BU_VSX_2 (CMPGE_8HI, "cmpge_8hi", CONST, vector_nltv8hi) -BU_VSX_2 (CMPGE_4SI, "cmpge_4si", CONST, vector_nltv4si) -BU_VSX_2 (CMPGE_2DI, "cmpge_2di", CONST, vector_nltv2di) -BU_VSX_2 (CMPGE_U16QI, "cmpge_u16qi", CONST, vector_nltuv16qi) -BU_VSX_2 (CMPGE_U8HI, "cmpge_u8hi", CONST, vector_nltuv8hi) -BU_VSX_2 (CMPGE_U4SI, "cmpge_u4si", CONST, vector_nltuv4si) -BU_VSX_2 (CMPGE_U2DI, "cmpge_u2di", CONST, vector_nltuv2di) - -BU_VSX_2 (CMPLE_16QI, "cmple_16qi", CONST, vector_ngtv16qi) -BU_VSX_2 (CMPLE_8HI, "cmple_8hi", CONST, vector_ngtv8hi) -BU_VSX_2 (CMPLE_4SI, "cmple_4si", CONST, vector_ngtv4si) -BU_VSX_2 (CMPLE_2DI, "cmple_2di", CONST, vector_ngtv2di) -BU_VSX_2 (CMPLE_U16QI, "cmple_u16qi", CONST, vector_ngtuv16qi) -BU_VSX_2 (CMPLE_U8HI, "cmple_u8hi", CONST, vector_ngtuv8hi) -BU_VSX_2 (CMPLE_U4SI, "cmple_u4si", CONST, vector_ngtuv4si) -BU_VSX_2 (CMPLE_U2DI, "cmple_u2di", CONST, vector_ngtuv2di) - -/* VSX abs builtin functions. */ -BU_VSX_A (XVABSDP, "xvabsdp", CONST, absv2df2) -BU_VSX_A (XVNABSDP, "xvnabsdp", CONST, vsx_nabsv2df2) -BU_VSX_A (XVABSSP, "xvabssp", CONST, absv4sf2) -BU_VSX_A (XVNABSSP, "xvnabssp", CONST, vsx_nabsv4sf2) - -/* 1 argument VSX builtin functions. */ -BU_VSX_1 (XVNEGDP, "xvnegdp", CONST, negv2df2) -BU_VSX_1 (XVSQRTDP, "xvsqrtdp", CONST, sqrtv2df2) -BU_VSX_1 (RSQRT_2DF, "xvrsqrtdp", CONST, rsqrtv2df2) -BU_VSX_1 (XVRSQRTEDP, "xvrsqrtedp", CONST, rsqrtev2df2) -BU_VSX_1 (XVTSQRTDP_FE, "xvtsqrtdp_fe", CONST, vsx_tsqrtv2df2_fe) -BU_VSX_1 (XVTSQRTDP_FG, "xvtsqrtdp_fg", CONST, vsx_tsqrtv2df2_fg) -BU_VSX_1 (XVREDP, "xvredp", CONST, vsx_frev2df2) - -BU_VSX_1 (XVNEGSP, "xvnegsp", CONST, negv4sf2) -BU_VSX_1 (XVSQRTSP, "xvsqrtsp", CONST, sqrtv4sf2) -BU_VSX_1 (RSQRT_4SF, "xvrsqrtsp", CONST, rsqrtv4sf2) -BU_VSX_1 (XVRSQRTESP, "xvrsqrtesp", CONST, rsqrtev4sf2) -BU_VSX_1 (XVTSQRTSP_FE, "xvtsqrtsp_fe", CONST, vsx_tsqrtv4sf2_fe) -BU_VSX_1 (XVTSQRTSP_FG, "xvtsqrtsp_fg", CONST, vsx_tsqrtv4sf2_fg) -BU_VSX_1 (XVRESP, "xvresp", CONST, vsx_frev4sf2) - -BU_VSX_1 (XSCVDPSP, "xscvdpsp", CONST, vsx_xscvdpsp) -BU_VSX_1 (XSCVSPDP, "xscvspdp", CONST, vsx_xscvspdp) -BU_VSX_1 (XVCVDPSP, "xvcvdpsp", CONST, vsx_xvcvdpsp) -BU_VSX_1 (XVCVSPDP, "xvcvspdp", CONST, vsx_xvcvspdp) -BU_VSX_1 (XSTSQRTDP_FE, "xstsqrtdp_fe", CONST, vsx_tsqrtdf2_fe) -BU_VSX_1 (XSTSQRTDP_FG, "xstsqrtdp_fg", CONST, vsx_tsqrtdf2_fg) - -BU_VSX_1 (XVCVDPSXDS, "xvcvdpsxds", CONST, vsx_fix_truncv2dfv2di2) -BU_VSX_1 (XVCVDPUXDS, "xvcvdpuxds", CONST, vsx_fixuns_truncv2dfv2di2) -BU_VSX_1 (XVCVDPUXDS_UNS, "xvcvdpuxds_uns", CONST, vsx_fixuns_truncv2dfv2di2) -BU_VSX_1 (XVCVSXDDP, "xvcvsxddp", CONST, vsx_floatv2div2df2) -BU_VSX_1 (XVCVUXDDP, "xvcvuxddp", CONST, vsx_floatunsv2div2df2) -BU_VSX_1 (XVCVUXDDP_UNS, "xvcvuxddp_uns", CONST, vsx_floatunsv2div2df2) - -BU_VSX_1 (XVCVSPSXWS, "xvcvspsxws", CONST, vsx_fix_truncv4sfv4si2) -BU_VSX_1 (XVCVSPUXWS, "xvcvspuxws", CONST, vsx_fixuns_truncv4sfv4si2) -BU_VSX_1 (XVCVSXWSP, "xvcvsxwsp", CONST, vsx_floatv4siv4sf2) -BU_VSX_1 (XVCVUXWSP, "xvcvuxwsp", CONST, vsx_floatunsv4siv4sf2) - -BU_VSX_1 (XVCVDPSXWS, "xvcvdpsxws", CONST, vsx_xvcvdpsxws) -BU_VSX_1 (XVCVDPUXWS, "xvcvdpuxws", CONST, vsx_xvcvdpuxws) -BU_VSX_1 (XVCVSXWDP, "xvcvsxwdp", CONST, vsx_xvcvsxwdp) -BU_VSX_1 (XVCVUXWDP, "xvcvuxwdp", CONST, vsx_xvcvuxwdp) -BU_VSX_1 (XVRDPI, "xvrdpi", CONST, vsx_xvrdpi) -BU_VSX_1 (XVRDPIC, "xvrdpic", CONST, vsx_xvrdpic) -BU_VSX_1 (XVRDPIM, "xvrdpim", CONST, vsx_floorv2df2) -BU_VSX_1 (XVRDPIP, "xvrdpip", CONST, vsx_ceilv2df2) -BU_VSX_1 (XVRDPIZ, "xvrdpiz", CONST, vsx_btruncv2df2) - -BU_VSX_1 (XVCVSPSXDS, "xvcvspsxds", CONST, vsx_xvcvspsxds) -BU_VSX_1 (XVCVSPUXDS, "xvcvspuxds", CONST, vsx_xvcvspuxds) -BU_VSX_1 (XVCVSXDSP, "xvcvsxdsp", CONST, vsx_xvcvsxdsp) -BU_VSX_1 (XVCVUXDSP, "xvcvuxdsp", CONST, vsx_xvcvuxdsp) - -BU_VSX_1 (XVCVSXWSP_V4SF, "vsx_xvcvsxwsp", CONST, vsx_xvcvsxwsp) -BU_VSX_1 (XVCVUXWSP_V4SF, "vsx_xvcvuxwsp", CONST, vsx_xvcvuxwsp) -BU_VSX_1 (FLOATE_V2DI, "floate_v2di", CONST, floatev2di) -BU_VSX_1 (FLOATE_V2DF, "floate_v2df", CONST, floatev2df) -BU_VSX_1 (FLOATO_V2DI, "floato_v2di", CONST, floatov2di) -BU_VSX_1 (FLOATO_V2DF, "floato_v2df", CONST, floatov2df) -BU_VSX_1 (UNS_FLOATO_V2DI, "uns_floato_v2di", CONST, unsfloatov2di) -BU_VSX_1 (UNS_FLOATE_V2DI, "uns_floate_v2di", CONST, unsfloatev2di) - -BU_VSX_1 (XVRSPI, "xvrspi", CONST, vsx_xvrspi) -BU_VSX_1 (XVRSPIC, "xvrspic", CONST, vsx_xvrspic) -BU_VSX_1 (XVRSPIM, "xvrspim", CONST, vsx_floorv4sf2) -BU_VSX_1 (XVRSPIP, "xvrspip", CONST, vsx_ceilv4sf2) -BU_VSX_1 (XVRSPIZ, "xvrspiz", CONST, vsx_btruncv4sf2) - -BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi) -BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic) -BU_VSX_1 (XSRDPIM, "xsrdpim", CONST, floordf2) -BU_VSX_1 (XSRDPIP, "xsrdpip", CONST, ceildf2) -BU_VSX_1 (XSRDPIZ, "xsrdpiz", CONST, btruncdf2) - -BU_VSX_1 (DOUBLEE_V4SI, "doublee_v4si", CONST, doubleev4si2) -BU_VSX_1 (DOUBLEE_V4SF, "doublee_v4sf", CONST, doubleev4sf2) -BU_VSX_1 (UNS_DOUBLEE_V4SI, "uns_doublee_v4si", CONST, unsdoubleev4si2) -BU_VSX_1 (DOUBLEO_V4SI, "doubleo_v4si", CONST, doubleov4si2) -BU_VSX_1 (DOUBLEO_V4SF, "doubleo_v4sf", CONST, doubleov4sf2) -BU_VSX_1 (UNS_DOUBLEO_V4SI, "uns_doubleo_v4si", CONST, unsdoubleov4si2) -BU_VSX_1 (DOUBLEH_V4SI, "doubleh_v4si", CONST, doublehv4si2) -BU_VSX_1 (DOUBLEH_V4SF, "doubleh_v4sf", CONST, doublehv4sf2) -BU_VSX_1 (UNS_DOUBLEH_V4SI, "uns_doubleh_v4si", CONST, unsdoublehv4si2) -BU_VSX_1 (DOUBLEL_V4SI, "doublel_v4si", CONST, doublelv4si2) -BU_VSX_1 (DOUBLEL_V4SF, "doublel_v4sf", CONST, doublelv4sf2) -BU_VSX_1 (UNS_DOUBLEL_V4SI, "uns_doublel_v4si", CONST, unsdoublelv4si2) - -BU_VSX_1 (VEC_VSIGNED_V4SF, "vsigned_v4sf", CONST, vsx_xvcvspsxws) -BU_VSX_1 (VEC_VSIGNED_V2DF, "vsigned_v2df", CONST, vsx_xvcvdpsxds) -BU_VSX_1 (VEC_VSIGNEDE_V2DF, "vsignede_v2df", CONST, vsignede_v2df) -BU_VSX_1 (VEC_VSIGNEDO_V2DF, "vsignedo_v2df", CONST, vsignedo_v2df) - -BU_VSX_1 (VEC_VUNSIGNED_V4SF, "vunsigned_v4sf", CONST, vsx_xvcvspsxws) -BU_VSX_1 (VEC_VUNSIGNED_V2DF, "vunsigned_v2df", CONST, vsx_xvcvdpsxds) -BU_VSX_1 (VEC_VUNSIGNEDE_V2DF, "vunsignede_v2df", CONST, vunsignede_v2df) -BU_VSX_1 (VEC_VUNSIGNEDO_V2DF, "vunsignedo_v2df", CONST, vunsignedo_v2df) - -/* VSX predicate functions. */ -BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p) -BU_VSX_P (XVCMPGESP_P, "xvcmpgesp_p", CONST, vector_ge_v4sf_p) -BU_VSX_P (XVCMPGTSP_P, "xvcmpgtsp_p", CONST, vector_gt_v4sf_p) -BU_VSX_P (XVCMPEQDP_P, "xvcmpeqdp_p", CONST, vector_eq_v2df_p) -BU_VSX_P (XVCMPGEDP_P, "xvcmpgedp_p", CONST, vector_ge_v2df_p) -BU_VSX_P (XVCMPGTDP_P, "xvcmpgtdp_p", CONST, vector_gt_v2df_p) - -/* VSX builtins that are handled as special cases. */ -BU_VSX_X (LXSDX, "lxsdx", PURE) -BU_VSX_X (LXVD2X_V1TI, "lxvd2x_v1ti", PURE) -BU_VSX_X (LXVD2X_V2DF, "lxvd2x_v2df", PURE) -BU_VSX_X (LXVD2X_V2DI, "lxvd2x_v2di", PURE) -BU_VSX_X (LXVDSX, "lxvdsx", PURE) -BU_VSX_X (LXVW4X_V4SF, "lxvw4x_v4sf", PURE) -BU_VSX_X (LXVW4X_V4SI, "lxvw4x_v4si", PURE) -BU_VSX_X (LXVW4X_V8HI, "lxvw4x_v8hi", PURE) -BU_VSX_X (LXVW4X_V16QI, "lxvw4x_v16qi", PURE) -BU_VSX_X (STXSDX, "stxsdx", MEM) -BU_VSX_X (STXVD2X_V1TI, "stxvd2x_v1ti", MEM) -BU_VSX_X (STXVD2X_V2DF, "stxvd2x_v2df", MEM) -BU_VSX_X (STXVD2X_V2DI, "stxvd2x_v2di", MEM) -BU_VSX_X (STXVW4X_V4SF, "stxvw4x_v4sf", MEM) -BU_VSX_X (STXVW4X_V4SI, "stxvw4x_v4si", MEM) -BU_VSX_X (STXVW4X_V8HI, "stxvw4x_v8hi", MEM) -BU_VSX_X (STXVW4X_V16QI, "stxvw4x_v16qi", MEM) -BU_VSX_X (LD_ELEMREV_V1TI, "ld_elemrev_v1ti", PURE) -BU_VSX_X (LD_ELEMREV_V2DF, "ld_elemrev_v2df", PURE) -BU_VSX_X (LD_ELEMREV_V2DI, "ld_elemrev_v2di", PURE) -BU_VSX_X (LD_ELEMREV_V4SF, "ld_elemrev_v4sf", PURE) -BU_VSX_X (LD_ELEMREV_V4SI, "ld_elemrev_v4si", PURE) -BU_VSX_X (LD_ELEMREV_V8HI, "ld_elemrev_v8hi", PURE) -BU_VSX_X (LD_ELEMREV_V16QI, "ld_elemrev_v16qi", PURE) -BU_VSX_X (ST_ELEMREV_V1TI, "st_elemrev_v1ti", MEM) -BU_VSX_X (ST_ELEMREV_V2DF, "st_elemrev_v2df", MEM) -BU_VSX_X (ST_ELEMREV_V2DI, "st_elemrev_v2di", MEM) -BU_VSX_X (ST_ELEMREV_V4SF, "st_elemrev_v4sf", MEM) -BU_VSX_X (ST_ELEMREV_V4SI, "st_elemrev_v4si", MEM) -BU_VSX_X (ST_ELEMREV_V8HI, "st_elemrev_v8hi", MEM) -BU_VSX_X (ST_ELEMREV_V16QI, "st_elemrev_v16qi", MEM) -BU_VSX_X (XSABSDP, "xsabsdp", CONST) -BU_VSX_X (XSADDDP, "xsadddp", FP) -BU_VSX_X (XSCMPODP, "xscmpodp", FP) -BU_VSX_X (XSCMPUDP, "xscmpudp", FP) -BU_VSX_X (XSCVDPSXDS, "xscvdpsxds", FP) -BU_VSX_X (XSCVDPSXWS, "xscvdpsxws", FP) -BU_VSX_X (XSCVDPUXDS, "xscvdpuxds", FP) -BU_VSX_X (XSCVDPUXWS, "xscvdpuxws", FP) -BU_VSX_X (XSCVSXDDP, "xscvsxddp", FP) -BU_VSX_X (XSCVUXDDP, "xscvuxddp", FP) -BU_VSX_X (XSDIVDP, "xsdivdp", FP) -BU_VSX_X (XSMADDADP, "xsmaddadp", FP) -BU_VSX_X (XSMADDMDP, "xsmaddmdp", FP) -BU_VSX_X (XSMOVDP, "xsmovdp", FP) -BU_VSX_X (XSMSUBADP, "xsmsubadp", FP) -BU_VSX_X (XSMSUBMDP, "xsmsubmdp", FP) -BU_VSX_X (XSMULDP, "xsmuldp", FP) -BU_VSX_X (XSNABSDP, "xsnabsdp", FP) -BU_VSX_X (XSNEGDP, "xsnegdp", FP) -BU_VSX_X (XSNMADDADP, "xsnmaddadp", FP) -BU_VSX_X (XSNMADDMDP, "xsnmaddmdp", FP) -BU_VSX_X (XSNMSUBADP, "xsnmsubadp", FP) -BU_VSX_X (XSNMSUBMDP, "xsnmsubmdp", FP) -BU_VSX_X (XSSUBDP, "xssubdp", FP) -BU_VSX_X (VEC_INIT_V1TI, "vec_init_v1ti", CONST) -BU_VSX_X (VEC_INIT_V2DF, "vec_init_v2df", CONST) -BU_VSX_X (VEC_INIT_V2DI, "vec_init_v2di", CONST) -BU_VSX_X (VEC_SET_V1TI, "vec_set_v1ti", CONST) -BU_VSX_X (VEC_SET_V2DF, "vec_set_v2df", CONST) -BU_VSX_X (VEC_SET_V2DI, "vec_set_v2di", CONST) -BU_VSX_X (VEC_EXT_V1TI, "vec_ext_v1ti", CONST) -BU_VSX_X (VEC_EXT_V2DF, "vec_ext_v2df", CONST) -BU_VSX_X (VEC_EXT_V2DI, "vec_ext_v2di", CONST) - -/* VSX overloaded builtins, add the overloaded functions not present in - Altivec. */ - -/* 3 argument VSX overloaded builtins. */ -BU_VSX_OVERLOAD_3 (MSUB, "msub") -BU_VSX_OVERLOAD_3 (NMADD, "nmadd") -BU_VSX_OVERLOAD_3V (XXPERMDI, "xxpermdi") -BU_VSX_OVERLOAD_3V (XXSLDWI, "xxsldwi") - -/* 2 argument VSX overloaded builtin functions. */ -BU_VSX_OVERLOAD_2 (DIV, "div") -BU_VSX_OVERLOAD_2 (XXMRGHW, "xxmrghw") -BU_VSX_OVERLOAD_2 (XXMRGLW, "xxmrglw") -BU_VSX_OVERLOAD_2 (XXSPLTD, "xxspltd") -BU_VSX_OVERLOAD_2 (XXSPLTW, "xxspltw") - -/* 1 argument VSX overloaded builtin functions. */ -BU_VSX_OVERLOAD_1 (DOUBLE, "double") -BU_VSX_OVERLOAD_1 (DOUBLEE, "doublee") -BU_VSX_OVERLOAD_1 (UNS_DOUBLEE, "uns_doublee") -BU_VSX_OVERLOAD_1 (DOUBLEO, "doubleo") -BU_VSX_OVERLOAD_1 (UNS_DOUBLEO, "uns_doubleo") -BU_VSX_OVERLOAD_1 (DOUBLEH, "doubleh") -BU_VSX_OVERLOAD_1 (UNS_DOUBLEH, "uns_doubleh") -BU_VSX_OVERLOAD_1 (DOUBLEL, "doublel") -BU_VSX_OVERLOAD_1 (UNS_DOUBLEL, "uns_doublel") -BU_VSX_OVERLOAD_1 (FLOAT, "float") -BU_VSX_OVERLOAD_1 (FLOATE, "floate") -BU_VSX_OVERLOAD_1 (FLOATO, "floato") - -BU_VSX_OVERLOAD_1 (VSIGNED, "vsigned") -BU_VSX_OVERLOAD_1 (VSIGNEDE, "vsignede") -BU_VSX_OVERLOAD_1 (VSIGNEDO, "vsignedo") - -BU_VSX_OVERLOAD_1 (VUNSIGNED, "vunsigned") -BU_VSX_OVERLOAD_1 (VUNSIGNEDE, "vunsignede") -BU_VSX_OVERLOAD_1 (VUNSIGNEDO, "vunsignedo") - -/* VSX builtins that are handled as special cases. */ - - -/* NON-TRADITIONAL BEHAVIOR HERE: Besides introducing the - __builtin_vec_ld and __builtin_vec_st built-in functions, - the VSX_BUILTIN_VEC_LD and VSX_BUILTIN_VEC_ST symbolic constants - introduced below are also affiliated with the __builtin_vec_vsx_ld - and __builtin_vec_vsx_st functions respectively. This unnatural - binding is formed with explicit calls to the def_builtin function - found in rs6000.c. */ -BU_VSX_OVERLOAD_X (LD, "ld") -BU_VSX_OVERLOAD_X (ST, "st") -BU_VSX_OVERLOAD_X (XL, "xl") -BU_VSX_OVERLOAD_X (XL_BE, "xl_be") -BU_VSX_OVERLOAD_X (XST, "xst") -BU_VSX_OVERLOAD_X (XST_BE, "xst_be") - - -/* 2 argument CMPB instructions added in ISA 2.05. */ -BU_P6_2 (CMPB_32, "cmpb_32", CONST, cmpbsi3) -BU_P6_64BIT_2 (CMPB, "cmpb", CONST, cmpbdi3) - -/* 1 argument VSX instructions added in ISA 2.07. */ -BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn) -BU_P8V_VSX_1 (XSCVDPSPN, "xscvdpspn", CONST, vsx_xscvdpspn) -BU_P8V_VSX_1 (REVB_V1TI, "revb_v1ti", CONST, revb_v1ti) -BU_P8V_VSX_1 (REVB_V2DI, "revb_v2di", CONST, revb_v2di) -BU_P8V_VSX_1 (REVB_V4SI, "revb_v4si", CONST, revb_v4si) -BU_P8V_VSX_1 (REVB_V8HI, "revb_v8hi", CONST, revb_v8hi) -BU_P8V_VSX_1 (REVB_V16QI, "revb_v16qi", CONST, revb_v16qi) -BU_P8V_VSX_1 (REVB_V2DF, "revb_v2df", CONST, revb_v2df) -BU_P8V_VSX_1 (REVB_V4SF, "revb_v4sf", CONST, revb_v4sf) - -/* Power 8 Altivec NEG functions. */ -BU_P8V_AV_1 (NEG_V2DI, "neg_v2di", CONST, negv2di2) -BU_P8V_AV_1 (NEG_V4SI, "neg_v4si", CONST, negv4si2) -BU_P8V_AV_1 (NEG_V8HI, "neg_v8hi", CONST, negv8hi2) -BU_P8V_AV_1 (NEG_V16QI, "neg_v16qi", CONST, negv16qi2) -BU_P8V_AV_1 (NEG_V4SF, "neg_v4sf", CONST, negv4sf2) -BU_P8V_AV_1 (NEG_V2DF, "neg_v2df", CONST, negv2df2) - - -/* 2 argument VSX instructions added in ISA 2.07. */ -BU_P8V_VSX_2 (FLOAT2_V2DF, "float2_v2df", CONST, float2_v2df) -BU_P8V_VSX_2 (FLOAT2_V2DI, "float2_v2di", CONST, float2_v2di) -BU_P8V_VSX_2 (UNS_FLOAT2_V2DI, "uns_float2_v2di", CONST, uns_float2_v2di) -BU_P8V_VSX_2 (VEC_VSIGNED2_V2DF, "vsigned2_v2df", CONST, vsigned2_v2df) -BU_P8V_VSX_2 (VEC_VUNSIGNED2_V2DF, "vunsigned2_v2df", CONST, vunsigned2_v2df) - - -/* 1 argument altivec instructions added in ISA 2.07. */ -BU_P8V_AV_1 (ABS_V2DI, "abs_v2di", CONST, absv2di2) -BU_P8V_AV_1 (VUPKHSW, "vupkhsw", CONST, altivec_vupkhsw) -BU_P8V_AV_1 (VUPKLSW, "vupklsw", CONST, altivec_vupklsw) -BU_P8V_AV_1 (VCLZB, "vclzb", CONST, clzv16qi2) -BU_P8V_AV_1 (VCLZH, "vclzh", CONST, clzv8hi2) -BU_P8V_AV_1 (VCLZW, "vclzw", CONST, clzv4si2) -BU_P8V_AV_1 (VCLZD, "vclzd", CONST, clzv2di2) -BU_P8V_AV_1 (VPOPCNTB, "vpopcntb", CONST, popcountv16qi2) -BU_P8V_AV_1 (VPOPCNTH, "vpopcnth", CONST, popcountv8hi2) -BU_P8V_AV_1 (VPOPCNTW, "vpopcntw", CONST, popcountv4si2) -BU_P8V_AV_1 (VPOPCNTD, "vpopcntd", CONST, popcountv2di2) -BU_P8V_AV_1 (VPOPCNTUB, "vpopcntub", CONST, popcountv16qi2) -BU_P8V_AV_1 (VPOPCNTUH, "vpopcntuh", CONST, popcountv8hi2) -BU_P8V_AV_1 (VPOPCNTUW, "vpopcntuw", CONST, popcountv4si2) -BU_P8V_AV_1 (VPOPCNTUD, "vpopcntud", CONST, popcountv2di2) -BU_P8V_AV_1 (VGBBD, "vgbbd", CONST, p8v_vgbbd) - -/* 2 argument altivec instructions added in ISA 2.07. */ -BU_P8V_AV_2 (VADDCUQ, "vaddcuq", CONST, altivec_vaddcuq) -BU_P8V_AV_2 (VADDUDM, "vaddudm", CONST, addv2di3) -BU_P8V_AV_2 (VADDUQM, "vadduqm", CONST, altivec_vadduqm) -BU_P8V_AV_2 (VMINSD, "vminsd", CONST, sminv2di3) -BU_P8V_AV_2 (VMAXSD, "vmaxsd", CONST, smaxv2di3) -BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3) -BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3) -BU_P8V_AV_2 (VMRGEW_V2DI, "vmrgew_v2di", CONST, p8_vmrgew_v2di) -BU_P8V_AV_2 (VMRGEW_V2DF, "vmrgew_v2df", CONST, p8_vmrgew_v2df) -BU_P8V_AV_2 (VMRGEW_V4SI, "vmrgew_v4si", CONST, p8_vmrgew_v4si) -BU_P8V_AV_2 (VMRGEW_V4SF, "vmrgew_v4sf", CONST, p8_vmrgew_v4sf) -BU_P8V_AV_2 (VMRGOW_V4SI, "vmrgow_v4si", CONST, p8_vmrgow_v4si) -BU_P8V_AV_2 (VMRGOW_V4SF, "vmrgow_v4sf", CONST, p8_vmrgow_v4sf) -BU_P8V_AV_2 (VMRGOW_V2DI, "vmrgow_v2di", CONST, p8_vmrgow_v2di) -BU_P8V_AV_2 (VMRGOW_V2DF, "vmrgow_v2df", CONST, p8_vmrgow_v2df) -BU_P8V_AV_2 (VBPERMQ, "vbpermq", CONST, altivec_vbpermq) -BU_P8V_AV_2 (VBPERMQ2, "vbpermq2", CONST, altivec_vbpermq2) -BU_P8V_AV_2 (VPKUDUM, "vpkudum", CONST, altivec_vpkudum) -BU_P8V_AV_2 (VPKSDSS, "vpksdss", CONST, altivec_vpksdss) -BU_P8V_AV_2 (VPKUDUS, "vpkudus", CONST, altivec_vpkudus) -BU_P8V_AV_2 (VPKSDUS, "vpksdus", CONST, altivec_vpksdus) -BU_P8V_AV_2 (VPMSUMB, "vpmsumb", CONST, crypto_vpmsumb) -BU_P8V_AV_2 (VPMSUMH, "vpmsumh", CONST, crypto_vpmsumh) -BU_P8V_AV_2 (VPMSUMW, "vpmsumw", CONST, crypto_vpmsumw) -BU_P8V_AV_2 (VPMSUMD, "vpmsumd", CONST, crypto_vpmsumd) -BU_P8V_AV_2 (VRLD, "vrld", CONST, vrotlv2di3) -BU_P8V_AV_2 (VSLD, "vsld", CONST, vashlv2di3) -BU_P8V_AV_2 (VSRD, "vsrd", CONST, vlshrv2di3) -BU_P8V_AV_2 (VSRAD, "vsrad", CONST, vashrv2di3) -BU_P8V_AV_2 (VSUBCUQ, "vsubcuq", CONST, altivec_vsubcuq) -BU_P8V_AV_2 (VSUBUDM, "vsubudm", CONST, subv2di3) -BU_P8V_AV_2 (VSUBUQM, "vsubuqm", CONST, altivec_vsubuqm) - -BU_P8V_AV_2 (EQV_V16QI_UNS, "eqv_v16qi_uns",CONST, eqvv16qi3) -BU_P8V_AV_2 (EQV_V16QI, "eqv_v16qi", CONST, eqvv16qi3) -BU_P8V_AV_2 (EQV_V8HI_UNS, "eqv_v8hi_uns", CONST, eqvv8hi3) -BU_P8V_AV_2 (EQV_V8HI, "eqv_v8hi", CONST, eqvv8hi3) -BU_P8V_AV_2 (EQV_V4SI_UNS, "eqv_v4si_uns", CONST, eqvv4si3) -BU_P8V_AV_2 (EQV_V4SI, "eqv_v4si", CONST, eqvv4si3) -BU_P8V_AV_2 (EQV_V2DI_UNS, "eqv_v2di_uns", CONST, eqvv2di3) -BU_P8V_AV_2 (EQV_V2DI, "eqv_v2di", CONST, eqvv2di3) -BU_P8V_AV_2 (EQV_V1TI_UNS, "eqv_v1ti_uns", CONST, eqvv1ti3) -BU_P8V_AV_2 (EQV_V1TI, "eqv_v1ti", CONST, eqvv1ti3) -BU_P8V_AV_2 (EQV_V4SF, "eqv_v4sf", CONST, eqvv4sf3) -BU_P8V_AV_2 (EQV_V2DF, "eqv_v2df", CONST, eqvv2df3) - -BU_P8V_AV_2 (NAND_V16QI_UNS, "nand_v16qi_uns", CONST, nandv16qi3) -BU_P8V_AV_2 (NAND_V16QI, "nand_v16qi", CONST, nandv16qi3) -BU_P8V_AV_2 (NAND_V8HI_UNS, "nand_v8hi_uns", CONST, nandv8hi3) -BU_P8V_AV_2 (NAND_V8HI, "nand_v8hi", CONST, nandv8hi3) -BU_P8V_AV_2 (NAND_V4SI_UNS, "nand_v4si_uns", CONST, nandv4si3) -BU_P8V_AV_2 (NAND_V4SI, "nand_v4si", CONST, nandv4si3) -BU_P8V_AV_2 (NAND_V2DI_UNS, "nand_v2di_uns", CONST, nandv2di3) -BU_P8V_AV_2 (NAND_V2DI, "nand_v2di", CONST, nandv2di3) -BU_P8V_AV_2 (NAND_V1TI_UNS, "nand_v1ti_uns", CONST, nandv1ti3) -BU_P8V_AV_2 (NAND_V1TI, "nand_v1ti", CONST, nandv1ti3) -BU_P8V_AV_2 (NAND_V4SF, "nand_v4sf", CONST, nandv4sf3) -BU_P8V_AV_2 (NAND_V2DF, "nand_v2df", CONST, nandv2df3) - -BU_P8V_AV_2 (ORC_V16QI_UNS, "orc_v16qi_uns",CONST, orcv16qi3) -BU_P8V_AV_2 (ORC_V16QI, "orc_v16qi", CONST, orcv16qi3) -BU_P8V_AV_2 (ORC_V8HI_UNS, "orc_v8hi_uns", CONST, orcv8hi3) -BU_P8V_AV_2 (ORC_V8HI, "orc_v8hi", CONST, orcv8hi3) -BU_P8V_AV_2 (ORC_V4SI_UNS, "orc_v4si_uns", CONST, orcv4si3) -BU_P8V_AV_2 (ORC_V4SI, "orc_v4si", CONST, orcv4si3) -BU_P8V_AV_2 (ORC_V2DI_UNS, "orc_v2di_uns", CONST, orcv2di3) -BU_P8V_AV_2 (ORC_V2DI, "orc_v2di", CONST, orcv2di3) -BU_P8V_AV_2 (ORC_V1TI_UNS, "orc_v1ti_uns", CONST, orcv1ti3) -BU_P8V_AV_2 (ORC_V1TI, "orc_v1ti", CONST, orcv1ti3) -BU_P8V_AV_2 (ORC_V4SF, "orc_v4sf", CONST, orcv4sf3) -BU_P8V_AV_2 (ORC_V2DF, "orc_v2df", CONST, orcv2df3) - -/* 3 argument altivec instructions added in ISA 2.07. */ -BU_P8V_AV_3 (VADDEUQM, "vaddeuqm", CONST, altivec_vaddeuqm) -BU_P8V_AV_3 (VADDECUQ, "vaddecuq", CONST, altivec_vaddecuq) -BU_P8V_AV_3 (VSUBEUQM, "vsubeuqm", CONST, altivec_vsubeuqm) -BU_P8V_AV_3 (VSUBECUQ, "vsubecuq", CONST, altivec_vsubecuq) - -/* Vector comparison instructions added in ISA 2.07. */ -BU_P8V_AV_2 (VCMPEQUD, "vcmpequd", CONST, vector_eqv2di) -BU_P8V_AV_2 (VCMPGTSD, "vcmpgtsd", CONST, vector_gtv2di) -BU_P8V_AV_2 (VCMPGTUD, "vcmpgtud", CONST, vector_gtuv2di) - -/* Vector comparison predicate instructions added in ISA 2.07. */ -BU_P8V_AV_P (VCMPEQUD_P, "vcmpequd_p", CONST, vector_eq_v2di_p) -BU_P8V_AV_P (VCMPGTSD_P, "vcmpgtsd_p", CONST, vector_gt_v2di_p) -BU_P8V_AV_P (VCMPGTUD_P, "vcmpgtud_p", CONST, vector_gtu_v2di_p) - -BU_P8V_AV_3 (VPERMXOR, "vpermxor", CONST, altivec_vpermxor) - -/* ISA 2.05 overloaded 2 argument functions. */ -BU_P6_OVERLOAD_2 (CMPB, "cmpb") - -/* ISA 2.07 vector overloaded 1 argument functions. */ -BU_P8V_OVERLOAD_1 (VUPKHSW, "vupkhsw") -BU_P8V_OVERLOAD_1 (VUPKLSW, "vupklsw") -BU_P8V_OVERLOAD_1 (VCLZ, "vclz") -BU_P8V_OVERLOAD_1 (VCLZB, "vclzb") -BU_P8V_OVERLOAD_1 (VCLZH, "vclzh") -BU_P8V_OVERLOAD_1 (VCLZW, "vclzw") -BU_P8V_OVERLOAD_1 (VCLZD, "vclzd") -BU_P8V_OVERLOAD_1 (VPOPCNT, "vpopcnt") -BU_P8V_OVERLOAD_1 (VPOPCNTB, "vpopcntb") -BU_P8V_OVERLOAD_1 (VPOPCNTH, "vpopcnth") -BU_P8V_OVERLOAD_1 (VPOPCNTW, "vpopcntw") -BU_P8V_OVERLOAD_1 (VPOPCNTD, "vpopcntd") -BU_P8V_OVERLOAD_1 (VPOPCNTU, "vpopcntu") -BU_P8V_OVERLOAD_1 (VPOPCNTUB, "vpopcntub") -BU_P8V_OVERLOAD_1 (VPOPCNTUH, "vpopcntuh") -BU_P8V_OVERLOAD_1 (VPOPCNTUW, "vpopcntuw") -BU_P8V_OVERLOAD_1 (VPOPCNTUD, "vpopcntud") -BU_P8V_OVERLOAD_1 (VGBBD, "vgbbd") -BU_P8V_OVERLOAD_1 (REVB, "revb") -BU_P8V_OVERLOAD_1 (NEG, "neg") - -/* ISA 2.07 vector overloaded 2 argument functions. */ -BU_P8V_OVERLOAD_2 (EQV, "eqv") -BU_P8V_OVERLOAD_2 (NAND, "nand") -BU_P8V_OVERLOAD_2 (ORC, "orc") -BU_P8V_OVERLOAD_2 (VADDCUQ, "vaddcuq") -BU_P8V_OVERLOAD_2 (VADDUDM, "vaddudm") -BU_P8V_OVERLOAD_2 (VADDUQM, "vadduqm") -BU_P8V_OVERLOAD_2 (VBPERMQ, "vbpermq") -BU_P8V_OVERLOAD_2 (VMAXSD, "vmaxsd") -BU_P8V_OVERLOAD_2 (VMAXUD, "vmaxud") -BU_P8V_OVERLOAD_2 (VMINSD, "vminsd") -BU_P8V_OVERLOAD_2 (VMINUD, "vminud") -BU_P8V_OVERLOAD_2 (VMRGEW, "vmrgew") -BU_P8V_OVERLOAD_2 (VMRGOW, "vmrgow") -BU_P8V_OVERLOAD_2 (VPKSDSS, "vpksdss") -BU_P8V_OVERLOAD_2 (VPKSDUS, "vpksdus") -BU_P8V_OVERLOAD_2 (VPKUDUM, "vpkudum") -BU_P8V_OVERLOAD_2 (VPKUDUS, "vpkudus") -BU_P8V_OVERLOAD_2 (VPMSUM, "vpmsum") -BU_P8V_OVERLOAD_2 (VRLD, "vrld") -BU_P8V_OVERLOAD_2 (VSLD, "vsld") -BU_P8V_OVERLOAD_2 (VSRAD, "vsrad") -BU_P8V_OVERLOAD_2 (VSRD, "vsrd") -BU_P8V_OVERLOAD_2 (VSUBCUQ, "vsubcuq") -BU_P8V_OVERLOAD_2 (VSUBUDM, "vsubudm") -BU_P8V_OVERLOAD_2 (VSUBUQM, "vsubuqm") -BU_P8V_OVERLOAD_2 (FLOAT2, "float2") -BU_P8V_OVERLOAD_2 (UNS_FLOAT2, "uns_float2") -BU_P8V_OVERLOAD_2 (VSIGNED2, "vsigned2") -BU_P8V_OVERLOAD_2 (VUNSIGNED2, "vunsigned2") - -/* ISA 2.07 vector overloaded 3 argument functions. */ -BU_P8V_OVERLOAD_3 (VADDECUQ, "vaddecuq") -BU_P8V_OVERLOAD_3 (VADDEUQM, "vaddeuqm") -BU_P8V_OVERLOAD_3 (VSUBECUQ, "vsubecuq") -BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm") -BU_P8V_OVERLOAD_3 (VPERMXOR, "vpermxor") - -/* ISA 3.0 vector overloaded 2-argument functions. */ -BU_P9V_AV_2 (VSLV, "vslv", CONST, vslv) -BU_P9V_AV_2 (VSRV, "vsrv", CONST, vsrv) -BU_P9V_AV_2 (CONVERT_4F32_8I16, "convert_4f32_8i16", CONST, convert_4f32_8i16) -BU_P9V_AV_2 (CONVERT_4F32_8F16, "convert_4f32_8f16", CONST, convert_4f32_8f16) - -BU_P9V_AV_2 (VFIRSTMATCHINDEX_V16QI, "first_match_index_v16qi", - CONST, first_match_index_v16qi) -BU_P9V_AV_2 (VFIRSTMATCHINDEX_V8HI, "first_match_index_v8hi", - CONST, first_match_index_v8hi) -BU_P9V_AV_2 (VFIRSTMATCHINDEX_V4SI, "first_match_index_v4si", - CONST, first_match_index_v4si) -BU_P9V_AV_2 (VFIRSTMATCHOREOSINDEX_V16QI, "first_match_or_eos_index_v16qi", - CONST, first_match_or_eos_index_v16qi) -BU_P9V_AV_2 (VFIRSTMATCHOREOSINDEX_V8HI, "first_match_or_eos_index_v8hi", - CONST, first_match_or_eos_index_v8hi) -BU_P9V_AV_2 (VFIRSTMATCHOREOSINDEX_V4SI, "first_match_or_eos_index_v4si", - CONST, first_match_or_eos_index_v4si) -BU_P9V_AV_2 (VFIRSTMISMATCHINDEX_V16QI, "first_mismatch_index_v16qi", - CONST, first_mismatch_index_v16qi) -BU_P9V_AV_2 (VFIRSTMISMATCHINDEX_V8HI, "first_mismatch_index_v8hi", - CONST, first_mismatch_index_v8hi) -BU_P9V_AV_2 (VFIRSTMISMATCHINDEX_V4SI, "first_mismatch_index_v4si", - CONST, first_mismatch_index_v4si) -BU_P9V_AV_2 (VFIRSTMISMATCHOREOSINDEX_V16QI, "first_mismatch_or_eos_index_v16qi", - CONST, first_mismatch_or_eos_index_v16qi) -BU_P9V_AV_2 (VFIRSTMISMATCHOREOSINDEX_V8HI, "first_mismatch_or_eos_index_v8hi", - CONST, first_mismatch_or_eos_index_v8hi) -BU_P9V_AV_2 (VFIRSTMISMATCHOREOSINDEX_V4SI, "first_mismatch_or_eos_index_v4si", - CONST, first_mismatch_or_eos_index_v4si) - -/* ISA 3.0 vector overloaded 2-argument functions. */ -BU_P9V_OVERLOAD_2 (VSLV, "vslv") -BU_P9V_OVERLOAD_2 (VSRV, "vsrv") -BU_P9V_OVERLOAD_2 (CONVERT_4F32_8I16, "convert_4f32_8i16") -BU_P9V_OVERLOAD_2 (CONVERT_4F32_8F16, "convert_4f32_8f16") - -/* 2 argument vector functions added in ISA 3.0 (power9). */ -BU_P9V_AV_2 (VADUB, "vadub", CONST, vaduv16qi3) -BU_P9V_AV_2 (VADUH, "vaduh", CONST, vaduv8hi3) -BU_P9V_AV_2 (VADUW, "vaduw", CONST, vaduv4si3) -BU_P9V_AV_2 (VRLWNM, "vrlwnm", CONST, altivec_vrlwnm) -BU_P9V_AV_2 (VRLDNM, "vrldnm", CONST, altivec_vrldnm) -BU_P9V_AV_2 (VBPERMD, "vbpermd", CONST, altivec_vbpermd) - -/* ISA 3.0 vector overloaded 2 argument functions. */ -BU_P9V_OVERLOAD_2 (VADU, "vadu") -BU_P9V_OVERLOAD_2 (VADUB, "vadub") -BU_P9V_OVERLOAD_2 (VADUH, "vaduh") -BU_P9V_OVERLOAD_2 (VADUW, "vaduw") -BU_P9V_OVERLOAD_2 (RLNM, "rlnm") -BU_P9V_OVERLOAD_2 (VBPERM, "vbperm_api") - -/* ISA 3.0 3-argument vector functions. */ -BU_P9V_AV_3 (VRLWMI, "vrlwmi", CONST, altivec_vrlwmi) -BU_P9V_AV_3 (VRLDMI, "vrldmi", CONST, altivec_vrldmi) - -/* ISA 3.0 vector overloaded 3-argument functions. */ -BU_P9V_OVERLOAD_3 (RLMI, "rlmi") - -/* 1 argument vsx scalar functions added in ISA 3.0 (power9). */ -BU_P9V_64BIT_VSX_1 (VSEEDP, "scalar_extract_exp", CONST, xsxexpdp) -BU_P9V_64BIT_VSX_1 (VSESDP, "scalar_extract_sig", CONST, xsxsigdp) - -BU_FLOAT128_HW_VSX_1 (VSEEQP, "scalar_extract_expq", CONST, xsxexpqp_kf) -BU_FLOAT128_HW_VSX_1 (VSESQP, "scalar_extract_sigq", CONST, xsxsigqp_kf) - -BU_FLOAT128_HW_VSX_1 (VSTDCNQP, "scalar_test_neg_qp", CONST, xststdcnegqp_kf) -BU_P9V_VSX_1 (VSTDCNDP, "scalar_test_neg_dp", CONST, xststdcnegdp) -BU_P9V_VSX_1 (VSTDCNSP, "scalar_test_neg_sp", CONST, xststdcnegsp) - -BU_P9V_VSX_1 (XXBRQ_V16QI, "xxbrq_v16qi", CONST, p9_xxbrq_v16qi) -BU_P9V_VSX_1 (XXBRQ_V1TI, "xxbrq_v1ti", CONST, p9_xxbrq_v1ti) -BU_P9V_VSX_1 (XXBRD_V2DI, "xxbrd_v2di", CONST, p9_xxbrd_v2di) -BU_P9V_VSX_1 (XXBRD_V2DF, "xxbrd_v2df", CONST, p9_xxbrd_v2df) -BU_P9V_VSX_1 (XXBRW_V4SI, "xxbrw_v4si", CONST, p9_xxbrw_v4si) -BU_P9V_VSX_1 (XXBRW_V4SF, "xxbrw_v4sf", CONST, p9_xxbrw_v4sf) -BU_P9V_VSX_1 (XXBRH_V8HI, "xxbrh_v8hi", CONST, p9_xxbrh_v8hi) - -/* 2 argument vsx scalar functions added in ISA 3.0 (power9). */ -BU_P9V_64BIT_VSX_2 (VSIEDP, "scalar_insert_exp", CONST, xsiexpdp) -BU_P9V_64BIT_VSX_2 (VSIEDPF, "scalar_insert_exp_dp", CONST, xsiexpdpf) - -BU_FLOAT128_HW_VSX_2 (VSIEQP, "scalar_insert_exp_q", CONST, xsiexpqp_kf) -BU_FLOAT128_HW_VSX_2 (VSIEQPF, "scalar_insert_exp_qp", CONST, xsiexpqpf_kf) - -BU_P9V_VSX_2 (VSCEDPGT, "scalar_cmp_exp_dp_gt", CONST, xscmpexpdp_gt) -BU_P9V_VSX_2 (VSCEDPLT, "scalar_cmp_exp_dp_lt", CONST, xscmpexpdp_lt) -BU_P9V_VSX_2 (VSCEDPEQ, "scalar_cmp_exp_dp_eq", CONST, xscmpexpdp_eq) -BU_P9V_VSX_2 (VSCEDPUO, "scalar_cmp_exp_dp_unordered", CONST, xscmpexpdp_unordered) - -BU_P9V_VSX_2 (VSCEQPGT, "scalar_cmp_exp_qp_gt", CONST, xscmpexpqp_gt_kf) -BU_P9V_VSX_2 (VSCEQPLT, "scalar_cmp_exp_qp_lt", CONST, xscmpexpqp_lt_kf) -BU_P9V_VSX_2 (VSCEQPEQ, "scalar_cmp_exp_qp_eq", CONST, xscmpexpqp_eq_kf) -BU_P9V_VSX_2 (VSCEQPUO, "scalar_cmp_exp_qp_unordered", CONST, xscmpexpqp_unordered_kf) - -BU_FLOAT128_HW_VSX_2 (VSTDCQP, "scalar_test_data_class_qp", CONST, xststdcqp_kf) -BU_P9V_VSX_2 (VSTDCDP, "scalar_test_data_class_dp", CONST, xststdcdp) -BU_P9V_VSX_2 (VSTDCSP, "scalar_test_data_class_sp", CONST, xststdcsp) - -/* ISA 3.0 vector scalar overloaded 1 argument functions. */ -BU_P9V_OVERLOAD_1 (VSEEDP, "scalar_extract_exp") -BU_P9V_OVERLOAD_1 (VSESDP, "scalar_extract_sig") - -BU_P9V_OVERLOAD_1 (VSTDCN, "scalar_test_neg") -BU_P9V_OVERLOAD_1 (VSTDCNQP, "scalar_test_neg_qp") -BU_P9V_OVERLOAD_1 (VSTDCNDP, "scalar_test_neg_dp") -BU_P9V_OVERLOAD_1 (VSTDCNSP, "scalar_test_neg_sp") - -BU_P9V_OVERLOAD_1 (VEXTRACT_FP_FROM_SHORTH, "vextract_fp_from_shorth") -BU_P9V_OVERLOAD_1 (VEXTRACT_FP_FROM_SHORTL, "vextract_fp_from_shortl") - -/* ISA 3.0 vector scalar overloaded 2 argument functions. */ -BU_P9V_OVERLOAD_2 (VFIRSTMATCHINDEX, "first_match_index") -BU_P9V_OVERLOAD_2 (VFIRSTMISMATCHINDEX, "first_mismatch_index") -BU_P9V_OVERLOAD_2 (VFIRSTMATCHOREOSINDEX, "first_match_or_eos_index") -BU_P9V_OVERLOAD_2 (VFIRSTMISMATCHOREOSINDEX, "first_mismatch_or_eos_index") - -BU_P9V_OVERLOAD_2 (VSIEDP, "scalar_insert_exp") - -BU_P9V_OVERLOAD_2 (VSTDC, "scalar_test_data_class") -BU_P9V_OVERLOAD_2 (VSTDCQP, "scalar_test_data_class_qp") -BU_P9V_OVERLOAD_2 (VSTDCDP, "scalar_test_data_class_dp") -BU_P9V_OVERLOAD_2 (VSTDCSP, "scalar_test_data_class_sp") - -BU_P9V_OVERLOAD_2 (VSCEGT, "scalar_cmp_exp_gt") -BU_P9V_OVERLOAD_2 (VSCEDPGT, "scalar_cmp_exp_dp_gt") -BU_P9V_OVERLOAD_2 (VSCEQPGT, "scalar_cmp_exp_qp_gt") -BU_P9V_OVERLOAD_2 (VSCELT, "scalar_cmp_exp_lt") -BU_P9V_OVERLOAD_2 (VSCEDPLT, "scalar_cmp_exp_dp_lt") -BU_P9V_OVERLOAD_2 (VSCEQPLT, "scalar_cmp_exp_qp_lt") -BU_P9V_OVERLOAD_2 (VSCEEQ, "scalar_cmp_exp_eq") -BU_P9V_OVERLOAD_2 (VSCEDPEQ, "scalar_cmp_exp_dp_eq") -BU_P9V_OVERLOAD_2 (VSCEQPEQ, "scalar_cmp_exp_qp_eq") -BU_P9V_OVERLOAD_2 (VSCEUO, "scalar_cmp_exp_unordered") -BU_P9V_OVERLOAD_2 (VSCEDPUO, "scalar_cmp_exp_dp_unordered") -BU_P9V_OVERLOAD_2 (VSCEQPUO, "scalar_cmp_exp_qp_unordered") - -/* 1 argument vsx vector functions added in ISA 3.0 (power9). */ -BU_P9V_VSX_1 (VEEDP, "extract_exp_dp", CONST, xvxexpdp) -BU_P9V_VSX_1 (VEESP, "extract_exp_sp", CONST, xvxexpsp) -BU_P9V_VSX_1 (VESDP, "extract_sig_dp", CONST, xvxsigdp) -BU_P9V_VSX_1 (VESSP, "extract_sig_sp", CONST, xvxsigsp) -BU_P9V_VSX_1 (VEXTRACT_FP_FROM_SHORTH, "vextract_fp_from_shorth", CONST, vextract_fp_from_shorth) -BU_P9V_VSX_1 (VEXTRACT_FP_FROM_SHORTL, "vextract_fp_from_shortl", CONST, vextract_fp_from_shortl) - -/* 2 argument vsx vector functions added in ISA 3.0 (power9). */ -BU_P9V_VSX_2 (VIEDP, "insert_exp_dp", CONST, xviexpdp) -BU_P9V_VSX_2 (VIESP, "insert_exp_sp", CONST, xviexpsp) -BU_P9V_VSX_2 (VTDCDP, "test_data_class_dp", CONST, xvtstdcdp) -BU_P9V_VSX_2 (VTDCSP, "test_data_class_sp", CONST, xvtstdcsp) - -/* ISA 3.0 vector overloaded 1 argument functions. */ -BU_P9V_OVERLOAD_1 (VES, "extract_sig") -BU_P9V_OVERLOAD_1 (VESDP, "extract_sig_dp") -BU_P9V_OVERLOAD_1 (VESSP, "extract_sig_sp") - -BU_P9V_OVERLOAD_1 (VEE, "extract_exp") -BU_P9V_OVERLOAD_1 (VEEDP, "extract_exp_dp") -BU_P9V_OVERLOAD_1 (VEESP, "extract_exp_sp") - -/* ISA 3.0 vector overloaded 2 argument functions. */ -BU_P9V_OVERLOAD_2 (VTDC, "test_data_class") -BU_P9V_OVERLOAD_2 (VTDCDP, "test_data_class_dp") -BU_P9V_OVERLOAD_2 (VTDCSP, "test_data_class_sp") - -BU_P9V_OVERLOAD_2 (VIE, "insert_exp") -BU_P9V_OVERLOAD_2 (VIEDP, "insert_exp_dp") -BU_P9V_OVERLOAD_2 (VIESP, "insert_exp_sp") - -/* 2 argument vector functions added in ISA 3.0 (power9). */ -BU_P9V_64BIT_VSX_2 (LXVL, "lxvl", PURE, lxvl) -BU_P9V_64BIT_VSX_2 (XL_LEN_R, "xl_len_r", PURE, xl_len_r) - -BU_P9V_AV_2 (VEXTUBLX, "vextublx", CONST, vextublx) -BU_P9V_AV_2 (VEXTUBRX, "vextubrx", CONST, vextubrx) -BU_P9V_AV_2 (VEXTUHLX, "vextuhlx", CONST, vextuhlx) -BU_P9V_AV_2 (VEXTUHRX, "vextuhrx", CONST, vextuhrx) -BU_P9V_AV_2 (VEXTUWLX, "vextuwlx", CONST, vextuwlx) -BU_P9V_AV_2 (VEXTUWRX, "vextuwrx", CONST, vextuwrx) - -/* Insert/extract 4 byte word into a vector. */ -BU_P9V_VSX_3 (INSERT4B, "insert4b", CONST, insert4b) -BU_P9V_VSX_2 (EXTRACT4B, "extract4b", CONST, extract4b) - -/* Hardware IEEE 128-bit floating point round to odd instrucitons added in ISA - 3.0 (power9). */ -BU_FLOAT128_HW_1 (SQRTF128_ODD, "sqrtf128_round_to_odd", FP, sqrtkf2_odd) -BU_FLOAT128_HW_1 (TRUNCF128_ODD, "truncf128_round_to_odd", FP, trunckfdf2_odd) -BU_FLOAT128_HW_2 (ADDF128_ODD, "addf128_round_to_odd", FP, addkf3_odd) -BU_FLOAT128_HW_2 (SUBF128_ODD, "subf128_round_to_odd", FP, subkf3_odd) -BU_FLOAT128_HW_2 (MULF128_ODD, "mulf128_round_to_odd", FP, mulkf3_odd) -BU_FLOAT128_HW_2 (DIVF128_ODD, "divf128_round_to_odd", FP, divkf3_odd) -BU_FLOAT128_HW_3 (FMAF128_ODD, "fmaf128_round_to_odd", FP, fmakf4_odd) - -/* 3 argument vector functions returning void, treated as SPECIAL, - added in ISA 3.0 (power9). */ -BU_P9V_64BIT_AV_X (STXVL, "stxvl", MISC) -BU_P9V_64BIT_AV_X (XST_LEN_R, "xst_len_r", MISC) - -/* 1 argument vector functions added in ISA 3.0 (power9). */ -BU_P9V_AV_1 (VCLZLSBB_V16QI, "vclzlsbb_v16qi", CONST, vclzlsbb_v16qi) -BU_P9V_AV_1 (VCLZLSBB_V8HI, "vclzlsbb_v8hi", CONST, vclzlsbb_v8hi) -BU_P9V_AV_1 (VCLZLSBB_V4SI, "vclzlsbb_v4si", CONST, vclzlsbb_v4si) -BU_P9V_AV_1 (VCTZLSBB_V16QI, "vctzlsbb_v16qi", CONST, vctzlsbb_v16qi) -BU_P9V_AV_1 (VCTZLSBB_V8HI, "vctzlsbb_v8hi", CONST, vctzlsbb_v8hi) -BU_P9V_AV_1 (VCTZLSBB_V4SI, "vctzlsbb_v4si", CONST, vctzlsbb_v4si) - -/* Built-in support for Power9 "VSU option" string operations includes - new awareness of the "vector compare not equal" (vcmpneb, vcmpneb., - vcmpneh, vcmpneh., vcmpnew, vcmpnew.) and "vector compare - not equal or zero" (vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., - vcmpnezw, vcmpnezw.) instructions. */ - -BU_P9V_AV_2 (CMPNEB, "vcmpneb", CONST, vcmpneb) -BU_P9V_AV_2 (CMPNEH, "vcmpneh", CONST, vcmpneh) -BU_P9V_AV_2 (CMPNEW, "vcmpnew", CONST, vcmpnew) - -BU_P9V_AV_2 (VCMPNEB_P, "vcmpneb_p", CONST, vector_ne_v16qi_p) -BU_P9V_AV_2 (VCMPNEH_P, "vcmpneh_p", CONST, vector_ne_v8hi_p) -BU_P9V_AV_2 (VCMPNEW_P, "vcmpnew_p", CONST, vector_ne_v4si_p) -BU_P9V_AV_2 (VCMPNED_P, "vcmpned_p", CONST, vector_ne_v2di_p) - -BU_P9V_AV_2 (VCMPNEFP_P, "vcmpnefp_p", CONST, vector_ne_v4sf_p) -BU_P9V_AV_2 (VCMPNEDP_P, "vcmpnedp_p", CONST, vector_ne_v2df_p) - -BU_P9V_AV_2 (VCMPAEB_P, "vcmpaeb_p", CONST, vector_ae_v16qi_p) -BU_P9V_AV_2 (VCMPAEH_P, "vcmpaeh_p", CONST, vector_ae_v8hi_p) -BU_P9V_AV_2 (VCMPAEW_P, "vcmpaew_p", CONST, vector_ae_v4si_p) -BU_P9V_AV_2 (VCMPAED_P, "vcmpaed_p", CONST, vector_ae_v2di_p) - -BU_P9V_AV_2 (VCMPAEFP_P, "vcmpaefp_p", CONST, vector_ae_v4sf_p) -BU_P9V_AV_2 (VCMPAEDP_P, "vcmpaedp_p", CONST, vector_ae_v2df_p) - -BU_P9V_AV_2 (CMPNEZB, "vcmpnezb", CONST, vcmpnezb) -BU_P9V_AV_2 (CMPNEZH, "vcmpnezh", CONST, vcmpnezh) -BU_P9V_AV_2 (CMPNEZW, "vcmpnezw", CONST, vcmpnezw) - -BU_P9V_AV_P (VCMPNEZB_P, "vcmpnezb_p", CONST, vector_nez_v16qi_p) -BU_P9V_AV_P (VCMPNEZH_P, "vcmpnezh_p", CONST, vector_nez_v8hi_p) -BU_P9V_AV_P (VCMPNEZW_P, "vcmpnezw_p", CONST, vector_nez_v4si_p) - -/* ISA 3.0 Vector scalar overloaded 2 argument functions */ -BU_P9V_OVERLOAD_2 (LXVL, "lxvl") -BU_P9V_OVERLOAD_2 (XL_LEN_R, "xl_len_r") -BU_P9V_OVERLOAD_2 (VEXTULX, "vextulx") -BU_P9V_OVERLOAD_2 (VEXTURX, "vexturx") -BU_P9V_OVERLOAD_2 (EXTRACT4B, "extract4b") - -/* ISA 3.0 Vector scalar overloaded 3 argument functions */ -BU_P9V_OVERLOAD_3 (STXVL, "stxvl") -BU_P9V_OVERLOAD_3 (XST_LEN_R, "xst_len_r") -BU_P9V_OVERLOAD_3 (INSERT4B, "insert4b") - -/* Overloaded CMPNE support was implemented prior to Power 9, - so is not mentioned here. */ -BU_P9V_OVERLOAD_2 (CMPNEZ, "vcmpnez") - -BU_P9V_OVERLOAD_P (VCMPNEZ_P, "vcmpnez_p") -BU_P9V_OVERLOAD_2 (VCMPNE_P, "vcmpne_p") -BU_P9V_OVERLOAD_2 (VCMPAE_P, "vcmpae_p") - -/* ISA 3.0 Vector scalar overloaded 1 argument functions */ -BU_P9V_OVERLOAD_1 (VCLZLSBB, "vclzlsbb") -BU_P9V_OVERLOAD_1 (VCTZLSBB, "vctzlsbb") - -/* 2 argument extended divide functions added in ISA 2.06. */ -BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si) -BU_P7_MISC_2 (DIVWEU, "divweu", CONST, diveu_si) -BU_P7_POWERPC64_MISC_2 (DIVDE, "divde", CONST, dive_di) -BU_P7_POWERPC64_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di) - -/* 1 argument DFP (decimal floating point) functions added in ISA 2.05. */ -BU_DFP_MISC_1 (DXEX, "dxex", CONST, dfp_dxex_dd) -BU_DFP_MISC_1 (DXEXQ, "dxexq", CONST, dfp_dxex_td) - -/* 2 argument DFP (decimal floating point) functions added in ISA 2.05. */ -BU_DFP_MISC_2 (DDEDPD, "ddedpd", CONST, dfp_ddedpd_dd) -BU_DFP_MISC_2 (DDEDPDQ, "ddedpdq", CONST, dfp_ddedpd_td) -BU_DFP_MISC_2 (DENBCD, "denbcd", CONST, dfp_denbcd_dd) -BU_DFP_MISC_2 (DENBCDQ, "denbcdq", CONST, dfp_denbcd_td) -BU_DFP_MISC_2 (DIEX, "diex", CONST, dfp_diex_dd) -BU_DFP_MISC_2 (DIEXQ, "diexq", CONST, dfp_diex_td) -BU_DFP_MISC_2 (DSCLI, "dscli", CONST, dfp_dscli_dd) -BU_DFP_MISC_2 (DSCLIQ, "dscliq", CONST, dfp_dscli_td) -BU_DFP_MISC_2 (DSCRI, "dscri", CONST, dfp_dscri_dd) -BU_DFP_MISC_2 (DSCRIQ, "dscriq", CONST, dfp_dscri_td) - -/* 0 argument void function that we pretend was added in ISA 2.06. - It's a special nop recognized by 2018+ firmware for P7 and up, - with speculation barrier semantics. */ -BU_P7_MISC_X (SPEC_BARRIER, "ppc_speculation_barrier", MISC) - -/* 1 argument BCD functions added in ISA 2.06. */ -BU_P7_MISC_1 (CDTBCD, "cdtbcd", CONST, cdtbcd) -BU_P7_MISC_1 (CBCDTD, "cbcdtd", CONST, cbcdtd) - -/* 2 argument BCD functions added in ISA 2.06. */ -BU_P7_MISC_2 (ADDG6S, "addg6s", CONST, addg6s) - -/* 3 argument BCD functions added in ISA 2.07. */ -BU_P8V_MISC_3 (BCDADD_V1TI, "bcdadd_v1ti", CONST, bcdadd_v1ti) -BU_P8V_MISC_3 (BCDADD_V16QI, "bcdadd_v16qi", CONST, bcdadd_v16qi) -BU_P8V_MISC_3 (BCDADD_LT_V1TI, "bcdadd_lt_v1ti", CONST, bcdadd_lt_v1ti) -BU_P8V_MISC_3 (BCDADD_LT_V16QI, "bcdadd_lt_v16qi", CONST, bcdadd_lt_v16qi) -BU_P8V_MISC_3 (BCDADD_EQ_V1TI, "bcdadd_eq_v1ti", CONST, bcdadd_eq_v1ti) -BU_P8V_MISC_3 (BCDADD_EQ_V16QI, "bcdadd_eq_v16qi", CONST, bcdadd_eq_v16qi) -BU_P8V_MISC_3 (BCDADD_GT_V1TI, "bcdadd_gt_v1ti", CONST, bcdadd_gt_v1ti) -BU_P8V_MISC_3 (BCDADD_GT_V16QI, "bcdadd_gt_v16qi", CONST, bcdadd_gt_v16qi) -BU_P8V_MISC_3 (BCDADD_OV_V1TI, "bcdadd_ov_v1ti", CONST, bcdadd_unordered_v1ti) -BU_P8V_MISC_3 (BCDADD_OV_V16QI, "bcdadd_ov_v16qi", CONST, bcdadd_unordered_v16qi) - -BU_P8V_MISC_3 (BCDSUB_V1TI, "bcdsub_v1ti", CONST, bcdsub_v1ti) -BU_P8V_MISC_3 (BCDSUB_V16QI, "bcdsub_v16qi", CONST, bcdsub_v16qi) -BU_P8V_MISC_3 (BCDSUB_LT_V1TI, "bcdsub_lt_v1ti", CONST, bcdsub_lt_v1ti) -BU_P8V_MISC_3 (BCDSUB_LT_V16QI, "bcdsub_lt_v16qi", CONST, bcdsub_lt_v16qi) -BU_P8V_MISC_3 (BCDSUB_LE_V1TI, "bcdsub_le_v1ti", CONST, bcdsub_le_v1ti) -BU_P8V_MISC_3 (BCDSUB_LE_V16QI, "bcdsub_le_v16qi", CONST, bcdsub_le_v16qi) -BU_P8V_MISC_3 (BCDSUB_EQ_V1TI, "bcdsub_eq_v1ti", CONST, bcdsub_eq_v1ti) -BU_P8V_MISC_3 (BCDSUB_EQ_V16QI, "bcdsub_eq_v16qi", CONST, bcdsub_eq_v16qi) -BU_P8V_MISC_3 (BCDSUB_GT_V1TI, "bcdsub_gt_v1ti", CONST, bcdsub_gt_v1ti) -BU_P8V_MISC_3 (BCDSUB_GT_V16QI, "bcdsub_gt_v16qi", CONST, bcdsub_gt_v16qi) -BU_P8V_MISC_3 (BCDSUB_GE_V1TI, "bcdsub_ge_v1ti", CONST, bcdsub_ge_v1ti) -BU_P8V_MISC_3 (BCDSUB_GE_V16QI, "bcdsub_ge_v16qi", CONST, bcdsub_ge_v16qi) -BU_P8V_MISC_3 (BCDSUB_OV_V1TI, "bcdsub_ov_v1ti", CONST, bcdsub_unordered_v1ti) -BU_P8V_MISC_3 (BCDSUB_OV_V16QI, "bcdsub_ov_v16qi", CONST, bcdsub_unordered_v16qi) - -BU_P8V_MISC_1 (BCDINVALID_V1TI, "bcdinvalid_v1ti", CONST, bcdinvalid_v1ti) -BU_P8V_MISC_1 (BCDINVALID_V16QI, "bcdinvalid_v16qi", CONST, bcdinvalid_v16qi) - -BU_P9V_AV_1 (BCDMUL10_V16QI, "bcdmul10_v16qi", CONST, bcdmul10_v16qi) -BU_P9V_AV_1 (BCDDIV10_V16QI, "bcddiv10_v16qi", CONST, bcddiv10_v16qi) -BU_P8V_MISC_1 (DENBCD_V16QI, "denb2dfp_v16qi", CONST, dfp_denbcd_v16qi) - -BU_P8V_OVERLOAD_3 (BCDADD, "bcdadd") -BU_P8V_OVERLOAD_3 (BCDADD_LT, "bcdadd_lt") -BU_P8V_OVERLOAD_3 (BCDADD_EQ, "bcdadd_eq") -BU_P8V_OVERLOAD_3 (BCDADD_GT, "bcdadd_gt") -BU_P8V_OVERLOAD_3 (BCDADD_OV, "bcdadd_ov") -BU_P8V_OVERLOAD_3 (BCDSUB, "bcdsub") -BU_P8V_OVERLOAD_3 (BCDSUB_LT, "bcdsub_lt") -BU_P8V_OVERLOAD_3 (BCDSUB_LE, "bcdsub_le") -BU_P8V_OVERLOAD_3 (BCDSUB_EQ, "bcdsub_eq") -BU_P8V_OVERLOAD_3 (BCDSUB_GT, "bcdsub_gt") -BU_P8V_OVERLOAD_3 (BCDSUB_GE, "bcdsub_ge") -BU_P8V_OVERLOAD_3 (BCDSUB_OV, "bcdsub_ov") -BU_P8V_OVERLOAD_1 (BCDINVALID, "bcdinvalid") -BU_P9V_OVERLOAD_1 (BCDMUL10, "bcdmul10") -BU_P9V_OVERLOAD_1 (BCDDIV10, "bcddiv10") -BU_P8V_OVERLOAD_1 (DENBCD, "denb2dfp") - -/* 2 argument pack/unpack 128-bit floating point types. */ -BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd) -BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd) - -/* 0 argument general-purpose register functions added in ISA 3.0 (power9). */ -BU_P9_MISC_0 (DARN_32, "darn_32", MISC, darn_32) -BU_P9_64BIT_MISC_0 (DARN_RAW, "darn_raw", MISC, darn_raw) -BU_P9_64BIT_MISC_0 (DARN, "darn", MISC, darn) - -BU_LDBL128_2 (PACK_TF, "pack_longdouble", CONST, packtf) -BU_LDBL128_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf) - -BU_IBM128_2 (PACK_IF, "pack_ibm128", CONST, packif) -BU_IBM128_2 (UNPACK_IF, "unpack_ibm128", CONST, unpackif) - -BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti) -BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti) - -/* 2 argument DFP (Decimal Floating Point) functions added in ISA 3.0. */ -BU_P9_DFP_MISC_2 (TSTSFI_LT_DD, "dtstsfi_lt_dd", CONST, dfptstsfi_lt_dd) -BU_P9_DFP_MISC_2 (TSTSFI_LT_TD, "dtstsfi_lt_td", CONST, dfptstsfi_lt_td) - -BU_P9_DFP_MISC_2 (TSTSFI_EQ_DD, "dtstsfi_eq_dd", CONST, dfptstsfi_eq_dd) -BU_P9_DFP_MISC_2 (TSTSFI_EQ_TD, "dtstsfi_eq_td", CONST, dfptstsfi_eq_td) - -BU_P9_DFP_MISC_2 (TSTSFI_GT_DD, "dtstsfi_gt_dd", CONST, dfptstsfi_gt_dd) -BU_P9_DFP_MISC_2 (TSTSFI_GT_TD, "dtstsfi_gt_td", CONST, dfptstsfi_gt_td) - -BU_P9_DFP_MISC_2 (TSTSFI_OV_DD, "dtstsfi_ov_dd", CONST, dfptstsfi_unordered_dd) -BU_P9_DFP_MISC_2 (TSTSFI_OV_TD, "dtstsfi_ov_td", CONST, dfptstsfi_unordered_td) - -/* 2 argument overloaded DFP functions added in ISA 3.0. */ -BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT, "dtstsfi_lt") -BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT_DD, "dtstsfi_lt_dd") -BU_P9_DFP_OVERLOAD_2 (TSTSFI_LT_TD, "dtstsfi_lt_td") - -BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ, "dtstsfi_eq") -BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ_DD, "dtstsfi_eq_dd") -BU_P9_DFP_OVERLOAD_2 (TSTSFI_EQ_TD, "dtstsfi_eq_td") - -BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT, "dtstsfi_gt") -BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT_DD, "dtstsfi_gt_dd") -BU_P9_DFP_OVERLOAD_2 (TSTSFI_GT_TD, "dtstsfi_gt_td") - -BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV, "dtstsfi_ov") -BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV_DD, "dtstsfi_ov_dd") -BU_P9_DFP_OVERLOAD_2 (TSTSFI_OV_TD, "dtstsfi_ov_td") - -/* 1 argument vector functions added in ISA 3.0 (power9). */ -BU_P9V_AV_1 (VCTZB, "vctzb", CONST, ctzv16qi2) -BU_P9V_AV_1 (VCTZH, "vctzh", CONST, ctzv8hi2) -BU_P9V_AV_1 (VCTZW, "vctzw", CONST, ctzv4si2) -BU_P9V_AV_1 (VCTZD, "vctzd", CONST, ctzv2di2) -BU_P9V_AV_1 (VPRTYBD, "vprtybd", CONST, parityv2di2) -BU_P9V_AV_1 (VPRTYBQ, "vprtybq", CONST, parityv1ti2) -BU_P9V_AV_1 (VPRTYBW, "vprtybw", CONST, parityv4si2) - -/* ISA 3.0 vector overloaded 1 argument functions. */ -BU_P9V_OVERLOAD_1 (VCTZ, "vctz") -BU_P9V_OVERLOAD_1 (VCTZB, "vctzb") -BU_P9V_OVERLOAD_1 (VCTZH, "vctzh") -BU_P9V_OVERLOAD_1 (VCTZW, "vctzw") -BU_P9V_OVERLOAD_1 (VCTZD, "vctzd") -BU_P9V_OVERLOAD_1 (VPRTYB, "vprtyb") -BU_P9V_OVERLOAD_1 (VPRTYBD, "vprtybd") -BU_P9V_OVERLOAD_1 (VPRTYBQ, "vprtybq") -BU_P9V_OVERLOAD_1 (VPRTYBW, "vprtybw") -BU_P9V_OVERLOAD_1 (VPARITY_LSBB, "vparity_lsbb") -BU_P9V_OVERLOAD_1 (VSIGNEXTI, "vsignexti") -BU_P9V_OVERLOAD_1 (VSIGNEXTLL, "vsignextll") - -/* 2 argument functions added in ISA 3.0 (power9). */ -BU_P9_2 (CMPRB, "byte_in_range", CONST, cmprb) -BU_P9_2 (CMPRB2, "byte_in_either_range", CONST, cmprb2) -BU_P9_64BIT_2 (CMPEQB, "byte_in_set", CONST, cmpeqb) - -/* 2 argument overloaded functions added in ISA 3.0 (power9). */ -BU_P9_OVERLOAD_2 (CMPRB, "byte_in_range") -BU_P9_OVERLOAD_2 (CMPRB2, "byte_in_either_range") -BU_P9_OVERLOAD_2 (CMPEQB, "byte_in_set") - - -BU_P9V_AV_1 (VSIGNEXTSB2W, "vsignextsb2w", CONST, vsignextend_qi_v4si) -BU_P9V_AV_1 (VSIGNEXTSH2W, "vsignextsh2w", CONST, vsignextend_hi_v4si) -BU_P9V_AV_1 (VSIGNEXTSB2D, "vsignextsb2d", CONST, vsignextend_qi_v2di) -BU_P9V_AV_1 (VSIGNEXTSH2D, "vsignextsh2d", CONST, vsignextend_hi_v2di) -BU_P9V_AV_1 (VSIGNEXTSW2D, "vsignextsw2d", CONST, vsignextend_si_v2di) - -/* Builtins for scalar instructions added in ISA 3.1 (power10). */ -BU_P10V_AV_P (VCMPEQUT_P, "vcmpequt_p", CONST, vector_eq_v1ti_p) -BU_P10V_AV_P (VCMPGTST_P, "vcmpgtst_p", CONST, vector_gt_v1ti_p) -BU_P10V_AV_P (VCMPGTUT_P, "vcmpgtut_p", CONST, vector_gtu_v1ti_p) - -BU_P10_POWERPC64_MISC_2 (CFUGED, "cfuged", CONST, cfuged) -BU_P10_POWERPC64_MISC_2 (CNTLZDM, "cntlzdm", CONST, cntlzdm) -BU_P10_POWERPC64_MISC_2 (CNTTZDM, "cnttzdm", CONST, cnttzdm) -BU_P10_POWERPC64_MISC_2 (PDEPD, "pdepd", CONST, pdepd) -BU_P10_POWERPC64_MISC_2 (PEXTD, "pextd", CONST, pextd) - -/* Builtins for vector instructions added in ISA 3.1 (power10). */ -BU_P10V_AV_2 (VCLRLB, "vclrlb", CONST, vclrlb) -BU_P10V_AV_2 (VCLRRB, "vclrrb", CONST, vclrrb) -BU_P10V_AV_2 (VCFUGED, "vcfuged", CONST, vcfuged) -BU_P10V_AV_2 (VCLZDM, "vclzdm", CONST, vclzdm) -BU_P10V_AV_2 (VCTZDM, "vctzdm", CONST, vctzdm) -BU_P10V_AV_2 (VPDEPD, "vpdepd", CONST, vpdepd) -BU_P10V_AV_2 (VPEXTD, "vpextd", CONST, vpextd) -BU_P10V_AV_2 (VGNB, "vgnb", CONST, vgnb) -BU_P10V_VSX_4 (XXEVAL, "xxeval", CONST, xxeval) -BU_P10V_VSX_2 (XXGENPCVM_V16QI, "xxgenpcvm_v16qi", CONST, xxgenpcvm_v16qi) -BU_P10V_VSX_2 (XXGENPCVM_V8HI, "xxgenpcvm_v8hi", CONST, xxgenpcvm_v8hi) -BU_P10V_VSX_2 (XXGENPCVM_V4SI, "xxgenpcvm_v4si", CONST, xxgenpcvm_v4si) -BU_P10V_VSX_2 (XXGENPCVM_V2DI, "xxgenpcvm_v2di", CONST, xxgenpcvm_v2di) -BU_P10V_AV_2 (VCMPGTUT, "vcmpgtut", CONST, vector_gtuv1ti) -BU_P10V_AV_2 (VCMPGTST, "vcmpgtst", CONST, vector_gtv1ti) -BU_P10V_AV_2 (VCMPEQUT, "vcmpequt", CONST, vector_eqv1ti) -BU_P10V_AV_2 (CMPNET, "vcmpnet", CONST, vcmpnet) -BU_P10V_AV_2 (CMPGE_1TI, "cmpge_1ti", CONST, vector_nltv1ti) -BU_P10V_AV_2 (CMPGE_U1TI, "cmpge_u1ti", CONST, vector_nltuv1ti) -BU_P10V_AV_2 (CMPLE_1TI, "cmple_1ti", CONST, vector_ngtv1ti) -BU_P10V_AV_2 (CMPLE_U1TI, "cmple_u1ti", CONST, vector_ngtuv1ti) -BU_P10V_AV_2 (VNOR_V1TI_UNS, "vnor_v1ti_uns",CONST, norv1ti3) -BU_P10V_AV_2 (VNOR_V1TI, "vnor_v1ti", CONST, norv1ti3) -BU_P10V_AV_2 (VCMPNET_P, "vcmpnet_p", CONST, vector_ne_v1ti_p) -BU_P10V_AV_2 (VCMPAET_P, "vcmpaet_p", CONST, vector_ae_v1ti_p) - -BU_P10V_AV_1 (VSIGNEXTSD2Q, "vsignext", CONST, vsignextend_v2di_v1ti) - -BU_P10V_AV_2 (VMULEUD, "vmuleud", CONST, vec_widen_umult_even_v2di) -BU_P10V_AV_2 (VMULESD, "vmulesd", CONST, vec_widen_smult_even_v2di) -BU_P10V_AV_2 (VMULOUD, "vmuloud", CONST, vec_widen_umult_odd_v2di) -BU_P10V_AV_2 (VMULOSD, "vmulosd", CONST, vec_widen_smult_odd_v2di) -BU_P10V_AV_2 (VRLQ, "vrlq", CONST, vrotlv1ti3) -BU_P10V_AV_2 (VSLQ, "vslq", CONST, vashlv1ti3) -BU_P10V_AV_2 (VSRQ, "vsrq", CONST, vlshrv1ti3) -BU_P10V_AV_2 (VSRAQ, "vsraq", CONST, vashrv1ti3) -BU_P10V_AV_2 (VRLQNM, "vrlqnm", CONST, altivec_vrlqnm) -BU_P10V_AV_2 (DIV_V1TI, "div_1ti", CONST, vsx_div_v1ti) -BU_P10V_AV_2 (UDIV_V1TI, "udiv_1ti", CONST, vsx_udiv_v1ti) -BU_P10V_AV_2 (DIVES_V1TI, "dives", CONST, vsx_dives_v1ti) -BU_P10V_AV_2 (DIVEU_V1TI, "diveu", CONST, vsx_diveu_v1ti) -BU_P10V_AV_2 (MODS_V1TI, "mods", CONST, vsx_mods_v1ti) -BU_P10V_AV_2 (MODU_V1TI, "modu", CONST, vsx_modu_v1ti) - -BU_P10V_AV_3 (VRLQMI, "vrlqmi", CONST, altivec_vrlqmi) -BU_P10V_AV_3 (VEXTRACTBL, "vextdubvlx", CONST, vextractlv16qi) -BU_P10V_AV_3 (VEXTRACTHL, "vextduhvlx", CONST, vextractlv8hi) -BU_P10V_AV_3 (VEXTRACTWL, "vextduwvlx", CONST, vextractlv4si) -BU_P10V_AV_3 (VEXTRACTDL, "vextddvlx", CONST, vextractlv2di) - -BU_P10V_AV_3 (VEXTRACTBR, "vextdubvhx", CONST, vextractrv16qi) -BU_P10V_AV_3 (VEXTRACTHR, "vextduhvhx", CONST, vextractrv8hi) -BU_P10V_AV_3 (VEXTRACTWR, "vextduwvhx", CONST, vextractrv4si) -BU_P10V_AV_3 (VEXTRACTDR, "vextddvhx", CONST, vextractrv2di) - -BU_P10V_AV_3 (VINSERTGPRBL, "vinsgubvlx", CONST, vinsertgl_v16qi) -BU_P10V_AV_3 (VINSERTGPRHL, "vinsguhvlx", CONST, vinsertgl_v8hi) -BU_P10V_AV_3 (VINSERTGPRWL, "vinsguwvlx", CONST, vinsertgl_v4si) -BU_P10V_AV_3 (VINSERTGPRDL, "vinsgudvlx", CONST, vinsertgl_v2di) -BU_P10V_AV_3 (VINSERTVPRBL, "vinsvubvlx", CONST, vinsertvl_v16qi) -BU_P10V_AV_3 (VINSERTVPRHL, "vinsvuhvlx", CONST, vinsertvl_v8hi) -BU_P10V_AV_3 (VINSERTVPRWL, "vinsvuwvlx", CONST, vinsertvl_v4si) - -BU_P10V_AV_3 (VINSERTGPRBR, "vinsgubvrx", CONST, vinsertgr_v16qi) -BU_P10V_AV_3 (VINSERTGPRHR, "vinsguhvrx", CONST, vinsertgr_v8hi) -BU_P10V_AV_3 (VINSERTGPRWR, "vinsguwvrx", CONST, vinsertgr_v4si) -BU_P10V_AV_3 (VINSERTGPRDR, "vinsgudvrx", CONST, vinsertgr_v2di) -BU_P10V_AV_3 (VINSERTVPRBR, "vinsvubvrx", CONST, vinsertvr_v16qi) -BU_P10V_AV_3 (VINSERTVPRHR, "vinsvuhvrx", CONST, vinsertvr_v8hi) -BU_P10V_AV_3 (VINSERTVPRWR, "vinsvuwvrx", CONST, vinsertvr_v4si) - -BU_P10V_AV_3 (VREPLACE_ELT_V4SI, "vreplace_v4si", CONST, vreplace_elt_v4si) -BU_P10V_AV_3 (VREPLACE_ELT_UV4SI, "vreplace_uv4si", CONST, vreplace_elt_v4si) -BU_P10V_AV_3 (VREPLACE_ELT_V4SF, "vreplace_v4sf", CONST, vreplace_elt_v4sf) -BU_P10V_AV_3 (VREPLACE_ELT_V2DI, "vreplace_v2di", CONST, vreplace_elt_v2di) -BU_P10V_AV_3 (VREPLACE_ELT_UV2DI, "vreplace_uv2di", CONST, vreplace_elt_v2di) -BU_P10V_AV_3 (VREPLACE_ELT_V2DF, "vreplace_v2df", CONST, vreplace_elt_v2df) - -BU_P10V_AV_3 (VREPLACE_UN_V4SI, "vreplace_un_v4si", CONST, vreplace_un_v4si) -BU_P10V_AV_3 (VREPLACE_UN_UV4SI, "vreplace_un_uv4si", CONST, vreplace_un_v4si) -BU_P10V_AV_3 (VREPLACE_UN_V4SF, "vreplace_un_v4sf", CONST, vreplace_un_v4sf) -BU_P10V_AV_3 (VREPLACE_UN_V2DI, "vreplace_un_v2di", CONST, vreplace_un_v2di) -BU_P10V_AV_3 (VREPLACE_UN_UV2DI, "vreplace_un_uv2di", CONST, vreplace_un_v2di) -BU_P10V_AV_3 (VREPLACE_UN_V2DF, "vreplace_un_v2df", CONST, vreplace_un_v2df) - -BU_P10V_AV_3 (VSLDB_V16QI, "vsldb_v16qi", CONST, vsldb_v16qi) -BU_P10V_AV_3 (VSLDB_V8HI, "vsldb_v8hi", CONST, vsldb_v8hi) -BU_P10V_AV_3 (VSLDB_V4SI, "vsldb_v4si", CONST, vsldb_v4si) -BU_P10V_AV_3 (VSLDB_V2DI, "vsldb_v2di", CONST, vsldb_v2di) - -BU_P10V_AV_3 (VSRDB_V16QI, "vsrdb_v16qi", CONST, vsrdb_v16qi) -BU_P10V_AV_3 (VSRDB_V8HI, "vsrdb_v8hi", CONST, vsrdb_v8hi) -BU_P10V_AV_3 (VSRDB_V4SI, "vsrdb_v4si", CONST, vsrdb_v4si) -BU_P10V_AV_3 (VSRDB_V2DI, "vsrdb_v2di", CONST, vsrdb_v2di) - -BU_P10V_AV_2 (DIVES_V4SI, "vdivesw", CONST, dives_v4si) -BU_P10V_AV_2 (DIVES_V2DI, "vdivesd", CONST, dives_v2di) -BU_P10V_AV_2 (DIVEU_V4SI, "vdiveuw", CONST, diveu_v4si) -BU_P10V_AV_2 (DIVEU_V2DI, "vdiveud", CONST, diveu_v2di) -BU_P10V_AV_2 (DIVS_V4SI, "vdivsw", CONST, divv4si3) -BU_P10V_AV_2 (DIVS_V2DI, "vdivsd", CONST, divv2di3) -BU_P10V_AV_2 (DIVU_V4SI, "vdivuw", CONST, udivv4si3) -BU_P10V_AV_2 (DIVU_V2DI, "vdivud", CONST, udivv2di3) -BU_P10V_AV_2 (MODS_V2DI, "vmodsd", CONST, modv2di3) -BU_P10V_AV_2 (MODS_V4SI, "vmodsw", CONST, modv4si3) -BU_P10V_AV_2 (MODU_V2DI, "vmodud", CONST, umodv2di3) -BU_P10V_AV_2 (MODU_V4SI, "vmoduw", CONST, umodv4si3) -BU_P10V_AV_2 (MULHS_V2DI, "vmulhsd", CONST, smulv2di3_highpart) -BU_P10V_AV_2 (MULHS_V4SI, "vmulhsw", CONST, smulv4si3_highpart) -BU_P10V_AV_2 (MULHU_V2DI, "vmulhud", CONST, umulv2di3_highpart) -BU_P10V_AV_2 (MULHU_V4SI, "vmulhuw", CONST, umulv4si3_highpart) -BU_P10V_AV_2 (MULLD_V2DI, "vmulld", CONST, mulv2di3) - -BU_P10V_VSX_1 (VXXSPLTIW_V4SI, "vxxspltiw_v4si", CONST, xxspltiw_v4si) -BU_P10V_VSX_1 (VXXSPLTIW_V4SF, "vxxspltiw_v4sf", CONST, xxspltiw_v4sf) - -BU_P10V_VSX_1 (VXXSPLTID, "vxxspltidp", CONST, xxspltidp_v2df) - -BU_P10V_VSX_3 (VXXSPLTI32DX_V4SI, "vxxsplti32dx_v4si", CONST, xxsplti32dx_v4si) -BU_P10V_VSX_3 (VXXSPLTI32DX_V4SF, "vxxsplti32dx_v4sf", CONST, xxsplti32dx_v4sf) - -BU_P10V_VSX_3 (VXXBLEND_V16QI, "xxblend_v16qi", CONST, xxblend_v16qi) -BU_P10V_VSX_3 (VXXBLEND_V8HI, "xxblend_v8hi", CONST, xxblend_v8hi) -BU_P10V_VSX_3 (VXXBLEND_V4SI, "xxblend_v4si", CONST, xxblend_v4si) -BU_P10V_VSX_3 (VXXBLEND_V2DI, "xxblend_v2di", CONST, xxblend_v2di) -BU_P10V_VSX_3 (VXXBLEND_V4SF, "xxblend_v4sf", CONST, xxblend_v4sf) -BU_P10V_VSX_3 (VXXBLEND_V2DF, "xxblend_v2df", CONST, xxblend_v2df) - -BU_P10V_VSX_4 (VXXPERMX, "xxpermx", CONST, xxpermx) - -BU_P10V_AV_1 (VSTRIBR, "vstribr", CONST, vstrir_v16qi) -BU_P10V_AV_1 (VSTRIHR, "vstrihr", CONST, vstrir_v8hi) -BU_P10V_AV_1 (VSTRIBL, "vstribl", CONST, vstril_v16qi) -BU_P10V_AV_1 (VSTRIHL, "vstrihl", CONST, vstril_v8hi) - -BU_P10V_AV_1 (VSTRIBR_P, "vstribr_p", CONST, vstrir_p_v16qi) -BU_P10V_AV_1 (VSTRIHR_P, "vstrihr_p", CONST, vstrir_p_v8hi) -BU_P10V_AV_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi) -BU_P10V_AV_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi) - -BU_P10V_VSX_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros", CONST, xvtlsbbz) -BU_P10V_VSX_1 (XVTLSBB_ONES, "xvtlsbb_all_ones", CONST, xvtlsbbo) - -BU_P10V_AV_1 (MTVSRBM, "mtvsrbm", CONST, vec_mtvsr_v16qi) -BU_P10V_AV_1 (MTVSRHM, "mtvsrhm", CONST, vec_mtvsr_v8hi) -BU_P10V_AV_1 (MTVSRWM, "mtvsrwm", CONST, vec_mtvsr_v4si) -BU_P10V_AV_1 (MTVSRDM, "mtvsrdm", CONST, vec_mtvsr_v2di) -BU_P10V_AV_1 (MTVSRQM, "mtvsrqm", CONST, vec_mtvsr_v1ti) -BU_P10V_AV_2 (VCNTMBB, "cntmbb", CONST, vec_cntmb_v16qi) -BU_P10V_AV_2 (VCNTMBH, "cntmbh", CONST, vec_cntmb_v8hi) -BU_P10V_AV_2 (VCNTMBW, "cntmbw", CONST, vec_cntmb_v4si) -BU_P10V_AV_2 (VCNTMBD, "cntmbd", CONST, vec_cntmb_v2di) -BU_P10V_AV_1 (VEXPANDMB, "vexpandmb", CONST, vec_expand_v16qi) -BU_P10V_AV_1 (VEXPANDMH, "vexpandmh", CONST, vec_expand_v8hi) -BU_P10V_AV_1 (VEXPANDMW, "vexpandmw", CONST, vec_expand_v4si) -BU_P10V_AV_1 (VEXPANDMD, "vexpandmd", CONST, vec_expand_v2di) -BU_P10V_AV_1 (VEXPANDMQ, "vexpandmq", CONST, vec_expand_v1ti) -BU_P10V_AV_1 (VEXTRACTMB, "vextractmb", CONST, vec_extract_v16qi) -BU_P10V_AV_1 (VEXTRACTMH, "vextractmh", CONST, vec_extract_v8hi) -BU_P10V_AV_1 (VEXTRACTMW, "vextractmw", CONST, vec_extract_v4si) -BU_P10V_AV_1 (VEXTRACTMD, "vextractmd", CONST, vec_extract_v2di) -BU_P10V_AV_1 (VEXTRACTMQ, "vextractmq", CONST, vec_extract_v1ti) - -/* Overloaded vector builtins for ISA 3.1 (power10). */ -BU_P10_OVERLOAD_2 (CLRL, "clrl") -BU_P10_OVERLOAD_2 (CLRR, "clrr") -BU_P10_OVERLOAD_2 (GNB, "gnb") -BU_P10_OVERLOAD_4 (XXEVAL, "xxeval") -BU_P10_OVERLOAD_2 (XXGENPCVM, "xxgenpcvm") - -BU_P10_OVERLOAD_3 (EXTRACTL, "extractl") -BU_P10_OVERLOAD_3 (EXTRACTH, "extracth") -BU_P10_OVERLOAD_3 (INSERTL, "insertl") -BU_P10_OVERLOAD_3 (INSERTH, "inserth") -BU_P10_OVERLOAD_3 (REPLACE_ELT, "replace_elt") -BU_P10_OVERLOAD_3 (REPLACE_UN, "replace_un") -BU_P10_OVERLOAD_3 (SLDB, "sldb") -BU_P10_OVERLOAD_3 (SRDB, "srdb") - -BU_P10_OVERLOAD_1 (VSTRIR, "strir") -BU_P10_OVERLOAD_1 (VSTRIL, "stril") - -BU_P10_OVERLOAD_1 (VSTRIR_P, "strir_p") -BU_P10_OVERLOAD_1 (VSTRIL_P, "stril_p") - -BU_P10_OVERLOAD_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros") -BU_P10_OVERLOAD_1 (XVTLSBB_ONES, "xvtlsbb_all_ones") - -BU_P10_OVERLOAD_2 (MULH, "mulh") -BU_P10_OVERLOAD_2 (DIVE, "dive") -BU_P10_OVERLOAD_2 (MOD, "mod") - -BU_P10_OVERLOAD_1 (MTVSRBM, "mtvsrbm") -BU_P10_OVERLOAD_1 (MTVSRHM, "mtvsrhm") -BU_P10_OVERLOAD_1 (MTVSRWM, "mtvsrwm") -BU_P10_OVERLOAD_1 (MTVSRDM, "mtvsrdm") -BU_P10_OVERLOAD_1 (MTVSRQM, "mtvsrqm") -BU_P10_OVERLOAD_2 (VCNTM, "cntm") -BU_P10_OVERLOAD_1 (VEXPANDM, "vexpandm") -BU_P10_OVERLOAD_1 (VEXTRACTM, "vextractm") -BU_P10_OVERLOAD_1 (XXSPLTIW, "xxspltiw") -BU_P10_OVERLOAD_1 (XXSPLTID, "xxspltid") -BU_P10_OVERLOAD_3 (XXSPLTI32DX, "xxsplti32dx") -BU_P10_OVERLOAD_3 (XXBLEND, "xxblend") -BU_P10_OVERLOAD_4 (XXPERMX, "xxpermx") - -/* 1 argument crypto functions. */ -BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox_v2di) -BU_CRYPTO_1 (VSBOX_BE, "vsbox_be", CONST, crypto_vsbox_v16qi) - -/* 2 argument crypto functions. */ -BU_CRYPTO_2 (VCIPHER, "vcipher", CONST, crypto_vcipher_v2di) -BU_CRYPTO_2 (VCIPHER_BE, "vcipher_be", CONST, crypto_vcipher_v16qi) -BU_CRYPTO_2 (VCIPHERLAST, "vcipherlast", - CONST, crypto_vcipherlast_v2di) -BU_CRYPTO_2 (VCIPHERLAST_BE, "vcipherlast_be", - CONST, crypto_vcipherlast_v16qi) -BU_CRYPTO_2 (VNCIPHER, "vncipher", CONST, crypto_vncipher_v2di) -BU_CRYPTO_2 (VNCIPHER_BE, "vncipher_be", CONST, crypto_vncipher_v16qi) -BU_CRYPTO_2 (VNCIPHERLAST, "vncipherlast", - CONST, crypto_vncipherlast_v2di) -BU_CRYPTO_2 (VNCIPHERLAST_BE, "vncipherlast_be", - CONST, crypto_vncipherlast_v16qi) -BU_CRYPTO_2A (VPMSUMB, "vpmsumb", CONST, crypto_vpmsumb) -BU_CRYPTO_2A (VPMSUMH, "vpmsumh", CONST, crypto_vpmsumh) -BU_CRYPTO_2A (VPMSUMW, "vpmsumw", CONST, crypto_vpmsumw) -BU_CRYPTO_2A (VPMSUMD, "vpmsumd", CONST, crypto_vpmsumd) - -/* 3 argument crypto functions. */ -BU_CRYPTO_3A (VPERMXOR_V2DI, "vpermxor_v2di", CONST, crypto_vpermxor_v2di) -BU_CRYPTO_3A (VPERMXOR_V4SI, "vpermxor_v4si", CONST, crypto_vpermxor_v4si) -BU_CRYPTO_3A (VPERMXOR_V8HI, "vpermxor_v8hi", CONST, crypto_vpermxor_v8hi) -BU_CRYPTO_3A (VPERMXOR_V16QI, "vpermxor_v16qi", CONST, crypto_vpermxor_v16qi) -BU_CRYPTO_3 (VSHASIGMAW, "vshasigmaw", CONST, crypto_vshasigmaw) -BU_CRYPTO_3 (VSHASIGMAD, "vshasigmad", CONST, crypto_vshasigmad) - -/* 2 argument crypto overloaded functions. */ -BU_CRYPTO_OVERLOAD_2A (VPMSUM, "vpmsum") - -/* 3 argument crypto overloaded functions. */ -BU_CRYPTO_OVERLOAD_3A (VPERMXOR, "vpermxor") -BU_CRYPTO_OVERLOAD_3 (VSHASIGMA, "vshasigma") - -BU_P10_OVERLOAD_1 (SIGNEXT, "vsignextq") - -/* HTM functions. */ -BU_HTM_1 (TABORT, "tabort", CR, tabort) -BU_HTM_3 (TABORTDC, "tabortdc", CR, tabortdc) -BU_HTM_3 (TABORTDCI, "tabortdci", CR, tabortdci) -BU_HTM_3 (TABORTWC, "tabortwc", CR, tabortwc) -BU_HTM_3 (TABORTWCI, "tabortwci", CR, tabortwci) -BU_HTM_1 (TBEGIN, "tbegin", CR, tbegin) -BU_HTM_0 (TCHECK, "tcheck", CR, tcheck) -BU_HTM_1 (TEND, "tend", CR, tend) -BU_HTM_0 (TENDALL, "tendall", CR, tend) -BU_HTM_0 (TRECHKPT, "trechkpt", CR, trechkpt) -BU_HTM_1 (TRECLAIM, "treclaim", CR, treclaim) -BU_HTM_0 (TRESUME, "tresume", CR, tsr) -BU_HTM_0 (TSUSPEND, "tsuspend", CR, tsr) -BU_HTM_1 (TSR, "tsr", CR, tsr) -BU_HTM_0 (TTEST, "ttest", CR, ttest) - -BU_HTM_0 (GET_TFHAR, "get_tfhar", SPR, nothing) -BU_HTM_V1 (SET_TFHAR, "set_tfhar", SPR, nothing) -BU_HTM_0 (GET_TFIAR, "get_tfiar", SPR, nothing) -BU_HTM_V1 (SET_TFIAR, "set_tfiar", SPR, nothing) -BU_HTM_0 (GET_TEXASR, "get_texasr", SPR, nothing) -BU_HTM_V1 (SET_TEXASR, "set_texasr", SPR, nothing) -BU_HTM_0 (GET_TEXASRU, "get_texasru", SPR, nothing) -BU_HTM_V1 (SET_TEXASRU, "set_texasru", SPR, nothing) - - -/* Power7 builtins, that aren't VSX instructions. */ -BU_SPECIAL_X (POWER7_BUILTIN_BPERMD, "__builtin_bpermd", RS6000_BTM_POPCNTD, - RS6000_BTC_CONST) - -/* Miscellaneous builtins. */ -BU_SPECIAL_X (RS6000_BUILTIN_RECIP, "__builtin_recipdiv", RS6000_BTM_FRE, - RS6000_BTC_FP) - -BU_SPECIAL_X (RS6000_BUILTIN_RECIPF, "__builtin_recipdivf", RS6000_BTM_FRES, - RS6000_BTC_FP) - -BU_SPECIAL_X (RS6000_BUILTIN_RSQRT, "__builtin_rsqrt", RS6000_BTM_FRSQRTE, - RS6000_BTC_FP) - -BU_SPECIAL_X (RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf", RS6000_BTM_FRSQRTES, - RS6000_BTC_FP) - -BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase", - RS6000_BTM_ALWAYS, RS6000_BTC_MISC) - -BU_SPECIAL_X (RS6000_BUILTIN_MFTB, "__builtin_ppc_mftb", - RS6000_BTM_ALWAYS, RS6000_BTC_MISC) - -BU_SPECIAL_X (RS6000_BUILTIN_MFFS, "__builtin_mffs", - RS6000_BTM_ALWAYS, RS6000_BTC_MISC) - -BU_SPECIAL_X (RS6000_BUILTIN_MFFSL, "__builtin_mffsl", - RS6000_BTM_ALWAYS, RS6000_BTC_MISC) - -RS6000_BUILTIN_X (RS6000_BUILTIN_MTFSF, "__builtin_mtfsf", - RS6000_BTM_ALWAYS, - RS6000_BTC_MISC | RS6000_BTC_UNARY | RS6000_BTC_VOID, - CODE_FOR_rs6000_mtfsf) - -RS6000_BUILTIN_X (RS6000_BUILTIN_MTFSB0, "__builtin_mtfsb0", - RS6000_BTM_ALWAYS, - RS6000_BTC_MISC | RS6000_BTC_UNARY | RS6000_BTC_VOID, - CODE_FOR_rs6000_mtfsb0) - -RS6000_BUILTIN_X (RS6000_BUILTIN_MTFSB1, "__builtin_mtfsb1", - RS6000_BTM_ALWAYS, - RS6000_BTC_MISC | RS6000_BTC_UNARY | RS6000_BTC_VOID, - CODE_FOR_rs6000_mtfsb1) - -RS6000_BUILTIN_X (RS6000_BUILTIN_SET_FPSCR_RN, "__builtin_set_fpscr_rn", - RS6000_BTM_ALWAYS, - RS6000_BTC_MISC | RS6000_BTC_UNARY| RS6000_BTC_VOID, - CODE_FOR_rs6000_set_fpscr_rn) - -RS6000_BUILTIN_X (RS6000_BUILTIN_SET_FPSCR_DRN, "__builtin_set_fpscr_drn", - RS6000_BTM_DFP, - RS6000_BTC_MISC | RS6000_BTM_64BIT | RS6000_BTC_UNARY - | RS6000_BTC_VOID, - CODE_FOR_rs6000_set_fpscr_drn) - -BU_SPECIAL_X (RS6000_BUILTIN_CPU_INIT, "__builtin_cpu_init", - RS6000_BTM_ALWAYS, RS6000_BTC_MISC) - -BU_SPECIAL_X (RS6000_BUILTIN_CPU_IS, "__builtin_cpu_is", - RS6000_BTM_ALWAYS, RS6000_BTC_MISC) - -BU_SPECIAL_X (RS6000_BUILTIN_CPU_SUPPORTS, "__builtin_cpu_supports", - RS6000_BTM_ALWAYS, RS6000_BTC_MISC) - -/* Darwin CfString builtin. */ -BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS, - RS6000_BTC_MISC) - -/* POWER10 MMA builtins. */ -BU_P10V_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn) -BU_P10V_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16) - -BU_MMA_PAIR_LD (LXVP, "lxvp", MISC) -BU_MMA_PAIR_ST (STXVP, "stxvp", PAIR) - -BU_MMA_1 (XXMFACC, "xxmfacc", QUAD, mma_xxmfacc) -BU_MMA_1 (XXMTACC, "xxmtacc", QUAD, mma_xxmtacc) -BU_MMA_1 (XXSETACCZ, "xxsetaccz", MISC, mma_xxsetaccz) - -BU_MMA_2 (DISASSEMBLE_ACC, "disassemble_acc", QUAD, mma_disassemble_acc) -BU_MMA_V2 (DISASSEMBLE_PAIR, "disassemble_pair", PAIR, vsx_disassemble_pair) -BU_COMPAT (VSX_BUILTIN_DISASSEMBLE_PAIR, "mma_disassemble_pair") - -BU_MMA_V3 (BUILD_PAIR, "build_pair", MISC, vsx_assemble_pair) -BU_MMA_V3 (ASSEMBLE_PAIR, "assemble_pair", MISC, vsx_assemble_pair) -BU_COMPAT (VSX_BUILTIN_ASSEMBLE_PAIR, "mma_assemble_pair") -BU_MMA_3 (XVBF16GER2, "xvbf16ger2", MISC, mma_xvbf16ger2) -BU_MMA_3 (XVF16GER2, "xvf16ger2", MISC, mma_xvf16ger2) -BU_MMA_3 (XVF32GER, "xvf32ger", MISC, mma_xvf32ger) -BU_MMA_3 (XVF64GER, "xvf64ger", PAIR, mma_xvf64ger) -BU_MMA_3 (XVI4GER8, "xvi4ger8", MISC, mma_xvi4ger8) -BU_MMA_3 (XVI8GER4, "xvi8ger4", MISC, mma_xvi8ger4) -BU_MMA_3 (XVI16GER2, "xvi16ger2", MISC, mma_xvi16ger2) -BU_MMA_3 (XVI16GER2S, "xvi16ger2s", MISC, mma_xvi16ger2s) -BU_MMA_3 (XVBF16GER2NN, "xvbf16ger2nn", QUAD, mma_xvbf16ger2nn) -BU_MMA_3 (XVBF16GER2NP, "xvbf16ger2np", QUAD, mma_xvbf16ger2np) -BU_MMA_3 (XVBF16GER2PN, "xvbf16ger2pn", QUAD, mma_xvbf16ger2pn) -BU_MMA_3 (XVBF16GER2PP, "xvbf16ger2pp", QUAD, mma_xvbf16ger2pp) -BU_MMA_3 (XVF16GER2NN, "xvf16ger2nn", QUAD, mma_xvf16ger2nn) -BU_MMA_3 (XVF16GER2NP, "xvf16ger2np", QUAD, mma_xvf16ger2np) -BU_MMA_3 (XVF16GER2PN, "xvf16ger2pn", QUAD, mma_xvf16ger2pn) -BU_MMA_3 (XVF16GER2PP, "xvf16ger2pp", QUAD, mma_xvf16ger2pp) -BU_MMA_3 (XVF32GERNN, "xvf32gernn", QUAD, mma_xvf32gernn) -BU_MMA_3 (XVF32GERNP, "xvf32gernp", QUAD, mma_xvf32gernp) -BU_MMA_3 (XVF32GERPN, "xvf32gerpn", QUAD, mma_xvf32gerpn) -BU_MMA_3 (XVF32GERPP, "xvf32gerpp", QUAD, mma_xvf32gerpp) -BU_MMA_3 (XVF64GERNN, "xvf64gernn", QUADPAIR, mma_xvf64gernn) -BU_MMA_3 (XVF64GERNP, "xvf64gernp", QUADPAIR, mma_xvf64gernp) -BU_MMA_3 (XVF64GERPN, "xvf64gerpn", QUADPAIR, mma_xvf64gerpn) -BU_MMA_3 (XVF64GERPP, "xvf64gerpp", QUADPAIR, mma_xvf64gerpp) -BU_MMA_3 (XVI4GER8PP, "xvi4ger8pp", QUAD, mma_xvi4ger8pp) -BU_MMA_3 (XVI8GER4PP, "xvi8ger4pp", QUAD, mma_xvi8ger4pp) -BU_MMA_3 (XVI8GER4SPP, "xvi8ger4spp", QUAD, mma_xvi8ger4spp) -BU_MMA_3 (XVI16GER2PP, "xvi16ger2pp", QUAD, mma_xvi16ger2pp) -BU_MMA_3 (XVI16GER2SPP, "xvi16ger2spp", QUAD, mma_xvi16ger2spp) - -BU_MMA_5 (BUILD_ACC, "build_acc", MISC, mma_assemble_acc) -BU_MMA_5 (ASSEMBLE_ACC, "assemble_acc", MISC, mma_assemble_acc) -BU_MMA_5 (PMXVF32GER, "pmxvf32ger", MISC, mma_pmxvf32ger) -BU_MMA_5 (PMXVF64GER, "pmxvf64ger", PAIR, mma_pmxvf64ger) -BU_MMA_5 (PMXVF32GERNN, "pmxvf32gernn", QUAD, mma_pmxvf32gernn) -BU_MMA_5 (PMXVF32GERNP, "pmxvf32gernp", QUAD, mma_pmxvf32gernp) -BU_MMA_5 (PMXVF32GERPN, "pmxvf32gerpn", QUAD, mma_pmxvf32gerpn) -BU_MMA_5 (PMXVF32GERPP, "pmxvf32gerpp", QUAD, mma_pmxvf32gerpp) -BU_MMA_5 (PMXVF64GERNN, "pmxvf64gernn", QUADPAIR, mma_pmxvf64gernn) -BU_MMA_5 (PMXVF64GERNP, "pmxvf64gernp", QUADPAIR, mma_pmxvf64gernp) -BU_MMA_5 (PMXVF64GERPN, "pmxvf64gerpn", QUADPAIR, mma_pmxvf64gerpn) -BU_MMA_5 (PMXVF64GERPP, "pmxvf64gerpp", QUADPAIR, mma_pmxvf64gerpp) - -BU_MMA_6 (PMXVBF16GER2, "pmxvbf16ger2", MISC, mma_pmxvbf16ger2) -BU_MMA_6 (PMXVF16GER2, "pmxvf16ger2", MISC, mma_pmxvf16ger2) -BU_MMA_6 (PMXVI4GER8, "pmxvi4ger8", MISC, mma_pmxvi4ger8) -BU_MMA_6 (PMXVI8GER4, "pmxvi8ger4", MISC, mma_pmxvi8ger4) -BU_MMA_6 (PMXVI16GER2, "pmxvi16ger2", MISC, mma_pmxvi16ger2) -BU_MMA_6 (PMXVI16GER2S, "pmxvi16ger2s", MISC, mma_pmxvi16ger2s) -BU_MMA_6 (PMXVBF16GER2NN, "pmxvbf16ger2nn", QUAD, mma_pmxvbf16ger2nn) -BU_MMA_6 (PMXVBF16GER2NP, "pmxvbf16ger2np", QUAD, mma_pmxvbf16ger2np) -BU_MMA_6 (PMXVBF16GER2PN, "pmxvbf16ger2pn", QUAD, mma_pmxvbf16ger2pn) -BU_MMA_6 (PMXVBF16GER2PP, "pmxvbf16ger2pp", QUAD, mma_pmxvbf16ger2pp) -BU_MMA_6 (PMXVF16GER2NN, "pmxvf16ger2nn", QUAD, mma_pmxvf16ger2nn) -BU_MMA_6 (PMXVF16GER2NP, "pmxvf16ger2np", QUAD, mma_pmxvf16ger2np) -BU_MMA_6 (PMXVF16GER2PN, "pmxvf16ger2pn", QUAD, mma_pmxvf16ger2pn) -BU_MMA_6 (PMXVF16GER2PP, "pmxvf16ger2pp", QUAD, mma_pmxvf16ger2pp) -BU_MMA_6 (PMXVI4GER8PP, "pmxvi4ger8pp", QUAD, mma_pmxvi4ger8pp) -BU_MMA_6 (PMXVI8GER4PP, "pmxvi8ger4pp", QUAD, mma_pmxvi8ger4pp) -BU_MMA_6 (PMXVI8GER4SPP, "pmxvi8ger4spp", QUAD, mma_pmxvi8ger4spp) -BU_MMA_6 (PMXVI16GER2PP, "pmxvi16ger2pp", QUAD, mma_pmxvi16ger2pp) -BU_MMA_6 (PMXVI16GER2SPP, "pmxvi16ger2spp", QUAD, mma_pmxvi16ger2spp) diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index d0fe960..594d09e 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -89,20 +89,6 @@ #define TARGET_NO_PROTOTYPE 0 #endif -struct builtin_compatibility -{ - const enum rs6000_builtins code; - const char *const name; -}; - -struct builtin_description -{ - const HOST_WIDE_INT mask; - const enum insn_code icode; - const char *const name; - const enum rs6000_builtins code; -}; - /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */ static const struct { @@ -184,127 +170,6 @@ static const struct static rtx rs6000_expand_new_builtin (tree, rtx, rtx, machine_mode, int); static bool rs6000_gimple_fold_new_builtin (gimple_stmt_iterator *gsi); - - -/* Hash table to keep track of the argument types for builtin functions. */ - -struct GTY((for_user)) builtin_hash_struct -{ - tree type; - machine_mode mode[4]; /* return value + 3 arguments. */ - unsigned char uns_p[4]; /* and whether the types are unsigned. */ -}; - -struct builtin_hasher : ggc_ptr_hash -{ - static hashval_t hash (builtin_hash_struct *); - static bool equal (builtin_hash_struct *, builtin_hash_struct *); -}; - -static GTY (()) hash_table *builtin_hash_table; - -/* Hash function for builtin functions with up to 3 arguments and a return - type. */ -hashval_t -builtin_hasher::hash (builtin_hash_struct *bh) -{ - unsigned ret = 0; - int i; - - for (i = 0; i < 4; i++) - { - ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]); - ret = (ret * 2) + bh->uns_p[i]; - } - - return ret; -} - -/* Compare builtin hash entries H1 and H2 for equivalence. */ -bool -builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2) -{ - return ((p1->mode[0] == p2->mode[0]) - && (p1->mode[1] == p2->mode[1]) - && (p1->mode[2] == p2->mode[2]) - && (p1->mode[3] == p2->mode[3]) - && (p1->uns_p[0] == p2->uns_p[0]) - && (p1->uns_p[1] == p2->uns_p[1]) - && (p1->uns_p[2] == p2->uns_p[2]) - && (p1->uns_p[3] == p2->uns_p[3])); -} - - -/* Table that classifies rs6000 builtin functions (pure, const, etc.). */ -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \ - { NAME, ICODE, MASK, ATTR }, - -struct rs6000_builtin_info_type { - const char *name; - const enum insn_code icode; - const HOST_WIDE_INT mask; - const unsigned attr; -}; - -static const struct rs6000_builtin_info_type rs6000_builtin_info[] = -{ -#include "rs6000-builtin.def" -}; - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - /* Nonzero if we can use a floating-point register to pass this arg. */ #define USE_FP_FOR_ARG_P(CUM,MODE) \ @@ -3130,367 +2995,6 @@ const char *rs6000_type_string (tree type_node) return "unknown"; } -static const struct builtin_compatibility bdesc_compat[] = -{ -#define RS6000_BUILTIN_COMPAT -#include "rs6000-builtin.def" -}; -#undef RS6000_BUILTIN_COMPAT - -/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_3arg[] = -{ -#include "rs6000-builtin.def" -}; - -/* Simple quaternary operations: VECd = foo (VECa, VECb, VECc, VECd). */ - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_4arg[] = -{ -#include "rs6000-builtin.def" -}; - -/* DST operations: void foo (void *, const int, const char). */ - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_dst[] = -{ -#include "rs6000-builtin.def" -}; - -/* Simple binary operations: VECc = foo (VECa, VECb). */ - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_2arg[] = -{ -#include "rs6000-builtin.def" -}; - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -/* AltiVec predicates. */ - -static const struct builtin_description bdesc_altivec_preds[] = -{ -#include "rs6000-builtin.def" -}; - -/* ABS* operations. */ - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_abs[] = -{ -#include "rs6000-builtin.def" -}; - -/* Simple unary operations: VECb = foo (unsigned literal) or VECb = - foo (VECa). */ - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_1arg[] = -{ -#include "rs6000-builtin.def" -}; - -/* Simple no-argument operations: result = __builtin_darn_32 () */ - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_0arg[] = -{ -#include "rs6000-builtin.def" -}; - -/* HTM builtins. */ -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_htm[] = -{ -#include "rs6000-builtin.def" -}; - -/* MMA builtins. */ -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) \ - { MASK, ICODE, NAME, ENUM }, - -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) - -static const struct builtin_description bdesc_mma[] = -{ -#include "rs6000-builtin.def" -}; - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -/* Return true if a builtin function is overloaded. */ -bool -rs6000_overloaded_builtin_p (enum rs6000_builtins fncode) -{ - return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0; -} - -const char * -rs6000_overloaded_builtin_name (enum rs6000_builtins fncode) -{ - return rs6000_builtin_info[(int)fncode].name; -} - static rtx altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target) { @@ -3611,24 +3115,6 @@ swap_endian_selector_for_mode (machine_mode mode) gen_rtvec_v (16, perm))); } -/* Return the appropriate SPR number associated with the given builtin. */ -static inline HOST_WIDE_INT -htm_spr_num (enum rs6000_builtins code) -{ - if (code == HTM_BUILTIN_GET_TFHAR - || code == HTM_BUILTIN_SET_TFHAR) - return TFHAR_SPR; - else if (code == HTM_BUILTIN_GET_TFIAR - || code == HTM_BUILTIN_SET_TFIAR) - return TFIAR_SPR; - else if (code == HTM_BUILTIN_GET_TEXASR - || code == HTM_BUILTIN_SET_TEXASR) - return TEXASR_SPR; - gcc_assert (code == HTM_BUILTIN_GET_TEXASRU - || code == HTM_BUILTIN_SET_TEXASRU); - return TEXASRU_SPR; -} - /* Return the correct ICODE value depending on whether we are setting or reading the HTM SPRs. */ static inline enum insn_code @@ -3768,18 +3254,6 @@ altivec_expand_vec_ext_builtin (tree exp, rtx target) return target; } -/* Check whether a builtin function is supported in this target - configuration. */ -bool -rs6000_builtin_is_supported_p (enum rs6000_builtins fncode) -{ - HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask; - if ((fnmask & rs6000_builtin_mask) != fnmask) - return false; - else - return true; -} - /* Raise an error message for a builtin function that is called without the appropriate target options being set. */ @@ -4005,190 +3479,6 @@ fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd) gsi_replace (gsi, g, true); } -/* Expand the MMA built-ins early, so that we can convert the pass-by-reference - __vector_quad arguments into pass-by-value arguments, leading to more - efficient code generation. */ - -bool -rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi) -{ - gimple *stmt = gsi_stmt (*gsi); - tree fndecl = gimple_call_fndecl (stmt); - enum rs6000_builtins fncode - = (enum rs6000_builtins) DECL_MD_FUNCTION_CODE (fndecl); - unsigned attr = rs6000_builtin_info[fncode].attr; - - if ((attr & RS6000_BTC_GIMPLE) == 0) - return false; - - unsigned nopnds = (attr & RS6000_BTC_OPND_MASK); - gimple_seq new_seq = NULL; - gimple *new_call; - tree new_decl; - - if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC - || fncode == VSX_BUILTIN_DISASSEMBLE_PAIR) - { - /* This is an MMA disassemble built-in function. */ - push_gimplify_context (true); - unsigned nvec = (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) ? 4 : 2; - tree dst_ptr = gimple_call_arg (stmt, 0); - tree src_ptr = gimple_call_arg (stmt, 1); - tree src_type = TREE_TYPE (src_ptr); - tree src = create_tmp_reg_or_ssa_name (TREE_TYPE (src_type)); - gimplify_assign (src, build_simple_mem_ref (src_ptr), &new_seq); - - /* If we are not disassembling an accumulator/pair or our destination is - another accumulator/pair, then just copy the entire thing as is. */ - if ((fncode == MMA_BUILTIN_DISASSEMBLE_ACC - && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_quad_type_node) - || (fncode == VSX_BUILTIN_DISASSEMBLE_PAIR - && TREE_TYPE (TREE_TYPE (dst_ptr)) == vector_pair_type_node)) - { - tree dst = build_simple_mem_ref (build1 (VIEW_CONVERT_EXPR, - src_type, dst_ptr)); - gimplify_assign (dst, src, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - - /* If we're disassembling an accumulator into a different type, we need - to emit a xxmfacc instruction now, since we cannot do it later. */ - if (fncode == MMA_BUILTIN_DISASSEMBLE_ACC) - { - new_decl = rs6000_builtin_decls[MMA_BUILTIN_XXMFACC_INTERNAL]; - new_call = gimple_build_call (new_decl, 1, src); - src = create_tmp_reg_or_ssa_name (vector_quad_type_node); - gimple_call_set_lhs (new_call, src); - gimple_seq_add_stmt (&new_seq, new_call); - } - - /* Copy the accumulator/pair vector by vector. */ - new_decl = rs6000_builtin_decls[fncode + 1]; - tree dst_type = build_pointer_type_for_mode (unsigned_V16QI_type_node, - ptr_mode, true); - tree dst_base = build1 (VIEW_CONVERT_EXPR, dst_type, dst_ptr); - for (unsigned i = 0; i < nvec; i++) - { - unsigned index = WORDS_BIG_ENDIAN ? i : nvec - 1 - i; - tree dst = build2 (MEM_REF, unsigned_V16QI_type_node, dst_base, - build_int_cst (dst_type, index * 16)); - tree dstssa = create_tmp_reg_or_ssa_name (unsigned_V16QI_type_node); - new_call = gimple_build_call (new_decl, 2, src, - build_int_cstu (uint16_type_node, i)); - gimple_call_set_lhs (new_call, dstssa); - gimple_seq_add_stmt (&new_seq, new_call); - gimplify_assign (dst, dstssa, &new_seq); - } - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - else if (fncode == VSX_BUILTIN_LXVP) - { - push_gimplify_context (true); - tree offset = gimple_call_arg (stmt, 0); - tree ptr = gimple_call_arg (stmt, 1); - tree lhs = gimple_call_lhs (stmt); - if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) - ptr = build1 (VIEW_CONVERT_EXPR, - build_pointer_type (vector_pair_type_node), ptr); - tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, - TREE_TYPE (ptr), ptr, offset)); - gimplify_assign (lhs, mem, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - else if (fncode == VSX_BUILTIN_STXVP) - { - push_gimplify_context (true); - tree src = gimple_call_arg (stmt, 0); - tree offset = gimple_call_arg (stmt, 1); - tree ptr = gimple_call_arg (stmt, 2); - if (TREE_TYPE (TREE_TYPE (ptr)) != vector_pair_type_node) - ptr = build1 (VIEW_CONVERT_EXPR, - build_pointer_type (vector_pair_type_node), ptr); - tree mem = build_simple_mem_ref (build2 (POINTER_PLUS_EXPR, - TREE_TYPE (ptr), ptr, offset)); - gimplify_assign (mem, src, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - return true; - } - - /* Convert this built-in into an internal version that uses pass-by-value - arguments. The internal built-in follows immediately after this one. */ - new_decl = rs6000_builtin_decls[fncode + 1]; - tree lhs, op[MAX_MMA_OPERANDS]; - tree acc = gimple_call_arg (stmt, 0); - push_gimplify_context (true); - - if ((attr & RS6000_BTC_QUAD) != 0) - { - /* This built-in has a pass-by-reference accumulator input, so load it - into a temporary accumulator for use as a pass-by-value input. */ - op[0] = create_tmp_reg_or_ssa_name (vector_quad_type_node); - for (unsigned i = 1; i < nopnds; i++) - op[i] = gimple_call_arg (stmt, i); - gimplify_assign (op[0], build_simple_mem_ref (acc), &new_seq); - } - else - { - /* This built-in does not use its pass-by-reference accumulator argument - as an input argument, so remove it from the input list. */ - nopnds--; - for (unsigned i = 0; i < nopnds; i++) - op[i] = gimple_call_arg (stmt, i + 1); - } - - switch (nopnds) - { - case 0: - new_call = gimple_build_call (new_decl, 0); - break; - case 1: - new_call = gimple_build_call (new_decl, 1, op[0]); - break; - case 2: - new_call = gimple_build_call (new_decl, 2, op[0], op[1]); - break; - case 3: - new_call = gimple_build_call (new_decl, 3, op[0], op[1], op[2]); - break; - case 4: - new_call = gimple_build_call (new_decl, 4, op[0], op[1], op[2], op[3]); - break; - case 5: - new_call = gimple_build_call (new_decl, 5, op[0], op[1], op[2], op[3], - op[4]); - break; - case 6: - new_call = gimple_build_call (new_decl, 6, op[0], op[1], op[2], op[3], - op[4], op[5]); - break; - case 7: - new_call = gimple_build_call (new_decl, 7, op[0], op[1], op[2], op[3], - op[4], op[5], op[6]); - break; - default: - gcc_unreachable (); - } - - if (fncode == VSX_BUILTIN_BUILD_PAIR || fncode == VSX_BUILTIN_ASSEMBLE_PAIR) - lhs = create_tmp_reg_or_ssa_name (vector_pair_type_node); - else - lhs = create_tmp_reg_or_ssa_name (vector_quad_type_node); - gimple_call_set_lhs (new_call, lhs); - gimple_seq_add_stmt (&new_seq, new_call); - gimplify_assign (build_simple_mem_ref (acc), lhs, &new_seq); - pop_gimplify_context (NULL); - gsi_replace_with_seq (gsi, new_seq, true); - - return true; -} - /* Fold a machine-dependent built-in in GIMPLE. (For folding into a constant, use rs6000_fold_builtin.) */ @@ -7262,5 +6552,3 @@ rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, reload_completed = 0; epilogue_completed = 0; } - -#include "gt-rs6000-call.h" diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 14f6b31..c01ae00 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -272,9 +272,6 @@ extern void rs6000_call_darwin (rtx, rtx, rtx, rtx); extern void rs6000_sibcall_darwin (rtx, rtx, rtx, rtx); extern void rs6000_aix_asm_output_dwarf_table_ref (char *); extern void get_ppc476_thunk_name (char name[32]); -extern bool rs6000_overloaded_builtin_p (enum rs6000_builtins); -extern bool rs6000_builtin_is_supported_p (enum rs6000_builtins); -extern const char *rs6000_overloaded_builtin_name (enum rs6000_builtins); extern int rs6000_store_data_bypass_p (rtx_insn *, rtx_insn *); extern HOST_WIDE_INT rs6000_builtin_mask_calculate (void); extern void rs6000_asm_output_dwarf_pcrel (FILE *file, int size, diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 9fc1577..5c077cd 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -171,7 +171,6 @@ static int dbg_cost_ctrl; /* Built in types. */ tree rs6000_builtin_types[RS6000_BTI_MAX]; -tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; /* Flag to say the TOC is initialized */ int toc_initialized, need_toc_init; @@ -2585,8 +2584,6 @@ rs6000_debug_reg_global (void) (int)rs6000_sched_restricted_insns_priority); fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins", (int)END_BUILTINS); - fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins", - (int)RS6000_BUILTIN_COUNT); fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX", (int)TARGET_FLOAT128_ENABLE_TYPE); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index b12ee8b..4d2f88d 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -2344,62 +2344,6 @@ extern int frame_pointer_needed; | RS6000_BTM_MMA \ | RS6000_BTM_P10) -/* Define builtin enum index. */ - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -#define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_4(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_M(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, - -enum rs6000_builtins -{ -#include "rs6000-builtin.def" - - RS6000_BUILTIN_COUNT -}; - -#undef RS6000_BUILTIN_0 -#undef RS6000_BUILTIN_1 -#undef RS6000_BUILTIN_2 -#undef RS6000_BUILTIN_3 -#undef RS6000_BUILTIN_4 -#undef RS6000_BUILTIN_A -#undef RS6000_BUILTIN_D -#undef RS6000_BUILTIN_H -#undef RS6000_BUILTIN_M -#undef RS6000_BUILTIN_P -#undef RS6000_BUILTIN_X - -/* Mappings for overloaded builtins. */ -struct altivec_builtin_types -{ - enum rs6000_builtins code; - enum rs6000_builtins overloaded_code; - signed char ret_type; - signed char op1; - signed char op2; - signed char op3; -}; - enum rs6000_builtin_type_index { RS6000_BTI_NOT_OPAQUE, @@ -2600,7 +2544,6 @@ enum rs6000_builtin_type_index #define ptr_long_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long_unsigned]) extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; -extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; #ifndef USED_FOR_TARGET extern GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2]; diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index 3d3143a..98ddd97 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -18,7 +18,6 @@ # along with GCC; see the file COPYING3. If not see # . -TM_H += $(srcdir)/config/rs6000/rs6000-builtin.def TM_H += $(srcdir)/config/rs6000/rs6000-cpus.def TM_H += $(srcdir)/config/rs6000/rs6000-modes.h PASSES_EXTRA += $(srcdir)/config/rs6000/rs6000-passes.def -- cgit v1.1 From d9421a8dcac385b882e4551ab3e52da38058b230 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 14 Dec 2021 13:32:14 -0600 Subject: rs6000: Rename functions with "new" in their names While we had two sets of built-in functionality at the same time, I put "new" in the names of quite a few functions. Time to undo that. 2021-12-02 Bill Schmidt gcc/ * config/rs6000/rs6000-c.c (altivec_resolve_new_overloaded_builtin): Remove forward declaration. (rs6000_new_builtin_type_compatible): Rename to rs6000_builtin_type_compatible. (rs6000_builtin_type_compatible): Remove. (altivec_resolve_overloaded_builtin): Remove. (altivec_build_new_resolved_builtin): Rename to altivec_build_resolved_builtin. (altivec_resolve_new_overloaded_builtin): Rename to altivec_resolve_overloaded_builtin. Remove static keyword. Adjust called function names. * config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Remove forward declaration. (rs6000_gimple_fold_new_builtin): Likewise. (rs6000_invalid_new_builtin): Rename to rs6000_invalid_builtin. (rs6000_gimple_fold_builtin): Remove. (rs6000_new_builtin_valid_without_lhs): Rename to rs6000_builtin_valid_without_lhs. (rs6000_new_builtin_is_supported): Rename to rs6000_builtin_is_supported. (rs6000_gimple_fold_new_mma_builtin): Rename to rs6000_gimple_fold_mma_builtin. (rs6000_gimple_fold_new_builtin): Rename to rs6000_gimple_fold_builtin. Remove static keyword. Adjust called function names. (rs6000_expand_builtin): Remove. (new_cpu_expand_builtin): Rename to cpu_expand_builtin. (new_mma_expand_builtin): Rename to mma_expand_builtin. (new_htm_spr_num): Rename to htm_spr_num. (new_htm_expand_builtin): Rename to htm_expand_builtin. Change name of called function. (rs6000_expand_new_builtin): Rename to rs6000_expand_builtin. Remove static keyword. Adjust called function names. (rs6000_new_builtin_decl): Rename to rs6000_builtin_decl. Remove static keyword. (rs6000_builtin_decl): Remove. * config/rs6000/rs6000-gen-builtins.c (write_decls): In gnerated code, rename rs6000_new_builtin_is_supported to rs6000_builtin_is_supported. * config/rs6000/rs6000-internal.h (rs6000_invalid_new_builtin): Rename to rs6000_invalid_builtin. * config/rs6000/rs6000.c (rs6000_new_builtin_vectorized_function): Rename to rs6000_builtin_vectorized_function. (rs6000_new_builtin_md_vectorized_function): Rename to rs6000_builtin_md_vectorized_function. (rs6000_builtin_vectorized_function): Remove. (rs6000_builtin_md_vectorized_function): Remove. --- gcc/config/rs6000/rs6000-c.c | 120 +++++++++++--------------------- gcc/config/rs6000/rs6000-call.c | 99 ++++++++------------------ gcc/config/rs6000/rs6000-gen-builtins.c | 3 +- gcc/config/rs6000/rs6000-internal.h | 2 +- gcc/config/rs6000/rs6000.c | 31 ++------- 5 files changed, 80 insertions(+), 175 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index d44edf5..f790c72 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -37,9 +37,6 @@ #include "rs6000-internal.h" -static tree altivec_resolve_new_overloaded_builtin (location_t, tree, void *); - - /* Handle the machine specific pragma longcall. Its syntax is # pragma longcall ( TOGGLE ) @@ -817,7 +814,7 @@ is_float128_p (tree t) /* Return true iff ARGTYPE can be compatibly passed as PARMTYPE. */ static bool -rs6000_new_builtin_type_compatible (tree parmtype, tree argtype) +rs6000_builtin_type_compatible (tree parmtype, tree argtype) { if (parmtype == error_mark_node) return false; @@ -840,23 +837,6 @@ rs6000_new_builtin_type_compatible (tree parmtype, tree argtype) return lang_hooks.types_compatible_p (parmtype, argtype); } -static inline bool -rs6000_builtin_type_compatible (tree t, int id) -{ - tree builtin_type; - builtin_type = rs6000_builtin_type (id); - if (t == error_mark_node) - return false; - if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type)) - return true; - else if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 - && is_float128_p (t) && is_float128_p (builtin_type)) - return true; - else - return lang_hooks.types_compatible_p (t, builtin_type); -} - - /* In addition to calling fold_convert for EXPR of type TYPE, also call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be hiding there (PR47197). */ @@ -873,16 +853,6 @@ fully_fold_convert (tree type, tree expr) return result; } -/* Implementation of the resolve_overloaded_builtin target hook, to - support Altivec's overloaded builtins. */ - -tree -altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, - void *passed_arglist) -{ - return altivec_resolve_new_overloaded_builtin (loc, fndecl, passed_arglist); -} - /* Build a tree for a function call to an Altivec non-overloaded builtin. The overloaded builtin that matched the types and args is described by DESC. The N arguments are given in ARGS, respectively. @@ -891,10 +861,9 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, a small exception for vec_{all,any}_{ge,le} predicates. */ static tree -altivec_build_new_resolved_builtin (tree *args, int n, tree fntype, - tree ret_type, - rs6000_gen_builtins bif_id, - rs6000_gen_builtins ovld_id) +altivec_build_resolved_builtin (tree *args, int n, tree fntype, tree ret_type, + rs6000_gen_builtins bif_id, + rs6000_gen_builtins ovld_id) { tree argtypes = TYPE_ARG_TYPES (fntype); tree arg_type[MAX_OVLD_ARGS]; @@ -963,9 +932,9 @@ altivec_build_new_resolved_builtin (tree *args, int n, tree fntype, support Altivec's overloaded builtins. FIXME: This code needs to be brutally factored. */ -static tree -altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, - void *passed_arglist) +tree +altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, + void *passed_arglist) { vec *arglist = static_cast *> (passed_arglist); unsigned int nargs = vec_safe_length (arglist); @@ -1096,7 +1065,7 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, vec *params = make_tree_vector (); vec_safe_push (params, arg0); vec_safe_push (params, arg1); - tree call = altivec_resolve_new_overloaded_builtin + tree call = altivec_resolve_overloaded_builtin (loc, rs6000_builtin_decls_x[RS6000_OVLD_VEC_CMPEQ], params); /* Use save_expr to ensure that operands used more than once @@ -1106,7 +1075,7 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, params = make_tree_vector (); vec_safe_push (params, call); vec_safe_push (params, call); - return altivec_resolve_new_overloaded_builtin + return altivec_resolve_overloaded_builtin (loc, rs6000_builtin_decls_x[RS6000_OVLD_VEC_NOR], params); } /* Other types are errors. */ @@ -1165,9 +1134,8 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, add_sub_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_SUB]; tree call - = altivec_resolve_new_overloaded_builtin (loc, - add_sub_builtin, - params); + = altivec_resolve_overloaded_builtin (loc, add_sub_builtin, + params); tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1); tree ones_vector = build_vector_from_val (arg0_type, const1); tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type, @@ -1175,9 +1143,8 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, params = make_tree_vector (); vec_safe_push (params, call); vec_safe_push (params, and_expr); - return altivec_resolve_new_overloaded_builtin (loc, - add_sub_builtin, - params); + return altivec_resolve_overloaded_builtin (loc, add_sub_builtin, + params); } /* For {un}signed __int128s use the vaddeuqm/vsubeuqm instruction directly. */ @@ -1244,9 +1211,8 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, else as_c_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_SUBC]; - tree call1 = altivec_resolve_new_overloaded_builtin (loc, - as_c_builtin, - params); + tree call1 = altivec_resolve_overloaded_builtin (loc, as_c_builtin, + params); params = make_tree_vector (); vec_safe_push (params, arg0); vec_safe_push (params, arg1); @@ -1256,9 +1222,8 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, else as_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_SUB]; - tree call2 = altivec_resolve_new_overloaded_builtin (loc, - as_builtin, - params); + tree call2 = altivec_resolve_overloaded_builtin (loc, as_builtin, + params); tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1); tree ones_vector = build_vector_from_val (arg0_type, const1); tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type, @@ -1266,14 +1231,14 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, params = make_tree_vector (); vec_safe_push (params, call2); vec_safe_push (params, and_expr); - call2 = altivec_resolve_new_overloaded_builtin (loc, as_c_builtin, - params); + call2 = altivec_resolve_overloaded_builtin (loc, as_c_builtin, + params); params = make_tree_vector (); vec_safe_push (params, call1); vec_safe_push (params, call2); tree or_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_OR]; - return altivec_resolve_new_overloaded_builtin (loc, or_builtin, - params); + return altivec_resolve_overloaded_builtin (loc, or_builtin, + params); } /* For {un}signed __int128s use the vaddecuq/vsubbecuq instructions. This occurs through normal processing. */ @@ -1779,17 +1744,17 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, tree parmtype0 = TREE_VALUE (TYPE_ARG_TYPES (fntype)); tree parmtype1 = TREE_VALUE (TREE_CHAIN (TYPE_ARG_TYPES (fntype))); - if (rs6000_new_builtin_type_compatible (types[0], parmtype0) - && rs6000_new_builtin_type_compatible (types[1], parmtype1)) + if (rs6000_builtin_type_compatible (types[0], parmtype0) + && rs6000_builtin_type_compatible (types[1], parmtype1)) { if (rs6000_builtin_decl (instance->bifid, false) != error_mark_node - && rs6000_new_builtin_is_supported (instance->bifid)) + && rs6000_builtin_is_supported (instance->bifid)) { tree ret_type = TREE_TYPE (instance->fntype); - return altivec_build_new_resolved_builtin (args, n, fntype, - ret_type, - instance->bifid, - fcode); + return altivec_build_resolved_builtin (args, n, fntype, + ret_type, + instance->bifid, + fcode); } else unsupported_builtin = true; @@ -1837,17 +1802,17 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, tree parmtype0 = TREE_VALUE (TYPE_ARG_TYPES (fntype)); tree parmtype1 = TREE_VALUE (TREE_CHAIN (TYPE_ARG_TYPES (fntype))); - if (rs6000_new_builtin_type_compatible (types[0], parmtype0) - && rs6000_new_builtin_type_compatible (types[1], parmtype1)) + if (rs6000_builtin_type_compatible (types[0], parmtype0) + && rs6000_builtin_type_compatible (types[1], parmtype1)) { if (rs6000_builtin_decl (instance->bifid, false) != error_mark_node - && rs6000_new_builtin_is_supported (instance->bifid)) + && rs6000_builtin_is_supported (instance->bifid)) { tree ret_type = TREE_TYPE (instance->fntype); - return altivec_build_new_resolved_builtin (args, n, fntype, - ret_type, - instance->bifid, - fcode); + return altivec_build_resolved_builtin (args, n, fntype, + ret_type, + instance->bifid, + fcode); } else unsupported_builtin = true; @@ -1869,8 +1834,7 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, arg_i++) { tree parmtype = TREE_VALUE (nextparm); - if (!rs6000_new_builtin_type_compatible (types[arg_i], - parmtype)) + if (!rs6000_builtin_type_compatible (types[arg_i], parmtype)) { mismatch = true; break; @@ -1881,16 +1845,16 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, if (mismatch) continue; - supported = rs6000_new_builtin_is_supported (instance->bifid); + supported = rs6000_builtin_is_supported (instance->bifid); if (rs6000_builtin_decl (instance->bifid, false) != error_mark_node && supported) { tree fntype = rs6000_builtin_info_x[instance->bifid].fntype; tree ret_type = TREE_TYPE (instance->fntype); - return altivec_build_new_resolved_builtin (args, n, fntype, - ret_type, - instance->bifid, - fcode); + return altivec_build_resolved_builtin (args, n, fntype, + ret_type, + instance->bifid, + fcode); } else { @@ -1908,7 +1872,7 @@ altivec_resolve_new_overloaded_builtin (location_t loc, tree fndecl, /* Indicate that the instantiation of the overloaded builtin name is not available with the target flags in effect. */ rs6000_gen_builtins fcode = (rs6000_gen_builtins) instance->bifid; - rs6000_invalid_new_builtin (fcode); + rs6000_invalid_builtin (fcode); /* Provide clarity of the relationship between the overload and the instantiation. */ const char *internal_name diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 594d09e..833a290 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -167,9 +167,6 @@ static const struct { "arch_3_1", PPC_FEATURE2_ARCH_3_1, 1 }, { "mma", PPC_FEATURE2_MMA, 1 }, }; - -static rtx rs6000_expand_new_builtin (tree, rtx, rtx, machine_mode, int); -static bool rs6000_gimple_fold_new_builtin (gimple_stmt_iterator *gsi); /* Nonzero if we can use a floating-point register to pass this arg. */ #define USE_FP_FOR_ARG_P(CUM,MODE) \ @@ -3258,7 +3255,7 @@ altivec_expand_vec_ext_builtin (tree exp, rtx target) appropriate target options being set. */ void -rs6000_invalid_new_builtin (enum rs6000_gen_builtins fncode) +rs6000_invalid_builtin (enum rs6000_gen_builtins fncode) { size_t j = (size_t) fncode; const char *name = rs6000_builtin_info_x[j].bifname; @@ -3479,20 +3476,11 @@ fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd) gsi_replace (gsi, g, true); } -/* Fold a machine-dependent built-in in GIMPLE. (For folding into - a constant, use rs6000_fold_builtin.) */ - -bool -rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) -{ - return rs6000_gimple_fold_new_builtin (gsi); -} - /* Helper function to sort out which built-ins may be valid without having a LHS. */ static bool -rs6000_new_builtin_valid_without_lhs (enum rs6000_gen_builtins fn_code, - tree fndecl) +rs6000_builtin_valid_without_lhs (enum rs6000_gen_builtins fn_code, + tree fndecl) { if (TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node) return true; @@ -3520,7 +3508,7 @@ rs6000_new_builtin_valid_without_lhs (enum rs6000_gen_builtins fn_code, /* Check whether a builtin function is supported in this target configuration. */ bool -rs6000_new_builtin_is_supported (enum rs6000_gen_builtins fncode) +rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) { switch (rs6000_builtin_info_x[(size_t) fncode].enable) { @@ -3576,8 +3564,8 @@ rs6000_new_builtin_is_supported (enum rs6000_gen_builtins fncode) __vector_quad arguments into pass-by-value arguments, leading to more efficient code generation. */ static bool -rs6000_gimple_fold_new_mma_builtin (gimple_stmt_iterator *gsi, - rs6000_gen_builtins fn_code) +rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi, + rs6000_gen_builtins fn_code) { gimple *stmt = gsi_stmt (*gsi); size_t fncode = (size_t) fn_code; @@ -3776,8 +3764,8 @@ rs6000_gimple_fold_new_mma_builtin (gimple_stmt_iterator *gsi, /* Fold a machine-dependent built-in in GIMPLE. (For folding into a constant, use rs6000_fold_builtin.) */ -static bool -rs6000_gimple_fold_new_builtin (gimple_stmt_iterator *gsi) +bool +rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) { gimple *stmt = gsi_stmt (*gsi); tree fndecl = gimple_call_fndecl (stmt); @@ -3796,23 +3784,23 @@ rs6000_gimple_fold_new_builtin (gimple_stmt_iterator *gsi) : "nothing"; if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_gimple_fold_new_builtin %d %s %s\n", + fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n", fn_code, fn_name1, fn_name2); if (!rs6000_fold_gimple) return false; /* Prevent gimple folding for code that does not have a LHS, unless it is - allowed per the rs6000_new_builtin_valid_without_lhs helper function. */ + allowed per the rs6000_builtin_valid_without_lhs helper function. */ if (!gimple_call_lhs (stmt) - && !rs6000_new_builtin_valid_without_lhs (fn_code, fndecl)) + && !rs6000_builtin_valid_without_lhs (fn_code, fndecl)) return false; /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */ - if (!rs6000_new_builtin_is_supported (fn_code)) + if (!rs6000_builtin_is_supported (fn_code)) return false; - if (rs6000_gimple_fold_new_mma_builtin (gsi, fn_code)) + if (rs6000_gimple_fold_mma_builtin (gsi, fn_code)) return true; switch (fn_code) @@ -4755,20 +4743,6 @@ rs6000_gimple_fold_new_builtin (gimple_stmt_iterator *gsi) return false; } -/* Expand an expression EXP that calls a built-in function, - with result going to TARGET if that's convenient - (and in mode MODE if that's convenient). - SUBTARGET may be used as the target for computing one of EXP's operands. - IGNORE is nonzero if the value is to be ignored. */ - -rtx -rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, - machine_mode mode ATTRIBUTE_UNUSED, - int ignore ATTRIBUTE_UNUSED) -{ - return rs6000_expand_new_builtin (exp, target, subtarget, mode, ignore); -} - /* Expand ALTIVEC_BUILTIN_MASK_FOR_LOAD. */ rtx rs6000_expand_ldst_mask (rtx target, tree arg0) @@ -4803,8 +4777,8 @@ rs6000_expand_ldst_mask (rtx target, tree arg0) /* Expand the CPU builtin in FCODE and store the result in TARGET. */ static rtx -new_cpu_expand_builtin (enum rs6000_gen_builtins fcode, - tree exp ATTRIBUTE_UNUSED, rtx target) +cpu_expand_builtin (enum rs6000_gen_builtins fcode, + tree exp ATTRIBUTE_UNUSED, rtx target) { /* __builtin_cpu_init () is a nop, so expand to nothing. */ if (fcode == RS6000_BIF_CPU_INIT) @@ -5206,8 +5180,8 @@ stv_expand_builtin (insn_code icode, rtx *op, /* Expand the MMA built-in in EXP, and return it. */ static rtx -new_mma_expand_builtin (tree exp, rtx target, insn_code icode, - rs6000_gen_builtins fcode) +mma_expand_builtin (tree exp, rtx target, insn_code icode, + rs6000_gen_builtins fcode) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); bool void_func = TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node; @@ -5319,7 +5293,7 @@ new_mma_expand_builtin (tree exp, rtx target, insn_code icode, /* Return the appropriate SPR number associated with the given builtin. */ static inline HOST_WIDE_INT -new_htm_spr_num (enum rs6000_gen_builtins code) +htm_spr_num (enum rs6000_gen_builtins code) { if (code == RS6000_BIF_GET_TFHAR || code == RS6000_BIF_SET_TFHAR) @@ -5338,8 +5312,8 @@ new_htm_spr_num (enum rs6000_gen_builtins code) /* Expand the HTM builtin in EXP and store the result in TARGET. Return the expanded rtx. */ static rtx -new_htm_expand_builtin (bifdata *bifaddr, rs6000_gen_builtins fcode, - tree exp, rtx target) +htm_expand_builtin (bifdata *bifaddr, rs6000_gen_builtins fcode, + tree exp, rtx target) { if (!TARGET_POWERPC64 && (fcode == RS6000_BIF_TABORTDC @@ -5425,7 +5399,7 @@ new_htm_expand_builtin (bifdata *bifaddr, rs6000_gen_builtins fcode, if (uses_spr) { machine_mode mode = TARGET_POWERPC64 ? DImode : SImode; - op[nopnds++] = gen_rtx_CONST_INT (mode, new_htm_spr_num (fcode)); + op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode)); } /* If this builtin accesses a CR field, then pass in a scratch CR field as the last operand. */ @@ -5497,11 +5471,9 @@ new_htm_expand_builtin (bifdata *bifaddr, rs6000_gen_builtins fcode, SUBTARGET may be used as the target for computing one of EXP's operands. IGNORE is nonzero if the value is to be ignored. Use the new builtin infrastructure. */ -static rtx -rs6000_expand_new_builtin (tree exp, rtx target, - rtx /* subtarget */, - machine_mode /* mode */, - int ignore) +rtx +rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, + machine_mode /* mode */, int ignore) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); enum rs6000_gen_builtins fcode @@ -5610,7 +5582,7 @@ rs6000_expand_new_builtin (tree exp, rtx target, || (e == ENB_P10_64 && TARGET_POWER10 && TARGET_POWERPC64) || (e == ENB_MMA && TARGET_MMA))) { - rs6000_invalid_new_builtin (fcode); + rs6000_invalid_builtin (fcode); return expand_call (exp, target, ignore); } @@ -5636,7 +5608,7 @@ rs6000_expand_new_builtin (tree exp, rtx target, } if (bif_is_cpu (*bifaddr)) - return new_cpu_expand_builtin (fcode, exp, target); + return cpu_expand_builtin (fcode, exp, target); if (bif_is_init (*bifaddr)) return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target); @@ -5651,7 +5623,7 @@ rs6000_expand_new_builtin (tree exp, rtx target, return altivec_expand_predicate_builtin (icode, exp, target); if (bif_is_htm (*bifaddr)) - return new_htm_expand_builtin (bifaddr, fcode, exp, target); + return htm_expand_builtin (bifaddr, fcode, exp, target); if (bif_is_32bit (*bifaddr) && TARGET_32BIT) { @@ -5837,7 +5809,7 @@ rs6000_expand_new_builtin (tree exp, rtx target, return lxvrze_expand_builtin (target, icode, op, mode[0], mode[1]); if (bif_is_mma (*bifaddr)) - return new_mma_expand_builtin (exp, target, icode, fcode); + return mma_expand_builtin (exp, target, icode, fcode); if (fcode == RS6000_BIF_PACK_IF && TARGET_LONG_DOUBLE_128 @@ -6386,8 +6358,8 @@ rs6000_init_builtins (void) return; } -static tree -rs6000_new_builtin_decl (unsigned code, bool /* initialize_p */) +tree +rs6000_builtin_decl (unsigned code, bool /* initialize_p */) { rs6000_gen_builtins fcode = (rs6000_gen_builtins) code; @@ -6397,17 +6369,6 @@ rs6000_new_builtin_decl (unsigned code, bool /* initialize_p */) return rs6000_builtin_decls_x[code]; } -/* Returns the rs6000 builtin decl for CODE. Note that we don't check - the builtin mask here since there could be some #pragma/attribute - target functions and the rs6000_builtin_mask could be wrong when - this checking happens, though it will be updated properly later. */ - -tree -rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) -{ - return rs6000_new_builtin_decl (code, initialize_p); -} - /* Return the internal arg pointer used for function incoming arguments. When -fsplit-stack, the arg pointer is r12 so we need to copy it to a pseudo in order for it to be preserved over calls diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c index bc59eb4..5c621c5 100644 --- a/gcc/config/rs6000/rs6000-gen-builtins.c +++ b/gcc/config/rs6000/rs6000-gen-builtins.c @@ -2382,8 +2382,7 @@ write_decls (void) fprintf (header_file, "extern void rs6000_init_generated_builtins ();\n\n"); fprintf (header_file, - "extern bool rs6000_new_builtin_is_supported " - "(rs6000_gen_builtins);\n"); + "extern bool rs6000_builtin_is_supported (rs6000_gen_builtins);\n"); fprintf (header_file, "extern tree rs6000_builtin_decl (unsigned, " "bool ATTRIBUTE_UNUSED);\n\n"); diff --git a/gcc/config/rs6000/rs6000-internal.h b/gcc/config/rs6000/rs6000-internal.h index a880fd3..49904b3 100644 --- a/gcc/config/rs6000/rs6000-internal.h +++ b/gcc/config/rs6000/rs6000-internal.h @@ -142,7 +142,7 @@ extern void rs6000_output_mi_thunk (FILE *file, extern bool rs6000_output_addr_const_extra (FILE *file, rtx x); extern bool rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi); extern tree rs6000_build_builtin_va_list (void); -extern void rs6000_invalid_new_builtin (rs6000_gen_builtins fncode); +extern void rs6000_invalid_builtin (rs6000_gen_builtins fncode); extern void rs6000_va_start (tree valist, rtx nextarg); extern tree rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, gimple_seq *post_p); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 5c077cd..9303e4e 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -5568,14 +5568,14 @@ rs6000_loop_unroll_adjust (unsigned nunroll, struct loop *loop) Implement targetm.vectorize.builtin_vectorized_function. */ static tree -rs6000_new_builtin_vectorized_function (unsigned int fn, tree type_out, - tree type_in) +rs6000_builtin_vectorized_function (unsigned int fn, tree type_out, + tree type_in) { machine_mode in_mode, out_mode; int in_n, out_n; if (TARGET_DEBUG_BUILTIN) - fprintf (stderr, "rs6000_new_builtin_vectorized_function (%s, %s, %s)\n", + fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n", combined_fn_name (combined_fn (fn)), GET_MODE_NAME (TYPE_MODE (type_out)), GET_MODE_NAME (TYPE_MODE (type_in))); @@ -5700,15 +5700,15 @@ rs6000_new_builtin_vectorized_function (unsigned int fn, tree type_out, /* Implement targetm.vectorize.builtin_md_vectorized_function. */ static tree -rs6000_new_builtin_md_vectorized_function (tree fndecl, tree type_out, - tree type_in) +rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out, + tree type_in) { machine_mode in_mode, out_mode; int in_n, out_n; if (TARGET_DEBUG_BUILTIN) fprintf (stderr, - "rs6000_new_builtin_md_vectorized_function (%s, %s, %s)\n", + "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n", IDENTIFIER_POINTER (DECL_NAME (fndecl)), GET_MODE_NAME (TYPE_MODE (type_out)), GET_MODE_NAME (TYPE_MODE (type_in))); @@ -5918,25 +5918,6 @@ rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out, return new_fndecl; } -/* Returns a function decl for a vectorized version of the builtin function - with builtin function code FN and the result vector type TYPE, or NULL_TREE - if it is not available. */ - -static tree -rs6000_builtin_vectorized_function (unsigned int fn, tree type_out, - tree type_in) -{ - return rs6000_new_builtin_vectorized_function (fn, type_out, type_in); -} - -/* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */ - -static tree -rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out, - tree type_in) -{ - return rs6000_new_builtin_md_vectorized_function (fndecl, type_out, type_in); -} /* Default CPU string for rs6000*_file_start functions. */ static const char *rs6000_default_cpu; -- cgit v1.1 From 926d64906af2efc8714d37e6db2171784cfa60cd Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Tue, 14 Dec 2021 13:34:11 -0600 Subject: rs6000: Rename arrays to remove temporary _x suffix While we had two sets of built-in infrastructure at once, I added _x as a suffix to two arrays to disambiguate the old and new versions. Time to fix that also. 2021-12-06 Bill Schmidt gcc/ * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Rename rs6000_builtin_decls_x to rs6000_builtin_decls. (altivec_resolve_overloaded_builtin): Likewise. Also rename rs6000_builtin_info_x to rs6000_builtin_info. * config/rs6000/rs6000-call.c (rs6000_invalid_builtin): Rename rs6000_builtin_info_x to rs6000_builtin_info. (rs6000_builtin_is_supported): Likewise. (rs6000_gimple_fold_mma_builtin): Likewise. Also rename rs6000_builtin_decls_x to rs6000_builtin_decls. (rs6000_gimple_fold_builtin): Rename rs6000_builtin_info_x to rs6000_builtin_info. (cpu_expand_builtin): Likewise. (rs6000_expand_builtin): Likewise. (rs6000_init_builtins): Likewise. Also rename rs6000_builtin_decls_x to rs6000_builtin_decls. (rs6000_builtin_decl): Rename rs6000_builtin_decls_x to rs6000_builtin_decls. * config/rs6000/rs6000-gen-builtins.c (write_decls): In generated code, rename rs6000_builtin_decls_x to rs6000_builtin_decls, and rename rs6000_builtin_info_x to rs6000_builtin_info. (write_bif_static_init): In generated code, rename rs6000_builtin_info_x to rs6000_builtin_info. (write_init_bif_table): In generated code, rename rs6000_builtin_decls_x to rs6000_builtin_decls, and rename rs6000_builtin_info_x to rs6000_builtin_info. (write_init_ovld_table): In generated code, rename rs6000_builtin_decls_x to rs6000_builtin_decls. (write_init_file): Likewise. * config/rs6000/rs6000.c (rs6000_builtin_vectorized_function): Likewise. (rs6000_builtin_md_vectorized_function): Likewise. (rs6000_builtin_reciprocal): Likewise. (add_condition_to_bb): Likewise. (rs6000_atomic_assign_expand_fenv): Likewise. --- gcc/config/rs6000/rs6000-c.c | 64 ++++++++++++++++----------------- gcc/config/rs6000/rs6000-call.c | 46 ++++++++++++------------ gcc/config/rs6000/rs6000-gen-builtins.c | 27 +++++++------- gcc/config/rs6000/rs6000.c | 58 +++++++++++++++--------------- 4 files changed, 96 insertions(+), 99 deletions(-) (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index f790c72..e0ebdee 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -867,7 +867,7 @@ altivec_build_resolved_builtin (tree *args, int n, tree fntype, tree ret_type, { tree argtypes = TYPE_ARG_TYPES (fntype); tree arg_type[MAX_OVLD_ARGS]; - tree fndecl = rs6000_builtin_decls_x[bif_id]; + tree fndecl = rs6000_builtin_decls[bif_id]; for (int i = 0; i < n; i++) { @@ -1001,13 +1001,13 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, case E_SFmode: { /* For floats use the xvmulsp instruction directly. */ - tree call = rs6000_builtin_decls_x[RS6000_BIF_XVMULSP]; + tree call = rs6000_builtin_decls[RS6000_BIF_XVMULSP]; return build_call_expr (call, 2, arg0, arg1); } case E_DFmode: { /* For doubles use the xvmuldp instruction directly. */ - tree call = rs6000_builtin_decls_x[RS6000_BIF_XVMULDP]; + tree call = rs6000_builtin_decls[RS6000_BIF_XVMULDP]; return build_call_expr (call, 2, arg0, arg1); } /* Other types are errors. */ @@ -1066,7 +1066,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, vec_safe_push (params, arg0); vec_safe_push (params, arg1); tree call = altivec_resolve_overloaded_builtin - (loc, rs6000_builtin_decls_x[RS6000_OVLD_VEC_CMPEQ], + (loc, rs6000_builtin_decls[RS6000_OVLD_VEC_CMPEQ], params); /* Use save_expr to ensure that operands used more than once that may have side effects (like calls) are only evaluated @@ -1076,7 +1076,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, vec_safe_push (params, call); vec_safe_push (params, call); return altivec_resolve_overloaded_builtin - (loc, rs6000_builtin_decls_x[RS6000_OVLD_VEC_NOR], params); + (loc, rs6000_builtin_decls[RS6000_OVLD_VEC_NOR], params); } /* Other types are errors. */ default: @@ -1129,9 +1129,9 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, vec_safe_push (params, arg1); if (fcode == RS6000_OVLD_VEC_ADDE) - add_sub_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_ADD]; + add_sub_builtin = rs6000_builtin_decls[RS6000_OVLD_VEC_ADD]; else - add_sub_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_SUB]; + add_sub_builtin = rs6000_builtin_decls[RS6000_OVLD_VEC_SUB]; tree call = altivec_resolve_overloaded_builtin (loc, add_sub_builtin, @@ -1207,9 +1207,9 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, vec_safe_push (params, arg1); if (fcode == RS6000_OVLD_VEC_ADDEC) - as_c_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_ADDC]; + as_c_builtin = rs6000_builtin_decls[RS6000_OVLD_VEC_ADDC]; else - as_c_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_SUBC]; + as_c_builtin = rs6000_builtin_decls[RS6000_OVLD_VEC_SUBC]; tree call1 = altivec_resolve_overloaded_builtin (loc, as_c_builtin, params); @@ -1218,9 +1218,9 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, vec_safe_push (params, arg1); if (fcode == RS6000_OVLD_VEC_ADDEC) - as_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_ADD]; + as_builtin = rs6000_builtin_decls[RS6000_OVLD_VEC_ADD]; else - as_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_SUB]; + as_builtin = rs6000_builtin_decls[RS6000_OVLD_VEC_SUB]; tree call2 = altivec_resolve_overloaded_builtin (loc, as_builtin, params); @@ -1236,7 +1236,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, params = make_tree_vector (); vec_safe_push (params, call1); vec_safe_push (params, call2); - tree or_builtin = rs6000_builtin_decls_x[RS6000_OVLD_VEC_OR]; + tree or_builtin = rs6000_builtin_decls[RS6000_OVLD_VEC_OR]; return altivec_resolve_overloaded_builtin (loc, or_builtin, params); } @@ -1380,34 +1380,34 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, break; case E_V1TImode: - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V1TI]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V1TI]; break; case E_V2DFmode: - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V2DF]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V2DF]; break; case E_V2DImode: - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V2DI]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V2DI]; break; case E_V4SFmode: - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V4SF]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V4SF]; break; case E_V4SImode: if (TARGET_DIRECT_MOVE_64BIT) - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V4SI]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V4SI]; break; case E_V8HImode: if (TARGET_DIRECT_MOVE_64BIT) - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V8HI]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V8HI]; break; case E_V16QImode: if (TARGET_DIRECT_MOVE_64BIT) - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V16QI]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V16QI]; break; } } @@ -1422,27 +1422,27 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, break; case E_V2DFmode: - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V2DF]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V2DF]; break; case E_V2DImode: - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V2DI]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V2DI]; break; case E_V4SFmode: - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V4SF]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V4SF]; break; case E_V4SImode: - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V4SI]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V4SI]; break; case E_V8HImode: - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V8HI]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V8HI]; break; case E_V16QImode: - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_EXT_V16QI]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_EXT_V16QI]; break; } } @@ -1542,9 +1542,9 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, arg2 = wide_int_to_tree (TREE_TYPE (arg2), selector); if (mode == V2DFmode) - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_SET_V2DF]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_SET_V2DF]; else if (mode == V2DImode) - call = rs6000_builtin_decls_x[RS6000_BIF_VEC_SET_V2DI]; + call = rs6000_builtin_decls[RS6000_BIF_VEC_SET_V2DI]; /* Note, __builtin_vec_insert_ has vector and scalar types reversed. */ @@ -1554,7 +1554,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode) && TREE_CODE (arg2) == INTEGER_CST) { - tree call = rs6000_builtin_decls_x[RS6000_BIF_VEC_SET_V1TI]; + tree call = rs6000_builtin_decls[RS6000_BIF_VEC_SET_V1TI]; wide_int selector = wi::zero(32); arg2 = wide_int_to_tree (TREE_TYPE (arg2), selector); @@ -1740,7 +1740,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, instance = instance->next; gcc_assert (instance != NULL); - tree fntype = rs6000_builtin_info_x[instance->bifid].fntype; + tree fntype = rs6000_builtin_info[instance->bifid].fntype; tree parmtype0 = TREE_VALUE (TYPE_ARG_TYPES (fntype)); tree parmtype1 = TREE_VALUE (TREE_CHAIN (TYPE_ARG_TYPES (fntype))); @@ -1798,7 +1798,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, instance = instance->next; gcc_assert (instance != NULL); - tree fntype = rs6000_builtin_info_x[instance->bifid].fntype; + tree fntype = rs6000_builtin_info[instance->bifid].fntype; tree parmtype0 = TREE_VALUE (TYPE_ARG_TYPES (fntype)); tree parmtype1 = TREE_VALUE (TREE_CHAIN (TYPE_ARG_TYPES (fntype))); @@ -1849,7 +1849,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, if (rs6000_builtin_decl (instance->bifid, false) != error_mark_node && supported) { - tree fntype = rs6000_builtin_info_x[instance->bifid].fntype; + tree fntype = rs6000_builtin_info[instance->bifid].fntype; tree ret_type = TREE_TYPE (instance->fntype); return altivec_build_resolved_builtin (args, n, fntype, ret_type, @@ -1876,7 +1876,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, /* Provide clarity of the relationship between the overload and the instantiation. */ const char *internal_name - = rs6000_builtin_info_x[instance->bifid].bifname; + = rs6000_builtin_info[instance->bifid].bifname; rich_location richloc (line_table, input_location); inform (&richloc, "overloaded builtin %qs is implemented by builtin %qs", diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 833a290..b98f4a4 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -3258,9 +3258,9 @@ void rs6000_invalid_builtin (enum rs6000_gen_builtins fncode) { size_t j = (size_t) fncode; - const char *name = rs6000_builtin_info_x[j].bifname; + const char *name = rs6000_builtin_info[j].bifname; - switch (rs6000_builtin_info_x[j].enable) + switch (rs6000_builtin_info[j].enable) { case ENB_P5: error ("%qs requires the %qs option", name, "-mcpu=power5"); @@ -3510,7 +3510,7 @@ rs6000_builtin_valid_without_lhs (enum rs6000_gen_builtins fn_code, bool rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) { - switch (rs6000_builtin_info_x[(size_t) fncode].enable) + switch (rs6000_builtin_info[(size_t) fncode].enable) { case ENB_ALWAYS: return true; @@ -3570,18 +3570,18 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi, gimple *stmt = gsi_stmt (*gsi); size_t fncode = (size_t) fn_code; - if (!bif_is_mma (rs6000_builtin_info_x[fncode])) + if (!bif_is_mma (rs6000_builtin_info[fncode])) return false; /* Each call that can be gimple-expanded has an associated built-in function that it will expand into. If this one doesn't, we have already expanded it! Exceptions: lxvp and stxvp. */ - if (rs6000_builtin_info_x[fncode].assoc_bif == RS6000_BIF_NONE + if (rs6000_builtin_info[fncode].assoc_bif == RS6000_BIF_NONE && fncode != RS6000_BIF_LXVP && fncode != RS6000_BIF_STXVP) return false; - bifdata *bd = &rs6000_builtin_info_x[fncode]; + bifdata *bd = &rs6000_builtin_info[fncode]; unsigned nopnds = bd->nargs; gimple_seq new_seq = NULL; gimple *new_call; @@ -3626,7 +3626,7 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi, to emit a xxmfacc instruction now, since we cannot do it later. */ if (fncode == RS6000_BIF_DISASSEMBLE_ACC) { - new_decl = rs6000_builtin_decls_x[RS6000_BIF_XXMFACC_INTERNAL]; + new_decl = rs6000_builtin_decls[RS6000_BIF_XXMFACC_INTERNAL]; new_call = gimple_build_call (new_decl, 1, src); src = create_tmp_reg_or_ssa_name (vector_quad_type_node); gimple_call_set_lhs (new_call, src); @@ -3635,7 +3635,7 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi, /* Copy the accumulator/pair vector by vector. */ new_decl - = rs6000_builtin_decls_x[rs6000_builtin_info_x[fncode].assoc_bif]; + = rs6000_builtin_decls[rs6000_builtin_info[fncode].assoc_bif]; tree dst_type = build_pointer_type_for_mode (unsigned_V16QI_type_node, ptr_mode, true); tree dst_base = build1 (VIEW_CONVERT_EXPR, dst_type, dst_ptr); @@ -3693,7 +3693,7 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi, /* Convert this built-in into an internal version that uses pass-by-value arguments. The internal built-in is found in the assoc_bif field. */ - new_decl = rs6000_builtin_decls_x[rs6000_builtin_info_x[fncode].assoc_bif]; + new_decl = rs6000_builtin_decls[rs6000_builtin_info[fncode].assoc_bif]; tree lhs, op[MAX_MMA_OPERANDS]; tree acc = gimple_call_arg (stmt, 0); push_gimplify_context (true); @@ -3777,8 +3777,8 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) gimple *g; size_t uns_fncode = (size_t) fn_code; - enum insn_code icode = rs6000_builtin_info_x[uns_fncode].icode; - const char *fn_name1 = rs6000_builtin_info_x[uns_fncode].bifname; + enum insn_code icode = rs6000_builtin_info[uns_fncode].icode; + const char *fn_name1 = rs6000_builtin_info[uns_fncode].bifname; const char *fn_name2 = (icode != CODE_FOR_nothing) ? get_insn_name ((int) icode) : "nothing"; @@ -4801,7 +4801,7 @@ cpu_expand_builtin (enum rs6000_gen_builtins fcode, if (TREE_CODE (arg) != STRING_CST) { error ("builtin %qs only accepts a string argument", - rs6000_builtin_info_x[(size_t) fcode].bifname); + rs6000_builtin_info[(size_t) fcode].bifname); return const0_rtx; } @@ -4820,7 +4820,7 @@ cpu_expand_builtin (enum rs6000_gen_builtins fcode, { /* Invalid CPU argument. */ error ("cpu %qs is an invalid argument to builtin %qs", - cpu, rs6000_builtin_info_x[(size_t) fcode].bifname); + cpu, rs6000_builtin_info[(size_t) fcode].bifname); return const0_rtx; } @@ -4849,7 +4849,7 @@ cpu_expand_builtin (enum rs6000_gen_builtins fcode, /* Invalid HWCAP argument. */ error ("%s %qs is an invalid argument to builtin %qs", "hwcap", hwcap, - rs6000_builtin_info_x[(size_t) fcode].bifname); + rs6000_builtin_info[(size_t) fcode].bifname); return const0_rtx; } @@ -4877,7 +4877,7 @@ cpu_expand_builtin (enum rs6000_gen_builtins fcode, #else warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware " - "capability bits", rs6000_builtin_info_x[(size_t) fcode].bifname); + "capability bits", rs6000_builtin_info[(size_t) fcode].bifname); /* For old LIBCs, always return FALSE. */ emit_move_insn (target, GEN_INT (0)); @@ -5479,7 +5479,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, enum rs6000_gen_builtins fcode = (enum rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl); size_t uns_fcode = (size_t)fcode; - enum insn_code icode = rs6000_builtin_info_x[uns_fcode].icode; + enum insn_code icode = rs6000_builtin_info[uns_fcode].icode; /* TODO: The following commentary and code is inherited from the original builtin processing code. The commentary is a bit confusing, with the @@ -5557,7 +5557,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, /* In case of "#pragma target" changes, we initialize all builtins but check for actual availability now, during expand time. For invalid builtins, generate a normal call. */ - bifdata *bifaddr = &rs6000_builtin_info_x[uns_fcode]; + bifdata *bifaddr = &rs6000_builtin_info[uns_fcode]; bif_enable e = bifaddr->enable; if (!(e == ENB_ALWAYS @@ -6267,7 +6267,7 @@ rs6000_init_builtins (void) fprintf (stderr, "\nAutogenerated built-in functions:\n\n"); for (int i = 1; i < (int) RS6000_BIF_MAX; i++) { - bif_enable e = rs6000_builtin_info_x[i].enable; + bif_enable e = rs6000_builtin_info[i].enable; if (e == ENB_P5 && !TARGET_POPCNTB) continue; if (e == ENB_P6 && !TARGET_CMPB) @@ -6306,10 +6306,10 @@ rs6000_init_builtins (void) continue; if (e == ENB_MMA && !TARGET_MMA) continue; - tree fntype = rs6000_builtin_info_x[i].fntype; + tree fntype = rs6000_builtin_info[i].fntype; tree t = TREE_TYPE (fntype); fprintf (stderr, "%s %s (", rs6000_type_string (t), - rs6000_builtin_info_x[i].bifname); + rs6000_builtin_info[i].bifname); t = TYPE_ARG_TYPES (fntype); while (t && TREE_VALUE (t) != void_type_node) { @@ -6320,7 +6320,7 @@ rs6000_init_builtins (void) fprintf (stderr, ", "); } fprintf (stderr, "); %s [%4d]\n", - rs6000_builtin_info_x[i].attr_string, (int) i); + rs6000_builtin_info[i].attr_string, (int) i); } fprintf (stderr, "\nEnd autogenerated built-in functions.\n\n\n"); } @@ -6349,7 +6349,7 @@ rs6000_init_builtins (void) } altivec_builtin_mask_for_load - = rs6000_builtin_decls_x[RS6000_BIF_MASK_FOR_LOAD]; + = rs6000_builtin_decls[RS6000_BIF_MASK_FOR_LOAD]; #ifdef SUBTARGET_INIT_BUILTINS SUBTARGET_INIT_BUILTINS; @@ -6366,7 +6366,7 @@ rs6000_builtin_decl (unsigned code, bool /* initialize_p */) if (fcode >= RS6000_OVLD_MAX) return error_mark_node; - return rs6000_builtin_decls_x[code]; + return rs6000_builtin_decls[code]; } /* Return the internal arg pointer used for function incoming diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c index 5c621c5..c6ddbc6 100644 --- a/gcc/config/rs6000/rs6000-gen-builtins.c +++ b/gcc/config/rs6000/rs6000-gen-builtins.c @@ -2212,7 +2212,7 @@ write_decls (void) fprintf (header_file, " RS6000_OVLD_MAX\n};\n\n"); fprintf (header_file, - "extern GTY(()) tree rs6000_builtin_decls_x[RS6000_OVLD_MAX];\n\n"); + "extern GTY(()) tree rs6000_builtin_decls[RS6000_OVLD_MAX];\n\n"); fprintf (header_file, "enum rs6000_ovld_instances\n{\n RS6000_INST_NONE,\n"); @@ -2343,9 +2343,6 @@ write_decls (void) "#define bif_is_ibmld(x)\t((x).bifattrs & bif_ibmld_bit)\n"); fprintf (header_file, "\n"); - /* #### Note that the _x is added for now to avoid conflict with - the existing rs6000_builtin_info[] file while testing. It will - be removed as we progress. */ /* #### Cannot mark this as a GC root because only pointer types can be marked as GTY((user)) and be GC roots. All trees in here are kept alive by other globals, so not a big deal. Alternatively, @@ -2353,7 +2350,7 @@ write_decls (void) to avoid requiring a GTY((user)) designation, but that seems unnecessarily gross. */ fprintf (header_file, - "extern bifdata rs6000_builtin_info_x[RS6000_BIF_MAX];\n\n"); + "extern bifdata rs6000_builtin_info[RS6000_BIF_MAX];\n\n"); fprintf (header_file, "struct GTY((user)) ovlddata\n"); fprintf (header_file, "{\n"); @@ -2502,12 +2499,12 @@ write_header_file (void) return 1; } -/* Write the decl and initializer for rs6000_builtin_info_x[]. */ +/* Write the decl and initializer for rs6000_builtin_info[]. */ static void write_bif_static_init (void) { const char *res[3]; - fprintf (init_file, "bifdata rs6000_builtin_info_x[RS6000_BIF_MAX] =\n"); + fprintf (init_file, "bifdata rs6000_builtin_info[RS6000_BIF_MAX] =\n"); fprintf (init_file, " {\n"); fprintf (init_file, " { /* RS6000_BIF_NONE: */\n"); fprintf (init_file, " \"\", ENB_ALWAYS, 0, CODE_FOR_nothing, 0,\n"); @@ -2674,7 +2671,7 @@ write_init_bif_table (void) for (int i = 0; i <= curr_bif; i++) { fprintf (init_file, - " rs6000_builtin_info_x[RS6000_BIF_%s].fntype" + " rs6000_builtin_info[RS6000_BIF_%s].fntype" "\n = %s;\n", bifs[i].idname, bifs[i].fndecl); @@ -2701,7 +2698,7 @@ write_init_bif_table (void) } fprintf (init_file, - " rs6000_builtin_decls_x[(int)RS6000_BIF_%s] = t\n", + " rs6000_builtin_decls[(int)RS6000_BIF_%s] = t\n", bifs[i].idname); fprintf (init_file, " = add_builtin_function (\"%s\",\n", @@ -2742,7 +2739,7 @@ write_init_bif_table (void) fprintf (init_file, " }\n"); fprintf (init_file, " else\n"); fprintf (init_file, " {\n"); - fprintf (init_file, " rs6000_builtin_decls_x" + fprintf (init_file, " rs6000_builtin_decls" "[(int)RS6000_BIF_%s] = NULL_TREE;\n", bifs[i].idname); fprintf (init_file, " }\n"); } @@ -2795,7 +2792,7 @@ write_init_ovld_table (void) } fprintf (init_file, - " rs6000_builtin_decls_x[(int)RS6000_OVLD_%s] = t\n", + " rs6000_builtin_decls[(int)RS6000_OVLD_%s] = t\n", stanza->stanza_id); fprintf (init_file, " = add_builtin_function (\"%s\",\n", @@ -2844,7 +2841,7 @@ write_init_file (void) fprintf (init_file, "#include \"rs6000-builtins.h\"\n"); fprintf (init_file, "\n"); - fprintf (init_file, "tree rs6000_builtin_decls_x[RS6000_OVLD_MAX];\n\n"); + fprintf (init_file, "tree rs6000_builtin_decls[RS6000_OVLD_MAX];\n\n"); write_bif_static_init (); write_ovld_static_init (); @@ -2860,11 +2857,11 @@ write_init_file (void) fprintf (init_file, "\n"); fprintf (init_file, - " rs6000_builtin_decls_x[RS6000_BIF_NONE] = NULL_TREE;\n"); + " rs6000_builtin_decls[RS6000_BIF_NONE] = NULL_TREE;\n"); fprintf (init_file, - " rs6000_builtin_decls_x[RS6000_BIF_MAX] = NULL_TREE;\n"); + " rs6000_builtin_decls[RS6000_BIF_MAX] = NULL_TREE;\n"); fprintf (init_file, - " rs6000_builtin_decls_x[RS6000_OVLD_NONE] = NULL_TREE;\n\n"); + " rs6000_builtin_decls[RS6000_OVLD_NONE] = NULL_TREE;\n\n"); write_init_bif_table (); write_init_ovld_table (); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 9303e4e..4481ba5 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -5596,95 +5596,95 @@ rs6000_builtin_vectorized_function (unsigned int fn, tree type_out, if (VECTOR_UNIT_VSX_P (V2DFmode) && out_mode == DFmode && out_n == 2 && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls_x[RS6000_BIF_CPSGNDP]; + return rs6000_builtin_decls[RS6000_BIF_CPSGNDP]; if (VECTOR_UNIT_VSX_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_CPSGNSP]; + return rs6000_builtin_decls[RS6000_BIF_CPSGNSP]; if (VECTOR_UNIT_ALTIVEC_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_COPYSIGN_V4SF]; + return rs6000_builtin_decls[RS6000_BIF_COPYSIGN_V4SF]; break; CASE_CFN_CEIL: if (VECTOR_UNIT_VSX_P (V2DFmode) && out_mode == DFmode && out_n == 2 && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls_x[RS6000_BIF_XVRDPIP]; + return rs6000_builtin_decls[RS6000_BIF_XVRDPIP]; if (VECTOR_UNIT_VSX_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_XVRSPIP]; + return rs6000_builtin_decls[RS6000_BIF_XVRSPIP]; if (VECTOR_UNIT_ALTIVEC_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_VRFIP]; + return rs6000_builtin_decls[RS6000_BIF_VRFIP]; break; CASE_CFN_FLOOR: if (VECTOR_UNIT_VSX_P (V2DFmode) && out_mode == DFmode && out_n == 2 && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls_x[RS6000_BIF_XVRDPIM]; + return rs6000_builtin_decls[RS6000_BIF_XVRDPIM]; if (VECTOR_UNIT_VSX_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_XVRSPIM]; + return rs6000_builtin_decls[RS6000_BIF_XVRSPIM]; if (VECTOR_UNIT_ALTIVEC_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_VRFIM]; + return rs6000_builtin_decls[RS6000_BIF_VRFIM]; break; CASE_CFN_FMA: if (VECTOR_UNIT_VSX_P (V2DFmode) && out_mode == DFmode && out_n == 2 && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls_x[RS6000_BIF_XVMADDDP]; + return rs6000_builtin_decls[RS6000_BIF_XVMADDDP]; if (VECTOR_UNIT_VSX_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_XVMADDSP]; + return rs6000_builtin_decls[RS6000_BIF_XVMADDSP]; if (VECTOR_UNIT_ALTIVEC_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_VMADDFP]; + return rs6000_builtin_decls[RS6000_BIF_VMADDFP]; break; CASE_CFN_TRUNC: if (VECTOR_UNIT_VSX_P (V2DFmode) && out_mode == DFmode && out_n == 2 && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls_x[RS6000_BIF_XVRDPIZ]; + return rs6000_builtin_decls[RS6000_BIF_XVRDPIZ]; if (VECTOR_UNIT_VSX_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_XVRSPIZ]; + return rs6000_builtin_decls[RS6000_BIF_XVRSPIZ]; if (VECTOR_UNIT_ALTIVEC_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_VRFIZ]; + return rs6000_builtin_decls[RS6000_BIF_VRFIZ]; break; CASE_CFN_NEARBYINT: if (VECTOR_UNIT_VSX_P (V2DFmode) && flag_unsafe_math_optimizations && out_mode == DFmode && out_n == 2 && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls_x[RS6000_BIF_XVRDPI]; + return rs6000_builtin_decls[RS6000_BIF_XVRDPI]; if (VECTOR_UNIT_VSX_P (V4SFmode) && flag_unsafe_math_optimizations && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_XVRSPI]; + return rs6000_builtin_decls[RS6000_BIF_XVRSPI]; break; CASE_CFN_RINT: if (VECTOR_UNIT_VSX_P (V2DFmode) && !flag_trapping_math && out_mode == DFmode && out_n == 2 && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls_x[RS6000_BIF_XVRDPIC]; + return rs6000_builtin_decls[RS6000_BIF_XVRDPIC]; if (VECTOR_UNIT_VSX_P (V4SFmode) && !flag_trapping_math && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_XVRSPIC]; + return rs6000_builtin_decls[RS6000_BIF_XVRSPIC]; break; default: break; @@ -5731,25 +5731,25 @@ rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out, if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_VRSQRTFP]; + return rs6000_builtin_decls[RS6000_BIF_VRSQRTFP]; break; case RS6000_BIF_RSQRT: if (VECTOR_UNIT_VSX_P (V2DFmode) && out_mode == DFmode && out_n == 2 && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls_x[RS6000_BIF_RSQRT_2DF]; + return rs6000_builtin_decls[RS6000_BIF_RSQRT_2DF]; break; case RS6000_BIF_RECIPF: if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode) && out_mode == SFmode && out_n == 4 && in_mode == SFmode && in_n == 4) - return rs6000_builtin_decls_x[RS6000_BIF_VRECIPFP]; + return rs6000_builtin_decls[RS6000_BIF_VRECIPFP]; break; case RS6000_BIF_RECIP: if (VECTOR_UNIT_VSX_P (V2DFmode) && out_mode == DFmode && out_n == 2 && in_mode == DFmode && in_n == 2) - return rs6000_builtin_decls_x[RS6000_BIF_RECIP_V2DF]; + return rs6000_builtin_decls[RS6000_BIF_RECIP_V2DF]; break; default: break; @@ -5804,7 +5804,7 @@ rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out, } if (in_mode == exp_mode && in_vmode == exp_vmode) - return rs6000_builtin_decls_x[bif]; + return rs6000_builtin_decls[bif]; } return NULL_TREE; @@ -22496,13 +22496,13 @@ rs6000_builtin_reciprocal (tree fndecl) if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode)) return NULL_TREE; - return rs6000_builtin_decls_x[RS6000_BIF_RSQRT_2DF]; + return rs6000_builtin_decls[RS6000_BIF_RSQRT_2DF]; case RS6000_BIF_XVSQRTSP: if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode)) return NULL_TREE; - return rs6000_builtin_decls_x[RS6000_BIF_RSQRT_4SF]; + return rs6000_builtin_decls[RS6000_BIF_RSQRT_4SF]; default: return NULL_TREE; @@ -25124,7 +25124,7 @@ add_condition_to_bb (tree function_decl, tree version_decl, tree bool_zero = build_int_cst (bool_int_type_node, 0); tree cond_var = create_tmp_var (bool_int_type_node); - tree predicate_decl = rs6000_builtin_decls_x[(int) RS6000_BIF_CPU_SUPPORTS]; + tree predicate_decl = rs6000_builtin_decls[(int) RS6000_BIF_CPU_SUPPORTS]; const char *arg_str = rs6000_clone_map[clone_isa].name; tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str); gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg); @@ -27766,8 +27766,8 @@ rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) return; } - tree mffs = rs6000_builtin_decls_x[RS6000_BIF_MFFS]; - tree mtfsf = rs6000_builtin_decls_x[RS6000_BIF_MTFSF]; + tree mffs = rs6000_builtin_decls[RS6000_BIF_MFFS]; + tree mtfsf = rs6000_builtin_decls[RS6000_BIF_MTFSF]; tree call_mffs = build_call_expr (mffs, 0); /* Generates the equivalent of feholdexcept (&fenv_var) -- cgit v1.1 From a888259a71fbbb7f14923751251e056829d76342 Mon Sep 17 00:00:00 2001 From: JoJo R Date: Tue, 14 Dec 2021 16:55:57 -0500 Subject: regrename: Skip renaming if instruction is noop move. gcc/ * regrename.c (find_rename_reg): Return satisfied regno if instruction is noop move. --- gcc/regrename.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'gcc') diff --git a/gcc/regrename.c b/gcc/regrename.c index b8a9ca3..fe72fcc 100644 --- a/gcc/regrename.c +++ b/gcc/regrename.c @@ -394,6 +394,11 @@ find_rename_reg (du_head_p this_head, enum reg_class super_class, this_head, *unavailable)) return this_head->tied_chain->regno; + /* If this insn is a noop move, then do not rename in this chain as doing so + would inhibit removal of the noop move. */ + if (noop_move_p (this_head->first->insn)) + return best_new_reg; + /* If PREFERRED_CLASS is not NO_REGS, we iterate in the first pass over registers that belong to PREFERRED_CLASS and try to find the best register within the class. If that failed, we iterate in -- cgit v1.1 From 85a438fc78dd12249ca854a3e5c577fefeb1a5cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=B6ren=20Tempel?= Date: Tue, 14 Dec 2021 18:07:47 -0500 Subject: [PATCH] stddef.h: add support for musl typedef macro guards The stddef.h header checks/sets various hardcoded toolchain/os specific macro guards to prevent redefining types such as ptrdiff_t, wchar_t, or size_t. However, without this patch, the file does not check/set the typedef macro guards for musl libc. This causes types such as size_t to be defined twice for files which include both musl's stdlib.h as well as GCC's ginclude/stddef.h. This is, for example, the case for libgo/sysinfo.c. If libgo/sysinfo.c has multiple typedefs for size_t this confuses -fdump-go-spec and causes size_t not to be included in the generated type definitions thereby causing a gcc-go compilation failure on Alpine Linux Edge (which uses musl libc) with the following error: sysinfo.go:7765:13: error: use of undefined type '_size_t' 7765 | type Size_t _size_t | ^ libcall_posix.go:49:35: error: non-integer len argument in make 49 | b := make([]byte, len) | This commit fixes this issue by ensuring that ptrdiff_t, wchar_t, and size_t are only defined once in the pre-processed libgo/sysinfo.c file by enhancing gcc/ginclude/stddef.h with musl-specific typedef macro guards. gcc/ChangeLog: * ginclude/stddef.h (__DEFINED_ptrdiff_t): Add support for musl libc typedef macro guard. (__DEFINED_size_t): Ditto. (__DEFINED_wchar_t): Ditto. --- gcc/ginclude/stddef.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'gcc') diff --git a/gcc/ginclude/stddef.h b/gcc/ginclude/stddef.h index 66619fe..50d710a 100644 --- a/gcc/ginclude/stddef.h +++ b/gcc/ginclude/stddef.h @@ -128,6 +128,7 @@ _TYPE_wchar_t; #ifndef ___int_ptrdiff_t_h #ifndef _GCC_PTRDIFF_T #ifndef _PTRDIFF_T_DECLARED /* DragonFly */ +#ifndef __DEFINED_ptrdiff_t /* musl libc */ #define _PTRDIFF_T #define _T_PTRDIFF_ #define _T_PTRDIFF @@ -137,10 +138,12 @@ _TYPE_wchar_t; #define ___int_ptrdiff_t_h #define _GCC_PTRDIFF_T #define _PTRDIFF_T_DECLARED +#define __DEFINED_ptrdiff_t #ifndef __PTRDIFF_TYPE__ #define __PTRDIFF_TYPE__ long int #endif typedef __PTRDIFF_TYPE__ ptrdiff_t; +#endif /* __DEFINED_ptrdiff_t */ #endif /* _PTRDIFF_T_DECLARED */ #endif /* _GCC_PTRDIFF_T */ #endif /* ___int_ptrdiff_t_h */ @@ -174,6 +177,7 @@ typedef __PTRDIFF_TYPE__ ptrdiff_t; #ifndef _SIZE_T_DEFINED #ifndef _BSD_SIZE_T_DEFINED_ /* Darwin */ #ifndef _SIZE_T_DECLARED /* FreeBSD 5 */ +#ifndef __DEFINED_size_t /* musl libc */ #ifndef ___int_size_t_h #ifndef _GCC_SIZE_T #ifndef _SIZET_ @@ -191,6 +195,7 @@ typedef __PTRDIFF_TYPE__ ptrdiff_t; #define _SIZE_T_DEFINED #define _BSD_SIZE_T_DEFINED_ /* Darwin */ #define _SIZE_T_DECLARED /* FreeBSD 5 */ +#define __DEFINED_size_t /* musl libc */ #define ___int_size_t_h #define _GCC_SIZE_T #define _SIZET_ @@ -215,6 +220,7 @@ typedef long ssize_t; #endif /* _SIZET_ */ #endif /* _GCC_SIZE_T */ #endif /* ___int_size_t_h */ +#endif /* __DEFINED_size_t */ #endif /* _SIZE_T_DECLARED */ #endif /* _BSD_SIZE_T_DEFINED_ */ #endif /* _SIZE_T_DEFINED */ @@ -251,6 +257,7 @@ typedef long ssize_t; #ifndef _BSD_WCHAR_T_DEFINED_ /* Darwin */ #ifndef _BSD_RUNE_T_DEFINED_ /* Darwin */ #ifndef _WCHAR_T_DECLARED /* FreeBSD 5 */ +#ifndef __DEFINED_wchar_t /* musl libc */ #ifndef _WCHAR_T_DEFINED_ #ifndef _WCHAR_T_DEFINED #ifndef _WCHAR_T_H @@ -272,6 +279,7 @@ typedef long ssize_t; #define __INT_WCHAR_T_H #define _GCC_WCHAR_T #define _WCHAR_T_DECLARED +#define __DEFINED_wchar_t /* On BSD/386 1.1, at least, machine/ansi.h defines _BSD_WCHAR_T_ instead of _WCHAR_T_, and _BSD_RUNE_T_ (which, unlike the other @@ -326,6 +334,7 @@ typedef __WCHAR_TYPE__ wchar_t; #endif #endif #endif +#endif /* __DEFINED_wchar_t */ #endif /* _WCHAR_T_DECLARED */ #endif /* _BSD_RUNE_T_DEFINED_ */ #endif -- cgit v1.1 From a2a0c91b47537b16908981e206f4e42db8425eca Mon Sep 17 00:00:00 2001 From: liuhongt Date: Tue, 14 Dec 2021 09:47:08 +0800 Subject: Fix ICE. [PR103682] Check is_gimple_assign before gimple_assign_rhs_code. gcc/ChangeLog: PR target/103682 * tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check is_gimple_assign before gimple_assign_rhs_code. gcc/testsuite/ChangeLog: * gcc.c-torture/compile/pr103682.c: New test. --- gcc/testsuite/gcc.c-torture/compile/pr103682.c | 3 +++ gcc/tree-ssa-ccp.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr103682.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.c-torture/compile/pr103682.c b/gcc/testsuite/gcc.c-torture/compile/pr103682.c new file mode 100644 index 0000000..5ee4b21 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr103682.c @@ -0,0 +1,3 @@ +int bug(unsigned *ready, unsigned u) { + return __atomic_fetch_and (ready, ~u, 0) & u; +} diff --git a/gcc/tree-ssa-ccp.c b/gcc/tree-ssa-ccp.c index 9e12da8..a5b1f60 100644 --- a/gcc/tree-ssa-ccp.c +++ b/gcc/tree-ssa-ccp.c @@ -3703,8 +3703,8 @@ optimize_atomic_bit_test_and (gimple_stmt_iterator *gsip, g = SSA_NAME_DEF_STMT (mask); } - rhs_code = gimple_assign_rhs_code (g); - if (rhs_code != LSHIFT_EXPR + if (!is_gimple_assign (g) + || gimple_assign_rhs_code (g) != LSHIFT_EXPR || !integer_onep (gimple_assign_rhs1 (g))) return; bit = gimple_assign_rhs2 (g); -- cgit v1.1 From 9c6586bc20ba49d6f42b889936cee0f7563a0966 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Wed, 15 Dec 2021 00:16:28 +0000 Subject: Daily bump. --- gcc/ChangeLog | 344 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/c/ChangeLog | 6 + gcc/cp/ChangeLog | 54 ++++++++ gcc/fortran/ChangeLog | 21 +++ gcc/jit/ChangeLog | 37 ++++++ gcc/testsuite/ChangeLog | 111 ++++++++++++++++ 7 files changed, 574 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 029d491..ca2c5ae 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,347 @@ +2021-12-14 liuhongt + + PR target/103682 + * tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check + is_gimple_assign before gimple_assign_rhs_code. + +2021-12-14 Sören Tempel + + * ginclude/stddef.h (__DEFINED_ptrdiff_t): Add support for musl + libc typedef macro guard. + (__DEFINED_size_t): Ditto. + (__DEFINED_wchar_t): Ditto. + +2021-12-14 JoJo R + + * regrename.c (find_rename_reg): Return satisfied regno + if instruction is noop move. + +2021-12-14 Bill Schmidt + + * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Rename + rs6000_builtin_decls_x to rs6000_builtin_decls. + (altivec_resolve_overloaded_builtin): Likewise. Also rename + rs6000_builtin_info_x to rs6000_builtin_info. + * config/rs6000/rs6000-call.c (rs6000_invalid_builtin): Rename + rs6000_builtin_info_x to rs6000_builtin_info. + (rs6000_builtin_is_supported): Likewise. + (rs6000_gimple_fold_mma_builtin): Likewise. Also rename + rs6000_builtin_decls_x to rs6000_builtin_decls. + (rs6000_gimple_fold_builtin): Rename rs6000_builtin_info_x to + rs6000_builtin_info. + (cpu_expand_builtin): Likewise. + (rs6000_expand_builtin): Likewise. + (rs6000_init_builtins): Likewise. Also rename rs6000_builtin_decls_x + to rs6000_builtin_decls. + (rs6000_builtin_decl): Rename rs6000_builtin_decls_x to + rs6000_builtin_decls. + * config/rs6000/rs6000-gen-builtins.c (write_decls): In generated code, + rename rs6000_builtin_decls_x to rs6000_builtin_decls, and rename + rs6000_builtin_info_x to rs6000_builtin_info. + (write_bif_static_init): In generated code, rename + rs6000_builtin_info_x to rs6000_builtin_info. + (write_init_bif_table): In generated code, rename + rs6000_builtin_decls_x to rs6000_builtin_decls, and rename + rs6000_builtin_info_x to rs6000_builtin_info. + (write_init_ovld_table): In generated code, rename + rs6000_builtin_decls_x to rs6000_builtin_decls. + (write_init_file): Likewise. + * config/rs6000/rs6000.c (rs6000_builtin_vectorized_function): + Likewise. + (rs6000_builtin_md_vectorized_function): Likewise. + (rs6000_builtin_reciprocal): Likewise. + (add_condition_to_bb): Likewise. + (rs6000_atomic_assign_expand_fenv): Likewise. + +2021-12-14 Bill Schmidt + + * config/rs6000/rs6000-c.c (altivec_resolve_new_overloaded_builtin): + Remove forward declaration. + (rs6000_new_builtin_type_compatible): Rename to + rs6000_builtin_type_compatible. + (rs6000_builtin_type_compatible): Remove. + (altivec_resolve_overloaded_builtin): Remove. + (altivec_build_new_resolved_builtin): Rename to + altivec_build_resolved_builtin. + (altivec_resolve_new_overloaded_builtin): Rename to + altivec_resolve_overloaded_builtin. Remove static keyword. Adjust + called function names. + * config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Remove + forward declaration. + (rs6000_gimple_fold_new_builtin): Likewise. + (rs6000_invalid_new_builtin): Rename to rs6000_invalid_builtin. + (rs6000_gimple_fold_builtin): Remove. + (rs6000_new_builtin_valid_without_lhs): Rename to + rs6000_builtin_valid_without_lhs. + (rs6000_new_builtin_is_supported): Rename to + rs6000_builtin_is_supported. + (rs6000_gimple_fold_new_mma_builtin): Rename to + rs6000_gimple_fold_mma_builtin. + (rs6000_gimple_fold_new_builtin): Rename to + rs6000_gimple_fold_builtin. Remove static keyword. Adjust called + function names. + (rs6000_expand_builtin): Remove. + (new_cpu_expand_builtin): Rename to cpu_expand_builtin. + (new_mma_expand_builtin): Rename to mma_expand_builtin. + (new_htm_spr_num): Rename to htm_spr_num. + (new_htm_expand_builtin): Rename to htm_expand_builtin. Change name + of called function. + (rs6000_expand_new_builtin): Rename to rs6000_expand_builtin. Remove + static keyword. Adjust called function names. + (rs6000_new_builtin_decl): Rename to rs6000_builtin_decl. Remove + static keyword. + (rs6000_builtin_decl): Remove. + * config/rs6000/rs6000-gen-builtins.c (write_decls): In gnerated code, + rename rs6000_new_builtin_is_supported to rs6000_builtin_is_supported. + * config/rs6000/rs6000-internal.h (rs6000_invalid_new_builtin): Rename + to rs6000_invalid_builtin. + * config/rs6000/rs6000.c (rs6000_new_builtin_vectorized_function): + Rename to rs6000_builtin_vectorized_function. + (rs6000_new_builtin_md_vectorized_function): Rename to + rs6000_builtin_md_vectorized_function. + (rs6000_builtin_vectorized_function): Remove. + (rs6000_builtin_md_vectorized_function): Remove. + +2021-12-14 Bill Schmidt + + * config/rs6000/rs6000-builtin.def: Delete. + * config/rs6000/rs6000-call.c (builtin_compatibility): Delete. + (builtin_description): Delete. + (builtin_hash_struct): Delete. + (builtin_hasher): Delete. + (builtin_hash_table): Delete. + (builtin_hasher::hash): Delete. + (builtin_hasher::equal): Delete. + (rs6000_builtin_info_type): Delete. + (rs6000_builtin_info): Delete. + (bdesc_compat): Delete. + (bdesc_3arg): Delete. + (bdesc_4arg): Delete. + (bdesc_dst): Delete. + (bdesc_2arg): Delete. + (bdesc_altivec_preds): Delete. + (bdesc_abs): Delete. + (bdesc_1arg): Delete. + (bdesc_0arg): Delete. + (bdesc_htm): Delete. + (bdesc_mma): Delete. + (rs6000_overloaded_builtin_p): Delete. + (rs6000_overloaded_builtin_name): Delete. + (htm_spr_num): Delete. + (rs6000_builtin_is_supported_p): Delete. + (rs6000_gimple_fold_mma_builtin): Delete. + (gt-rs6000-call.h): Remove include directive. + * config/rs6000/rs6000-protos.h (rs6000_overloaded_builtin_p): Delete. + (rs6000_builtin_is_supported_p): Delete. + (rs6000_overloaded_builtin_name): Delete. + * config/rs6000/rs6000.c (rs6000_builtin_decls): Delete. + (rs6000_debug_reg_global): Remove reference to RS6000_BUILTIN_COUNT. + * config/rs6000/rs6000.h (rs6000_builtins): Delete. + (altivec_builtin_types): Delete. + (rs6000_builtin_decls): Delete. + * config/rs6000/t-rs6000 (TM_H): Don't add rs6000-builtin.def. + +2021-12-14 Bill Schmidt + + * config/rs6000/rs6000-builtin-new.def: Rename to... + * config/rs6000/rs6000-builtins.def: ...this. + * config/rs6000/rs6000-gen-builtins.c: Adjust header commentary. + * config/rs6000/t-rs6000 (EXTRA_GTYPE_DEPS): Rename + rs6000-builtin-new.def to rs6000-builtins.def. + (rs6000-builtins.c): Likewise. + +2021-12-14 Bill Schmidt + + * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Remove. + * config/rs6000/rs6000.h (altivec_overloaded_builtins): Remove. + +2021-12-14 Peter Bergner + + PR target/103548 + * config/rs6000/mma.md (UNSPEC_MMA_ASSEMBLE): Rename unspec from this... + (UNSPEC_VSX_ASSEMBLE): ...to this. + (UNSPECV_MMA_ASSEMBLE): New unspecv. + (vsx_assemble_pair): Use UNSPEC_VSX_ASSEMBLE. + (*vsx_assemble_pair): Likewise. + (mma_assemble_acc): Use UNSPECV_MMA_ASSEMBLE. + (*mma_assemble_acc): Likewise. + * config/rs6000/rs6000.c (rs6000_split_multireg_move): Handle + UNSPEC_VOLATILE. Use UNSPEC_VSX_ASSEMBLE and UNSPECV_MMA_ASSEMBLE. + +2021-12-14 Uroš Bizjak + + PR target/103571 + * config/i386/i386-expand.c (ix86_expand_vector_init_duplicate) + : Implement for TARGET_SSE2. + : Implement for TARGET_AVX. + : Implement for TARGET_AVX512F. + (ix86_expand_vector_set_var): Handle V32HFmode + without TARGET_AVX512BW. + (ix86_expand_vector_extract) + : Implement for TARGET_SSE2. + : Implement for TARGET_AVX. + : Implement for TARGET_AVX512BW. + (expand_vec_perm_broadcast_1) : New. + * config/i386/sse.md (VI12HF_AVX512VL): Remove + TARGET_AVX512FP16 condition. + (V): Ditto. + (V_256_512): Ditto. + (avx_vbroadcastf128_): Use V_256H mode iterator. + +2021-12-14 Bill Schmidt + + * config/rs6000/darwin.h (SUBTARGET_INIT_BUILTINS): Remove + test for new_builtins_are_live and simplify. + * config/rs6000/rs6000-c.c (altivec_build_resolved_builtin): Remove + dead function. + (altivec_resolve_overloaded_builtin): Remove test for + new_builtins_are_live and simplify. + * config/rs6000/rs6000-call.c (altivec_init_builtins): Remove forward + declaration. + (builtin_function_type): Likewise. + (rs6000_common_init_builtins): Likewise. + (htm_init_builtins): Likewise. + (mma_init_builtins): Likewise. + (def_builtin): Remove dead function. + (rs6000_expand_zeroop_builtin): Likewise. + (rs6000_expand_mtfsf_builtin): Likewise. + (rs6000_expand_mtfsb_builtin): Likewise. + (rs6000_expand_set_fpscr_rn_builtin): Likewise. + (rs6000_expand_set_fpscr_drn_builtin): Likewise. + (rs6000_expand_unop_builtin): Likewise. + (altivec_expand_abs_builtin): Likewise. + (rs6000_expand_binop_builtin): Likewise. + (altivec_expand_lxvr_builtin): Likewise. + (altivec_expand_lv_builtin): Likewise. + (altivec_expand_stxvl_builtin): Likewise. + (altivec_expand_stv_builtin): Likewise. + (mma_expand_builtin): Likewise. + (htm_expand_builtin): Likewise. + (cpu_expand_builtin): Likewise. + (rs6000_expand_quaternop_builtin): Likewise. + (rs6000_expand_ternop_builtin): Likewise. + (altivec_expand_dst_builtin): Likewise. + (altivec_expand_vec_sel_builtin): Likewise. + (altivec_expand_builtin): Likewise. + (rs6000_invalid_builtin): Likewise. + (rs6000_builtin_valid_without_lhs): Likewise. + (rs6000_gimple_fold_builtin): Remove test for new_builtins_are_live and + simplify. + (rs6000_expand_builtin): Likewise. + (rs6000_init_builtins): Remove tests for new_builtins_are_live and + simplify. + (rs6000_builtin_decl): Likewise. + (altivec_init_builtins): Remove dead function. + (mma_init_builtins): Likewise. + (htm_init_builtins): Likewise. + (builtin_quaternary_function_type): Likewise. + (builtin_function_type): Likewise. + (rs6000_common_init_builtins): Likewise. + * config/rs6000/rs6000-gen-builtins.c (write_header_file): Don't + declare new_builtins_are_live. + (write_init_bif_table): In generated code, remove test for + new_builtins_are_live and simplify. + (write_init_ovld_table): Likewise. + (write_init_file): Don't initialize new_builtins_are_live. + * config/rs6000/rs6000.c (rs6000_builtin_vectorized_function): Remove + test for new_builtins_are_live and simplify. + (rs6000_builtin_md_vectorized_function): Likewise. + (rs6000_builtin_reciprocal): Likewise. + (add_condition_to_bb): Likewise. + (rs6000_atomic_assign_expand_fenv): Likewise. + +2021-12-14 Bill Schmidt + + PR target/103625 + * config/rs6000/rs6000-builtin-new.def (__builtin_altivec_vcmpequd): + Move to power8-vector stanza. + (__builtin_altivec_vcmpequd_p): Likewise. + (__builtin_altivec_vcmpgtsd): Likewise. + (__builtin_altivec_vcmpgtsd_p): Likewise. + (__builtin_altivec_vcmpgtud): Likewise. + (__builtin_altivec_vcmpgtud_p): Likewise. + +2021-12-14 Bill Schmidt + + PR target/103623 + * config/rs6000/rs6000-builtin-new.def (__builtin_pack_longdouble): Add + ibmld attribute. + (__builtin_unpack_longdouble): Likewise. + * config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Add special + handling for ibmld attribute. + * config/rs6000/rs6000-gen-builtins.c (attrinfo): Add isibmld. + (parse_bif_attrs): Handle ibmld. + (write_decls): Likewise. + (write_bif_static_init): Likewise. + +2021-12-14 Jan Hubicka + + PR ipa/103585 + * ipa-modref-tree.c (modref_access_node::range_info_useful_p): Handle + MODREF_GLOBAL_MEMORY_PARM. + (modref_access_node::dump): Likewise. + (modref_access_node::get_call_arg): Likewise. + * ipa-modref-tree.h (enum modref_special_parms): Add + MODREF_GLOBAL_MEMORY_PARM. + (modref_access_node::useful_for_kill): Handle + MODREF_GLOBAL_MEMORY_PARM. + (modref:tree::merge): Add promote_unknown_to_global. + * ipa-modref.c (verify_arg):New function. + (may_access_nonescaping_parm_p): New function. + (modref_access_analysis::record_global_memory_load): New member + function. + (modref_access_analysis::record_global_memory_store): Likewise. + (modref_access_analysis::process_fnspec): Distingush global and local + memory. + (modref_access_analysis::analyze_call): Likewise. + * tree-ssa-alias.c (ref_may_access_global_memory_p): New function. + (modref_may_conflict): Use it. + +2021-12-14 Przemyslaw Wirkus + + * config/aarch64/aarch64-builtins.c (enum aarch64_builtins): + Define AARCH64_LS64_BUILTIN_LD64B, AARCH64_LS64_BUILTIN_ST64B, + AARCH64_LS64_BUILTIN_ST64BV, AARCH64_LS64_BUILTIN_ST64BV0. + (aarch64_init_ls64_builtin_decl): Helper function. + (aarch64_init_ls64_builtins): Helper function. + (aarch64_init_ls64_builtins_types): Helper function. + (aarch64_general_init_builtins): Init LS64 intrisics for + TARGET_LS64. + (aarch64_expand_builtin_ls64): LS64 intrinsics expander. + (aarch64_general_expand_builtin): Handle aarch64_expand_builtin_ls64. + (ls64_builtins_data): New helper struct. + (v8di_UP): New define. + * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define + __ARM_FEATURE_LS64. + * config/aarch64/aarch64.c (aarch64_classify_address): Enforce the + V8DI range (7-bit signed scaled) for both ends of the range. + * config/aarch64/aarch64-simd.md (movv8di): New pattern. + (aarch64_movv8di): New pattern. + * config/aarch64/aarch64.h (AARCH64_ISA_LS64): New define. + (TARGET_LS64): New define. + * config/aarch64/aarch64.md: Add UNSPEC_LD64B, UNSPEC_ST64B, + UNSPEC_ST64BV and UNSPEC_ST64BV0. + (ld64b): New define_insn. + (st64b): New define_insn. + (st64bv): New define_insn. + (st64bv0): New define_insn. + * config/aarch64/arm_acle.h (data512_t): New type derived from + __arm_data512_t. + (__arm_data512_t): New internal type. + (__arm_ld64b): New intrinsic. + (__arm_st64b): New intrinsic. + (__arm_st64bv): New intrinsic. + (__arm_st64bv0): New intrinsic. + * config/arm/types.md: Add new type ls64. + +2021-12-14 Olivier Hainque + + * config/i386/t-vxworks: Drop the fPIC multilibs. + +2021-12-14 Fred Konrad + + * config/rs6000/t-vxworks: Drop the fPIC multilib. + 2021-12-13 Vladimir N. Makarov PR target/99531 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index e502600..c11bfa6 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20211214 +20211215 diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog index 90c0640..e9c054d 100644 --- a/gcc/c/ChangeLog +++ b/gcc/c/ChangeLog @@ -1,3 +1,9 @@ +2021-12-14 Jakub Jelinek + + PR c/103587 + * c-parser.c (c_parser_balanced_token_sequence): For CPP_PRAGMA, + consume the pragma and silently skip to the pragma eol. + 2021-12-12 Jonathan Wakely * c-decl.c: Define INCLUDE_MEMORY instead of INCLUDE_UNIQUE_PTR. diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 0cdb2e1..c72be7d 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,57 @@ +2021-12-14 Patrick Palka + + PR c++/103408 + * constraint.cc (type_deducible_p): Remove workaround for + non-templated requires-expressions. + (normalize_placeholder_type_constraints): Likewise. + * cp-tree.h (current_template_depth): Define. + (PROCESSING_REAL_TEMPLATE_DECL): Inspect current_template_depth + instead of the magnitude of processing_template_decl. + * decl.c (start_decl): Likewise. + (grokfndecl): Likewise. + (grokvardecl): Likewise. + (grokdeclarator): Likewise. + * friend.c (make_friend_class): Likewise. Calculate + friend_depth differently when called at instantiation time + instead of parse time. + (do_friend): Likewise. + * parser.c (cp_parser_requires_clause_expression): Remove + workaround for lambdas inside constraints. + (cp_parser_constraint_expression): Likewise. + (cp_parser_requires_expression): Likewise. + (synthesize_implicit_template_parm): Add to current_template_parms + before calling process_template_parm. + * pt.c (inline_needs_template_parms): Inspect + current_template_depth instead of the magnitude of + processing_template_decl. + (push_inline_template_parms_recursive): Likewise. + (maybe_begin_member_template_processing): Likewise. + (begin_template_parm_list): Likewise. + (process_template_parm): Likewise. + (end_template_parm_list): Likewise. + (push_template_decl): Likewise. + (add_inherited_template_parms): Likewise. + (instantiate_class_template_1): Don't adjust + processing_template_decl around the call to make_friend_class. + adjust_processing_template_decl to adjust_template_depth. Set + current_template_parms instead of processing_template_decl when + adjust_template_depth. + (make_auto_1): Inspect current_template_depth instead of the + magnitude of processing_template_decl. + (splice_late_return_type): Likewise. + * semantics.c (fixup_template_type): Likewise. + +2021-12-14 Patrick Palka + + * call.c (build_new_op): Use releasing_vec for arglist. Declare + conv in the scope it's used. + +2021-12-14 Patrick Palka + + * cp-tree.h (COMPOUND_EXPR_OVERLOADED): Remove. + * pt.c (build_non_dependent_expr): Don't inspect the flag. + * tree.c (build_min_non_dep): Don't set the flag. + 2021-12-12 Jonathan Wakely * error.c: Define INCLUDE_MEMORY instead of diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index fc7bea1..264fa1b 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,24 @@ +2021-12-14 Harald Anlauf + + PR fortran/103717 + * frontend-passes.c (doloop_code): Prevent NULL pointer + dereference when checking for passing a do-loop variable to a + contained procedure with an interface mismatch. + +2021-12-14 Harald Anlauf + + PR fortran/103718 + PR fortran/103719 + * frontend-passes.c (doloop_contained_procedure_code): Add several + checks to prevent NULL pointer dereferences on valid and invalid + code called within do-loops. + +2021-12-14 Manfred Schwarb + + PR fortran/91497 + * simplify.c (simplify_min_max): Disable conversion warnings for + MIN1 and MAX1. + 2021-12-13 Tobias Burnus PR fortran/103576 diff --git a/gcc/jit/ChangeLog b/gcc/jit/ChangeLog index ab06d51..0b44fc1 100644 --- a/gcc/jit/ChangeLog +++ b/gcc/jit/ChangeLog @@ -1,3 +1,40 @@ +2021-12-14 Petter Tomner + + * jit-common.h: New enum + * jit-playback.c : Folding an setting intitial + (global_new_decl) : Handle const global generation + (new_global) : New flag + (global_set_init_rvalue) : New + (new_ctor) : New + (new_global_initialized) : Flag + (as_truth_value) : Fold + (new_unary_op) : Fold + (new_binary_op) : Fold + (new_comparison) : Fold + (new_array_access) : Fold + (new_dereference) : Fold + (get_address) : Fold + * jit-playback.h : + (global_set_init_rvalue) : New + (new_ctor) : New + * jit-recording.c : + * jit-recording.h : + (new_global_init_rvalue) : New + (new_ctor) : New + (ctor) : New, inherits rvalue + (global_init_rvalue) : New, inherits memento + (type::is_union) : New + * libgccjit++.h : New entrypoints, see C-header + * libgccjit.c : See .h + * libgccjit.h : New entrypoints + (gcc_jit_context_new_array_constructor) : New + (gcc_jit_context_new_struct_constructor) : New + (gcc_jit_context_new_union_constructor) : New + (gcc_jit_global_set_initializer_rvalue) : New + (LIBGCCJIT_HAVE_CTORS) : New feuture macro + * libgccjit.map : New entrypoints added to ABI 19 + * docs/topics/expressions.rst : Updated docs + 2021-12-12 Antoni Boucher PR target/100688 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1a61c86..3dffea8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,114 @@ +2021-12-14 liuhongt + + * gcc.c-torture/compile/pr103682.c: New test. + +2021-12-14 Peter Bergner + + PR target/103548 + * gcc.target/powerpc/mma-builtin-10-pair.c: New test. + * gcc.target/powerpc/mma-builtin-10-quad.c: New test. + +2021-12-14 Harald Anlauf + + PR fortran/103717 + * gfortran.dg/do_check_19.f90: New test. + +2021-12-14 Harald Anlauf + + PR fortran/103718 + PR fortran/103719 + * gfortran.dg/do_check_18.f90: New test. + +2021-12-14 Petter Tomner + + * jit.dg/all-non-failing-tests.h: Added two tests + * jit.dg/test-error-ctor-array-wrong-obj.c: New + * jit.dg/test-error-ctor-struct-too-big.c: New + * jit.dg/test-error-ctor-struct-wrong-field-obj.c: New + * jit.dg/test-error-ctor-struct-wrong-type.c: New + * jit.dg/test-error-ctor-struct-wrong-type2.c + * jit.dg/test-error-ctor-union-wrong-field-name.c: New + * jit.dg/test-error-global-already-init.c: New + * jit.dg/test-error-global-common-section.c: New + * jit.dg/test-error-global-init-too-small-array.c: New + * jit.dg/test-error-global-lvalue-init.c: New + * jit.dg/test-error-global-nonconst-init.c: New + * jit.dg/test-global-init-rvalue.c: New + * jit.dg/test-local-init-rvalue.c: New + +2021-12-14 Harald Anlauf + + PR libfortran/103634 + * gfortran.dg/intrinsic_pack_6.f90: New test. + +2021-12-14 Jan Hubicka + + * gcc.dg/analyzer/data-model-1.c: Disable ipa-modref. + * gcc.dg/uninit-38.c: Likewise. + * gcc.dg/uninit-pr98578.c: Liewise. + +2021-12-14 Manfred Schwarb + + PR fortran/91497 + * gfortran.dg/pr91497.f90: Adjust test to use + dg-require-effective-target directive. + * gfortran.dg/pr91497_2.f90: New test to cover all targets. + Cover MAX1 and MIN1 intrinsics. + +2021-12-14 Vladimir N. Makarov + + PR target/99531 + * gcc.target/i386/pr99531.c: Do not scan for ia32. + +2021-12-14 Przemyslaw Wirkus + + * gcc.target/aarch64/acle/ls64_asm.c: New test. + * gcc.target/aarch64/acle/ls64_ld64b.c: New test. + * gcc.target/aarch64/acle/ls64_ld64b-2.c: New test. + * gcc.target/aarch64/acle/ls64_ld64b-3.c: New test. + * gcc.target/aarch64/acle/ls64_st64b.c: New test. + * gcc.target/aarch64/acle/ls64_ld_st_o0.c: New test. + * gcc.target/aarch64/acle/ls64_st64b-2.c: New test. + * gcc.target/aarch64/acle/ls64_st64bv.c: New test. + * gcc.target/aarch64/acle/ls64_st64bv-2.c: New test. + * gcc.target/aarch64/acle/ls64_st64bv-3.c: New test. + * gcc.target/aarch64/acle/ls64_st64bv0.c: New test. + * gcc.target/aarch64/acle/ls64_st64bv0-2.c: New test. + * gcc.target/aarch64/acle/ls64_st64bv0-3.c: New test. + * gcc.target/aarch64/pragma_cpp_predefs_2.c: Add checks + for __ARM_FEATURE_LS64. + +2021-12-14 Martin Liska + + * gcc.target/i386/avx2-psraq-1.c: Use ARRAY_SIZE. + * gcc.target/i386/m128-check.h: Move it to the top-level + context. + * gcc.target/i386/sse2-psraq-1.c: Use ARRAY_SIZE. + * gcc.target/i386/sse4_2-check.h: Include the header with + ARRAY_SIZE definition. + +2021-12-14 Patrick Palka + + PR c++/103408 + * g++.dg/concepts/diagnostic18.C: Expect a "constraints on a + non-templated function" error. + * g++.dg/cpp23/auto-fncast11.C: New test. + +2021-12-14 Jakub Jelinek + + PR c/103587 + * gcc.dg/pr103587.c: New test. + +2021-12-14 Thomas Schwinge + + PR fortran/103576 + PR testsuite/103697 + * gfortran.dg/goacc/privatization-1-compute-loop.f90: Adjust. + * gfortran.dg/goacc/privatization-1-compute.f90: Likewise. + * gfortran.dg/goacc/privatization-1-routine_gang-loop.f90: + Likewise. + * gfortran.dg/goacc/privatization-1-routine_gang.f90: Likewise. + 2021-12-13 Vladimir N. Makarov PR target/99531 -- cgit v1.1 From c95a9f1ee7ebd461cbced455271a993bae3a42b6 Mon Sep 17 00:00:00 2001 From: Alexandre Oliva Date: Wed, 15 Dec 2021 02:22:33 -0300 Subject: [PR100843] store by mult pieces: punt on max_len < min_len The testcase confuses the code that detects min and max len for the memset, so max_len ends up less than min_len. That shouldn't be possible, but the testcase requires us to handle this case. The store-by-mult-pieces algorithm actually relies on min and max lengths, so if we find them to be inconsistent, the best we can do is punting. for gcc/ChangeLog PR middle-end/100843 * builtins.c (try_store_by_multiple_pieces): Fail if min_len is greater than max_len. for gcc/testsuite/ChangeLog PR middle-end/100843 * gcc.dg/pr100843.c: New. --- gcc/builtins.c | 3 ++- gcc/testsuite/gcc.dg/pr100843.c | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.dg/pr100843.c (limited to 'gcc') diff --git a/gcc/builtins.c b/gcc/builtins.c index 03829c0..304d87d 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -3963,7 +3963,8 @@ try_store_by_multiple_pieces (rtx to, rtx len, unsigned int ctz_len, else if (max_len == min_len) blksize = max_len; else - gcc_unreachable (); + /* Huh, max_len < min_len? Punt. See pr100843.c. */ + return false; if (min_len >= blksize) { min_len -= blksize; diff --git a/gcc/testsuite/gcc.dg/pr100843.c b/gcc/testsuite/gcc.dg/pr100843.c new file mode 100644 index 0000000..695a2ec --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr100843.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -w" } */ + +char c; +void *memset(); +void test_integer_conversion_memset(void *d) { + memset(d, '\0', c); +} -- cgit v1.1 From 71cc9b8c39148d19a8043b74ca8b6b4e8b8072ca Mon Sep 17 00:00:00 2001 From: Alexandre Oliva Date: Wed, 15 Dec 2021 02:22:34 -0300 Subject: [PR100518] store by mult pieces: keep addr in Pmode The conversion of a MEM address to ptr_mode in try_store_by_multiple_pieces was misguided: copy_addr_to_reg expects Pmode for addresses. for gcc/ChangeLog PR target/100518 * builtins.c (try_store_by_multiple_pieces): Drop address conversion to ptr_mode. for gcc/testsuite/ChangeLog PR target/100518 * gcc.target/aarch64/pr100518.c: New. --- gcc/builtins.c | 2 +- gcc/testsuite/gcc.target/aarch64/pr100518.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr100518.c (limited to 'gcc') diff --git a/gcc/builtins.c b/gcc/builtins.c index 304d87d..cd8947b 100644 --- a/gcc/builtins.c +++ b/gcc/builtins.c @@ -4003,7 +4003,7 @@ try_store_by_multiple_pieces (rtx to, rtx len, unsigned int ctz_len, constfundata = &valc; } - rtx ptr = copy_addr_to_reg (convert_to_mode (ptr_mode, XEXP (to, 0), 0)); + rtx ptr = copy_addr_to_reg (XEXP (to, 0)); rtx rem = copy_to_mode_reg (ptr_mode, convert_to_mode (ptr_mode, len, 0)); to = replace_equiv_address (to, ptr); set_mem_align (to, align); diff --git a/gcc/testsuite/gcc.target/aarch64/pr100518.c b/gcc/testsuite/gcc.target/aarch64/pr100518.c new file mode 100644 index 0000000..5ca599f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr100518.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-mabi=ilp32 -mstrict-align -O2" } */ + +int unsigned_range_min, unsigned_range_max, a11___trans_tmp_1; + +void a11() { + a11___trans_tmp_1 = unsigned_range_max < unsigned_range_min; + __builtin_memset((char *)1, 0, a11___trans_tmp_1); +} -- cgit v1.1 From c6756b3bc1d2af1c8e86f0ad1711e9b9134520ba Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 15 Dec 2021 00:56:25 -0500 Subject: Add new constant data structure. This patch provides the data structure and function to convert a CONST_INT, CONST_DOUBLE, CONST_VECTOR, or VEC_DUPLICATE of a constant) to an array of bytes, half-words, words, and double words that can be loaded into a 128-bit vector register. The next patches will use this data structure to generate code that generates load of the vector/floating point registers using the XXSPLTIDP, XXSPLTIW, and LXVKQ instructions that were added in power10. 2021-12-15 Michael Meissner gcc/ * config/rs6000/rs6000-protos.h (VECTOR_128BIT_BITS): New macro. (VECTOR_128BIT_BYTES): Likewise. (VECTOR_128BIT_HALF_WORDS): Likewise. (VECTOR_128BIT_WORDS): Likewise. (VECTOR_128BIT_DOUBLE_WORDS): Likewise. (vec_const_128bit_type): New structure type. (vec_const_128bit_to_bytes): New declaration. * config/rs6000/rs6000.c (constant_int_to_128bit_vector): New helper function. (constant_fp_to_128bit_vector): New helper function. (vec_const_128bit_to_bytes): New function. --- gcc/config/rs6000/rs6000-protos.h | 28 +++++ gcc/config/rs6000/rs6000.c | 253 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 281 insertions(+) (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index c01ae00..81345d8 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -222,6 +222,34 @@ address_is_prefixed (rtx addr, return (iform == INSN_FORM_PREFIXED_NUMERIC || iform == INSN_FORM_PCREL_LOCAL); } + +/* Functions and data structures relating to 128-bit constants that are + converted to byte, half-word, word, and double-word values. All fields are + kept in big endian order. We also convert scalar values to 128-bits if they + are going to be loaded into vector registers. */ +#define VECTOR_128BIT_BITS 128 +#define VECTOR_128BIT_BYTES (128 / 8) +#define VECTOR_128BIT_HALF_WORDS (128 / 16) +#define VECTOR_128BIT_WORDS (128 / 32) +#define VECTOR_128BIT_DOUBLE_WORDS (128 / 64) + +typedef struct { + /* Constant as various sized items. */ + unsigned HOST_WIDE_INT double_words[VECTOR_128BIT_DOUBLE_WORDS]; + unsigned int words[VECTOR_128BIT_WORDS]; + unsigned short half_words[VECTOR_128BIT_HALF_WORDS]; + unsigned char bytes[VECTOR_128BIT_BYTES]; + + unsigned original_size; /* Constant size before splat. */ + bool fp_constant_p; /* Is the constant floating point? */ + bool all_double_words_same; /* Are the double words all equal? */ + bool all_words_same; /* Are the words all equal? */ + bool all_half_words_same; /* Are the half words all equal? */ + bool all_bytes_same; /* Are the bytes all equal? */ +} vec_const_128bit_type; + +extern bool vec_const_128bit_to_bytes (rtx, machine_mode, + vec_const_128bit_type *); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 4481ba5..819314d 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -28334,6 +28334,259 @@ rs6000_output_addr_vec_elt (FILE *file, int value) fprintf (file, "\n"); } + +/* Copy an integer constant to the vector constant structure. */ + +static void +constant_int_to_128bit_vector (rtx op, + machine_mode mode, + size_t byte_num, + vec_const_128bit_type *info) +{ + unsigned HOST_WIDE_INT uvalue = UINTVAL (op); + unsigned bitsize = GET_MODE_BITSIZE (mode); + + for (int shift = bitsize - 8; shift >= 0; shift -= 8) + info->bytes[byte_num++] = (uvalue >> shift) & 0xff; +} + +/* Copy a floating point constant to the vector constant structure. */ + +static void +constant_fp_to_128bit_vector (rtx op, + machine_mode mode, + size_t byte_num, + vec_const_128bit_type *info) +{ + unsigned bitsize = GET_MODE_BITSIZE (mode); + unsigned num_words = bitsize / 32; + const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op); + long real_words[VECTOR_128BIT_WORDS]; + + /* Make sure we don't overflow the real_words array and that it is + filled completely. */ + gcc_assert (num_words <= VECTOR_128BIT_WORDS && (bitsize % 32) == 0); + + real_to_target (real_words, rtype, mode); + + /* Iterate over each 32-bit word in the floating point constant. The + real_to_target function puts out words in target endian fashion. We need + to arrange the order so that the bytes are written in big endian order. */ + for (unsigned num = 0; num < num_words; num++) + { + unsigned endian_num = (BYTES_BIG_ENDIAN + ? num + : num_words - 1 - num); + + unsigned uvalue = real_words[endian_num]; + for (int shift = 32 - 8; shift >= 0; shift -= 8) + info->bytes[byte_num++] = (uvalue >> shift) & 0xff; + } + + /* Mark that this constant involves floating point. */ + info->fp_constant_p = true; +} + +/* Convert a vector constant OP with mode MODE to a vector 128-bit constant + structure INFO. + + Break out the constant out to bytes, half words, words, and double words. + Return true if we have successfully converted the constant. + + We handle CONST_INT, CONST_DOUBLE, CONST_VECTOR, and VEC_DUPLICATE of + constants. Integer and floating point scalar constants are splatted to fill + out the vector. */ + +bool +vec_const_128bit_to_bytes (rtx op, + machine_mode mode, + vec_const_128bit_type *info) +{ + /* Initialize the constant structure. */ + memset ((void *)info, 0, sizeof (vec_const_128bit_type)); + + /* Assume CONST_INTs are DImode. */ + if (mode == VOIDmode) + mode = CONST_INT_P (op) ? DImode : GET_MODE (op); + + if (mode == VOIDmode) + return false; + + unsigned size = GET_MODE_SIZE (mode); + bool splat_p = false; + + if (size > VECTOR_128BIT_BYTES) + return false; + + /* Set up the bits. */ + switch (GET_CODE (op)) + { + /* Integer constants, default to double word. */ + case CONST_INT: + { + constant_int_to_128bit_vector (op, mode, 0, info); + splat_p = true; + break; + } + + /* Floating point constants. */ + case CONST_DOUBLE: + { + /* Fail if the floating point constant is the wrong mode. */ + if (GET_MODE (op) != mode) + return false; + + /* SFmode stored as scalars are stored in DFmode format. */ + if (mode == SFmode) + { + mode = DFmode; + size = GET_MODE_SIZE (DFmode); + } + + constant_fp_to_128bit_vector (op, mode, 0, info); + splat_p = true; + break; + } + + /* Vector constants, iterate over each element. On little endian + systems, we have to reverse the element numbers. */ + case CONST_VECTOR: + { + /* Fail if the vector constant is the wrong mode or size. */ + if (GET_MODE (op) != mode + || GET_MODE_SIZE (mode) != VECTOR_128BIT_BYTES) + return false; + + machine_mode ele_mode = GET_MODE_INNER (mode); + size_t ele_size = GET_MODE_SIZE (ele_mode); + size_t nunits = GET_MODE_NUNITS (mode); + + for (size_t num = 0; num < nunits; num++) + { + rtx ele = CONST_VECTOR_ELT (op, num); + size_t byte_num = (BYTES_BIG_ENDIAN + ? num + : nunits - 1 - num) * ele_size; + + if (CONST_INT_P (ele)) + constant_int_to_128bit_vector (ele, ele_mode, byte_num, info); + else if (CONST_DOUBLE_P (ele)) + constant_fp_to_128bit_vector (ele, ele_mode, byte_num, info); + else + return false; + } + + break; + } + + /* Treat VEC_DUPLICATE of a constant just like a vector constant. + Since we are duplicating the element, we don't have to worry about + endian issues. */ + case VEC_DUPLICATE: + { + /* Fail if the vector duplicate is the wrong mode or size. */ + if (GET_MODE (op) != mode + || GET_MODE_SIZE (mode) != VECTOR_128BIT_BYTES) + return false; + + machine_mode ele_mode = GET_MODE_INNER (mode); + size_t ele_size = GET_MODE_SIZE (ele_mode); + rtx ele = XEXP (op, 0); + size_t nunits = GET_MODE_NUNITS (mode); + + if (!CONST_INT_P (ele) && !CONST_DOUBLE_P (ele)) + return false; + + for (size_t num = 0; num < nunits; num++) + { + size_t byte_num = num * ele_size; + + if (CONST_INT_P (ele)) + constant_int_to_128bit_vector (ele, ele_mode, byte_num, info); + else + constant_fp_to_128bit_vector (ele, ele_mode, byte_num, info); + } + + break; + } + + /* Any thing else, just return failure. */ + default: + return false; + } + + /* Splat the constant to fill 128 bits if desired. */ + if (splat_p && size < VECTOR_128BIT_BYTES) + { + if ((VECTOR_128BIT_BYTES % size) != 0) + return false; + + for (size_t offset = size; + offset < VECTOR_128BIT_BYTES; + offset += size) + memcpy ((void *) &info->bytes[offset], + (void *) &info->bytes[0], + size); + } + + /* Remember original size. */ + info->original_size = size; + + /* Determine if the bytes are all the same. */ + unsigned char first_byte = info->bytes[0]; + info->all_bytes_same = true; + for (size_t i = 1; i < VECTOR_128BIT_BYTES; i++) + if (first_byte != info->bytes[i]) + { + info->all_bytes_same = false; + break; + } + + /* Pack half words together & determine if all of the half words are the + same. */ + for (size_t i = 0; i < VECTOR_128BIT_HALF_WORDS; i++) + info->half_words[i] = ((info->bytes[i * 2] << 8) + | info->bytes[(i * 2) + 1]); + + unsigned short first_hword = info->half_words[0]; + info->all_half_words_same = true; + for (size_t i = 1; i < VECTOR_128BIT_HALF_WORDS; i++) + if (first_hword != info->half_words[i]) + { + info->all_half_words_same = false; + break; + } + + /* Pack words together & determine if all of the words are the same. */ + for (size_t i = 0; i < VECTOR_128BIT_WORDS; i++) + info->words[i] = ((info->bytes[i * 4] << 24) + | (info->bytes[(i * 4) + 1] << 16) + | (info->bytes[(i * 4) + 2] << 8) + | info->bytes[(i * 4) + 3]); + + info->all_words_same + = (info->words[0] == info->words[1] + && info->words[0] == info->words[1] + && info->words[0] == info->words[2] + && info->words[0] == info->words[3]); + + /* Pack double words together & determine if all of the double words are the + same. */ + for (size_t i = 0; i < VECTOR_128BIT_DOUBLE_WORDS; i++) + { + unsigned HOST_WIDE_INT d_word = 0; + for (size_t j = 0; j < 8; j++) + d_word = (d_word << 8) | info->bytes[(i * 8) + j]; + + info->double_words[i] = d_word; + } + + info->all_double_words_same + = (info->double_words[0] == info->double_words[1]); + + return true; +} + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-rs6000.h" -- cgit v1.1 From 8ccd8b12ded1782f4273fd1f381b7d554df61a12 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 15 Dec 2021 00:57:44 -0500 Subject: Add LXVKQ support. This patch adds support to generate the LXVKQ instruction to load specific IEEE-128 floating point constants. Compared to the last time I submitted this patch, I modified it so that it uses the bit pattern of the vector to see if it can generate the LXVKQ instruction. This means on a little endian Power system, the following code will generate a LXVKQ 34,16 instruction: vector long long foo (void) { return (vector long long) { 0x0000000000000000, 0x8000000000000000 }; } because that vector pattern is the same bit pattern as -0.0F128. 2021-12-14 Michael Meissner gcc/ * config/rs6000/constraints.md (eQ): New constraint. * config/rs6000/predicates.md (easy_fp_constant): Add support for generating the LXVKQ instruction. (easy_vector_constant_ieee128): New predicate. (easy_vector_constant): Add support for generating the LXVKQ instruction. * config/rs6000/rs6000-protos.h (constant_generates_lxvkq): New declaration. * config/rs6000/rs6000.c (output_vec_const_move): Add support for generating LXVKQ. (constant_generates_lxvkq): New function. * config/rs6000/rs6000.opt (-mieee128-constant): New debug option. * config/rs6000/vsx.md (vsx_mov_64bit): Add support for generating LXVKQ. (vsx_mov_32bit): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eQ constraint. gcc/testsuite/ * gcc.target/powerpc/float128-constant.c: New test. --- gcc/config/rs6000/constraints.md | 6 + gcc/config/rs6000/predicates.md | 34 +++++ gcc/config/rs6000/rs6000-protos.h | 1 + gcc/config/rs6000/rs6000.c | 62 ++++++++ gcc/config/rs6000/rs6000.opt | 4 + gcc/config/rs6000/vsx.md | 14 ++ gcc/doc/md.texi | 4 + .../gcc.target/powerpc/float128-constant.c | 160 +++++++++++++++++++++ 8 files changed, 285 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-constant.c (limited to 'gcc') diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index c8cff1a..e72132b 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -213,6 +213,12 @@ "A signed 34-bit integer constant if prefixed instructions are supported." (match_operand 0 "cint34_operand")) +;; A TF/KF scalar constant or a vector constant that can load certain IEEE +;; 128-bit constants into vector registers using LXVKQ. +(define_constraint "eQ" + "An IEEE 128-bit constant that can be loaded into VSX registers." + (match_operand 0 "easy_vector_constant_ieee128")) + ;; Floating-point constraints. These two are defined so that insn ;; length attributes can be calculated exactly. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index f216ffd..be72167 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -601,6 +601,14 @@ if (TARGET_VSX && op == CONST0_RTX (mode)) return 1; + /* Constants that can be generated with ISA 3.1 instructions are easy. */ + vec_const_128bit_type vsx_const; + if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const)) + { + if (constant_generates_lxvkq (&vsx_const) != 0) + return true; + } + /* Otherwise consider floating point constants hard, so that the constant gets pushed to memory during the early RTL phases. This has the advantage that double precision constants that can be @@ -609,6 +617,23 @@ return 0; }) +;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded +;; via the LXVKQ instruction. + +(define_predicate "easy_vector_constant_ieee128" + (match_code "const_vector,const_double") +{ + vec_const_128bit_type vsx_const; + + /* Can we generate the LXVKQ instruction? */ + if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10 + || !TARGET_VSX) + return false; + + return (vec_const_128bit_to_bytes (op, mode, &vsx_const) + && constant_generates_lxvkq (&vsx_const) != 0); +}) + ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction. @@ -653,6 +678,15 @@ if (zero_constant (op, mode) || all_ones_constant (op, mode)) return true; + /* Constants that can be generated with ISA 3.1 instructions are + easy. */ + vec_const_128bit_type vsx_const; + if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const)) + { + if (constant_generates_lxvkq (&vsx_const) != 0) + return true; + } + if (TARGET_P9_VECTOR && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 81345d8..4a2e7fa 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -250,6 +250,7 @@ typedef struct { extern bool vec_const_128bit_to_bytes (rtx, machine_mode, vec_const_128bit_type *); +extern unsigned constant_generates_lxvkq (vec_const_128bit_type *); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 819314d..0bc3844 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6700,6 +6700,17 @@ output_vec_const_move (rtx *operands) gcc_unreachable (); } + vec_const_128bit_type vsx_const; + if (TARGET_POWER10 && vec_const_128bit_to_bytes (vec, mode, &vsx_const)) + { + unsigned imm = constant_generates_lxvkq (&vsx_const); + if (imm) + { + operands[2] = GEN_INT (imm); + return "lxvkq %x0,%2"; + } + } + if (TARGET_P9_VECTOR && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value)) { @@ -28587,6 +28598,57 @@ vec_const_128bit_to_bytes (rtx op, return true; } +/* Determine if an IEEE 128-bit constant can be loaded with LXVKQ. Return zero + if the LXVKQ instruction cannot be used. Otherwise return the immediate + value to be used with the LXVKQ instruction. */ + +unsigned +constant_generates_lxvkq (vec_const_128bit_type *vsx_const) +{ + /* Is the instruction supported with power10 code generation, IEEE 128-bit + floating point hardware and VSX registers are available. */ + if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10 + || !TARGET_VSX) + return 0; + + /* All of the constants that are generated by LXVKQ have the bottom 3 words + that are 0. */ + if (vsx_const->words[1] != 0 + || vsx_const->words[2] != 0 + || vsx_const->words[3] != 0) + return 0; + + /* See if we have a match for the first word. */ + switch (vsx_const->words[0]) + { + case 0x3FFF0000U: return 1; /* IEEE 128-bit +1.0. */ + case 0x40000000U: return 2; /* IEEE 128-bit +2.0. */ + case 0x40008000U: return 3; /* IEEE 128-bit +3.0. */ + case 0x40010000U: return 4; /* IEEE 128-bit +4.0. */ + case 0x40014000U: return 5; /* IEEE 128-bit +5.0. */ + case 0x40018000U: return 6; /* IEEE 128-bit +6.0. */ + case 0x4001C000U: return 7; /* IEEE 128-bit +7.0. */ + case 0x7FFF0000U: return 8; /* IEEE 128-bit +Infinity. */ + case 0x7FFF8000U: return 9; /* IEEE 128-bit quiet NaN. */ + case 0x80000000U: return 16; /* IEEE 128-bit -0.0. */ + case 0xBFFF0000U: return 17; /* IEEE 128-bit -1.0. */ + case 0xC0000000U: return 18; /* IEEE 128-bit -2.0. */ + case 0xC0008000U: return 19; /* IEEE 128-bit -3.0. */ + case 0xC0010000U: return 20; /* IEEE 128-bit -4.0. */ + case 0xC0014000U: return 21; /* IEEE 128-bit -5.0. */ + case 0xC0018000U: return 22; /* IEEE 128-bit -6.0. */ + case 0xC001C000U: return 23; /* IEEE 128-bit -7.0. */ + case 0xFFFF0000U: return 24; /* IEEE 128-bit -Infinity. */ + + /* anything else cannot be loaded. */ + default: + break; + } + + return 0; +} + + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-rs6000.h" diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 9d7878f..b7433ec 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -640,6 +640,10 @@ mprivileged Target Var(rs6000_privileged) Init(0) Generate code that will run in privileged state. +mieee128-constant +Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save +Generate (do not generate) code that uses the LXVKQ instruction. + -param=rs6000-density-pct-threshold= Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param When costing for loop vectorization, we probably need to penalize the loop body diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 83d6c7b..de04840 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1192,16 +1192,19 @@ ;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR) ;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW +;; LXVKQ ;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, r, we, ?wQ, ?&r, ??r, ??Y, , wa, v, + wa, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, we, r, r, wQ, Y, r, r, wE, jwM, + eQ, ?jwM, W, , v, wZ"))] "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) @@ -1213,35 +1216,43 @@ [(set_attr "type" "vecstore, vecload, vecsimple, mtvsr, mfvsr, load, store, load, store, *, vecsimple, vecsimple, + vecperm, vecsimple, *, *, vecstore, vecload") (set_attr "num_insns" "*, *, *, 2, *, 2, 2, 2, 2, 2, *, *, + *, *, 5, 2, *, *") (set_attr "max_prefixed_insns" "*, *, *, *, *, 2, 2, 2, 2, 2, *, *, + *, *, *, *, *, *") (set_attr "length" "*, *, *, 8, *, 8, 8, 8, 8, 8, *, *, + *, *, 20, 8, *, *") (set_attr "isa" ", , , *, *, *, *, *, *, *, p9v, *, + p10, , *, *, *, *")]) ;; VSX store VSX load VSX move GPR load GPR store GPR move +;; LXVKQ ;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const ;; LVX (VMX) STVX (VMX) (define_insn "*vsx_mov_32bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, ??r, ??Y, , + wa, wa, v, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, Y, r, r, + eQ, wE, jwM, ?jwM, W, , v, wZ"))] @@ -1253,14 +1264,17 @@ } [(set_attr "type" "vecstore, vecload, vecsimple, load, store, *, + vecperm, vecsimple, vecsimple, vecsimple, *, *, vecstore, vecload") (set_attr "length" "*, *, *, 16, 16, 16, + *, *, *, *, 20, 16, *, *") (set_attr "isa" ", , , *, *, *, + p10, p9v, *, , *, *, *, *")]) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 8fd0f8d..69cb7e3 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3336,6 +3336,10 @@ A constant whose negation is a signed 16-bit constant. @item eI A signed 34-bit integer constant if prefixed instructions are supported. +@item eQ +An IEEE 128-bit constant that can be loaded into a VSX register with +the @code{lxvkq} instruction. + @ifset INTERNALS @item G A floating point constant that can be loaded into a register with one diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c new file mode 100644 index 0000000..e3286a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-constant.c @@ -0,0 +1,160 @@ +/* { dg-require-effective-target ppc_float128_hw } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit + constants. */ + +_Float128 +return_0 (void) +{ + return 0.0f128; /* XXSPLTIB 34,0. */ +} + +_Float128 +return_1 (void) +{ + return 1.0f128; /* LXVKQ 34,1. */ +} + +_Float128 +return_2 (void) +{ + return 2.0f128; /* LXVKQ 34,2. */ +} + +_Float128 +return_3 (void) +{ + return 3.0f128; /* LXVKQ 34,3. */ +} + +_Float128 +return_4 (void) +{ + return 4.0f128; /* LXVKQ 34,4. */ +} + +_Float128 +return_5 (void) +{ + return 5.0f128; /* LXVKQ 34,5. */ +} + +_Float128 +return_6 (void) +{ + return 6.0f128; /* LXVKQ 34,6. */ +} + +_Float128 +return_7 (void) +{ + return 7.0f128; /* LXVKQ 34,7. */ +} + +_Float128 +return_m0 (void) +{ + return -0.0f128; /* LXVKQ 34,16. */ +} + +_Float128 +return_m1 (void) +{ + return -1.0f128; /* LXVKQ 34,17. */ +} + +_Float128 +return_m2 (void) +{ + return -2.0f128; /* LXVKQ 34,18. */ +} + +_Float128 +return_m3 (void) +{ + return -3.0f128; /* LXVKQ 34,19. */ +} + +_Float128 +return_m4 (void) +{ + return -4.0f128; /* LXVKQ 34,20. */ +} + +_Float128 +return_m5 (void) +{ + return -5.0f128; /* LXVKQ 34,21. */ +} + +_Float128 +return_m6 (void) +{ + return -6.0f128; /* LXVKQ 34,22. */ +} + +_Float128 +return_m7 (void) +{ + return -7.0f128; /* LXVKQ 34,23. */ +} + +_Float128 +return_inf (void) +{ + return __builtin_inff128 (); /* LXVKQ 34,8. */ +} + +_Float128 +return_minf (void) +{ + return - __builtin_inff128 (); /* LXVKQ 34,24. */ +} + +_Float128 +return_nan (void) +{ + return __builtin_nanf128 (""); /* LXVKQ 34,9. */ +} + +/* Note, the following NaNs should not generate a LXVKQ instruction. */ +_Float128 +return_mnan (void) +{ + return - __builtin_nanf128 (""); /* PLXV 34,... */ +} + +_Float128 +return_nan2 (void) +{ + return __builtin_nanf128 ("1"); /* PLXV 34,... */ +} + +_Float128 +return_nans (void) +{ + return __builtin_nansf128 (""); /* PLXV 34,... */ +} + +vector long long +return_longlong_neg_0 (void) +{ + /* This vector is the same pattern as -0.0F128. */ +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#define FIRST 0x8000000000000000 +#define SECOND 0x0000000000000000 + +#else +#define FIRST 0x0000000000000000 +#define SECOND 0x8000000000000000 +#endif + + return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */ +} + +/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */ +/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */ + -- cgit v1.1 From d730aa8a9ff26a36c3b480402c1507f3d2e48db9 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 15 Dec 2021 01:37:08 -0500 Subject: Generate XXSPLTIW on power10. This patch adds support to automatically generate the ISA 3.1 XXSPLTIW instruction for V8HImode, V4SImode, and V4SFmode vectors. It does this by adding support for vector constants that can be used, and adding a VEC_DUPLICATE pattern to generate the actual XXSPLTIW instruction. Add the eP constraint to recognize constants that can be loaded into vector registers with a single prefixed instruction such as xxspltiw and xxspltidp. I added 4 new tests to test loading up V16QI, V8HI, V4SI, and V4SF vector constants. 2021-12-14 Michael Meissner gcc/ * config/rs6000/constraints.md (eP): Update comment. * config/rs6000/predicates.md (easy_fp_constant): Add support for generating XXSPLTIW. (vsx_prefixed_constant): New predicate. (easy_vector_constant): Add support for generating XXSPLTIW. * config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New declaration. (constant_generates_xxspltiw): Likewise. * config/rs6000/rs6000.c (xxspltib_constant_p): Generate XXSPLTIW if possible instead of XXSPLTIB and sign extending the constant. (output_vec_const_move): Add support for XXSPLTIW. (prefixed_xxsplti_p): New function. (constant_generates_xxspltiw): New function. * config/rs6000/rs6000.md (prefixed attribute): Add support to mark XXSPLTI* instructions as being prefixed. * config/rs6000/rs6000.opt (-msplat-word-constant): New debug switch. * config/rs6000/vsx.md (vsx_mov_64bit): Add support for generating XXSPLTIW or XXSPLTIDP. (vsx_mov_32bit): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eP constraint. gcc/testsuite/ * gcc.target/powerpc/vec-splat-constant-v16qi.c: New test. * gcc.target/powerpc/vec-splat-constant-v4sf.c: New test. * gcc.target/powerpc/vec-splat-constant-v4si.c: New test. * gcc.target/powerpc/vec-splat-constant-v8hi.c: New test. * gcc.target/powerpc/vec-splati-runnable.c: Update insn count. --- gcc/config/rs6000/constraints.md | 6 ++ gcc/config/rs6000/predicates.md | 46 +++++++++++- gcc/config/rs6000/rs6000-protos.h | 2 + gcc/config/rs6000/rs6000.c | 83 ++++++++++++++++++++++ gcc/config/rs6000/rs6000.md | 5 ++ gcc/config/rs6000/rs6000.opt | 4 ++ gcc/config/rs6000/vsx.md | 28 ++++---- gcc/doc/md.texi | 4 ++ .../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 +++++++ .../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 +++++++++++++++++ .../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 +++++++++++++ .../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 ++++++++++++++++ .../gcc.target/powerpc/vec-splati-runnable.c | 4 +- 13 files changed, 371 insertions(+), 18 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c (limited to 'gcc') diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index e72132b..a4b0583 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -213,6 +213,12 @@ "A signed 34-bit integer constant if prefixed instructions are supported." (match_operand 0 "cint34_operand")) +;; A SF/DF scalar constant or a vector constant that can be loaded into vector +;; registers with one prefixed instruction such as XXSPLTIDP or XXSPLTIW. +(define_constraint "eP" + "A constant that can be loaded into a VSX register with one prefixed insn." + (match_operand 0 "vsx_prefixed_constant")) + ;; A TF/KF scalar constant or a vector constant that can load certain IEEE ;; 128-bit constants into vector registers using LXVKQ. (define_constraint "eQ" diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index be72167..886ace7 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -605,7 +605,10 @@ vec_const_128bit_type vsx_const; if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const)) { - if (constant_generates_lxvkq (&vsx_const) != 0) + if (constant_generates_lxvkq (&vsx_const)) + return true; + + if (constant_generates_xxspltiw (&vsx_const)) return true; } @@ -617,6 +620,42 @@ return 0; }) +;; Return 1 if the operand is a 64-bit floating point scalar constant or a +;; vector constant that can be loaded to a VSX register with one prefixed +;; instruction, such as XXSPLTIDP or XXSPLTIW. +;; +;; In addition regular constants, we also recognize constants formed with the +;; VEC_DUPLICATE insn from scalar constants. +;; +;; We don't handle scalar integer constants here because the assumption is the +;; normal integer constants will be loaded into GPR registers. For the +;; constants that need to be loaded into vector registers, the instructions +;; don't work well with TImode variables assigned a constant. This is because +;; the 64-bit scalar constants are splatted into both halves of the register. + +(define_predicate "vsx_prefixed_constant" + (match_code "const_double,const_vector,vec_duplicate") +{ + /* If we can generate the constant with a few Altivec instructions, don't + generate a prefixed instruction. */ + if (CONST_VECTOR_P (op) && easy_altivec_constant (op, mode)) + return false; + + /* Do we have prefixed instructions and are VSX registers available? Is the + constant recognized? */ + if (!TARGET_PREFIXED || !TARGET_VSX) + return false; + + vec_const_128bit_type vsx_const; + if (!vec_const_128bit_to_bytes (op, mode, &vsx_const)) + return false; + + if (constant_generates_xxspltiw (&vsx_const)) + return true; + + return false; +}) + ;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded ;; via the LXVKQ instruction. @@ -683,7 +722,10 @@ vec_const_128bit_type vsx_const; if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const)) { - if (constant_generates_lxvkq (&vsx_const) != 0) + if (constant_generates_lxvkq (&vsx_const)) + return true; + + if (constant_generates_xxspltiw (&vsx_const)) return true; } diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 4a2e7fa..74699ab 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -198,6 +198,7 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode); extern bool prefixed_load_p (rtx_insn *); extern bool prefixed_store_p (rtx_insn *); extern bool prefixed_paddi_p (rtx_insn *); +extern bool prefixed_xxsplti_p (rtx_insn *); extern void rs6000_asm_output_opcode (FILE *); extern void output_pcrel_opt_reloc (rtx); extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int); @@ -251,6 +252,7 @@ typedef struct { extern bool vec_const_128bit_to_bytes (rtx, machine_mode, vec_const_128bit_type *); extern unsigned constant_generates_lxvkq (vec_const_128bit_type *); +extern unsigned constant_generates_xxspltiw (vec_const_128bit_type *); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 0bc3844..5c1b620 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6649,6 +6649,13 @@ xxspltib_constant_p (rtx op, else if (IN_RANGE (value, -1, 0)) *num_insns_ptr = 1; + /* Do not generate XXSPLTIB and a sign extend operation if we can generate a + single XXSPLTIW or XXSPLTIDP instruction. */ + else if (vsx_prefixed_constant (op, mode)) + return false; + + /* Return XXSPLITB followed by a sign extend operation to convert the + constant to V8HImode or V4SImode. */ else *num_insns_ptr = 2; @@ -6709,6 +6716,13 @@ output_vec_const_move (rtx *operands) operands[2] = GEN_INT (imm); return "lxvkq %x0,%2"; } + + imm = constant_generates_xxspltiw (&vsx_const); + if (imm) + { + operands[2] = GEN_INT (imm); + return "xxspltiw %x0,%2"; + } } if (TARGET_P9_VECTOR @@ -26480,6 +26494,41 @@ prefixed_paddi_p (rtx_insn *insn) return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL); } +/* Whether an instruction is a prefixed XXSPLTI* instruction. This is called + from the prefixed attribute processing. */ + +bool +prefixed_xxsplti_p (rtx_insn *insn) +{ + rtx set = single_set (insn); + if (!set) + return false; + + rtx dest = SET_DEST (set); + rtx src = SET_SRC (set); + machine_mode mode = GET_MODE (dest); + + if (!REG_P (dest) && !SUBREG_P (dest)) + return false; + + if (GET_CODE (src) == UNSPEC) + { + int unspec = XINT (src, 1); + return (unspec == UNSPEC_XXSPLTIW + || unspec == UNSPEC_XXSPLTIDP + || unspec == UNSPEC_XXSPLTI32DX); + } + + vec_const_128bit_type vsx_const; + if (vec_const_128bit_to_bytes (src, mode, &vsx_const)) + { + if (constant_generates_xxspltiw (&vsx_const)) + return true; + } + + return false; +} + /* Whether the next instruction needs a 'p' prefix issued before the instruction is printed out. */ static bool prepend_p_to_next_insn; @@ -28648,6 +28697,40 @@ constant_generates_lxvkq (vec_const_128bit_type *vsx_const) return 0; } +/* Determine if a vector constant can be loaded with XXSPLTIW. Return zero if + the XXSPLTIW instruction cannot be used. Otherwise return the immediate + value to be used with the XXSPLTIW instruction. */ + +unsigned +constant_generates_xxspltiw (vec_const_128bit_type *vsx_const) +{ + if (!TARGET_SPLAT_WORD_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX) + return 0; + + if (!vsx_const->all_words_same) + return 0; + + /* If we can use XXSPLTIB, don't generate XXSPLTIW. */ + if (vsx_const->all_bytes_same) + return 0; + + /* See if we can use VSPLTISH or VSPLTISW. */ + if (vsx_const->all_half_words_same) + { + unsigned short h_word = vsx_const->half_words[0]; + short sign_h_word = ((h_word & 0xffff) ^ 0x8000) - 0x8000; + if (EASY_VECTOR_15 (sign_h_word)) + return 0; + } + + unsigned int word = vsx_const->words[0]; + int sign_word = ((word & 0xffffffff) ^ 0x80000000) - 0x80000000; + if (EASY_VECTOR_15 (sign_word)) + return 0; + + return vsx_const->words[0]; +} + struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 6bec2bd..3a7bcd2 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -315,6 +315,11 @@ (eq_attr "type" "integer,add") (if_then_else (match_test "prefixed_paddi_p (insn)") (const_string "yes") + (const_string "no")) + + (eq_attr "type" "vecperm") + (if_then_else (match_test "prefixed_xxsplti_p (insn)") + (const_string "yes") (const_string "no"))] (const_string "no"))) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index b7433ec..ec7b106 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -640,6 +640,10 @@ mprivileged Target Var(rs6000_privileged) Init(0) Generate code that will run in privileged state. +msplat-word-constant +Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save +Generate (do not generate) code that uses the XXSPLTIW instruction. + mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index de04840..802db0d 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1192,19 +1192,19 @@ ;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR) ;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW -;; LXVKQ +;; LXVKQ XXSPLTI* ;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, r, we, ?wQ, ?&r, ??r, ??Y, , wa, v, - wa, + wa, wa, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, we, r, r, wQ, Y, r, r, wE, jwM, - eQ, + eQ, eP, ?jwM, W, , v, wZ"))] "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) @@ -1216,43 +1216,43 @@ [(set_attr "type" "vecstore, vecload, vecsimple, mtvsr, mfvsr, load, store, load, store, *, vecsimple, vecsimple, - vecperm, + vecperm, vecperm, vecsimple, *, *, vecstore, vecload") (set_attr "num_insns" "*, *, *, 2, *, 2, 2, 2, 2, 2, *, *, - *, + *, *, *, 5, 2, *, *") (set_attr "max_prefixed_insns" "*, *, *, *, *, 2, 2, 2, 2, 2, *, *, - *, + *, *, *, *, *, *, *") (set_attr "length" "*, *, *, 8, *, 8, 8, 8, 8, 8, *, *, - *, + *, *, *, 20, 8, *, *") (set_attr "isa" ", , , *, *, *, *, *, *, *, p9v, *, - p10, + p10, p10, , *, *, *, *")]) ;; VSX store VSX load VSX move GPR load GPR store GPR move -;; LXVKQ +;; LXVKQ XXSPLTI* ;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const ;; LVX (VMX) STVX (VMX) (define_insn "*vsx_mov_32bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, ??r, ??Y, , - wa, + wa, wa, wa, v, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, Y, r, r, - eQ, + eQ, eP, wE, jwM, ?jwM, W, , v, wZ"))] @@ -1264,17 +1264,17 @@ } [(set_attr "type" "vecstore, vecload, vecsimple, load, store, *, - vecperm, + vecperm, vecperm, vecsimple, vecsimple, vecsimple, *, *, vecstore, vecload") (set_attr "length" "*, *, *, 16, 16, 16, - *, + *, *, *, *, *, 20, 16, *, *") (set_attr "isa" ", , , *, *, *, - p10, + p10, p10, p9v, *, , *, *, *, *")]) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 69cb7e3..9ec051e 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3336,6 +3336,10 @@ A constant whose negation is a signed 16-bit constant. @item eI A signed 34-bit integer constant if prefixed instructions are supported. +@item eP +A scalar floating point constant or a vector constant that can be +loaded to a VSX register with one prefixed instruction. + @item eQ An IEEE 128-bit constant that can be loaded into a VSX register with the @code{lxvkq} instruction. diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c new file mode 100644 index 0000000..27764dd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +#include + +/* Test whether XXSPLTIW is generated for V16HI vector constants where the + first 4 elements are the same as the next 4 elements, etc. */ + +vector unsigned char +v16qi_const_1 (void) +{ + return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */ +} + +vector unsigned char +v16qi_const_2 (void) +{ + return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4, + 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */ +} + +/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */ +/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ +/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c new file mode 100644 index 0000000..1f0475c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c @@ -0,0 +1,67 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +#include + +/* Test whether XXSPLTIW is generated for V4SF vector constants. */ + +vector float +v4sf_const_1 (void) +{ + return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */ +} + +vector float +v4sf_const_nan (void) +{ + return (vector float) { __builtin_nanf (""), + __builtin_nanf (""), + __builtin_nanf (""), + __builtin_nanf ("") }; /* XXSPLTIW. */ +} + +vector float +v4sf_const_inf (void) +{ + return (vector float) { __builtin_inff (), + __builtin_inff (), + __builtin_inff (), + __builtin_inff () }; /* XXSPLTIW. */ +} + +vector float +v4sf_const_m0 (void) +{ + return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */ +} + +vector float +v4sf_splats_1 (void) +{ + return vec_splats (1.0f); /* XXSPLTIW. */ +} + +vector float +v4sf_splats_nan (void) +{ + return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */ +} + +vector float +v4sf_splats_inf (void) +{ + return vec_splats (__builtin_inff ()); /* XXSPLTIW. */ +} + +vector float +v8hi_splats_m0 (void) +{ + return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */ +} + +/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ +/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c new file mode 100644 index 0000000..02d0c6d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +#include + +/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure + the power9 support (XXSPLTIB/VEXTSB2W) is not done. */ + +vector int +v4si_const_1 (void) +{ + return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */ +} + +vector int +v4si_const_126 (void) +{ + return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */ +} + +vector int +v4si_const_1023 (void) +{ + return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ +} + +vector int +v4si_splats_1 (void) +{ + return vec_splats (1); /* VSLTPISW. */ +} + +vector int +v4si_splats_126 (void) +{ + return vec_splats (126); /* XXSPLTIW. */ +} + +vector int +v8hi_splats_1023 (void) +{ + return vec_splats (1023); /* XXSPLTIW. */ +} + +/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ +/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */ +/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ +/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c new file mode 100644 index 0000000..59418d3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +#include + +/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure + the power9 support (XXSPLTIB/VUPKLSB) is not done. */ + +vector short +v8hi_const_1 (void) +{ + return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */ +} + +vector short +v8hi_const_126 (void) +{ + return (vector short) { 126, 126, 126, 126, + 126, 126, 126, 126 }; /* XXSPLTIW. */ +} + +vector short +v8hi_const_1023 (void) +{ + return (vector short) { 1023, 1023, 1023, 1023, + 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ +} + +vector short +v8hi_splats_1 (void) +{ + return vec_splats ((short)1); /* VSLTPISH. */ +} + +vector short +v8hi_splats_126 (void) +{ + return vec_splats ((short)126); /* XXSPLTIW. */ +} + +vector short +v8hi_splats_1023 (void) +{ + return vec_splats ((short)1023); /* XXSPLTIW. */ +} + +/* Test that we can optimiza V8HI where all of the even elements are the same + and all of the odd elements are the same. */ +vector short +v8hi_const_1023_1000 (void) +{ + return (vector short) { 1023, 1000, 1023, 1000, + 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */ +} + +/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */ +/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ +/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */ +/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ +/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c index a135279..6c01666 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c @@ -149,8 +149,8 @@ main (int argc, char *argv []) return 0; } -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */ /* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */ -- cgit v1.1 From 8d443ac032ecf0d8275bb0f6838ed7c9aee4e7a5 Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 15 Dec 2021 02:02:24 -0500 Subject: Generate XXSPLTIDP for vectors on power10. This patch implements XXSPLTIDP support for all vector constants. The XXSPLTIDP instruction is given a 32-bit immediate that is converted to a vector of two DFmode constants. The immediate is in SFmode format, so only constants that fit as SFmode values can be loaded with XXSPLTIDP. The constraint (eP) added in the previous patch for XXSPLTIW is also used for XXSPLTIDP. DImode scalar constants are not handled. This is due to the majority of DImode constants will be in the GPR registers. With vector registers, you have the problem that XXSPLTIDP splats the double word into both elements of the vector. However, if TImode is loaded with an integer constant, it wants a full 128-bit constant. SFmode and DFmode scalar constants are not handled in this patch. The support for for those constants will be in the next patch. I have added a temporary switch (-msplat-float-constant) to control whether or not the XXSPLTIDP instruction is generated. I added 2 new tests to test loading up V2DI and V2DF vector constants. 2021-12-14 Michael Meissner gcc/ * config/rs6000/predicates.md (easy_fp_constant): Add support for generating XXSPLTIDP. (vsx_prefixed_constant): Likewise. (easy_vector_constant): Likewise. * config/rs6000/rs6000-protos.h (constant_generates_xxspltidp): New declaration. * config/rs6000/rs6000.c (output_vec_const_move): Add support for generating XXSPLTIDP. (prefixed_xxsplti_p): Likewise. (constant_generates_xxspltidp): New function. * config/rs6000/rs6000.opt (-msplat-float-constant): New debug option. gcc/testsuite/ * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn regex for power10. * gcc.target/powerpc/vec-splat-constant-v2df.c: New test. * gcc.target/powerpc/vec-splat-constant-v2di.c: New test. --- gcc/config/rs6000/predicates.md | 9 ++ gcc/config/rs6000/rs6000-protos.h | 1 + gcc/config/rs6000/rs6000.c | 108 +++++++++++++++++++++ gcc/config/rs6000/rs6000.opt | 4 + .../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +- .../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ++++++++++++ .../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ++++++++++ 7 files changed, 241 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c (limited to 'gcc') diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 886ace7..0d9f6a6 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -610,6 +610,9 @@ if (constant_generates_xxspltiw (&vsx_const)) return true; + + if (constant_generates_xxspltidp (&vsx_const)) + return true; } /* Otherwise consider floating point constants hard, so that the @@ -653,6 +656,9 @@ if (constant_generates_xxspltiw (&vsx_const)) return true; + if (constant_generates_xxspltidp (&vsx_const)) + return true; + return false; }) @@ -727,6 +733,9 @@ if (constant_generates_xxspltiw (&vsx_const)) return true; + + if (constant_generates_xxspltidp (&vsx_const)) + return true; } if (TARGET_P9_VECTOR diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 74699ab..3e03d37 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -253,6 +253,7 @@ extern bool vec_const_128bit_to_bytes (rtx, machine_mode, vec_const_128bit_type *); extern unsigned constant_generates_lxvkq (vec_const_128bit_type *); extern unsigned constant_generates_xxspltiw (vec_const_128bit_type *); +extern unsigned constant_generates_xxspltidp (vec_const_128bit_type *); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 5c1b620..e82a47f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6723,6 +6723,13 @@ output_vec_const_move (rtx *operands) operands[2] = GEN_INT (imm); return "xxspltiw %x0,%2"; } + + imm = constant_generates_xxspltidp (&vsx_const); + if (imm) + { + operands[2] = GEN_INT (imm); + return "xxspltidp %x0,%2"; + } } if (TARGET_P9_VECTOR @@ -26524,6 +26531,9 @@ prefixed_xxsplti_p (rtx_insn *insn) { if (constant_generates_xxspltiw (&vsx_const)) return true; + + if (constant_generates_xxspltidp (&vsx_const)) + return true; } return false; @@ -28731,6 +28741,104 @@ constant_generates_xxspltiw (vec_const_128bit_type *vsx_const) return vsx_const->words[0]; } +/* Determine if a vector constant can be loaded with XXSPLTIDP. Return zero if + the XXSPLTIDP instruction cannot be used. Otherwise return the immediate + value to be used with the XXSPLTIDP instruction. */ + +unsigned +constant_generates_xxspltidp (vec_const_128bit_type *vsx_const) +{ + if (!TARGET_SPLAT_FLOAT_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX) + return 0; + + /* Reject if the two 64-bit segments are not the same. */ + if (!vsx_const->all_double_words_same) + return 0; + + /* If the bytes, half words, or words are all the same, don't use XXSPLTIDP. + Use a simpler instruction (XXSPLTIB, VSPLTISB, VSPLTISH, or VSPLTISW). */ + if (vsx_const->all_bytes_same + || vsx_const->all_half_words_same + || vsx_const->all_words_same) + return 0; + + unsigned HOST_WIDE_INT value = vsx_const->double_words[0]; + + /* Avoid values that look like DFmode NaN's, except for the normal NaN bit + pattern and the signalling NaN bit pattern. Recognize infinity and + negative infinity. */ + + /* Bit representation of DFmode normal quiet NaN. */ +#define RS6000_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000) + + /* Bit representation of DFmode normal signaling NaN. */ +#define RS6000_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000) + + /* Bit representation of DFmode positive infinity. */ +#define RS6000_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000) + + /* Bit representation of DFmode negative infinity. */ +#define RS6000_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000) + + if (value != RS6000_CONST_DF_NAN + && value != RS6000_CONST_DF_NANS + && value != RS6000_CONST_DF_INF + && value != RS6000_CONST_DF_NEG_INF) + { + /* The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for + the exponent, and 52 bits for the mantissa (not counting the hidden + bit used for normal numbers). NaN values have the exponent set to all + 1 bits, and the mantissa non-zero (mantissa == 0 is infinity). */ + + int df_exponent = (value >> 52) & 0x7ff; + unsigned HOST_WIDE_INT + df_mantissa = value & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U); + + if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */ + return 0; + + /* Avoid values that are DFmode subnormal values. Subnormal numbers have + the exponent all 0 bits, and the mantissa non-zero. If the value is + subnormal, then the hidden bit in the mantissa is not set. */ + if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */ + return 0; + } + + /* Change the representation to DFmode constant. */ + long df_words[2] = { vsx_const->words[0], vsx_const->words[1] }; + + /* real_from_target takes the target words in target order. */ + if (!BYTES_BIG_ENDIAN) + std::swap (df_words[0], df_words[1]); + + REAL_VALUE_TYPE rv_type; + real_from_target (&rv_type, df_words, DFmode); + + const REAL_VALUE_TYPE *rv = &rv_type; + + /* Validate that the number can be stored as a SFmode value. */ + if (!exact_real_truncate (SFmode, rv)) + return 0; + + /* Validate that the number is not a SFmode subnormal value (exponent is 0, + mantissa field is non-zero) which is undefined for the XXSPLTIDP + instruction. */ + long sf_value; + real_to_target (&sf_value, rv, SFmode); + + /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent, + and 23 bits for the mantissa. Subnormal numbers have the exponent all + 0 bits, and the mantissa non-zero. */ + long sf_exponent = (sf_value >> 23) & 0xFF; + long sf_mantissa = sf_value & 0x7FFFFF; + + if (sf_exponent == 0 && sf_mantissa != 0) + return 0; + + /* Return the immediate to be used. */ + return sf_value; +} + struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index ec7b106..c1d661d 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -644,6 +644,10 @@ msplat-word-constant Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save Generate (do not generate) code that uses the XXSPLTIW instruction. +msplat-float-constant +Target Var(TARGET_SPLAT_FLOAT_CONSTANT) Init(1) Save +Generate (do not generate) code that uses the XXSPLTIDP instruction. + mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c index bd1502b..dcb30e1 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c @@ -24,11 +24,12 @@ vector signed long long splats4(void) return (vector signed long long) vec_sl(mzero, mzero); } -/* Codegen will consist of splat and shift instructions for most types. - If folding is enabled, the vec_sl tests using vector long long type will - generate a lvx instead of a vspltisw+vsld pair. */ +/* Codegen will consist of splat and shift instructions for most types. If + folding is enabled, the vec_sl tests using vector long long type will + generate a lvx instead of a vspltisw+vsld pair. On power10, it will + generate a xxspltidp instruction instead of the lvx. */ /* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */ /* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */ -/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c new file mode 100644 index 0000000..82ffc86 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +#include + +/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP + instruction. */ + +vector double +v2df_double_0 (void) +{ + return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */ +} + +vector double +v2df_double_1 (void) +{ + return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */ +} + +#ifndef __FAST_MATH__ +vector double +v2df_double_m0 (void) +{ + return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */ +} + +vector double +v2df_double_nan (void) +{ + return (vector double) { __builtin_nan (""), + __builtin_nan ("") }; /* XXSPLTIDP. */ +} + +vector double +v2df_double_inf (void) +{ + return (vector double) { __builtin_inf (), + __builtin_inf () }; /* XXSPLTIDP. */ +} + +vector double +v2df_double_m_inf (void) +{ + return (vector double) { - __builtin_inf (), + - __builtin_inf () }; /* XXSPLTIDP. */ +} +#endif + +vector double +v2df_double_pi (void) +{ + return (vector double) { M_PI, M_PI }; /* PLVX. */ +} + +vector double +v2df_double_denorm (void) +{ + return (vector double) { (double)0x1p-149f, + (double)0x1p-149f }; /* PLVX. */ +} + +/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c new file mode 100644 index 0000000..4d44f94 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +/* Test generating V2DImode constants that have the same bit pattern as + V2DFmode constants that can be loaded with the XXSPLTIDP instruction with + the ISA 3.1 (power10). */ + +vector long long +vector_0 (void) +{ + /* XXSPLTIB or XXLXOR. */ + return (vector long long) { 0LL, 0LL }; +} + +vector long long +vector_1 (void) +{ + /* XXSPLTIB and VEXTSB2D. */ + return (vector long long) { 1LL, 1LL }; +} + +/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated + with XXSPLTISDP. */ +vector long long +vector_float_neg_0 (void) +{ + /* XXSPLTIDP. */ + return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL }; +} + +/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with + XXSPLTISDP. */ +vector long long +vector_float_1_0 (void) +{ + /* XXSPLTIDP. */ + return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL }; +} + +/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated + with XXSPLTIDP. */ +vector long long +scalar_pi (void) +{ + /* PLXV. */ + return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL }; +} + +/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */ -- cgit v1.1 From 575ad7700f3d29d9310a778818c0c7a360f4eb1a Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Wed, 15 Dec 2021 02:30:20 -0500 Subject: Generate XXSPLTIDP for scalars on power10. This patch implements XXSPLTIDP support for SF, and DF scalar constants. The previous patch added support for vector constants. This patch adds the support for SFmode and DFmode scalar constants. I added 2 new tests to test loading up SF and DF scalar constants. 2021-12-15 Michael Meissner gcc/ * config/rs6000/rs6000.md (UNSPEC_XXSPLTIDP_CONST): New unspec. (UNSPEC_XXSPLTIW_CONST): New unspec. (movsf_hardfloat): Add support for generating XXSPLTIDP. (mov_hardfloat32): Likewise. (mov_hardfloat64): Likewise. (xxspltidp__internal): New insns. (xxspltiw__internal): New insns. (splitters for SF/DFmode): Add new splitters for XXSPLTIDP. gcc/testsuite/ * gcc.target/powerpc/vec-splat-constant-df.c: New test. * gcc.target/powerpc/vec-splat-constant-sf.c: New test. --- gcc/config/rs6000/rs6000.md | 97 ++++++++++++++++++---- .../gcc.target/powerpc/vec-splat-constant-df.c | 60 +++++++++++++ .../gcc.target/powerpc/vec-splat-constant-sf.c | 60 +++++++++++++ 3 files changed, 199 insertions(+), 18 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c (limited to 'gcc') diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3a7bcd2..4122acb 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -156,6 +156,8 @@ UNSPEC_PEXTD UNSPEC_HASHST UNSPEC_HASHCHK + UNSPEC_XXSPLTIDP_CONST + UNSPEC_XXSPLTIW_CONST ]) ;; @@ -7764,17 +7766,17 @@ ;; ;; LWZ LFS LXSSP LXSSPX STFS STXSSP ;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP -;; MR MT MF NOP +;; MR MT MF NOP XXSPLTIDP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa, m, wY, Z, m, wa, !r, f, wa, - !r, *c*l, !r, *h") + !r, *c*l, !r, *h, wa") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa, r, j, j, f, wa, - r, r, *h, 0"))] + r, r, *h, 0, eP"))] "(register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT @@ -7796,15 +7798,16 @@ mr %0,%1 mt%0 %1 mf%1 %0 - nop" + nop + #" [(set_attr "type" "load, fpload, fpload, fpload, fpstore, fpstore, fpstore, store, veclogical, integer, fpsimple, fpsimple, - *, mtjmpr, mfjmpr, *") + *, mtjmpr, mfjmpr, *, vecperm") (set_attr "isa" "*, *, p9v, p8v, *, p9v, p8v, *, *, *, *, *, - *, *, *, *")]) + *, *, *, *, p10")]) ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ ;; FMR MR MT%0 MF%1 NOP @@ -8064,18 +8067,18 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSD STXSD XXLOR XXLXOR GPR<-0 -;; LWZ STW MR +;; LWZ STW MR XXSPLTIDP (define_insn "*mov_hardfloat32" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, - Y, r, !r") + Y, r, !r, wa") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , - r, Y, r"))] + r, Y, r, eP"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -8092,20 +8095,21 @@ # # # + # #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, two, - store, load, two") + store, load, two, vecperm") (set_attr "size" "64") (set_attr "length" "*, *, *, *, *, *, *, *, *, 8, - 8, 8, 8") + 8, 8, 8, *") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, - *, *, *")]) + *, *, *, p10")]) ;; STW LWZ MR G-const H-const F-const @@ -8132,19 +8136,19 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSDX STXSDX XXLOR XXLXOR LI 0 ;; STD LD MR MT{CTR,LR} MF{CTR,LR} -;; NOP MFVSRD MTVSRD +;; NOP MFVSRD MTVSRD XXSPLTIDP (define_insn "*mov_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, YZ, r, !r, *c*l, !r, - *h, r, ") + *h, r, , wa") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , r, YZ, r, r, *h, - 0, , r"))] + 0, , r, eP"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -8166,18 +8170,19 @@ mf%1 %0 nop mfvsrd %0,%x1 - mtvsrd %x0,%1" + mtvsrd %x0,%1 + #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, integer, store, load, *, mtjmpr, mfjmpr, - *, mfvsr, mtvsr") + *, mfvsr, mtvsr, vecperm") (set_attr "size" "64") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, *, *, *, *, *, - *, p8v, p8v")]) + *, p8v, p8v, p10")]) ;; STD LD MR MT MF G-const ;; H-const F-const Special @@ -8211,6 +8216,62 @@ (set_attr "length" "*, *, *, *, *, 8, 12, 16, *")]) + +;; Split the VSX prefixed instruction to support SFmode and DFmode scalar +;; constants that look like DFmode floating point values where both elements +;; are the same. The constant has to be expressible as a SFmode constant that +;; is not a SFmode denormal value. +;; +;; We don't need splitters for the 128-bit types, since the function +;; rs6000_output_move_128bit handles the generation of XXSPLTIDP. +(define_insn "xxspltidp__internal" + [(set (match_operand:SFDF 0 "register_operand" "=wa") + (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")] + UNSPEC_XXSPLTIDP_CONST))] + "TARGET_POWER10" + "xxspltidp %x0,%1" + [(set_attr "type" "vecperm") + (set_attr "prefixed" "yes")]) + +(define_insn "xxspltiw__internal" + [(set (match_operand:SFDF 0 "register_operand" "=wa") + (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")] + UNSPEC_XXSPLTIW_CONST))] + "TARGET_POWER10" + "xxspltiw %x0,%1" + [(set_attr "type" "vecperm") + (set_attr "prefixed" "yes")]) + +(define_split + [(set (match_operand:SFDF 0 "vsx_register_operand") + (match_operand:SFDF 1 "vsx_prefixed_constant"))] + "TARGET_POWER10" + [(pc)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + vec_const_128bit_type vsx_const; + + if (!vec_const_128bit_to_bytes (src, mode, &vsx_const)) + gcc_unreachable (); + + unsigned imm = constant_generates_xxspltidp (&vsx_const); + if (imm) + { + emit_insn (gen_xxspltidp__internal (dest, GEN_INT (imm))); + DONE; + } + + imm = constant_generates_xxspltiw (&vsx_const); + if (imm) + { + emit_insn (gen_xxspltiw__internal (dest, GEN_INT (imm))); + DONE; + } + + else + gcc_unreachable (); +}) (define_expand "mov" [(set (match_operand:FMOVE128 0 "general_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c new file mode 100644 index 0000000..8f6e176 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c @@ -0,0 +1,60 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +#include + +/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP + instruction. */ + +double +scalar_double_0 (void) +{ + return 0.0; /* XXSPLTIB or XXLXOR. */ +} + +double +scalar_double_1 (void) +{ + return 1.0; /* XXSPLTIDP. */ +} + +#ifndef __FAST_MATH__ +double +scalar_double_m0 (void) +{ + return -0.0; /* XXSPLTIDP. */ +} + +double +scalar_double_nan (void) +{ + return __builtin_nan (""); /* XXSPLTIDP. */ +} + +double +scalar_double_inf (void) +{ + return __builtin_inf (); /* XXSPLTIDP. */ +} + +double +scalar_double_m_inf (void) /* XXSPLTIDP. */ +{ + return - __builtin_inf (); +} +#endif + +double +scalar_double_pi (void) +{ + return M_PI; /* PLFD. */ +} + +double +scalar_double_denorm (void) +{ + return 0x1p-149f; /* PLFD. */ +} + +/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c new file mode 100644 index 0000000..72504bd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c @@ -0,0 +1,60 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +#include + +/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP + instruction. */ + +float +scalar_float_0 (void) +{ + return 0.0f; /* XXSPLTIB or XXLXOR. */ +} + +float +scalar_float_1 (void) +{ + return 1.0f; /* XXSPLTIDP. */ +} + +#ifndef __FAST_MATH__ +float +scalar_float_m0 (void) +{ + return -0.0f; /* XXSPLTIDP. */ +} + +float +scalar_float_nan (void) +{ + return __builtin_nanf (""); /* XXSPLTIDP. */ +} + +float +scalar_float_inf (void) +{ + return __builtin_inff (); /* XXSPLTIDP. */ +} + +float +scalar_float_m_inf (void) /* XXSPLTIDP. */ +{ + return - __builtin_inff (); +} +#endif + +float +scalar_float_pi (void) +{ + return (float)M_PI; /* XXSPLTIDP. */ +} + +float +scalar_float_denorm (void) +{ + return 0x1p-149f; /* PLFS. */ +} + +/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */ -- cgit v1.1 From 8f9fea41a767f6ad8cf3d521031048a2491f98b1 Mon Sep 17 00:00:00 2001 From: Haochen Jiang Date: Wed, 1 Dec 2021 16:48:28 +0800 Subject: Add combine splitter to transform vashr/vlshr/vashl_optab to ashr/lshr/ashl_optab for const vector duplicate operand. gcc/ChangeLog: PR target/101796 * config/i386/predicates.md (const_vector_operand): Add new predicate. * config/i386/sse.md(3): Add new define_split below. gcc/testsuite/ChangeLog: PR target/101796 * gcc.target/i386/pr101796-1.c: New test. --- gcc/config/i386/predicates.md | 13 +++++++++++++ gcc/config/i386/sse.md | 14 ++++++++++++++ gcc/testsuite/gcc.target/i386/pr101796-1.c | 20 ++++++++++++++++++++ 3 files changed, 47 insertions(+) create mode 100755 gcc/testsuite/gcc.target/i386/pr101796-1.c (limited to 'gcc') diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 4ccbe11..770e2f0 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1844,6 +1844,19 @@ return true; }) +;; Return true if OP is a const vector with duplicate value. +(define_predicate "const_vector_duplicate_operand" + (match_code "const_vector") +{ + rtx elt = XVECEXP (op, 0, 0); + int i, nelt = XVECLEN (op, 0); + + for (i = 1; i < nelt; ++i) + if (!rtx_equal_p (elt, XVECEXP (op, 0, i))) + return false; + return true; +}) + ;; Return true if OP is a parallel for a vbroadcast permute. (define_predicate "avx_vbroadcast_operand" (and (match_code "parallel") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 929eef5..768a93e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15287,6 +15287,20 @@ (const_string "0"))) (set_attr "mode" "")]) +;; PR target/101796: Transfrom movl+vpbranchcastw+vpsravw to vpsraw +;; when COUNT is immediate. +(define_split + [(set (match_operand:VI248_AVX512BW 0 "register_operand") + (any_shift:VI248_AVX512BW + (match_operand:VI248_AVX512BW 1 "nonimmediate_operand") + (match_operand:VI248_AVX512BW 2 "const_vector_duplicate_operand")))] + "TARGET_AVX512F && GET_MODE_UNIT_BITSIZE (mode) + > INTVAL (XVECEXP (operands[2], 0, 0))" + [(set (match_dup 0) + (any_shift:VI248_AVX512BW + (match_dup 1) + (match_dup 3)))] + "operands[3] = XVECEXP (operands[2], 0, 0);") (define_expand "vec_shl_" [(set (match_dup 3) diff --git a/gcc/testsuite/gcc.target/i386/pr101796-1.c b/gcc/testsuite/gcc.target/i386/pr101796-1.c new file mode 100755 index 0000000..3a5f50d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101796-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512bw" } */ +/* { dg-final {scan-assembler-times "vpsrlw\[ \\t\]" 1 } } */ +/* { dg-final {scan-assembler-times "vpsllw\[ \\t\]" 1 } } */ +/* { dg-final {scan-assembler-times "vpsraw\[ \\t\]" 1 } } */ +/* { dg-final {scan-assembler-not "vpbroadcastw\[ \\t\]" } } */ +/* { dg-final {scan-assembler-not "vpsrlvw\[ \\t\]" } } */ +/* { dg-final {scan-assembler-not "vpsllvw\[ \\t\]" } } */ +/* { dg-final {scan-assembler-not "vpsravw\[ \\t\]" } } */ +#include + +volatile __m512i a, b; + +void +foo() +{ + b = _mm512_srlv_epi16 (a, _mm512_set1_epi16 (3)); + b = _mm512_sllv_epi16 (a, _mm512_set1_epi16 (4)); + b = _mm512_srav_epi16 (a, _mm512_set1_epi16 (5)); +} -- cgit v1.1 From c0e34451ae582c901a2df08498b36f68ae401f0a Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 15 Dec 2021 10:27:08 +0100 Subject: openmp: Avoid calling operand_equal_p on OMP_CLAUSEs [PR103704] On OMP_CLAUSEs we reuse TREE_TYPE as CP_OMP_CLAUSE_INFO in the C++ FE. This confuses the hashing code that operand_equal_p does when checking. There is really no reason to compare OMP_CLAUSEs against expressions like captured this, they will never compare equal. 2021-12-15 Jakub Jelinek PR c++/103704 * semantics.c (finish_omp_target_clauses_r): For OMP_CLAUSEs just walk subtrees. * g++.dg/gomp/pr103704.C: New test. --- gcc/cp/semantics.c | 3 +++ gcc/testsuite/g++.dg/gomp/pr103704.C | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 gcc/testsuite/g++.dg/gomp/pr103704.C (limited to 'gcc') diff --git a/gcc/cp/semantics.c b/gcc/cp/semantics.c index d8b20ff..356fb83 100644 --- a/gcc/cp/semantics.c +++ b/gcc/cp/semantics.c @@ -9325,6 +9325,9 @@ finish_omp_target_clauses_r (tree *tp, int *walk_subtrees, void *ptr) return NULL_TREE; } + if (TREE_CODE (t) == OMP_CLAUSE) + return NULL_TREE; + if (current_object) { tree this_expr = TREE_OPERAND (current_object, 0); diff --git a/gcc/testsuite/g++.dg/gomp/pr103704.C b/gcc/testsuite/g++.dg/gomp/pr103704.C new file mode 100644 index 0000000..68767c4 --- /dev/null +++ b/gcc/testsuite/g++.dg/gomp/pr103704.C @@ -0,0 +1,19 @@ +// PR c++/103704 +// { dg-do compile } + +struct S { int a; }; + +template +struct U : public T { + T a; + U () + { +#pragma omp target +#pragma omp teams +#pragma omp distribute private(a) + for (int k = 0; k < 1; ++k) + ; + } +}; + +struct V : public U { V () : U () {} }; -- cgit v1.1 From 127c7178d5ec502d95862fd823537cbca1a0cb99 Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Mon, 13 Dec 2021 15:34:30 +0100 Subject: i386: Fix emissing of __builtin_cpu_supports. PR target/103661 gcc/ChangeLog: * config/i386/i386-builtins.c (fold_builtin_cpu): Compare to 0 as API expects that non-zero values are returned (do that it mask == 31). For "avx512vbmi2" argument, we return now 1 << 31, which is a negative integer value. --- gcc/config/i386/i386-builtins.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/config/i386/i386-builtins.c b/gcc/config/i386/i386-builtins.c index 0fb14b5..4b30cf7 100644 --- a/gcc/config/i386/i386-builtins.c +++ b/gcc/config/i386/i386-builtins.c @@ -2353,7 +2353,11 @@ fold_builtin_cpu (tree fndecl, tree *args) /* Return __cpu_model.__cpu_features[0] & field_val */ final = build2 (BIT_AND_EXPR, unsigned_type_node, array_elt, build_int_cstu (unsigned_type_node, field_val)); - return build1 (CONVERT_EXPR, integer_type_node, final); + if (isa_names_table[i].feature == (INT_TYPE_SIZE - 1)) + return build2 (NE_EXPR, integer_type_node, final, + build_int_cst (unsigned_type_node, 0)); + else + return build1 (CONVERT_EXPR, integer_type_node, final); } gcc_unreachable (); } -- cgit v1.1 From e75a0a03588977c8c758091f9b50d456a5f67227 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 15 Dec 2021 10:41:02 +0100 Subject: dwarf2cfi: Improve cfa_reg comparisons [PR103619] On Tue, Dec 14, 2021 at 10:32:21AM -0700, Jeff Law wrote: > I think the attached testcase should trigger on c6x with -mbig-endian -O2 -g Thanks. Finally I see what's going on. c6x doesn't really need the CFA with span > 1 (and I bet neither does armbe), the only reason why dwf_cfa_reg is called is that the code in 13 cases just tries to compare the CFA against dwf_cfa_reg (some_reg). And that dwf_cfa_reg on some reg that usually isn't a CFA reg results in targetm.dwarf_register_span hook call, which on targets like c6x or armeb and others for some registers creates a PARALLEL with various REGs in it, then the loop with the assertion and finally operator== which just notes that the reg is different and fails. This seems compile time memory and time inefficient. The following so far untested patch instead adds an extra operator== and != for comparison of cfa_reg with rtx, which has the most common case where it is a different register number done early without actually invoking dwf_cfa_reg. This means the assertion in dwf_cfa_reg can stay as is (at least until some big endian target needs to have hard frame pointer or stack pointer with span > 1 as well). I've removed a different assertion there because it is redundant - dwf_regno already has exactly that assertion in it too. And I've included those 2 tweaks to avoid creating a REG in GC memory when we can use {stack,hard_frame}_pointer_rtx which is already initialized to the same REG we need by init_emit_regs. On Tue, Dec 14, 2021 at 03:05:37PM -0700, Jeff Law wrote: > So if someone is unfamiliar with the underlying issues here and needs to > twiddle dwarf2cfi, how are they supposed to know if they should compare > directly or use dwf_cfa_reg? Comparison without dwf_cfa_reg should be used whenever possible, because for registers which are never CFA related that won't call targetm.dwarf_register_span uselessly. The only comparisons with dwf_cfa_reg I've kept are the: regno = dwf_cfa_reg (XEXP (XEXP (dest, 0), 0)); if (cur_cfa->reg == regno) offset -= cur_cfa->offset; else if (cur_trace->cfa_store.reg == regno) offset -= cur_trace->cfa_store.offset; else { gcc_assert (cur_trace->cfa_temp.reg == regno); offset -= cur_trace->cfa_temp.offset; } and struct cfa_reg regno = dwf_cfa_reg (XEXP (dest, 0)); if (cur_cfa->reg == regno) offset = -cur_cfa->offset; else if (cur_trace->cfa_store.reg == regno) offset = -cur_trace->cfa_store.offset; else { gcc_assert (cur_trace->cfa_temp.reg == regno); offset = -cur_trace->cfa_temp.offset; } and there are 2 reasons for it: 1) there is an assertion, which guarantees it must compare equal to one of those 3 cfa related struct cfa_reg structs, so it must be some CFA related register (so, right now, targetm.dwarf_register_span shouldn't return non-NULL in those on anything but gcn) 2) it is compared 3 times in a row, so for the GCN case doing if (cur_cfa->reg == XEXP (XEXP (dest, 0), 0)) offset -= cur_cfa->offset; else if (cur_trace->cfa_store.reg == XEXP (XEXP (dest, 0), 0)) offset -= cur_trace->cfa_store.offset; else { gcc_assert (cur_trace->cfa_temp.reg == XEXP (XEXP (dest, 0), 0)); offset -= cur_trace->cfa_temp.offset; } could actually create more GC allocated garbage than the way it is written now. But doing it that way would work fine. I think for most of the comparisons even comparing with dwf_cfa_reg would work but be less compile time/memory efficient (e.g. those assertions that it is equal to some CFA related cfa_reg or in any spots where only the CFA related regs may appear in the frame related patterns). I'm aware just of a single spot where comparison with dwf_cfa_reg doesn't work (when the assert is in dwf_cfa_reg), that is the spot that was ICEing on your testcase, where we save arbitrary call saved register: if (REG_P (src) && REGNO (src) != STACK_POINTER_REGNUM && REGNO (src) != HARD_FRAME_POINTER_REGNUM && cur_cfa->reg == src) 2021-12-15 Jakub Jelinek PR debug/103619 * dwarf2cfi.c (dwf_cfa_reg): Remove gcc_assert. (operator==, operator!=): New overloaded operators. (dwarf2out_frame_debug_adjust_cfa, dwarf2out_frame_debug_cfa_offset, dwarf2out_frame_debug_expr): Compare vars with cfa_reg type directly with REG rtxes rather than with dwf_cfa_reg results on those REGs. (create_cie_data): Use stack_pointer_rtx instead of gen_rtx_REG (Pmode, STACK_POINTER_REGNUM). (execute_dwarf2_frame): Use hard_frame_pointer_rtx instead of gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM). --- gcc/dwarf2cfi.c | 58 ++++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 37 insertions(+), 21 deletions(-) (limited to 'gcc') diff --git a/gcc/dwarf2cfi.c b/gcc/dwarf2cfi.c index 9dd1dfe..b8aa805 100644 --- a/gcc/dwarf2cfi.c +++ b/gcc/dwarf2cfi.c @@ -1113,8 +1113,6 @@ dwf_cfa_reg (rtx reg) { struct cfa_reg result; - gcc_assert (REGNO (reg) < FIRST_PSEUDO_REGISTER); - result.reg = dwf_regno (reg); result.span = 1; result.span_width = 0; @@ -1144,6 +1142,28 @@ dwf_cfa_reg (rtx reg) return result; } +/* More efficient comparisons that don't call targetm.dwarf_register_span + unnecessarily. These cfa_reg vs. rtx comparisons should be done at + least for call-saved REGs that might not be CFA related (like stack + pointer, hard frame pointer or DRAP registers are), in other cases it is + just a compile time and memory optimization. */ + +static bool +operator== (cfa_reg &cfa, rtx reg) +{ + unsigned int regno = dwf_regno (reg); + if (cfa.reg != regno) + return false; + struct cfa_reg other = dwf_cfa_reg (reg); + return cfa == other; +} + +static inline bool +operator!= (cfa_reg &cfa, rtx reg) +{ + return !(cfa == reg); +} + /* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */ static bool @@ -1313,7 +1333,7 @@ dwarf2out_frame_debug_adjust_cfa (rtx pat) switch (GET_CODE (src)) { case PLUS: - gcc_assert (dwf_cfa_reg (XEXP (src, 0)) == cur_cfa->reg); + gcc_assert (cur_cfa->reg == XEXP (src, 0)); cur_cfa->offset -= rtx_to_poly_int64 (XEXP (src, 1)); break; @@ -1346,11 +1366,11 @@ dwarf2out_frame_debug_cfa_offset (rtx set) switch (GET_CODE (addr)) { case REG: - gcc_assert (dwf_cfa_reg (addr) == cur_cfa->reg); + gcc_assert (cur_cfa->reg == addr); offset = -cur_cfa->offset; break; case PLUS: - gcc_assert (dwf_cfa_reg (XEXP (addr, 0)) == cur_cfa->reg); + gcc_assert (cur_cfa->reg == XEXP (addr, 0)); offset = rtx_to_poly_int64 (XEXP (addr, 1)) - cur_cfa->offset; break; default: @@ -1797,7 +1817,7 @@ dwarf2out_frame_debug_expr (rtx expr) { /* Setting FP from SP. */ case REG: - if (cur_cfa->reg == dwf_cfa_reg (src)) + if (cur_cfa->reg == src) { /* Rule 1 */ /* Update the CFA rule wrt SP or FP. Make sure src is @@ -1828,7 +1848,7 @@ dwarf2out_frame_debug_expr (rtx expr) { gcc_assert (REGNO (dest) == HARD_FRAME_POINTER_REGNUM && fde->drap_reg != INVALID_REGNUM - && cur_cfa->reg != dwf_cfa_reg (src) + && cur_cfa->reg != src && fde->rule18); fde->rule18 = 0; /* The save of hard frame pointer has been deferred @@ -1852,8 +1872,7 @@ dwarf2out_frame_debug_expr (rtx expr) /* Adjusting SP. */ if (REG_P (XEXP (src, 1))) { - gcc_assert (dwf_cfa_reg (XEXP (src, 1)) - == cur_trace->cfa_temp.reg); + gcc_assert (cur_trace->cfa_temp.reg == XEXP (src, 1)); offset = cur_trace->cfa_temp.offset; } else if (!poly_int_rtx_p (XEXP (src, 1), &offset)) @@ -1886,7 +1905,7 @@ dwarf2out_frame_debug_expr (rtx expr) gcc_assert (frame_pointer_needed); gcc_assert (REG_P (XEXP (src, 0)) - && dwf_cfa_reg (XEXP (src, 0)) == cur_cfa->reg); + && cur_cfa->reg == XEXP (src, 0)); offset = rtx_to_poly_int64 (XEXP (src, 1)); if (GET_CODE (src) != MINUS) offset = -offset; @@ -1899,7 +1918,7 @@ dwarf2out_frame_debug_expr (rtx expr) /* Rule 4 */ if (REG_P (XEXP (src, 0)) - && dwf_cfa_reg (XEXP (src, 0)) == cur_cfa->reg + && cur_cfa->reg == XEXP (src, 0) && poly_int_rtx_p (XEXP (src, 1), &offset)) { /* Setting a temporary CFA register that will be copied @@ -1914,7 +1933,7 @@ dwarf2out_frame_debug_expr (rtx expr) /* Rule 5 */ else if (REG_P (XEXP (src, 0)) - && dwf_cfa_reg (XEXP (src, 0)) == cur_trace->cfa_temp.reg + && cur_trace->cfa_temp.reg == XEXP (src, 0) && XEXP (src, 1) == stack_pointer_rtx) { /* Setting a scratch register that we will use instead @@ -1945,7 +1964,7 @@ dwarf2out_frame_debug_expr (rtx expr) /* Rule 7 */ case IOR: gcc_assert (REG_P (XEXP (src, 0)) - && dwf_cfa_reg (XEXP (src, 0)) == cur_trace->cfa_temp.reg + && cur_trace->cfa_temp.reg == XEXP (src, 0) && CONST_INT_P (XEXP (src, 1))); cur_trace->cfa_temp.reg = dwf_cfa_reg (dest); @@ -1981,7 +2000,7 @@ dwarf2out_frame_debug_expr (rtx expr) dwarf2out_flush_queued_reg_saves (); gcc_assert (cur_trace->cfa_store.reg - == dwf_cfa_reg (XEXP (src, 0))); + == XEXP (src, 0)); fde->stack_realign = 1; fde->stack_realignment = INTVAL (XEXP (src, 1)); cur_trace->cfa_store.offset = 0; @@ -2109,8 +2128,7 @@ dwarf2out_frame_debug_expr (rtx expr) /* Rule 14 */ case POST_INC: - gcc_assert (cur_trace->cfa_temp.reg - == dwf_cfa_reg (XEXP (XEXP (dest, 0), 0))); + gcc_assert (cur_trace->cfa_temp.reg == XEXP (XEXP (dest, 0), 0)); offset = -cur_trace->cfa_temp.offset; cur_trace->cfa_temp.offset -= GET_MODE_SIZE (GET_MODE (dest)); break; @@ -2128,7 +2146,7 @@ dwarf2out_frame_debug_expr (rtx expr) if (REG_P (src) && REGNO (src) != STACK_POINTER_REGNUM && REGNO (src) != HARD_FRAME_POINTER_REGNUM - && dwf_cfa_reg (src) == cur_cfa->reg) + && cur_cfa->reg == src) { /* We're storing the current CFA reg into the stack. */ @@ -3210,8 +3228,7 @@ create_cie_data (void) dw_cfa_location loc; dw_trace_info cie_trace; - dw_stack_pointer_regnum = dwf_cfa_reg (gen_rtx_REG (Pmode, - STACK_POINTER_REGNUM)); + dw_stack_pointer_regnum = dwf_cfa_reg (stack_pointer_rtx); memset (&cie_trace, 0, sizeof (cie_trace)); cur_trace = &cie_trace; @@ -3270,8 +3287,7 @@ static unsigned int execute_dwarf2_frame (void) { /* Different HARD_FRAME_POINTER_REGNUM might coexist in the same file. */ - dw_frame_pointer_regnum - = dwf_cfa_reg (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM)); + dw_frame_pointer_regnum = dwf_cfa_reg (hard_frame_pointer_rtx); /* The first time we're called, compute the incoming frame state. */ if (cie_cfi_vec == NULL) -- cgit v1.1 From 6bf5d9108ae2dcb6cb883442d7bd299fd8fc15e9 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 15 Dec 2021 11:18:14 +0100 Subject: testsuite: Fix up cpp23/auto-fncast11.C testcase [PR103408] This test fails: +FAIL: g++.dg/cpp23/auto-fncast11.C -std=c++2b (test for errors, line 19) +FAIL: g++.dg/cpp23/auto-fncast11.C -std=c++2b (test for excess errors) because the regex in dg-error was missing an indefinite article. 2021-12-15 Jakub Jelinek PR c++/103408 * g++.dg/cpp23/auto-fncast11.C: Fix expected diagnostic wording. --- gcc/testsuite/g++.dg/cpp23/auto-fncast11.C | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/testsuite/g++.dg/cpp23/auto-fncast11.C b/gcc/testsuite/g++.dg/cpp23/auto-fncast11.C index 669dda1..1ae0426 100644 --- a/gcc/testsuite/g++.dg/cpp23/auto-fncast11.C +++ b/gcc/testsuite/g++.dg/cpp23/auto-fncast11.C @@ -16,4 +16,4 @@ static_assert(requires { requires auto(auto(true)); }); static_assert(!requires { requires auto(false); }); static_assert(!requires { requires auto(auto(false)); }); -auto f() requires (auto(false)); // { dg-error "constraints on non-templated" } +auto f() requires (auto(false)); // { dg-error "constraints on a non-templated" } -- cgit v1.1 From d5c965374cd688b0a8ad0334c85c971c1e9c3f44 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Wed, 15 Dec 2021 10:26:10 +0000 Subject: middle-end: REE should always check all vector usages, even if it finds a defining def. [PR103350] This and the report in PR103632 are caused by a bug in REE where it generates incorrect code. It's trying to eliminate the following zero extension (insn 54 90 102 2 (set (reg:V4SI 33 v1) (zero_extend:V4SI (reg/v:V4HI 40 v8))) (nil)) by folding it in the definition of `v8`: (insn 2 5 104 2 (set (reg/v:V4HI 40 v8) (reg:V4HI 32 v0 [156])) (nil)) which is fine, except that `v8` is also used by the extracts, e.g.: (insn 11 10 12 2 (set (reg:SI 1 x1) (zero_extend:SI (vec_select:HI (reg/v:V4HI 40 v8) (parallel [ (const_int 3) ])))) (nil)) REE replaces insn 2 by folding insn 54 and placing it at the definition site of insn 2, so before insn 11. Trying to eliminate extension: (insn 54 90 102 2 (set (reg:V4SI 33 v1) (zero_extend:V4SI (reg/v:V4HI 40 v8))) (nil)) Tentatively merged extension with definition (copy needed): (insn 2 5 104 2 (set (reg:V4SI 33 v1) (zero_extend:V4SI (reg:V4HI 32 v0))) (nil)) to produce (insn 2 5 110 2 (set (reg:V4SI 33 v1) (zero_extend:V4SI (reg:V4HI 32 v0))) (nil)) (insn 110 2 104 2 (set (reg:V4SI 40 v8) (reg:V4SI 33 v1)) (nil)) The new insn 2 using v0 directly is correct, but the insn 110 it creates is wrong, `v8` should still be V4HI. or it also needs to eliminate the zero extension from the extracts, so instead of (insn 11 10 12 2 (set (reg:SI 1 x1) (zero_extend:SI (vec_select:HI (reg/v:V4HI 40 v8) (parallel [ (const_int 3) ])))) (nil)) it should be (insn 11 10 12 2 (set (reg:SI 1 x1) (vec_select:SI (reg/v:V4SI 40 v8) (parallel [ (const_int 3) ]))) (nil)) without doing so the indices have been remapped in the extension and so we extract the wrong elements At any other optimization level but -Os ree seems to abort so this doesn't trigger: Trying to eliminate extension: (insn 54 90 101 2 (set (reg:V4SI 32 v0) (zero_extend:V4SI (reg/v:V4HI 40 v8))) (nil)) Elimination opportunities = 2 realized = 0 purely due to the ordering of instructions. REE doesn't check uses of `v8` because it assumes that with a zero extended value, you still have access to the lower bits by using the the bottom part of the register. This is true for scalar but not for vector. This would have been fine as well if REE had eliminated the zero_extend on insn 11 and the rest but it doesn't do so since REE can only handle cases where the SRC value are REG_P. It does try to do this in add_removable_extension: 1160 /* For vector mode extensions, ensure that all uses of the 1161 XEXP (src, 0) register are in insn or debug insns, as unlike 1162 integral extensions lowpart subreg of the sign/zero extended 1163 register are not equal to the original register, so we have 1164 to change all uses or none and the current code isn't able 1165 to change them all at once in one transaction. */ However this code doesn't trigger for the example because REE doesn't check the uses if the defining instruction doesn't feed into another extension.. Which is bogus. For vectors it should always check all usages. r12-2288-g8695bf78dad1a42636775843ca832a2f4dba4da3 simply exposed this as it now lowers VEC_SELECT 0 into the RTL canonical form subreg 0 which causes REE to run more often. gcc/ChangeLog: PR rtl-optimization/103350 * ree.c (add_removable_extension): Don't stop at first definition but inspect all. gcc/testsuite/ChangeLog: PR rtl-optimization/103350 * gcc.target/aarch64/pr103350-1.c: New test. * gcc.target/aarch64/pr103350-2.c: New test. --- gcc/ree.c | 35 ++++++++---------- gcc/testsuite/gcc.target/aarch64/pr103350-1.c | 48 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/pr103350-2.c | 53 +++++++++++++++++++++++++++ 3 files changed, 117 insertions(+), 19 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr103350-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr103350-2.c (limited to 'gcc') diff --git a/gcc/ree.c b/gcc/ree.c index e31ca2f..13debe8 100644 --- a/gcc/ree.c +++ b/gcc/ree.c @@ -1165,31 +1165,28 @@ add_removable_extension (const_rtx expr, rtx_insn *insn, to change them all at once in one transaction. */ else if (VECTOR_MODE_P (GET_MODE (XEXP (src, 0)))) { - if (idx == 0) - { - struct df_link *ref_chain, *ref_link; + struct df_link *ref_chain, *ref_link; - ref_chain = DF_REF_CHAIN (def->ref); - for (ref_link = ref_chain; ref_link; ref_link = ref_link->next) + ref_chain = DF_REF_CHAIN (def->ref); + for (ref_link = ref_chain; ref_link; ref_link = ref_link->next) + { + if (ref_link->ref == NULL + || DF_REF_INSN_INFO (ref_link->ref) == NULL) { - if (ref_link->ref == NULL - || DF_REF_INSN_INFO (ref_link->ref) == NULL) - { - idx = -1U; - break; - } - rtx_insn *use_insn = DF_REF_INSN (ref_link->ref); - if (use_insn != insn && !DEBUG_INSN_P (use_insn)) - { - idx = -1U; - break; - } + idx = -1U; + break; + } + rtx_insn *use_insn = DF_REF_INSN (ref_link->ref); + if (use_insn != insn && !DEBUG_INSN_P (use_insn)) + { + idx = -1U; + break; } - if (idx == -1U) - def_map[INSN_UID (DF_REF_INSN (def->ref))] = idx; } + if (idx == -1U) { + def_map[INSN_UID (DF_REF_INSN (def->ref))] = idx; if (dump_file) { fprintf (dump_file, "Cannot eliminate extension:\n"); diff --git a/gcc/testsuite/gcc.target/aarch64/pr103350-1.c b/gcc/testsuite/gcc.target/aarch64/pr103350-1.c new file mode 100644 index 0000000..61c796d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr103350-1.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-additional-options "-Os -fno-tree-ter -save-temps -fdump-rtl-ree-all -free -std=c99 -w" } */ + +typedef unsigned char u8; +typedef unsigned char __attribute__((__vector_size__ (8))) v64u8; +typedef unsigned char __attribute__((__vector_size__ (16))) v128u8; +typedef unsigned char __attribute__((__vector_size__ (32))) v256u8; +typedef unsigned short __attribute__((__vector_size__ (8))) v64u16; +typedef unsigned int __attribute__((__vector_size__ (16))) v128u32; +typedef unsigned long long u64; +typedef unsigned __int128 u128; + +v64u16 foo0_v32u16_0 = { 4, 5, 6, 7 }; +u64 foo0_u64_0 = 0x30; + +__attribute__((__noipa__)) +v64u8 foo0 (v64u16 v64u16_0, u128 u128_0) +{ + /* 03 00 05 00 03 00 02 00 ... */ + v256u8 v256u16_1 = (v256u8)__builtin_shufflevector (v64u16_0, foo0_v32u16_0, + 3, 5, 3, 2, 3, 5, 1, 0, + 3, 5, 3, 2, 2, 0, 2, 0); + /* 00 00 00 00 01 00 00 00 ... */ + v128u8 v128u8_1 = (v128u8) __builtin_convertvector (v64u16_0, v128u32); + /* 10 */ + u8 u8_1 = foo0_u64_0 % u128_0; + /* 03 00 05 00 04 00 02 00 ... */ + v128u8 v128u8_r = ((union {v256u8 a; v128u8 b[2];}) v256u16_1).b[0] + v128u8_1; + /* 00 00 01 00 02 00 03 00 */ + v64u8 v64u8_0 = (v64u8)v64u16_0; + /* 03 00 06 00 06 00 05 00 */ + v64u8 v64u8_r = ((union {v128u8 a; v64u8 b[2];}) v128u8_r).b[0] + v64u8_0; + /* 13 10 16 10 16 10 15 10 */ + return v64u8_r + u8_1; +} + +int +main (void) +{ + v64u8 x = foo0 ((v64u16){ 0, 1, 2, 3 }, 0x20); + v64u8 exp = { 0x13, 0x10, 0x16, 0x10, 0x16, 0x10, 0x15, 0x10 }; + for (unsigned i = 0; i < sizeof(x); i++) + if (x[i] != exp[i]) + __builtin_abort(); + return 0; +} + +/* { dg-final { scan-rtl-dump {because some vector uses aren't extension} ree } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/pr103350-2.c b/gcc/testsuite/gcc.target/aarch64/pr103350-2.c new file mode 100644 index 0000000..2696212 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr103350-2.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-additional-options "-O2 -save-temps -fdump-rtl-ree-all -free -std=c99 -w" } */ + +typedef unsigned char __attribute__((__vector_size__ (8))) v64u8; +typedef unsigned char __attribute__((__vector_size__ (16))) v128u8; +typedef unsigned short __attribute__((__vector_size__ (8))) v64u16; +typedef unsigned short __attribute__((__vector_size__ (64))) v512u16; +typedef unsigned int __attribute__((__vector_size__ (16))) v128u32; +typedef unsigned long long u64; +typedef unsigned long long __attribute__((__vector_size__ (8))) v64u64; +typedef unsigned long long __attribute__((__vector_size__ (16))) v128u64; +typedef unsigned __int128 u128; +typedef unsigned __int128 __attribute__((__vector_size__ (64))) v512u128; +v512u16 foo0_v512u16_0; +u64 foo0_u64_0; +u64 foo0_u16_0; + +void +foo0 (v64u16 v64u16_0, v64u64 v64u64_0, u128 u128_0, v64u8 * ret) +{ + /* { 0, 4, 0, 0 } */ + v128u32 v128u32_2 = __builtin_convertvector (v64u16_0, v128u32); + /* 0 */ + foo0_u16_0 ^= foo0_u64_0 % u128_0; + /* { 0, ... } */ + foo0_v512u16_0 *= + __builtin_shufflevector (v64u16_0, v64u16_0, 7, 7, 2, 1, 0, 0, 3, 6, 2, 3, + 1, 0, 7, 5, 6, 7, 4, 3, 2, 3, 0, 6, 1, 2, 3, 3, + 6, 7, 6, 2, 4, 3); + /* { 0, 0, 0, 0, 4, 0, ... } */ + v128u8 v128u8_r = (v128u8) ((v512u128) foo0_v512u16_0)[0] + + (v128u8) v128u32_2; + /* { 0, 0, 4, 0, 4, 0, 0, 0 } */ + v64u8 v64u8_r = (v64u8) ((v128u64) v128u8_r)[0] + + (v64u8) v64u16_0 + (v64u8) v64u64_0; + *ret = v64u8_r; +} + +int +main (void) +{ + v64u8 x, exp = (v64u8){ 0, 0, 4, 0, 4, 0, 0, 0 }; + foo0 ((v64u16){0, 4}, (v64u64){}, 5, &x); + /* + for (unsigned i = 0; i < sizeof (x); i++) + __builtin_printf ("%02x", x[i]); + */ + for (unsigned i = 0; i < sizeof (x); i++) + if (x[i] != exp[i]) __builtin_abort(); + return 0; +} + +/* { dg-final { scan-rtl-dump {because some vector uses aren't extension} ree } } */ -- cgit v1.1 From 7527ddecef4721b3f4b00e8ad22d390b457c310b Mon Sep 17 00:00:00 2001 From: Martin Liska Date: Wed, 15 Dec 2021 12:09:28 +0100 Subject: c++: Fix warning word splitting [PR103713] PR c++/103713 gcc/cp/ChangeLog: * tree.c (maybe_warn_parm_abi): Fix warning word splitting. --- gcc/cp/tree.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/cp/tree.c b/gcc/cp/tree.c index f6f7927f..284fb5f 100644 --- a/gcc/cp/tree.c +++ b/gcc/cp/tree.c @@ -4371,8 +4371,9 @@ maybe_warn_parm_abi (tree t, location_t loc) "the calling convention for %qT, which was " "accidentally changed in 8.1", t); else - w = warning_at (loc, OPT_Wabi, "%<-fabi-version=12%> (GCC 8.1) accident" - "ally changes the calling convention for %qT", t); + w = warning_at (loc, OPT_Wabi, "%<-fabi-version=12%> (GCC 8.1) " + "accidentally changes the calling convention for %qT", + t); if (w) inform (location_of (t), " declared here"); return; -- cgit v1.1 From 73c3dacef9a30d7d66918606a97c496c71289f1b Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 15 Dec 2021 12:19:00 +0000 Subject: aarch64: Don't classify vector pairs as short vectors [PR103094] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In this PR we were wrongly classifying a pair of 8-byte vectors as a 16-byte “short vector” (in the AAPCS64 sense). As the comment in the patch says, this stems from an old condition in aarch64_short_vector_p that is too loose, but that would be difficult to tighten now. We can still do the right thing for the newly-added modes though, since there are no backwards compatibility concerns there. Co-authored-by: Tamar Christina gcc/ PR target/103094 * config/aarch64/aarch64.c (aarch64_short_vector_p): Return false for structure modes, rather than ignoring the type in that case. gcc/testsuite/ PR target/103094 * gcc.target/aarch64/pr103094.c: New test. --- gcc/config/aarch64/aarch64.c | 19 +++++++++++++++++-- gcc/testsuite/gcc.target/aarch64/pr103094.c | 22 ++++++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr103094.c (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index f07330c..ff4a808 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -19299,7 +19299,21 @@ aarch64_short_vector_p (const_tree type, else if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) { - /* Rely only on the type, not the mode, when processing SVE types. */ + /* The containing "else if" is too loose: it means that we look at TYPE + if the type is a vector type (good), but that we otherwise ignore TYPE + and look only at the mode. This is wrong because the type describes + the language-level information whereas the mode is purely an internal + GCC concept. We can therefore reach here for types that are not + vectors in the AAPCS64 sense. + + We can't "fix" that for the traditional Advanced SIMD vector modes + without breaking backwards compatibility. However, there's no such + baggage for the structure modes, which were introduced in GCC 12. */ + if (aarch64_advsimd_struct_mode_p (mode)) + return false; + + /* For similar reasons, rely only on the type, not the mode, when + processing SVE types. */ if (type && aarch64_some_values_include_pst_objects_p (type)) /* Leave later code to report an error if SVE is disabled. */ gcc_assert (!TARGET_SVE || aarch64_sve_mode_p (mode)); @@ -19310,7 +19324,8 @@ aarch64_short_vector_p (const_tree type, { /* 64-bit and 128-bit vectors should only acquire an SVE mode if they are being treated as scalable AAPCS64 types. */ - gcc_assert (!aarch64_sve_mode_p (mode)); + gcc_assert (!aarch64_sve_mode_p (mode) + && !aarch64_advsimd_struct_mode_p (mode)); return true; } return false; diff --git a/gcc/testsuite/gcc.target/aarch64/pr103094.c b/gcc/testsuite/gcc.target/aarch64/pr103094.c new file mode 100644 index 0000000..beda99d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr103094.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-fdump-rtl-expand -w" } */ + +#include + +void foo (uint8x8x2_t cols_01_23, uint8x8x2_t cols_45_67, uint16_t* +outptr0) { + uint16x4x4_t cols_01_23_45_67 = { { + vreinterpret_u16_u8(cols_01_23.val[0]), + vreinterpret_u16_u8(cols_01_23.val[1]), + vreinterpret_u16_u8(cols_45_67.val[0]), + vreinterpret_u16_u8(cols_45_67.val[1]) + } }; + + vst4_lane_u16(outptr0, cols_01_23_45_67, 0); } + +/* Check that we expand to v0 and v2 from the function arguments. */ +/* { dg-final { scan-rtl-dump {\(reg:V2x8QI \d+ v0 \[ cols_01_23 +\]\)} expand } } */ +/* { dg-final { scan-rtl-dump {\(reg:V2x8QI \d+ v2 \[ cols_45_67 +\]\)} expand } } */ + -- cgit v1.1 From eede2498e61e00a176fb2908ca0317b55c084a84 Mon Sep 17 00:00:00 2001 From: Tom de Vries Date: Wed, 15 Dec 2021 14:37:58 +0100 Subject: [nvptx] Add -mptx=7.0 Add support for ptx isa version 7.0, required for the addition of -misa=sm_75 and -misa=sm_80. Tested by setting the default ptx isa version to 7.0, and doing a build and libgomp test run. gcc/ChangeLog: * config/nvptx/nvptx-opts.h (enum ptx_version): Add PTX_VERSION_7_0. * config/nvptx/nvptx.c (nvptx_file_start): Handle TARGET_PTX_7_0. * config/nvptx/nvptx.h (TARGET_PTX_7_0): New macro. * config/nvptx/nvptx.opt (ptx_version): Add 7.0. --- gcc/config/nvptx/nvptx-opts.h | 3 ++- gcc/config/nvptx/nvptx.c | 4 +++- gcc/config/nvptx/nvptx.h | 1 + gcc/config/nvptx/nvptx.opt | 3 +++ 4 files changed, 9 insertions(+), 2 deletions(-) (limited to 'gcc') diff --git a/gcc/config/nvptx/nvptx-opts.h b/gcc/config/nvptx/nvptx-opts.h index f7371dc..396fe87 100644 --- a/gcc/config/nvptx/nvptx-opts.h +++ b/gcc/config/nvptx/nvptx-opts.h @@ -30,7 +30,8 @@ enum ptx_isa enum ptx_version { PTX_VERSION_3_1, - PTX_VERSION_6_3 + PTX_VERSION_6_3, + PTX_VERSION_7_0 }; #endif diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c index 445d7ce..51eef2b 100644 --- a/gcc/config/nvptx/nvptx.c +++ b/gcc/config/nvptx/nvptx.c @@ -5404,7 +5404,9 @@ static void nvptx_file_start (void) { fputs ("// BEGIN PREAMBLE\n", asm_out_file); - if (TARGET_PTX_6_3) + if (TARGET_PTX_7_0) + fputs ("\t.version\t7.0\n", asm_out_file); + else if (TARGET_PTX_6_3) fputs ("\t.version\t6.3\n", asm_out_file); else fputs ("\t.version\t3.1\n", asm_out_file); diff --git a/gcc/config/nvptx/nvptx.h b/gcc/config/nvptx/nvptx.h index c3480cc..92fd9d3 100644 --- a/gcc/config/nvptx/nvptx.h +++ b/gcc/config/nvptx/nvptx.h @@ -90,6 +90,7 @@ #define TARGET_SM53 (ptx_isa_option >= PTX_ISA_SM53) #define TARGET_PTX_6_3 (ptx_version_option >= PTX_VERSION_6_3) +#define TARGET_PTX_7_0 (ptx_version_option >= PTX_VERSION_7_0) /* Registers. Since ptx is a virtual target, we just define a few hard registers for special purposes and leave pseudos unallocated. diff --git a/gcc/config/nvptx/nvptx.opt b/gcc/config/nvptx/nvptx.opt index 514f19d..04b45da 100644 --- a/gcc/config/nvptx/nvptx.opt +++ b/gcc/config/nvptx/nvptx.opt @@ -79,6 +79,9 @@ Enum(ptx_version) String(3.1) Value(PTX_VERSION_3_1) EnumValue Enum(ptx_version) String(6.3) Value(PTX_VERSION_6_3) +EnumValue +Enum(ptx_version) String(7.0) Value(PTX_VERSION_7_0) + mptx= Target RejectNegative ToLower Joined Enum(ptx_version) Var(ptx_version_option) Init(PTX_VERSION_3_1) Specify the version of the ptx version to use. -- cgit v1.1 From 308d688bebdd1f29cb82c7d0e09b43e57c581659 Mon Sep 17 00:00:00 2001 From: Roger Sayle Date: Sun, 12 Dec 2021 18:03:03 +0100 Subject: nvptx: Add -misa=sm_75 and -misa=sm_80 Add new target macros TARGET_SM75 and TARGET_SM80. Add support for __builtin_tanhf, HFmode exp2/tanh and also for HFmode min/max, controlled by TARGET_SM75 and TARGET_SM80 respectively. The following has been tested on nvptx-none, hosted on x86_64-pc-linux-gnu with a "make" and "make -k check" with no new failures. gcc/ChangeLog: * config/nvptx/nvptx-opts.h (ptx_isa): PTX_ISA_SM75 and PTX_ISA_SM80 ISA levels. * config/nvptx/nvptx.opt: Add sm_75 and sm_80 to -misa. * config/nvptx/nvptx.h (TARGET_SM75, TARGET_SM80): New helper macros to conditionalize functionality on target ISA. * config/nvptx/nvptx-c.c (nvptx_cpu_cpp_builtins): Add __PTX_SM__ support for the new ISA levels. * config/nvptx/nvptx.c (nvptx_file_start): Add support for TARGET_SM75 and TARGET_SM80. * config/nvptx/nvptx.md (define_c_enum "unspec"): New UNSPEC_TANH. (define_mode_iterator HSFM): New iterator for HFmode and SFmode. (exp2hf2): New define_insn controlled by TARGET_SM75. (tanh2): New define_insn controlled by TARGET_SM75. (sminhf3, smaxhf3): New define_isnns controlled by TARGET_SM80. gcc/testsuite/ChangeLog: * gcc.target/nvptx/float16-2.c: New test case. * gcc.target/nvptx/tanh-1.c: New test case. --- gcc/config/nvptx/nvptx-c.c | 6 +++++- gcc/config/nvptx/nvptx-opts.h | 4 +++- gcc/config/nvptx/nvptx.c | 6 +++++- gcc/config/nvptx/nvptx.h | 2 ++ gcc/config/nvptx/nvptx.md | 32 ++++++++++++++++++++++++++++++ gcc/config/nvptx/nvptx.opt | 6 ++++++ gcc/testsuite/gcc.target/nvptx/float16-2.c | 20 +++++++++++++++++++ gcc/testsuite/gcc.target/nvptx/tanh-1.c | 9 +++++++++ 8 files changed, 82 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/nvptx/float16-2.c create mode 100644 gcc/testsuite/gcc.target/nvptx/tanh-1.c (limited to 'gcc') diff --git a/gcc/config/nvptx/nvptx-c.c b/gcc/config/nvptx/nvptx-c.c index 7efdf70..d51ad00 100644 --- a/gcc/config/nvptx/nvptx-c.c +++ b/gcc/config/nvptx/nvptx-c.c @@ -39,7 +39,11 @@ nvptx_cpu_cpp_builtins (void) cpp_define (parse_in, "__nvptx_softstack__"); if (TARGET_UNIFORM_SIMT) cpp_define (parse_in,"__nvptx_unisimt__"); - if (TARGET_SM53) + if (TARGET_SM80) + cpp_define (parse_in, "__PTX_SM__=800"); + else if (TARGET_SM75) + cpp_define (parse_in, "__PTX_SM__=750"); + else if (TARGET_SM53) cpp_define (parse_in, "__PTX_SM__=530"); else if (TARGET_SM35) cpp_define (parse_in, "__PTX_SM__=350"); diff --git a/gcc/config/nvptx/nvptx-opts.h b/gcc/config/nvptx/nvptx-opts.h index 396fe87..7b6ecd4 100644 --- a/gcc/config/nvptx/nvptx-opts.h +++ b/gcc/config/nvptx/nvptx-opts.h @@ -24,7 +24,9 @@ enum ptx_isa { PTX_ISA_SM30, PTX_ISA_SM35, - PTX_ISA_SM53 + PTX_ISA_SM53, + PTX_ISA_SM75, + PTX_ISA_SM80 }; enum ptx_version diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c index 51eef2b..ff44d9f 100644 --- a/gcc/config/nvptx/nvptx.c +++ b/gcc/config/nvptx/nvptx.c @@ -5410,7 +5410,11 @@ nvptx_file_start (void) fputs ("\t.version\t6.3\n", asm_out_file); else fputs ("\t.version\t3.1\n", asm_out_file); - if (TARGET_SM53) + if (TARGET_SM80) + fputs ("\t.target\tsm_80\n", asm_out_file); + else if (TARGET_SM75) + fputs ("\t.target\tsm_75\n", asm_out_file); + else if (TARGET_SM53) fputs ("\t.target\tsm_53\n", asm_out_file); else if (TARGET_SM35) fputs ("\t.target\tsm_35\n", asm_out_file); diff --git a/gcc/config/nvptx/nvptx.h b/gcc/config/nvptx/nvptx.h index 92fd9d3..a25cccb 100644 --- a/gcc/config/nvptx/nvptx.h +++ b/gcc/config/nvptx/nvptx.h @@ -88,6 +88,8 @@ #define TARGET_SM35 (ptx_isa_option >= PTX_ISA_SM35) #define TARGET_SM53 (ptx_isa_option >= PTX_ISA_SM53) +#define TARGET_SM75 (ptx_isa_option >= PTX_ISA_SM75) +#define TARGET_SM80 (ptx_isa_option >= PTX_ISA_SM80) #define TARGET_PTX_6_3 (ptx_version_option >= PTX_VERSION_6_3) #define TARGET_PTX_7_0 (ptx_version_option >= PTX_VERSION_7_0) diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index da4ac8f..6599b3a 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -26,6 +26,7 @@ UNSPEC_EXP2 UNSPEC_SIN UNSPEC_COS + UNSPEC_TANH UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC @@ -196,6 +197,7 @@ (define_mode_iterator QHIM [QI HI]) (define_mode_iterator QHSIM [QI HI SI]) (define_mode_iterator SDFM [SF DF]) +(define_mode_iterator HSFM [HF SF]) (define_mode_iterator SDCM [SC DC]) (define_mode_iterator BITS [SI SF]) (define_mode_iterator BITD [DI DF]) @@ -1143,6 +1145,36 @@ "TARGET_SM53" "%.\\tmul.f16\\t%0, %1, %2;") +(define_insn "exp2hf2" + [(set (match_operand:HF 0 "nvptx_register_operand" "=R") + (unspec:HF [(match_operand:HF 1 "nvptx_register_operand" "R")] + UNSPEC_EXP2))] + "TARGET_SM75 && flag_unsafe_math_optimizations" + "%.\\tex2.approx.f16\\t%0, %1;") + +(define_insn "tanh2" + [(set (match_operand:HSFM 0 "nvptx_register_operand" "=R") + (unspec:HSFM [(match_operand:HSFM 1 "nvptx_register_operand" "R")] + UNSPEC_TANH))] + "TARGET_SM75 && flag_unsafe_math_optimizations" + "%.\\ttanh.approx%t0\\t%0, %1;") + +;; HFmode floating point arithmetic. + +(define_insn "sminhf3" + [(set (match_operand:HF 0 "nvptx_register_operand" "=R") + (smin:HF (match_operand:HF 1 "nvptx_register_operand" "R") + (match_operand:HF 2 "nvptx_register_operand" "R")))] + "TARGET_SM80" + "%.\\tmin.f16\\t%0, %1, %2;") + +(define_insn "smaxhf3" + [(set (match_operand:HF 0 "nvptx_register_operand" "=R") + (smax:HF (match_operand:HF 1 "nvptx_register_operand" "R") + (match_operand:HF 2 "nvptx_register_operand" "R")))] + "TARGET_SM80" + "%.\\tmax.f16\\t%0, %1, %2;") + ;; Conversions involving floating point (define_insn "extendsfdf2" diff --git a/gcc/config/nvptx/nvptx.opt b/gcc/config/nvptx/nvptx.opt index 04b45da..1d88ef1 100644 --- a/gcc/config/nvptx/nvptx.opt +++ b/gcc/config/nvptx/nvptx.opt @@ -64,6 +64,12 @@ Enum(ptx_isa) String(sm_35) Value(PTX_ISA_SM35) EnumValue Enum(ptx_isa) String(sm_53) Value(PTX_ISA_SM53) +EnumValue +Enum(ptx_isa) String(sm_75) Value(PTX_ISA_SM75) + +EnumValue +Enum(ptx_isa) String(sm_80) Value(PTX_ISA_SM80) + ; Default needs to be in sync with default in ASM_SPEC in nvptx.h. misa= Target RejectNegative ToLower Joined Enum(ptx_isa) Var(ptx_isa_option) Init(PTX_ISA_SM35) diff --git a/gcc/testsuite/gcc.target/nvptx/float16-2.c b/gcc/testsuite/gcc.target/nvptx/float16-2.c new file mode 100644 index 0000000..5748a9c --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/float16-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -misa=sm_80 -mptx=7.0" } */ + +_Float16 x; +_Float16 y; +_Float16 t; + +void foo() +{ + t = x < y ? x : y; +} + +void bar() +{ + t = x > y ? x : y; +} + +/* { dg-final { scan-assembler "min.f16" } } */ +/* { dg-final { scan-assembler "max.f16" } } */ + diff --git a/gcc/testsuite/gcc.target/nvptx/tanh-1.c b/gcc/testsuite/gcc.target/nvptx/tanh-1.c new file mode 100644 index 0000000..56a0e5a --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/tanh-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ffast-math -misa=sm_75 -mptx=7.0" } */ + +float foo(float x) +{ + return __builtin_tanhf(x); +} + +/* { dg-final { scan-assembler "tanh.approx.f32" } } */ -- cgit v1.1 From 3e714cc55efe5e402a7db6703dbfd70baa53dfbe Mon Sep 17 00:00:00 2001 From: Iain Sandoe Date: Wed, 8 Dec 2021 20:58:34 +0000 Subject: configure: Account CXXFLAGS in gcc-plugin.m4. We now use a C++ compiler so that we need to process CXXFLAGS as well as CFLAGS in the gcc-plugin config fragment. Signed-off-by: Iain Sandoe config/ChangeLog: * gcc-plugin.m4: Save and process CXXFLAGS. gcc/ChangeLog: * configure: Regenerate. libcc1/ChangeLog: * configure: Regenerate. --- gcc/configure | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'gcc') diff --git a/gcc/configure b/gcc/configure index de20e5d..5470987 100755 --- a/gcc/configure +++ b/gcc/configure @@ -32038,14 +32038,18 @@ fi # Check that we can build shared objects with -fPIC -shared saved_LDFLAGS="$LDFLAGS" saved_CFLAGS="$CFLAGS" + saved_CXXFLAGS="$CXXFLAGS" case "${host}" in *-*-darwin*) CFLAGS=`echo $CFLAGS | sed s/-mdynamic-no-pic//g` CFLAGS="$CFLAGS -fPIC" + CXXFLAGS=`echo $CXXFLAGS | sed s/-mdynamic-no-pic//g` + CXXFLAGS="$CXXFLAGS -fPIC" LDFLAGS="$LDFLAGS -shared -undefined dynamic_lookup" ;; *) CFLAGS="$CFLAGS -fPIC" + CXXFLAGS="$CXXFLAGS -fPIC" LDFLAGS="$LDFLAGS -fPIC -shared" ;; esac @@ -32077,6 +32081,7 @@ rm -f core conftest.err conftest.$ac_objext \ fi LDFLAGS="$saved_LDFLAGS" CFLAGS="$saved_CFLAGS" + CXXFLAGS="$saved_CXXFLAGS" # If plugin support had been requested but not available, fail. if test x"$enable_plugin" = x"no" ; then -- cgit v1.1 From 639ece7abfa3688008cb791aec4c7a1a4f76e59f Mon Sep 17 00:00:00 2001 From: Martin Sebor Date: Wed, 15 Dec 2021 08:43:02 -0700 Subject: Add new test [PR78969]. gcc/testsuite/ChangeLog: PR tree-optimization/78969 * gcc.dg/tree-ssa/builtin-snprintf-warn-6.c: New test. --- .../gcc.dg/tree-ssa/builtin-snprintf-warn-6.c | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/builtin-snprintf-warn-6.c (limited to 'gcc') diff --git a/gcc/testsuite/gcc.dg/tree-ssa/builtin-snprintf-warn-6.c b/gcc/testsuite/gcc.dg/tree-ssa/builtin-snprintf-warn-6.c new file mode 100644 index 0000000..2857e83 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/builtin-snprintf-warn-6.c @@ -0,0 +1,47 @@ +/* PR tree-optimization/78969 - bogus snprintf truncation warning due to + missing range info + { dg-do compile } + { dg-options "-O2 -Wall -Wformat-truncation=2" } */ + +typedef __SIZE_TYPE__ size_t; + +extern int snprintf (char*, size_t, const char*, ...); + + +void f (unsigned j, char *p) +{ + if (j > 999) + j = 0; + + snprintf (p, 4, "%3u", j); +} + +void g (unsigned j, char *p) +{ + if (j > 999) + return; + + snprintf (p, 4, "%3u", j); // { dg-bogus "-Wformat-truncation" } +} + + +void pr78969_c4 (char * p /* NNN\0" */) +{ + for (int idx = 0; idx < 1000; idx++) { + // guaranteed to be in [0-999] range + snprintf (p, 4, "%d", idx); // { dg-bogus "-Wformat-truncation" } + } +} + + +void sink (int, ...); + +char d[4]; + +void pr78969_c12 (unsigned i) +{ + if (i >= 1000 && i < 10000) + snprintf (d, 4, "%3d", i / 10); // { dg-bogus "-Wformat-truncation" } + else + sink (i / 10 % 10); +} -- cgit v1.1 From fd43568cc54e17c8b4a845677872c6282bc6dbb7 Mon Sep 17 00:00:00 2001 From: Iain Buclaw Date: Wed, 15 Dec 2021 19:47:02 +0100 Subject: d: Merge upstream dmd 93108bb9e, druntime 6364e010, phobos 575b67a9b. D front-end changes: - Import dmd v2.098.1-beta.1. - Default extern(C++) compatibility to C++17. Druntime changes: - Import druntime v2.098.1-beta.1. - Fix definition of stat_t on MIPS64 (PR103604) Phobos changes: - Import phobos v2.098.1-beta.1. gcc/d/ChangeLog: * d-lang.cc (d_init_options): Set default -fextern-std= to C++17. * dmd/MERGE: Merge upstream dmd 93108bb9e. * gdc.texi (Runtime Options): Document the default for -fextern-std=. libphobos/ChangeLog: PR d/103604 * configure: Regenerate. * configure.ac (libtool_VERSION): Update to 3:0:0. * libdruntime/MERGE: Merge upstream druntime 6364e010. * src/MERGE: Merge upstream phobos 575b67a9b. * testsuite/libphobos.traits/all_satisfy.d: New test. * testsuite/libphobos.traits/traits.exp: New test. --- gcc/d/d-lang.cc | 4 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/VERSION | 2 +- gcc/d/dmd/constfold.d | 20 +- gcc/d/dmd/cparse.d | 36 +- gcc/d/dmd/ctfeexpr.d | 11 +- gcc/d/dmd/dinterpret.d | 2 +- gcc/d/dmd/dsymbol.d | 55 ++- gcc/d/dmd/dsymbol.h | 1 + gcc/d/dmd/dsymbolsem.d | 7 +- gcc/d/dmd/dtemplate.d | 14 + gcc/d/dmd/expression.d | 2 +- gcc/d/dmd/expressionsem.d | 79 +++-- gcc/d/dmd/importc.d | 93 +++++- gcc/d/dmd/initsem.d | 13 +- gcc/d/dmd/lexer.d | 18 +- gcc/d/dmd/opover.d | 18 +- gcc/d/dmd/optimize.d | 55 +++ gcc/d/dmd/parse.d | 21 +- gcc/d/dmd/printast.d | 27 ++ gcc/d/dmd/semantic3.d | 12 + gcc/d/dmd/statementsem.d | 111 +++--- gcc/d/dmd/target.d | 2 +- gcc/d/dmd/target.h | 1 + gcc/d/dmd/tokens.d | 72 +--- gcc/d/dmd/tokens.h | 26 -- gcc/d/dmd/typesem.d | 33 +- gcc/d/gdc.texi | 11 +- gcc/testsuite/gdc.test/compilable/cppmangle.d | 371 +++++++++++---------- gcc/testsuite/gdc.test/compilable/cppmangle3.d | 9 +- gcc/testsuite/gdc.test/compilable/issue21203.d | 210 ++++++++++++ gcc/testsuite/gdc.test/compilable/issue21340.d | 38 +++ gcc/testsuite/gdc.test/compilable/test10028.d | 7 + gcc/testsuite/gdc.test/compilable/test20236.d | 22 ++ gcc/testsuite/gdc.test/compilable/test20860.d | 16 + gcc/testsuite/gdc.test/compilable/test21073.d | 16 + gcc/testsuite/gdc.test/compilable/test21414.d | 13 + gcc/testsuite/gdc.test/fail_compilation/b15875.d | 2 +- gcc/testsuite/gdc.test/fail_compilation/fail116.d | 2 +- .../gdc.test/fail_compilation/fail20616.d | 26 ++ .../gdc.test/fail_compilation/fail22529.d | 14 + .../gdc.test/fail_compilation/fail22570.d | 21 ++ gcc/testsuite/gdc.test/fail_compilation/ice22516.d | 21 ++ .../gdc.test/fail_compilation/test22574.d | 12 + .../gdc.test/fail_compilation/test_switch_error.d | 101 ++++++ gcc/testsuite/gdc.test/runnable/interpret.d | 23 ++ gcc/testsuite/gdc.test/runnable/test16579.d | 57 ++++ gcc/testsuite/gdc.test/runnable/test18054.d | 41 +++ gcc/testsuite/gdc.test/runnable_cxx/cppa.d | 59 +++- .../gdc.test/runnable_cxx/extra-files/cppb.cpp | 33 -- 50 files changed, 1423 insertions(+), 439 deletions(-) create mode 100644 gcc/testsuite/gdc.test/compilable/issue21203.d create mode 100644 gcc/testsuite/gdc.test/compilable/issue21340.d create mode 100644 gcc/testsuite/gdc.test/compilable/test10028.d create mode 100644 gcc/testsuite/gdc.test/compilable/test20236.d create mode 100644 gcc/testsuite/gdc.test/compilable/test20860.d create mode 100644 gcc/testsuite/gdc.test/compilable/test21073.d create mode 100644 gcc/testsuite/gdc.test/compilable/test21414.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail20616.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail22529.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail22570.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/ice22516.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/test22574.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/test_switch_error.d create mode 100644 gcc/testsuite/gdc.test/runnable/test16579.d create mode 100644 gcc/testsuite/gdc.test/runnable/test18054.d (limited to 'gcc') diff --git a/gcc/d/d-lang.cc b/gcc/d/d-lang.cc index 2c5d206..d762195 100644 --- a/gcc/d/d-lang.cc +++ b/gcc/d/d-lang.cc @@ -297,8 +297,8 @@ d_init_options (unsigned int, cl_decoded_option *decoded_options) global.params.argv0 = xstrdup (decoded_options[0].arg); global.params.errorLimit = flag_max_errors; - /* Default extern(C++) mangling to C++14. */ - global.params.cplusplus = CppStdRevisionCpp14; + /* Default extern(C++) mangling to C++17. */ + global.params.cplusplus = CppStdRevisionCpp17; /* Warnings and deprecations are disabled by default. */ global.params.useDeprecated = DIAGNOSTICinform; diff --git a/gcc/d/dmd/MERGE b/gcc/d/dmd/MERGE index 4bae16c..d7eff4f 100644 --- a/gcc/d/dmd/MERGE +++ b/gcc/d/dmd/MERGE @@ -1,4 +1,4 @@ -3982604c54e8770585985a33577fbf19b9b5c9ce +93108bb9ea6216d67fa97bb4842fb59f26f6bfc7 The first line of this file holds the git revision number of the last merge done from the dlang/dmd repository. diff --git a/gcc/d/dmd/VERSION b/gcc/d/dmd/VERSION index fa5940e..822edd4 100644 --- a/gcc/d/dmd/VERSION +++ b/gcc/d/dmd/VERSION @@ -1 +1 @@ -v2.098.0 +v2.098.1-beta.1 diff --git a/gcc/d/dmd/constfold.d b/gcc/d/dmd/constfold.d index 3ca23f2..3cc358e 100644 --- a/gcc/d/dmd/constfold.d +++ b/gcc/d/dmd/constfold.d @@ -1054,6 +1054,12 @@ UnionExp Cast(const ref Loc loc, Type type, Type to, Expression e1) emplaceExp!(UnionExp)(&ue, ex); return ue; } + if (e1.type.toBasetype.equals(type) && type.equals(to)) + { + emplaceExp!(UnionExp)(&ue, e1); + ue.exp().type = type; + return ue; + } if (e1.type.implicitConvTo(to) >= MATCH.constant || to.implicitConvTo(e1.type) >= MATCH.constant) { goto L1; @@ -1087,7 +1093,19 @@ UnionExp Cast(const ref Loc loc, Type type, Type to, Expression e1) } else if (tb.ty == Tbool) { - emplaceExp!(IntegerExp)(&ue, loc, e1.toInteger() != 0, type); + bool val = void; + const opt = e1.toBool(); + if (opt.hasValue(true)) + val = true; + else if (opt.hasValue(false)) + val = false; + else + { + cantExp(ue); + return ue; + } + + emplaceExp!(IntegerExp)(&ue, loc, val, type); } else if (type.isintegral()) { diff --git a/gcc/d/dmd/cparse.d b/gcc/d/dmd/cparse.d index dfc45e0..b1532ad 100644 --- a/gcc/d/dmd/cparse.d +++ b/gcc/d/dmd/cparse.d @@ -975,12 +975,17 @@ final class CParser(AST) : Parser!AST token.value == TOK.leftParenthesis && !isCastExpression(pt)) { - /* this might actually be a function - * call that looks like `(a)(b)` or even `(a)(b,c)` + /* (t)(...)... might be a cast expression or a function call, + * with different grammars: a cast would be cparseCastExp(), + * a function call would be cparsePostfixExp(CallExp(cparseArguments())). + * We can't know until t is known. So, parse it as a function call + * and let semantic() rewrite the AST as a CastExp if it turns out + * to be a type. */ auto ie = new AST.IdentifierExp(loc, t.isTypeIdentifier().ident); - ie.parens = true; // disambiguate it from being a declaration - return new AST.CallExp(loc, ie, cparseArguments()); + ie.parens = true; // let semantic know it might be a CastExp + AST.Expression e = new AST.CallExp(loc, ie, cparseArguments()); + return cparsePostfixOperators(e); } else { @@ -1483,9 +1488,12 @@ final class CParser(AST) : Parser!AST /* If a declarator does not follow, it is unnamed */ - if (token.value == TOK.semicolon && tspec) + if (token.value == TOK.semicolon) { nextToken(); + if (!tspec) + return; // accept empty declaration as an extension + auto tt = tspec.isTypeTag(); if (!tt || !tt.id && (tt.tok == TOK.struct_ || tt.tok == TOK.union_)) @@ -1662,7 +1670,8 @@ final class CParser(AST) : Parser!AST { // Give non-extern variables an implicit void initializer // if one has not been explicitly set. - if (!hasInitializer && !(specifier.scw & SCW.xextern)) + if (!hasInitializer && + !(specifier.scw & (SCW.xextern | SCW.xstatic | SCW.x_Thread_local) || level == LVL.global)) initializer = new AST.VoidInitializer(token.loc); s = new AST.VarDeclaration(token.loc, dt, id, initializer, specifiersToSTC(level, specifier)); } @@ -2492,7 +2501,18 @@ final class CParser(AST) : Parser!AST return t; } - t = constApply(t); + if (declarator == DTR.xparameter && + t.isTypePointer()) + { + /* Because there are instances in .h files of "const pointer to mutable", + * skip applying transitive `const` + * https://issues.dlang.org/show_bug.cgi?id=22534 + */ + auto tn = cast(AST.TypeNext)t; + tn.next = constApply(tn.next); + } + else + t = constApply(t); } //printf("result: %s\n", t.toChars()); @@ -2610,6 +2630,8 @@ final class CParser(AST) : Parser!AST Identifier id; auto t = cparseDeclarator(DTR.xparameter, tspec, id, specifier); + if (token.value == TOK.__attribute__) + cparseGnuAttributes(specifier); if (specifier.mod & MOD.xconst) t = toConst(t); auto param = new AST.Parameter(STC.parameter, t, id, null, null); diff --git a/gcc/d/dmd/ctfeexpr.d b/gcc/d/dmd/ctfeexpr.d index 9cd09ba..baacaa6 100644 --- a/gcc/d/dmd/ctfeexpr.d +++ b/gcc/d/dmd/ctfeexpr.d @@ -1574,7 +1574,7 @@ Expression ctfeIndex(UnionExp* pue, const ref Loc loc, Type type, Expression e1, assert(0); } -Expression ctfeCast(UnionExp* pue, const ref Loc loc, Type type, Type to, Expression e) +Expression ctfeCast(UnionExp* pue, const ref Loc loc, Type type, Type to, Expression e, bool explicitCast = false) { Expression paint() { @@ -1587,9 +1587,12 @@ Expression ctfeCast(UnionExp* pue, const ref Loc loc, Type type, Type to, Expres if (e.op == EXP.classReference) { // Disallow reinterpreting class casts. Do this by ensuring that - // the original class can implicitly convert to the target class - ClassDeclaration originalClass = (cast(ClassReferenceExp)e).originalClass(); - if (originalClass.type.implicitConvTo(to.mutableOf())) + // the original class can implicitly convert to the target class. + // Also do not check 'alias this' for explicit cast expressions. + auto tclass = (cast(ClassReferenceExp)e).originalClass().type.isTypeClass(); + auto match = explicitCast ? tclass.implicitConvToWithoutAliasThis(to.mutableOf()) + : tclass.implicitConvTo(to.mutableOf()); + if (match) return paint(); else { diff --git a/gcc/d/dmd/dinterpret.d b/gcc/d/dmd/dinterpret.d index 891adb3..8f20c38 100644 --- a/gcc/d/dmd/dinterpret.d +++ b/gcc/d/dmd/dinterpret.d @@ -6068,7 +6068,7 @@ public: result = pue.exp(); return; } - result = ctfeCast(pue, e.loc, e.type, e.to, e1); + result = ctfeCast(pue, e.loc, e.type, e.to, e1, true); } override void visit(AssertExp e) diff --git a/gcc/d/dmd/dsymbol.d b/gcc/d/dmd/dsymbol.d index b1d1b1d..0f75157 100644 --- a/gcc/d/dmd/dsymbol.d +++ b/gcc/d/dmd/dsymbol.d @@ -462,6 +462,21 @@ extern (C++) class Dsymbol : ASTNode return null; } + /************************************** + * Does this Dsymbol come from a C file? + * Returns: + * true if it does + */ + final bool isCsymbol() + { + if (Module m = getModule()) + { + if (m.isCFile) + return true; + } + return false; + } + /********************************** * Determine which Module a Dsymbol is in, as far as access rights go. */ @@ -1783,7 +1798,7 @@ extern (C++) final class WithScopeSymbol : ScopeDsymbol // Acts as proxy to the with class declaration Dsymbol s = null; Expression eold = null; - for (Expression e = withstate.exp; e != eold; e = resolveAliasThis(_scope, e)) + for (Expression e = withstate.exp; e && e != eold; e = resolveAliasThis(_scope, e, true)) { if (e.op == EXP.scope_) { @@ -2426,7 +2441,9 @@ Dsymbol handleSymbolRedeclarations(ref Scope sc, Dsymbol s, Dsymbol s2, ScopeDsy auto vd2 = s2.isVarDeclaration(); // existing declaration if (vd && vd2) { - // if one is `static` and the other isn't + /* if one is `static` and the other isn't, the result is undefined + * behavior, C11 6.2.2.7 + */ if ((vd.storage_class ^ vd2.storage_class) & STC.static_) return collision(); @@ -2437,7 +2454,10 @@ Dsymbol handleSymbolRedeclarations(ref Scope sc, Dsymbol s, Dsymbol s2, ScopeDsy return collision(); // can't both have initializers if (i1) - return vd; + { + vd2._init = vd._init; + vd._init = null; + } /* BUG: the types should match, which needs semantic() to be run on it * extern int x; @@ -2454,15 +2474,38 @@ Dsymbol handleSymbolRedeclarations(ref Scope sc, Dsymbol s, Dsymbol s2, ScopeDsy auto fd2 = s2.isFuncDeclaration(); // existing declaration if (fd && fd2) { - // if one is `static` and the other isn't - if ((fd.storage_class ^ fd2.storage_class) & STC.static_) + /* if one is `static` and the other isn't, the result is undefined + * behavior, C11 6.2.2.7 + * However, match what gcc allows: + * static int sun1(); int sun1() { return 0; } + * and: + * static int sun2() { return 0; } int sun2(); + * Both produce a static function. + * + * Both of these should fail: + * int sun3(); static int sun3() { return 0; } + * and: + * int sun4() { return 0; } static int sun4(); + */ + // if adding `static` + if ( fd.storage_class & STC.static_ && + !(fd2.storage_class & STC.static_)) + { return collision(); + } if (fd.fbody && fd2.fbody) return collision(); // can't both have bodies if (fd.fbody) - return fd; + { + fd2.fbody = fd.fbody; // transfer body to existing declaration + fd.fbody = null; + + auto tf = fd.type.toTypeFunction(); + auto tf2 = fd2.type.toTypeFunction(); + tf2.parameterList = tf.parameterList; // transfer parameter list. + } /* BUG: just like with VarDeclaration, the types should match, which needs semantic() to be run on it. * FuncDeclaration::semantic2() can detect this, but it relies overnext being set. diff --git a/gcc/d/dmd/dsymbol.h b/gcc/d/dmd/dsymbol.h index 02252fd..668b079 100644 --- a/gcc/d/dmd/dsymbol.h +++ b/gcc/d/dmd/dsymbol.h @@ -199,6 +199,7 @@ public: void deprecation(const char *format, ...); bool checkDeprecated(const Loc &loc, Scope *sc); Module *getModule(); + bool isCsymbol(); Module *getAccessModule(); Dsymbol *pastMixin(); Dsymbol *toParent(); diff --git a/gcc/d/dmd/dsymbolsem.d b/gcc/d/dmd/dsymbolsem.d index 0bf9a80..3a9abd2d 100644 --- a/gcc/d/dmd/dsymbolsem.d +++ b/gcc/d/dmd/dsymbolsem.d @@ -46,6 +46,7 @@ import dmd.func; import dmd.globals; import dmd.id; import dmd.identifier; +import dmd.importc; import dmd.init; import dmd.initsem; import dmd.hdrgen; @@ -891,6 +892,10 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor bool isBlit = false; d_uns64 sz; + if (sc.flags & SCOPE.Cfile && !dsym._init) + { + addDefaultCInitializer(dsym); + } if (!dsym._init && !(dsym.storage_class & (STC.static_ | STC.gshared | STC.extern_)) && fd && @@ -900,7 +905,7 @@ private extern(C++) final class DsymbolSemanticVisitor : Visitor { // Provide a default initializer - //printf("Providing default initializer for '%s'\n", toChars()); + //printf("Providing default initializer for '%s'\n", dsym.toChars()); if (sz == SIZE_INVALID && dsym.type.ty != Terror) dsym.error("size of type `%s` is invalid", dsym.type.toChars()); diff --git a/gcc/d/dmd/dtemplate.d b/gcc/d/dmd/dtemplate.d index 5dedcba..b1760dd 100644 --- a/gcc/d/dmd/dtemplate.d +++ b/gcc/d/dmd/dtemplate.d @@ -5529,6 +5529,20 @@ extern (C++) final class TemplateValueParameter : TemplateParameter override bool declareParameter(Scope* sc) { + /* + Do type semantic earlier. + + This means for certain erroneous value parameters + their "type" can be known earlier and thus a better + error message given. + + For example: + `template test(x* x) {}` + now yields "undefined identifier" rather than the opaque + "variable `x` is used as a type". + */ + if (valType) + valType = valType.typeSemantic(loc, sc); auto v = new VarDeclaration(loc, valType, ident, null); v.storage_class = STC.templateparameter; return sc.insert(v) !is null; diff --git a/gcc/d/dmd/expression.d b/gcc/d/dmd/expression.d index e6b7e30..749a50a 100644 --- a/gcc/d/dmd/expression.d +++ b/gcc/d/dmd/expression.d @@ -3985,7 +3985,7 @@ extern (C++) final class FuncExp : Expression } else { - assert(tok == TOK.function_ || tok == TOK.reserved && type.ty == Tpointer); + assert(tok == TOK.function_ || tok == TOK.reserved && type.ty == Tpointer || fd.errors); tx = tfx.pointerTo(); } //printf("\ttx = %s, to = %s\n", tx.toChars(), to.toChars()); diff --git a/gcc/d/dmd/expressionsem.d b/gcc/d/dmd/expressionsem.d index ec2bce4..48e47ce 100644 --- a/gcc/d/dmd/expressionsem.d +++ b/gcc/d/dmd/expressionsem.d @@ -316,6 +316,9 @@ Expression resolveOpDollar(Scope* sc, ArrayExp ae, IntervalExp ie, Expression* p ie.lwr = sem(ie.lwr); ie.upr = sem(ie.upr); + if (ie.lwr.isErrorExp() || ie.upr.isErrorExp()) + errors = true; + if (lengthVar != ae.lengthVar && sc.func) { // If $ was used, declare it now @@ -536,16 +539,16 @@ private Expression resolveUFCS(Scope* sc, CallExp ce) ce.e1 = ey; if (isDotOpDispatch(ey)) { - uint errors = global.startGagging(); - e = ce.syntaxCopy().expressionSemantic(sc); - if (!global.endGagging(errors)) - return e; - // even opDispatch and UFCS must have valid arguments, // so now that we've seen indication of a problem, // check them for issues. Expressions* originalArguments = Expression.arraySyntaxCopy(ce.arguments); + uint errors = global.startGagging(); + e = ce.expressionSemantic(sc); + if (!global.endGagging(errors)) + return e; + if (arrayExpressionSemantic(originalArguments, sc)) return ErrorExp.get(); @@ -2792,6 +2795,8 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor exp.error("undefined identifier `%s`, did you mean %s `%s`?", exp.ident.toChars(), s2.kind(), s2.toChars()); else if (const p = Scope.search_correct_C(exp.ident)) exp.error("undefined identifier `%s`, did you mean `%s`?", exp.ident.toChars(), p); + else if (exp.ident == Id.dollar) + exp.error("undefined identifier `$`"); else exp.error("undefined identifier `%s`", exp.ident.toChars()); @@ -4244,6 +4249,16 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor return; } } + if (sc.flags & SCOPE.Cfile) + { + /* See if need to rewrite the AST because of cast/call ambiguity + */ + if (auto e = castCallAmbiguity(exp, sc)) + { + result = expressionSemantic(e, sc); + return; + } + } if (Expression ex = resolveUFCS(sc, exp)) { @@ -4425,24 +4440,6 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor else if (exp.e1.op == EXP.type && (sc && sc.flags & SCOPE.Cfile)) { const numArgs = exp.arguments ? exp.arguments.length : 0; - if (e1org.parens && numArgs >= 1) - { - /* Ambiguous cases arise from CParser where there is not enough - * information to determine if we have a function call or a cast. - * ( type-name ) ( identifier ) ; - * ( identifier ) ( identifier ) ; - * If exp.e1 is a type-name, then this is a cast. - */ - Expression arg; - foreach (a; (*exp.arguments)[]) - { - arg = arg ? new CommaExp(a.loc, arg, a) : a; - } - auto t = exp.e1.isTypeExp().type; - auto e = new CastExp(exp.loc, arg, t); - result = e.expressionSemantic(sc); - return; - } /* Ambiguous cases arise from CParser where there is not enough * information to determine if we have a function call or declaration. @@ -6406,6 +6403,18 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor printf("DotIdExp::semantic(this = %p, '%s')\n", exp, exp.toChars()); //printf("e1.op = %d, '%s'\n", e1.op, Token::toChars(e1.op)); } + + if (sc.flags & SCOPE.Cfile) + { + /* See if need to rewrite the AST because of cast/call ambiguity + */ + if (auto e = castCallAmbiguity(exp, sc)) + { + result = expressionSemantic(e, sc); + return; + } + } + if (exp.arrow) // ImportC only exp.e1 = exp.e1.expressionSemantic(sc).arrayFuncConv(sc); @@ -8059,6 +8068,17 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor } assert(!exp.type); + if (sc.flags & SCOPE.Cfile) + { + /* See if need to rewrite the AST because of cast/call ambiguity + */ + if (auto e = castCallAmbiguity(exp, sc)) + { + result = expressionSemantic(e, sc); + return; + } + } + result = exp.carraySemantic(sc); // C semantics if (result) return; @@ -8452,6 +8472,17 @@ private extern (C++) final class ExpressionSemanticVisitor : Visitor return; } + if (sc.flags & SCOPE.Cfile) + { + /* See if need to rewrite the AST because of cast/call ambiguity + */ + if (auto e = castCallAmbiguity(exp, sc)) + { + result = expressionSemantic(e, sc); + return; + } + } + if (Expression ex = binSemantic(exp, sc)) { result = ex; @@ -13050,7 +13081,7 @@ private bool fit(StructDeclaration sd, const ref Loc loc, Scope* sc, Expressions e = resolveProperties(sc, e); if (i >= nfields) { - if (i <= sd.fields.dim && e.op == EXP.null_) + if (i < sd.fields.dim && e.op == EXP.null_) { // CTFE sometimes creates null as hidden pointer; we'll allow this. continue; diff --git a/gcc/d/dmd/importc.d b/gcc/d/dmd/importc.d index 0dad1a8..5ee961f 100644 --- a/gcc/d/dmd/importc.d +++ b/gcc/d/dmd/importc.d @@ -15,13 +15,18 @@ module dmd.importc; import core.stdc.stdio; +import dmd.astenums; import dmd.dcast; +import dmd.declaration; import dmd.dscope; import dmd.dsymbol; import dmd.expression; import dmd.expressionsem; import dmd.identifier; +import dmd.init; import dmd.mtype; +import dmd.tokens; +import dmd.typesem; /************************************** * C11 does not allow array or function parameters. @@ -84,7 +89,7 @@ Expression arrayFuncConv(Expression e, Scope* sc) } else if (t.isTypeFunction()) { - e = e.addressOf(); + e = new AddrExp(e.loc, e); } else return e; @@ -169,3 +174,89 @@ Expression carraySemantic(ArrayExp ae, Scope* sc) auto ep = new PtrExp(ae.loc, new AddExp(ae.loc, e1, e2)); return ep.expressionSemantic(sc); } + +/****************************************** + * Determine default initializer for const global symbol. + */ +void addDefaultCInitializer(VarDeclaration dsym) +{ + //printf("addDefaultCInitializer() %s\n", dsym.toChars()); + if (!(dsym.storage_class & (STC.static_ | STC.gshared))) + return; + if (dsym.storage_class & (STC.extern_ | STC.field | STC.in_ | STC.foreach_ | STC.parameter | STC.result)) + return; + + Type t = dsym.type; + if (t.isTypeSArray() && t.isTypeSArray().isIncomplete()) + { + dsym._init = new VoidInitializer(dsym.loc); + return; // incomplete arrays will be diagnosed later + } + + if (t.isMutable()) + return; + + auto e = dsym.type.defaultInit(dsym.loc, true); + dsym._init = new ExpInitializer(dsym.loc, e); +} + +/******************************************** + * Resolve cast/call grammar ambiguity. + * Params: + * e = expression that might be a cast, might be a call + * sc = context + * Returns: + * null means leave as is, !=null means rewritten AST + */ +Expression castCallAmbiguity(Expression e, Scope* sc) +{ + Expression* pe = &e; + + while (1) + { + // Walk down the postfix expressions till we find a CallExp or something else + switch ((*pe).op) + { + case EXP.dotIdentifier: + pe = &(*pe).isDotIdExp().e1; + continue; + + case EXP.plusPlus: + case EXP.minusMinus: + pe = &(*pe).isPostExp().e1; + continue; + + case EXP.array: + pe = &(*pe).isArrayExp().e1; + continue; + + case EXP.call: + auto ce = (*pe).isCallExp(); + if (ce.e1.parens) + { + ce.e1 = expressionSemantic(ce.e1, sc); + if (ce.e1.op == EXP.type) + { + const numArgs = ce.arguments ? ce.arguments.length : 0; + if (numArgs >= 1) + { + ce.e1.parens = false; + Expression arg; + foreach (a; (*ce.arguments)[]) + { + arg = arg ? new CommaExp(a.loc, arg, a) : a; + } + auto t = ce.e1.isTypeExp().type; + *pe = arg; + return new CastExp(ce.loc, e, t); + } + } + } + return null; + + default: + return null; + } + } +} + diff --git a/gcc/d/dmd/initsem.d b/gcc/d/dmd/initsem.d index c5aa0f4..51ee27d 100644 --- a/gcc/d/dmd/initsem.d +++ b/gcc/d/dmd/initsem.d @@ -434,11 +434,22 @@ extern(C++) Initializer initializerSemantic(Initializer init, Scope* sc, ref Typ return i; } if (sc.flags & SCOPE.Cfile) + { /* the interpreter turns (char*)"string" into &"string"[0] which then * it cannot interpret. Resolve that case by doing optimize() first */ i.exp = i.exp.optimize(WANTvalue); - i.exp = i.exp.ctfeInterpret(); + if (i.exp.isSymOffExp()) + { + /* `static variable cannot be read at compile time` + * https://issues.dlang.org/show_bug.cgi?id=22513 + * Maybe this would be better addressed in ctfeInterpret()? + */ + needInterpret = NeedInterpret.INITnointerpret; + } + } + if (needInterpret) + i.exp = i.exp.ctfeInterpret(); if (i.exp.op == EXP.voidExpression) error(i.loc, "variables cannot be initialized with an expression of type `void`. Use `void` initialization instead."); } diff --git a/gcc/d/dmd/lexer.d b/gcc/d/dmd/lexer.d index d38cce4..bb76a1a 100644 --- a/gcc/d/dmd/lexer.d +++ b/gcc/d/dmd/lexer.d @@ -2073,6 +2073,7 @@ class Lexer bool overflow = false; bool anyBinaryDigitsNoSingleUS = false; bool anyHexDigitsNoSingleUS = false; + char errorDigit = 0; dchar c = *p; if (c == '0') { @@ -2093,8 +2094,7 @@ class Lexer case '8': case '9': - if (Ccompile) - error("octal digit expected, not `%c`", c); + errorDigit = cast(char) c; base = 8; break; case 'x': @@ -2205,12 +2205,9 @@ class Lexer // got a digit here, set any necessary flags, check for errors anyHexDigitsNoSingleUS = true; anyBinaryDigitsNoSingleUS = true; - if (!err && d >= base) + if (!errorDigit && d >= base) { - error("%s digit expected, not `%c`", base == 2 ? "binary".ptr : - base == 8 ? "octal".ptr : - "decimal".ptr, c); - err = true; + errorDigit = cast(char) c; } // Avoid expensive overflow check if we aren't at risk of overflow if (n <= 0x0FFF_FFFF_FFFF_FFFFUL) @@ -2224,6 +2221,13 @@ class Lexer } } Ldone: + if (errorDigit) + { + error("%s digit expected, not `%c`", base == 2 ? "binary".ptr : + base == 8 ? "octal".ptr : + "decimal".ptr, errorDigit); + err = true; + } if (overflow && !err) { error("integer overflow"); diff --git a/gcc/d/dmd/opover.d b/gcc/d/dmd/opover.d index 4d250c0..bafeaa3 100644 --- a/gcc/d/dmd/opover.d +++ b/gcc/d/dmd/opover.d @@ -523,8 +523,14 @@ Expression op_overload(Expression e, Scope* sc, EXP* pop = null) { // Deal with $ result = resolveOpDollar(sc, ae, ie, &e0); + if (result.op == EXP.error) + { + if (!e0 && !search_function(ad, Id.dollar)) { + ae.loc.errorSupplemental("Aggregate declaration '%s' does not define 'opDollar'", ae.e1.toChars()); + } return; + } /* Rewrite a[i..j] as: * a.opSlice(i, j) */ @@ -597,11 +603,13 @@ Expression op_overload(Expression e, Scope* sc, EXP* pop = null) /* Rewrite op(e1) as: * op(e1.aliasthis) */ - Expression e1 = resolveAliasThis(sc, e.e1); - result = e.copy(); - (cast(UnaExp)result).e1 = e1; - result = result.op_overload(sc); - return; + if (auto e1 = resolveAliasThis(sc, e.e1, true)) + { + result = e.copy(); + (cast(UnaExp)result).e1 = e1; + result = result.op_overload(sc); + return; + } } } } diff --git a/gcc/d/dmd/optimize.d b/gcc/d/dmd/optimize.d index 6b2176b..ca9e0b3 100644 --- a/gcc/d/dmd/optimize.d +++ b/gcc/d/dmd/optimize.d @@ -26,6 +26,7 @@ import dmd.expressionsem; import dmd.globals; import dmd.init; import dmd.mtype; +import dmd.printast; import dmd.root.ctfloat; import dmd.sideeffect; import dmd.tokens; @@ -270,6 +271,7 @@ package void setLengthVarIfKnown(VarDeclaration lengthVar, Type type) */ Expression Expression_optimize(Expression e, int result, bool keepLvalue) { + //printf("Expression_optimize() %s\n", e.toChars()); Expression ret = e; void error() @@ -459,6 +461,59 @@ Expression Expression_optimize(Expression e, int result, bool keepLvalue) return; } } + if (e.e1.isDotVarExp()) + { + /****************************** + * Run down the left side of the a.b.c expression to determine the + * leftmost variable being addressed (`a`), and accumulate the offsets of the `.b` and `.c`. + * Params: + * e = the DotVarExp or VarExp + * var = set to the VarExp at the end, or null if doesn't end in VarExp + * offset = accumulation of all the .var offsets encountered + * Returns: true on error + */ + static bool getVarAndOffset(Expression e, ref VarDeclaration var, ref uint offset) + { + if (e.type.size() == SIZE_INVALID) // trigger computation of v.offset + return true; + + if (auto dve = e.isDotVarExp()) + { + auto v = dve.var.isVarDeclaration(); + if (!v || !v.isField() || v.isBitFieldDeclaration()) + return false; + + if (getVarAndOffset(dve.e1, var, offset)) + return true; + offset += v.offset; + } + else if (auto ve = e.isVarExp()) + { + if (!ve.var.isReference() && + !ve.var.isImportedSymbol() && + ve.var.isDataseg() && + ve.var.isCsymbol()) + { + var = ve.var.isVarDeclaration(); + } + } + return false; + } + + uint offset; + VarDeclaration var; + if (getVarAndOffset(e.e1, var, offset)) + { + ret = ErrorExp.get(); + return; + } + if (var) + { + ret = new SymOffExp(e.loc, var, offset, false); + ret.type = e.type; + return; + } + } if (auto ae = e.e1.isIndexExp()) { // Convert &array[n] to &array+n diff --git a/gcc/d/dmd/parse.d b/gcc/d/dmd/parse.d index 2229e78..94056ab 100644 --- a/gcc/d/dmd/parse.d +++ b/gcc/d/dmd/parse.d @@ -5758,7 +5758,26 @@ LagainStc: nextToken(); } else - check(TOK.semicolon, "statement"); + { + /* + * https://issues.dlang.org/show_bug.cgi?id=22529 + * Avoid empty declaration error in case of missing semicolon + * followed by another token and another semicolon. E.g.: + * + * foo() + * return; + * + * When the missing `;` error is emitted, token is sitting on return. + * If we simply use `check` to emit the error, the token is advanced + * to `;` and the empty statement error would follow. To avoid that, + * we check if the next token is a semicolon and simply output the error, + * otherwise we fall back on the old path (advancing the token). + */ + if (token.value != TOK.semicolon && peek(&token).value == TOK.semicolon) + error("found `%s` when expecting `;` following statement", token.toChars()); + else + check(TOK.semicolon, "statement"); + } s = new AST.ExpStatement(loc, exp); break; } diff --git a/gcc/d/dmd/printast.d b/gcc/d/dmd/printast.d index b9f0c5e..33b5e7f3 100644 --- a/gcc/d/dmd/printast.d +++ b/gcc/d/dmd/printast.d @@ -82,6 +82,24 @@ extern (C++) final class PrintASTVisitor : Visitor printf(".var: %s\n", e.var ? e.var.toChars() : ""); } + override void visit(SymOffExp e) + { + printIndent(indent); + printf("SymOff %s\n", e.type ? e.type.toChars() : ""); + printIndent(indent + 2); + printf(".var: %s\n", e.var ? e.var.toChars() : ""); + printIndent(indent + 2); + printf(".offset: %llx\n", e.offset); + } + + override void visit(VarExp e) + { + printIndent(indent); + printf("Var %s\n", e.type ? e.type.toChars() : ""); + printIndent(indent + 2); + printf(".var: %s\n", e.var ? e.var.toChars() : ""); + } + override void visit(DsymbolExp e) { visit(cast(Expression)e); @@ -120,6 +138,15 @@ extern (C++) final class PrintASTVisitor : Visitor printAST(e.e1, indent + 2); } + override void visit(DotVarExp e) + { + printIndent(indent); + printf("DotVar %s\n", e.type ? e.type.toChars() : ""); + printIndent(indent + 2); + printf(".var: %s\n", e.var.toChars()); + printAST(e.e1, indent + 2); + } + override void visit(BinExp e) { visit(cast(Expression)e); diff --git a/gcc/d/dmd/semantic3.d b/gcc/d/dmd/semantic3.d index 893f96b..da328fd 100644 --- a/gcc/d/dmd/semantic3.d +++ b/gcc/d/dmd/semantic3.d @@ -235,6 +235,18 @@ private extern(C++) final class Semantic3Visitor : Visitor if (funcdecl.errors || isError(funcdecl.parent)) { funcdecl.errors = true; + + // Mark that the return type could not be inferred + if (funcdecl.inferRetType) + { + assert(funcdecl.type); + auto tf = funcdecl.type.isTypeFunction(); + + // Only change the return type s.t. other analysis is + // still possible e.g. missmatched parameter types + if (tf && !tf.next) + tf.next = Type.terror; + } return; } //printf("FuncDeclaration::semantic3('%s.%s', %p, sc = %p, loc = %s)\n", funcdecl.parent.toChars(), funcdecl.toChars(), funcdecl, sc, funcdecl.loc.toChars()); diff --git a/gcc/d/dmd/statementsem.d b/gcc/d/dmd/statementsem.d index 6979cdf..91855ac 100644 --- a/gcc/d/dmd/statementsem.d +++ b/gcc/d/dmd/statementsem.d @@ -2471,64 +2471,69 @@ private extern (C++) final class StatementSemanticVisitor : Visitor { Expression initialExp = cs.exp; - cs.exp = cs.exp.implicitCastTo(sc, sw.condition.type); - cs.exp = cs.exp.optimize(WANTvalue | WANTexpand); - - Expression e = cs.exp; - // Remove all the casts the user and/or implicitCastTo may introduce - // otherwise we'd sometimes fail the check below. - while (e.op == EXP.cast_) - e = (cast(CastExp)e).e1; - - /* This is where variables are allowed as case expressions. - */ - if (e.op == EXP.variable) - { - VarExp ve = cast(VarExp)e; - VarDeclaration v = ve.var.isVarDeclaration(); - Type t = cs.exp.type.toBasetype(); - if (v && (t.isintegral() || t.ty == Tclass)) + // The switch'ed value has errors and doesn't provide the actual type + // Don't touch the case to not replace it with an `ErrorExp` even if it is valid + if (sw.condition.type && !sw.condition.type.isTypeError()) + { + cs.exp = cs.exp.implicitCastTo(sc, sw.condition.type); + cs.exp = cs.exp.optimize(WANTvalue | WANTexpand); + + Expression e = cs.exp; + // Remove all the casts the user and/or implicitCastTo may introduce + // otherwise we'd sometimes fail the check below. + while (e.op == EXP.cast_) + e = (cast(CastExp)e).e1; + + /* This is where variables are allowed as case expressions. + */ + if (e.op == EXP.variable) { - /* Flag that we need to do special code generation - * for this, i.e. generate a sequence of if-then-else - */ - sw.hasVars = 1; - - /* TODO check if v can be uninitialized at that point. - */ - if (!v.isConst() && !v.isImmutable()) - { - cs.error("`case` variables have to be `const` or `immutable`"); - } - - if (sw.isFinal) - { - cs.error("`case` variables not allowed in `final switch` statements"); - errors = true; - } - - /* Find the outermost scope `scx` that set `sw`. - * Then search scope `scx` for a declaration of `v`. - */ - for (Scope* scx = sc; scx; scx = scx.enclosing) + VarExp ve = cast(VarExp)e; + VarDeclaration v = ve.var.isVarDeclaration(); + Type t = cs.exp.type.toBasetype(); + if (v && (t.isintegral() || t.ty == Tclass)) { - if (scx.enclosing && scx.enclosing.sw == sw) - continue; - assert(scx.sw == sw); + /* Flag that we need to do special code generation + * for this, i.e. generate a sequence of if-then-else + */ + sw.hasVars = 1; + + /* TODO check if v can be uninitialized at that point. + */ + if (!v.isConst() && !v.isImmutable()) + { + cs.error("`case` variables have to be `const` or `immutable`"); + } - if (!scx.search(cs.exp.loc, v.ident, null)) + if (sw.isFinal) { - cs.error("`case` variable `%s` declared at %s cannot be declared in `switch` body", - v.toChars(), v.loc.toChars()); + cs.error("`case` variables not allowed in `final switch` statements"); errors = true; } - break; + + /* Find the outermost scope `scx` that set `sw`. + * Then search scope `scx` for a declaration of `v`. + */ + for (Scope* scx = sc; scx; scx = scx.enclosing) + { + if (scx.enclosing && scx.enclosing.sw == sw) + continue; + assert(scx.sw == sw); + + if (!scx.search(cs.exp.loc, v.ident, null)) + { + cs.error("`case` variable `%s` declared at %s cannot be declared in `switch` body", + v.toChars(), v.loc.toChars()); + errors = true; + } + break; + } + goto L1; } - goto L1; } + else + cs.exp = cs.exp.ctfeInterpret(); } - else - cs.exp = cs.exp.ctfeInterpret(); if (StringExp se = cs.exp.toStringExp()) cs.exp = se; @@ -2539,6 +2544,8 @@ private extern (C++) final class StatementSemanticVisitor : Visitor } L1: + // // Don't check other cases if this has errors + if (!cs.exp.isErrorExp()) foreach (cs2; *sw.cases) { //printf("comparing '%s' with '%s'\n", exp.toChars(), cs.exp.toChars()); @@ -2877,9 +2884,6 @@ private extern (C++) final class StatementSemanticVisitor : Visitor if (rs.exp.op == EXP.call) rs.exp = valueNoDtor(rs.exp); - if (e0) - e0 = e0.optimize(WANTvalue); - /* Void-return function can have void / noreturn typed expression * on return statement. */ @@ -2904,7 +2908,10 @@ private extern (C++) final class StatementSemanticVisitor : Visitor rs.exp = null; } if (e0) + { + e0 = e0.optimize(WANTvalue); e0 = checkGC(sc, e0); + } } if (rs.exp) diff --git a/gcc/d/dmd/target.d b/gcc/d/dmd/target.d index 7a875a5..8e434a3 100644 --- a/gcc/d/dmd/target.d +++ b/gcc/d/dmd/target.d @@ -323,7 +323,7 @@ struct TargetC /// https://docs.microsoft.com/en-us/cpp/cpp/cpp-bit-fields?view=msvc-160 Gcc_Clang, /// gcc and clang } - + bool crtDestructorsSupported = true; /// Not all platforms support crt_destructor ubyte longsize; /// size of a C `long` or `unsigned long` type ubyte long_doublesize; /// size of a C `long double` ubyte wchar_tsize; /// size of a C `wchar_t` type diff --git a/gcc/d/dmd/target.h b/gcc/d/dmd/target.h index 1363693..6348d93 100644 --- a/gcc/d/dmd/target.h +++ b/gcc/d/dmd/target.h @@ -70,6 +70,7 @@ struct TargetC Gcc_Clang, // gcc and clang }; + uint8_t crtDestructorsSupported; // Not all platforms support crt_destructor uint8_t longsize; // size of a C 'long' or 'unsigned long' type uint8_t long_doublesize; // size of a C 'long double' uint8_t wchar_tsize; // size of a C 'wchar_t' type diff --git a/gcc/d/dmd/tokens.d b/gcc/d/dmd/tokens.d index 2609af5..2d98d5e 100644 --- a/gcc/d/dmd/tokens.d +++ b/gcc/d/dmd/tokens.d @@ -52,38 +52,22 @@ enum TOK : ushort new_, delete_, star, - symbolOffset, variable, - dotVariable, - dotIdentifier, - dotTemplateInstance, - dotType, slice, - arrayLength, version_, module_, dollar, template_, - dotTemplateDeclaration, declaration, typeof_, pragma_, - dSymbol, typeid_, uadd, remove, - newAnonymousClass, comment, - arrayLiteral, - assocArrayLiteral, - structLiteral, - classReference, - thrownException, - delegatePointer, - delegateFunctionPointer, // Operators - lessThan = 54, + lessThan, greaterThan, lessOrEqual, greaterOrEqual, @@ -94,7 +78,7 @@ enum TOK : ushort index, is_, - leftShift = 64, + leftShift, rightShift, leftShiftAssign, rightShiftAssign, @@ -136,7 +120,7 @@ enum TOK : ushort preMinusMinus, // Numeric literals - int32Literal = 104, + int32Literal, uns32Literal, int64Literal, uns64Literal, @@ -150,22 +134,21 @@ enum TOK : ushort imaginary80Literal, // Char constants - charLiteral = 116, + charLiteral, wcharLiteral, dcharLiteral, // Leaf operators - identifier = 119, + identifier, string_, hexadecimalString, this_, super_, - halt, tuple, error, // Basic types - void_ = 127, + void_, int8, uns8, int16, @@ -191,7 +174,7 @@ enum TOK : ushort bool_, // Aggregates - struct_ = 151, + struct_, class_, interface_, union_, @@ -223,7 +206,7 @@ enum TOK : ushort immutable_, // Statements - if_ = 181, + if_, else_, while_, for_, @@ -249,7 +232,7 @@ enum TOK : ushort onScopeSuccess, // Contracts - invariant_ = 205, + invariant_, // Testing unittest_, @@ -259,7 +242,7 @@ enum TOK : ushort ref_, macro_, - parameters = 210, + parameters, traits, overloadSet, pure_, @@ -279,18 +262,9 @@ enum TOK : ushort vector, pound, - interval = 229, - voidExpression, - cantExpression, - showCtfeContext, - - objcClassReference, - vectorArray, - arrow, // -> colonColon, // :: wchar_tLiteral, - compoundLiteral, // ( type-name ) { initializer-list } // C only keywords inline, @@ -885,33 +859,17 @@ extern (C++) struct Token // For debugging TOK.error: "error", - TOK.dotIdentifier: "dotid", - TOK.dotTemplateDeclaration: "dottd", - TOK.dotTemplateInstance: "dotti", - TOK.dotVariable: "dotvar", - TOK.dotType: "dottype", - TOK.symbolOffset: "symoff", - TOK.arrayLength: "arraylength", - TOK.arrayLiteral: "arrayliteral", - TOK.assocArrayLiteral: "assocarrayliteral", - TOK.structLiteral: "structliteral", TOK.string_: "string", - TOK.dSymbol: "symbol", TOK.tuple: "tuple", TOK.declaration: "declaration", TOK.onScopeExit: "scope(exit)", TOK.onScopeSuccess: "scope(success)", TOK.onScopeFailure: "scope(failure)", - TOK.delegatePointer: "delegateptr", // Finish up TOK.reserved: "reserved", TOK.remove: "remove", - TOK.newAnonymousClass: "newanonclass", TOK.comment: "comment", - TOK.classReference: "classreference", - TOK.thrownException: "thrownexception", - TOK.delegateFunctionPointer: "delegatefuncptr", TOK.int32Literal: "int32v", TOK.uns32Literal: "uns32v", TOK.int64Literal: "int64v", @@ -928,19 +886,9 @@ extern (C++) struct Token TOK.wcharLiteral: "wcharv", TOK.dcharLiteral: "dcharv", TOK.wchar_tLiteral: "wchar_tv", - TOK.compoundLiteral: "compoundliteral", - TOK.halt: "halt", TOK.hexadecimalString: "xstring", - TOK.interval: "interval", - TOK.voidExpression: "voidexp", - TOK.cantExpression: "cantexp", - TOK.showCtfeContext : "showCtfeContext", - - TOK.objcClassReference: "class", - TOK.vectorArray: "vectorarray", - // C only keywords TOK.inline : "inline", TOK.register : "register", diff --git a/gcc/d/dmd/tokens.h b/gcc/d/dmd/tokens.h index f3e4411..2e1d1f4 100644 --- a/gcc/d/dmd/tokens.h +++ b/gcc/d/dmd/tokens.h @@ -61,35 +61,19 @@ enum class TOK : unsigned short new_, delete_, star, - symbolOffset, variable, - dotVariable, - dotIdentifier, - dotTemplateInstance, - dotType, slice, - arrayLength, version_, module_, dollar, template_, - dotTemplateDeclaration, declaration, typeof_, pragma_, - dSymbol, typeid_, uadd, remove, - newAnonymousClass, comment, - arrayLiteral, - assocArrayLiteral, - structLiteral, - classReference, - thrownException, - delegatePointer, - delegateFunctionPointer, // Operators lessThan, // 54 @@ -169,7 +153,6 @@ enum class TOK : unsigned short hexadecimalString, this_, super_, - halt, tuple, error, @@ -288,18 +271,9 @@ enum class TOK : unsigned short vector, pound, - interval, // 229 - voidExpression, - cantExpression, - showCtfeContext, - - objcClassReference, - vectorArray, - arrow, // -> colonColon, // :: wchar_tLiteral, - compoundLiteral, // ( type-name ) { initializer-list } // C only keywords inline_, diff --git a/gcc/d/dmd/typesem.d b/gcc/d/dmd/typesem.d index 417d2c1..2a86416 100644 --- a/gcc/d/dmd/typesem.d +++ b/gcc/d/dmd/typesem.d @@ -1709,13 +1709,22 @@ extern(C++) Type typeSemantic(Type type, const ref Loc loc, Scope* sc) } else if (e.op == EXP.variable) // special case: variable is used as a type { + /* + N.B. This branch currently triggers for the following code + template test(x* x) + { + + } + i.e. the compiler prints "variable x is used as a type" + which isn't a particularly good error message (x is a variable?). + */ Dsymbol varDecl = mtype.toDsymbol(sc); const(Loc) varDeclLoc = varDecl.getLoc(); - Module varDeclModule = varDecl.getModule(); + Module varDeclModule = varDecl.getModule(); //This can be null .error(loc, "variable `%s` is used as a type", mtype.toChars()); - - if (varDeclModule != sc._module) // variable is imported + //Check for null to avoid https://issues.dlang.org/show_bug.cgi?id=22574 + if ((varDeclModule !is null) && varDeclModule != sc._module) // variable is imported { const(Loc) varDeclModuleImportLoc = varDeclModule.getLoc(); .errorSupplemental( @@ -4630,11 +4639,12 @@ Expression dotExp(Type mt, Scope* sc, Expression e, Identifier ident, int flag) * Params: * mt = the type for which the init expression is returned * loc = the location where the expression needs to be evaluated + * isCfile = default initializers are different with C * * Returns: * The initialization expression for the type. */ -extern (C++) Expression defaultInit(Type mt, const ref Loc loc) +extern (C++) Expression defaultInit(Type mt, const ref Loc loc, const bool isCfile = false) { Expression visitBasic(TypeBasic mt) { @@ -4647,12 +4657,12 @@ extern (C++) Expression defaultInit(Type mt, const ref Loc loc) switch (mt.ty) { case Tchar: - value = 0xFF; + value = isCfile ? 0 : 0xFF; break; case Twchar: case Tdchar: - value = 0xFFFF; + value = isCfile ? 0 : 0xFFFF; break; case Timaginary32: @@ -4661,14 +4671,15 @@ extern (C++) Expression defaultInit(Type mt, const ref Loc loc) case Tfloat32: case Tfloat64: case Tfloat80: - return new RealExp(loc, target.RealProperties.nan, mt); + return new RealExp(loc, isCfile ? CTFloat.zero : target.RealProperties.nan, mt); case Tcomplex32: case Tcomplex64: case Tcomplex80: { // Can't use fvalue + I*fvalue (the im part becomes a quiet NaN). - const cvalue = complex_t(target.RealProperties.nan, target.RealProperties.nan); + const cvalue = isCfile ? complex_t(CTFloat.zero, CTFloat.zero) + : complex_t(target.RealProperties.nan, target.RealProperties.nan); return new ComplexExp(loc, cvalue, mt); } @@ -4686,7 +4697,7 @@ extern (C++) Expression defaultInit(Type mt, const ref Loc loc) { //printf("TypeVector::defaultInit()\n"); assert(mt.basetype.ty == Tsarray); - Expression e = mt.basetype.defaultInit(loc); + Expression e = mt.basetype.defaultInit(loc, isCfile); auto ve = new VectorExp(loc, e, mt); ve.type = mt; ve.dim = cast(int)(mt.basetype.size(loc) / mt.elementType().size(loc)); @@ -4700,9 +4711,9 @@ extern (C++) Expression defaultInit(Type mt, const ref Loc loc) printf("TypeSArray::defaultInit() '%s'\n", mt.toChars()); } if (mt.next.ty == Tvoid) - return mt.tuns8.defaultInit(loc); + return mt.tuns8.defaultInit(loc, isCfile); else - return mt.next.defaultInit(loc); + return mt.next.defaultInit(loc, isCfile); } Expression visitFunction(TypeFunction mt) diff --git a/gcc/d/gdc.texi b/gcc/d/gdc.texi index d37d205..bfec156 100644 --- a/gcc/d/gdc.texi +++ b/gcc/d/gdc.texi @@ -267,15 +267,16 @@ Sets the C++ name mangling compatibility to the version identified by @table @samp @item c++98 @item c++03 -Sets @code{__traits(getTargetInfo "cppStd")} to @code{199711}. +Sets @code{__traits(getTargetInfo, "cppStd")} to @code{199711}. @item c++11 -Sets @code{__traits(getTargetInfo "cppStd")} to @code{201103}. +Sets @code{__traits(getTargetInfo, "cppStd")} to @code{201103}. @item c++14 -Sets @code{__traits(getTargetInfo "cppStd")} to @code{201402}. +Sets @code{__traits(getTargetInfo, "cppStd")} to @code{201402}. @item c++17 -Sets @code{__traits(getTargetInfo "cppStd")} to @code{201703}. +Sets @code{__traits(getTargetInfo, "cppStd")} to @code{201703}. +This is the default. @item c++20 -Sets @code{__traits(getTargetInfo "cppStd")} to @code{202002}. +Sets @code{__traits(getTargetInfo, "cppStd")} to @code{202002}. @end table @item -fno-invariants diff --git a/gcc/testsuite/gdc.test/compilable/cppmangle.d b/gcc/testsuite/gdc.test/compilable/cppmangle.d index 1820de9..8c112d1 100644 --- a/gcc/testsuite/gdc.test/compilable/cppmangle.d +++ b/gcc/testsuite/gdc.test/compilable/cppmangle.d @@ -7,6 +7,12 @@ import core.stdc.stdio; +version (CppRuntime_Clang) version = CppMangle_Itanium; +version (CppRuntime_DigitalMars) version = CppMangle_MSVC; +version (CppRuntime_Gcc) version = CppMangle_Itanium; +version (CppRuntime_Microsoft) version = CppMangle_MSVC; +version (CppRuntime_Sun) version = CppMangle_Itanium; + extern (C++) int foob(int i, int j, int k); class C @@ -45,23 +51,26 @@ void test1() c.bar(4, 5, 6); } -version (Posix) +version (CppMangle_Itanium) { static assert(foo.mangleof == "_Z3fooiii"); static assert(foob.mangleof == "_Z4foobiii"); static assert(C.bar.mangleof == "_ZN1C3barEiii"); } -version (Win32) -{ - static assert(foo.mangleof == "?foo@@YAHHHH@Z"); - static assert(foob.mangleof == "?foob@@YAHHHH@Z"); - static assert(C.bar.mangleof == "?bar@C@@UAEHHHH@Z"); -} -version (Win64) +version (CppMangle_MSVC) { - static assert(foo.mangleof == "?foo@@YAHHHH@Z"); - static assert(foob.mangleof == "?foob@@YAHHHH@Z"); - static assert(C.bar.mangleof == "?bar@C@@UEAAHHHH@Z"); + version (Win32) + { + static assert(foo.mangleof == "?foo@@YAHHHH@Z"); + static assert(foob.mangleof == "?foob@@YAHHHH@Z"); + static assert(C.bar.mangleof == "?bar@C@@UAEHHHH@Z"); + } + version (Win64) + { + static assert(foo.mangleof == "?foo@@YAHHHH@Z"); + static assert(foob.mangleof == "?foob@@YAHHHH@Z"); + static assert(C.bar.mangleof == "?bar@C@@UEAAHHHH@Z"); + } } /****************************************/ @@ -81,7 +90,7 @@ void test2() assert(i == 8); } -version (Posix) +version (CppMangle_Itanium) { static assert (getD.mangleof == "_Z4getDv"); static assert (D.bar.mangleof == "_ZN1D3barEiii"); @@ -118,7 +127,7 @@ void test3() assert(i == 8); } -version (Posix) +version (CppMangle_Itanium) { static assert (callE.mangleof == "_Z5callEP1E"); static assert (E.bar.mangleof == "_ZN1E3barEiii"); @@ -134,7 +143,7 @@ void test4() foo4(null); } -version (Posix) +version (CppMangle_Itanium) { static assert(foo4.mangleof == "_Z4foo4Pc"); } @@ -160,7 +169,7 @@ void test5() assert(f.p == cast(void*)b); } -version (Posix) +version (CppMangle_Itanium) { static assert(bar5.getFoo.mangleof == "_ZN4bar56getFooEi"); static assert (newBar.mangleof == "_Z6newBarv"); @@ -190,7 +199,7 @@ void test6() assert(f.d == 2.5); } -version (Posix) +version (CppMangle_Itanium) { static assert (foo6.mangleof == "_Z4foo6v"); } @@ -221,7 +230,7 @@ void test8() foo8(&c); } -version (Posix) +version (CppMangle_Itanium) { static assert(foo8.mangleof == "_Z4foo8PKc"); } @@ -239,7 +248,7 @@ void test9() foobar9(a, a); } -version (Posix) +version (CppMangle_Itanium) { static assert(foobar9.mangleof == "_Z7foobar9P5elem9S0_"); } @@ -298,7 +307,7 @@ extern (C++) void test10058l(void* function(void*), void* function(const (void)*), const(void)* function(void*)) { } } -version (Posix) +version (CppMangle_Itanium) { static assert(test10058a.mangleof == "_Z10test10058aPv"); static assert(test10058b.mangleof == "_Z10test10058bPFvPvE"); @@ -329,7 +338,7 @@ class CallExp static void test11696d(Loc, Expression*, Expression*); } -version (Posix) +version (CppMangle_Itanium) { static assert(CallExp.test11696a.mangleof == "_ZN7CallExp10test11696aE3LocP10ExpressionS2_"); static assert(CallExp.test11696b.mangleof == "_ZN7CallExp10test11696bE3LocP10ExpressionPS2_"); @@ -353,7 +362,7 @@ extern(C++, `N13337a`, `N13337b`, `N13337c`) void foo13337_3(S13337_2 s); } -version (Posix) +version (CppMangle_Itanium) { static assert(foo13337.mangleof == "_ZN7N13337a7N13337b7N13337c8foo13337ENS1_6S13337E"); static assert(foo13337_2.mangleof == "_ZN7N13337a7N13337b7N13337c10foo13337_2ENS1_6S13337E"); @@ -383,7 +392,7 @@ extern(C++) } } -version (Posix) +version (CppMangle_Itanium) { static assert(Struct7030.foo.mangleof == "_ZNK10Struct70303fooEi"); static assert(Struct7030.bar.mangleof == "_ZN10Struct70303barEi"); @@ -494,7 +503,7 @@ extern (C++) void func_20413(pair!(int, float), pair!(float, int)); } -version (Posix) +version (CppMangle_Itanium) { // https://issues.dlang.org/show_bug.cgi?id=17947 static assert(std.pair!(void*, void*).swap.mangleof == "_ZNSt4pairIPvS0_E4swapERS1_"); @@ -531,7 +540,7 @@ alias T36 = int ********** ********** ********** **********; extern (C++) void test36(T36, T36*) { } -version (Posix) +version (CppMangle_Itanium) { static assert(test36.mangleof == "_Z6test36PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPiPS12_"); } @@ -545,7 +554,7 @@ int test37(T)(){ return 0;} extern(C++, `SPACE`) int test37(T)(){ return 0;} -version (Posix) // all non-Windows machines +version (CppMangle_Itanium) // all non-Windows machines { static assert(SPACE.test37!int.mangleof == "_ZN5SPACE6test37IiEEiv"); static assert(test37!int.mangleof == "_ZN5SPACE6test37IiEEiv"); @@ -556,11 +565,11 @@ version (Posix) // all non-Windows machines extern (C++) void test15388(typeof(null)); -version (Posix) +version (CppMangle_Itanium) { static assert(test15388.mangleof == "_Z9test15388Dn"); } -version (Windows) +version (CppMangle_MSVC) { static assert(test15388.mangleof == "?test15388@@YAX$$T@Z"); } @@ -583,7 +592,7 @@ extern (C++) struct Test14086_S ~this(); } -version(Posix) +version (CppMangle_Itanium) { static assert(Test14086.__ctor.mangleof == "_ZN9Test14086C1Ev"); static assert(Test14086.__dtor.mangleof == "_ZN9Test14086D1Ev"); @@ -591,21 +600,24 @@ version(Posix) static assert(Test14086_S.__ctor.mangleof == "_ZN11Test14086_SC1Ei"); static assert(Test14086_S.__dtor.mangleof == "_ZN11Test14086_SD1Ev"); } -version(Win32) -{ - static assert(Test14086.__ctor.mangleof == "??0Test14086@@QAE@XZ"); - static assert(Test14086.__dtor.mangleof == "??1Test14086@@UAE@XZ"); - static assert(Test14086_2.__dtor.mangleof == "??1Test14086_2@@QAE@XZ"); - static assert(Test14086_S.__ctor.mangleof == "??0Test14086_S@@QAE@H@Z"); - static assert(Test14086_S.__dtor.mangleof == "??1Test14086_S@@QAE@XZ"); -} -version(Win64) +version (CppMangle_MSVC) { - static assert(Test14086.__ctor.mangleof == "??0Test14086@@QEAA@XZ"); - static assert(Test14086.__dtor.mangleof == "??1Test14086@@UEAA@XZ"); - static assert(Test14086_2.__dtor.mangleof == "??1Test14086_2@@QEAA@XZ"); - static assert(Test14086_S.__ctor.mangleof == "??0Test14086_S@@QEAA@H@Z"); - static assert(Test14086_S.__dtor.mangleof == "??1Test14086_S@@QEAA@XZ"); + version (Win32) + { + static assert(Test14086.__ctor.mangleof == "??0Test14086@@QAE@XZ"); + static assert(Test14086.__dtor.mangleof == "??1Test14086@@UAE@XZ"); + static assert(Test14086_2.__dtor.mangleof == "??1Test14086_2@@QAE@XZ"); + static assert(Test14086_S.__ctor.mangleof == "??0Test14086_S@@QAE@H@Z"); + static assert(Test14086_S.__dtor.mangleof == "??1Test14086_S@@QAE@XZ"); + } + version (Win64) + { + static assert(Test14086.__ctor.mangleof == "??0Test14086@@QEAA@XZ"); + static assert(Test14086.__dtor.mangleof == "??1Test14086@@UEAA@XZ"); + static assert(Test14086_2.__dtor.mangleof == "??1Test14086_2@@QEAA@XZ"); + static assert(Test14086_S.__ctor.mangleof == "??0Test14086_S@@QEAA@H@Z"); + static assert(Test14086_S.__dtor.mangleof == "??1Test14086_S@@QEAA@XZ"); + } } /**************************************/ @@ -623,17 +635,20 @@ struct S18888(alias arg = T18888) alias I = T18888!(arg!int); } -version(Posix) +version (CppMangle_Itanium) { static assert(S18888!().I.fun.mangleof == "_ZN6T18888IS_IiEE3funEv"); } -version(Win32) -{ - static assert(S18888!().I.fun.mangleof == "?fun@?$T18888@U?$T18888@H@@@@QAEXXZ"); -} -version(Win64) +version (CppMangle_MSVC) { - static assert(S18888!().I.fun.mangleof == "?fun@?$T18888@U?$T18888@H@@@@QEAAXXZ"); + version (Win32) + { + static assert(S18888!().I.fun.mangleof == "?fun@?$T18888@U?$T18888@H@@@@QAEXXZ"); + } + version (Win64) + { + static assert(S18888!().I.fun.mangleof == "?fun@?$T18888@U?$T18888@H@@@@QEAAXXZ"); + } } /**************************************/ @@ -653,26 +668,29 @@ extern (C++) class C18890_2 Agg s; } -version (Posix) +version (CppMangle_Itanium) { static assert(C18890.__dtor.mangleof == "_ZN6C18890D1Ev"); static assert(C18890.__xdtor.mangleof == "_ZN6C18890D1Ev"); static assert(C18890_2.__dtor.mangleof == "_ZN8C18890_26__dtorEv"); static assert(C18890_2.__xdtor.mangleof == "_ZN8C18890_2D1Ev"); } -version (Win32) +version (CppMangle_MSVC) { - static assert(C18890.__dtor.mangleof == "??1C18890@@UAE@XZ"); - static assert(C18890.__xdtor.mangleof == "??_GC18890@@UAEPAXI@Z"); - static assert(C18890_2.__dtor.mangleof == "?__dtor@C18890_2@@UAEXXZ"); - static assert(C18890_2.__xdtor.mangleof == "??_GC18890_2@@UAEPAXI@Z"); -} -version (Win64) -{ - static assert(C18890.__dtor.mangleof == "??1C18890@@UEAA@XZ"); - static assert(C18890.__xdtor.mangleof == "??_GC18890@@UEAAPEAXI@Z"); - static assert(C18890_2.__dtor.mangleof == "?__dtor@C18890_2@@UEAAXXZ"); - static assert(C18890_2.__xdtor.mangleof == "??_GC18890_2@@UEAAPEAXI@Z"); + version (Win32) + { + static assert(C18890.__dtor.mangleof == "??1C18890@@UAE@XZ"); + static assert(C18890.__xdtor.mangleof == "??_GC18890@@UAEPAXI@Z"); + static assert(C18890_2.__dtor.mangleof == "?__dtor@C18890_2@@UAEXXZ"); + static assert(C18890_2.__xdtor.mangleof == "??_GC18890_2@@UAEPAXI@Z"); + } + version (Win64) + { + static assert(C18890.__dtor.mangleof == "??1C18890@@UEAA@XZ"); + static assert(C18890.__xdtor.mangleof == "??_GC18890@@UEAAPEAXI@Z"); + static assert(C18890_2.__dtor.mangleof == "?__dtor@C18890_2@@UEAAXXZ"); + static assert(C18890_2.__xdtor.mangleof == "??_GC18890_2@@UEAAPEAXI@Z"); + } } /**************************************/ @@ -688,20 +706,23 @@ extern (C++) class C18891 Agg s; } -version (Posix) +version (CppMangle_Itanium) { static assert(C18891.__dtor.mangleof == "_ZN6C18891D1Ev"); static assert(C18891.__xdtor.mangleof == "_ZN6C18891D1Ev"); } -version (Win32) +version (CppMangle_MSVC) { - static assert(C18891.__dtor.mangleof == "??1C18891@@UAE@XZ"); - static assert(C18891.__xdtor.mangleof == "??_GC18891@@UAEPAXI@Z"); -} -version (Win64) -{ - static assert(C18891.__dtor.mangleof == "??1C18891@@UEAA@XZ"); - static assert(C18891.__xdtor.mangleof == "??_GC18891@@UEAAPEAXI@Z"); + version (Win32) + { + static assert(C18891.__dtor.mangleof == "??1C18891@@UAE@XZ"); + static assert(C18891.__xdtor.mangleof == "??_GC18891@@UAEPAXI@Z"); + } + version (Win64) + { + static assert(C18891.__dtor.mangleof == "??1C18891@@UEAA@XZ"); + static assert(C18891.__xdtor.mangleof == "??_GC18891@@UEAAPEAXI@Z"); + } } /**************************************/ @@ -719,7 +740,7 @@ extern (C++) struct TestOperators int opAssign(int); } -version (Posix) +version (CppMangle_Itanium) { static assert(TestOperators.opUnary!"*".mangleof == "_ZN13TestOperatorsdeEv"); static assert(TestOperators.opUnary!"++".mangleof == "_ZN13TestOperatorsppEv"); @@ -753,73 +774,76 @@ version (Posix) static assert(TestOperators.opIndex.mangleof == "_ZN13TestOperatorsixEi"); static assert(TestOperators.opCall.mangleof == "_ZN13TestOperatorsclEif"); } -version (Win32) -{ - static assert(TestOperators.opUnary!"*".mangleof == "??DTestOperators@@QAEHXZ"); - static assert(TestOperators.opUnary!"++".mangleof == "??ETestOperators@@QAEHXZ"); - static assert(TestOperators.opUnary!"--".mangleof == "??FTestOperators@@QAEHXZ"); - static assert(TestOperators.opUnary!"-".mangleof == "??GTestOperators@@QAEHXZ"); - static assert(TestOperators.opUnary!"+".mangleof == "??HTestOperators@@QAEHXZ"); - static assert(TestOperators.opUnary!"~".mangleof == "??STestOperators@@QAEHXZ"); - static assert(TestOperators.opBinary!">>".mangleof == "??5TestOperators@@QAEHH@Z"); - static assert(TestOperators.opBinary!"<<".mangleof == "??6TestOperators@@QAEHH@Z"); - static assert(TestOperators.opBinary!"*".mangleof == "??DTestOperators@@QAEHH@Z"); - static assert(TestOperators.opBinary!"-".mangleof == "??GTestOperators@@QAEHH@Z"); - static assert(TestOperators.opBinary!"+".mangleof == "??HTestOperators@@QAEHH@Z"); - static assert(TestOperators.opBinary!"&".mangleof == "??ITestOperators@@QAEHH@Z"); - static assert(TestOperators.opBinary!"/".mangleof == "??KTestOperators@@QAEHH@Z"); - static assert(TestOperators.opBinary!"%".mangleof == "??LTestOperators@@QAEHH@Z"); - static assert(TestOperators.opBinary!"^".mangleof == "??TTestOperators@@QAEHH@Z"); - static assert(TestOperators.opBinary!"|".mangleof == "??UTestOperators@@QAEHH@Z"); - static assert(TestOperators.opOpAssign!"*".mangleof == "??XTestOperators@@QAEHH@Z"); - static assert(TestOperators.opOpAssign!"+".mangleof == "??YTestOperators@@QAEHH@Z"); - static assert(TestOperators.opOpAssign!"-".mangleof == "??ZTestOperators@@QAEHH@Z"); - static assert(TestOperators.opOpAssign!"/".mangleof == "??_0TestOperators@@QAEHH@Z"); - static assert(TestOperators.opOpAssign!"%".mangleof == "??_1TestOperators@@QAEHH@Z"); - static assert(TestOperators.opOpAssign!">>".mangleof == "??_2TestOperators@@QAEHH@Z"); - static assert(TestOperators.opOpAssign!"<<".mangleof == "??_3TestOperators@@QAEHH@Z"); - static assert(TestOperators.opOpAssign!"&".mangleof == "??_4TestOperators@@QAEHH@Z"); - static assert(TestOperators.opOpAssign!"|".mangleof == "??_5TestOperators@@QAEHH@Z"); - static assert(TestOperators.opOpAssign!"^".mangleof == "??_6TestOperators@@QAEHH@Z"); - static assert(TestOperators.opCast!int.mangleof == "??BTestOperators@@QAEHXZ"); - static assert(TestOperators.opAssign.mangleof == "??4TestOperators@@QAEHH@Z"); - static assert(TestOperators.opEquals.mangleof == "??8TestOperators@@QAE_NH@Z"); - static assert(TestOperators.opIndex.mangleof == "??ATestOperators@@QAEHH@Z"); - static assert(TestOperators.opCall.mangleof == "??RTestOperators@@QAEHHM@Z"); -} -version (Win64) -{ - static assert(TestOperators.opUnary!"*".mangleof == "??DTestOperators@@QEAAHXZ"); - static assert(TestOperators.opUnary!"++".mangleof == "??ETestOperators@@QEAAHXZ"); - static assert(TestOperators.opUnary!"--".mangleof == "??FTestOperators@@QEAAHXZ"); - static assert(TestOperators.opUnary!"-".mangleof == "??GTestOperators@@QEAAHXZ"); - static assert(TestOperators.opUnary!"+".mangleof == "??HTestOperators@@QEAAHXZ"); - static assert(TestOperators.opUnary!"~".mangleof == "??STestOperators@@QEAAHXZ"); - static assert(TestOperators.opBinary!">>".mangleof == "??5TestOperators@@QEAAHH@Z"); - static assert(TestOperators.opBinary!"<<".mangleof == "??6TestOperators@@QEAAHH@Z"); - static assert(TestOperators.opBinary!"*".mangleof == "??DTestOperators@@QEAAHH@Z"); - static assert(TestOperators.opBinary!"-".mangleof == "??GTestOperators@@QEAAHH@Z"); - static assert(TestOperators.opBinary!"+".mangleof == "??HTestOperators@@QEAAHH@Z"); - static assert(TestOperators.opBinary!"&".mangleof == "??ITestOperators@@QEAAHH@Z"); - static assert(TestOperators.opBinary!"/".mangleof == "??KTestOperators@@QEAAHH@Z"); - static assert(TestOperators.opBinary!"%".mangleof == "??LTestOperators@@QEAAHH@Z"); - static assert(TestOperators.opBinary!"^".mangleof == "??TTestOperators@@QEAAHH@Z"); - static assert(TestOperators.opBinary!"|".mangleof == "??UTestOperators@@QEAAHH@Z"); - static assert(TestOperators.opOpAssign!"*".mangleof == "??XTestOperators@@QEAAHH@Z"); - static assert(TestOperators.opOpAssign!"+".mangleof == "??YTestOperators@@QEAAHH@Z"); - static assert(TestOperators.opOpAssign!"-".mangleof == "??ZTestOperators@@QEAAHH@Z"); - static assert(TestOperators.opOpAssign!"/".mangleof == "??_0TestOperators@@QEAAHH@Z"); - static assert(TestOperators.opOpAssign!"%".mangleof == "??_1TestOperators@@QEAAHH@Z"); - static assert(TestOperators.opOpAssign!">>".mangleof == "??_2TestOperators@@QEAAHH@Z"); - static assert(TestOperators.opOpAssign!"<<".mangleof == "??_3TestOperators@@QEAAHH@Z"); - static assert(TestOperators.opOpAssign!"&".mangleof == "??_4TestOperators@@QEAAHH@Z"); - static assert(TestOperators.opOpAssign!"|".mangleof == "??_5TestOperators@@QEAAHH@Z"); - static assert(TestOperators.opOpAssign!"^".mangleof == "??_6TestOperators@@QEAAHH@Z"); - static assert(TestOperators.opCast!int.mangleof == "??BTestOperators@@QEAAHXZ"); - static assert(TestOperators.opAssign.mangleof == "??4TestOperators@@QEAAHH@Z"); - static assert(TestOperators.opEquals.mangleof == "??8TestOperators@@QEAA_NH@Z"); - static assert(TestOperators.opIndex.mangleof == "??ATestOperators@@QEAAHH@Z"); - static assert(TestOperators.opCall.mangleof == "??RTestOperators@@QEAAHHM@Z"); +version (CppMangle_MSVC) +{ + version (Win32) + { + static assert(TestOperators.opUnary!"*".mangleof == "??DTestOperators@@QAEHXZ"); + static assert(TestOperators.opUnary!"++".mangleof == "??ETestOperators@@QAEHXZ"); + static assert(TestOperators.opUnary!"--".mangleof == "??FTestOperators@@QAEHXZ"); + static assert(TestOperators.opUnary!"-".mangleof == "??GTestOperators@@QAEHXZ"); + static assert(TestOperators.opUnary!"+".mangleof == "??HTestOperators@@QAEHXZ"); + static assert(TestOperators.opUnary!"~".mangleof == "??STestOperators@@QAEHXZ"); + static assert(TestOperators.opBinary!">>".mangleof == "??5TestOperators@@QAEHH@Z"); + static assert(TestOperators.opBinary!"<<".mangleof == "??6TestOperators@@QAEHH@Z"); + static assert(TestOperators.opBinary!"*".mangleof == "??DTestOperators@@QAEHH@Z"); + static assert(TestOperators.opBinary!"-".mangleof == "??GTestOperators@@QAEHH@Z"); + static assert(TestOperators.opBinary!"+".mangleof == "??HTestOperators@@QAEHH@Z"); + static assert(TestOperators.opBinary!"&".mangleof == "??ITestOperators@@QAEHH@Z"); + static assert(TestOperators.opBinary!"/".mangleof == "??KTestOperators@@QAEHH@Z"); + static assert(TestOperators.opBinary!"%".mangleof == "??LTestOperators@@QAEHH@Z"); + static assert(TestOperators.opBinary!"^".mangleof == "??TTestOperators@@QAEHH@Z"); + static assert(TestOperators.opBinary!"|".mangleof == "??UTestOperators@@QAEHH@Z"); + static assert(TestOperators.opOpAssign!"*".mangleof == "??XTestOperators@@QAEHH@Z"); + static assert(TestOperators.opOpAssign!"+".mangleof == "??YTestOperators@@QAEHH@Z"); + static assert(TestOperators.opOpAssign!"-".mangleof == "??ZTestOperators@@QAEHH@Z"); + static assert(TestOperators.opOpAssign!"/".mangleof == "??_0TestOperators@@QAEHH@Z"); + static assert(TestOperators.opOpAssign!"%".mangleof == "??_1TestOperators@@QAEHH@Z"); + static assert(TestOperators.opOpAssign!">>".mangleof == "??_2TestOperators@@QAEHH@Z"); + static assert(TestOperators.opOpAssign!"<<".mangleof == "??_3TestOperators@@QAEHH@Z"); + static assert(TestOperators.opOpAssign!"&".mangleof == "??_4TestOperators@@QAEHH@Z"); + static assert(TestOperators.opOpAssign!"|".mangleof == "??_5TestOperators@@QAEHH@Z"); + static assert(TestOperators.opOpAssign!"^".mangleof == "??_6TestOperators@@QAEHH@Z"); + static assert(TestOperators.opCast!int.mangleof == "??BTestOperators@@QAEHXZ"); + static assert(TestOperators.opAssign.mangleof == "??4TestOperators@@QAEHH@Z"); + static assert(TestOperators.opEquals.mangleof == "??8TestOperators@@QAE_NH@Z"); + static assert(TestOperators.opIndex.mangleof == "??ATestOperators@@QAEHH@Z"); + static assert(TestOperators.opCall.mangleof == "??RTestOperators@@QAEHHM@Z"); + } + version (Win64) + { + static assert(TestOperators.opUnary!"*".mangleof == "??DTestOperators@@QEAAHXZ"); + static assert(TestOperators.opUnary!"++".mangleof == "??ETestOperators@@QEAAHXZ"); + static assert(TestOperators.opUnary!"--".mangleof == "??FTestOperators@@QEAAHXZ"); + static assert(TestOperators.opUnary!"-".mangleof == "??GTestOperators@@QEAAHXZ"); + static assert(TestOperators.opUnary!"+".mangleof == "??HTestOperators@@QEAAHXZ"); + static assert(TestOperators.opUnary!"~".mangleof == "??STestOperators@@QEAAHXZ"); + static assert(TestOperators.opBinary!">>".mangleof == "??5TestOperators@@QEAAHH@Z"); + static assert(TestOperators.opBinary!"<<".mangleof == "??6TestOperators@@QEAAHH@Z"); + static assert(TestOperators.opBinary!"*".mangleof == "??DTestOperators@@QEAAHH@Z"); + static assert(TestOperators.opBinary!"-".mangleof == "??GTestOperators@@QEAAHH@Z"); + static assert(TestOperators.opBinary!"+".mangleof == "??HTestOperators@@QEAAHH@Z"); + static assert(TestOperators.opBinary!"&".mangleof == "??ITestOperators@@QEAAHH@Z"); + static assert(TestOperators.opBinary!"/".mangleof == "??KTestOperators@@QEAAHH@Z"); + static assert(TestOperators.opBinary!"%".mangleof == "??LTestOperators@@QEAAHH@Z"); + static assert(TestOperators.opBinary!"^".mangleof == "??TTestOperators@@QEAAHH@Z"); + static assert(TestOperators.opBinary!"|".mangleof == "??UTestOperators@@QEAAHH@Z"); + static assert(TestOperators.opOpAssign!"*".mangleof == "??XTestOperators@@QEAAHH@Z"); + static assert(TestOperators.opOpAssign!"+".mangleof == "??YTestOperators@@QEAAHH@Z"); + static assert(TestOperators.opOpAssign!"-".mangleof == "??ZTestOperators@@QEAAHH@Z"); + static assert(TestOperators.opOpAssign!"/".mangleof == "??_0TestOperators@@QEAAHH@Z"); + static assert(TestOperators.opOpAssign!"%".mangleof == "??_1TestOperators@@QEAAHH@Z"); + static assert(TestOperators.opOpAssign!">>".mangleof == "??_2TestOperators@@QEAAHH@Z"); + static assert(TestOperators.opOpAssign!"<<".mangleof == "??_3TestOperators@@QEAAHH@Z"); + static assert(TestOperators.opOpAssign!"&".mangleof == "??_4TestOperators@@QEAAHH@Z"); + static assert(TestOperators.opOpAssign!"|".mangleof == "??_5TestOperators@@QEAAHH@Z"); + static assert(TestOperators.opOpAssign!"^".mangleof == "??_6TestOperators@@QEAAHH@Z"); + static assert(TestOperators.opCast!int.mangleof == "??BTestOperators@@QEAAHXZ"); + static assert(TestOperators.opAssign.mangleof == "??4TestOperators@@QEAAHH@Z"); + static assert(TestOperators.opEquals.mangleof == "??8TestOperators@@QEAA_NH@Z"); + static assert(TestOperators.opIndex.mangleof == "??ATestOperators@@QEAAHH@Z"); + static assert(TestOperators.opCall.mangleof == "??RTestOperators@@QEAAHHM@Z"); + } } import cppmangle2; @@ -839,14 +863,14 @@ extern(C++, `Namespace18922`) void func18922_3(Struct18922) {} } -version (Posix) +version (CppMangle_Itanium) { static assert(func18922.mangleof == "_ZN14Namespace189229func18922ENS_11Struct18922E"); static assert(func18922_1.mangleof == "_ZN14Namespace1892211func18922_1ENS_11Struct18922E"); static assert(func18922_2.mangleof == "_ZN14Namespace1892211func18922_2ENS_11Struct18922E"); static assert(func18922_3.mangleof == "_ZN14Namespace1892211func18922_3ENS_11Struct18922E"); } -else version(Windows) +else version (CppMangle_MSVC) { static assert(func18922.mangleof == "?func18922@Namespace18922@@YAXUStruct18922@1@@Z"); static assert(func18922_1.mangleof == "?func18922_1@Namespace18922@@YAXUStruct18922@1@@Z"); @@ -858,7 +882,7 @@ else version(Windows) // https://issues.dlang.org/show_bug.cgi?id=18957 // extern(C++) doesn't mangle 'std' correctly on posix systems -version (Posix) +version (CppMangle_Itanium) { // https://godbolt.org/z/C5T2LQ /+ @@ -881,7 +905,7 @@ extern(C++) struct test19043(T) {} extern(C++) void test19043a(test19043!(const(char)) a) {} extern(C++) void test19043b(T)(T a) {} -version(Windows) +version (CppMangle_MSVC) { static assert(test19043a.mangleof == "?test19043a@@YAXU?$test19043@$$CBD@@@Z"); static assert(test19043b!(test19043!(const(char))).mangleof == @@ -890,7 +914,7 @@ version(Windows) // https://issues.dlang.org/show_bug.cgi?id=16479 // Missing substitution while mangling C++ template parameter for functions -version (Posix) extern (C++) +version (CppMangle_Itanium) extern (C++) { // Make sure aliases are still resolved alias Alias16479 = int; @@ -1084,15 +1108,18 @@ extern(C++, (AliasSeq!(Tup, "yay"))) { void test19278_4(); } -version(Win64) +version (CppMangle_MSVC) { - static assert(test19278.mangleof == "?test19278@helloworld@@YAXXZ"); - static assert(test19278_2.mangleof == "?test19278_2@lookup@@YAXXZ"); - static assert(test19278_3.mangleof == "?test19278_3@world@hello@@YAXXZ"); - static assert(test19278_4.mangleof == "?test19278_4@yay@world@hello@@YAXXZ"); - static assert(test19278_var.mangleof == "?test19278_var@world@hello@@3_KA"); + version (Win64) + { + static assert(test19278.mangleof == "?test19278@helloworld@@YAXXZ"); + static assert(test19278_2.mangleof == "?test19278_2@lookup@@YAXXZ"); + static assert(test19278_3.mangleof == "?test19278_3@world@hello@@YAXXZ"); + static assert(test19278_4.mangleof == "?test19278_4@yay@world@hello@@YAXXZ"); + static assert(test19278_var.mangleof == "?test19278_var@world@hello@@3_KA"); + } } -else version(Posix) +else version (CppMangle_Itanium) { static assert(test19278.mangleof == "_ZN10helloworld9test19278Ev"); static assert(test19278_2.mangleof == "_ZN6lookup11test19278_2Ev"); @@ -1105,23 +1132,26 @@ else version(Posix) // https://issues.dlang.org/show_bug.cgi?id=18958 // Issue 18958 - extern(C++) wchar, dchar mangling not correct -version(Posix) +version (Posix) enum __c_wchar_t : dchar; -else version(Windows) +else version (Windows) enum __c_wchar_t : wchar; alias wchar_t = __c_wchar_t; extern (C++) void test_char_mangling(char, wchar, dchar, wchar_t); -version (Posix) +version (CppMangle_Itanium) { static assert(test_char_mangling.mangleof == "_Z18test_char_manglingcDsDiw"); } -version (Win64) +version (CppMangle_MSVC) { - static assert(test_char_mangling.mangleof == "?test_char_mangling@@YAXD_S_U_W@Z"); + version (Win64) + { + static assert(test_char_mangling.mangleof == "?test_char_mangling@@YAXD_S_U_W@Z"); + } } // https://github.com/dlang/dmd/pull/10021/files#r294055424 -version (Posix) +version (CppMangle_Itanium) { extern(C++, PR10021_NS) struct PR10021_Struct(T){} extern(C++) void PR10021_fun(int i)(PR10021_Struct!int); @@ -1129,7 +1159,7 @@ version (Posix) } // https://github.com/dlang/dmd/pull/10021#discussion_r294095749 -version (Posix) +version (CppMangle_Itanium) { extern(C++, "a", "b") struct PR10021_Struct2 @@ -1142,7 +1172,7 @@ version (Posix) } /// https://issues.dlang.org/show_bug.cgi?id=20022 -version (Posix) +version (CppMangle_Itanium) { extern(C++, `ns20022`) enum Enum20022_1 { A = 1, } extern(C++) void fun20022_1(Enum20022_1); @@ -1167,7 +1197,7 @@ version (Posix) } // https://issues.dlang.org/show_bug.cgi?id=20094 -version (Posix) +version (CppMangle_Itanium) { extern(C++, "ns20094") { @@ -1180,7 +1210,7 @@ version (Posix) } // https://issues.dlang.org/show_bug.cgi?id=20223 -version (Posix) +version (CppMangle_Itanium) { extern(C++) { @@ -1206,7 +1236,7 @@ version (Posix) } // https://issues.dlang.org/show_bug.cgi?id=20224 -version (Posix) +version (CppMangle_Itanium) { extern(C++) public int test20224_1(T)(set20224!T set); // ok extern(C++) public int test20224_2(T)(ref set20224!T set); // segfault @@ -1228,7 +1258,7 @@ version (Posix) /**************************************/ -version (Posix) +version (CppMangle_Itanium) { extern (C++) struct Loc2 {}; extern (C++) class FuncDeclaration @@ -1251,7 +1281,7 @@ extern(C++, `bar`) // https://issues.dlang.org/show_bug.cgi?id=20700 // Only testing on WIn64 because the mangling includes 'E', // and the bug can be tested on either platform -version (Win64) extern(C++) +version (CppMangle_MSVC) version (Win64) extern(C++) { void test20700_1(Struct20700); extern(C++, class) struct Struct20700 {} @@ -1285,12 +1315,15 @@ extern (C++) alias fpcpp = noreturn function(); int funccpp(fpcpp); - version (Posix) + version (CppMangle_Itanium) static assert(funccpp.mangleof == "_Z7funccppPFvvE"); - version (Win32) - static assert(funccpp.mangleof == "?funccpp@@YAHP6AXXZ@Z"); + version (CppMangle_MSVC) + { + version (Win32) + static assert(funccpp.mangleof == "?funccpp@@YAHP6AXXZ@Z"); - version (Win64) - static assert(funccpp.mangleof == "?funccpp@@YAHP6AXXZ@Z"); + version (Win64) + static assert(funccpp.mangleof == "?funccpp@@YAHP6AXXZ@Z"); + } } diff --git a/gcc/testsuite/gdc.test/compilable/cppmangle3.d b/gcc/testsuite/gdc.test/compilable/cppmangle3.d index 531509c..93e49c7 100644 --- a/gcc/testsuite/gdc.test/compilable/cppmangle3.d +++ b/gcc/testsuite/gdc.test/compilable/cppmangle3.d @@ -3,6 +3,11 @@ // https://issues.dlang.org/show_bug.cgi?id=19920 module cppmangle3; +version (CppRuntime_Clang) version = CppMangle_Itanium; +version (CppRuntime_DigitalMars) version = CppMangle_MSVC; +version (CppRuntime_Gcc) version = CppMangle_Itanium; +version (CppRuntime_Microsoft) version = CppMangle_MSVC; +version (CppRuntime_Sun) version = CppMangle_Itanium; extern(C++, "true") { @@ -23,8 +28,8 @@ extern(C++, "std", "chrono") void func(); } -version(Windows) static assert(func.mangleof == "?func@chrono@std@@YAXXZ"); -else static assert(func.mangleof == "_ZNSt6chrono4funcEv"); +version(CppMangle_MSVC) static assert(func.mangleof == "?func@chrono@std@@YAXXZ"); +else static assert(func.mangleof == "_ZNSt6chrono4funcEv"); struct Foo { diff --git a/gcc/testsuite/gdc.test/compilable/issue21203.d b/gcc/testsuite/gdc.test/compilable/issue21203.d new file mode 100644 index 0000000..30291a3 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/issue21203.d @@ -0,0 +1,210 @@ +version (CppRuntime_Clang) version = CppMangle_Itanium; +version (CppRuntime_Gcc) version = CppMangle_Itanium; +version (CppRuntime_Sun) version = CppMangle_Itanium; + +template ScopeClass(C , string name = C.stringof) +//if (is(C == class) && __traits(getLinkage, C) == "C++") +{ + //enum name = C.stringof; + enum ns = __traits(getCppNamespaces,C); + extern(C++, class) + { + extern(C++,(ns)) + { + pragma(mangle, C, name) + struct ScopeClass + { + char[__traits(classInstanceSize, C)] buffer; + //... all the things ... + } + } + } +} + +// Basic tests +extern(C++) +{ + class MyClassA {} + void funa(ScopeClass!MyClassA); // mangles MyClass + void funb(const ScopeClass!MyClassA); // mangles const MyClass + void func(ref ScopeClass!MyClassA); // mangles MyClass& + void fund(ref const ScopeClass!MyClassA); // mangles const MyClass& + void fune(const(ScopeClass!MyClassA)*); +} + +version (CppMangle_Itanium) +{ + static assert(funa.mangleof == "_Z4funa8MyClassA"); + static assert(funb.mangleof == "_Z4funb8MyClassA"); + static assert(func.mangleof == "_Z4funcR8MyClassA"); + static assert(fund.mangleof == "_Z4fundRK8MyClassA"); + static assert(fune.mangleof == "_Z4funePK8MyClassA"); +} +else version (CppRuntime_Microsoft) +{ + static assert(funa.mangleof == "?funa@@YAXVMyClassA@@@Z"); + static assert(funb.mangleof == "?funb@@YAXVMyClassA@@@Z"); + static if (size_t.sizeof == ulong.sizeof) + { + static assert(func.mangleof == "?func@@YAXAEAVMyClassA@@@Z"); + static assert(fund.mangleof == "?fund@@YAXAEBVMyClassA@@@Z"); + static assert(fune.mangleof == "?fune@@YAXPEBVMyClassA@@@Z"); + } + else + { + static assert(func.mangleof == "?func@@YAXAAVMyClassA@@@Z"); + static assert(fund.mangleof == "?fund@@YAXABVMyClassA@@@Z"); + static assert(fune.mangleof == "?fune@@YAXPBVMyClassA@@@Z"); + } +} + +//Basic tests with a namespace +extern(C++, "ns") +{ + class MyClassB {} + void funf(ScopeClass!MyClassB); // mangles MyClass + void fung(const ScopeClass!MyClassB); // mangles const MyClass + void funh(ref ScopeClass!MyClassB); // mangles MyClass& + void funi(ref const ScopeClass!MyClassB); // mangles const MyClass& + void funj(const(ScopeClass!MyClassB)*); +} + +version (CppMangle_Itanium) +{ + static assert(funf.mangleof == "_ZN2ns4funfENS_8MyClassBE"); + static assert(fung.mangleof == "_ZN2ns4fungENS_8MyClassBE"); + static assert(funh.mangleof == "_ZN2ns4funhERNS_8MyClassBE"); + static assert(funi.mangleof == "_ZN2ns4funiERKNS_8MyClassBE"); + static assert(funj.mangleof == "_ZN2ns4funjEPKNS_8MyClassBE"); +} +else version (CppRuntime_Microsoft) +{ + static assert(funf.mangleof == "?funf@ns@@YAXVMyClassB@1@@Z"); + static assert(fung.mangleof == "?fung@ns@@YAXVMyClassB@1@@Z"); + static if (size_t.sizeof == ulong.sizeof) + { + static assert(funh.mangleof == "?funh@ns@@YAXAEAVMyClassB@1@@Z"); + static assert(funi.mangleof == "?funi@ns@@YAXAEBVMyClassB@1@@Z"); + static assert(funj.mangleof == "?funj@ns@@YAXPEBVMyClassB@1@@Z"); + } + else + { + static assert(funh.mangleof == "?funh@ns@@YAXAAVMyClassB@1@@Z"); + static assert(funi.mangleof == "?funi@ns@@YAXABVMyClassB@1@@Z"); + static assert(funj.mangleof == "?funj@ns@@YAXPBVMyClassB@1@@Z"); + } +} + +//Templates +extern(C++) +{ + void funTempl(T)(); + class MyClassC {} + alias funTemplA = funTempl!(ScopeClass!MyClassC); + alias funTemplB = funTempl!(const ScopeClass!MyClassC); + alias funTemplC = funTempl!(const(ScopeClass!MyClassC)*); + // N.B funTempl!([const] ref ScopeClass!MyClassC) is not permissable in D +} +version (CppMangle_Itanium) +{ + static assert(funTemplA.mangleof == "_Z8funTemplI8MyClassCEvv"); + static assert(funTemplB.mangleof == "_Z8funTemplIK8MyClassCEvv"); + static assert(funTemplC.mangleof == "_Z8funTemplIPK8MyClassCEvv"); +} +else version (CppRuntime_Microsoft) +{ + static assert(funTemplA.mangleof == "??$funTempl@VMyClassC@@@@YAXXZ"); + static assert(funTemplB.mangleof == "??$funTempl@$$CBVMyClassC@@@@YAXXZ"); + static if (size_t.sizeof == ulong.sizeof) + static assert(funTemplC.mangleof == "??$funTempl@PEBVMyClassC@@@@YAXXZ"); + else + static assert(funTemplC.mangleof == "??$funTempl@PBVMyClassC@@@@YAXXZ"); +} + +template _function(F) +{ +extern(C++, "std") +{ + extern(C++, struct) + pragma(mangle, "function") + class _function + { + } +} +} +template FunctionOf(F) +{ + F f; + alias FunctionOf = typeof(*f); +} +extern(C++) void funk(ScopeClass!(_function!(FunctionOf!(void function(int))),"function") a ){ } + +version (CppMangle_Itanium) +{ + static assert(funk.mangleof == "_Z4funkSt8functionIFviEE"); +} +else version (CppRuntime_Microsoft) +{ + static assert(funk.mangleof == "?funk@@YAXV?$function@$$A6AXH@Z@std@@@Z"); +} + +extern(C++, "ns") +{ + pragma(mangle, "function") + class _function2 + { + public final void test(); + } +} + +version (CppMangle_Itanium) +{ + static assert(_function2.test.mangleof == "_ZN2ns8function4testEv"); +} +else version (CppRuntime_Microsoft) +{ + static if (size_t.sizeof == ulong.sizeof) + static assert(_function2.test.mangleof == "?test@function@ns@@QEAAXXZ"); + else + static assert(_function2.test.mangleof == "?test@function@ns@@QAEXXZ"); +} + +extern(C++, "ns") +{ + template _function3(T) + { + pragma(mangle, _function3, "function") + class _function3 + { + public final void test(); + } + } +} + +version (CppMangle_Itanium) +{ + static assert(_function3!(int).test.mangleof == "_ZN2ns8functionIiE4testEv"); +} +else version (CppRuntime_Microsoft) +{ + static if (size_t.sizeof == ulong.sizeof) + static assert(_function3!(int).test.mangleof == "?test@?$function@H@ns@@QEAAXXZ"); + else + static assert(_function3!(int).test.mangleof == "?test@?$function@H@ns@@QAEXXZ"); +} + +extern(C++) +{ + struct Foo {} + pragma(mangle, Foo) struct Foo_Doppelganger {} + + void funl(Foo_Doppelganger f); +} +version (CppMangle_Itanium) +{ + static assert(funl.mangleof == "_Z4funl3Foo"); +} +else version (CppRuntime_Microsoft) +{ + static assert(funl.mangleof == "?funl@@YAXUFoo@@@Z"); +} diff --git a/gcc/testsuite/gdc.test/compilable/issue21340.d b/gcc/testsuite/gdc.test/compilable/issue21340.d new file mode 100644 index 0000000..22eda6e --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/issue21340.d @@ -0,0 +1,38 @@ +version (CppRuntime_Clang) version = CppMangle_Itanium; +version (CppRuntime_Gcc) version = CppMangle_Itanium; +version (CppRuntime_Sun) version = CppMangle_Itanium; + +template ScopeClass(C) +if (is(C == class) && __traits(getLinkage, C) == "C++") +{ + + extern(C++, class) + extern(C++, __traits(getCppNamespaces,C)) + extern(C++, (ns)) + class ScopeClass { } +} +extern(C++) class Foo {} +extern(C++) void test(ScopeClass!Foo) +{ +} +version(CppMangle_Itanium) +{ + static assert (test.mangleof == "_Z4testP10ScopeClassIP3FooE"); +} +else version (CppRuntime_Microsoft) +{ + version (Win32) + { + static assert (test.mangleof == "?test@@YAXPAV?$ScopeClass@PAVFoo@@@@@Z"); + } + version (Win64) + { + static assert (test.mangleof == "?test@@YAXPEAV?$ScopeClass@PEAVFoo@@@@@Z"); + } +} +alias AliasSeq(T...) = T; +alias ns = AliasSeq!(); +immutable ns2 = AliasSeq!(); +extern(C++,(ns)) class Bar {} +extern(C++,) class Baz {} +extern(C++, (ns2)) class Quux {} diff --git a/gcc/testsuite/gdc.test/compilable/test10028.d b/gcc/testsuite/gdc.test/compilable/test10028.d new file mode 100644 index 0000000..4dc5523 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/test10028.d @@ -0,0 +1,7 @@ +enum E:char[4]{ str = "abcd" } +enum x = { + int[char[4]] aa; + aa[E.str] = 1; + foreach(key,val; aa) {} + return aa["abcd"]; +}(); diff --git a/gcc/testsuite/gdc.test/compilable/test20236.d b/gcc/testsuite/gdc.test/compilable/test20236.d new file mode 100644 index 0000000..d50c874 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/test20236.d @@ -0,0 +1,22 @@ +// https://issues.dlang.org/show_bug.cgi?id=20236 + +/* +TEST_OUTPUT: +--- +--- +*/ + +struct X +{ + alias y this; + deprecated int y() { return 5; } + int x() { return 5; } +} + +void main() +{ + static void func(int) {} + with(X.init) { + func(x); + } +} diff --git a/gcc/testsuite/gdc.test/compilable/test20860.d b/gcc/testsuite/gdc.test/compilable/test20860.d new file mode 100644 index 0000000..78b9ddd --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/test20860.d @@ -0,0 +1,16 @@ +// https://issues.dlang.org/show_bug.cgi?id=20860 + +struct A +{ + this(int a) {} + /// + void opDispatch(string methodName, Params...)(Params params) { + } + + ~this() {} +} + +void main() +{ + A(3).test(); +} diff --git a/gcc/testsuite/gdc.test/compilable/test21073.d b/gcc/testsuite/gdc.test/compilable/test21073.d new file mode 100644 index 0000000..47d7881 --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/test21073.d @@ -0,0 +1,16 @@ +// https://issues.dlang.org/show_bug.cgi?id=21073 + +class C +{ + auto internal() const + { + return 5; + } + alias internal this; +} + +void main() pure +{ + const c = new C; + auto r = cast(C)c; +} diff --git a/gcc/testsuite/gdc.test/compilable/test21414.d b/gcc/testsuite/gdc.test/compilable/test21414.d new file mode 100644 index 0000000..e8a201c --- /dev/null +++ b/gcc/testsuite/gdc.test/compilable/test21414.d @@ -0,0 +1,13 @@ +// https://issues.dlang.org/show_bug.cgi?id=21414 + +struct State +{ + string s; + + immutable this(string s) + { + this.s = s; + } +} + +immutable rootState = new immutable State("b"); diff --git a/gcc/testsuite/gdc.test/fail_compilation/b15875.d b/gcc/testsuite/gdc.test/fail_compilation/b15875.d index daa79b7..15f362b 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/b15875.d +++ b/gcc/testsuite/gdc.test/fail_compilation/b15875.d @@ -1,6 +1,6 @@ /* TEST_OUTPUT: --- -fail_compilation/b15875.d(9): Error: circular reference to variable `a` +fail_compilation/b15875.d(9): Error: undefined identifier `a` fail_compilation/b15875.d(10): Error: circular reference to `b15875.f` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail116.d b/gcc/testsuite/gdc.test/fail_compilation/fail116.d index 66a01c6..64f225d 100644 --- a/gcc/testsuite/gdc.test/fail_compilation/fail116.d +++ b/gcc/testsuite/gdc.test/fail_compilation/fail116.d @@ -1,7 +1,7 @@ /* TEST_OUTPUT: --- -fail_compilation/fail116.d(11): Error: circular `typeof` definition +fail_compilation/fail116.d(11): Error: undefined identifier `x` fail_compilation/fail116.d(16): Error: template instance `square!1.2` does not match template declaration `square(_error_ x)` --- */ diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail20616.d b/gcc/testsuite/gdc.test/fail_compilation/fail20616.d new file mode 100644 index 0000000..0f76e31 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/fail20616.d @@ -0,0 +1,26 @@ +/* +TEST_OUTPUT: +--- +fail_compilation/fail20616.d(16): Error: undefined identifier `$` +fail_compilation/fail20616.d(16): Aggregate declaration 'X()' does not define 'opDollar' +fail_compilation/fail20616.d(18): Error: undefined identifier `$` +fail_compilation/fail20616.d(18): Aggregate declaration 'b' does not define 'opDollar' +--- +*/ +module fail20616; + +void g() { + struct X { + auto opSlice(size_t a, size_t b) { return ""; } + } + auto x = X()[0 .. $]; + auto b = X(); + auto c = b[0 .. $ - 1]; + auto v = [1, 2, 3]; + auto d = v[$.. $]; +} + +int main() { + g(); + return 0; +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail22529.d b/gcc/testsuite/gdc.test/fail_compilation/fail22529.d new file mode 100644 index 0000000..3bec3c0f --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/fail22529.d @@ -0,0 +1,14 @@ +// https://issues.dlang.org/show_bug.cgi?id=22529 + +/* +TEST_OUTPUT: +--- +fail_compilation/fail22529.d(13): Error: found `return` when expecting `;` following statement +--- +*/ + +void main() +{ + foo() + return; +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/fail22570.d b/gcc/testsuite/gdc.test/fail_compilation/fail22570.d new file mode 100644 index 0000000..cb8c286 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/fail22570.d @@ -0,0 +1,21 @@ +// https://issues.dlang.org/show_bug.cgi?id=22570 + +/* +TEST_OUTPUT: +--- +fail_compilation/fail22570.d(19): Error: more initializers than fields (1) of `S` +fail_compilation/fail22570.d(20): Error: more initializers than fields (1) of `S` +--- +*/ + +struct S +{ + Object o1; +} + +void main() @safe +{ + S[] s; + s = [S(null, null)]; + s ~= S(null, null); +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/ice22516.d b/gcc/testsuite/gdc.test/fail_compilation/ice22516.d new file mode 100644 index 0000000..1c71f38 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/ice22516.d @@ -0,0 +1,21 @@ +/++ +https://issues.dlang.org/show_bug.cgi?id=22516 + +TEST_OUTPUT: +--- +fail_compilation/ice22516.d(18): Error: undefined identifier `X` +--- ++/ + +struct Data +{ + void function() eval; + +} + +struct Builtins +{ + X x; + + Data myData = { (){} }; +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/test22574.d b/gcc/testsuite/gdc.test/fail_compilation/test22574.d new file mode 100644 index 0000000..2a7b884 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/test22574.d @@ -0,0 +1,12 @@ +//https://issues.dlang.org/show_bug.cgi?id=22574 +/* +TEST_OUTPUT: +--- +fail_compilation/test22574.d(100): Error: undefined identifier `x` +--- +*/ +#line 100 +template test(x* x) +{ + +} diff --git a/gcc/testsuite/gdc.test/fail_compilation/test_switch_error.d b/gcc/testsuite/gdc.test/fail_compilation/test_switch_error.d new file mode 100644 index 0000000..a0d1d12 --- /dev/null +++ b/gcc/testsuite/gdc.test/fail_compilation/test_switch_error.d @@ -0,0 +1,101 @@ +/++ +https://issues.dlang.org/show_bug.cgi?id=22514 +TEST_OUTPUT: +--- +fail_compilation/test_switch_error.d(13): Error: undefined identifier `doesNotExist` +fail_compilation/test_switch_error.d(16): Error: undefined identifier `alsoDoesNotExits` +fail_compilation/test_switch_error.d(19): Error: duplicate `case 2` in `switch` statement +--- +++/ + +void test1() +{ + switch (doesNotExist) + { + case 1: + alsoDoesNotExits(); + break; + case 2: break; + case 2: break; + } +} + +/++ +TEST_OUTPUT: +--- +fail_compilation/test_switch_error.d(105): Error: undefined identifier `doesNotExist` +--- +++/ +#line 100 + +enum foo = 1; + +void test2() +{ + switch (doesNotExist) + { + case foo: break; + } +} + +/++ +TEST_OUTPUT: +--- +fail_compilation/test_switch_error.d(206): Error: undefined identifier `a` +fail_compilation/test_switch_error.d(207): Error: undefined identifier `b` +--- +++/ +#line 200 + +void test3() +{ + + switch (1) + { + case a: break; + case b: break; + } +} + +/++ +TEST_OUTPUT: +--- +fail_compilation/test_switch_error.d(303): Error: undefined identifier `doesNotExits` +--- +++/ +#line 300 + +void test4() +{ + auto foo = doesNotExits(); + switch (1) + { + case foo: break; + case foo: break; + } +} + +/++ +TEST_OUTPUT: +--- +fail_compilation/test_switch_error.d(405): Error: `case` variables have to be `const` or `immutable` +fail_compilation/test_switch_error.d(412): Error: `case` variables not allowed in `final switch` statements +--- +++/ +#line 400 + +void test5(int i) +{ + switch (i) + { + case i: break; + default: break; + } + + const int j = i; + final switch (i) + { + case j: break; + + } +} diff --git a/gcc/testsuite/gdc.test/runnable/interpret.d b/gcc/testsuite/gdc.test/runnable/interpret.d index 989fb2e..d8059d3 100644 --- a/gcc/testsuite/gdc.test/runnable/interpret.d +++ b/gcc/testsuite/gdc.test/runnable/interpret.d @@ -3661,6 +3661,28 @@ void test20133() } /************************************************/ +// https://issues.dlang.org/show_bug.cgi?id=22530 + +class D22530 { } + +class C22530 +{ + D22530 y = new D22530; + alias y this; +} + +void test22530() +{ + // fixed + static assert(cast(D22530)(new C22530) is null); + static assert((1 ? cast(D22530)(new C22530) : new D22530) is null); + + // runtime version already works + assert(cast(D22530)(new C22530) is null); + assert((1 ? cast(D22530)(new C22530) : new D22530) is null); +} + +/************************************************/ int main() { @@ -3789,6 +3811,7 @@ int main() test20400(); test21878(); test20133(); + test22530(); printf("Success\n"); return 0; diff --git a/gcc/testsuite/gdc.test/runnable/test16579.d b/gcc/testsuite/gdc.test/runnable/test16579.d new file mode 100644 index 0000000..e42ead9 --- /dev/null +++ b/gcc/testsuite/gdc.test/runnable/test16579.d @@ -0,0 +1,57 @@ +// REQUIRED_ARGS: -unittest +// PERMUTE_ARGS: +// https://issues.dlang.org/show_bug.cgi?id=16579 + +struct Thing +{ + enum Instance = Thing(); + int a = 42; + + void iter() + { + assert(this.a == 42); + } +} + +void main() +{ + return Thing.Instance.iter; // Added 'return' +} + +// From https://issues.dlang.org/show_bug.cgi?id=16576 + +alias a = test2!(); +alias b = test3!(); + + +template test2() +{ + struct Thing{ + static enum Instance = Thing([0, 1, 2, 3]); + int[] array; + void iter(in string str) const{ + foreach(j, tup; this.array) assert(tup == j); + assert(this.array && this.array.length == 4); + } + } + unittest{ + auto test(in string str){return Thing.Instance.iter(str);} + test("?"); + } +} + +template test3() +{ + struct Thing{ + static enum Instance = Thing([0, 1, 2, 3]); + int[] array; + void iter() const{ + foreach(j, tup; this.array) assert(tup == j); + assert(this.array && this.array.length == 4); + } + } + unittest{ + auto test(){return Thing.Instance.iter();} + test(); + } +} diff --git a/gcc/testsuite/gdc.test/runnable/test18054.d b/gcc/testsuite/gdc.test/runnable/test18054.d new file mode 100644 index 0000000..610dff1 --- /dev/null +++ b/gcc/testsuite/gdc.test/runnable/test18054.d @@ -0,0 +1,41 @@ +/+ +REQUIRED_ARGS: -d +RUN_OUTPUT: +--- +float: 1 == 1 +double: 1 == 1 +real: 1 == 1 +ifloat: 1 == 1 +idouble: 1 == 1 +ireal: 1 == 1 +cfloat: 1 == 1 +cdouble: 1 == 1 +creal: 1 == 1 +--- ++/ + +import core.stdc.stdio : printf; + +void test(T, string lit)() +{ + T d = mixin(lit); + bool runtime = cast(bool) d; + bool folded = cast(bool) mixin(lit); + + printf((T.stringof ~ ": %d == %d\n\0").ptr, runtime, folded); +} + +void main() +{ + test!(float, "0.5f"); + test!(double, "0.5" ); + test!(real, "0.5L"); + + test!(ifloat, "0.5i"); + test!(idouble, "0.5i"); + test!(ireal, "0.5i"); + + test!(cfloat, "0.3 + 0.5i"); + test!(cdouble, "0.3 + 0.5i"); + test!(creal, "0.3 + 0.5i"); +} diff --git a/gcc/testsuite/gdc.test/runnable_cxx/cppa.d b/gcc/testsuite/gdc.test/runnable_cxx/cppa.d index e6db3c4..c60d6c6 100644 --- a/gcc/testsuite/gdc.test/runnable_cxx/cppa.d +++ b/gcc/testsuite/gdc.test/runnable_cxx/cppa.d @@ -442,28 +442,54 @@ void test13161() version (linux) { - extern(C++, __gnu_cxx) + static if (__traits(getTargetInfo, "cppStd") < 201703) { - struct new_allocator(T) + // See note on std::allocator below. + extern(C++, __gnu_cxx) { - alias size_type = size_t; - static if (is(T : char)) - void deallocate(T*, size_type) { } - else - void deallocate(T*, size_type); + struct new_allocator(T) + { + alias size_type = size_t; + static if (is(T : char)) + void deallocate(T*, size_type) { } + else + void deallocate(T*, size_type); + } } } } extern (C++, std) { + version (linux) + { + static if (__traits(getTargetInfo, "cppStd") >= 201703) + { + // std::allocator no longer derives from __gnu_cxx::new_allocator, + // it derives from std::__new_allocator instead. + struct __new_allocator(T) + { + alias size_type = size_t; + static if (is(T : char)) + void deallocate(T*, size_type) { } + else + void deallocate(T*, size_type); + } + } + } + extern (C++, class) struct allocator(T) { version (linux) { alias size_type = size_t; void deallocate(T* p, size_type sz) - { (cast(__gnu_cxx.new_allocator!T*)&this).deallocate(p, sz); } + { + static if (__traits(getTargetInfo, "cppStd") >= 201703) + (cast(std.__new_allocator!T*)&this).deallocate(p, sz); + else + (cast(__gnu_cxx.new_allocator!T*)&this).deallocate(p, sz); + } } } @@ -476,12 +502,21 @@ extern (C++, std) { } - // https://gcc.gnu.org/onlinedocs/libstdc++/manual/using_dual_abi.html - version (none) + version (CppRuntime_Gcc) { - extern (C++, __cxx11) + // https://gcc.gnu.org/onlinedocs/libstdc++/manual/using_dual_abi.html + static if (__traits(getTargetInfo, "cppStd") >= 201103) + { + extern (C++, __cxx11) + { + struct basic_string(T, C = char_traits!T, A = allocator!T) + { + } + } + } + else { - struct basic_string(T, C = char_traits!T, A = allocator!T) + extern (C++, class) struct basic_string(T, C = char_traits!T, A = allocator!T) { } } diff --git a/gcc/testsuite/gdc.test/runnable_cxx/extra-files/cppb.cpp b/gcc/testsuite/gdc.test/runnable_cxx/extra-files/cppb.cpp index ab1ea0a5..ea4fb1c 100644 --- a/gcc/testsuite/gdc.test/runnable_cxx/extra-files/cppb.cpp +++ b/gcc/testsuite/gdc.test/runnable_cxx/extra-files/cppb.cpp @@ -1,36 +1,3 @@ -/* -GCC 5.1 introduced new implementations of std::string and std::list: - -https://gcc.gnu.org/onlinedocs/libstdc++/manual/using_dual_abi.html - -This causes e.g. std::string to be actually defined as -std::__cxx11::string. - -On machines with GCC 5.1, this manifests as a linker error when -running the cppa.d / cppb.cpp test: - -cppa.o: In function `_D4cppa6test14FZv': -cppa.d:(.text._D4cppa6test14FZv+0x11): undefined reference to `foo14a(std::string*)' -cppa.d:(.text._D4cppa6test14FZv+0x18): undefined reference to `foo14b(std::basic_string, std::allocator >*)' -cppa.d:(.text._D4cppa6test14FZv+0x3a): undefined reference to `foo14f(std::char_traits*, std::string*, std::string*)' -cppa.o: In function `_D4cppa7testeh3FZv': -cppa.d:(.text._D4cppa7testeh3FZv+0x19): undefined reference to `throwle()' -collect2: error: ld returned 1 exit status ---- errorlevel 1 - -When the .cpp file is compiled with g++ 5.3.0, the actual function -signatures in the cppb.o object file are: - -foo14a(std::__cxx11::basic_string, std::allocator >*) -foo14b(std::__cxx11::basic_string, std::allocator >*) -foo14f(std::char_traits*, std::__cxx11::basic_string, std::allocator >*, std::__cxx11::basic_string, std::allocator >*) - -Fortunately, it is easily possible to disable the new feature -by defining _GLIBCXX_USE_CXX11_ABI as 0 before including any standard -headers. -*/ -#define _GLIBCXX_USE_CXX11_ABI 0 - #include #include #include -- cgit v1.1 From 45b768cb80930c0beeb735727349c44ec66f7dd2 Mon Sep 17 00:00:00 2001 From: Thomas Schwinge Date: Fri, 10 Dec 2021 19:08:26 +0100 Subject: testsuite: Be more informative for ICEs For example, for the two (FAIL, XFAIL) 'gcc/testsuite/lib/gcc-dg.exp:gcc-dg-test-1' cases: -FAIL: g++.dg/modules/xtreme-header-3_a.H -std=c++17 (internal compiler error) +FAIL: g++.dg/modules/xtreme-header-3_a.H -std=c++17 (internal compiler error: tree check: expected var_decl or function_decl or field_decl or type_decl or concept_decl or template_decl, have namespace_decl in get_merge_kind, at cp/module.cc:10072) -FAIL: gfortran.dg/gomp/clauses-1.f90 -O (internal compiler error) +FAIL: gfortran.dg/gomp/clauses-1.f90 -O (internal compiler error: Segmentation fault) -XFAIL: c-c++-common/goacc/kernels-decompose-ice-1.c (internal compiler error) +XFAIL: c-c++-common/goacc/kernels-decompose-ice-1.c (internal compiler error: in lower_omp_target, at omp-low.c:13147) -XFAIL: g++.dg/cpp1z/constexpr-lambda26.C -std=c++17 (internal compiler error) +XFAIL: g++.dg/cpp1z/constexpr-lambda26.C -std=c++17 (internal compiler error: in cxx_eval_constant_expression, at cp/constexpr.c:6954) That allows for more easily spotting when during development you're trading one ICE for another. gcc/testsuite/ * lib/fortran-torture.exp (fortran-torture-compile) (fortran-torture-execute): Be more informative for ICEs. * lib/gcc-defs.exp (${tool}_check_compile): Likewise. * lib/gcc-dg.exp (gcc-dg-test-1): Likewise. * lib/go-torture.exp (go-torture-compile, go-torture-execute): Likewise. --- gcc/testsuite/lib/fortran-torture.exp | 8 ++++---- gcc/testsuite/lib/gcc-defs.exp | 4 ++-- gcc/testsuite/lib/gcc-dg.exp | 6 +++--- gcc/testsuite/lib/go-torture.exp | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) (limited to 'gcc') diff --git a/gcc/testsuite/lib/fortran-torture.exp b/gcc/testsuite/lib/fortran-torture.exp index d6759aa..11d73d9 100644 --- a/gcc/testsuite/lib/fortran-torture.exp +++ b/gcc/testsuite/lib/fortran-torture.exp @@ -138,8 +138,8 @@ proc fortran-torture-compile { src option } { return } - if [string match "*internal compiler error*" $comp_output] then { - gfortran_fail $testcase "$option (internal compiler error)" + if [regexp -line -- "internal compiler error.*" $comp_output ice] then { + gfortran_fail $testcase "$option ($ice)" catch { remote_file build delete $output } return } @@ -263,8 +263,8 @@ proc fortran-torture-execute { src } { continue } - if [string match "*internal compiler error*" $comp_output] then { - gfortran_fail $testcase "$option (internal compiler error)" + if [regexp -line -- "internal compiler error.*" $comp_output ice] then { + gfortran_fail $testcase "$option ($ice)" catch { remote_file build delete $executable } continue } diff --git a/gcc/testsuite/lib/gcc-defs.exp b/gcc/testsuite/lib/gcc-defs.exp index d17308d..66df4e1 100644 --- a/gcc/testsuite/lib/gcc-defs.exp +++ b/gcc/testsuite/lib/gcc-defs.exp @@ -38,8 +38,8 @@ proc ${tool}_check_compile {testcase option objname gcc_output} { return 0 } - if [string match "*internal compiler error*" $gcc_output] then { - ${tool}_fail $testcase "$option (internal compiler error)" + if [regexp -line -- "internal compiler error.*" $gcc_output ice] then { + ${tool}_fail $testcase "$option ($ice)" return 0 } diff --git a/gcc/testsuite/lib/gcc-dg.exp b/gcc/testsuite/lib/gcc-dg.exp index 78a6c36..4640596 100644 --- a/gcc/testsuite/lib/gcc-dg.exp +++ b/gcc/testsuite/lib/gcc-dg.exp @@ -315,13 +315,13 @@ proc gcc-dg-test-1 { target_compile prog do_what extra_tool_flags } { # to avoid a second failure for excess errors. # "Error reporting routines re-entered" ICE says "Internal" rather than # "internal", so match that too. - if [string match {*[Ii]nternal compiler error*} $comp_output] { + if [regexp -line -- {[Ii]nternal compiler error.*} $comp_output ice] { upvar 2 name name if { $expect_ice == 0 } { - fail "$name (internal compiler error)" + fail "$name ($ice)" } else { # We expected an ICE and we got it. - xfail "$name (internal compiler error)" + xfail "$name ($ice)" # Prune the ICE from the output. set comp_output [prune_ices $comp_output] } diff --git a/gcc/testsuite/lib/go-torture.exp b/gcc/testsuite/lib/go-torture.exp index 28247a1..adeae36 100644 --- a/gcc/testsuite/lib/go-torture.exp +++ b/gcc/testsuite/lib/go-torture.exp @@ -88,8 +88,8 @@ proc go-torture-compile { src option } { return } - if [string match "*internal compiler error*" $comp_output] then { - go_fail $testcase "$option (internal compiler error)" + if [regexp -line -- "internal compiler error.*" $comp_output ice] then { + go_fail $testcase "$option ($ice)" catch { remote_file build delete $output } return } @@ -224,8 +224,8 @@ proc go-torture-execute { src } { continue } - if [string match "*internal compiler error*" $comp_output] then { - go_fail $testcase "$option (internal compiler error)" + if [regexp -line -- "internal compiler error.*" $comp_output ice] then { + go_fail $testcase "$option ($ice)" catch { remote_file build delete $executable } continue } -- cgit v1.1 From 06d5dcef72542baf49ac245cfde2ad7ecef0916b Mon Sep 17 00:00:00 2001 From: Marek Polacek Date: Fri, 10 Dec 2021 15:38:35 -0500 Subject: c++: Allow constexpr decltype(auto) [PR102229] My r11-2202 was trying to enforce [dcl.type.auto.deduct]/4, which says "If the placeholder-type-specifier is of the form type-constraint[opt] decltype(auto), T shall be the placeholder alone." But this made us reject 'constexpr decltype(auto)', which, after clarification from CWG, should be valid. [dcl.type.auto.deduct]/4 is supposed to be a syntactic constraint, not semantic, so it's OK that the constexpr marks the object as const. As a consequence, checking TYPE_QUALS in do_auto_deduction is too late, and we have a FIXME there anyway. So in this patch I'm attempting to detect 'const decltype(auto)' earlier. If I'm going to use TYPE_QUALS, it needs to happen before we mark the object as const due to constexpr, that is, before grokdeclarator's /* A `constexpr' specifier used in an object declaration declares the object as `const'. */ if (constexpr_p && innermost_code != cdk_function) ... Constrained decltype(auto) was a little problem, hence the TYPENAME check. But in a typename context you can't use decltype(auto) anyway, I think. PR c++/102229 gcc/cp/ChangeLog: * decl.c (check_decltype_auto): New. (grokdeclarator): Call it. * pt.c (do_auto_deduction): Don't check decltype(auto) here. gcc/testsuite/ChangeLog: * g++.dg/cpp1y/decltype-auto5.C: New test. --- gcc/cp/decl.c | 58 +++++++++++++++++++---------- gcc/cp/pt.c | 13 ------- gcc/testsuite/g++.dg/cpp1y/decltype-auto5.C | 35 +++++++++++++++++ 3 files changed, 74 insertions(+), 32 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp1y/decltype-auto5.C (limited to 'gcc') diff --git a/gcc/cp/decl.c b/gcc/cp/decl.c index 7c2048c..2e03398 100644 --- a/gcc/cp/decl.c +++ b/gcc/cp/decl.c @@ -11354,6 +11354,33 @@ name_unnamed_type (tree type, tree decl) gcc_assert (!TYPE_UNNAMED_P (type)); } +/* Check that decltype(auto) was well-formed: only plain decltype(auto) + is allowed. TYPE might contain a decltype(auto). Returns true if + there was a problem, false otherwise. */ + +static bool +check_decltype_auto (location_t loc, tree type) +{ + if (tree a = type_uses_auto (type)) + { + if (AUTO_IS_DECLTYPE (a)) + { + if (a != type) + { + error_at (loc, "%qT as type rather than plain " + "%", type); + return true; + } + else if (TYPE_QUALS (type) != TYPE_UNQUALIFIED) + { + error_at (loc, "% cannot be cv-qualified"); + return true; + } + } + } + return false; +} + /* Given declspecs and a declarator (abstract or otherwise), determine the name and type of the object declared and construct a DECL node for it. @@ -12702,25 +12729,9 @@ grokdeclarator (const cp_declarator *declarator, "allowed"); return error_mark_node; } - /* Only plain decltype(auto) is allowed. */ - if (tree a = type_uses_auto (type)) - { - if (AUTO_IS_DECLTYPE (a)) - { - if (a != type) - { - error_at (typespec_loc, "%qT as type rather than " - "plain %", type); - return error_mark_node; - } - else if (TYPE_QUALS (type) != TYPE_UNQUALIFIED) - { - error_at (typespec_loc, "% cannot be " - "cv-qualified"); - return error_mark_node; - } - } - } + + if (check_decltype_auto (typespec_loc, type)) + return error_mark_node; if (ctype == NULL_TREE && decl_context == FIELD @@ -13080,6 +13091,15 @@ grokdeclarator (const cp_declarator *declarator, id_loc = declarator ? declarator->id_loc : input_location; + if (innermost_code != cdk_function + /* Don't check this if it can be the artifical decltype(auto) + we created when building a constraint in a compound-requirement: + that the type-constraint is plain is going to be checked in + cp_parser_compound_requirement. */ + && decl_context != TYPENAME + && check_decltype_auto (id_loc, type)) + return error_mark_node; + /* A `constexpr' specifier used in an object declaration declares the object as `const'. */ if (constexpr_p && innermost_code != cdk_function) diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 42133a3..62a058d 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -29894,19 +29894,6 @@ do_auto_deduction (tree type, tree init, tree auto_node, return error_mark_node; targs = make_tree_vec (1); TREE_VEC_ELT (targs, 0) = deduced; - /* FIXME: These errors ought to be diagnosed at parse time. */ - if (type != auto_node) - { - if (complain & tf_error) - error ("%qT as type rather than plain %", type); - return error_mark_node; - } - else if (TYPE_QUALS (type) != TYPE_UNQUALIFIED) - { - if (complain & tf_error) - error ("% cannot be cv-qualified"); - return error_mark_node; - } } else { diff --git a/gcc/testsuite/g++.dg/cpp1y/decltype-auto5.C b/gcc/testsuite/g++.dg/cpp1y/decltype-auto5.C new file mode 100644 index 0000000..01cc54f --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp1y/decltype-auto5.C @@ -0,0 +1,35 @@ +// PR c++/102229 +// { dg-do compile { target c++14 } } + +struct S { + constexpr static decltype(auto) x = 42; + const constexpr static decltype(auto) y = 42; // { dg-error "cannot be cv-qualified" } + + constexpr decltype(auto) mfn1 () { return 0; } + const constexpr decltype(auto) mfn2 () { return 0; } // { dg-error "cannot be cv-qualified" } +}; + +constexpr decltype(auto) i = 42; +const constexpr decltype(auto) j = 42; // { dg-error "cannot be cv-qualified" } + +constexpr decltype(auto) fn() { return 42; } +const decltype(auto) fn2() { return 42; } // { dg-error "cannot be cv-qualified" } + +auto constexpr foo() -> const decltype(auto) // { dg-error "cannot be cv-qualified" } +{ + return 0; +} + +#if __cpp_concepts +template +concept C = true; + +constexpr C decltype(auto) x1 = 0; +const constexpr C decltype(auto) x2 = 0; // { dg-error "cannot be cv-qualified" "" { target c++20 } } + +constexpr C decltype(auto) fn3() { return 0; } +const constexpr C decltype(auto) fn4() { return 0; } // { dg-error "cannot be cv-qualified" "" { target c++20 } } +#endif + +template // { dg-error "cannot be cv-qualified" } +void g (); -- cgit v1.1 From 8a89c39be01dbafc8cd77a48339c32c814495333 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Thu, 16 Dec 2021 00:16:28 +0000 Subject: Daily bump. --- gcc/ChangeLog | 169 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/cp/ChangeLog | 18 ++++++ gcc/d/ChangeLog | 6 ++ gcc/testsuite/ChangeLog | 85 ++++++++++++++++++++++++ 5 files changed, 279 insertions(+), 1 deletion(-) (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ca2c5ae..f2bd21b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,172 @@ +2021-12-15 Iain Sandoe + + * configure: Regenerate. + +2021-12-15 Roger Sayle + + * config/nvptx/nvptx-opts.h (ptx_isa): PTX_ISA_SM75 and PTX_ISA_SM80 + ISA levels. + * config/nvptx/nvptx.opt: Add sm_75 and sm_80 to -misa. + * config/nvptx/nvptx.h (TARGET_SM75, TARGET_SM80): + New helper macros to conditionalize functionality on target ISA. + * config/nvptx/nvptx-c.c (nvptx_cpu_cpp_builtins): Add __PTX_SM__ + support for the new ISA levels. + * config/nvptx/nvptx.c (nvptx_file_start): Add support for TARGET_SM75 + and TARGET_SM80. + * config/nvptx/nvptx.md (define_c_enum "unspec"): New UNSPEC_TANH. + (define_mode_iterator HSFM): New iterator for HFmode and SFmode. + (exp2hf2): New define_insn controlled by TARGET_SM75. + (tanh2): New define_insn controlled by TARGET_SM75. + (sminhf3, smaxhf3): New define_isnns controlled by TARGET_SM80. + +2021-12-15 Tom de Vries + + * config/nvptx/nvptx-opts.h (enum ptx_version): Add PTX_VERSION_7_0. + * config/nvptx/nvptx.c (nvptx_file_start): Handle TARGET_PTX_7_0. + * config/nvptx/nvptx.h (TARGET_PTX_7_0): New macro. + * config/nvptx/nvptx.opt (ptx_version): Add 7.0. + +2021-12-15 Richard Sandiford + Tamar Christina + + PR target/103094 + * config/aarch64/aarch64.c (aarch64_short_vector_p): Return false + for structure modes, rather than ignoring the type in that case. + +2021-12-15 Tamar Christina + + PR rtl-optimization/103350 + * ree.c (add_removable_extension): Don't stop at first definition but + inspect all. + +2021-12-15 Jakub Jelinek + + PR debug/103619 + * dwarf2cfi.c (dwf_cfa_reg): Remove gcc_assert. + (operator==, operator!=): New overloaded operators. + (dwarf2out_frame_debug_adjust_cfa, dwarf2out_frame_debug_cfa_offset, + dwarf2out_frame_debug_expr): Compare vars with cfa_reg type directly + with REG rtxes rather than with dwf_cfa_reg results on those REGs. + (create_cie_data): Use stack_pointer_rtx instead of + gen_rtx_REG (Pmode, STACK_POINTER_REGNUM). + (execute_dwarf2_frame): Use hard_frame_pointer_rtx instead of + gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM). + +2021-12-15 Martin Liska + + PR target/103661 + * config/i386/i386-builtins.c (fold_builtin_cpu): Compare to 0 + as API expects that non-zero values are returned (do that + it mask == 31). + For "avx512vbmi2" argument, we return now 1 << 31, which is a + negative integer value. + +2021-12-15 Haochen Jiang + + PR target/101796 + * config/i386/predicates.md (const_vector_operand): + Add new predicate. + * config/i386/sse.md(3): + Add new define_split below. + +2021-12-15 Michael Meissner + + * config/rs6000/rs6000.md (UNSPEC_XXSPLTIDP_CONST): New unspec. + (UNSPEC_XXSPLTIW_CONST): New unspec. + (movsf_hardfloat): Add support for generating XXSPLTIDP. + (mov_hardfloat32): Likewise. + (mov_hardfloat64): Likewise. + (xxspltidp__internal): New insns. + (xxspltiw__internal): New insns. + (splitters for SF/DFmode): Add new splitters for XXSPLTIDP. + +2021-12-15 Michael Meissner + + * config/rs6000/predicates.md (easy_fp_constant): Add support for + generating XXSPLTIDP. + (vsx_prefixed_constant): Likewise. + (easy_vector_constant): Likewise. + * config/rs6000/rs6000-protos.h (constant_generates_xxspltidp): + New declaration. + * config/rs6000/rs6000.c (output_vec_const_move): Add support for + generating XXSPLTIDP. + (prefixed_xxsplti_p): Likewise. + (constant_generates_xxspltidp): New function. + * config/rs6000/rs6000.opt (-msplat-float-constant): New debug option. + +2021-12-15 Michael Meissner + + * config/rs6000/constraints.md (eP): Update comment. + * config/rs6000/predicates.md (easy_fp_constant): Add support for + generating XXSPLTIW. + (vsx_prefixed_constant): New predicate. + (easy_vector_constant): Add support for + generating XXSPLTIW. + * config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New + declaration. + (constant_generates_xxspltiw): Likewise. + * config/rs6000/rs6000.c (xxspltib_constant_p): Generate XXSPLTIW + if possible instead of XXSPLTIB and sign extending the constant. + (output_vec_const_move): Add support for XXSPLTIW. + (prefixed_xxsplti_p): New function. + (constant_generates_xxspltiw): New function. + * config/rs6000/rs6000.md (prefixed attribute): Add support to + mark XXSPLTI* instructions as being prefixed. + * config/rs6000/rs6000.opt (-msplat-word-constant): New debug + switch. + * config/rs6000/vsx.md (vsx_mov_64bit): Add support for + generating XXSPLTIW or XXSPLTIDP. + (vsx_mov_32bit): Likewise. + * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the + eP constraint. + +2021-12-15 Michael Meissner + + * config/rs6000/constraints.md (eQ): New constraint. + * config/rs6000/predicates.md (easy_fp_constant): Add support for + generating the LXVKQ instruction. + (easy_vector_constant_ieee128): New predicate. + (easy_vector_constant): Add support for generating the LXVKQ + instruction. + * config/rs6000/rs6000-protos.h (constant_generates_lxvkq): New + declaration. + * config/rs6000/rs6000.c (output_vec_const_move): Add support for + generating LXVKQ. + (constant_generates_lxvkq): New function. + * config/rs6000/rs6000.opt (-mieee128-constant): New debug + option. + * config/rs6000/vsx.md (vsx_mov_64bit): Add support for + generating LXVKQ. + (vsx_mov_32bit): Likewise. + * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the + eQ constraint. + +2021-12-15 Michael Meissner + + * config/rs6000/rs6000-protos.h (VECTOR_128BIT_BITS): New macro. + (VECTOR_128BIT_BYTES): Likewise. + (VECTOR_128BIT_HALF_WORDS): Likewise. + (VECTOR_128BIT_WORDS): Likewise. + (VECTOR_128BIT_DOUBLE_WORDS): Likewise. + (vec_const_128bit_type): New structure type. + (vec_const_128bit_to_bytes): New declaration. + * config/rs6000/rs6000.c (constant_int_to_128bit_vector): New + helper function. + (constant_fp_to_128bit_vector): New helper function. + (vec_const_128bit_to_bytes): New function. + +2021-12-15 Alexandre Oliva + + PR target/100518 + * builtins.c (try_store_by_multiple_pieces): Drop address + conversion to ptr_mode. + +2021-12-15 Alexandre Oliva + + PR middle-end/100843 + * builtins.c (try_store_by_multiple_pieces): Fail if min_len + is greater than max_len. + 2021-12-14 liuhongt PR target/103682 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index c11bfa6..4f5ebad 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20211215 +20211216 diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index c72be7d..e427701 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,21 @@ +2021-12-15 Marek Polacek + + PR c++/102229 + * decl.c (check_decltype_auto): New. + (grokdeclarator): Call it. + * pt.c (do_auto_deduction): Don't check decltype(auto) here. + +2021-12-15 Martin Liska + + PR c++/103713 + * tree.c (maybe_warn_parm_abi): Fix warning word splitting. + +2021-12-15 Jakub Jelinek + + PR c++/103704 + * semantics.c (finish_omp_target_clauses_r): For OMP_CLAUSEs + just walk subtrees. + 2021-12-14 Patrick Palka PR c++/103408 diff --git a/gcc/d/ChangeLog b/gcc/d/ChangeLog index 91b3d7c..8bc711f 100644 --- a/gcc/d/ChangeLog +++ b/gcc/d/ChangeLog @@ -1,3 +1,9 @@ +2021-12-15 Iain Buclaw + + * d-lang.cc (d_init_options): Set default -fextern-std= to C++17. + * dmd/MERGE: Merge upstream dmd 93108bb9e. + * gdc.texi (Runtime Options): Document the default for -fextern-std=. + 2021-12-10 Iain Buclaw PR d/103529 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3dffea8..a38eac6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,88 @@ +2021-12-15 Marek Polacek + + PR c++/102229 + * g++.dg/cpp1y/decltype-auto5.C: New test. + +2021-12-15 Thomas Schwinge + + * lib/fortran-torture.exp (fortran-torture-compile) + (fortran-torture-execute): Be more informative for ICEs. + * lib/gcc-defs.exp (${tool}_check_compile): Likewise. + * lib/gcc-dg.exp (gcc-dg-test-1): Likewise. + * lib/go-torture.exp (go-torture-compile, go-torture-execute): + Likewise. + +2021-12-15 Martin Sebor + + PR tree-optimization/78969 + * gcc.dg/tree-ssa/builtin-snprintf-warn-6.c: New test. + +2021-12-15 Roger Sayle + + * gcc.target/nvptx/float16-2.c: New test case. + * gcc.target/nvptx/tanh-1.c: New test case. + +2021-12-15 Richard Sandiford + Tamar Christina + + PR target/103094 + * gcc.target/aarch64/pr103094.c: New test. + +2021-12-15 Tamar Christina + + PR rtl-optimization/103350 + * gcc.target/aarch64/pr103350-1.c: New test. + * gcc.target/aarch64/pr103350-2.c: New test. + +2021-12-15 Jakub Jelinek + + PR c++/103408 + * g++.dg/cpp23/auto-fncast11.C: Fix expected diagnostic wording. + +2021-12-15 Jakub Jelinek + + PR c++/103704 + * g++.dg/gomp/pr103704.C: New test. + +2021-12-15 Haochen Jiang + + PR target/101796 + * gcc.target/i386/pr101796-1.c: New test. + +2021-12-15 Michael Meissner + + * gcc.target/powerpc/vec-splat-constant-df.c: New test. + * gcc.target/powerpc/vec-splat-constant-sf.c: New test. + +2021-12-15 Michael Meissner + + * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn + regex for power10. + * gcc.target/powerpc/vec-splat-constant-v2df.c: New test. + * gcc.target/powerpc/vec-splat-constant-v2di.c: New test. + +2021-12-15 Michael Meissner + + * gcc.target/powerpc/vec-splat-constant-v16qi.c: New test. + * gcc.target/powerpc/vec-splat-constant-v4sf.c: New test. + * gcc.target/powerpc/vec-splat-constant-v4si.c: New test. + * gcc.target/powerpc/vec-splat-constant-v8hi.c: New test. + * gcc.target/powerpc/vec-splati-runnable.c: Update insn count. + +2021-12-15 Michael Meissner + + * gcc.target/powerpc/float128-constant.c: New test. + +2021-12-15 Alexandre Oliva + + PR target/100518 + * gcc.target/aarch64/pr100518.c: New. + +2021-12-15 Alexandre Oliva + + PR middle-end/100843 + * gcc.dg/pr100843.c: New. + 2021-12-14 liuhongt * gcc.c-torture/compile/pr103682.c: New test. -- cgit v1.1 From 2c1ac0bf3d44e4ca6e32533d8b498c7d1dbd2425 Mon Sep 17 00:00:00 2001 From: Tobias Burnus Date: Thu, 16 Dec 2021 11:19:37 +0100 Subject: For -foffload= suggest also 'disable' and 'default' [PR103644] gcc/ChangeLog: PR driver/103644 * gcc.c (check_offload_target_name): Add 'default' and 'disable' to the candidate list. --- gcc/gcc.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) (limited to 'gcc') diff --git a/gcc/gcc.c b/gcc/gcc.c index 694c257..b75b50b 100644 --- a/gcc/gcc.c +++ b/gcc/gcc.c @@ -4017,26 +4017,25 @@ check_offload_target_name (const char *target, ptrdiff_t len) memcpy (cand, OFFLOAD_TARGETS, olen); for (c = strtok (cand, ","); c; c = strtok (NULL, ",")) candidates.safe_push (c); + candidates.safe_push ("default"); + candidates.safe_push ("disable"); char *target2 = XALLOCAVEC (char, len + 1); memcpy (target2, target, len); target2[len] = '\0'; - error ("GCC is not configured to support %qs as offload target", target2); + error ("GCC is not configured to support %qs as %<-foffload=%> argument", + target2); - if (candidates.is_empty ()) - inform (UNKNOWN_LOCATION, "no offloading targets configured"); + char *s; + const char *hint = candidates_list_and_hint (target2, s, candidates); + if (hint) + inform (UNKNOWN_LOCATION, + "valid %<-foffload=%> arguments are: %s; " + "did you mean %qs?", s, hint); else - { - char *s; - const char *hint = candidates_list_and_hint (target2, s, candidates); - if (hint) - inform (UNKNOWN_LOCATION, - "valid offload targets are: %s; did you mean %qs?", s, hint); - else - inform (UNKNOWN_LOCATION, "valid offload targets are: %s", s); - XDELETEVEC (s); - } + inform (UNKNOWN_LOCATION, "valid %<-foffload=%> arguments are: %s", s); + XDELETEVEC (s); return false; } return true; -- cgit v1.1 From 0a68862e782847752be0ea2b2a987278cdbefc9e Mon Sep 17 00:00:00 2001 From: Przemyslaw Wirkus Date: Thu, 16 Dec 2021 10:49:00 +0000 Subject: aarch64: fix: ls64 tests fail on aarch64_be [PR103729] This patch is sorting issue with LS64 intrinsics tests failing with AArch64_be targets. gcc/ChangeLog: PR target/103729 * config/aarch64/aarch64-simd.md (aarch64_movv8di): Allow big endian targets to move V8DI. --- gcc/config/aarch64/aarch64-simd.md | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'gcc') diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 9ebf795..f95a7e1 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -7265,9 +7265,8 @@ (define_insn "*aarch64_movv8di" [(set (match_operand:V8DI 0 "nonimmediate_operand" "=r,m,r") (match_operand:V8DI 1 "general_operand" " r,r,m"))] - "!BYTES_BIG_ENDIAN - && (register_operand (operands[0], V8DImode) - || register_operand (operands[1], V8DImode))" + "(register_operand (operands[0], V8DImode) + || register_operand (operands[1], V8DImode))" "#" [(set_attr "type" "multiple,multiple,multiple") (set_attr "length" "32,16,16")] -- cgit v1.1