From 45d34276c2f3a2ee7f8bccfdef1dffe31018e6d9 Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Fri, 25 Mar 2016 19:40:03 +1030 Subject: [RS6000] PR70052, ICE compiling _Decimal128 test case gcc/ PR target/70052 * config/rs6000/constraints.md (j): Simplify. * config/rs6000/predicates.md (easy_fp_constant): Exclude decimal float 0.D. * config/rs6000/rs6000.md (zero_fp): New mode_attr. (mov_hardfloat, mov_hardfloat32, mov_hardfloat64, mov_64bit_dm, mov_32bit): Use zero_fp in place of j in all constraint alternatives. (movtd_64bit_nodm): Delete "j" constraint alternative. gcc/testsuite/ * gcc.dg/dfp/pr70052.c: New test. From-SVN: r234479 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config/rs6000/constraints.md | 2 +- gcc/config/rs6000/predicates.md | 7 ++++--- gcc/config/rs6000/rs6000.md | 26 ++++++++++++++++++-------- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.dg/dfp/pr70052.c | 24 ++++++++++++++++++++++++ 6 files changed, 63 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/dfp/pr70052.c (limited to 'gcc') diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e66ec5b..6c9e945 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2016-03-25 Alan Modra + + PR target/70052 + * config/rs6000/constraints.md (j): Simplify. + * config/rs6000/predicates.md (easy_fp_constant): Exclude + decimal float 0.D. + * config/rs6000/rs6000.md (zero_fp): New mode_attr. + (mov_hardfloat, mov_hardfloat32, mov_hardfloat64, + mov_64bit_dm, mov_32bit): Use zero_fp in place of j + in all constraint alternatives. + (movtd_64bit_nodm): Delete "j" constraint alternative. + 2016-03-24 Aldy Hernandez * tree-ssa-propagate.c: Enhance docs for diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 9eca757..ea15764 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -272,4 +272,4 @@ usually better to use @samp{m} or @samp{es} in @code{asm} statements)" (define_constraint "j" "Zero vector constant" - (match_test "op == const0_rtx || op == CONST0_RTX (GET_MODE (op))")) + (match_test "op == const0_rtx || op == CONST0_RTX (mode)")) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 072291e..71fac76 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -527,13 +527,14 @@ && mode != DImode) return 1; + /* 0.0D is not all zero bits. */ + if (DECIMAL_FLOAT_MODE_P (mode)) + return 0; + /* The constant 0.0 is easy under VSX. */ if (TARGET_VSX && SCALAR_FLOAT_MODE_P (mode) && op == CONST0_RTX (mode)) return 1; - if (DECIMAL_FLOAT_MODE_P (mode)) - return 0; - /* If we are using V.4 style PIC, consider all constants to be hard. */ if (flag_pic && DEFAULT_ABI == ABI_V4) return 0; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d4678af..ef1dea8 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -428,6 +428,16 @@ (SD "REAL_VALUE_TO_TARGET_DECIMAL32") (DD "REAL_VALUE_TO_TARGET_DECIMAL64")]) +; Whether 0.0 has an all-zero bit pattern +(define_mode_attr zero_fp [(SF "j") + (DF "j") + (TF "j") + (IF "j") + (KF "j") + (SD "wn") + (DD "wn") + (TD "wn")]) + ; Definitions for load to 32-bit fpr register (define_mode_attr f32_lr [(SF "f") (SD "wz")]) (define_mode_attr f32_lr2 [(SF "wb") (SD "wn")]) @@ -6472,7 +6482,7 @@ (define_insn "mov_hardfloat" [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,,,!r,,,,,,Z,?,?r,*c*l,!r,*h") - (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,,j,j,,,,,Z,,r,,r,h,0"))] + (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,,,,,,,,Z,,r,,r,h,0"))] "(gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode)) && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)" @@ -6612,7 +6622,7 @@ (define_insn "*mov_hardfloat32" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,Z,,o,,,!r,Y,r,!r") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,,o,,,j,j,r,Y,r"))] + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,,o,,,,,r,Y,r"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -6650,7 +6660,7 @@ ; List Y->r and r->Y before r->r for reload. (define_insn "*mov_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,o,,Z,,,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,o,,Z,,,j,j,r,Y,r,r,h,0,wg,r,,r"))] + (match_operand:FMOVE64 1 "input_operand" "d,m,d,o,,Z,,,,,r,Y,r,r,h,0,wg,r,,r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -6713,7 +6723,7 @@ (define_insn_and_split "*mov_64bit_dm" [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r,r,wh") - (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,j,r,jY,r,wh,r"))] + (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,,r,Y,r,wh,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && FLOAT128_2REG_P (mode) && (mode != TDmode || WORDS_BIG_ENDIAN) @@ -6726,8 +6736,8 @@ [(set_attr "length" "8,8,8,8,12,12,8,8,8")]) (define_insn_and_split "*movtd_64bit_nodm" - [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r") - (match_operand:TD 1 "input_operand" "d,m,d,j,r,jY,r"))] + [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") + (match_operand:TD 1 "input_operand" "d,m,d,r,Y,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN && (gpc_reg_operand (operands[0], TDmode) || gpc_reg_operand (operands[1], TDmode))" @@ -6735,11 +6745,11 @@ "&& reload_completed" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,8,12,12,8")]) + [(set_attr "length" "8,8,8,12,12,8")]) (define_insn_and_split "*mov_32bit" [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r") - (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,j,r,jY,r"))] + (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,,r,Y,r"))] "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64 && (FLOAT128_2REG_P (mode) || int_reg_operand_not_pseudo (operands[0], mode) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8891090..351bdcf 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2016-03-25 Alan Modra + + * gcc.dg/dfp/pr70052.c: New test. + 2016-03-24 Richard Henderson PR middle-end/69845 diff --git a/gcc/testsuite/gcc.dg/dfp/pr70052.c b/gcc/testsuite/gcc.dg/dfp/pr70052.c new file mode 100644 index 0000000..53eb075 --- /dev/null +++ b/gcc/testsuite/gcc.dg/dfp/pr70052.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +typedef struct +{ + _Decimal128 td0; + _Decimal128 td1; +} TDx2_t; + + +TDx2_t +D256_add_finite (void) +{ + _Decimal128 z, zz; + TDx2_t result = {0.DL, 0.DL}; + + if (zz == 0.DL) + { + result.td0 = z; + return result; + } + + return result; +} -- cgit v1.1